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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-09-27 09:36:57 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2021-10-20 19:40:54 +0100 |
| commit | 00fa3461c86dd289b441d4d5a6bb236064bd207b (patch) | |
| tree | b234afb66834b8695032e3f5ef0ad2c8c2408fc2 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 36179af21cc812ccac37678b1c8114856876fb3f (diff) | |
irqchip/mchp-eic: Add support for the Microchip EIC
Add support for Microchip External Interrupt Controller. The controller
supports 2 external interrupt lines. For every external input there is
a connection to GIC. The interrupt controllers contains only 4
registers:
- EIC_GFCS (read only): which indicates that glitch filter configuration
is ready (not addressed in this implementation)
- EIC_SCFG0R, EIC_SCFG1R (read, write): allows per interrupt specific
settings: enable, polarity/edge settings, glitch filter settings
- EIC_WPMR, EIC_WPSR: enables write protection mode specific settings
(which are architecture specific) for the controller and are not
addressed in this implementation
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210927063657.2157676-3-claudiu.beznea@microchip.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions