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| author | Arnd Bergmann <arnd@arndb.de> | 2022-11-21 10:49:40 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-11-21 10:49:41 +0100 |
| commit | 267511c9778b76aa2a85c9d707a04dd1eedfd608 (patch) | |
| tree | 7ce69ad0217dba890722dc579c7cc4b9d6fef16c /tools/perf/scripts/python/syscall-counts.py | |
| parent | 1d4456221fe394eab50b4ce7902b5c76cf650c00 (diff) | |
| parent | 1776fca7fadbac2260a22e2ecb708e8a1ba9310d (diff) | |
Merge tag 'renesas-riscv-defconfig-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig
Renesas RISC-V defconfig updates for v6.2
- Enable support for the Renesas RZ/Five SoC and the RZ/Five SMARC EVK
board in the risc-v defconfig.
* tag 'renesas-riscv-defconfig-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
riscv: configs: defconfig: Enable Renesas RZ/Five SoC
Link: https://lore.kernel.org/r/cover.1668788928.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions