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authorLaurentiu Mihalcea <laurentiu.mihalcea@nxp.com>2024-10-21 11:52:16 -0400
committerShawn Guo <shawnguo@kernel.org>2024-11-01 17:25:02 +0800
commit8a85a9aade360f76c888be34c94fe8374815d39f (patch)
treefddfdbcb809076af9820fc481b690d47e7f1a5ff /tools/perf/scripts/python/syscall-counts.py
parentc199740245c13ec5a72f79d504a7d9b588692e86 (diff)
dt-bindings: dsp: fsl,dsp: fix power domain count
Per the current binding, QM/QXP DSPs are supposed to have 4 power domains, while the rest just 1. For QM/QXP, the 4 power domains are: DSP, DSP_RAM, MU13A, MU13B. First off, drop MU13A from the count as its already attached to lsio_mu13. This decreases the count to 3. Secondly, drop DSP and DSP_RAM from the count for QXP. These are already attached to the DSP's LPCGs. Thirdly, a new power domain is required for DSP-SCU communication (MU2A). With this in mind, the number of required power domains for QXP is 2 (MU2A, MU13B), while for QM it's 4 (MU13B, DSP, DSP_RAM, MU2A). Update the fsl,dsp binding to reflect all of this information. Since the arm,mhuv2 binding has an example node using the fsl,imx8qxp-dsp compatible, remove two of the extra PDs to align with the required power domain count. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
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