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| author | Jagan Teki <jagan@amarulasolutions.com> | 2022-12-12 20:27:45 +0530 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2023-01-20 16:04:35 +0100 |
| commit | 2e337a8d14bd4b04913d52ccf076be29d846acd7 (patch) | |
| tree | 2e047fd10d1b1147096a15ecfa63578dc0eb6e91 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 996e1defca34485dd2bd70b173f069aab5f21a65 (diff) | |
drm: exynos: dsi: Properly name HSA/HBP/HFP/HSE bits
HSA/HBP/HFP/HSE mode bits in Processor Reference Manuals specify
a naming conversion as 'disable mode bit' due to its bit definition,
0 = Enable and 1 = Disable.
For HSE bit, the i.MX 8M Mini/Nano/Plus Applications Processor
Reference Manual named this bit as 'HseDisableMode' but the bit
definition is quite opposite like
0 = Disables transfer
1 = Enables transfer
which clearly states that HSE is not a disable bit.
HSE is named as per the manual even though it is not a disable
bit however the driver logic for handling HSE is based on the
MIPI_DSI_MODE_VIDEO_HSE flag itself.
Cc: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20221212145745.15387-2-jagan@amarulasolutions.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
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