diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2024-12-02 19:20:02 +0000 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-02-04 20:28:06 +0000 |
| commit | 9b181f4a95389163b3a6ec1dccc5c25038e16958 (patch) | |
| tree | 0ad10adbabed2f32bc5b5756cf14463c39c1e332 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 2014c95afecee3e76ca4a56956a936e23283f05b (diff) | |
riscv: dts: microchip: update pcie reg properties to new format
The existing PolarFire SoC devicetrees all use root port instance 1,
update the reg properties in PCIe nodes to use the new format that
specifies the instance in use. Failing to do so would still work but
produces warnings:
mpfs-icicle-kit.dtb: pcie@3000000000: reg: [[48, 0, 0, 134217728], [0, 1124073472, 0, 65536]] is too short
mpfs-icicle-kit.dtb: pcie@3000000000: reg-names: ['cfg', 'apb'] is too short
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor@kernel.org>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: valentina.fernandezalanis@microchip.com
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions