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| author | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2024-11-21 13:27:26 +0200 |
|---|---|---|
| committer | Vinod Govindapillai <vinod.govindapillai@intel.com> | 2024-12-12 09:28:47 +0200 |
| commit | a831920c370c5b93901350154c6e4324b797b57b (patch) | |
| tree | 4cc73dcb06214689b5daca105d77c6265e13fb14 /tools/perf/scripts/python/task-analyzer.py | |
| parent | aac49b862a855e170620f023fbca370fac763e33 (diff) | |
drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip
Xe3 is capable of switching automatically to min ddb allocation
(not using any extra blocks) or interim SAGV-adjusted allocation
in case if async flip is used. Introduce the minimum and interim
ddb allocation configuration for that purpose. Also i915 is
replaced with intel_display within the patch's context
v2: update min/interim ddb declarations and handling (Ville)
update to register definitions styling
consolidation of minimal wm0 check with min DDB check
Bspec: 69880, 72053
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-4-vinod.govindapillai@intel.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions