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author | Zhang Rui <rui.zhang@intel.com> | 2023-08-26 14:57:12 +0800 |
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committer | Zhang Rui <rui.zhang@intel.com> | 2023-09-27 22:14:19 +0800 |
commit | a98f886035d5f7e0ec66036dd6bf98b40e75b692 (patch) | |
tree | 1b91f7e7410926142319cee30196612ca56e96da /tools/perf/scripts/python/task-analyzer.py | |
parent | b9cd66833d3a651cea10666674e9abcf2182e8ad (diff) |
tools/power/turbostat: Simplify the logic for RAPL enumeration
The support for each RAPL domains, as well as the support for the perf
status of each RAPL domains, can be detected by checking the
availabilities of the corresponding RAPL MSRs.
Change the code accordingly and remove the hardcoded logic for each
model.
Note that this also fixes the INTEL_FAM6_ATOM_TREMONT model, which has
RAPL_PKG_PERF_STATUS and MSR_DRAM_PERF_STATUS but doesn't have BIC_PKG__
and BIC_RAM__ set.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions