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| author | Sinthu Raja <sinthu.raja@ti.com> | 2023-09-21 15:30:37 +0530 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2023-10-05 20:44:41 +0530 |
| commit | b024d1a853b7bc8e2e01aa9a219d81a9df1a2ceb (patch) | |
| tree | e21039481290a9903fa098bf9961fb5452dfcb2e /tools/perf/scripts/python/task-analyzer.py | |
| parent | c2e7258dbd451fff84fac2375aaec2f56f57f0b3 (diff) | |
arm64: dts: ti: Add USB Type C swap defines for J721S2 SoC
Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C
lane swap. Update the macro definition for it.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230921100039.19897-2-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions