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| author | Laura Nao <laura.nao@collabora.com> | 2025-09-15 17:19:23 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-09-21 09:33:43 -0700 |
| commit | d3c4dde9770dbe2eb3a57c3d952c630e81fcd1c0 (patch) | |
| tree | 67f66022d0eae90504b428a8440bb4fec49cf53f /tools/perf/scripts/python/task-analyzer.py | |
| parent | 2c327a17718d8d6e7e79c2ab73ea6073aae9f22d (diff) | |
clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC
MT8196 uses set/clr/upd registers for mux gate enable/disable control,
along with a FENC bit to check the status. Add new set of mux gate
clock operations with support for set/clr/upd and FENC status logic.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions