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authorFabrizio Castro <fabrizio.castro.jz@renesas.com>2023-07-18 20:24:50 +0100
committerMark Brown <broonie@kernel.org>2023-07-19 14:33:31 +0100
commitd5737d12779a171e76ad07635d1ed06a22009da7 (patch)
tree21f4af314cde5b74ad453b6ac1f8698cd24e9c6e /tools/perf/scripts/python/task-analyzer.py
parent35057870b1cb4d1fcc16b72590befed091d3bed0 (diff)
spi: rzv2m-csi: Squash timing settings into one statement
Register CLKSEL hosts the configuration for both clock polarity and data phase, and both values can be set in one write operation. Squash the clock polarity and data phase register writes into one statement, for efficiency. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230718192453.543549-2-fabrizio.castro.jz@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
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