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| author | Cyril Bur <cyrilbur@tenstorrent.com> | 2025-06-02 12:15:43 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2025-06-05 14:03:17 -0700 |
| commit | 265d6aba165c500389c80d394ac247460c443ef5 (patch) | |
| tree | 4c44f088d103b32e738be63f649b609e6bbdc3c8 /tools/perf/scripts/python | |
| parent | 2670a39b1ea68fb0b9175e26e299f3fe974e0332 (diff) | |
riscv: uaccess: Only restore the CSR_STATUS SUM bit
During switch to csrs will OR the value of the register into the
corresponding csr. In this case we're only interested in restoring the
SUM bit not the entire register.
Signed-off-by: Cyril Bur <cyrilbur@tenstorrent.com>
Link: https://lore.kernel.org/r/20250522160954.429333-1-cyrilbur@tenstorrent.com
Co-developed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Fixes: 788aa64c01f1 ("riscv: save the SR_SUM status over switches")
Link: https://lore.kernel.org/r/20250602121543.1544278-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions