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authorShiju Jose <shiju.jose@huawei.com>2024-10-14 15:30:03 +0100
committerIra Weiny <ira.weiny@intel.com>2024-10-25 11:23:26 -0500
commit53ab8678e7180834be29cf56cd52825fc3427c02 (patch)
tree72f7ee41204d63362520abf5fd9c3091136b8dbc /tools/perf/scripts/python
parentcce3cd647721dc30273f0546852b5c26820eb715 (diff)
cxl/events: Fix Trace DRAM Event Record
CXL spec rev 3.0 section 8.2.9.2.1.2 defines the DRAM Event Record. Fix decode memory event type field of DRAM Event Record. For e.g. if value is 0x1 it will be reported as an Invalid Address (General Media Event Record - Memory Event Type) instead of Scrub Media ECC Error (DRAM Event Record - Memory Event Type) and so on. Fixes: 2d6c1e6d60ba ("cxl/mem: Trace DRAM Event Record") Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Link: https://patch.msgid.link/20241014143003.1170-1-shiju.jose@huawei.com Signed-off-by: Ira Weiny <ira.weiny@intel.com>
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