diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2025-08-25 16:26:36 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2025-09-04 18:27:12 +0200 |
| commit | 9bada5ff4bf7a057d40ae49eab5d9081535b5f3c (patch) | |
| tree | 2dbbc28b26f6bb0ad67a31febe2322cc14d7d9a4 /tools/perf/scripts/python | |
| parent | 955e18baeb933096f417ac01d6781380d7c8a374 (diff) | |
clk: amlogic: align s4 and c3 pwm clock descriptions
s4 and c3 follow exactly the same structure when it comes to PWM clocks but
differ in the way these clocks are described, for no obvious reason.
Align the description of the pwm clocks of these SoCs with the composite
clock helpers.
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-11-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions