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| author | Marijn Suijten <marijn.suijten@somainline.org> | 2022-12-22 00:19:36 +0100 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-12 21:45:17 +0200 |
| commit | cda3774c242e156cdcc279bd36b404af89f744c6 (patch) | |
| tree | 0ce852595aa5e820c0b4bc7aa8cb5a266efa6560 /tools/perf/scripts/python | |
| parent | a2f33995c19db64398ab6440e8c38fe9d4df6e3c (diff) | |
drm/msm/dpu: Wire up DSC mask for active CTL configuration
Active CTLs have to configure what DSC block(s) have to be enabled, and
what DSC block(s) have to be flushed; this value was initialized to zero
resulting in the necessary register writes to never happen (or would
write zero otherwise). This seems to have gotten lost in the DSC v4->v5
series while refactoring how the combination with merge_3d was handled.
Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/515693/
Link: https://lore.kernel.org/r/20221221231943.1961117-2-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions