Pull clk fixes from Stephen Boyd: "Fixes for some SoC clk drivers: - Define the gate clk for the OTG PHY on Rockchip RK3576 so the nvmem driver actually works - Initialize clk_hw_onecell_data::num before accessing the 'hws' array to keep UBSAN happy - Fix a perf degradation on the Allwinner D1 MMC clk that was making things half bad - Fix the Allwinner SNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT macro to have proper order of arguments" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: sunxi-ng: d1: Add missing divider for MMC mod clocks clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] in probe() clk: sunxi-ng: fix order of arguments in clock macro clk: rockchip: rk3576: define clk_otp_phy_g