diff options
| author | Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> | 2023-06-30 19:52:33 +0530 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@linaro.org> | 2023-07-13 05:32:09 +0300 |
| commit | 18d7d01a0a0eb32b78149c8259bf49504d5fa4e0 (patch) | |
| tree | ce168afc57a7613f5f23ce9e5fb420832901996e /tools/perf | |
| parent | cfc2928cb213d5c20b6313abb2d603c0c60d7637 (diff) | |
mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected
Setting the status register write disable (SRWD) bit in the status
register (SR) with WP# signal of the flash left floating or wrongly tied to
GND (that includes internal pull-downs), will configure the SR permanently
as read-only. If WP# signal is left floating or wrongly tied to GND, avoid
setting SRWD bit while writing the SR during flash protection.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20230630142233.63585-3-amit.kumar-mahapatra@amd.com
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Diffstat (limited to 'tools/perf')
0 files changed, 0 insertions, 0 deletions