diff options
32 files changed, 1541 insertions, 853 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index faea33e4f731..deb2cf971871 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -171,6 +171,7 @@ properties: - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite - hardkernel,odroid-xu4 # Hardkernel Odroid XU4 - hardkernel,odroid-hc1 # Hardkernel Odroid HC1 + - samsung,k3g # Samsung Galaxy S5 (SM-G900H) - const: samsung,exynos5800 - const: samsung,exynos5 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d08a3c450ce7..e3caad23568a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -246,6 +246,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5422-odroidxu3.dtb \ exynos5422-odroidxu3-lite.dtb \ exynos5422-odroidxu4.dtb \ + exynos5422-samsung-k3g.dtb \ exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-dlink-dir-685.dtb \ diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi index ecf416690a15..bc9a78f6d4b7 100644 --- a/arch/arm/boot/dts/exynos-syscon-restart.dtsi +++ b/arch/arm/boot/dts/exynos-syscon-restart.dtsi @@ -7,7 +7,7 @@ poweroff: syscon-poweroff { compatible = "syscon-poweroff"; regmap = <&pmu_system_controller>; - offset = <0x330C>; /* PS_HOLD_CONTROL */ + offset = <0x330c>; /* PS_HOLD_CONTROL */ mask = <0x5200>; /* reset value */ }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 02a9dc479d34..80d90fe7fad1 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -31,7 +31,7 @@ firmware@205f000 { compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; + reg = <0x0205f000 0x1000>; }; gpio-keys { @@ -438,7 +438,6 @@ broken-cd; non-removable; cap-mmc-highspeed; - desc-num = <4>; mmc-hs200-1_8v; card-detect-delay = <200>; vmmc-supply = <&vemmc_reg>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 6d2c7bb19184..1f9cba0607e1 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -36,7 +36,7 @@ firmware@205f000 { compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; + reg = <0x0205f000 0x1000>; }; gpio-keys { @@ -250,7 +250,7 @@ i80-if-timings { cs-setup = <0>; wr-setup = <0>; - wr-act = <1>; + wr-active = <1>; wr-hold = <0>; }; }; @@ -619,7 +619,6 @@ broken-cd; non-removable; cap-mmc-highspeed; - desc-num = <4>; mmc-hs200-1_8v; card-detect-delay = <200>; vmmc-supply = <&ldo12_reg>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index a2d6ee7fff08..28bb2ce8ccf7 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -46,6 +46,157 @@ serial2 = &serial_2; }; + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_dmc CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <800000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_isp: bus-isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + + bus_isp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + }; + + bus_lcd0: bus-lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus-mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + + bus_mcuisp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peril: bus-peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + + bus_peril_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -129,6 +280,31 @@ clock-output-names = "xtcxo"; }; + bus_leftbus_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -188,35 +364,35 @@ pd_cam: power-domain@10023c00 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; + reg = <0x10023c00 0x20>; #power-domain-cells = <0>; label = "CAM"; }; pd_mfc: power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; + reg = <0x10023c40 0x20>; #power-domain-cells = <0>; label = "MFC"; }; pd_g3d: power-domain@10023c60 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; + reg = <0x10023c60 0x20>; #power-domain-cells = <0>; label = "G3D"; }; pd_lcd0: power-domain@10023c80 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; + reg = <0x10023c80 0x20>; #power-domain-cells = <0>; label = "LCD0"; }; pd_isp: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; + reg = <0x10023ca0 0x20>; #power-domain-cells = <0>; label = "ISP"; }; @@ -233,7 +409,7 @@ cmu_dmc: clock-controller@105c0000 { compatible = "samsung,exynos3250-cmu-dmc"; - reg = <0x105C0000 0x2000>; + reg = <0x105c0000 0x2000>; #clock-cells = <1>; }; @@ -248,7 +424,7 @@ tmu: tmu@100c0000 { compatible = "samsung,exynos3250-tmu"; - reg = <0x100C0000 0x100>; + reg = <0x100c0000 0x100>; interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_TMU_APBIF>; clock-names = "tmu_apbif"; @@ -342,7 +518,7 @@ dsi_0: dsi@11c80000 { compatible = "samsung,exynos3250-mipi-dsi"; - reg = <0x11C80000 0x10000>; + reg = <0x11c80000 0x10000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; samsung,phy-type = <0>; power-domains = <&pd_lcd0>; @@ -365,7 +541,7 @@ #iommu-cells = <0>; }; - hsotg: hsotg@12480000 { + hsotg: usb@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; @@ -412,9 +588,9 @@ status = "disabled"; }; - exynos_usbphy: exynos-usbphy@125b0000 { + exynos_usbphy: usb-phy@125b0000 { compatible = "samsung,exynos3250-usb2-phy"; - reg = <0x125B0000 0x100>; + reg = <0x125b0000 0x100>; samsung,pmureg-phandle = <&pmu_system_controller>; clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; clock-names = "phy", "ref"; @@ -442,7 +618,7 @@ adc: adc@126c0000 { compatible = "samsung,exynos3250-adc"; - reg = <0x126C0000 0x100>; + reg = <0x126c0000 0x100>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; clock-names = "adc", "sclk"; clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; @@ -593,7 +769,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; + reg = <0x138a0000 0x100>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C4>; clock-names = "i2c"; @@ -606,7 +782,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; + reg = <0x138b0000 0x100>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C5>; clock-names = "i2c"; @@ -619,7 +795,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; + reg = <0x138c0000 0x100>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C6>; clock-names = "i2c"; @@ -632,7 +808,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; + reg = <0x138d0000 0x100>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_I2C7>; clock-names = "i2c"; @@ -688,7 +864,7 @@ pwm: pwm@139d0000 { compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; + reg = <0x139d0000 0x1000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, @@ -771,182 +947,6 @@ clock-names = "ppmu"; status = "disabled"; }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_dmc CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp-table1 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <800000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <800000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <800000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <875000>; - }; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus-lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_160>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mcuisp: bus-mcuisp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; - clock-names = "bus"; - operating-points-v2 = <&bus_mcuisp_opp_table>; - status = "disabled"; - }; - - bus_isp: bus-isp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_isp_opp_table>; - status = "disabled"; - }; - - bus_peril: bus-peril { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peril_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <900000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - opp-microvolt = <900000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - bus_mcuisp_opp_table: opp-table3 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - }; - - bus_isp_opp_table: opp-table4 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_peril_opp_table: opp-table5 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; }; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 5c4ecda27a47..44dcb1377475 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -65,7 +65,7 @@ clock_audss: clock-controller@3810000 { compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, <&clock CLK_SCLK_AUDIO0>, @@ -113,28 +113,28 @@ pd_mfc: power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; + reg = <0x10023c40 0x20>; #power-domain-cells = <0>; label = "MFC"; }; pd_g3d: power-domain@10023c60 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; + reg = <0x10023c60 0x20>; #power-domain-cells = <0>; label = "G3D"; }; pd_lcd0: power-domain@10023c80 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; + reg = <0x10023c80 0x20>; #power-domain-cells = <0>; label = "LCD0"; }; pd_tv: power-domain@10023c20 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C20 0x20>; + reg = <0x10023c20 0x20>; #power-domain-cells = <0>; power-domains = <&pd_lcd0>; label = "TV"; @@ -142,21 +142,21 @@ pd_cam: power-domain@10023c00 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; + reg = <0x10023c00 0x20>; #power-domain-cells = <0>; label = "CAM"; }; pd_gps: power-domain@10023ce0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CE0 0x20>; + reg = <0x10023ce0 0x20>; #power-domain-cells = <0>; label = "GPS"; }; pd_gps_alive: power-domain@10023d00 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023D00 0x20>; + reg = <0x10023d00 0x20>; #power-domain-cells = <0>; label = "GPS alive"; }; @@ -190,7 +190,7 @@ dsi_0: dsi@11c80000 { compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11C80000 0x10000>; + reg = <0x11c80000 0x10000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; @@ -309,7 +309,7 @@ keypad: keypad@100a0000 { compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; + reg = <0x100a0000 0x100>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_KEYIF>; clock-names = "keypad"; @@ -352,9 +352,9 @@ status = "disabled"; }; - exynos_usbphy: exynos-usbphy@125b0000 { + exynos_usbphy: usb-phy@125b0000 { compatible = "samsung,exynos4210-usb2-phy"; - reg = <0x125B0000 0x100>; + reg = <0x125b0000 0x100>; samsung,pmureg-phandle = <&pmu_system_controller>; clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; clock-names = "phy", "ref"; @@ -362,7 +362,7 @@ status = "disabled"; }; - hsotg: hsotg@12480000 { + hsotg: usb@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; @@ -546,7 +546,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; + reg = <0x138a0000 0x100>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C4>; clock-names = "i2c"; @@ -559,7 +559,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; + reg = <0x138b0000 0x100>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C5>; clock-names = "i2c"; @@ -572,7 +572,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; + reg = <0x138c0000 0x100>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C6>; clock-names = "i2c"; @@ -585,7 +585,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; + reg = <0x138d0000 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C7>; clock-names = "i2c"; @@ -598,14 +598,14 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x138E0000 0x100>; + reg = <0x138e0000 0x100>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_I2C_HDMI>; clock-names = "i2c"; status = "disabled"; - hdmi_i2c_phy: hdmiphy@38 { - compatible = "exynos4210-hdmiphy"; + hdmi_i2c_phy: hdmi-phy@38 { + compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; }; @@ -657,7 +657,7 @@ pwm: pwm@139d0000 { compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; + reg = <0x139d0000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, @@ -712,7 +712,7 @@ tmu: tmu@100c0000 { interrupt-parent = <&combiner>; - reg = <0x100C0000 0x100>; + reg = <0x100c0000 0x100>; interrupts = <2 4>; status = "disabled"; #thermal-sensor-cells = <0>; @@ -739,7 +739,7 @@ hdmi: hdmi@12d00000 { compatible = "samsung,exynos4210-hdmi"; - reg = <0x12D00000 0x70000>; + reg = <0x12d00000 0x70000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; @@ -756,7 +756,7 @@ hdmicec: cec@100b0000 { compatible = "samsung,s5p-cec"; - reg = <0x100B0000 0x200>; + reg = <0x100b0000 0x200>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; @@ -770,7 +770,7 @@ mixer: mixer@12c10000 { compatible = "samsung,exynos4210-mixer"; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; + reg = <0x12c10000 0x2100>, <0x12c00000 0x300>; power-domains = <&pd_tv>; iommus = <&sysmmu_tv>; status = "disabled"; @@ -902,7 +902,7 @@ sysmmu_tv: sysmmu@12e20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x12E20000 0x1000>; + reg = <0x12e20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 4>; clock-names = "sysmmu", "master"; @@ -913,7 +913,7 @@ sysmmu_fimc0: sysmmu@11a20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A20000 0x1000>; + reg = <0x11a20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 2>; clock-names = "sysmmu", "master"; @@ -924,7 +924,7 @@ sysmmu_fimc1: sysmmu@11a30000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A30000 0x1000>; + reg = <0x11a30000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 3>; clock-names = "sysmmu", "master"; @@ -935,7 +935,7 @@ sysmmu_fimc2: sysmmu@11a40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A40000 0x1000>; + reg = <0x11a40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 4>; clock-names = "sysmmu", "master"; @@ -946,7 +946,7 @@ sysmmu_fimc3: sysmmu@11a50000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A50000 0x1000>; + reg = <0x11a50000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 5>; clock-names = "sysmmu", "master"; @@ -957,7 +957,7 @@ sysmmu_jpeg: sysmmu@11a60000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A60000 0x1000>; + reg = <0x11a60000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 6>; clock-names = "sysmmu", "master"; @@ -968,7 +968,7 @@ sysmmu_rotator: sysmmu@12a30000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x12A30000 0x1000>; + reg = <0x12a30000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 0>; clock-names = "sysmmu", "master"; @@ -979,7 +979,7 @@ sysmmu_fimd0: sysmmu@11e20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11E20000 0x1000>; + reg = <0x11e20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 2>; clock-names = "sysmmu", "master"; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 2c25cc37934e..5a1ec714c612 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -28,6 +28,151 @@ pinctrl2 = &pinctrl_2; }; + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + opp-suspend; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_lcd0: bus-lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -82,6 +227,22 @@ }; }; + bus_leftbus_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-suspend; + }; + }; + soc: soc { sysram: sram@2020000 { compatible = "mmio-sram"; @@ -103,7 +264,7 @@ pd_lcd1: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; + reg = <0x10023ca0 0x20>; #power-domain-cells = <0>; label = "LCD1"; }; @@ -195,7 +356,7 @@ sysmmu_g2d: sysmmu@12a20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x12A20000 0x1000>; + reg = <0x12a20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 7>; clock-names = "sysmmu", "master"; @@ -214,167 +375,6 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus-lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1025000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1150000>; - opp-suspend; - }; - }; - - bus_acp_opp_table: opp-table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_peri_opp_table: opp-table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp-5000000 { - opp-hz = /bits/ 64 <5000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_fsys_opp_table: opp-table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp-10000000 { - opp-hz = /bits/ 64 <10000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_display_opp_table: opp-table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - }; - - bus_leftbus_opp_table: opp-table6 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-suspend; - }; - }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 202ab0fee3b7..b596e997e451 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -214,7 +214,7 @@ bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; pinctrl-names = "default"; - cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpx0 7 GPIO_ACTIVE_LOW>; cap-sd-highspeed; vmmc-supply = <&ldo23_reg>; vqmmc-supply = <&ldo17_reg>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index a67cb61e3cbb..e42e39dc0e40 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -25,7 +25,7 @@ firmware@203f000 { compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; + reg = <0x0203f000 0x1000>; }; fixed-rate-clocks { diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 8e1c19a8ad06..d5074fa57142 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -33,7 +33,7 @@ firmware@204f000 { compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; + reg = <0x0204f000 0x1000>; }; fixed-rate-clocks { @@ -273,9 +273,16 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x39>; - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index e7669b9e9edb..7c2780d3e37c 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -19,7 +19,7 @@ firmware@204f000 { compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; + reg = <0x0204f000 0x1000>; }; gpio_keys: gpio-keys { diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index a5ad88b897ff..42812da1f882 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -23,7 +23,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x7FF00000>; + reg = <0x40000000 0x7ff00000>; }; vbus_otg_reg: regulator-1 { diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 68d589e081bc..d5316cf2fbb6 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -22,7 +22,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x3FF00000>; + reg = <0x40000000 0x3ff00000>; }; leds { diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts index f4b68c75c962..7be4cbdc4413 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -17,6 +17,6 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x7FF00000>; + reg = <0x40000000 0x7ff00000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index a3905e27b9cd..ea9fd284386d 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -31,7 +31,7 @@ firmware@203f000 { compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; + reg = <0x0203f000 0x1000>; }; mmc_reg: regulator-0 { diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 7a515b87bc7c..3e05a49f29ff 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -32,7 +32,7 @@ firmware@204f000 { compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; + reg = <0x0204f000 0x1000>; }; fixed-rate-clocks { @@ -132,8 +132,6 @@ precharge-current-microamp = <250000>; charge-term-current-microamp = <250000>; constant-charge-voltage-max-microvolt = <4200000>; - - power-supplies = <&power_supply>; }; i2c-gpio-1 { @@ -200,7 +198,7 @@ stmpe_adc { compatible = "st,stmpe-adc"; #io-channel-cells = <1>; - st,norequest-mask = <0x2F>; + st,norequest-mask = <0x2f>; }; }; }; @@ -247,6 +245,7 @@ pinctrl-0 = <&led_bl_reset>; pinctrl-names = "default"; enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>; + power-supply = <&panel_vdd>; pwms = <&pwm 1 78770 0>; brightness-levels = <0 48 128 255>; num-interpolated-steps = <8>; diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi index 58847d4fa846..8ab31c3daa48 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi @@ -12,7 +12,7 @@ #include "exynos-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 04388c575efe..e0b6162d2e2a 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -79,6 +79,7 @@ panel { compatible = "innolux,at070tn92"; + power-supply = <&vddq_lcd>; port { panel_input: endpoint { @@ -86,6 +87,13 @@ }; }; }; + + vddq_lcd: regulator-vddq-lcd { + compatible = "regulator-fixed"; + regulator-name = "vddq-lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &cpu_thermal { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index aa0b61b59970..11f9dd94b6b3 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -31,6 +31,134 @@ mshc0 = &mshc_0; }; + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + }; + + bus_c2c: bus-c2c { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_C2C>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -55,7 +183,7 @@ cpu0: cpu@a00 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA00>; + reg = <0xa00>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -65,7 +193,7 @@ cpu1: cpu@a01 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA01>; + reg = <0xa01>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -75,7 +203,7 @@ cpu2: cpu@a02 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA02>; + reg = <0xa02>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -85,7 +213,7 @@ cpu3: cpu@a03 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA03>; + reg = <0xa03>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -93,7 +221,7 @@ }; }; - cpu0_opp_table: opp-table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -171,6 +299,53 @@ }; }; + bus_dmc_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <900000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <900000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-suspend; + }; + }; + + bus_leftbus_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + opp-suspend; + }; + }; soc: soc { @@ -201,7 +376,7 @@ pinctrl_3: pinctrl@106e0000 { compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106E0000 0x1000>; + reg = <0x106e0000 0x1000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; @@ -225,7 +400,7 @@ pd_isp: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; + reg = <0x10023ca0 0x20>; #power-domain-cells = <0>; label = "ISP"; }; @@ -285,7 +460,7 @@ adc: adc@126c0000 { compatible = "samsung,exynos4212-adc"; - reg = <0x126C0000 0x100>; + reg = <0x126c0000 0x100>; interrupt-parent = <&combiner>; interrupts = <10 3>; clocks = <&clock CLK_TSADC>; @@ -318,7 +493,7 @@ sysmmu_g2d: sysmmu@10a40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A40000 0x1000>; + reg = <0x10a40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 7>; clock-names = "sysmmu", "master"; @@ -350,7 +525,7 @@ sysmmu_fimc_fd: sysmmu@122a0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x122A0000 0x1000>; + reg = <0x122a0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 4>; power-domains = <&pd_isp>; @@ -361,7 +536,7 @@ sysmmu_fimc_mcuctl: sysmmu@122b0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x122B0000 0x1000>; + reg = <0x122b0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 5>; power-domains = <&pd_isp>; @@ -372,7 +547,7 @@ sysmmu_fimc_lite0: sysmmu@123b0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x123B0000 0x1000>; + reg = <0x123b0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 0>; power-domains = <&pd_isp>; @@ -384,7 +559,7 @@ sysmmu_fimc_lite1: sysmmu@123c0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x123C0000 0x1000>; + reg = <0x123c0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 1>; power-domains = <&pd_isp>; @@ -393,182 +568,6 @@ <&isp_clock CLK_ISP_FIMC_LITE1>; #iommu-cells = <0>; }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - samsung,data-clock-ratio = <4>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_c2c: bus-c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp-table1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - opp-suspend; - }; - }; - - bus_acp_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - interconnects = <&bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - interconnects = <&bus_leftbus &bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp-table3 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - opp-suspend; - }; - }; - - bus_display_opp_table: opp-table4 { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_fsys_opp_table: opp-table5 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_peri_opp_table: opp-table6 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; }; }; @@ -615,7 +614,7 @@ fimc_lite_1: fimc-lite@123a0000 { compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123A0000 0x1000>; + reg = <0x123a0000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; @@ -812,7 +811,7 @@ compatible = "samsung,exynos4412-tmu"; interrupt-parent = <&combiner>; interrupts = <2 4>; - reg = <0x100C0000 0x100>; + reg = <0x100c0000 0x100>; clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; status = "disabled"; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index c8da0d4b1b33..48e43b6b3213 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -104,31 +104,31 @@ serial_0: serial@12c00000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; + reg = <0x12c00000 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; }; serial_1: serial@12c10000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; + reg = <0x12c10000 0x100>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; }; serial_2: serial@12c20000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; + reg = <0x12c20000 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; }; serial_3: serial@12c30000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; + reg = <0x12c30000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; }; i2c_0: i2c@12c60000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; + reg = <0x12c60000 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -138,7 +138,7 @@ i2c_1: i2c@12c70000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; + reg = <0x12c70000 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -148,7 +148,7 @@ i2c_2: i2c@12c80000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; + reg = <0x12c80000 0x100>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -158,7 +158,7 @@ i2c_3: i2c@12c90000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; + reg = <0x12c90000 0x100>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -168,7 +168,7 @@ pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; - reg = <0x12DD0000 0x100>; + reg = <0x12dd0000 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, @@ -180,7 +180,7 @@ rtc: rtc@101e0000 { compatible = "samsung,s3c6410-rtc"; - reg = <0x101E0000 0x100>; + reg = <0x101e0000 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -198,7 +198,7 @@ dp: dp-controller@145b0000 { compatible = "samsung,exynos5-dp"; - reg = <0x145B0000 0x1000>; + reg = <0x145b0000 0x1000>; interrupts = <10 3>; interrupt-parent = <&combiner>; status = "disabled"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 4708dcd575a7..a5db4ac213d5 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -81,7 +81,7 @@ }; }; - cpu0_opp_table: opp-table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -216,14 +216,14 @@ pd_disp1: power-domain@100440a0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440A0 0x20>; + reg = <0x100440a0 0x20>; #power-domain-cells = <0>; label = "DISP1"; }; pd_mau: power-domain@100440c0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; + reg = <0x100440c0 0x20>; #power-domain-cells = <0>; label = "MAU"; }; @@ -236,7 +236,7 @@ clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; @@ -247,7 +247,7 @@ timer@101c0000 { compatible = "samsung,exynos5250-mct", "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; + reg = <0x101c0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; interrupts-extended = <&combiner 23 3>, @@ -302,7 +302,7 @@ watchdog@101d0000 { compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; + reg = <0x101d0000 0x100>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; @@ -322,7 +322,7 @@ rotator: rotator@11c00000 { compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; + reg = <0x11c00000 0x64>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; @@ -387,10 +387,10 @@ sata: sata@122f0000 { compatible = "snps,dwc-ahci"; - reg = <0x122F0000 0x1ff>; + reg = <0x122f0000 0x1ff>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; - clock-names = "sata", "sclk_sata"; + clock-names = "sata", "pclk"; phys = <&sata_phy>; phy-names = "sata-phy"; ports-implemented = <0x1>; @@ -410,7 +410,7 @@ /* i2c_0-3 are defined in exynos5.dtsi */ i2c_4: i2c@12ca0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CA0000 0x100>; + reg = <0x12ca0000 0x100>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -423,7 +423,7 @@ i2c_5: i2c@12cb0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CB0000 0x100>; + reg = <0x12cb0000 0x100>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -436,7 +436,7 @@ i2c_6: i2c@12cc0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CC0000 0x100>; + reg = <0x12cc0000 0x100>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -449,7 +449,7 @@ i2c_7: i2c@12cd0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CD0000 0x100>; + reg = <0x12cd0000 0x100>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -462,7 +462,7 @@ i2c_8: i2c@12ce0000 { compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x12CE0000 0x1000>; + reg = <0x12ce0000 0x1000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -470,7 +470,7 @@ clock-names = "i2c"; status = "disabled"; - hdmiphy: hdmiphy@38 { + hdmiphy: hdmi-phy@38 { compatible = "samsung,exynos4212-hdmiphy"; reg = <0x38>; }; @@ -478,7 +478,7 @@ i2c_9: i2c@121d0000 { compatible = "samsung,exynos5-sata-phy-i2c"; - reg = <0x121D0000 0x100>; + reg = <0x121d0000 0x100>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_SATA_PHYI2C>; @@ -608,7 +608,7 @@ i2s1: i2s@12d60000 { compatible = "samsung,s3c6410-i2s"; status = "disabled"; - reg = <0x12D60000 0x100>; + reg = <0x12d60000 0x100>; dmas = <&pdma1 12>, <&pdma1 11>; dma-names = "tx", "rx"; @@ -623,7 +623,7 @@ i2s2: i2s@12d70000 { compatible = "samsung,s3c6410-i2s"; status = "disabled"; - reg = <0x12D70000 0x100>; + reg = <0x12d70000 0x100>; dmas = <&pdma0 12>, <&pdma0 11>; dma-names = "tx", "rx"; @@ -635,17 +635,17 @@ #sound-dai-cells = <1>; }; - usbdrd: usb3 { + usbdrd: usb@12000000 { compatible = "samsung,exynos5250-dwusb3"; clocks = <&clock CLK_USB3>; clock-names = "usbdrd30"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x12000000 0x10000>; - usbdrd_dwc3: usb@12000000 { + usbdrd_dwc3: usb@0 { compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; + reg = <0x0 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; phy-names = "usb2-phy", "usb3-phy"; @@ -695,7 +695,7 @@ pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; + reg = <0x121a0000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; @@ -704,7 +704,7 @@ pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; + reg = <0x121b0000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; @@ -722,7 +722,7 @@ mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; + reg = <0x11c10000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; @@ -787,7 +787,7 @@ hdmicec: cec@101b0000 { compatible = "samsung,s5p-cec"; - reg = <0x101B0000 0x200>; + reg = <0x101b0000 0x200>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; @@ -838,7 +838,7 @@ adc: adc@12d10000 { compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>; + reg = <0x12d10000 0x100>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ADC>; clock-names = "adc"; @@ -849,7 +849,7 @@ sysmmu_g2d: sysmmu@10a60000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; + reg = <0x10a60000 0x1000>; interrupt-parent = <&combiner>; interrupts = <24 5>; clock-names = "sysmmu", "master"; @@ -881,7 +881,7 @@ sysmmu_rotator: sysmmu@11d40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; + reg = <0x11d40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 0>; clock-names = "sysmmu", "master"; @@ -891,7 +891,7 @@ sysmmu_jpeg: sysmmu@11f20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; + reg = <0x11f20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 2>; power-domains = <&pd_gsc>; @@ -922,7 +922,7 @@ sysmmu_fimc_fd: sysmmu@132a0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132A0000 0x1000>; + reg = <0x132a0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 0>; clock-names = "sysmmu"; @@ -952,7 +952,7 @@ sysmmu_fimc_mcuctl: sysmmu@132b0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132B0000 0x1000>; + reg = <0x132b0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 4>; clock-names = "sysmmu"; @@ -962,7 +962,7 @@ sysmmu_fimc_odc: sysmmu@132c0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132C0000 0x1000>; + reg = <0x132c0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <11 0>; clock-names = "sysmmu"; @@ -972,7 +972,7 @@ sysmmu_fimc_dis0: sysmmu@132d0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132D0000 0x1000>; + reg = <0x132d0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <10 4>; clock-names = "sysmmu"; @@ -982,7 +982,7 @@ sysmmu_fimc_dis1: sysmmu@132e0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132E0000 0x1000>; + reg = <0x132e0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <9 4>; clock-names = "sysmmu"; @@ -992,7 +992,7 @@ sysmmu_fimc_3dnr: sysmmu@132f0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132F0000 0x1000>; + reg = <0x132f0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 6>; clock-names = "sysmmu"; @@ -1002,7 +1002,7 @@ sysmmu_fimc_lite0: sysmmu@13c40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13C40000 0x1000>; + reg = <0x13c40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <3 4>; power-domains = <&pd_gsc>; @@ -1013,7 +1013,7 @@ sysmmu_fimc_lite1: sysmmu@13c50000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13C50000 0x1000>; + reg = <0x13c50000 0x1000>; interrupt-parent = <&combiner>; interrupts = <24 1>; power-domains = <&pd_gsc>; @@ -1024,7 +1024,7 @@ sysmmu_gsc0: sysmmu@13e80000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; + reg = <0x13e80000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 0>; power-domains = <&pd_gsc>; @@ -1035,7 +1035,7 @@ sysmmu_gsc1: sysmmu@13e90000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; + reg = <0x13e90000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 2>; power-domains = <&pd_gsc>; @@ -1046,7 +1046,7 @@ sysmmu_gsc2: sysmmu@13ea0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13EA0000 0x1000>; + reg = <0x13ea0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 4>; power-domains = <&pd_gsc>; @@ -1057,7 +1057,7 @@ sysmmu_gsc3: sysmmu@13eb0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13EB0000 0x1000>; + reg = <0x13eb0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 6>; power-domains = <&pd_gsc>; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 3c3b751d4360..387b8494f18f 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -87,7 +87,7 @@ status = "okay"; broken-cd; cap-mmc-highspeed; - supports-hs200-mode; /* 200 MHz */ + mmc-hs200-1_8v; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index ff1ee409eff3..a97449b4640c 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -177,7 +177,7 @@ clock_g2d: clock-controller@10a00000 { compatible = "samsung,exynos5260-clock-g2d"; - reg = <0x10A00000 0x10000>; + reg = <0x10a00000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_G2D_333>; @@ -187,7 +187,7 @@ clock_mif: clock-controller@10ce0000 { compatible = "samsung,exynos5260-clock-mif"; - reg = <0x10CE0000 0x10000>; + reg = <0x10ce0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>; clock-names = "fin_pll"; @@ -213,7 +213,7 @@ clock_fsys: clock-controller@122e0000 { compatible = "samsung,exynos5260-clock-fsys"; - reg = <0x122E0000 0x10000>; + reg = <0x122e0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&fin_pll>, @@ -233,7 +233,7 @@ clock_aud: clock-controller@128c0000 { compatible = "samsung,exynos5260-clock-aud"; - reg = <0x128C0000 0x10000>; + reg = <0x128c0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_FOUT_AUD_PLL>, @@ -247,7 +247,7 @@ clock_isp: clock-controller@133c0000 { compatible = "samsung,exynos5260-clock-isp"; - reg = <0x133C0000 0x10000>; + reg = <0x133c0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_ISP1_266>, @@ -261,7 +261,7 @@ clock_gscl: clock-controller@13f00000 { compatible = "samsung,exynos5260-clock-gscl"; - reg = <0x13F00000 0x10000>; + reg = <0x13f00000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_GSCL_400>, @@ -335,7 +335,7 @@ mct: timer@100b0000 { compatible = "samsung,exynos5260-mct", "samsung,exynos4210-mct"; - reg = <0x100B0000 0x1000>; + reg = <0x100b0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, @@ -356,8 +356,8 @@ compatible = "arm,cci-400"; #address-cells = <1>; #size-cells = <1>; - reg = <0x10F00000 0x1000>; - ranges = <0x0 0x10F00000 0x6000>; + reg = <0x10f00000 0x1000>; + ranges = <0x0 0x10f00000 0x6000>; cci_control0: slave-if@4000 { compatible = "arm,cci-400-ctrl-if"; @@ -392,18 +392,18 @@ pinctrl_2: pinctrl@128b0000 { compatible = "samsung,exynos5260-pinctrl"; - reg = <0x128B0000 0x1000>; + reg = <0x128b0000 0x1000>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; }; pmu_system_controller: system-controller@10d50000 { compatible = "samsung,exynos5260-pmu", "syscon"; - reg = <0x10D50000 0x10000>; + reg = <0x10d50000 0x10000>; }; uart0: serial@12c00000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; + reg = <0x12c00000 0x100>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; @@ -412,7 +412,7 @@ uart1: serial@12c10000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; + reg = <0x12c10000 0x100>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; @@ -421,7 +421,7 @@ uart2: serial@12c20000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; + reg = <0x12c20000 0x100>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; @@ -499,7 +499,7 @@ hsi2c_0: i2c@12da0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DA0000 0x1000>; + reg = <0x12da0000 0x1000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -512,7 +512,7 @@ hsi2c_1: i2c@12db0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DB0000 0x1000>; + reg = <0x12db0000 0x1000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -525,7 +525,7 @@ hsi2c_2: i2c@12dc0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DC0000 0x1000>; + reg = <0x12dc0000 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -538,7 +538,7 @@ hsi2c_3: i2c@12dd0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DD0000 0x1000>; + reg = <0x12dd0000 0x1000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index d1cbc6b8a570..232561620da2 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -164,8 +164,7 @@ }; &hsi2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; + clock-frequency = <400000>; status = "okay"; usb3503: usb-hub@8 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 8a6b890fb8f7..350b8afa0a3a 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -81,7 +81,7 @@ clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5410-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; clock-names = "pll_ref", "pll_in"; diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi index d19bc3d266fa..63675fe189cd 100644 --- a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi +++ b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi @@ -51,7 +51,6 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; key-power { debounce-interval = <10>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9f2523a873d9..13d7be236a23 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -37,12 +37,123 @@ spi2 = &spi_2; }; + bus_disp1: bus-disp1 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_DISP1>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_disp1_fimd: bus-disp1-fimd { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_DISP1>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys2: bus-fsys2 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys_apb: bus-fsys-apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_PCLK200_FSYS>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_g2d: bus-g2d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333_G2D>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_g2d_acp: bus-g2d-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266_G2D>; + clock-names = "bus"; + status = "disabled"; + }; + bus_gen: bus-gen { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_gscl_scaler: bus-gscl-scaler { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_GSCL>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_jpeg: bus-jpeg { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_JPEG>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_jpeg_apb: bus-jpeg-apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK166>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_mscl: bus-mscl { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_MSCL>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_noc: bus-noc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK100_NOC>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK66>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_wcore: bus-wcore { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_WCORE>; + clock-names = "bus"; + status = "disabled"; + }; + /* * The 'cpus' node is not present here but instead it is provided * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. */ - cluster_a15_opp_table: opp-table0 { + cluster_a15_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -108,7 +219,7 @@ }; }; - cluster_a7_opp_table: opp-table1 { + cluster_a7_opp_table: opp-table-1 { compatible = "operating-points-v2"; opp-shared; @@ -182,7 +293,7 @@ clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5420-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; @@ -262,37 +373,37 @@ nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1000 0x200>; + reg = <0x10ca1000 0x200>; status = "disabled"; }; nocp_mem0_1: nocp@10ca1400 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1400 0x200>; + reg = <0x10ca1400 0x200>; status = "disabled"; }; nocp_mem1_0: nocp@10ca1800 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1800 0x200>; + reg = <0x10ca1800 0x200>; status = "disabled"; }; nocp_mem1_1: nocp@10ca1c00 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1C00 0x200>; + reg = <0x10ca1c00 0x200>; status = "disabled"; }; nocp_g3d_0: nocp@11a51000 { compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51000 0x200>; + reg = <0x11a51000 0x200>; status = "disabled"; }; nocp_g3d_1: nocp@11a51400 { compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51400 0x200>; + reg = <0x11a51400 0x200>; status = "disabled"; }; @@ -374,14 +485,14 @@ disp_pd: power-domain@100440c0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; + reg = <0x100440c0 0x20>; #power-domain-cells = <0>; label = "DISP"; }; mau_pd: power-domain@100440e0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440E0 0x20>; + reg = <0x100440e0 0x20>; #power-domain-cells = <0>; label = "MAU"; }; @@ -442,7 +553,7 @@ pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; + reg = <0x121a0000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; @@ -451,7 +562,7 @@ pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; + reg = <0x121b0000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; @@ -469,7 +580,7 @@ mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; + reg = <0x11c10000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; @@ -507,7 +618,7 @@ i2s1: i2s@12d60000 { compatible = "samsung,exynos5420-i2s"; - reg = <0x12D60000 0x100>; + reg = <0x12d60000 0x100>; dmas = <&pdma1 12>, <&pdma1 11>; dma-names = "tx", "rx"; @@ -523,7 +634,7 @@ i2s2: i2s@12d70000 { compatible = "samsung,exynos5420-i2s"; - reg = <0x12D70000 0x100>; + reg = <0x12d70000 0x100>; dmas = <&pdma0 12>, <&pdma0 11>; dma-names = "tx", "rx"; @@ -592,12 +703,12 @@ }; mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; + compatible = "samsung,exynos5420-mipi-video-phy"; syscon = <&pmu_system_controller>; #phy-cells = <1>; }; - dsi@14500000 { + dsi: dsi@14500000 { compatible = "samsung,exynos5410-mipi-dsi"; reg = <0x14500000 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -612,7 +723,7 @@ hsi2c_8: i2c@12e00000 { compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E00000 0x1000>; + reg = <0x12e00000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -625,7 +736,7 @@ hsi2c_9: i2c@12e10000 { compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E10000 0x1000>; + reg = <0x12e10000 0x1000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -638,7 +749,7 @@ hsi2c_10: i2c@12e20000 { compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E20000 0x1000>; + reg = <0x12e20000 0x1000>; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -665,13 +776,13 @@ #sound-dai-cells = <0>; }; - hdmiphy: hdmiphy@145d0000 { - reg = <0x145D0000 0x20>; + hdmiphy: hdmi-phy@145d0000 { + reg = <0x145d0000 0x20>; }; hdmicec: cec@101b0000 { compatible = "samsung,s5p-cec"; - reg = <0x101B0000 0x200>; + reg = <0x101b0000 0x200>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; @@ -696,7 +807,7 @@ rotator: rotator@11c00000 { compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; + reg = <0x11c00000 0x64>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; @@ -805,7 +916,7 @@ jpeg_0: jpeg@11f50000 { compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F50000 0x1000>; + reg = <0x11f50000 0x1000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG>; @@ -814,7 +925,7 @@ jpeg_1: jpeg@11f60000 { compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F60000 0x1000>; + reg = <0x11f60000 0x1000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG2>; @@ -879,7 +990,7 @@ sysmmu_g2dr: sysmmu@10a60000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; + reg = <0x10a60000 0x1000>; interrupt-parent = <&combiner>; interrupts = <24 5>; clock-names = "sysmmu", "master"; @@ -889,7 +1000,7 @@ sysmmu_g2dw: sysmmu@10a70000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A70000 0x1000>; + reg = <0x10a70000 0x1000>; interrupt-parent = <&combiner>; interrupts = <22 2>; clock-names = "sysmmu", "master"; @@ -910,7 +1021,7 @@ sysmmu_gscl0: sysmmu@13e80000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; + reg = <0x13e80000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 0>; clock-names = "sysmmu", "master"; @@ -921,7 +1032,7 @@ sysmmu_gscl1: sysmmu@13e90000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; + reg = <0x13e90000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 2>; clock-names = "sysmmu", "master"; @@ -953,7 +1064,7 @@ sysmmu_scaler2r: sysmmu@128a0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128A0000 0x1000>; + reg = <0x128a0000 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; @@ -963,7 +1074,7 @@ sysmmu_scaler0w: sysmmu@128c0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128C0000 0x1000>; + reg = <0x128c0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <27 2>; clock-names = "sysmmu", "master"; @@ -974,7 +1085,7 @@ sysmmu_scaler1w: sysmmu@128d0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128D0000 0x1000>; + reg = <0x128d0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <22 6>; clock-names = "sysmmu", "master"; @@ -985,7 +1096,7 @@ sysmmu_scaler2w: sysmmu@128e0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128E0000 0x1000>; + reg = <0x128e0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <19 6>; clock-names = "sysmmu", "master"; @@ -996,7 +1107,7 @@ sysmmu_rotator: sysmmu@11d40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; + reg = <0x11d40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 0>; clock-names = "sysmmu", "master"; @@ -1006,7 +1117,7 @@ sysmmu_jpeg0: sysmmu@11f10000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11F10000 0x1000>; + reg = <0x11f10000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 2>; clock-names = "sysmmu", "master"; @@ -1016,7 +1127,7 @@ sysmmu_jpeg1: sysmmu@11f20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; + reg = <0x11f20000 0x1000>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; @@ -1066,118 +1177,6 @@ power-domains = <&disp_pd>; #iommu-cells = <0>; }; - - bus_wcore: bus-wcore { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_WCORE>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_noc: bus-noc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK100_NOC>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys_apb: bus-fsys-apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_PCLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys2: bus-fsys2 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_gen: bus-gen { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK66>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d: bus-g2d { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d_acp: bus-g2d-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg: bus-jpeg { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_JPEG>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg_apb: bus-jpeg-apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK166>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_disp1_fimd: bus-disp1-fimd { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_disp1: bus-disp1 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_gscl_scaler: bus-gscl-scaler { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_GSCL>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mscl: bus-mscl { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_MSCL>; - clock-names = "bus"; - status = "disabled"; - }; }; thermal-zones { diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 35818c4cd852..30fc677d8bac 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -16,7 +16,7 @@ / { memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x7EA00000>; + reg = <0x40000000 0x7ea00000>; }; chosen { @@ -35,7 +35,7 @@ }; }; - bus_wcore_opp_table: opp-table2 { + bus_wcore_opp_table: opp-table-2 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -61,7 +61,7 @@ }; }; - bus_noc_opp_table: opp-table3 { + bus_noc_opp_table: opp-table-3 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -79,7 +79,7 @@ }; }; - bus_fsys_apb_opp_table: opp-table4 { + bus_fsys_apb_opp_table: opp-table-4 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -91,7 +91,7 @@ }; }; - bus_fsys2_opp_table: opp-table5 { + bus_fsys2_opp_table: opp-table-5 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -106,7 +106,7 @@ }; }; - bus_mfc_opp_table: opp-table6 { + bus_mfc_opp_table: opp-table-6 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -127,7 +127,7 @@ }; }; - bus_gen_opp_table: opp-table7 { + bus_gen_opp_table: opp-table-7 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -145,7 +145,7 @@ }; }; - bus_peri_opp_table: opp-table8 { + bus_peri_opp_table: opp-table-8 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -154,7 +154,7 @@ }; }; - bus_g2d_opp_table: opp-table9 { + bus_g2d_opp_table: opp-table-9 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -175,7 +175,7 @@ }; }; - bus_g2d_acp_opp_table: opp-table10 { + bus_g2d_acp_opp_table: opp-table-10 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -193,7 +193,7 @@ }; }; - bus_jpeg_opp_table: opp-table11 { + bus_jpeg_opp_table: opp-table-11 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -211,7 +211,7 @@ }; }; - bus_jpeg_apb_opp_table: opp-table12 { + bus_jpeg_apb_opp_table: opp-table-12 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -229,7 +229,7 @@ }; }; - bus_disp1_fimd_opp_table: opp-table13 { + bus_disp1_fimd_opp_table: opp-table-13 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -241,7 +241,7 @@ }; }; - bus_disp1_opp_table: opp-table14 { + bus_disp1_opp_table: opp-table-14 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -256,7 +256,7 @@ }; }; - bus_gscl_opp_table: opp-table15 { + bus_gscl_opp_table: opp-table-15 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -271,7 +271,7 @@ }; }; - bus_mscl_opp_table: opp-table16 { + bus_mscl_opp_table: opp-table-16 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -292,7 +292,7 @@ }; }; - dmc_opp_table: opp-table17 { + dmc_opp_table: opp-table-17 { compatible = "operating-points-v2"; opp00 { diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts new file mode 100644 index 000000000000..df41723d56d4 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Galaxy S5 (SM-G900H) device-tree source + * + * Copyright (c) 2023 Markuss Broks + */ + +/dts-v1/; +#include <dt-bindings/clock/samsung,s2mps11.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" + +/ { + model = "Samsung Galaxy S5 (SM-G900H)"; + compatible = "samsung,k3g", "samsung,exynos5800", \ + "samsung,exynos5"; + + chassis-type = "handset"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; /* 2 GiB */ + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + tsp_vdd: regulator-tsp-vdd-en { + compatible = "regulator-fixed"; + regulator-name = "tsp_vdd_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpy3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&gpu { + status = "okay"; + mali-supply = <&buck4_reg>; +}; + +&hsi2c_7 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD_KFC"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "VDD_CAM_ISP"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3550000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_APIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_APIO_MMC01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_ADC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_HRM_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_MIPI_PLL_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD_VTF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_UOTG"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_HSIC_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDD_APIO_MMC2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD_MOTOR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD_CAM1_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + /* Unused */ + regulator-name = "VDD_LDO17"; + }; + + ldo18_reg: LDO18 { + regulator-name = "VDD_CODEC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_VMMC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD_CAM1_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_CAM_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "VDD_CAM0_S_CORE"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD_MIFS"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD_MHL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD_CAM0_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo27_reg: LDO27 { + regulator-name = "VDD_G3DS"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + regulator-name = "VDD_LCD_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo29_reg: LDO29 { + /* Unused */ + regulator-name = "VDD_LDO29"; + }; + + ldo30_reg: LDO30 { + regulator-name = "VDD_TOUCH"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo31_reg: LDO31 { + regulator-name = "VDD_COMP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo32_reg: LDO32 { + regulator-name = "VDD_TOUCH_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo33_reg: LDO33 { + regulator-name = "VDD_MHL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo34_reg: LDO34 { + regulator-name = "VDD_HRM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo35_reg: LDO35 { + regulator-name = "VDD_SIL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "VDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "VDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "VDD_KEY_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c_0 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupt-parent = <&gpx1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + vio-supply = <&ldo32_reg>; + vdd-supply = <&tsp_vdd>; + syna,startup-delay-ms = <100>; + + pinctrl-0 = <&touch_irq>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +/* eMMC flash */ +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + cap-mmc-highspeed; + non-removable; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; + bus-width = <8>; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx0-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; + + touch_irq: touch-irq-pins { + samsung,pins = "gpx1-6"; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&timer { + arm,cpu-registers-not-fw-configured; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 3ec43761d8b9..5c799886c275 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -142,15 +142,15 @@ status = "disabled"; }; - usbdrd3_0: usb3-0 { + usbdrd3_0: usb@12000000 { compatible = "samsung,exynos5250-dwusb3"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x12000000 0x10000>; - usbdrd_dwc3_0: usb@12000000 { + usbdrd_dwc3_0: usb@0 { compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; + reg = <0x0 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; phy-names = "usb2-phy", "usb3-phy"; @@ -164,15 +164,15 @@ #phy-cells = <1>; }; - usbdrd3_1: usb3-1 { + usbdrd3_1: usb@12400000 { compatible = "samsung,exynos5250-dwusb3"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x12400000 0x10000>; - usbdrd_dwc3_1: usb@12400000 { + usbdrd_dwc3_1: usb@0 { compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; + reg = <0x0 0x10000>; phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; phy-names = "usb2-phy", "usb3-phy"; snps,dis_u3_susphy_quirk; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 526729dad53f..8328ddb3b02f 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -148,6 +148,10 @@ }; }; +&dsi { + compatible = "samsung,exynos5422-mipi-dsi"; +}; + &mfc { compatible = "samsung,mfc-v8"; }; |