diff options
14 files changed, 1262 insertions, 23 deletions
diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml index 9952e0ef7767..6ad78429dc74 100644 --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml @@ -163,11 +163,9 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/phy/phy.h> sata: ahci@fd0c0000 { @@ -175,7 +173,7 @@ examples: reg = <0xfd0c0000 0x200>; interrupt-parent = <&gic>; interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zynqmp_clk SATA_REF>; + clocks = <&zynqmp_clk 22>; ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index ac3198953b8e..b5399c65a731 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -75,7 +75,6 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> fpd_dma_chan1: dma-controller@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; @@ -84,7 +83,7 @@ examples: interrupts = <0 117 0x4>; #dma-cells = <1>; clock-names = "clk_main", "clk_apb"; - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; xlnx,bus-width = <128>; dma-coherent; }; diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml index 8cbad7e792b6..a403392fb263 100644 --- a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -193,7 +193,6 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> bus { #address-cells = <2>; @@ -204,7 +203,7 @@ examples: interrupt-parent = <&gic>; interrupts = <0 56 4>; reg = <0x0 0xffa50000 0x0 0x800>; - clocks = <&zynqmp_clk AMS_REF>; + clocks = <&zynqmp_clk 70>; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 3c30dd23cd4e..8d69846b2e09 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -197,7 +197,6 @@ examples: }; - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> #include <dt-bindings/phy/phy.h> @@ -210,9 +209,9 @@ examples: interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, - <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, - <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, + <&zynqmp_clk 51>, <&zynqmp_clk 50>, + <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index 131aba5ed9f4..fb5c39c79d28 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -9,8 +9,8 @@ title: Xilinx Zynq Platforms maintainers: - Michal Simek <michal.simek@amd.com> -description: | - Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC +description: + AMD/Xilinx boards with ARM 32/64bits cores properties: $nodename: @@ -187,6 +187,13 @@ properties: - const: qemu,mbv - const: amd,mbv + - description: Xilinx Versal NET VN-X revA platform + items: + enum: + - xlnx,versal-net-vnx-revA + - xlnx,versal-net-vnx + - xlnx,versal-net + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 04d4d3b4916d..02cf1314367b 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -65,14 +65,13 @@ allOf: examples: - | - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> soc { #address-cells = <2>; #size-cells = <2>; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; - clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 53>, <&zynqmp_clk 82>; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index 00f87a558c7d..b5843f4d17d8 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -101,7 +101,6 @@ examples: #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> - #include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> #include <dt-bindings/phy/phy.h> axi { @@ -113,7 +112,7 @@ examples: #size-cells = <0x2>; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; - clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 1068b0fa8e98..7f5a8801cad1 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -29,3 +29,5 @@ zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv- dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb + +dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi new file mode 100644 index 000000000000..b7a8a1a512cb --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET fixed clock + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/ { + clk60: clk60 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + }; + + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk150: clk150 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; + + clk160: clk160 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <160000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + clk450: clk450 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <450000000>; + }; + + clk1200: clk1200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1200000000>; + }; + + firmware { + versal_net_firmware: versal-net-firmware { + compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; + bootph-all; + method = "smc"; + }; + }; +}; + +&adma0 { + clocks = <&clk450>, <&clk450>; +}; + +&adma1 { + clocks = <&clk450>, <&clk450>; +}; + +&adma2 { + clocks = <&clk450>, <&clk450>; +}; + +&adma3 { + clocks = <&clk450>, <&clk450>; +}; + +&adma4 { + clocks = <&clk450>, <&clk450>; +}; + +&adma5 { + clocks = <&clk450>, <&clk450>; +}; + +&adma6 { + clocks = <&clk450>, <&clk450>; +}; + +&adma7 { + clocks = <&clk450>, <&clk450>; +}; + +&can0 { + clocks = <&clk160>, <&clk160>; +}; + +&can1 { + clocks = <&clk160>, <&clk160>; +}; + +&gem0 { + clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; +}; + +&gem1 { + clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; +}; + +&gpio0 { + clocks = <&clk100>; +}; + +&gpio1 { + clocks = <&clk100>; +}; + +&i2c0 { + clocks = <&clk100>; +}; + +&i2c1 { + clocks = <&clk100>; +}; + +&i3c0 { + clocks = <&clk100>; +}; + +&i3c1 { + clocks = <&clk100>; +}; + +&ospi { + clocks = <&clk200>; +}; + +&qspi { + clocks = <&clk300>, <&clk300>; +}; + +&rtc { + /* Nothing */ +}; + +&sdhci0 { + clocks = <&clk200>, <&clk200>, <&clk1200>; +}; + +&sdhci1 { + clocks = <&clk200>, <&clk200>, <&clk1200>; +}; + +&serial0 { + clocks = <&clk100>, <&clk100>; +}; + +&serial1 { + clocks = <&clk100>, <&clk100>; +}; + +&spi0 { + clocks = <&clk200>, <&clk200>; +}; + +&spi1 { + clocks = <&clk200>, <&clk200>; +}; + +&ttc0 { + clocks = <&clk150>; +}; + +&usb0 { + clocks = <&clk60>, <&clk60>; +}; + +&dwc3_0 { + clocks = <&clk60>; +}; + +&usb1 { + clocks = <&clk60>, <&clk60>; +}; + +&dwc3_1 { + clocks = <&clk60>; +}; + +&wwdt0 { + clocks = <&clk150>; +}; + +&wwdt1 { + clocks = <&clk150>; +}; + +&wwdt2 { + clocks = <&clk150>; +}; + +&wwdt3 { + clocks = <&clk150>; +}; + +&lpd_wwdt0 { + clocks = <&clk150>; +}; + +&lpd_wwdt1 { + clocks = <&clk150>; +}; diff --git a/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts b/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts new file mode 100644 index 000000000000..06b2301f48a0 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-net-vn-x-b2197-01-revA.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Net VNX board revA + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "versal-net.dtsi" +#include "versal-net-clk.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net"; + model = "Xilinx Versal NET VNX revA"; + dma-coherent; + + memory: memory@0 { + reg = <0 0 0 0x80000000>; + device_type = "memory"; + }; + + memory_hi: memory@800000000 { + reg = <8 0 3 0x80000000>; + device_type = "memory"; + }; + + memory_hi2: memory@50000000000 { + reg = <0x500 0 4 0>; + device_type = "memory"; + }; + + chosen { + bootargs = "console=ttyAMA1,115200n8"; + stdout-path = "serial1:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rsc_tbl_carveout: rproc@bbf14000 { + reg = <0 0xbbf14000 0 0x1000>; + no-map; + }; + rpu0vdev0vring0: rpu0vdev0vring0@bbf15000 { + reg = <0 0xbbf15000 0 0x1000>; + no-map; + }; + rpu0vdev0vring1: rpu0vdev0vring1@bbf16000 { + reg = <0 0xbbf16000 0 0x1000>; + no-map; + }; + rpu0vdev0buffer: rpu0vdev0buffer@bbf17000 { + reg = <0 0xbbf17000 0 0xD000>; + no-map; + }; + reserve_others: reserveothers@0 { + reg = <0 0x0 0 0x1c200000>; + no-map; + }; + pdi_update: pdiupdate@1c200000 { + reg = <0 0x1c200000 0 0x6000000>; + no-map; + }; + reserve_optee_atf: reserveopteeatf@22200000 { + reg = <0 0x22200000 0 0x4100000>; + no-map; + }; + }; +}; + +&gem1 { + status = "okay"; + iommus = <&smmu 0x235>; + phy-handle = <&phy>; + phy-mode = "rmii"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy: ethernet-phy@4 { + reg = <4>; + }; + }; +}; + +&ospi { + num-cs = <2>; + iommus = <&smmu 0x245>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&sdhci1 { + status = "okay"; + iommus = <&smmu 0x243>; + non-removable; + disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; + bus-width = <8>; + no-1-8-v; +}; + +&serial1 { + status = "okay"; +}; + +&smmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi new file mode 100644 index 000000000000..fc9f49e57385 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net"; + model = "Xilinx Versal NET"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu100>; + }; + core2 { + cpu = <&cpu200>; + }; + core3 { + cpu = <&cpu300>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu10000>; + }; + + core1 { + cpu = <&cpu10100>; + }; + + core2 { + cpu = <&cpu10200>; + }; + + core3 { + cpu = <&cpu10300>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu20000>; + }; + + core1 { + cpu = <&cpu20100>; + }; + + core2 { + cpu = <&cpu20200>; + }; + + core3 { + cpu = <&cpu20300>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu30000>; + }; + + core1 { + cpu = <&cpu30100>; + }; + + core2 { + cpu = <&cpu30200>; + }; + + core3 { + cpu = <&cpu30300>; + }; + }; + + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu100: cpu@100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu200: cpu@200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu300: cpu@300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10000: cpu@10000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10100: cpu@10100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10200: cpu@10200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10300: cpu@10300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20000: cpu@20000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20100: cpu@20100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20200: cpu@20200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20300: cpu@20300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30000: cpu@30000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30100: cpu@30100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30200: cpu@30200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30300: cpu@30300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <600>; + min-residency-us = <10000>; + }; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-1066000000 { + opp-hz = /bits/ 64 <1066000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1866000000 { + opp-hz = /bits/ 64 <1866000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1999000000 { + opp-hz = /bits/ 64 <1999000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2050000000 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2100000000 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2200000000 { + opp-hz = /bits/ 64 <2200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &dcc; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc = &rtc; + usb0 = &usb0; + usb1 = &usb1; + spi0 = &ospi; + spi1 = &qspi; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + bootph-all; + }; + + firmware { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + fpga: fpga-region { + compatible = "fpga-region"; + fpga-mgr = <&versal_fpga>; + #address-cells = <2>; + #size-cells = <2>; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; + }; + + versal_fpga: versal-fpga { + compatible = "xlnx,versal-fpga"; + }; + + amba: axi { + compatible = "simple-bus"; + bootph-all; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + adma0: dma-controller@ebd00000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd00000 0 0x1000>; + interrupts = <0 72 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma1: dma-controller@ebd10000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd10000 0 0x1000>; + interrupts = <0 73 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma2: dma-controller@ebd20000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd20000 0 0x1000>; + interrupts = <0 74 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma3: dma-controller@ebd30000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd30000 0 0x1000>; + interrupts = <0 75 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma4: dma-controller@ebd40000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd40000 0 0x1000>; + interrupts = <0 76 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma5: dma-controller@ebd50000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd50000 0 0x1000>; + interrupts = <0 77 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma6: dma-controller@ebd60000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd60000 0 0x1000>; + interrupts = <0 78 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma7: dma-controller@ebd70000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd70000 0 0x1000>; + interrupts = <0 79 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + can0: can@f1980000 { + compatible = "xlnx,canfd-2.0"; + status = "disabled"; + reg = <0 0xf1980000 0 0x6000>; + interrupts = <0 27 4>; + clock-names = "can_clk", "s_axi_aclk"; + rx-fifo-depth = <64>; + tx-mailbox-count = <32>; + }; + + can1: can@f1990000 { + compatible = "xlnx,canfd-2.0"; + status = "disabled"; + reg = <0 0xf1990000 0 0x6000>; + interrupts = <0 28 4>; + clock-names = "can_clk", "s_axi_aclk"; + rx-fifo-depth = <64>; + tx-mailbox-count = <32>; + }; + + gem0: ethernet@f19e0000 { + compatible = "xlnx,versal-gem", "cdns,gem"; + status = "disabled"; + reg = <0 0xf19e0000 0 0x1000>; + interrupts = <0 39 4>, <0 39 4>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", + "tsu_clk"; + }; + + gem1: ethernet@f19f0000 { + compatible = "xlnx,versal-gem", "cdns,gem"; + status = "disabled"; + reg = <0 0xf19f0000 0 0x1000>; + interrupts = <0 41 4>, <0 41 4>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", + "tsu_clk"; + }; + + gic: interrupt-controller@e2000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + reg = <0 0xe2000000 0 0x10000>, + <0 0xe2060000 0 0x200000>; + interrupt-controller; + interrupts = <1 9 4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + its: msi-controller@e2040000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0 0xe2040000 0 0x20000>; + }; + }; + + gpio0: gpio@f19d0000 { + compatible = "xlnx,versal-gpio-1.0"; + status = "disabled"; + reg = <0 0xf19d0000 0 0x1000>; + interrupts = <0 20 4>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@f1020000 { + compatible = "xlnx,pmc-gpio-1.0"; + status = "disabled"; + reg = <0 0xf1020000 0 0x1000>; + interrupts = <0 180 4>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + i2c0: i2c@f1940000 { + compatible = "cdns,i2c-r1p14"; + status = "disabled"; + reg = <0 0xf1940000 0 0x1000>; + interrupts = <0 21 4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@f1950000 { + compatible = "cdns,i2c-r1p14"; + status = "disabled"; + reg = <0 0xf1950000 0 0x1000>; + interrupts = <0 22 4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i3c0: i3c@f1948000 { + compatible = "snps,dw-i3c-master-1.00a"; + status = "disabled"; + reg = <0 0xf1948000 0 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <0 21 4>; + }; + + i3c1: i3c@f1958000 { + compatible = "snps,dw-i3c-master-1.00a"; + status = "disabled"; + reg = <0 0xf1958000 0 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <0 22 4>; + }; + + ospi: spi@f1010000 { + compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; + status = "disabled"; + reg = <0 0xf1010000 0 0x10000>, + <0 0xc0000000 0 0x20000000>; + interrupts = <0 182 4>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,is-dma = <1>; /* u-boot specific */ + cdns,trigger-address = <0xc0000000>; + }; + + qspi: spi@f1030000 { + compatible = "xlnx,versal-qspi-1.0"; + status = "disabled"; + reg = <0 0xf1030000 0 0x1000>; + interrupts = <0 183 4>; + clock-names = "ref_clk", "pclk"; + }; + + rtc: rtc@f12a0000 { + compatible = "xlnx,zynqmp-rtc"; + status = "disabled"; + reg = <0 0xf12a0000 0 0x100>; + interrupts = <0 200 4>, <0 201 4>; + interrupt-names = "alarm", "sec"; + calibration = <0x8000>; + }; + + sdhci0: mmc@f1040000 { + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0 0xf1040000 0 0x10000>; + interrupts = <0 184 4>; + clock-names = "clk_xin", "clk_ahb", "gate"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; + }; + + sdhci1: mmc@f1050000 { + compatible = "xlnx,versal-net-emmc"; + status = "disabled"; + reg = <0 0xf1050000 0 0x10000>; + interrupts = <0 186 4>; + clock-names = "clk_xin", "clk_ahb", "gate"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd1", "clk_in_sd1"; + }; + + serial0: serial@f1920000 { + bootph-all; + compatible = "arm,pl011", "arm,primecell"; + status = "disabled"; + reg = <0 0xf1920000 0 0x1000>; + interrupts = <0 25 4>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: serial@f1930000 { + bootph-all; + compatible = "arm,pl011", "arm,primecell"; + status = "disabled"; + reg = <0 0xf1930000 0 0x1000>; + interrupts = <0 26 4>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + }; + + smmu: iommu@ec000000 { + compatible = "arm,smmu-v3"; + status = "disabled"; + reg = <0 0xec000000 0 0x40000>; + #iommu-cells = <1>; + interrupt-names = "combined"; + interrupts = <0 169 4>; + dma-coherent; + }; + + spi0: spi@f1960000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupts = <0 23 4>; + reg = <0 0xf1960000 0 0x1000>; + clock-names = "ref_clk", "pclk"; + }; + + spi1: spi@f1970000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupts = <0 24 4>; + reg = <0 0xf1970000 0 0x1000>; + clock-names = "ref_clk", "pclk"; + }; + + ttc0: timer@f1dc0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 43 4>, <0 44 4>, <0 45 4>; + timer-width = <32>; + reg = <0x0 0xf1dc0000 0x0 0x1000>; + }; + + ttc1: timer@f1dd0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 46 4>, <0 47 4>, <0 48 4>; + timer-width = <32>; + reg = <0x0 0xf1dd0000 0x0 0x1000>; + }; + + ttc2: timer@f1de0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 49 4>, <0 50 4>, <0 51 4>; + timer-width = <32>; + reg = <0x0 0xf1de0000 0x0 0x1000>; + }; + + ttc3: timer@f1df0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 52 4>, <0 53 4>, <0 54 4>; + timer-width = <32>; + reg = <0x0 0xf1df0000 0x0 0x1000>; + }; + + usb0: usb@f1e00000 { + compatible = "xlnx,versal-dwc3"; + status = "disabled"; + reg = <0 0xf1e00000 0 0x100>; + clock-names = "bus_clk", "ref_clk"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dwc3_0: usb@f1b00000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0 0xf1b00000 0 0x10000>; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + snps,usb3_lpm_capable; + clock-names = "ref"; + }; + }; + + usb1: usb@f1e10000 { + compatible = "xlnx,versal-dwc3"; + status = "disabled"; + reg = <0x0 0xf1e10000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dwc3_1: usb@f1c00000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0x0 0xf1c00000 0x0 0x10000>; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,usb3_lpm_capable; + clock-names = "ref"; + }; + }; + + wwdt0: watchdog@ecc10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecc10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt1: watchdog@ecd10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecd10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt2: watchdog@ece10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xece10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt3: watchdog@ecf10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecf10000 0 0x10000>; + timeout-sec = <30>; + }; + + lpd_wwdt0: watchdog@ea420000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xea420000 0 0x10000>; + timeout-sec = <30>; + }; + + lpd_wwdt1: watchdog@ea430000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xea430000 0 0x10000>; + timeout-sec = <30>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h b/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h new file mode 100644 index 000000000000..0aa17f2a2818 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _XLNX_ZYNQMP_CLK_H +#define _XLNX_ZYNQMP_CLK_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif /* _XLNX_ZYNQMP_CLK_H */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 60d1b1acf9a0..52e122fc7c9e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -8,41 +8,46 @@ * Michal Simek <michal.simek@amd.com> */ -#include <dt-bindings/clock/xlnx-zynqmp-clk.h> +#include "xlnx-zynqmp-clk.h" / { - pss_ref_clk: pss_ref_clk { + pss_ref_clk: pss-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; + clock-output-names = "pss_ref_clk"; }; - video_clk: video_clk { + video_clk: video-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "video_clk"; }; - pss_alt_ref_clk: pss_alt_ref_clk { + pss_alt_ref_clk: pss-alt-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; + clock-output-names = "pss_alt_ref_clk"; }; - gt_crx_ref_clk: gt_crx_ref_clk { + gt_crx_ref_clk: gt-crx-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; + clock-output-names = "gt_crx_ref_clk"; }; - aux_ref_clk: aux_ref_clk { + aux_ref_clk: aux-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "aux_ref_clk"; }; }; diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cdc4c0b9a374..f0f7ddd3dcbd 100644 --- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -9,6 +9,13 @@ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure firmware values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead use the header in the DTS source directory." + #define IOPLL 0 #define RPLL 1 #define APLL 2 |