diff options
| -rw-r--r-- | arch/riscv/kernel/head.S | 10 | ||||
| -rw-r--r-- | arch/riscv/kvm/vcpu.c | 3 |
2 files changed, 10 insertions, 3 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 356d5397b2a2..bdf3352acf4c 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -131,6 +131,12 @@ secondary_start_sbi: csrw CSR_IE, zero csrw CSR_IP, zero +#ifndef CONFIG_RISCV_M_MODE + /* Enable time CSR */ + li t0, 0x2 + csrw CSR_SCOUNTEREN, t0 +#endif + /* Load the global pointer */ load_global_pointer @@ -226,6 +232,10 @@ SYM_CODE_START(_start_kernel) * to hand it to us. */ csrr a0, CSR_MHARTID +#else + /* Enable time CSR */ + li t0, 0x2 + csrw CSR_SCOUNTEREN, t0 #endif /* CONFIG_RISCV_M_MODE */ /* Load the global pointer */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index a78f9ec2fa0e..a7188e007db9 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -79,9 +79,6 @@ static void kvm_riscv_vcpu_context_reset(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_VTW; cntx->hstatus |= HSTATUS_SPVP; cntx->hstatus |= HSTATUS_SPV; - - /* By default, make CY, TM, and IR counters accessible in VU mode */ - csr->scounteren = 0x7; } static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) |