diff options
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 38 |
1 files changed, 28 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 439831715cbb..db8fef7a4f1b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -275,9 +275,6 @@ ð0m0_rgmii_clk ð0m0_rgmii_bus ðm0_clk0_25m_out>; - snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x21>; status = "okay"; }; @@ -293,9 +290,6 @@ ð1m0_rgmii_clk ð1m0_rgmii_bus ðm0_clk1_25m_out>; - snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x20>; status = "okay"; }; @@ -715,18 +709,32 @@ }; &mdio0 { - rgmii_phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; }; }; &mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; }; }; @@ -786,6 +794,16 @@ }; }; + network { + rgmii_phy0_rst: rgmii-phy0-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgmii_phy1_rst: rgmii-phy1-rst { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie0 { pcie0_rst: pcie0-rst { rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; |