diff options
| -rw-r--r-- | drivers/pinctrl/pinctrl-cy8c95x0.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 781949e0e09e..9a92707d2525 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -475,7 +475,7 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip bool *change, bool async, bool force) { - int ret, off, i, read_val; + int ret, off, i; /* Caller should never modify PORTSEL directly */ if (reg == CY8C95X0_PORTSEL) @@ -497,24 +497,20 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip if (ret < 0) return ret; - /* Update the cache when a WC bit is written */ + /* Mimic what hardware does and update the cache when a WC bit is written. + * Allows to mark the registers as non-volatile and reduces I/O cycles. + */ if (cy8c95x0_wc_register(reg) && (mask & val)) { + /* Writing a 1 clears set bits in the other drive mode registers */ + regcache_cache_only(chip->regmap, true); for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) { if (i == reg) continue; - off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port); - - ret = regmap_read(chip->regmap, off, &read_val); - if (ret < 0) - continue; - if (!(read_val & mask & val)) - continue; - - regcache_cache_only(chip->regmap, true); - regmap_update_bits(chip->regmap, off, mask & val, 0); - regcache_cache_only(chip->regmap, false); + off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port); + regmap_clear_bits(chip->regmap, off, mask & val); } + regcache_cache_only(chip->regmap, false); } return ret; |