diff options
30 files changed, 4541 insertions, 3623 deletions
diff --git a/drivers/accel/habanalabs/common/command_submission.c b/drivers/accel/habanalabs/common/command_submission.c index 8270db0a72a2..af9d2e22c6e7 100644 --- a/drivers/accel/habanalabs/common/command_submission.c +++ b/drivers/accel/habanalabs/common/command_submission.c @@ -14,10 +14,10 @@ #define HL_CS_FLAGS_TYPE_MASK (HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT | \ HL_CS_FLAGS_COLLECTIVE_WAIT | HL_CS_FLAGS_RESERVE_SIGNALS_ONLY | \ HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND | \ - HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES) + HL_CS_FLAGS_ENGINES_COMMAND | HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES) -#define MAX_TS_ITER_NUM 10 +#define MAX_TS_ITER_NUM 100 /** * enum hl_cs_wait_status - cs wait status @@ -657,7 +657,7 @@ static inline void cs_release_sob_reset_handler(struct hl_device *hdev, /* * we get refcount upon reservation of signals or signal/wait cs for the * hw_sob object, and need to put it when the first staged cs - * (which cotains the encaps signals) or cs signal/wait is completed. + * (which contains the encaps signals) or cs signal/wait is completed. */ if ((hl_cs_cmpl->type == CS_TYPE_SIGNAL) || (hl_cs_cmpl->type == CS_TYPE_WAIT) || @@ -1082,9 +1082,8 @@ static void wake_pending_user_interrupt_threads(struct hl_user_interrupt *interrupt) { struct hl_user_pending_interrupt *pend, *temp; - unsigned long flags; - spin_lock_irqsave(&interrupt->wait_list_lock, flags); + spin_lock(&interrupt->wait_list_lock); list_for_each_entry_safe(pend, temp, &interrupt->wait_list_head, wait_list_node) { if (pend->ts_reg_info.buf) { list_del(&pend->wait_list_node); @@ -1095,7 +1094,7 @@ wake_pending_user_interrupt_threads(struct hl_user_interrupt *interrupt) complete_all(&pend->fence.completion); } } - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); } void hl_release_pending_user_interrupts(struct hl_device *hdev) @@ -1168,6 +1167,22 @@ static void cs_completion(struct work_struct *work) hl_complete_job(hdev, job); } +u32 hl_get_active_cs_num(struct hl_device *hdev) +{ + u32 active_cs_num = 0; + struct hl_cs *cs; + + spin_lock(&hdev->cs_mirror_lock); + + list_for_each_entry(cs, &hdev->cs_mirror_list, mirror_node) + if (!cs->completed) + active_cs_num++; + + spin_unlock(&hdev->cs_mirror_lock); + + return active_cs_num; +} + static int validate_queue_index(struct hl_device *hdev, struct hl_cs_chunk *chunk, enum hl_queue_type *queue_type, @@ -1304,6 +1319,8 @@ static enum hl_cs_type hl_cs_get_cs_type(u32 cs_type_flags) return CS_UNRESERVE_SIGNALS; else if (cs_type_flags & HL_CS_FLAGS_ENGINE_CORE_COMMAND) return CS_TYPE_ENGINE_CORE; + else if (cs_type_flags & HL_CS_FLAGS_ENGINES_COMMAND) + return CS_TYPE_ENGINES; else if (cs_type_flags & HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES) return CS_TYPE_FLUSH_PCI_HBW_WRITES; else @@ -2429,10 +2446,13 @@ out: static int cs_ioctl_engine_cores(struct hl_fpriv *hpriv, u64 engine_cores, u32 num_engine_cores, u32 core_command) { - int rc; struct hl_device *hdev = hpriv->hdev; void __user *engine_cores_arr; u32 *cores; + int rc; + + if (!hdev->asic_prop.supports_engine_modes) + return -EPERM; if (!num_engine_cores || num_engine_cores > hdev->asic_prop.num_engine_cores) { dev_err(hdev->dev, "Number of engine cores %d is invalid\n", num_engine_cores); @@ -2461,6 +2481,48 @@ static int cs_ioctl_engine_cores(struct hl_fpriv *hpriv, u64 engine_cores, return rc; } +static int cs_ioctl_engines(struct hl_fpriv *hpriv, u64 engines_arr_user_addr, + u32 num_engines, enum hl_engine_command command) +{ + struct hl_device *hdev = hpriv->hdev; + u32 *engines, max_num_of_engines; + void __user *engines_arr; + int rc; + + if (!hdev->asic_prop.supports_engine_modes) + return -EPERM; + + if (command >= HL_ENGINE_COMMAND_MAX) { + dev_err(hdev->dev, "Engine command is invalid\n"); + return -EINVAL; + } + + max_num_of_engines = hdev->asic_prop.max_num_of_engines; + if (command == HL_ENGINE_CORE_RUN || command == HL_ENGINE_CORE_HALT) + max_num_of_engines = hdev->asic_prop.num_engine_cores; + + if (!num_engines || num_engines > max_num_of_engines) { + dev_err(hdev->dev, "Number of engines %d is invalid\n", num_engines); + return -EINVAL; + } + + engines_arr = (void __user *) (uintptr_t) engines_arr_user_addr; + engines = kmalloc_array(num_engines, sizeof(u32), GFP_KERNEL); + if (!engines) + return -ENOMEM; + + if (copy_from_user(engines, engines_arr, num_engines * sizeof(u32))) { + dev_err(hdev->dev, "Failed to copy engine-ids array from user\n"); + kfree(engines); + return -EFAULT; + } + + rc = hdev->asic_funcs->set_engines(hdev, engines, num_engines, command); + kfree(engines); + + return rc; +} + static int cs_ioctl_flush_pci_hbw_writes(struct hl_fpriv *hpriv) { struct hl_device *hdev = hpriv->hdev; @@ -2532,6 +2594,10 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) rc = cs_ioctl_engine_cores(hpriv, args->in.engine_cores, args->in.num_engine_cores, args->in.core_command); break; + case CS_TYPE_ENGINES: + rc = cs_ioctl_engines(hpriv, args->in.engines, + args->in.num_engines, args->in.engine_command); + break; case CS_TYPE_FLUSH_PCI_HBW_WRITES: rc = cs_ioctl_flush_pci_hbw_writes(hpriv); break; @@ -3143,8 +3209,9 @@ static int ts_buff_get_kernel_ts_record(struct hl_mmap_mem_buf *buf, struct hl_user_pending_interrupt *cb_last = (struct hl_user_pending_interrupt *)ts_buff->kernel_buff_address + (ts_buff->kernel_buff_size / sizeof(struct hl_user_pending_interrupt)); - unsigned long flags, iter_counter = 0; + unsigned long iter_counter = 0; u64 current_cq_counter; + ktime_t timestamp; /* Validate ts_offset not exceeding last max */ if (requested_offset_record >= cb_last) { @@ -3153,8 +3220,10 @@ static int ts_buff_get_kernel_ts_record(struct hl_mmap_mem_buf *buf, return -EINVAL; } + timestamp = ktime_get(); + start_over: - spin_lock_irqsave(wait_list_lock, flags); + spin_lock(wait_list_lock); /* Unregister only if we didn't reach the target value * since in this case there will be no handling in irq context @@ -3165,7 +3234,7 @@ start_over: current_cq_counter = *requested_offset_record->cq_kernel_addr; if (current_cq_counter < requested_offset_record->cq_target_value) { list_del(&requested_offset_record->wait_list_node); - spin_unlock_irqrestore(wait_list_lock, flags); + spin_unlock(wait_list_lock); hl_mmap_mem_buf_put(requested_offset_record->ts_reg_info.buf); hl_cb_put(requested_offset_record->ts_reg_info.cq_cb); @@ -3176,13 +3245,14 @@ start_over: dev_dbg(buf->mmg->dev, "ts node in middle of irq handling\n"); - /* irq handling in the middle give it time to finish */ - spin_unlock_irqrestore(wait_list_lock, flags); - usleep_range(1, 10); + /* irq thread handling in the middle give it time to finish */ + spin_unlock(wait_list_lock); + usleep_range(100, 1000); if (++iter_counter == MAX_TS_ITER_NUM) { dev_err(buf->mmg->dev, - "handling registration interrupt took too long!!\n"); - return -EINVAL; + "Timestamp offset processing reached timeout of %lld ms\n", + ktime_ms_delta(ktime_get(), timestamp)); + return -EAGAIN; } goto start_over; @@ -3197,7 +3267,7 @@ start_over: (u64 *) cq_cb->kernel_address + cq_offset; requested_offset_record->cq_target_value = target_value; - spin_unlock_irqrestore(wait_list_lock, flags); + spin_unlock(wait_list_lock); } *pend = requested_offset_record; @@ -3217,7 +3287,7 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, struct hl_user_pending_interrupt *pend; struct hl_mmap_mem_buf *buf; struct hl_cb *cq_cb; - unsigned long timeout, flags; + unsigned long timeout; long completion_rc; int rc = 0; @@ -3264,7 +3334,7 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, pend->cq_target_value = target_value; } - spin_lock_irqsave(&interrupt->wait_list_lock, flags); + spin_lock(&interrupt->wait_list_lock); /* We check for completion value as interrupt could have been received * before we added the node to the wait list @@ -3272,7 +3342,7 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, if (*pend->cq_kernel_addr >= target_value) { if (register_ts_record) pend->ts_reg_info.in_use = 0; - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); *status = HL_WAIT_CS_STATUS_COMPLETED; @@ -3284,7 +3354,7 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, goto set_timestamp; } } else if (!timeout_us) { - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); *status = HL_WAIT_CS_STATUS_BUSY; pend->fence.timestamp = ktime_get(); goto set_timestamp; @@ -3309,7 +3379,7 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, pend->ts_reg_info.in_use = 1; list_add_tail(&pend->wait_list_node, &interrupt->wait_list_head); - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); if (register_ts_record) { rc = *status = HL_WAIT_CS_STATUS_COMPLETED; @@ -3353,9 +3423,9 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, * for ts record, the node will be deleted in the irq handler after * we reach the target value. */ - spin_lock_irqsave(&interrupt->wait_list_lock, flags); + spin_lock(&interrupt->wait_list_lock); list_del(&pend->wait_list_node); - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); set_timestamp: *timestamp = ktime_to_ns(pend->fence.timestamp); @@ -3383,7 +3453,7 @@ static int _hl_interrupt_wait_ioctl_user_addr(struct hl_device *hdev, struct hl_ u64 *timestamp) { struct hl_user_pending_interrupt *pend; - unsigned long timeout, flags; + unsigned long timeout; u64 completion_value; long completion_rc; int rc = 0; @@ -3403,9 +3473,9 @@ static int _hl_interrupt_wait_ioctl_user_addr(struct hl_device *hdev, struct hl_ /* Add pending user interrupt to relevant list for the interrupt * handler to monitor */ - spin_lock_irqsave(&interrupt->wait_list_lock, flags); + spin_lock(&interrupt->wait_list_lock); list_add_tail(&pend->wait_list_node, &interrupt->wait_list_head); - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); /* We check for completion value as interrupt could have been received * before we added the node to the wait list @@ -3436,14 +3506,14 @@ wait_again: * If comparison fails, keep waiting until timeout expires */ if (completion_rc > 0) { - spin_lock_irqsave(&interrupt->wait_list_lock, flags); + spin_lock(&interrupt->wait_list_lock); /* reinit_completion must be called before we check for user * completion value, otherwise, if interrupt is received after * the comparison and before the next wait_for_completion, * we will reach timeout and fail */ reinit_completion(&pend->fence.completion); - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); if (copy_from_user(&completion_value, u64_to_user_ptr(user_address), 8)) { dev_err(hdev->dev, "Failed to copy completion value from user\n"); @@ -3480,9 +3550,9 @@ wait_again: } remove_pending_user_interrupt: - spin_lock_irqsave(&interrupt->wait_list_lock, flags); + spin_lock(&interrupt->wait_list_lock); list_del(&pend->wait_list_node); - spin_unlock_irqrestore(&interrupt->wait_list_lock, flags); + spin_unlock(&interrupt->wait_list_lock); *timestamp = ktime_to_ns(pend->fence.timestamp); diff --git a/drivers/accel/habanalabs/common/debugfs.c b/drivers/accel/habanalabs/common/debugfs.c index 945c0e6758ca..22dd17c077c0 100644 --- a/drivers/accel/habanalabs/common/debugfs.c +++ b/drivers/accel/habanalabs/common/debugfs.c @@ -258,7 +258,7 @@ static int vm_show(struct seq_file *s, void *data) if (!dev_entry->hdev->mmu_enable) return 0; - spin_lock(&dev_entry->ctx_mem_hash_spinlock); + mutex_lock(&dev_entry->ctx_mem_hash_mutex); list_for_each_entry(ctx, &dev_entry->ctx_mem_hash_list, debugfs_list) { once = false; @@ -329,7 +329,7 @@ static int vm_show(struct seq_file *s, void *data) } - spin_unlock(&dev_entry->ctx_mem_hash_spinlock); + mutex_unlock(&dev_entry->ctx_mem_hash_mutex); ctx = hl_get_compute_ctx(dev_entry->hdev); if (ctx) { @@ -1583,209 +1583,216 @@ static const struct file_operations hl_debugfs_fops = { .release = single_release, }; -static void add_secured_nodes(struct hl_dbg_device_entry *dev_entry) +static void add_secured_nodes(struct hl_dbg_device_entry *dev_entry, struct dentry *root) { debugfs_create_u8("i2c_bus", 0644, - dev_entry->root, + root, &dev_entry->i2c_bus); debugfs_create_u8("i2c_addr", 0644, - dev_entry->root, + root, &dev_entry->i2c_addr); debugfs_create_u8("i2c_reg", 0644, - dev_entry->root, + root, &dev_entry->i2c_reg); debugfs_create_u8("i2c_len", 0644, - dev_entry->root, + root, &dev_entry->i2c_len); debugfs_create_file("i2c_data", 0644, - dev_entry->root, + root, dev_entry, &hl_i2c_data_fops); debugfs_create_file("led0", 0200, - dev_entry->root, + root, dev_entry, &hl_led0_fops); debugfs_create_file("led1", 0200, - dev_entry->root, + root, dev_entry, &hl_led1_fops); debugfs_create_file("led2", 0200, - dev_entry->root, + root, dev_entry, &hl_led2_fops); } -void hl_debugfs_add_device(struct hl_device *hdev) +static void add_files_to_device(struct hl_device *hdev, struct hl_dbg_device_entry *dev_entry, + struct dentry *root) { - struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; int count = ARRAY_SIZE(hl_debugfs_list); struct hl_debugfs_entry *entry; int i; - dev_entry->hdev = hdev; - dev_entry->entry_arr = kmalloc_array(count, - sizeof(struct hl_debugfs_entry), - GFP_KERNEL); - if (!dev_entry->entry_arr) - return; - - dev_entry->data_dma_blob_desc.size = 0; - dev_entry->data_dma_blob_desc.data = NULL; - dev_entry->mon_dump_blob_desc.size = 0; - dev_entry->mon_dump_blob_desc.data = NULL; - - INIT_LIST_HEAD(&dev_entry->file_list); - INIT_LIST_HEAD(&dev_entry->cb_list); - INIT_LIST_HEAD(&dev_entry->cs_list); - INIT_LIST_HEAD(&dev_entry->cs_job_list); - INIT_LIST_HEAD(&dev_entry->userptr_list); - INIT_LIST_HEAD(&dev_entry->ctx_mem_hash_list); - mutex_init(&dev_entry->file_mutex); - init_rwsem(&dev_entry->state_dump_sem); - spin_lock_init(&dev_entry->cb_spinlock); - spin_lock_init(&dev_entry->cs_spinlock); - spin_lock_init(&dev_entry->cs_job_spinlock); - spin_lock_init(&dev_entry->userptr_spinlock); - spin_lock_init(&dev_entry->ctx_mem_hash_spinlock); - - dev_entry->root = debugfs_create_dir(dev_name(hdev->dev), - hl_debug_root); - debugfs_create_x64("memory_scrub_val", 0644, - dev_entry->root, + root, &hdev->memory_scrub_val); debugfs_create_file("memory_scrub", 0200, - dev_entry->root, + root, dev_entry, &hl_mem_scrub_fops); debugfs_create_x64("addr", 0644, - dev_entry->root, + root, &dev_entry->addr); debugfs_create_file("data32", 0644, - dev_entry->root, + root, dev_entry, &hl_data32b_fops); debugfs_create_file("data64", 0644, - dev_entry->root, + root, dev_entry, &hl_data64b_fops); debugfs_create_file("set_power_state", 0200, - dev_entry->root, + root, dev_entry, &hl_power_fops); debugfs_create_file("device", 0200, - dev_entry->root, + root, dev_entry, &hl_device_fops); debugfs_create_file("clk_gate", 0200, - dev_entry->root, + root, dev_entry, &hl_clk_gate_fops); debugfs_create_file("stop_on_err", 0644, - dev_entry->root, + root, dev_entry, &hl_stop_on_err_fops); debugfs_create_file("dump_security_violations", 0644, - dev_entry->root, + root, dev_entry, &hl_security_violations_fops); debugfs_create_file("dump_razwi_events", 0644, - dev_entry->root, + root, dev_entry, &hl_razwi_check_fops); debugfs_create_file("dma_size", 0200, - dev_entry->root, + root, dev_entry, &hl_dma_size_fops); debugfs_create_blob("data_dma", 0400, - dev_entry->root, + root, &dev_entry->data_dma_blob_desc); debugfs_create_file("monitor_dump_trig", 0200, - dev_entry->root, + root, dev_entry, &hl_monitor_dump_fops); debugfs_create_blob("monitor_dump", 0400, - dev_entry->root, + root, &dev_entry->mon_dump_blob_desc); debugfs_create_x8("skip_reset_on_timeout", 0644, - dev_entry->root, + root, &hdev->reset_info.skip_reset_on_timeout); debugfs_create_file("state_dump", 0600, - dev_entry->root, + root, dev_entry, &hl_state_dump_fops); debugfs_create_file("timeout_locked", 0644, - dev_entry->root, + root, dev_entry, &hl_timeout_locked_fops); debugfs_create_u32("device_release_watchdog_timeout", 0644, - dev_entry->root, + root, &hdev->device_release_watchdog_timeout_sec); for (i = 0, entry = dev_entry->entry_arr ; i < count ; i++, entry++) { debugfs_create_file(hl_debugfs_list[i].name, 0444, - dev_entry->root, + root, entry, &hl_debugfs_fops); entry->info_ent = &hl_debugfs_list[i]; entry->dev_entry = dev_entry; } +} + +void hl_debugfs_add_device(struct hl_device *hdev) +{ + struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; + int count = ARRAY_SIZE(hl_debugfs_list); + + dev_entry->hdev = hdev; + dev_entry->entry_arr = kmalloc_array(count, + sizeof(struct hl_debugfs_entry), + GFP_KERNEL); + if (!dev_entry->entry_arr) + return; + + dev_entry->data_dma_blob_desc.size = 0; + dev_entry->data_dma_blob_desc.data = NULL; + dev_entry->mon_dump_blob_desc.size = 0; + dev_entry->mon_dump_blob_desc.data = NULL; + + INIT_LIST_HEAD(&dev_entry->file_list); + INIT_LIST_HEAD(&dev_entry->cb_list); + INIT_LIST_HEAD(&dev_entry->cs_list); + INIT_LIST_HEAD(&dev_entry->cs_job_list); + INIT_LIST_HEAD(&dev_entry->userptr_list); + INIT_LIST_HEAD(&dev_entry->ctx_mem_hash_list); + mutex_init(&dev_entry->file_mutex); + init_rwsem(&dev_entry->state_dump_sem); + spin_lock_init(&dev_entry->cb_spinlock); + spin_lock_init(&dev_entry->cs_spinlock); + spin_lock_init(&dev_entry->cs_job_spinlock); + spin_lock_init(&dev_entry->userptr_spinlock); + mutex_init(&dev_entry->ctx_mem_hash_mutex); + + dev_entry->root = debugfs_create_dir(dev_name(hdev->dev), + hl_debug_root); + add_files_to_device(hdev, dev_entry, dev_entry->root); if (!hdev->asic_prop.fw_security_enabled) - add_secured_nodes(dev_entry); + add_secured_nodes(dev_entry, dev_entry->root); } void hl_debugfs_remove_device(struct hl_device *hdev) @@ -1795,6 +1802,7 @@ void hl_debugfs_remove_device(struct hl_device *hdev) debugfs_remove_recursive(entry->root); + mutex_destroy(&entry->ctx_mem_hash_mutex); mutex_destroy(&entry->file_mutex); vfree(entry->data_dma_blob_desc.data); @@ -1901,18 +1909,18 @@ void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx) { struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; - spin_lock(&dev_entry->ctx_mem_hash_spinlock); + mutex_lock(&dev_entry->ctx_mem_hash_mutex); list_add(&ctx->debugfs_list, &dev_entry->ctx_mem_hash_list); - spin_unlock(&dev_entry->ctx_mem_hash_spinlock); + mutex_unlock(&dev_entry->ctx_mem_hash_mutex); } void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx) { struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs; - spin_lock(&dev_entry->ctx_mem_hash_spinlock); + mutex_lock(&dev_entry->ctx_mem_hash_mutex); list_del(&ctx->debugfs_list); - spin_unlock(&dev_entry->ctx_mem_hash_spinlock); + mutex_unlock(&dev_entry->ctx_mem_hash_mutex); } /** diff --git a/drivers/accel/habanalabs/common/decoder.c b/drivers/accel/habanalabs/common/decoder.c index 2aab14d74b53..69c78c1784b4 100644 --- a/drivers/accel/habanalabs/common/decoder.c +++ b/drivers/accel/habanalabs/common/decoder.c @@ -46,7 +46,7 @@ static void dec_print_abnrm_intr_source(struct hl_device *hdev, u32 irq_status) static void dec_error_intr_work(struct hl_device *hdev, u32 base_addr, u32 core_id) { bool reset_required = false; - u32 irq_status; + u32 irq_status, event_mask; irq_status = RREG32(base_addr + VCMD_IRQ_STATUS_OFFSET); @@ -54,17 +54,27 @@ static void dec_error_intr_work(struct hl_device *hdev, u32 base_addr, u32 core_ dec_print_abnrm_intr_source(hdev, irq_status); - if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK) - reset_required = true; - /* Clear the interrupt */ WREG32(base_addr + VCMD_IRQ_STATUS_OFFSET, irq_status); /* Flush the interrupt clear */ RREG32(base_addr + VCMD_IRQ_STATUS_OFFSET); - if (reset_required) - hl_device_reset(hdev, HL_DRV_RESET_HARD); + if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK) { + reset_required = true; + event_mask = HL_NOTIFIER_EVENT_GENERAL_HW_ERR; + } else if (irq_status & VCMD_IRQ_STATUS_CMDERR_MASK) { + event_mask = HL_NOTIFIER_EVENT_UNDEFINED_OPCODE; + } else { + event_mask = HL_NOTIFIER_EVENT_USER_ENGINE_ERR; + } + + if (reset_required) { + event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET; + hl_device_cond_reset(hdev, 0, event_mask); + } else { + hl_notifier_event_send_all(hdev, event_mask); + } } static void dec_completion_abnrm(struct work_struct *work) diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c index 9933e5858a36..713005998cbc 100644 --- a/drivers/accel/habanalabs/common/device.c +++ b/drivers/accel/habanalabs/common/device.c @@ -22,7 +22,6 @@ enum dma_alloc_type { DMA_ALLOC_COHERENT, - DMA_ALLOC_CPU_ACCESSIBLE, DMA_ALLOC_POOL, }; @@ -121,9 +120,6 @@ static void *hl_dma_alloc_common(struct hl_device *hdev, size_t size, dma_addr_t case DMA_ALLOC_COHERENT: ptr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, size, dma_handle, flag); break; - case DMA_ALLOC_CPU_ACCESSIBLE: - ptr = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, size, dma_handle); - break; case DMA_ALLOC_POOL: ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, size, flag, dma_handle); break; @@ -147,9 +143,6 @@ static void hl_asic_dma_free_common(struct hl_device *hdev, size_t size, void *c case DMA_ALLOC_COHERENT: hdev->asic_funcs->asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle); break; - case DMA_ALLOC_CPU_ACCESSIBLE: - hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, size, cpu_addr); - break; case DMA_ALLOC_POOL: hdev->asic_funcs->asic_dma_pool_free(hdev, cpu_addr, dma_handle); break; @@ -170,18 +163,6 @@ void hl_asic_dma_free_coherent_caller(struct hl_device *hdev, size_t size, void hl_asic_dma_free_common(hdev, size, cpu_addr, dma_handle, DMA_ALLOC_COHERENT, caller); } -void *hl_cpu_accessible_dma_pool_alloc_caller(struct hl_device *hdev, size_t size, - dma_addr_t *dma_handle, const char *caller) -{ - return hl_dma_alloc_common(hdev, size, dma_handle, 0, DMA_ALLOC_CPU_ACCESSIBLE, caller); -} - -void hl_cpu_accessible_dma_pool_free_caller(struct hl_device *hdev, size_t size, void *vaddr, - const char *caller) -{ - hl_asic_dma_free_common(hdev, size, vaddr, 0, DMA_ALLOC_CPU_ACCESSIBLE, caller); -} - void *hl_asic_dma_pool_zalloc_caller(struct hl_device *hdev, size_t size, gfp_t mem_flags, dma_addr_t *dma_handle, const char *caller) { @@ -194,6 +175,16 @@ void hl_asic_dma_pool_free_caller(struct hl_device *hdev, void *vaddr, dma_addr_ hl_asic_dma_free_common(hdev, 0, vaddr, dma_addr, DMA_ALLOC_POOL, caller); } +void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle) +{ + return hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, size, dma_handle); +} + +void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr) +{ + hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, size, vaddr); +} + int hl_dma_map_sgtable(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir) { struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -389,18 +380,17 @@ bool hl_ctrl_device_operational(struct hl_device *hdev, static void print_idle_status_mask(struct hl_device *hdev, const char *message, u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE]) { - u32 pad_width[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {}; - - BUILD_BUG_ON(HL_BUSY_ENGINES_MASK_EXT_SIZE != 4); - - pad_width[3] = idle_mask[3] ? 16 : 0; - pad_width[2] = idle_mask[2] || pad_width[3] ? 16 : 0; - pad_width[1] = idle_mask[1] || pad_width[2] ? 16 : 0; - pad_width[0] = idle_mask[0] || pad_width[1] ? 16 : 0; - - dev_err(hdev->dev, "%s (mask %0*llx_%0*llx_%0*llx_%0*llx)\n", - message, pad_width[3], idle_mask[3], pad_width[2], idle_mask[2], - pad_width[1], idle_mask[1], pad_width[0], idle_mask[0]); + if (idle_mask[3]) + dev_err(hdev->dev, "%s (mask %#llx_%016llx_%016llx_%016llx)\n", + message, idle_mask[3], idle_mask[2], idle_mask[1], idle_mask[0]); + else if (idle_mask[2]) + dev_err(hdev->dev, "%s (mask %#llx_%016llx_%016llx)\n", + message, idle_mask[2], idle_mask[1], idle_mask[0]); + else if (idle_mask[1]) + dev_err(hdev->dev, "%s (mask %#llx_%016llx)\n", + message, idle_mask[1], idle_mask[0]); + else + dev_err(hdev->dev, "%s (mask %#llx)\n", message, idle_mask[0]); } static void hpriv_release(struct kref *ref) @@ -423,6 +413,9 @@ static void hpriv_release(struct kref *ref) mutex_destroy(&hpriv->ctx_lock); mutex_destroy(&hpriv->restore_phase_mutex); + /* There should be no memory buffers at this point and handles IDR can be destroyed */ + hl_mem_mgr_idr_destroy(&hpriv->mem_mgr); + /* Device should be reset if reset-upon-device-release is enabled, or if there is a pending * reset that waits for device release. */ @@ -492,6 +485,36 @@ int hl_hpriv_put(struct hl_fpriv *hpriv) return kref_put(&hpriv->refcount, hpriv_release); } +static void print_device_in_use_info(struct hl_device *hdev, const char *message) +{ + u32 active_cs_num, dmabuf_export_cnt; + bool unknown_reason = true; + char buf[128]; + size_t size; + int offset; + + size = sizeof(buf); + offset = 0; + + active_cs_num = hl_get_active_cs_num(hdev); + if (active_cs_num) { + unknown_reason = false; + offset += scnprintf(buf + offset, size - offset, " [%u active CS]", active_cs_num); + } + + dmabuf_export_cnt = atomic_read(&hdev->dmabuf_export_cnt); + if (dmabuf_export_cnt) { + unknown_reason = false; + offset += scnprintf(buf + offset, size - offset, " [%u exported dma-buf]", + dmabuf_export_cnt); + } + + if (unknown_reason) + scnprintf(buf + offset, size - offset, " [unknown reason]"); + + dev_notice(hdev->dev, "%s%s\n", message, buf); +} + /* * hl_device_release - release function for habanalabs device * @@ -514,17 +537,20 @@ static int hl_device_release(struct inode *inode, struct file *filp) } hl_ctx_mgr_fini(hdev, &hpriv->ctx_mgr); + + /* Memory buffers might be still in use at this point and thus the handles IDR destruction + * is postponed to hpriv_release(). + */ hl_mem_mgr_fini(&hpriv->mem_mgr); hdev->compute_ctx_in_release = 1; if (!hl_hpriv_put(hpriv)) { - dev_notice(hdev->dev, "User process closed FD but device still in use\n"); + print_device_in_use_info(hdev, "User process closed FD but device still in use"); hl_device_reset(hdev, HL_DRV_RESET_HARD); } - hdev->last_open_session_duration_jif = - jiffies - hdev->last_successful_open_jif; + hdev->last_open_session_duration_jif = jiffies - hdev->last_successful_open_jif; return 0; } @@ -617,7 +643,7 @@ static void device_release_func(struct device *dev) * device_init_cdev - Initialize cdev and device for habanalabs device * * @hdev: pointer to habanalabs device structure - * @hclass: pointer to the class object of the device + * @class: pointer to the class object of the device * @minor: minor number of the specific device * @fpos: file operations to install for this device * @name: name of the device as it will appear in the filesystem @@ -626,7 +652,7 @@ static void device_release_func(struct device *dev) * * Initialize a cdev and a Linux device for habanalabs's device. */ -static int device_init_cdev(struct hl_device *hdev, struct class *hclass, +static int device_init_cdev(struct hl_device *hdev, struct class *class, int minor, const struct file_operations *fops, char *name, struct cdev *cdev, struct device **dev) @@ -640,7 +666,7 @@ static int device_init_cdev(struct hl_device *hdev, struct class *hclass, device_initialize(*dev); (*dev)->devt = MKDEV(hdev->major, minor); - (*dev)->class = hclass; + (*dev)->class = class; (*dev)->release = device_release_func; dev_set_drvdata(*dev, hdev); dev_set_name(*dev, "%s", name); @@ -733,14 +759,14 @@ static void device_hard_reset_pending(struct work_struct *work) static void device_release_watchdog_func(struct work_struct *work) { - struct hl_device_reset_work *device_release_watchdog_work = - container_of(work, struct hl_device_reset_work, reset_work.work); - struct hl_device *hdev = device_release_watchdog_work->hdev; + struct hl_device_reset_work *watchdog_work = + container_of(work, struct hl_device_reset_work, reset_work.work); + struct hl_device *hdev = watchdog_work->hdev; u32 flags; - dev_dbg(hdev->dev, "Device wasn't released in time. Initiate device reset.\n"); + dev_dbg(hdev->dev, "Device wasn't released in time. Initiate hard-reset.\n"); - flags = device_release_watchdog_work->flags | HL_DRV_RESET_FROM_WD_THR; + flags = watchdog_work->flags | HL_DRV_RESET_HARD | HL_DRV_RESET_FROM_WD_THR; hl_device_reset(hdev, flags); } @@ -805,7 +831,7 @@ static int device_early_init(struct hl_device *hdev) } for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) { - snprintf(workq_name, 32, "hl-free-jobs-%u", (u32) i); + snprintf(workq_name, 32, "hl%u-free-jobs-%u", hdev->cdev_idx, (u32) i); hdev->cq_wq[i] = create_singlethread_workqueue(workq_name); if (hdev->cq_wq[i] == NULL) { dev_err(hdev->dev, "Failed to allocate CQ workqueue\n"); @@ -814,14 +840,16 @@ static int device_early_init(struct hl_device *hdev) } } - hdev->eq_wq = create_singlethread_workqueue("hl-events"); + snprintf(workq_name, 32, "hl%u-events", hdev->cdev_idx); + hdev->eq_wq = create_singlethread_workqueue(workq_name); if (hdev->eq_wq == NULL) { dev_err(hdev->dev, "Failed to allocate EQ workqueue\n"); rc = -ENOMEM; goto free_cq_wq; } - hdev->cs_cmplt_wq = alloc_workqueue("hl-cs-completions", WQ_UNBOUND, 0); + snprintf(workq_name, 32, "hl%u-cs-completions", hdev->cdev_idx); + hdev->cs_cmplt_wq = alloc_workqueue(workq_name, WQ_UNBOUND, 0); if (!hdev->cs_cmplt_wq) { dev_err(hdev->dev, "Failed to allocate CS completions workqueue\n"); @@ -829,7 +857,8 @@ static int device_early_init(struct hl_device *hdev) goto free_eq_wq; } - hdev->ts_free_obj_wq = alloc_workqueue("hl-ts-free-obj", WQ_UNBOUND, 0); + snprintf(workq_name, 32, "hl%u-ts-free-obj", hdev->cdev_idx); + hdev->ts_free_obj_wq = alloc_workqueue(workq_name, WQ_UNBOUND, 0); if (!hdev->ts_free_obj_wq) { dev_err(hdev->dev, "Failed to allocate Timestamp registration free workqueue\n"); @@ -837,15 +866,15 @@ static int device_early_init(struct hl_device *hdev) goto free_cs_cmplt_wq; } - hdev->prefetch_wq = alloc_workqueue("hl-prefetch", WQ_UNBOUND, 0); + snprintf(workq_name, 32, "hl%u-prefetch", hdev->cdev_idx); + hdev->prefetch_wq = alloc_workqueue(workq_name, WQ_UNBOUND, 0); if (!hdev->prefetch_wq) { dev_err(hdev->dev, "Failed to allocate MMU prefetch workqueue\n"); rc = -ENOMEM; goto free_ts_free_wq; } - hdev->hl_chip_info = kzalloc(sizeof(struct hwmon_chip_info), - GFP_KERNEL); + hdev->hl_chip_info = kzalloc(sizeof(struct hwmon_chip_info), GFP_KERNEL); if (!hdev->hl_chip_info) { rc = -ENOMEM; goto free_prefetch_wq; @@ -857,7 +886,8 @@ static int device_early_init(struct hl_device *hdev) hl_mem_mgr_init(hdev->dev, &hdev->kernel_mem_mgr); - hdev->reset_wq = create_singlethread_workqueue("hl_device_reset"); + snprintf(workq_name, 32, "hl%u_device_reset", hdev->cdev_idx); + hdev->reset_wq = create_singlethread_workqueue(workq_name); if (!hdev->reset_wq) { rc = -ENOMEM; dev_err(hdev->dev, "Failed to create device reset WQ\n"); @@ -887,6 +917,7 @@ static int device_early_init(struct hl_device *hdev) free_cb_mgr: hl_mem_mgr_fini(&hdev->kernel_mem_mgr); + hl_mem_mgr_idr_destroy(&hdev->kernel_mem_mgr); free_chip_info: kfree(hdev->hl_chip_info); free_prefetch_wq: @@ -930,6 +961,7 @@ static void device_early_fini(struct hl_device *hdev) mutex_destroy(&hdev->clk_throttling.lock); hl_mem_mgr_fini(&hdev->kernel_mem_mgr); + hl_mem_mgr_idr_destroy(&hdev->kernel_mem_mgr); kfree(hdev->hl_chip_info); @@ -953,6 +985,8 @@ static void hl_device_heartbeat(struct work_struct *work) { struct hl_device *hdev = container_of(work, struct hl_device, work_heartbeat.work); + struct hl_info_fw_err_info info = {0}; + u64 event_mask = HL_NOTIFIER_EVENT_DEVICE_RESET | HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE; if (!hl_device_operational(hdev, NULL)) goto reschedule; @@ -963,7 +997,10 @@ static void hl_device_heartbeat(struct work_struct *work) if (hl_device_operational(hdev, NULL)) dev_err(hdev->dev, "Device heartbeat failed!\n"); - hl_device_reset(hdev, HL_DRV_RESET_HARD | HL_DRV_RESET_HEARTBEAT); + info.err_type = HL_INFO_FW_HEARTBEAT_ERR; + info.event_mask = &event_mask; + hl_handle_fw_err(hdev, &info); + hl_device_cond_reset(hdev, HL_DRV_RESET_HARD | HL_DRV_RESET_HEARTBEAT, event_mask); return; @@ -1402,7 +1439,7 @@ static void handle_reset_trigger(struct hl_device *hdev, u32 flags) */ if (hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0)) dev_warn(hdev->dev, - "Failed to disable PCI access by F/W\n"); + "Failed to disable FW's PCI access\n"); } } @@ -1424,12 +1461,11 @@ static void handle_reset_trigger(struct hl_device *hdev, u32 flags) */ int hl_device_reset(struct hl_device *hdev, u32 flags) { - bool hard_reset, from_hard_reset_thread, fw_reset, hard_instead_soft = false, - reset_upon_device_release = false, schedule_hard_reset = false, - delay_reset, from_dev_release, from_watchdog_thread; + bool hard_reset, from_hard_reset_thread, fw_reset, reset_upon_device_release, + schedule_hard_reset = false, delay_reset, from_dev_release, from_watchdog_thread; u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {0}; struct hl_ctx *ctx; - int i, rc; + int i, rc, hw_fini_rc; if (!hdev->init_done) { dev_err(hdev->dev, "Can't reset before initialization is done\n"); @@ -1442,6 +1478,7 @@ int hl_device_reset(struct hl_device *hdev, u32 flags) from_dev_release = !!(flags & HL_DRV_RESET_DEV_RELEASE); delay_reset = !!(flags & HL_DRV_RESET_DELAY); from_watchdog_thread = !!(flags & HL_DRV_RESET_FROM_WD_THR); + reset_upon_device_release = hdev->reset_upon_device_release && from_dev_release; if (!hard_reset && (hl_device_status(hdev) == HL_DEVICE_STATUS_MALFUNCTION)) { dev_dbg(hdev->dev, "soft-reset isn't supported on a malfunctioning device\n"); @@ -1449,30 +1486,26 @@ int hl_device_reset(struct hl_device *hdev, u32 flags) } if (!hard_reset && !hdev->asic_prop.supports_compute_reset) { - hard_instead_soft = true; + dev_dbg(hdev->dev, "asic doesn't support compute reset - do hard-reset instead\n"); hard_reset = true; } - if (hdev->reset_upon_device_release && from_dev_release) { + if (reset_upon_device_release) { if (hard_reset) { dev_crit(hdev->dev, "Aborting reset because hard-reset is mutually exclusive with reset-on-device-release\n"); return -EINVAL; } - reset_upon_device_release = true; - goto do_reset; } if (!hard_reset && !hdev->asic_prop.allow_inference_soft_reset) { - hard_instead_soft = true; + dev_dbg(hdev->dev, + "asic doesn't allow inference soft reset - do hard-reset instead\n"); hard_reset = true; } - if (hard_instead_soft) - dev_dbg(hdev->dev, "Doing hard-reset instead of compute reset\n"); - do_reset: /* Re-entry of reset thread */ if (from_hard_reset_thread && hdev->process_kill_trial_cnt) @@ -1480,14 +1513,14 @@ do_reset: /* * Prevent concurrency in this function - only one reset should be - * done at any given time. Only need to perform this if we didn't - * get from the dedicated hard reset thread + * done at any given time. We need to perform this only if we didn't + * get here from a dedicated hard reset thread. */ if (!from_hard_reset_thread) { /* Block future CS/VM/JOB completion operations */ spin_lock(&hdev->reset_info.lock); if (hdev->reset_info.in_reset) { - /* We only allow scheduling of a hard reset during compute reset */ + /* We allow scheduling of a hard reset only during a compute reset */ if (hard_reset && hdev->reset_info.in_compute_reset) hdev->reset_info.hard_reset_schedule_flags = flags; spin_unlock(&hdev->reset_info.lock); @@ -1505,15 +1538,17 @@ do_reset: /* Cancel the device release watchdog work if required. * In case of reset-upon-device-release while the release watchdog work is - * scheduled, do hard-reset instead of compute-reset. + * scheduled due to a hard-reset, do hard-reset instead of compute-reset. */ if ((hard_reset || from_dev_release) && hdev->reset_info.watchdog_active) { + struct hl_device_reset_work *watchdog_work = + &hdev->device_release_watchdog_work; + hdev->reset_info.watchdog_active = 0; if (!from_watchdog_thread) - cancel_delayed_work_sync( - &hdev->device_release_watchdog_work.reset_work); + cancel_delayed_work_sync(&watchdog_work->reset_work); - if (from_dev_release) { + if (from_dev_release && (watchdog_work->flags & HL_DRV_RESET_HARD)) { hdev->reset_info.in_compute_reset = 0; flags |= HL_DRV_RESET_HARD; flags &= ~HL_DRV_RESET_DEV_RELEASE; @@ -1524,6 +1559,7 @@ do_reset: if (delay_reset) usleep_range(HL_RESET_DELAY_USEC, HL_RESET_DELAY_USEC << 1); +escalate_reset_flow: handle_reset_trigger(hdev, flags); /* This also blocks future CS/VM/JOB completion operations */ @@ -1539,7 +1575,6 @@ do_reset: dev_dbg(hdev->dev, "Going to reset engines of inference device\n"); } -again: if ((hard_reset) && (!from_hard_reset_thread)) { hdev->reset_info.hard_reset_pending = true; @@ -1592,7 +1627,7 @@ kill_processes: } /* Reset the H/W. It will be in idle state after this returns */ - hdev->asic_funcs->hw_fini(hdev, hard_reset, fw_reset); + hw_fini_rc = hdev->asic_funcs->hw_fini(hdev, hard_reset, fw_reset); if (hard_reset) { hdev->fw_loader.fw_comp_loaded = FW_TYPE_NONE; @@ -1619,6 +1654,10 @@ kill_processes: hl_ctx_put(ctx); } + if (hw_fini_rc) { + rc = hw_fini_rc; + goto out_err; + } /* Finished tear-down, starting to re-initialize */ if (hard_reset) { @@ -1787,7 +1826,7 @@ kill_processes: hdev->disabled = true; hard_reset = true; handle_reset_trigger(hdev, flags); - goto again; + goto escalate_reset_flow; } } @@ -1804,20 +1843,19 @@ out_err: "%s Failed to reset! Device is NOT usable\n", dev_name(&(hdev)->pdev->dev)); hdev->reset_info.hard_reset_cnt++; - } else if (reset_upon_device_release) { - spin_unlock(&hdev->reset_info.lock); - dev_err(hdev->dev, "Failed to reset device after user release\n"); - flags |= HL_DRV_RESET_HARD; - flags &= ~HL_DRV_RESET_DEV_RELEASE; - hard_reset = true; - goto again; } else { + if (reset_upon_device_release) { + dev_err(hdev->dev, "Failed to reset device after user release\n"); + flags &= ~HL_DRV_RESET_DEV_RELEASE; + } else { + dev_err(hdev->dev, "Failed to do compute reset\n"); + hdev->reset_info.compute_reset_cnt++; + } + spin_unlock(&hdev->reset_info.lock); - dev_err(hdev->dev, "Failed to do compute reset\n"); - hdev->reset_info.compute_reset_cnt++; flags |= HL_DRV_RESET_HARD; hard_reset = true; - goto again; + goto escalate_reset_flow; } hdev->reset_info.in_reset = 0; @@ -1840,10 +1878,6 @@ int hl_device_cond_reset(struct hl_device *hdev, u32 flags, u64 event_mask) { struct hl_ctx *ctx = NULL; - /* Device release watchdog is only for hard reset */ - if (!(flags & HL_DRV_RESET_HARD) && hdev->asic_prop.allow_inference_soft_reset) - goto device_reset; - /* F/W reset cannot be postponed */ if (flags & HL_DRV_RESET_BYPASS_REQ_TO_FW) goto device_reset; @@ -1871,7 +1905,7 @@ int hl_device_cond_reset(struct hl_device *hdev, u32 flags, u64 event_mask) goto out; hdev->device_release_watchdog_work.flags = flags; - dev_dbg(hdev->dev, "Device is going to be reset in %u sec unless being released\n", + dev_dbg(hdev->dev, "Device is going to be hard-reset in %u sec unless being released\n", hdev->device_release_watchdog_timeout_sec); schedule_delayed_work(&hdev->device_release_watchdog_work.reset_work, msecs_to_jiffies(hdev->device_release_watchdog_timeout_sec * 1000)); @@ -1939,37 +1973,27 @@ void hl_notifier_event_send_all(struct hl_device *hdev, u64 event_mask) mutex_unlock(&hdev->fpriv_ctrl_list_lock); } -/* - * hl_device_init - main initialization function for habanalabs device - * - * @hdev: pointer to habanalabs device structure - * - * Allocate an id for the device, do early initialization and then call the - * ASIC specific initialization functions. Finally, create the cdev and the - * Linux device to expose it to the user - */ -int hl_device_init(struct hl_device *hdev, struct class *hclass) +static int create_cdev(struct hl_device *hdev) { - int i, rc, cq_cnt, user_interrupt_cnt, cq_ready_cnt; char *name; - bool add_cdev_sysfs_on_err = false; + int rc; hdev->cdev_idx = hdev->id / 2; name = kasprintf(GFP_KERNEL, "hl%d", hdev->cdev_idx); if (!name) { rc = -ENOMEM; - goto out_disabled; + goto out_err; } /* Initialize cdev and device structures */ - rc = device_init_cdev(hdev, hclass, hdev->id, &hl_ops, name, + rc = device_init_cdev(hdev, hdev->hclass, hdev->id, &hl_ops, name, &hdev->cdev, &hdev->dev); kfree(name); if (rc) - goto out_disabled; + goto out_err; name = kasprintf(GFP_KERNEL, "hl_controlD%d", hdev->cdev_idx); if (!name) { @@ -1978,7 +2002,7 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) } /* Initialize cdev and device structures for control device */ - rc = device_init_cdev(hdev, hclass, hdev->id_control, &hl_ctrl_ops, + rc = device_init_cdev(hdev, hdev->hclass, hdev->id_control, &hl_ctrl_ops, name, &hdev->cdev_ctrl, &hdev->dev_ctrl); kfree(name); @@ -1986,10 +2010,36 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) if (rc) goto free_dev; + return 0; + +free_dev: + put_device(hdev->dev); +out_err: + return rc; +} + +/* + * hl_device_init - main initialization function for habanalabs device + * + * @hdev: pointer to habanalabs device structure + * + * Allocate an id for the device, do early initialization and then call the + * ASIC specific initialization functions. Finally, create the cdev and the + * Linux device to expose it to the user + */ +int hl_device_init(struct hl_device *hdev) +{ + int i, rc, cq_cnt, user_interrupt_cnt, cq_ready_cnt; + bool add_cdev_sysfs_on_err = false; + + rc = create_cdev(hdev); + if (rc) + goto out_disabled; + /* Initialize ASIC function pointers and perform early init */ rc = device_early_init(hdev); if (rc) - goto free_dev_ctrl; + goto free_dev; user_interrupt_cnt = hdev->asic_prop.user_dec_intr_count + hdev->asic_prop.user_interrupt_count; @@ -2241,9 +2291,8 @@ free_usr_intr_mem: kfree(hdev->user_interrupt); early_fini: device_early_fini(hdev); -free_dev_ctrl: - put_device(hdev->dev_ctrl); free_dev: + put_device(hdev->dev_ctrl); put_device(hdev->dev); out_disabled: hdev->disabled = true; @@ -2364,7 +2413,9 @@ void hl_device_fini(struct hl_device *hdev) hl_cb_pool_fini(hdev); /* Reset the H/W. It will be in idle state after this returns */ - hdev->asic_funcs->hw_fini(hdev, true, false); + rc = hdev->asic_funcs->hw_fini(hdev, true, false); + if (rc) + dev_err(hdev->dev, "hw_fini failed in device fini while removing device %d\n", rc); hdev->fw_loader.fw_comp_loaded = FW_TYPE_NONE; @@ -2566,3 +2617,49 @@ void hl_handle_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_ if (event_mask) *event_mask |= HL_NOTIFIER_EVENT_PAGE_FAULT; } + +static void hl_capture_hw_err(struct hl_device *hdev, u16 event_id) +{ + struct hw_err_info *info = &hdev->captured_err_info.hw_err; + + /* Capture only the first HW err */ + if (atomic_cmpxchg(&info->event_detected, 0, 1)) + return; + + info->event.timestamp = ktime_to_ns(ktime_get()); + info->event.event_id = event_id; + + info->event_info_available = true; +} + +void hl_handle_critical_hw_err(struct hl_device *hdev, u16 event_id, u64 *event_mask) +{ + hl_capture_hw_err(hdev, event_id); + + if (event_mask) + *event_mask |= HL_NOTIFIER_EVENT_CRITICL_HW_ERR; +} + +static void hl_capture_fw_err(struct hl_device *hdev, struct hl_info_fw_err_info *fw_info) +{ + struct fw_err_info *info = &hdev->captured_err_info.fw_err; + + /* Capture only the first FW error */ + if (atomic_cmpxchg(&info->event_detected, 0, 1)) + return; + + info->event.timestamp = ktime_to_ns(ktime_get()); + info->event.err_type = fw_info->err_type; + if (fw_info->err_type == HL_INFO_FW_REPORTED_ERR) + info->event.event_id = fw_info->event_id; + + info->event_info_available = true; +} + +void hl_handle_fw_err(struct hl_device *hdev, struct hl_info_fw_err_info *info) +{ + hl_capture_fw_err(hdev, info); + + if (info->event_mask) + *info->event_mask |= HL_NOTIFIER_EVENT_CRITICL_FW_ERR; +} diff --git a/drivers/accel/habanalabs/common/firmware_if.c b/drivers/accel/habanalabs/common/firmware_if.c index da892d8fb3d6..7ea611392f8c 100644 --- a/drivers/accel/habanalabs/common/firmware_if.c +++ b/drivers/accel/habanalabs/common/firmware_if.c @@ -3152,7 +3152,7 @@ int hl_fw_get_sec_attest_info(struct hl_device *hdev, struct cpucp_sec_attest_in int hl_fw_send_generic_request(struct hl_device *hdev, enum hl_passthrough_type sub_opcode, dma_addr_t buff, u32 *size) { - struct cpucp_packet pkt = {0}; + struct cpucp_packet pkt = {}; u64 result; int rc = 0; diff --git a/drivers/accel/habanalabs/common/habanalabs.h b/drivers/accel/habanalabs/common/habanalabs.h index fa05e76d3d21..a6f5c2152b0a 100644 --- a/drivers/accel/habanalabs/common/habanalabs.h +++ b/drivers/accel/habanalabs/common/habanalabs.h @@ -155,18 +155,12 @@ enum hl_mmu_enablement { #define hl_asic_dma_alloc_coherent(hdev, size, dma_handle, flags) \ hl_asic_dma_alloc_coherent_caller(hdev, size, dma_handle, flags, __func__) -#define hl_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle) \ - hl_cpu_accessible_dma_pool_alloc_caller(hdev, size, dma_handle, __func__) - #define hl_asic_dma_pool_zalloc(hdev, size, mem_flags, dma_handle) \ hl_asic_dma_pool_zalloc_caller(hdev, size, mem_flags, dma_handle, __func__) #define hl_asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle) \ hl_asic_dma_free_coherent_caller(hdev, size, cpu_addr, dma_handle, __func__) -#define hl_cpu_accessible_dma_pool_free(hdev, size, vaddr) \ - hl_cpu_accessible_dma_pool_free_caller(hdev, size, vaddr, __func__) - #define hl_asic_dma_pool_free(hdev, vaddr, dma_addr) \ hl_asic_dma_pool_free_caller(hdev, vaddr, dma_addr, __func__) @@ -378,6 +372,7 @@ enum hl_cs_type { CS_RESERVE_SIGNALS, CS_UNRESERVE_SIGNALS, CS_TYPE_ENGINE_CORE, + CS_TYPE_ENGINES, CS_TYPE_FLUSH_PCI_HBW_WRITES, }; @@ -592,6 +587,8 @@ struct hl_hints_range { * @host_base_address: host physical start address for host DMA from device * @host_end_address: host physical end address for host DMA from device * @max_freq_value: current max clk frequency. + * @engine_core_interrupt_reg_addr: interrupt register address for engine core to use + * in order to raise events toward FW. * @clk_pll_index: clock PLL index that specify which PLL determines the clock * we display to the user * @mmu_pgt_size: MMU page tables total size. @@ -612,8 +609,8 @@ struct hl_hints_range { * @cb_pool_cb_cnt: number of CBs in the CB pool. * @cb_pool_cb_size: size of each CB in the CB pool. * @decoder_enabled_mask: which decoders are enabled. - * @decoder_binning_mask: which decoders are binned, 0 means usable and 1 - * means binned (at most one binned decoder per dcore). + * @decoder_binning_mask: which decoders are binned, 0 means usable and 1 means binned. + * @rotator_enabled_mask: which rotators are enabled. * @edma_enabled_mask: which EDMAs are enabled. * @edma_binning_mask: which EDMAs are binned, 0 means usable and 1 means * binned (at most one binned DMA). @@ -648,7 +645,8 @@ struct hl_hints_range { * which the property supports_user_set_page_size is true * (i.e. the DRAM supports multiple page sizes), otherwise * it will shall be equal to dram_page_size. - * @num_engine_cores: number of engine cpu cores + * @num_engine_cores: number of engine cpu cores. + * @max_num_of_engines: maximum number of all engines in the ASIC. * @num_of_special_blocks: special_blocks array size. * @glbl_err_cause_num: global err cause number. * @hbw_flush_reg: register to read to generate HBW flush. value of 0 means HBW flush is @@ -663,6 +661,8 @@ struct hl_hints_range { * @first_available_cq: first available CQ for the user. * @user_interrupt_count: number of user interrupts. * @user_dec_intr_count: number of decoder interrupts exposed to user. + * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host. + * @unexpected_user_error_interrupt_id: interrupt id used to indicate an unexpected user error. * @cache_line_size: device cache line size. * @server_type: Server type that the ASIC is currently installed in. * The value is according to enum hl_server_type in uapi file. @@ -698,6 +698,7 @@ struct hl_hints_range { * @supports_user_set_page_size: true if user can set the allocation page size. * @dma_mask: the dma mask to be set for this device * @supports_advanced_cpucp_rc: true if new cpucp opcodes are supported. + * @supports_engine_modes: true if changing engines/engine_cores modes is supported. */ struct asic_fixed_properties { struct hw_queue_properties *hw_queues_props; @@ -739,6 +740,7 @@ struct asic_fixed_properties { u64 host_base_address; u64 host_end_address; u64 max_freq_value; + u64 engine_core_interrupt_reg_addr; u32 clk_pll_index; u32 mmu_pgt_size; u32 mmu_pte_size; @@ -759,6 +761,7 @@ struct asic_fixed_properties { u32 cb_pool_cb_size; u32 decoder_enabled_mask; u32 decoder_binning_mask; + u32 rotator_enabled_mask; u32 edma_enabled_mask; u32 edma_binning_mask; u32 max_pending_cs; @@ -775,6 +778,7 @@ struct asic_fixed_properties { u32 xbar_edge_enabled_mask; u32 device_mem_alloc_default_page_size; u32 num_engine_cores; + u32 max_num_of_engines; u32 num_of_special_blocks; u32 glbl_err_cause_num; u32 hbw_flush_reg; @@ -788,6 +792,8 @@ struct asic_fixed_properties { u16 first_available_cq[HL_MAX_DCORES]; u16 user_interrupt_count; u16 user_dec_intr_count; + u16 tpc_interrupt_id; + u16 unexpected_user_error_interrupt_id; u16 cache_line_size; u16 server_type; u8 completion_queues_count; @@ -811,6 +817,7 @@ struct asic_fixed_properties { u8 supports_user_set_page_size; u8 dma_mask; u8 supports_advanced_cpucp_rc; + u8 supports_engine_modes; }; /** @@ -1096,6 +1103,8 @@ struct hl_cq { enum hl_user_interrupt_type { HL_USR_INTERRUPT_CQ = 0, HL_USR_INTERRUPT_DECODER, + HL_USR_INTERRUPT_TPC, + HL_USR_INTERRUPT_UNEXPECTED }; /** @@ -1104,6 +1113,7 @@ enum hl_user_interrupt_type { * @type: user interrupt type * @wait_list_head: head to the list of user threads pending on this interrupt * @wait_list_lock: protects wait_list_head + * @timestamp: last timestamp taken upon interrupt * @interrupt_id: msix interrupt id */ struct hl_user_interrupt { @@ -1111,6 +1121,7 @@ struct hl_user_interrupt { enum hl_user_interrupt_type type; struct list_head wait_list_head; spinlock_t wait_list_lock; + ktime_t timestamp; u32 interrupt_id; }; @@ -1562,6 +1573,7 @@ struct engines_data { * @access_dev_mem: access device memory * @set_dram_bar_base: set the base of the DRAM BAR * @set_engine_cores: set a config command to engine cores + * @set_engines: set a config command to user engines * @send_device_activity: indication to FW about device availability * @set_dram_properties: set DRAM related properties. * @set_binning_masks: set binning/enable masks for all relevant components. @@ -1574,7 +1586,7 @@ struct hl_asic_funcs { int (*sw_init)(struct hl_device *hdev); int (*sw_fini)(struct hl_device *hdev); int (*hw_init)(struct hl_device *hdev); - void (*hw_fini)(struct hl_device *hdev, bool hard_reset, bool fw_reset); + int (*hw_fini)(struct hl_device *hdev, bool hard_reset, bool fw_reset); void (*halt_engines)(struct hl_device *hdev, bool hard_reset, bool fw_reset); int (*suspend)(struct hl_device *hdev); int (*resume)(struct hl_device *hdev); @@ -1701,6 +1713,8 @@ struct hl_asic_funcs { u64 (*set_dram_bar_base)(struct hl_device *hdev, u64 addr); int (*set_engine_cores)(struct hl_device *hdev, u32 *core_ids, u32 num_cores, u32 core_command); + int (*set_engines)(struct hl_device *hdev, u32 *engine_ids, + u32 num_engines, u32 engine_command); int (*send_device_activity)(struct hl_device *hdev, bool open); int (*set_dram_properties)(struct hl_device *hdev); int (*set_binning_masks)(struct hl_device *hdev); @@ -1824,7 +1838,7 @@ struct hl_cs_outcome_store { * @hpriv: pointer to the private (Kernel Driver) data of the process (fd). * @hdev: pointer to the device structure. * @refcount: reference counter for the context. Context is released only when - * this hits 0l. It is incremented on CS and CS_WAIT. + * this hits 0. It is incremented on CS and CS_WAIT. * @cs_pending: array of hl fence objects representing pending CS. * @outcome_store: storage data structure used to remember outcomes of completed * command submissions for a long time after CS id wraparound. @@ -2318,7 +2332,7 @@ struct hl_debugfs_entry { * @userptr_list: list of available userptrs (virtual memory chunk descriptor). * @userptr_spinlock: protects userptr_list. * @ctx_mem_hash_list: list of available contexts with MMU mappings. - * @ctx_mem_hash_spinlock: protects cb_list. + * @ctx_mem_hash_mutex: protects list of available contexts with MMU mappings. * @data_dma_blob_desc: data DMA descriptor of blob. * @mon_dump_blob_desc: monitor dump descriptor of blob. * @state_dump: data of the system states in case of a bad cs. @@ -2349,7 +2363,7 @@ struct hl_dbg_device_entry { struct list_head userptr_list; spinlock_t userptr_spinlock; struct list_head ctx_mem_hash_list; - spinlock_t ctx_mem_hash_spinlock; + struct mutex ctx_mem_hash_mutex; struct debugfs_blob_wrapper data_dma_blob_desc; struct debugfs_blob_wrapper mon_dump_blob_desc; char *state_dump[HL_STATE_DUMP_HIST_LEN]; @@ -2974,8 +2988,8 @@ struct cs_timeout_info { * @cq_addr: the address of the current handled command buffer * @cq_size: the size of the current handled command buffer * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array. - * should be equal to 1 incase of undefined opcode - * in Upper-CP (specific stream) and equal to 4 incase + * should be equal to 1 in case of undefined opcode + * in Upper-CP (specific stream) and equal to 4 in case * of undefined opcode in Lower-CP. * @engine_id: engine-id that the error occurred on * @stream_id: the stream id the error occurred on. In case the stream equals to @@ -3032,17 +3046,55 @@ struct razwi_info { }; /** + * struct hw_err_info - HW error information. + * @event: holds information on the event. + * @event_detected: if set as 1, then a HW event was discovered for the + * first time after the driver has finished booting-up. + * currently we assume that only fatal events (that require hard-reset) are + * reported so we don't care of the others that might follow it. + * so once changed to 1, it will remain that way. + * TODO: support multiple events. + * @event_info_available: indicates that a HW event info is now available. + */ +struct hw_err_info { + struct hl_info_hw_err_event event; + atomic_t event_detected; + bool event_info_available; +}; + +/** + * struct fw_err_info - FW error information. + * @event: holds information on the event. + * @event_detected: if set as 1, then a FW event was discovered for the + * first time after the driver has finished booting-up. + * currently we assume that only fatal events (that require hard-reset) are + * reported so we don't care of the others that might follow it. + * so once changed to 1, it will remain that way. + * TODO: support multiple events. + * @event_info_available: indicates that a HW event info is now available. + */ +struct fw_err_info { + struct hl_info_fw_err_event event; + atomic_t event_detected; + bool event_info_available; +}; + +/** * struct hl_error_info - holds information collected during an error. * @cs_timeout: CS timeout error information. * @razwi_info: RAZWI information. * @undef_opcode: undefined opcode information. * @page_fault_info: page fault information. + * @hw_err: (fatal) hardware error information. + * @fw_err: firmware error information. */ struct hl_error_info { struct cs_timeout_info cs_timeout; struct razwi_info razwi_info; struct undefined_opcode_info undef_opcode; struct page_fault_info page_fault_info; + struct hw_err_info hw_err; + struct fw_err_info fw_err; }; /** @@ -3090,6 +3142,7 @@ struct hl_reset_info { * (required only for PCI address match mode) * @pcie_bar: array of available PCIe bars virtual addresses. * @rmmio: configuration area address on SRAM. + * @hclass: pointer to the habanalabs class. * @cdev: related char device. * @cdev_ctrl: char device for control operations only (INFO IOCTL) * @dev: related kernel basic device structure. @@ -3104,6 +3157,8 @@ struct hl_reset_info { * @user_interrupt: array of hl_user_interrupt. upon the corresponding user * interrupt, driver will monitor the list of fences * registered to this interrupt. + * @tpc_interrupt: single TPC interrupt for all TPCs. + * @unexpected_error_interrupt: single interrupt for unexpected user error indication. * @common_user_cq_interrupt: common user CQ interrupt for all user CQ interrupts. * upon any user CQ interrupt, driver will monitor the * list of fences registered to this common structure. @@ -3199,6 +3254,7 @@ struct hl_reset_info { * drams are binned-out * @tpc_binning: contains mask of tpc engines that is received from the f/w which indicates which * tpc engines are binned-out + * @dmabuf_export_cnt: number of dma-buf exporting. * @card_type: Various ASICs have several card types. This indicates the card * type of the current device. * @major: habanalabs kernel driver major. @@ -3253,6 +3309,8 @@ struct hl_reset_info { * @supports_mmu_prefetch: true if prefetch is supported, otherwise false. * @reset_upon_device_release: reset the device when the user closes the file descriptor of the * device. + * @supports_ctx_switch: true if a ctx switch is required upon first submission. + * @support_preboot_binning: true if we support read binning info from preboot. * @nic_ports_mask: Controls which NIC ports are enabled. Used only for testing. * @fw_components: Controls which f/w components to load to the device. There are multiple f/w * stages and sometimes we want to stop at a certain stage. Used only for testing. @@ -3266,14 +3324,13 @@ struct hl_reset_info { * Used only for testing. * @heartbeat: Controls if we want to enable the heartbeat mechanism vs. the f/w, which verifies * that the f/w is always alive. Used only for testing. - * @supports_ctx_switch: true if a ctx switch is required upon first submission. - * @support_preboot_binning: true if we support read binning info from preboot. */ struct hl_device { struct pci_dev *pdev; u64 pcie_bar_phys[HL_PCI_NUM_BARS]; void __iomem *pcie_bar[HL_PCI_NUM_BARS]; void __iomem *rmmio; + struct class *hclass; struct cdev cdev; struct cdev cdev_ctrl; struct device *dev; @@ -3286,6 +3343,8 @@ struct hl_device { enum hl_asic_type asic_type; struct hl_cq *completion_queue; struct hl_user_interrupt *user_interrupt; + struct hl_user_interrupt tpc_interrupt; + struct hl_user_interrupt unexpected_error_interrupt; struct hl_user_interrupt common_user_cq_interrupt; struct hl_user_interrupt common_decoder_interrupt; struct hl_cs **shadow_cs_queue; @@ -3369,7 +3428,7 @@ struct hl_device { u64 fw_comms_poll_interval_usec; u64 dram_binning; u64 tpc_binning; - + atomic_t dmabuf_export_cnt; enum cpucp_card_types card_type; u32 major; u32 high_pll; @@ -3412,7 +3471,7 @@ struct hl_device { u8 supports_ctx_switch; u8 support_preboot_binning; - /* Parameters for bring-up */ + /* Parameters for bring-up to be upstreamed */ u64 nic_ports_mask; u64 fw_components; u8 mmu_enable; @@ -3450,6 +3509,20 @@ struct hl_cs_encaps_sig_handle { u32 count; }; +/** + * struct hl_info_fw_err_info - firmware error information structure + * @err_type: The type of error detected (or reported). + * @event_mask: Pointer to the event mask to be modified with the detected error flag + * (can be NULL) + * @event_id: The id of the event that reported the error + * (applicable when err_type is HL_INFO_FW_REPORTED_ERR). + */ +struct hl_info_fw_err_info { + enum hl_info_fw_err_type err_type; + u64 *event_mask; + u16 event_id; +}; + /* * IOCTLs */ @@ -3474,6 +3547,10 @@ struct hl_ioctl_desc { hl_ioctl_t *func; }; +static inline bool hl_is_fw_ver_below_1_9(struct hl_device *hdev) +{ + return (hdev->fw_major_version < 42); +} /* * Kernel module functions that can be accessed by entire module @@ -3537,14 +3614,12 @@ static inline bool hl_mem_area_crosses_range(u64 address, u32 size, } uint64_t hl_set_dram_bar_default(struct hl_device *hdev, u64 addr); +void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle); +void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr); void *hl_asic_dma_alloc_coherent_caller(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle, gfp_t flag, const char *caller); void hl_asic_dma_free_coherent_caller(struct hl_device *hdev, size_t size, void *cpu_addr, dma_addr_t dma_handle, const char *caller); -void *hl_cpu_accessible_dma_pool_alloc_caller(struct hl_device *hdev, size_t size, - dma_addr_t *dma_handle, const char *caller); -void hl_cpu_accessible_dma_pool_free_caller(struct hl_device *hdev, size_t size, void *vaddr, - const char *caller); void *hl_asic_dma_pool_zalloc_caller(struct hl_device *hdev, size_t size, gfp_t mem_flags, dma_addr_t *dma_handle, const char *caller); void hl_asic_dma_pool_free_caller(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr, @@ -3591,7 +3666,7 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg); irqreturn_t hl_irq_handler_eq(int irq, void *arg); irqreturn_t hl_irq_handler_dec_abnrm(int irq, void *arg); irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg); -irqreturn_t hl_irq_handler_default(int irq, void *arg); +irqreturn_t hl_irq_user_interrupt_thread_handler(int irq, void *arg); u32 hl_cq_inc_ptr(u32 ptr); int hl_asid_init(struct hl_device *hdev); @@ -3612,7 +3687,7 @@ int hl_ctx_get_fences(struct hl_ctx *ctx, u64 *seq_arr, void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr); void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr); -int hl_device_init(struct hl_device *hdev, struct class *hclass); +int hl_device_init(struct hl_device *hdev); void hl_device_fini(struct hl_device *hdev); int hl_device_suspend(struct hl_device *hdev); int hl_device_resume(struct hl_device *hdev); @@ -3662,6 +3737,7 @@ bool cs_needs_timeout(struct hl_cs *cs); bool is_staged_cs_last_exists(struct hl_device *hdev, struct hl_cs *cs); struct hl_cs *hl_staged_cs_find_first(struct hl_device *hdev, u64 cs_seq); void hl_multi_cs_completion_init(struct hl_device *hdev); +u32 hl_get_active_cs_num(struct hl_device *hdev); void goya_set_asic_funcs(struct hl_device *hdev); void gaudi_set_asic_funcs(struct hl_device *hdev); @@ -3861,6 +3937,7 @@ const char *hl_sync_engine_to_string(enum hl_sync_engine_type engine_type); void hl_mem_mgr_init(struct device *dev, struct hl_mem_mgr *mmg); void hl_mem_mgr_fini(struct hl_mem_mgr *mmg); +void hl_mem_mgr_idr_destroy(struct hl_mem_mgr *mmg); int hl_mem_mgr_mmap(struct hl_mem_mgr *mmg, struct vm_area_struct *vma, void *args); struct hl_mmap_mem_buf *hl_mmap_mem_buf_get(struct hl_mem_mgr *mmg, @@ -3879,6 +3956,8 @@ void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_o void hl_capture_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu); void hl_handle_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu, u64 *event_mask); +void hl_handle_critical_hw_err(struct hl_device *hdev, u16 event_id, u64 *event_mask); +void hl_handle_fw_err(struct hl_device *hdev, struct hl_info_fw_err_info *info); #ifdef CONFIG_DEBUG_FS diff --git a/drivers/accel/habanalabs/common/habanalabs_drv.c b/drivers/accel/habanalabs/common/habanalabs_drv.c index 03dae57dc838..a4b3f50f1cba 100644 --- a/drivers/accel/habanalabs/common/habanalabs_drv.c +++ b/drivers/accel/habanalabs/common/habanalabs_drv.c @@ -12,7 +12,6 @@ #include "../include/hw_ip/pci/pci_general.h" #include <linux/pci.h> -#include <linux/aer.h> #include <linux/module.h> #define CREATE_TRACE_POINTS @@ -221,12 +220,9 @@ int hl_device_open(struct inode *inode, struct file *filp) hl_debugfs_add_file(hpriv); + memset(&hdev->captured_err_info, 0, sizeof(hdev->captured_err_info)); atomic_set(&hdev->captured_err_info.cs_timeout.write_enable, 1); - atomic_set(&hdev->captured_err_info.razwi_info.razwi_detected, 0); - atomic_set(&hdev->captured_err_info.page_fault_info.page_fault_detected, 0); hdev->captured_err_info.undef_opcode.write_enable = true; - hdev->captured_err_info.razwi_info.razwi_info_available = false; - hdev->captured_err_info.page_fault_info.page_fault_info_available = false; hdev->open_counter++; hdev->last_successful_open_jif = jiffies; @@ -237,6 +233,7 @@ int hl_device_open(struct inode *inode, struct file *filp) out_err: mutex_unlock(&hdev->fpriv_list_lock); hl_mem_mgr_fini(&hpriv->mem_mgr); + hl_mem_mgr_idr_destroy(&hpriv->mem_mgr); hl_ctx_mgr_fini(hpriv->hdev, &hpriv->ctx_mgr); filp->private_data = NULL; mutex_destroy(&hpriv->ctx_lock); @@ -324,6 +321,7 @@ static void copy_kernel_module_params_to_device(struct hl_device *hdev) hdev->asic_prop.fw_security_enabled = is_asic_secured(hdev->asic_type); hdev->major = hl_major; + hdev->hclass = hl_class; hdev->memory_scrub = memory_scrub; hdev->reset_on_lockup = reset_on_lockup; hdev->boot_error_status_mask = boot_error_status_mask; @@ -550,9 +548,7 @@ static int hl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_set_drvdata(pdev, hdev); - pci_enable_pcie_error_reporting(pdev); - - rc = hl_device_init(hdev, hl_class); + rc = hl_device_init(hdev); if (rc) { dev_err(&pdev->dev, "Fatal error during habanalabs device init\n"); rc = -ENODEV; @@ -562,7 +558,6 @@ static int hl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return 0; disable_device: - pci_disable_pcie_error_reporting(pdev); pci_set_drvdata(pdev, NULL); destroy_hdev(hdev); @@ -585,7 +580,6 @@ static void hl_pci_remove(struct pci_dev *pdev) return; hl_device_fini(hdev); - pci_disable_pcie_error_reporting(pdev); pci_set_drvdata(pdev, NULL); destroy_hdev(hdev); } diff --git a/drivers/accel/habanalabs/common/habanalabs_ioctl.c b/drivers/accel/habanalabs/common/habanalabs_ioctl.c index 5005e6fca691..203ee857810c 100644 --- a/drivers/accel/habanalabs/common/habanalabs_ioctl.c +++ b/drivers/accel/habanalabs/common/habanalabs_ioctl.c @@ -102,11 +102,15 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) hw_ip.mme_master_slave_mode = prop->mme_master_slave_mode; hw_ip.first_available_interrupt_id = prop->first_available_user_interrupt; hw_ip.number_of_user_interrupts = prop->user_interrupt_count; + hw_ip.tpc_interrupt_id = prop->tpc_interrupt_id; hw_ip.edma_enabled_mask = prop->edma_enabled_mask; hw_ip.server_type = prop->server_type; hw_ip.security_enabled = prop->fw_security_enabled; hw_ip.revision_id = hdev->pdev->revision; + hw_ip.rotator_enabled_mask = prop->rotator_enabled_mask; + hw_ip.engine_core_interrupt_reg_addr = prop->engine_core_interrupt_reg_addr; + hw_ip.reserved_dram_size = dram_kmd_size; return copy_to_user(out, &hw_ip, min((size_t) size, sizeof(hw_ip))) ? -EFAULT : 0; @@ -830,6 +834,50 @@ static int user_mappings_info(struct hl_fpriv *hpriv, struct hl_info_args *args) return copy_to_user(out, pgf_info->user_mappings, actual_size) ? -EFAULT : 0; } +static int hw_err_info(struct hl_fpriv *hpriv, struct hl_info_args *args) +{ + void __user *user_buf = (void __user *) (uintptr_t) args->return_pointer; + struct hl_device *hdev = hpriv->hdev; + u32 user_buf_size = args->return_size; + struct hw_err_info *info; + int rc; + + if ((!user_buf_size) || (!user_buf)) + return -EINVAL; + + if (user_buf_size < sizeof(struct hl_info_hw_err_event)) + return -ENOMEM; + + info = &hdev->captured_err_info.hw_err; + if (!info->event_info_available) + return -ENOENT; + + rc = copy_to_user(user_buf, &info->event, sizeof(struct hl_info_hw_err_event)); + return rc ? -EFAULT : 0; +} + +static int fw_err_info(struct hl_fpriv *hpriv, struct hl_info_args *args) +{ + void __user *user_buf = (void __user *) (uintptr_t) args->return_pointer; + struct hl_device *hdev = hpriv->hdev; + u32 user_buf_size = args->return_size; + struct fw_err_info *info; + int rc; + + if ((!user_buf_size) || (!user_buf)) + return -EINVAL; + + if (user_buf_size < sizeof(struct hl_info_fw_err_event)) + return -ENOMEM; + + info = &hdev->captured_err_info.fw_err; + if (!info->event_info_available) + return -ENOENT; + + rc = copy_to_user(user_buf, &info->event, sizeof(struct hl_info_fw_err_event)); + return rc ? -EFAULT : 0; +} + static int send_fw_generic_request(struct hl_device *hdev, struct hl_info_args *info_args) { void __user *buff = (void __user *) (uintptr_t) info_args->return_pointer; @@ -950,6 +998,14 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, case HL_INFO_UNREGISTER_EVENTFD: return eventfd_unregister(hpriv, args); + case HL_INFO_HW_ERR_EVENT: + return hw_err_info(hpriv, args); + + case HL_INFO_FW_ERR_EVENT: + return fw_err_info(hpriv, args); + + case HL_INFO_DRAM_USAGE: + return dram_usage_info(hpriv, args); default: break; } @@ -962,10 +1018,6 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, } switch (args->op) { - case HL_INFO_DRAM_USAGE: - rc = dram_usage_info(hpriv, args); - break; - case HL_INFO_HW_IDLE: rc = hw_idle(hdev, args); break; diff --git a/drivers/accel/habanalabs/common/irq.c b/drivers/accel/habanalabs/common/irq.c index 04844e843a7b..fab1abc5c910 100644 --- a/drivers/accel/habanalabs/common/irq.c +++ b/drivers/accel/habanalabs/common/irq.c @@ -280,7 +280,6 @@ static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interru struct list_head *ts_reg_free_list_head = NULL; struct timestamp_reg_work_obj *job; bool reg_node_handle_fail = false; - ktime_t now = ktime_get(); int rc; /* For registration nodes: @@ -303,13 +302,13 @@ static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interru if (pend->ts_reg_info.buf) { if (!reg_node_handle_fail) { rc = handle_registration_node(hdev, pend, - &ts_reg_free_list_head, now); + &ts_reg_free_list_head, intr->timestamp); if (rc) reg_node_handle_fail = true; } } else { /* Handle wait target value node */ - pend->fence.timestamp = now; + pend->fence.timestamp = intr->timestamp; complete_all(&pend->fence.completion); } } @@ -326,6 +325,26 @@ static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interru } } +static void handle_tpc_interrupt(struct hl_device *hdev) +{ + u64 event_mask; + u32 flags; + + event_mask = HL_NOTIFIER_EVENT_TPC_ASSERT | + HL_NOTIFIER_EVENT_USER_ENGINE_ERR | + HL_NOTIFIER_EVENT_DEVICE_RESET; + + flags = HL_DRV_RESET_DELAY; + + dev_err_ratelimited(hdev->dev, "Received TPC assert\n"); + hl_device_cond_reset(hdev, flags, event_mask); +} + +static void handle_unexpected_user_interrupt(struct hl_device *hdev) +{ + dev_err_ratelimited(hdev->dev, "Received unexpected user error interrupt\n"); +} + /** * hl_irq_handler_user_interrupt - irq handler for user interrupts * @@ -336,6 +355,23 @@ static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interru irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg) { struct hl_user_interrupt *user_int = arg; + + user_int->timestamp = ktime_get(); + + return IRQ_WAKE_THREAD; +} + +/** + * hl_irq_user_interrupt_thread_handler - irq thread handler for user interrupts. + * This function is invoked by threaded irq mechanism + * + * @irq: irq number + * @arg: pointer to user interrupt structure + * + */ +irqreturn_t hl_irq_user_interrupt_thread_handler(int irq, void *arg) +{ + struct hl_user_interrupt *user_int = arg; struct hl_device *hdev = user_int->hdev; switch (user_int->type) { @@ -351,6 +387,12 @@ irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg) /* Handle decoder interrupt registered on this specific irq */ handle_user_interrupt(hdev, user_int); break; + case HL_USR_INTERRUPT_TPC: + handle_tpc_interrupt(hdev); + break; + case HL_USR_INTERRUPT_UNEXPECTED: + handle_unexpected_user_interrupt(hdev); + break; default: break; } @@ -359,24 +401,6 @@ irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg) } /** - * hl_irq_handler_default - default irq handler - * - * @irq: irq number - * @arg: pointer to user interrupt structure - * - */ -irqreturn_t hl_irq_handler_default(int irq, void *arg) -{ - struct hl_user_interrupt *user_interrupt = arg; - struct hl_device *hdev = user_interrupt->hdev; - u32 interrupt_id = user_interrupt->interrupt_id; - - dev_err(hdev->dev, "got invalid user interrupt %u", interrupt_id); - - return IRQ_HANDLED; -} - -/** * hl_irq_handler_eq - irq handler for event queue * * @irq: irq number @@ -405,11 +429,10 @@ irqreturn_t hl_irq_handler_eq(int irq, void *arg) cur_eqe_index = FIELD_GET(EQ_CTL_INDEX_MASK, cur_eqe); if ((hdev->event_queue.check_eqe_index) && - (((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK) - != cur_eqe_index)) { + (((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK) != cur_eqe_index)) { dev_dbg(hdev->dev, - "EQE 0x%x in queue is ready but index does not match %d!=%d", - eq_base[eq->ci].hdr.ctl, + "EQE %#x in queue is ready but index does not match %d!=%d", + cur_eqe, ((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK), cur_eqe_index); break; diff --git a/drivers/accel/habanalabs/common/memory.c b/drivers/accel/habanalabs/common/memory.c index 761a47e89b00..17b79d717896 100644 --- a/drivers/accel/habanalabs/common/memory.c +++ b/drivers/accel/habanalabs/common/memory.c @@ -235,10 +235,8 @@ static int dma_map_host_va(struct hl_device *hdev, u64 addr, u64 size, } rc = hl_pin_host_memory(hdev, addr, size, userptr); - if (rc) { - dev_err(hdev->dev, "Failed to pin host memory\n"); + if (rc) goto pin_err; - } userptr->dma_mapped = true; userptr->dir = DMA_BIDIRECTIONAL; @@ -1097,10 +1095,8 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, u64 *device huge_page_size = hdev->asic_prop.pmmu_huge.page_size; rc = dma_map_host_va(hdev, addr, size, &userptr); - if (rc) { - dev_err(hdev->dev, "failed to get userptr from va\n"); + if (rc) return rc; - } rc = init_phys_pg_pack_from_userptr(ctx, userptr, &phys_pg_pack, false); @@ -1270,6 +1266,18 @@ init_page_pack_err: return rc; } +/* Should be called while the context's mem_hash_lock is taken */ +static struct hl_vm_hash_node *get_vm_hash_node_locked(struct hl_ctx *ctx, u64 vaddr) +{ + struct hl_vm_hash_node *hnode; + + hash_for_each_possible(ctx->mem_hash, hnode, node, vaddr) + if (vaddr == hnode->vaddr) + return hnode; + + return NULL; +} + /** * unmap_device_va() - unmap the given device virtual address. * @ctx: pointer to the context structure. @@ -1285,10 +1293,10 @@ static int unmap_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, { struct hl_vm_phys_pg_pack *phys_pg_pack = NULL; u64 vaddr = args->unmap.device_virt_addr; - struct hl_vm_hash_node *hnode = NULL; struct asic_fixed_properties *prop; struct hl_device *hdev = ctx->hdev; struct hl_userptr *userptr = NULL; + struct hl_vm_hash_node *hnode; struct hl_va_range *va_range; enum vm_type *vm_type; bool is_userptr; @@ -1298,15 +1306,10 @@ static int unmap_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, /* protect from double entrance */ mutex_lock(&ctx->mem_hash_lock); - hash_for_each_possible(ctx->mem_hash, hnode, node, (unsigned long)vaddr) - if (vaddr == hnode->vaddr) - break; - + hnode = get_vm_hash_node_locked(ctx, vaddr); if (!hnode) { mutex_unlock(&ctx->mem_hash_lock); - dev_err(hdev->dev, - "unmap failed, no mem hnode for vaddr 0x%llx\n", - vaddr); + dev_err(hdev->dev, "unmap failed, no mem hnode for vaddr 0x%llx\n", vaddr); return -EINVAL; } @@ -1779,6 +1782,44 @@ static void hl_unmap_dmabuf(struct dma_buf_attachment *attachment, kfree(sgt); } +static struct hl_vm_hash_node *memhash_node_export_get(struct hl_ctx *ctx, u64 addr) +{ + struct hl_device *hdev = ctx->hdev; + struct hl_vm_hash_node *hnode; + + /* get the memory handle */ + mutex_lock(&ctx->mem_hash_lock); + hnode = get_vm_hash_node_locked(ctx, addr); + if (!hnode) { + mutex_unlock(&ctx->mem_hash_lock); + dev_dbg(hdev->dev, "map address %#llx not found\n", addr); + return ERR_PTR(-EINVAL); + } + + if (upper_32_bits(hnode->handle)) { + mutex_unlock(&ctx->mem_hash_lock); + dev_dbg(hdev->dev, "invalid handle %#llx for map address %#llx\n", + hnode->handle, addr); + return ERR_PTR(-EINVAL); + } + + /* + * node found, increase export count so this memory cannot be unmapped + * and the hash node cannot be deleted. + */ + hnode->export_cnt++; + mutex_unlock(&ctx->mem_hash_lock); + + return hnode; +} + +static void memhash_node_export_put(struct hl_ctx *ctx, struct hl_vm_hash_node *hnode) +{ + mutex_lock(&ctx->mem_hash_lock); + hnode->export_cnt--; + mutex_unlock(&ctx->mem_hash_lock); +} + static void hl_release_dmabuf(struct dma_buf *dmabuf) { struct hl_dmabuf_priv *hl_dmabuf = dmabuf->priv; @@ -1789,13 +1830,15 @@ static void hl_release_dmabuf(struct dma_buf *dmabuf) ctx = hl_dmabuf->ctx; - if (hl_dmabuf->memhash_hnode) { - mutex_lock(&ctx->mem_hash_lock); - hl_dmabuf->memhash_hnode->export_cnt--; - mutex_unlock(&ctx->mem_hash_lock); - } + if (hl_dmabuf->memhash_hnode) + memhash_node_export_put(ctx, hl_dmabuf->memhash_hnode); + atomic_dec(&ctx->hdev->dmabuf_export_cnt); hl_ctx_put(ctx); + + /* Paired with get_file() in export_dmabuf() */ + fput(ctx->hpriv->filp); + kfree(hl_dmabuf); } @@ -1834,6 +1877,13 @@ static int export_dmabuf(struct hl_ctx *ctx, hl_dmabuf->ctx = ctx; hl_ctx_get(hl_dmabuf->ctx); + atomic_inc(&ctx->hdev->dmabuf_export_cnt); + + /* Get compute device file to enforce release order, such that all exported dma-buf will be + * released first and only then the compute device. + * Paired with fput() in hl_release_dmabuf(). + */ + get_file(ctx->hpriv->filp); *dmabuf_fd = fd; @@ -1933,47 +1983,6 @@ static int validate_export_params(struct hl_device *hdev, u64 device_addr, u64 s return 0; } -static struct hl_vm_hash_node *memhash_node_export_get(struct hl_ctx *ctx, u64 addr) -{ - struct hl_device *hdev = ctx->hdev; - struct hl_vm_hash_node *hnode; - - /* get the memory handle */ - mutex_lock(&ctx->mem_hash_lock); - hash_for_each_possible(ctx->mem_hash, hnode, node, (unsigned long)addr) - if (addr == hnode->vaddr) - break; - - if (!hnode) { - mutex_unlock(&ctx->mem_hash_lock); - dev_dbg(hdev->dev, "map address %#llx not found\n", addr); - return ERR_PTR(-EINVAL); - } - - if (upper_32_bits(hnode->handle)) { - mutex_unlock(&ctx->mem_hash_lock); - dev_dbg(hdev->dev, "invalid handle %#llx for map address %#llx\n", - hnode->handle, addr); - return ERR_PTR(-EINVAL); - } - - /* - * node found, increase export count so this memory cannot be unmapped - * and the hash node cannot be deleted. - */ - hnode->export_cnt++; - mutex_unlock(&ctx->mem_hash_lock); - - return hnode; -} - -static void memhash_node_export_put(struct hl_ctx *ctx, struct hl_vm_hash_node *hnode) -{ - mutex_lock(&ctx->mem_hash_lock); - hnode->export_cnt--; - mutex_unlock(&ctx->mem_hash_lock); -} - static struct hl_vm_phys_pg_pack *get_phys_pg_pack_from_hash_node(struct hl_device *hdev, struct hl_vm_hash_node *hnode) { @@ -2221,11 +2230,11 @@ static struct hl_mmap_mem_buf_behavior hl_ts_behavior = { * allocate_timestamps_buffers() - allocate timestamps buffers * This function will allocate ts buffer that will later on be mapped to the user * in order to be able to read the timestamp. - * in additon it'll allocate an extra buffer for registration management. + * in addition it'll allocate an extra buffer for registration management. * since we cannot fail during registration for out-of-memory situation, so * we'll prepare a pool which will be used as user interrupt nodes and instead * of dynamically allocating nodes while registration we'll pick the node from - * this pool. in addtion it'll add node to the mapping hash which will be used + * this pool. in addition it'll add node to the mapping hash which will be used * to map user ts buffer to the internal kernel ts buffer. * @hpriv: pointer to the private data of the fd * @args: ioctl input diff --git a/drivers/accel/habanalabs/common/memory_mgr.c b/drivers/accel/habanalabs/common/memory_mgr.c index 0f2759e26547..c4d84df355b0 100644 --- a/drivers/accel/habanalabs/common/memory_mgr.c +++ b/drivers/accel/habanalabs/common/memory_mgr.c @@ -275,7 +275,7 @@ int hl_mem_mgr_mmap(struct hl_mem_mgr *mmg, struct vm_area_struct *vma, if (atomic_cmpxchg(&buf->mmap, 0, 1)) { dev_err(mmg->dev, - "%s, Memory mmap failed, already mmaped to user\n", + "%s, Memory mmap failed, already mapped to user\n", buf->behavior->topic); rc = -EINVAL; goto put_mem; @@ -341,8 +341,19 @@ void hl_mem_mgr_fini(struct hl_mem_mgr *mmg) "%s: Buff handle %u for CTX is still alive\n", topic, id); } +} - /* TODO: can it happen that some buffer is still in use at this point? */ +/** + * hl_mem_mgr_idr_destroy() - destroy memory manager IDR. + * @mmg: parent unified memory manager + * + * Destroy the memory manager IDR. + * Shall be called when IDR is empty and no memory buffers are in use. + */ +void hl_mem_mgr_idr_destroy(struct hl_mem_mgr *mmg) +{ + if (!idr_is_empty(&mmg->handles)) + dev_crit(mmg->dev, "memory manager IDR is destroyed while it is not empty!\n"); idr_destroy(&mmg->handles); } diff --git a/drivers/accel/habanalabs/common/mmu/mmu.c b/drivers/accel/habanalabs/common/mmu/mmu.c index a42ae8bc61e8..17581b1bcc77 100644 --- a/drivers/accel/habanalabs/common/mmu/mmu.c +++ b/drivers/accel/habanalabs/common/mmu/mmu.c @@ -540,8 +540,8 @@ static void hl_mmu_pa_page_with_offset(struct hl_ctx *ctx, u64 virt_addr, u32 page_off; /* - * Bit arithmetics cannot be used for non power of two page - * sizes. In addition, since bit arithmetics is not used, + * Bit arithmetic cannot be used for non power of two page + * sizes. In addition, since bit arithmetic is not used, * we cannot ignore dram base. All that shall be considered. */ @@ -757,7 +757,7 @@ u64 hl_mmu_get_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte) * @mmu_prop: MMU properties. * @hop_idx: HOP index. * @hop_addr: HOP address. - * @virt_addr: virtual address fro the translation. + * @virt_addr: virtual address for the translation. * * @return the matching PTE value on success, otherwise U64_MAX. */ diff --git a/drivers/accel/habanalabs/common/security.c b/drivers/accel/habanalabs/common/security.c index 5f03ade07ead..297e6e44fd0c 100644 --- a/drivers/accel/habanalabs/common/security.c +++ b/drivers/accel/habanalabs/common/security.c @@ -502,7 +502,7 @@ free_glbl_sec: int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, - const struct range *regs_range_array, u32 regs_range_array_size) + const struct range *user_regs_range_array, u32 user_regs_range_array_size) { int i; struct hl_block_glbl_sec *glbl_sec; @@ -514,8 +514,8 @@ int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset, return -ENOMEM; hl_secure_block(hdev, glbl_sec, blocks_array_size); - hl_unsecure_registers_range(hdev, regs_range_array, - regs_range_array_size, 0, pb_blocks, glbl_sec, + hl_unsecure_registers_range(hdev, user_regs_range_array, + user_regs_range_array_size, 0, pb_blocks, glbl_sec, blocks_array_size); /* Fill all blocks with the same configuration */ diff --git a/drivers/accel/habanalabs/common/security.h b/drivers/accel/habanalabs/common/security.h index 234b4a6ed8bc..d7a3b3e82ea4 100644 --- a/drivers/accel/habanalabs/common/security.h +++ b/drivers/accel/habanalabs/common/security.h @@ -10,7 +10,7 @@ #include <linux/io-64-nonatomic-lo-hi.h> -extern struct hl_device *hdev; +struct hl_device; /* special blocks */ #define HL_MAX_NUM_OF_GLBL_ERR_CAUSE 10 diff --git a/drivers/accel/habanalabs/gaudi/gaudi.c b/drivers/accel/habanalabs/gaudi/gaudi.c index bb858b94e1e8..08a4b1cf2b42 100644 --- a/drivers/accel/habanalabs/gaudi/gaudi.c +++ b/drivers/accel/habanalabs/gaudi/gaudi.c @@ -656,6 +656,7 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev) prop->cfg_size = CFG_SIZE; prop->max_asid = MAX_ASID; prop->num_of_events = GAUDI_EVENT_SIZE; + prop->max_num_of_engines = GAUDI_ENGINE_ID_SIZE; prop->tpc_enabled_mask = TPC_ENABLED_MASK; set_default_power_values(hdev); @@ -679,6 +680,7 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev) (num_sync_stream_queues * HL_RSVD_MONS); prop->first_available_user_interrupt = USHRT_MAX; + prop->tpc_interrupt_id = USHRT_MAX; for (i = 0 ; i < HL_MAX_DCORES ; i++) prop->first_available_cq[i] = USHRT_MAX; @@ -867,13 +869,18 @@ pci_init: rc = hl_fw_read_preboot_status(hdev); if (rc) { if (hdev->reset_on_preboot_fail) + /* we are already on failure flow, so don't check if hw_fini fails. */ hdev->asic_funcs->hw_fini(hdev, true, false); goto pci_fini; } if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); - hdev->asic_funcs->hw_fini(hdev, true, false); + rc = hdev->asic_funcs->hw_fini(hdev, true, false); + if (rc) { + dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc); + goto pci_fini; + } } return 0; @@ -3718,7 +3725,7 @@ static int gaudi_mmu_init(struct hl_device *hdev) if (rc) { dev_err(hdev->dev, "failed to set hop0 addr for asid %d\n", i); - goto err; + return rc; } } @@ -3729,7 +3736,9 @@ static int gaudi_mmu_init(struct hl_device *hdev) /* mem cache invalidation */ WREG32(mmSTLB_MEM_CACHE_INVALIDATION, 1); - hl_mmu_invalidate_cache(hdev, true, 0); + rc = hl_mmu_invalidate_cache(hdev, true, 0); + if (rc) + return rc; WREG32(mmMMU_UP_MMU_ENABLE, 1); WREG32(mmMMU_UP_SPI_MASK, 0xF); @@ -3745,9 +3754,6 @@ static int gaudi_mmu_init(struct hl_device *hdev) gaudi->hw_cap_initialized |= HW_CAP_MMU; return 0; - -err: - return rc; } static int gaudi_load_firmware_to_device(struct hl_device *hdev) @@ -4068,7 +4074,7 @@ disable_queues: return rc; } -static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) +static int gaudi_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) { struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; @@ -4078,7 +4084,7 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset if (!hard_reset) { dev_err(hdev->dev, "GAUDI doesn't support soft-reset\n"); - return; + return 0; } if (hdev->pldm) { @@ -4199,10 +4205,10 @@ skip_reset: msleep(reset_timeout_ms); status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM); - if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) - dev_err(hdev->dev, - "Timeout while waiting for device to reset 0x%x\n", - status); + if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) { + dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status); + return -ETIMEDOUT; + } if (gaudi) { gaudi->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | HW_CAP_HBM | @@ -4215,6 +4221,7 @@ skip_reset: hdev->device_cpu_is_halted = false; } + return 0; } static int gaudi_suspend(struct hl_device *hdev) @@ -7297,7 +7304,7 @@ static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type, u64 *e } static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type, - bool razwi, u64 *event_mask) + bool check_razwi, u64 *event_mask) { bool is_read = false, is_write = false; u16 engine_id[2], num_of_razwi_eng = 0; @@ -7316,7 +7323,7 @@ static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type, dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", event_type, desc); - if (razwi) { + if (check_razwi) { gaudi_print_and_get_razwi_info(hdev, &engine_id[0], &engine_id[1], &is_read, &is_write); gaudi_print_and_get_mmu_error_info(hdev, &razwi_addr, event_mask); @@ -7333,8 +7340,9 @@ static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type, num_of_razwi_eng = 1; } - hl_handle_razwi(hdev, razwi_addr, engine_id, num_of_razwi_eng, razwi_flags, - event_mask); + if (razwi_flags) + hl_handle_razwi(hdev, razwi_addr, engine_id, num_of_razwi_eng, + razwi_flags, event_mask); } } @@ -7633,6 +7641,7 @@ static void gaudi_print_clk_change_info(struct hl_device *hdev, u16 event_type, static void gaudi_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry) { struct gaudi_device *gaudi = hdev->asic_specific; + struct hl_info_fw_err_info fw_err_info; u64 data = le64_to_cpu(eq_entry->data[0]), event_mask = 0; u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); u32 fw_fatal_err_flag = 0, flags = 0; @@ -7911,7 +7920,10 @@ static void gaudi_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entr case GAUDI_EVENT_FW_ALIVE_S: gaudi_print_irq_info(hdev, event_type, false, &event_mask); gaudi_print_fw_alive_info(hdev, &eq_entry->fw_alive); - event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR; + fw_err_info.err_type = HL_INFO_FW_REPORTED_ERR; + fw_err_info.event_id = event_type; + fw_err_info.event_mask = &event_mask; + hl_handle_fw_err(hdev, &fw_err_info); goto reset_device; default: @@ -7942,6 +7954,10 @@ reset_device: } if (reset_required) { + /* escalate general hw errors to critical/fatal error */ + if (event_mask & HL_NOTIFIER_EVENT_GENERAL_HW_ERR) + hl_handle_critical_hw_err(hdev, event_type, &event_mask); + hl_device_cond_reset(hdev, flags, event_mask); } else { hl_fw_unmask_irq(hdev, event_type); @@ -8403,19 +8419,26 @@ static int gaudi_internal_cb_pool_init(struct hl_device *hdev, } mutex_lock(&hdev->mmu_lock); + rc = hl_mmu_map_contiguous(ctx, hdev->internal_cb_va_base, hdev->internal_cb_pool_dma_addr, HOST_SPACE_INTERNAL_CB_SZ); - - hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR); - mutex_unlock(&hdev->mmu_lock); - if (rc) goto unreserve_internal_cb_pool; + rc = hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR); + if (rc) + goto unmap_internal_cb_pool; + + mutex_unlock(&hdev->mmu_lock); + return 0; +unmap_internal_cb_pool: + hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base, + HOST_SPACE_INTERNAL_CB_SZ); unreserve_internal_cb_pool: + mutex_unlock(&hdev->mmu_lock); hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ); destroy_internal_cb_pool: diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2.c b/drivers/accel/habanalabs/gaudi2/gaudi2.c index 6f415fa94eee..edcbda3d9b40 100644 --- a/drivers/accel/habanalabs/gaudi2/gaudi2.c +++ b/drivers/accel/habanalabs/gaudi2/gaudi2.c @@ -23,7 +23,8 @@ #define GAUDI2_DMA_POOL_BLK_SIZE SZ_256 /* 256 bytes */ #define GAUDI2_RESET_TIMEOUT_MSEC 2000 /* 2000ms */ -#define GAUDI2_RESET_POLL_TIMEOUT_USEC 50000 /* 50ms */ + +#define GAUDI2_RESET_POLL_TIMEOUT_USEC 500000 /* 500ms */ #define GAUDI2_PLDM_HRESET_TIMEOUT_MSEC 25000 /* 25s */ #define GAUDI2_PLDM_SRESET_TIMEOUT_MSEC 25000 /* 25s */ #define GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC 3000000 /* 3s */ @@ -86,10 +87,11 @@ #define KDMA_TIMEOUT_USEC USEC_PER_SEC -#define IS_DMA_IDLE(dma_core_idle_ind_mask) \ - (!((dma_core_idle_ind_mask) & \ - ((DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK) | \ - (DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK)))) +#define IS_DMA_IDLE(dma_core_sts0) \ + (!((dma_core_sts0) & (DCORE0_EDMA0_CORE_STS0_BUSY_MASK))) + +#define IS_DMA_HALTED(dma_core_sts1) \ + ((dma_core_sts1) & (DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK)) #define IS_MME_IDLE(mme_arch_sts) (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) @@ -132,6 +134,282 @@ #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0) +/* RAZWI initiator coordinates */ +#define RAZWI_GET_AXUSER_XY(x) \ + ((x & 0xF8001FF0) >> 4) + +#define RAZWI_GET_AXUSER_LOW_XY(x) \ + ((x & 0x00001FF0) >> 4) + +#define RAZWI_INITIATOR_AXUER_L_X_SHIFT 0 +#define RAZWI_INITIATOR_AXUER_L_X_MASK 0x1F +#define RAZWI_INITIATOR_AXUER_L_Y_SHIFT 5 +#define RAZWI_INITIATOR_AXUER_L_Y_MASK 0xF + +#define RAZWI_INITIATOR_AXUER_H_X_SHIFT 23 +#define RAZWI_INITIATOR_AXUER_H_X_MASK 0x1F + +#define RAZWI_INITIATOR_ID_X_Y_LOW(x, y) \ + ((((y) & RAZWI_INITIATOR_AXUER_L_Y_MASK) << RAZWI_INITIATOR_AXUER_L_Y_SHIFT) | \ + (((x) & RAZWI_INITIATOR_AXUER_L_X_MASK) << RAZWI_INITIATOR_AXUER_L_X_SHIFT)) + +#define RAZWI_INITIATOR_ID_X_HIGH(x) \ + (((x) & RAZWI_INITIATOR_AXUER_H_X_MASK) << RAZWI_INITIATOR_AXUER_H_X_SHIFT) + +#define RAZWI_INITIATOR_ID_X_Y(xl, yl, xh) \ + (RAZWI_INITIATOR_ID_X_Y_LOW(xl, yl) | RAZWI_INITIATOR_ID_X_HIGH(xh)) + +#define PSOC_RAZWI_ENG_STR_SIZE 128 +#define PSOC_RAZWI_MAX_ENG_PER_RTR 5 + +struct gaudi2_razwi_info { + u32 axuser_xy; + u32 rtr_ctrl; + u16 eng_id; + char *eng_name; +}; + +static struct gaudi2_razwi_info common_razwi_info[] = { + {RAZWI_INITIATOR_ID_X_Y(2, 4, 0), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_DEC_0, "DEC0"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_DEC_1, "DEC1"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 18), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_DEC_0, "DEC2"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_DEC_1, "DEC3"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 0), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_DEC_0, "DEC4"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_DEC_1, "DEC5"}, + {RAZWI_INITIATOR_ID_X_Y(17, 11, 18), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_DEC_0, "DEC6"}, + {RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_DEC_1, "DEC7"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 6), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC8"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 7), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC9"}, + {RAZWI_INITIATOR_ID_X_Y(3, 4, 2), mmDCORE0_RTR1_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_TPC_0, "TPC0"}, + {RAZWI_INITIATOR_ID_X_Y(3, 4, 4), mmDCORE0_RTR1_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_TPC_1, "TPC1"}, + {RAZWI_INITIATOR_ID_X_Y(4, 4, 2), mmDCORE0_RTR2_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_TPC_2, "TPC2"}, + {RAZWI_INITIATOR_ID_X_Y(4, 4, 4), mmDCORE0_RTR2_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_TPC_3, "TPC3"}, + {RAZWI_INITIATOR_ID_X_Y(5, 4, 2), mmDCORE0_RTR3_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_TPC_4, "TPC4"}, + {RAZWI_INITIATOR_ID_X_Y(5, 4, 4), mmDCORE0_RTR3_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_TPC_5, "TPC5"}, + {RAZWI_INITIATOR_ID_X_Y(16, 4, 14), mmDCORE1_RTR6_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_TPC_0, "TPC6"}, + {RAZWI_INITIATOR_ID_X_Y(16, 4, 16), mmDCORE1_RTR6_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_TPC_1, "TPC7"}, + {RAZWI_INITIATOR_ID_X_Y(15, 4, 14), mmDCORE1_RTR5_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_TPC_2, "TPC8"}, + {RAZWI_INITIATOR_ID_X_Y(15, 4, 16), mmDCORE1_RTR5_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_TPC_3, "TPC9"}, + {RAZWI_INITIATOR_ID_X_Y(14, 4, 14), mmDCORE1_RTR4_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_TPC_4, "TPC10"}, + {RAZWI_INITIATOR_ID_X_Y(14, 4, 16), mmDCORE1_RTR4_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_TPC_5, "TPC11"}, + {RAZWI_INITIATOR_ID_X_Y(5, 11, 2), mmDCORE2_RTR3_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_TPC_0, "TPC12"}, + {RAZWI_INITIATOR_ID_X_Y(5, 11, 4), mmDCORE2_RTR3_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_TPC_1, "TPC13"}, + {RAZWI_INITIATOR_ID_X_Y(4, 11, 2), mmDCORE2_RTR2_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_TPC_2, "TPC14"}, + {RAZWI_INITIATOR_ID_X_Y(4, 11, 4), mmDCORE2_RTR2_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_TPC_3, "TPC15"}, + {RAZWI_INITIATOR_ID_X_Y(3, 11, 2), mmDCORE2_RTR1_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_TPC_4, "TPC16"}, + {RAZWI_INITIATOR_ID_X_Y(3, 11, 4), mmDCORE2_RTR1_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_TPC_5, "TPC17"}, + {RAZWI_INITIATOR_ID_X_Y(14, 11, 14), mmDCORE3_RTR4_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_TPC_0, "TPC18"}, + {RAZWI_INITIATOR_ID_X_Y(14, 11, 16), mmDCORE3_RTR4_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_TPC_1, "TPC19"}, + {RAZWI_INITIATOR_ID_X_Y(15, 11, 14), mmDCORE3_RTR5_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_TPC_2, "TPC20"}, + {RAZWI_INITIATOR_ID_X_Y(15, 11, 16), mmDCORE3_RTR5_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_TPC_3, "TPC21"}, + {RAZWI_INITIATOR_ID_X_Y(16, 11, 14), mmDCORE3_RTR6_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_TPC_4, "TPC22"}, + {RAZWI_INITIATOR_ID_X_Y(16, 11, 16), mmDCORE3_RTR6_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC23"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC24"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 8), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC0_0, "NIC0"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 10), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC0_1, "NIC1"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 12), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC1_0, "NIC2"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC1_1, "NIC3"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 15), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC2_0, "NIC4"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC2_1, "NIC5"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC3_0, "NIC6"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 6), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC3_1, "NIC7"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 8), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC4_0, "NIC8"}, + {RAZWI_INITIATOR_ID_X_Y(17, 11, 12), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC4_1, "NIC9"}, + {RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC5_0, "NIC10"}, + {RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_NIC5_1, "NIC11"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_PDMA_0, "PDMA0"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 3), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_PDMA_1, "PDMA1"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "PMMU"}, + {RAZWI_INITIATOR_ID_X_Y(2, 4, 5), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "PCIE"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 16), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_ARC_FARM, "ARC_FARM"}, + {RAZWI_INITIATOR_ID_X_Y(17, 4, 17), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_KDMA, "KDMA"}, + {RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_EDMA_0, "EDMA0"}, + {RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_EDMA_1, "EDMA1"}, + {RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_EDMA_0, "EDMA2"}, + {RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_EDMA_1, "EDMA3"}, + {RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_EDMA_0, "EDMA4"}, + {RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_EDMA_1, "EDMA5"}, + {RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_EDMA_0, "EDMA6"}, + {RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_EDMA_1, "EDMA7"}, + {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU0"}, + {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU1"}, + {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU2"}, + {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU3"}, + {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU4"}, + {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU5"}, + {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU6"}, + {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU7"}, + {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU8"}, + {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU9"}, + {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU10"}, + {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU11"}, + {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU12"}, + {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU13"}, + {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU14"}, + {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_SIZE, "HMMU15"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_ROT_0, "ROT0"}, + {RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_ROT_1, "ROT1"}, + {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE, + GAUDI2_ENGINE_ID_PSOC, "CPU"}, + {RAZWI_INITIATOR_ID_X_Y(17, 11, 11), mmDCORE3_RTR7_CTRL_BASE, + GAUDI2_ENGINE_ID_PSOC, "PSOC"} +}; + +static struct gaudi2_razwi_info mme_razwi_info[] = { + /* MME X high coordinate is N/A, hence using only low coordinates */ + {RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_WR"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_RD"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE2"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE3"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE, + GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE4"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_WR"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_RD"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE2"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE3"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE, + GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE4"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_WR"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_RD"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE2"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE3"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE, + GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE4"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_WR"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_RD"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE0"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE1"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE2"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE3"}, + {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE, + GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE4"} +}; + enum hl_pmmu_fatal_cause { LATENCY_RD_OUT_FIFO_OVERRUN, LATENCY_WR_OUT_FIFO_OVERRUN, @@ -1437,6 +1715,34 @@ static const u32 gaudi2_tpc_cfg_blocks_bases[TPC_ID_SIZE] = { [TPC_ID_DCORE0_TPC6] = mmDCORE0_TPC6_CFG_BASE, }; +static const u32 gaudi2_tpc_eml_cfg_blocks_bases[TPC_ID_SIZE] = { + [TPC_ID_DCORE0_TPC0] = mmDCORE0_TPC0_EML_CFG_BASE, + [TPC_ID_DCORE0_TPC1] = mmDCORE0_TPC1_EML_CFG_BASE, + [TPC_ID_DCORE0_TPC2] = mmDCORE0_TPC2_EML_CFG_BASE, + [TPC_ID_DCORE0_TPC3] = mmDCORE0_TPC3_EML_CFG_BASE, + [TPC_ID_DCORE0_TPC4] = mmDCORE0_TPC4_EML_CFG_BASE, + [TPC_ID_DCORE0_TPC5] = mmDCORE0_TPC5_EML_CFG_BASE, + [TPC_ID_DCORE1_TPC0] = mmDCORE1_TPC0_EML_CFG_BASE, + [TPC_ID_DCORE1_TPC1] = mmDCORE1_TPC1_EML_CFG_BASE, + [TPC_ID_DCORE1_TPC2] = mmDCORE1_TPC2_EML_CFG_BASE, + [TPC_ID_DCORE1_TPC3] = mmDCORE1_TPC3_EML_CFG_BASE, + [TPC_ID_DCORE1_TPC4] = mmDCORE1_TPC4_EML_CFG_BASE, + [TPC_ID_DCORE1_TPC5] = mmDCORE1_TPC5_EML_CFG_BASE, + [TPC_ID_DCORE2_TPC0] = mmDCORE2_TPC0_EML_CFG_BASE, + [TPC_ID_DCORE2_TPC1] = mmDCORE2_TPC1_EML_CFG_BASE, + [TPC_ID_DCORE2_TPC2] = mmDCORE2_TPC2_EML_CFG_BASE, + [TPC_ID_DCORE2_TPC3] = mmDCORE2_TPC3_EML_CFG_BASE, + [TPC_ID_DCORE2_TPC4] = mmDCORE2_TPC4_EML_CFG_BASE, + [TPC_ID_DCORE2_TPC5] = mmDCORE2_TPC5_EML_CFG_BASE, + [TPC_ID_DCORE3_TPC0] = mmDCORE3_TPC0_EML_CFG_BASE, + [TPC_ID_DCORE3_TPC1] = mmDCORE3_TPC1_EML_CFG_BASE, + [TPC_ID_DCORE3_TPC2] = mmDCORE3_TPC2_EML_CFG_BASE, + [TPC_ID_DCORE3_TPC3] = mmDCORE3_TPC3_EML_CFG_BASE, + [TPC_ID_DCORE3_TPC4] = mmDCORE3_TPC4_EML_CFG_BASE, + [TPC_ID_DCORE3_TPC5] = mmDCORE3_TPC5_EML_CFG_BASE, + [TPC_ID_DCORE0_TPC6] = mmDCORE0_TPC6_EML_CFG_BASE, +}; + const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE] = { [ROTATOR_ID_0] = mmROT0_BASE, [ROTATOR_ID_1] = mmROT1_BASE @@ -1475,6 +1781,56 @@ static const u32 gaudi2_rot_id_to_queue_id[ROTATOR_ID_SIZE] = { [ROTATOR_ID_1] = GAUDI2_QUEUE_ID_ROT_1_0, }; +static const u32 gaudi2_tpc_engine_id_to_tpc_id[] = { + [GAUDI2_DCORE0_ENGINE_ID_TPC_0] = TPC_ID_DCORE0_TPC0, + [GAUDI2_DCORE0_ENGINE_ID_TPC_1] = TPC_ID_DCORE0_TPC1, + [GAUDI2_DCORE0_ENGINE_ID_TPC_2] = TPC_ID_DCORE0_TPC2, + [GAUDI2_DCORE0_ENGINE_ID_TPC_3] = TPC_ID_DCORE0_TPC3, + [GAUDI2_DCORE0_ENGINE_ID_TPC_4] = TPC_ID_DCORE0_TPC4, + [GAUDI2_DCORE0_ENGINE_ID_TPC_5] = TPC_ID_DCORE0_TPC5, + [GAUDI2_DCORE1_ENGINE_ID_TPC_0] = TPC_ID_DCORE1_TPC0, + [GAUDI2_DCORE1_ENGINE_ID_TPC_1] = TPC_ID_DCORE1_TPC1, + [GAUDI2_DCORE1_ENGINE_ID_TPC_2] = TPC_ID_DCORE1_TPC2, + [GAUDI2_DCORE1_ENGINE_ID_TPC_3] = TPC_ID_DCORE1_TPC3, + [GAUDI2_DCORE1_ENGINE_ID_TPC_4] = TPC_ID_DCORE1_TPC4, + [GAUDI2_DCORE1_ENGINE_ID_TPC_5] = TPC_ID_DCORE1_TPC5, + [GAUDI2_DCORE2_ENGINE_ID_TPC_0] = TPC_ID_DCORE2_TPC0, + [GAUDI2_DCORE2_ENGINE_ID_TPC_1] = TPC_ID_DCORE2_TPC1, + [GAUDI2_DCORE2_ENGINE_ID_TPC_2] = TPC_ID_DCORE2_TPC2, + [GAUDI2_DCORE2_ENGINE_ID_TPC_3] = TPC_ID_DCORE2_TPC3, + [GAUDI2_DCORE2_ENGINE_ID_TPC_4] = TPC_ID_DCORE2_TPC4, + [GAUDI2_DCORE2_ENGINE_ID_TPC_5] = TPC_ID_DCORE2_TPC5, + [GAUDI2_DCORE3_ENGINE_ID_TPC_0] = TPC_ID_DCORE3_TPC0, + [GAUDI2_DCORE3_ENGINE_ID_TPC_1] = TPC_ID_DCORE3_TPC1, + [GAUDI2_DCORE3_ENGINE_ID_TPC_2] = TPC_ID_DCORE3_TPC2, + [GAUDI2_DCORE3_ENGINE_ID_TPC_3] = TPC_ID_DCORE3_TPC3, + [GAUDI2_DCORE3_ENGINE_ID_TPC_4] = TPC_ID_DCORE3_TPC4, + [GAUDI2_DCORE3_ENGINE_ID_TPC_5] = TPC_ID_DCORE3_TPC5, + /* the PCI TPC is placed last (mapped liked HW) */ + [GAUDI2_DCORE0_ENGINE_ID_TPC_6] = TPC_ID_DCORE0_TPC6, +}; + +static const u32 gaudi2_mme_engine_id_to_mme_id[] = { + [GAUDI2_DCORE0_ENGINE_ID_MME] = MME_ID_DCORE0, + [GAUDI2_DCORE1_ENGINE_ID_MME] = MME_ID_DCORE1, + [GAUDI2_DCORE2_ENGINE_ID_MME] = MME_ID_DCORE2, + [GAUDI2_DCORE3_ENGINE_ID_MME] = MME_ID_DCORE3, +}; + +static const u32 gaudi2_edma_engine_id_to_edma_id[] = { + [GAUDI2_ENGINE_ID_PDMA_0] = DMA_CORE_ID_PDMA0, + [GAUDI2_ENGINE_ID_PDMA_1] = DMA_CORE_ID_PDMA1, + [GAUDI2_DCORE0_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA0, + [GAUDI2_DCORE0_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA1, + [GAUDI2_DCORE1_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA2, + [GAUDI2_DCORE1_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA3, + [GAUDI2_DCORE2_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA4, + [GAUDI2_DCORE2_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA5, + [GAUDI2_DCORE3_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA6, + [GAUDI2_DCORE3_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA7, + [GAUDI2_ENGINE_ID_KDMA] = DMA_CORE_ID_KDMA, +}; + const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = { GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0, GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0, @@ -1499,41 +1855,6 @@ static const char gaudi2_vdec_irq_name[GAUDI2_VDEC_MSIX_ENTRIES][GAUDI2_MAX_STRI "gaudi2 vdec s_1", "gaudi2 vdec s_1 abnormal" }; -static const u32 rtr_coordinates_to_rtr_id[NUM_OF_RTR_PER_DCORE * NUM_OF_DCORES] = { - RTR_ID_X_Y(2, 4), - RTR_ID_X_Y(3, 4), - RTR_ID_X_Y(4, 4), - RTR_ID_X_Y(5, 4), - RTR_ID_X_Y(6, 4), - RTR_ID_X_Y(7, 4), - RTR_ID_X_Y(8, 4), - RTR_ID_X_Y(9, 4), - RTR_ID_X_Y(10, 4), - RTR_ID_X_Y(11, 4), - RTR_ID_X_Y(12, 4), - RTR_ID_X_Y(13, 4), - RTR_ID_X_Y(14, 4), - RTR_ID_X_Y(15, 4), - RTR_ID_X_Y(16, 4), - RTR_ID_X_Y(17, 4), - RTR_ID_X_Y(2, 11), - RTR_ID_X_Y(3, 11), - RTR_ID_X_Y(4, 11), - RTR_ID_X_Y(5, 11), - RTR_ID_X_Y(6, 11), - RTR_ID_X_Y(7, 11), - RTR_ID_X_Y(8, 11), - RTR_ID_X_Y(9, 11), - RTR_ID_X_Y(0, 0),/* 24 no id */ - RTR_ID_X_Y(0, 0),/* 25 no id */ - RTR_ID_X_Y(0, 0),/* 26 no id */ - RTR_ID_X_Y(0, 0),/* 27 no id */ - RTR_ID_X_Y(14, 11), - RTR_ID_X_Y(15, 11), - RTR_ID_X_Y(16, 11), - RTR_ID_X_Y(17, 11) -}; - enum rtr_id { DCORE0_RTR0, DCORE0_RTR1, @@ -1784,6 +2105,12 @@ static void gaudi2_set_arc_id_cap(struct hl_device *hdev, u64 arc_id); static void gaudi2_memset_device_lbw(struct hl_device *hdev, u32 addr, u32 size, u32 val); static int gaudi2_send_job_to_kdma(struct hl_device *hdev, u64 src_addr, u64 dst_addr, u32 size, bool is_memset); +static bool gaudi2_get_tpc_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e); +static bool gaudi2_get_mme_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e); +static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e); static u64 gaudi2_mmu_scramble_addr(struct hl_device *hdev, u64 raw_addr); static void gaudi2_init_scrambler_hbm(struct hl_device *hdev) @@ -1988,6 +2315,8 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev) prop->hints_range_reservation = true; + prop->rotator_enabled_mask = BIT(NUM_OF_ROT) - 1; + if (hdev->pldm) prop->mmu_pgt_size = 0x800000; /* 8MB */ else @@ -2011,7 +2340,6 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev) prop->dmmu.num_hops = MMU_ARCH_6_HOPS; prop->dmmu.last_mask = LAST_MASK; prop->dmmu.host_resident = 1; - /* TODO: will be duplicated until implementing per-MMU props */ prop->dmmu.hop_table_size = prop->mmu_hop_table_size; prop->dmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; @@ -2027,7 +2355,6 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev) prop->pmmu.host_resident = 1; prop->pmmu.num_hops = MMU_ARCH_6_HOPS; prop->pmmu.last_mask = LAST_MASK; - /* TODO: will be duplicated until implementing per-MMU props */ prop->pmmu.hop_table_size = prop->mmu_hop_table_size; prop->pmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size; @@ -2084,11 +2411,14 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev) prop->pmmu_huge.end_addr = VA_HOST_SPACE_HPAGE_END; } + prop->max_num_of_engines = GAUDI2_ENGINE_ID_SIZE; prop->num_engine_cores = CPU_ID_MAX; prop->cfg_size = CFG_SIZE; prop->max_asid = MAX_ASID; prop->num_of_events = GAUDI2_EVENT_SIZE; + prop->supports_engine_modes = true; + prop->dc_power_default = DC_POWER_DEFAULT; prop->cb_pool_cb_cnt = GAUDI2_CB_POOL_CB_CNT; @@ -2107,6 +2437,8 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev) (num_sync_stream_queues * HL_RSVD_MONS); prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST; + prop->tpc_interrupt_id = GAUDI2_IRQ_NUM_TPC_ASSERT; + prop->unexpected_user_error_interrupt_id = GAUDI2_IRQ_NUM_UNEXPECTED_ERROR; prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER; @@ -2644,13 +2976,18 @@ static int gaudi2_early_init(struct hl_device *hdev) rc = hl_fw_read_preboot_status(hdev); if (rc) { if (hdev->reset_on_preboot_fail) + /* we are already on failure flow, so don't check if hw_fini fails. */ hdev->asic_funcs->hw_fini(hdev, true, false); goto pci_fini; } if (gaudi2_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); - hdev->asic_funcs->hw_fini(hdev, true, false); + rc = hdev->asic_funcs->hw_fini(hdev, true, false); + if (rc) { + dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc); + goto pci_fini; + } } return 0; @@ -2692,6 +3029,7 @@ static bool gaudi2_is_arc_tpc_owned(u64 arc_id) static void gaudi2_init_arcs(struct hl_device *hdev) { + struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; struct gaudi2_device *gaudi2 = hdev->asic_specific; u64 arc_id; u32 i; @@ -2721,6 +3059,10 @@ static void gaudi2_init_arcs(struct hl_device *hdev) gaudi2_set_arc_id_cap(hdev, arc_id); } + + /* Fetch ARC scratchpad address */ + hdev->asic_prop.engine_core_interrupt_reg_addr = + CFG_BASE + le32_to_cpu(dyn_regs->eng_arc_irq_ctrl); } static int gaudi2_scrub_arc_dccm(struct hl_device *hdev, u32 cpu_id) @@ -2772,16 +3114,21 @@ static int gaudi2_scrub_arc_dccm(struct hl_device *hdev, u32 cpu_id) return 0; } -static void gaudi2_scrub_arcs_dccm(struct hl_device *hdev) +static int gaudi2_scrub_arcs_dccm(struct hl_device *hdev) { u16 arc_id; + int rc; for (arc_id = CPU_ID_SCHED_ARC0 ; arc_id < CPU_ID_MAX ; arc_id++) { if (!gaudi2_is_arc_enabled(hdev, arc_id)) continue; - gaudi2_scrub_arc_dccm(hdev, arc_id); + rc = gaudi2_scrub_arc_dccm(hdev, arc_id); + if (rc) + return rc; } + + return 0; } static int gaudi2_late_init(struct hl_device *hdev) @@ -2805,7 +3152,13 @@ static int gaudi2_late_init(struct hl_device *hdev) } gaudi2_init_arcs(hdev); - gaudi2_scrub_arcs_dccm(hdev); + + rc = gaudi2_scrub_arcs_dccm(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to scrub arcs DCCM\n"); + goto disable_pci_access; + } + gaudi2_init_security(hdev); return 0; @@ -2989,6 +3342,13 @@ static void gaudi2_user_interrupt_setup(struct hl_device *hdev) struct asic_fixed_properties *prop = &hdev->asic_prop; int i, j, k; + /* Initialize TPC interrupt */ + HL_USR_INTR_STRUCT_INIT(hdev->tpc_interrupt, hdev, 0, HL_USR_INTERRUPT_TPC); + + /* Initialize general purpose interrupt */ + HL_USR_INTR_STRUCT_INIT(hdev->unexpected_error_interrupt, hdev, 0, + HL_USR_INTERRUPT_UNEXPECTED); + /* Initialize common user CQ interrupt */ HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev, HL_COMMON_USER_CQ_INTERRUPT_ID, HL_USR_INTERRUPT_CQ); @@ -3646,6 +4006,10 @@ static const char *gaudi2_irq_name(u16 irq_number) return "gaudi2 completion"; case GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ... GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM: return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM]; + case GAUDI2_IRQ_NUM_TPC_ASSERT: + return "gaudi2 tpc assert"; + case GAUDI2_IRQ_NUM_UNEXPECTED_ERROR: + return "gaudi2 tpc assert"; case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST: return "gaudi2 user completion"; default: @@ -3677,7 +4041,6 @@ static void gaudi2_dec_disable_msix(struct hl_device *hdev, u32 max_irq_num) static int gaudi2_dec_enable_msix(struct hl_device *hdev) { int rc, i, irq_init_cnt, irq, relative_idx; - irq_handler_t irq_handler; struct hl_dec *dec; for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM, irq_init_cnt = 0; @@ -3687,20 +4050,24 @@ static int gaudi2_dec_enable_msix(struct hl_device *hdev) irq = pci_irq_vector(hdev->pdev, i); relative_idx = i - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM; - irq_handler = (relative_idx % 2) ? - hl_irq_handler_dec_abnrm : - hl_irq_handler_user_interrupt; - - dec = hdev->dec + relative_idx / 2; - /* We pass different structures depending on the irq handler. For the abnormal * interrupt we pass hl_dec and for the regular interrupt we pass the relevant * user_interrupt entry + * + * TODO: change the dec abnrm to threaded irq */ - rc = request_irq(irq, irq_handler, 0, gaudi2_irq_name(i), - ((relative_idx % 2) ? - (void *) dec : - (void *) &hdev->user_interrupt[dec->core_id])); + + dec = hdev->dec + relative_idx / 2; + if (relative_idx % 2) { + rc = request_irq(irq, hl_irq_handler_dec_abnrm, 0, + gaudi2_irq_name(i), (void *) dec); + } else { + rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt, + hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT, + gaudi2_irq_name(i), + (void *) &hdev->user_interrupt[dec->core_id]); + } + if (rc) { dev_err(hdev->dev, "Failed to request IRQ %d", irq); goto free_dec_irqs; @@ -3719,7 +4086,6 @@ static int gaudi2_enable_msix(struct hl_device *hdev) struct asic_fixed_properties *prop = &hdev->asic_prop; struct gaudi2_device *gaudi2 = hdev->asic_specific; int rc, irq, i, j, user_irq_init_cnt; - irq_handler_t irq_handler; struct hl_cq *cq; if (gaudi2->hw_cap_initialized & HW_CAP_MSIX) @@ -3755,14 +4121,33 @@ static int gaudi2_enable_msix(struct hl_device *hdev) goto free_event_irq; } + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT); + rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt, + hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT, + gaudi2_irq_name(GAUDI2_IRQ_NUM_TPC_ASSERT), &hdev->tpc_interrupt); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_dec_irq; + } + + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR); + rc = request_irq(irq, hl_irq_handler_user_interrupt, 0, + gaudi2_irq_name(GAUDI2_IRQ_NUM_UNEXPECTED_ERROR), + &hdev->unexpected_error_interrupt); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_tpc_irq; + } + for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0; user_irq_init_cnt < prop->user_interrupt_count; i++, j++, user_irq_init_cnt++) { irq = pci_irq_vector(hdev->pdev, i); - irq_handler = hl_irq_handler_user_interrupt; + rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt, + hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT, + gaudi2_irq_name(i), &hdev->user_interrupt[j]); - rc = request_irq(irq, irq_handler, 0, gaudi2_irq_name(i), &hdev->user_interrupt[j]); if (rc) { dev_err(hdev->dev, "Failed to request IRQ %d", irq); goto free_user_irq; @@ -3780,9 +4165,13 @@ free_user_irq: irq = pci_irq_vector(hdev->pdev, i); free_irq(irq, &hdev->user_interrupt[j]); } - - gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1); - + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR); + free_irq(irq, &hdev->unexpected_error_interrupt); +free_tpc_irq: + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT); + free_irq(irq, &hdev->tpc_interrupt); +free_dec_irq: + gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_DEC_LAST + 1); free_event_irq: irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE); free_irq(irq, cq); @@ -3814,6 +4203,9 @@ static void gaudi2_sync_irqs(struct hl_device *hdev) synchronize_irq(irq); } + synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT)); + synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR)); + for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count; i++, j++) { irq = pci_irq_vector(hdev->pdev, i); @@ -3840,6 +4232,12 @@ static void gaudi2_disable_msix(struct hl_device *hdev) gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1); + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT); + free_irq(irq, &hdev->tpc_interrupt); + + irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR); + free_irq(irq, &hdev->unexpected_error_interrupt); + for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0; k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) { @@ -4037,7 +4435,6 @@ static int gaudi2_set_engine_cores(struct hl_device *hdev, u32 *core_ids, { int i, rc; - for (i = 0 ; i < num_cores ; i++) { if (gaudi2_is_arc_enabled(hdev, core_ids[i])) gaudi2_set_arc_running_mode(hdev, core_ids[i], core_command); @@ -4059,6 +4456,139 @@ static int gaudi2_set_engine_cores(struct hl_device *hdev, u32 *core_ids, return 0; } +static int gaudi2_set_tpc_engine_mode(struct hl_device *hdev, u32 engine_id, u32 engine_command) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base, reg_addr, reg_val, tpc_id; + + if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK)) + return 0; + + tpc_id = gaudi2_tpc_engine_id_to_tpc_id[engine_id]; + if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + tpc_id))) + return 0; + + reg_base = gaudi2_tpc_cfg_blocks_bases[tpc_id]; + reg_addr = reg_base + TPC_CFG_STALL_OFFSET; + reg_val = FIELD_PREP(DCORE0_TPC0_CFG_TPC_STALL_V_MASK, + !!(engine_command == HL_ENGINE_STALL)); + WREG32(reg_addr, reg_val); + + if (engine_command == HL_ENGINE_RESUME) { + reg_base = gaudi2_tpc_eml_cfg_blocks_bases[tpc_id]; + reg_addr = reg_base + TPC_EML_CFG_DBG_CNT_OFFSET; + RMWREG32(reg_addr, 0x1, DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK); + } + + return 0; +} + +static int gaudi2_set_mme_engine_mode(struct hl_device *hdev, u32 engine_id, u32 engine_command) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base, reg_addr, reg_val, mme_id; + + mme_id = gaudi2_mme_engine_id_to_mme_id[engine_id]; + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + mme_id))) + return 0; + + reg_base = gaudi2_mme_ctrl_lo_blocks_bases[mme_id]; + reg_addr = reg_base + MME_CTRL_LO_QM_STALL_OFFSET; + reg_val = FIELD_PREP(DCORE0_MME_CTRL_LO_QM_STALL_V_MASK, + !!(engine_command == HL_ENGINE_STALL)); + WREG32(reg_addr, reg_val); + + return 0; +} + +static int gaudi2_set_edma_engine_mode(struct hl_device *hdev, u32 engine_id, u32 engine_command) +{ + struct gaudi2_device *gaudi2 = hdev->asic_specific; + u32 reg_base, reg_addr, reg_val, edma_id; + + if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK)) + return 0; + + edma_id = gaudi2_edma_engine_id_to_edma_id[engine_id]; + if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + edma_id))) + return 0; + + reg_base = gaudi2_dma_core_blocks_bases[edma_id]; + reg_addr = reg_base + EDMA_CORE_CFG_STALL_OFFSET; + reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK, + !!(engine_command == HL_ENGINE_STALL)); + WREG32(reg_addr, reg_val); + + if (engine_command == HL_ENGINE_STALL) { + reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK, 0x1) | + FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK, 0x1); + WREG32(reg_addr, reg_val); + } + + return 0; +} + +static int gaudi2_set_engine_modes(struct hl_device *hdev, + u32 *engine_ids, u32 num_engines, u32 engine_command) +{ + int i, rc; + + for (i = 0 ; i < num_engines ; ++i) { + switch (engine_ids[i]) { + case GAUDI2_DCORE0_ENGINE_ID_TPC_0 ... GAUDI2_DCORE0_ENGINE_ID_TPC_5: + case GAUDI2_DCORE1_ENGINE_ID_TPC_0 ... GAUDI2_DCORE1_ENGINE_ID_TPC_5: + case GAUDI2_DCORE2_ENGINE_ID_TPC_0 ... GAUDI2_DCORE2_ENGINE_ID_TPC_5: + case GAUDI2_DCORE3_ENGINE_ID_TPC_0 ... GAUDI2_DCORE3_ENGINE_ID_TPC_5: + rc = gaudi2_set_tpc_engine_mode(hdev, engine_ids[i], engine_command); + if (rc) + return rc; + + break; + case GAUDI2_DCORE0_ENGINE_ID_MME: + case GAUDI2_DCORE1_ENGINE_ID_MME: + case GAUDI2_DCORE2_ENGINE_ID_MME: + case GAUDI2_DCORE3_ENGINE_ID_MME: + rc = gaudi2_set_mme_engine_mode(hdev, engine_ids[i], engine_command); + if (rc) + return rc; + + break; + case GAUDI2_DCORE0_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE0_ENGINE_ID_EDMA_1: + case GAUDI2_DCORE1_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE1_ENGINE_ID_EDMA_1: + case GAUDI2_DCORE2_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE2_ENGINE_ID_EDMA_1: + case GAUDI2_DCORE3_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE3_ENGINE_ID_EDMA_1: + rc = gaudi2_set_edma_engine_mode(hdev, engine_ids[i], engine_command); + if (rc) + return rc; + + break; + default: + dev_err(hdev->dev, "Invalid engine ID %u\n", engine_ids[i]); + return -EINVAL; + } + } + + return 0; +} + +static int gaudi2_set_engines(struct hl_device *hdev, u32 *engine_ids, + u32 num_engines, u32 engine_command) +{ + switch (engine_command) { + case HL_ENGINE_CORE_HALT: + case HL_ENGINE_CORE_RUN: + return gaudi2_set_engine_cores(hdev, engine_ids, num_engines, engine_command); + + case HL_ENGINE_STALL: + case HL_ENGINE_RESUME: + return gaudi2_set_engine_modes(hdev, engine_ids, num_engines, engine_command); + + default: + dev_err(hdev->dev, "failed to execute command id %u\n", engine_command); + return -EINVAL; + } +} + static void gaudi2_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset) { u32 wait_timeout_ms; @@ -5509,11 +6039,10 @@ static void gaudi2_send_hard_reset_cmd(struct hl_device *hdev) * gaudi2_execute_hard_reset - execute hard reset by driver/FW * * @hdev: pointer to the habanalabs device structure - * @reset_sleep_ms: sleep time in msec after reset * * This function executes hard reset based on if driver/FW should do the reset */ -static void gaudi2_execute_hard_reset(struct hl_device *hdev, u32 reset_sleep_ms) +static void gaudi2_execute_hard_reset(struct hl_device *hdev) { if (hdev->asic_prop.hard_reset_done_by_fw) { gaudi2_send_hard_reset_cmd(hdev); @@ -5531,17 +6060,37 @@ static void gaudi2_execute_hard_reset(struct hl_device *hdev, u32 reset_sleep_ms WREG32(mmPSOC_RESET_CONF_SW_ALL_RST, 1); } +static int gaudi2_get_soft_rst_done_indication(struct hl_device *hdev, u32 poll_timeout_us) +{ + int i, rc = 0; + u32 reg_val; + + for (i = 0 ; i < GAUDI2_RESET_POLL_CNT ; i++) + rc = hl_poll_timeout( + hdev, + mmCPU_RST_STATUS_TO_HOST, + reg_val, + reg_val == CPU_RST_STATUS_SOFT_RST_DONE, + 1000, + poll_timeout_us); + + if (rc) + dev_err(hdev->dev, "Timeout while waiting for FW to complete soft reset (0x%x)\n", + reg_val); + return rc; +} + /** * gaudi2_execute_soft_reset - execute soft reset by driver/FW * * @hdev: pointer to the habanalabs device structure - * @reset_sleep_ms: sleep time in msec after reset * @driver_performs_reset: true if driver should perform reset instead of f/w. + * @poll_timeout_us: time to wait for response from f/w. * * This function executes soft reset based on if driver/FW should do the reset */ -static void gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms, - bool driver_performs_reset) +static int gaudi2_execute_soft_reset(struct hl_device *hdev, bool driver_performs_reset, + u32 poll_timeout_us) { struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs; @@ -5554,7 +6103,8 @@ static void gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms WREG32(le32_to_cpu(dyn_regs->gic_host_soft_rst_irq), gaudi2_irq_map_table[GAUDI2_EVENT_CPU_SOFT_RESET].cpu_id); - return; + + return gaudi2_get_soft_rst_done_indication(hdev, poll_timeout_us); } /* Block access to engines, QMANs and SM during reset, these @@ -5569,17 +6119,14 @@ static void gaudi2_execute_soft_reset(struct hl_device *hdev, u32 reset_sleep_ms mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE + HL_BLOCK_SIZE); WREG32(mmPSOC_RESET_CONF_SOFT_RST, 1); + return 0; } -static void gaudi2_poll_btm_indication(struct hl_device *hdev, u32 reset_sleep_ms, - u32 poll_timeout_us) +static void gaudi2_poll_btm_indication(struct hl_device *hdev, u32 poll_timeout_us) { int i, rc = 0; u32 reg_val; - /* without this sleep reset will not work */ - msleep(reset_sleep_ms); - /* We poll the BTM done indication multiple times after reset due to * a HW errata 'GAUDI2_0300' */ @@ -5596,30 +6143,12 @@ static void gaudi2_poll_btm_indication(struct hl_device *hdev, u32 reset_sleep_m dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", reg_val); } -static void gaudi2_get_soft_rst_done_indication(struct hl_device *hdev, u32 poll_timeout_us) -{ - int i, rc = 0; - u32 reg_val; - - for (i = 0 ; i < GAUDI2_RESET_POLL_CNT ; i++) - rc = hl_poll_timeout( - hdev, - mmCPU_RST_STATUS_TO_HOST, - reg_val, - reg_val == CPU_RST_STATUS_SOFT_RST_DONE, - 1000, - poll_timeout_us); - - if (rc) - dev_err(hdev->dev, "Timeout while waiting for FW to complete soft reset (0x%x)\n", - reg_val); -} - -static void gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) +static int gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) { struct gaudi2_device *gaudi2 = hdev->asic_specific; u32 poll_timeout_us, reset_sleep_ms; bool driver_performs_reset = false; + int rc; if (hdev->pldm) { reset_sleep_ms = hard_reset ? GAUDI2_PLDM_HRESET_TIMEOUT_MSEC : @@ -5637,7 +6166,7 @@ static void gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_rese if (hard_reset) { driver_performs_reset = !hdev->asic_prop.hard_reset_done_by_fw; - gaudi2_execute_hard_reset(hdev, reset_sleep_ms); + gaudi2_execute_hard_reset(hdev); } else { /* * As we have to support also work with preboot only (which does not supports @@ -5647,11 +6176,13 @@ static void gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_rese */ driver_performs_reset = (hdev->fw_components == FW_TYPE_PREBOOT_CPU && !hdev->asic_prop.fw_security_enabled); - gaudi2_execute_soft_reset(hdev, reset_sleep_ms, driver_performs_reset); + rc = gaudi2_execute_soft_reset(hdev, driver_performs_reset, poll_timeout_us); + if (rc) + return rc; } skip_reset: - if (driver_performs_reset || hard_reset) + if (driver_performs_reset || hard_reset) { /* * Instead of waiting for BTM indication we should wait for preboot ready: * Consider the below scenario: @@ -5671,17 +6202,18 @@ skip_reset: * communicate with FW that is during reset. * to overcome this we will always wait to preboot ready indication */ - if ((hdev->fw_components & FW_TYPE_PREBOOT_CPU)) { - msleep(reset_sleep_ms); + + /* without this sleep reset will not work */ + msleep(reset_sleep_ms); + + if (hdev->fw_components & FW_TYPE_PREBOOT_CPU) hl_fw_wait_preboot_ready(hdev); - } else { - gaudi2_poll_btm_indication(hdev, reset_sleep_ms, poll_timeout_us); - } - else - gaudi2_get_soft_rst_done_indication(hdev, poll_timeout_us); + else + gaudi2_poll_btm_indication(hdev, poll_timeout_us); + } if (!gaudi2) - return; + return 0; gaudi2->dec_hw_cap_initialized &= ~(HW_CAP_DEC_MASK); gaudi2->tpc_hw_cap_initialized &= ~(HW_CAP_TPC_MASK); @@ -5708,6 +6240,7 @@ skip_reset: HW_CAP_PDMA_MASK | HW_CAP_EDMA_MASK | HW_CAP_MME_MASK | HW_CAP_ROT_MASK); } + return 0; } static int gaudi2_suspend(struct hl_device *hdev) @@ -6369,12 +6902,16 @@ static int gaudi2_compute_reset_late_init(struct hl_device *hdev) { struct gaudi2_device *gaudi2 = hdev->asic_specific; size_t irq_arr_size; + int rc; - /* TODO: missing gaudi2_nic_resume. - * Until implemented nic_hw_cap_initialized will remain zeroed - */ gaudi2_init_arcs(hdev); - gaudi2_scrub_arcs_dccm(hdev); + + rc = gaudi2_scrub_arcs_dccm(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to scrub arcs DCCM\n"); + return rc; + } + gaudi2_init_security(hdev); /* Unmask all IRQs since some could have been received during the soft reset */ @@ -6382,74 +6919,21 @@ static int gaudi2_compute_reset_late_init(struct hl_device *hdev) return hl_fw_unmask_irq_arr(hdev, gaudi2->hw_events, irq_arr_size); } -static void gaudi2_is_tpc_engine_idle(struct hl_device *hdev, int dcore, int inst, u32 offset, - struct iterate_module_ctx *ctx) -{ - struct gaudi2_tpc_idle_data *idle_data = ctx->data; - u32 tpc_cfg_sts, qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts; - bool is_eng_idle; - int engine_idx; - - if ((dcore == 0) && (inst == (NUM_DCORE0_TPC - 1))) - engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_6; - else - engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_0 + - dcore * GAUDI2_ENGINE_ID_DCORE_OFFSET + inst; - - tpc_cfg_sts = RREG32(mmDCORE0_TPC0_CFG_STATUS + offset); - qm_glbl_sts0 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS0 + offset); - qm_glbl_sts1 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS1 + offset); - qm_cgm_sts = RREG32(mmDCORE0_TPC0_QM_CGM_STS + offset); - - is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) && - IS_TPC_IDLE(tpc_cfg_sts); - *(idle_data->is_idle) &= is_eng_idle; - - if (idle_data->mask && !is_eng_idle) - set_bit(engine_idx, idle_data->mask); - - if (idle_data->e) - hl_engine_data_sprintf(idle_data->e, - idle_data->tpc_fmt, dcore, inst, - is_eng_idle ? "Y" : "N", - qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts); -} - -static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, - struct engines_data *e) +static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) { - u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_idle_ind_mask, - mme_arch_sts, dec_swreg15, dec_enabled_bit; + u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_sts0, dma_core_sts1; struct asic_fixed_properties *prop = &hdev->asic_prop; - const char *rot_fmt = "%-6d%-5d%-9s%#-14x%#-12x%s\n"; unsigned long *mask = (unsigned long *) mask_arr; - const char *edma_fmt = "%-6d%-6d%-9s%#-14x%#x\n"; - const char *mme_fmt = "%-5d%-6s%-9s%#-14x%#x\n"; - const char *nic_fmt = "%-5d%-9s%#-14x%#-12x\n"; - const char *pdma_fmt = "%-6d%-9s%#-14x%#x\n"; - const char *pcie_dec_fmt = "%-10d%-9s%#x\n"; - const char *dec_fmt = "%-6d%-5d%-9s%#x\n"; + const char *edma_fmt = "%-6d%-6d%-9s%#-14x%#-15x%#x\n"; bool is_idle = true, is_eng_idle; - u64 offset; - - struct gaudi2_tpc_idle_data tpc_idle_data = { - .tpc_fmt = "%-6d%-5d%-9s%#-14x%#-12x%#x\n", - .e = e, - .mask = mask, - .is_idle = &is_idle, - }; - struct iterate_module_ctx tpc_iter = { - .fn = &gaudi2_is_tpc_engine_idle, - .data = &tpc_idle_data, - }; - int engine_idx, i, j; + u64 offset; - /* EDMA, Two engines per Dcore */ if (e) hl_engine_data_sprintf(e, - "\nCORE EDMA is_idle QM_GLBL_STS0 DMA_CORE_IDLE_IND_MASK\n" - "---- ---- ------- ------------ ----------------------\n"); + "\nCORE EDMA is_idle QM_GLBL_STS0 DMA_CORE_STS0 DMA_CORE_STS1\n" + "---- ---- ------- ------------ ------------- -------------\n"); for (i = 0; i < NUM_OF_DCORES; i++) { for (j = 0 ; j < NUM_OF_EDMA_PER_DCORE ; j++) { @@ -6462,45 +6946,56 @@ static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask i * GAUDI2_ENGINE_ID_DCORE_OFFSET + j; offset = i * DCORE_OFFSET + j * DCORE_EDMA_OFFSET; - dma_core_idle_ind_mask = - RREG32(mmDCORE0_EDMA0_CORE_IDLE_IND_MASK + offset); + dma_core_sts0 = RREG32(mmDCORE0_EDMA0_CORE_STS0 + offset); + dma_core_sts1 = RREG32(mmDCORE0_EDMA0_CORE_STS1 + offset); qm_glbl_sts0 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS0 + offset); qm_glbl_sts1 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS1 + offset); qm_cgm_sts = RREG32(mmDCORE0_EDMA0_QM_CGM_STS + offset); is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) && - IS_DMA_IDLE(dma_core_idle_ind_mask); + IS_DMA_IDLE(dma_core_sts0) && !IS_DMA_HALTED(dma_core_sts1); is_idle &= is_eng_idle; if (mask && !is_eng_idle) set_bit(engine_idx, mask); if (e) - hl_engine_data_sprintf(e, edma_fmt, i, j, - is_eng_idle ? "Y" : "N", - qm_glbl_sts0, - dma_core_idle_ind_mask); + hl_engine_data_sprintf(e, edma_fmt, i, j, is_eng_idle ? "Y" : "N", + qm_glbl_sts0, dma_core_sts0, dma_core_sts1); } } - /* PDMA, Two engines in Full chip */ + return is_idle; +} + +static bool gaudi2_get_pdma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) +{ + u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_sts0, dma_core_sts1; + unsigned long *mask = (unsigned long *) mask_arr; + const char *pdma_fmt = "%-6d%-9s%#-14x%#-15x%#x\n"; + bool is_idle = true, is_eng_idle; + int engine_idx, i; + u64 offset; + if (e) hl_engine_data_sprintf(e, - "\nPDMA is_idle QM_GLBL_STS0 DMA_CORE_IDLE_IND_MASK\n" - "---- ------- ------------ ----------------------\n"); + "\nPDMA is_idle QM_GLBL_STS0 DMA_CORE_STS0 DMA_CORE_STS1\n" + "---- ------- ------------ ------------- -------------\n"); for (i = 0 ; i < NUM_OF_PDMA ; i++) { engine_idx = GAUDI2_ENGINE_ID_PDMA_0 + i; offset = i * PDMA_OFFSET; - dma_core_idle_ind_mask = RREG32(mmPDMA0_CORE_IDLE_IND_MASK + offset); + dma_core_sts0 = RREG32(mmPDMA0_CORE_STS0 + offset); + dma_core_sts1 = RREG32(mmPDMA0_CORE_STS1 + offset); qm_glbl_sts0 = RREG32(mmPDMA0_QM_GLBL_STS0 + offset); qm_glbl_sts1 = RREG32(mmPDMA0_QM_GLBL_STS1 + offset); qm_cgm_sts = RREG32(mmPDMA0_QM_CGM_STS + offset); is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) && - IS_DMA_IDLE(dma_core_idle_ind_mask); + IS_DMA_IDLE(dma_core_sts0) && !IS_DMA_HALTED(dma_core_sts1); is_idle &= is_eng_idle; if (mask && !is_eng_idle) @@ -6508,9 +7003,22 @@ static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask if (e) hl_engine_data_sprintf(e, pdma_fmt, i, is_eng_idle ? "Y" : "N", - qm_glbl_sts0, dma_core_idle_ind_mask); + qm_glbl_sts0, dma_core_sts0, dma_core_sts1); } + return is_idle; +} + +static bool gaudi2_get_nic_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) +{ + unsigned long *mask = (unsigned long *) mask_arr; + const char *nic_fmt = "%-5d%-9s%#-14x%#-12x\n"; + u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts; + bool is_idle = true, is_eng_idle; + int engine_idx, i; + u64 offset = 0; + /* NIC, twelve macros in Full chip */ if (e && hdev->nic_ports_mask) hl_engine_data_sprintf(e, @@ -6544,6 +7052,19 @@ static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask qm_glbl_sts0, qm_cgm_sts); } + return is_idle; +} + +static bool gaudi2_get_mme_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) +{ + u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, mme_arch_sts; + unsigned long *mask = (unsigned long *) mask_arr; + const char *mme_fmt = "%-5d%-6s%-9s%#-14x%#x\n"; + bool is_idle = true, is_eng_idle; + int engine_idx, i; + u64 offset; + if (e) hl_engine_data_sprintf(e, "\nMME Stub is_idle QM_GLBL_STS0 MME_ARCH_STATUS\n" @@ -6574,16 +7095,82 @@ static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask set_bit(engine_idx, mask); } - /* - * TPC - */ + return is_idle; +} + +static void gaudi2_is_tpc_engine_idle(struct hl_device *hdev, int dcore, int inst, u32 offset, + struct iterate_module_ctx *ctx) +{ + struct gaudi2_tpc_idle_data *idle_data = ctx->data; + u32 tpc_cfg_sts, qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts; + bool is_eng_idle; + int engine_idx; + + if ((dcore == 0) && (inst == (NUM_DCORE0_TPC - 1))) + engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_6; + else + engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_0 + + dcore * GAUDI2_ENGINE_ID_DCORE_OFFSET + inst; + + tpc_cfg_sts = RREG32(mmDCORE0_TPC0_CFG_STATUS + offset); + qm_glbl_sts0 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS0 + offset); + qm_glbl_sts1 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS1 + offset); + qm_cgm_sts = RREG32(mmDCORE0_TPC0_QM_CGM_STS + offset); + + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) && + IS_TPC_IDLE(tpc_cfg_sts); + *(idle_data->is_idle) &= is_eng_idle; + + if (idle_data->mask && !is_eng_idle) + set_bit(engine_idx, idle_data->mask); + + if (idle_data->e) + hl_engine_data_sprintf(idle_data->e, + idle_data->tpc_fmt, dcore, inst, + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts); +} + +static bool gaudi2_get_tpc_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + unsigned long *mask = (unsigned long *) mask_arr; + bool is_idle = true; + + struct gaudi2_tpc_idle_data tpc_idle_data = { + .tpc_fmt = "%-6d%-5d%-9s%#-14x%#-12x%#x\n", + .e = e, + .mask = mask, + .is_idle = &is_idle, + }; + struct iterate_module_ctx tpc_iter = { + .fn = &gaudi2_is_tpc_engine_idle, + .data = &tpc_idle_data, + }; + if (e && prop->tpc_enabled_mask) hl_engine_data_sprintf(e, - "\nCORE TPC is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_IDLE_IND_MASK\n" - "---- --- -------- ------------ ---------- ----------------------\n"); + "\nCORE TPC is_idle QM_GLBL_STS0 QM_CGM_STS STATUS\n" + "---- --- ------- ------------ ---------- ------\n"); gaudi2_iterate_tpcs(hdev, &tpc_iter); + return tpc_idle_data.is_idle; +} + +static bool gaudi2_get_decoder_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + unsigned long *mask = (unsigned long *) mask_arr; + const char *pcie_dec_fmt = "%-10d%-9s%#x\n"; + const char *dec_fmt = "%-6d%-5d%-9s%#x\n"; + bool is_idle = true, is_eng_idle; + u32 dec_swreg15, dec_enabled_bit; + int engine_idx, i, j; + u64 offset; + /* Decoders, two each Dcore and two shared PCIe decoders */ if (e && (prop->decoder_enabled_mask & (~PCIE_DEC_EN_MASK))) hl_engine_data_sprintf(e, @@ -6638,10 +7225,23 @@ static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask is_eng_idle ? "Y" : "N", dec_swreg15); } + return is_idle; +} + +static bool gaudi2_get_rotator_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) +{ + const char *rot_fmt = "%-6d%-5d%-9s%#-14x%#-14x%#x\n"; + unsigned long *mask = (unsigned long *) mask_arr; + u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts; + bool is_idle = true, is_eng_idle; + int engine_idx, i; + u64 offset; + if (e) hl_engine_data_sprintf(e, - "\nCORE ROT is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_STS0\n" - "---- ---- ------- ------------ ---------- -------------\n"); + "\nCORE ROT is_idle QM_GLBL_STS0 QM_GLBL_STS1 QM_CGM_STS\n" + "---- --- ------- ------------ ------------ ----------\n"); for (i = 0 ; i < NUM_OF_ROT ; i++) { engine_idx = GAUDI2_ENGINE_ID_ROT_0 + i; @@ -6660,12 +7260,28 @@ static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask if (e) hl_engine_data_sprintf(e, rot_fmt, i, 0, is_eng_idle ? "Y" : "N", - qm_glbl_sts0, qm_cgm_sts, "-"); + qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts); } return is_idle; } +static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, + struct engines_data *e) +{ + bool is_idle = true; + + is_idle &= gaudi2_get_edma_idle_status(hdev, mask_arr, mask_len, e); + is_idle &= gaudi2_get_pdma_idle_status(hdev, mask_arr, mask_len, e); + is_idle &= gaudi2_get_nic_idle_status(hdev, mask_arr, mask_len, e); + is_idle &= gaudi2_get_mme_idle_status(hdev, mask_arr, mask_len, e); + is_idle &= gaudi2_get_tpc_idle_status(hdev, mask_arr, mask_len, e); + is_idle &= gaudi2_get_decoder_idle_status(hdev, mask_arr, mask_len, e); + is_idle &= gaudi2_get_rotator_idle_status(hdev, mask_arr, mask_len, e); + + return is_idle; +} + static void gaudi2_hw_queues_lock(struct hl_device *hdev) __acquires(&gaudi2->hw_queues_lock) { @@ -7040,7 +7656,7 @@ static bool gaudi2_handle_ecc_event(struct hl_device *hdev, u16 event_type, memory_wrapper_idx = ecc_data->memory_wrapper_idx; gaudi2_print_event(hdev, event_type, !ecc_data->is_critical, - "ECC error detected. address: %#llx. Syndrom: %#llx. block id %u. critical %u.\n", + "ECC error detected. address: %#llx. Syndrom: %#llx. block id %u. critical %u.", ecc_address, ecc_syndrom, memory_wrapper_idx, ecc_data->is_critical); return !!ecc_data->is_critical; @@ -7352,10 +7968,8 @@ static void gaudi2_ack_module_razwi_event_handler(struct hl_device *hdev, case RAZWI_TPC: hbw_rtr_id = gaudi2_tpc_initiator_hbw_rtr_id[module_idx]; - /* TODO : remove this check and depend only on tpc routers table - * when SW-118828 is resolved - */ - if (!hdev->asic_prop.fw_security_enabled && + if (hl_is_fw_ver_below_1_9(hdev) && + !hdev->asic_prop.fw_security_enabled && ((module_idx == 0) || (module_idx == 1))) lbw_rtr_id = DCORE0_RTR0; else @@ -7526,297 +8140,115 @@ static void gaudi2_check_if_razwi_happened(struct hl_device *hdev) gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_ROT, mod_idx, 0, NULL); } -static const char *gaudi2_get_initiators_name(u32 rtr_id) -{ - switch (rtr_id) { - case DCORE0_RTR0: - return "DEC0/1/8/9, TPC24, PDMA0/1, PMMU, PCIE_IF, EDMA0/2, HMMU0/2/4/6, CPU"; - case DCORE0_RTR1: - return "TPC0/1"; - case DCORE0_RTR2: - return "TPC2/3"; - case DCORE0_RTR3: - return "TPC4/5"; - case DCORE0_RTR4: - return "MME0_SBTE0/1"; - case DCORE0_RTR5: - return "MME0_WAP0/SBTE2"; - case DCORE0_RTR6: - return "MME0_CTRL_WR/SBTE3"; - case DCORE0_RTR7: - return "MME0_WAP1/CTRL_RD/SBTE4"; - case DCORE1_RTR0: - return "MME1_WAP1/CTRL_RD/SBTE4"; - case DCORE1_RTR1: - return "MME1_CTRL_WR/SBTE3"; - case DCORE1_RTR2: - return "MME1_WAP0/SBTE2"; - case DCORE1_RTR3: - return "MME1_SBTE0/1"; - case DCORE1_RTR4: - return "TPC10/11"; - case DCORE1_RTR5: - return "TPC8/9"; - case DCORE1_RTR6: - return "TPC6/7"; - case DCORE1_RTR7: - return "DEC2/3, NIC0/1/2/3/4, ARC_FARM, KDMA, EDMA1/3, HMMU1/3/5/7"; - case DCORE2_RTR0: - return "DEC4/5, NIC5/6/7/8, EDMA4/6, HMMU8/10/12/14, ROT0"; - case DCORE2_RTR1: - return "TPC16/17"; - case DCORE2_RTR2: - return "TPC14/15"; - case DCORE2_RTR3: - return "TPC12/13"; - case DCORE2_RTR4: - return "MME2_SBTE0/1"; - case DCORE2_RTR5: - return "MME2_WAP0/SBTE2"; - case DCORE2_RTR6: - return "MME2_CTRL_WR/SBTE3"; - case DCORE2_RTR7: - return "MME2_WAP1/CTRL_RD/SBTE4"; - case DCORE3_RTR0: - return "MME3_WAP1/CTRL_RD/SBTE4"; - case DCORE3_RTR1: - return "MME3_CTRL_WR/SBTE3"; - case DCORE3_RTR2: - return "MME3_WAP0/SBTE2"; - case DCORE3_RTR3: - return "MME3_SBTE0/1"; - case DCORE3_RTR4: - return "TPC18/19"; - case DCORE3_RTR5: - return "TPC20/21"; - case DCORE3_RTR6: - return "TPC22/23"; - case DCORE3_RTR7: - return "DEC6/7, NIC9/10/11, EDMA5/7, HMMU9/11/13/15, ROT1, PSOC"; - default: - return "N/A"; - } -} - -static u16 gaudi2_get_razwi_initiators(u32 rtr_id, u16 *engines) -{ - switch (rtr_id) { - case DCORE0_RTR0: - engines[0] = GAUDI2_DCORE0_ENGINE_ID_DEC_0; - engines[1] = GAUDI2_DCORE0_ENGINE_ID_DEC_1; - engines[2] = GAUDI2_PCIE_ENGINE_ID_DEC_0; - engines[3] = GAUDI2_PCIE_ENGINE_ID_DEC_1; - engines[4] = GAUDI2_DCORE0_ENGINE_ID_TPC_6; - engines[5] = GAUDI2_ENGINE_ID_PDMA_0; - engines[6] = GAUDI2_ENGINE_ID_PDMA_1; - engines[7] = GAUDI2_ENGINE_ID_PCIE; - engines[8] = GAUDI2_DCORE0_ENGINE_ID_EDMA_0; - engines[9] = GAUDI2_DCORE1_ENGINE_ID_EDMA_0; - engines[10] = GAUDI2_ENGINE_ID_PSOC; - return 11; - - case DCORE0_RTR1: - engines[0] = GAUDI2_DCORE0_ENGINE_ID_TPC_0; - engines[1] = GAUDI2_DCORE0_ENGINE_ID_TPC_1; - return 2; - - case DCORE0_RTR2: - engines[0] = GAUDI2_DCORE0_ENGINE_ID_TPC_2; - engines[1] = GAUDI2_DCORE0_ENGINE_ID_TPC_3; - return 2; - - case DCORE0_RTR3: - engines[0] = GAUDI2_DCORE0_ENGINE_ID_TPC_4; - engines[1] = GAUDI2_DCORE0_ENGINE_ID_TPC_5; - return 2; - - case DCORE0_RTR4: - case DCORE0_RTR5: - case DCORE0_RTR6: - case DCORE0_RTR7: - engines[0] = GAUDI2_DCORE0_ENGINE_ID_MME; - return 1; - - case DCORE1_RTR0: - case DCORE1_RTR1: - case DCORE1_RTR2: - case DCORE1_RTR3: - engines[0] = GAUDI2_DCORE1_ENGINE_ID_MME; - return 1; - - case DCORE1_RTR4: - engines[0] = GAUDI2_DCORE1_ENGINE_ID_TPC_4; - engines[1] = GAUDI2_DCORE1_ENGINE_ID_TPC_5; - return 2; - - case DCORE1_RTR5: - engines[0] = GAUDI2_DCORE1_ENGINE_ID_TPC_2; - engines[1] = GAUDI2_DCORE1_ENGINE_ID_TPC_3; - return 2; - - case DCORE1_RTR6: - engines[0] = GAUDI2_DCORE1_ENGINE_ID_TPC_0; - engines[1] = GAUDI2_DCORE1_ENGINE_ID_TPC_1; - return 2; - - case DCORE1_RTR7: - engines[0] = GAUDI2_DCORE1_ENGINE_ID_DEC_0; - engines[1] = GAUDI2_DCORE1_ENGINE_ID_DEC_1; - engines[2] = GAUDI2_ENGINE_ID_NIC0_0; - engines[3] = GAUDI2_ENGINE_ID_NIC1_0; - engines[4] = GAUDI2_ENGINE_ID_NIC2_0; - engines[5] = GAUDI2_ENGINE_ID_NIC3_0; - engines[6] = GAUDI2_ENGINE_ID_NIC4_0; - engines[7] = GAUDI2_ENGINE_ID_ARC_FARM; - engines[8] = GAUDI2_ENGINE_ID_KDMA; - engines[9] = GAUDI2_DCORE0_ENGINE_ID_EDMA_1; - engines[10] = GAUDI2_DCORE1_ENGINE_ID_EDMA_1; - return 11; - - case DCORE2_RTR0: - engines[0] = GAUDI2_DCORE2_ENGINE_ID_DEC_0; - engines[1] = GAUDI2_DCORE2_ENGINE_ID_DEC_1; - engines[2] = GAUDI2_ENGINE_ID_NIC5_0; - engines[3] = GAUDI2_ENGINE_ID_NIC6_0; - engines[4] = GAUDI2_ENGINE_ID_NIC7_0; - engines[5] = GAUDI2_ENGINE_ID_NIC8_0; - engines[6] = GAUDI2_DCORE2_ENGINE_ID_EDMA_0; - engines[7] = GAUDI2_DCORE3_ENGINE_ID_EDMA_0; - engines[8] = GAUDI2_ENGINE_ID_ROT_0; - return 9; - - case DCORE2_RTR1: - engines[0] = GAUDI2_DCORE2_ENGINE_ID_TPC_4; - engines[1] = GAUDI2_DCORE2_ENGINE_ID_TPC_5; - return 2; - - case DCORE2_RTR2: - engines[0] = GAUDI2_DCORE2_ENGINE_ID_TPC_2; - engines[1] = GAUDI2_DCORE2_ENGINE_ID_TPC_3; - return 2; - - case DCORE2_RTR3: - engines[0] = GAUDI2_DCORE2_ENGINE_ID_TPC_0; - engines[1] = GAUDI2_DCORE2_ENGINE_ID_TPC_1; - return 2; - - case DCORE2_RTR4: - case DCORE2_RTR5: - case DCORE2_RTR6: - case DCORE2_RTR7: - engines[0] = GAUDI2_DCORE2_ENGINE_ID_MME; - return 1; - case DCORE3_RTR0: - case DCORE3_RTR1: - case DCORE3_RTR2: - case DCORE3_RTR3: - engines[0] = GAUDI2_DCORE3_ENGINE_ID_MME; - return 1; - case DCORE3_RTR4: - engines[0] = GAUDI2_DCORE3_ENGINE_ID_TPC_0; - engines[1] = GAUDI2_DCORE3_ENGINE_ID_TPC_1; - return 2; - case DCORE3_RTR5: - engines[0] = GAUDI2_DCORE3_ENGINE_ID_TPC_2; - engines[1] = GAUDI2_DCORE3_ENGINE_ID_TPC_3; - return 2; - case DCORE3_RTR6: - engines[0] = GAUDI2_DCORE3_ENGINE_ID_TPC_4; - engines[1] = GAUDI2_DCORE3_ENGINE_ID_TPC_5; - return 2; - case DCORE3_RTR7: - engines[0] = GAUDI2_DCORE3_ENGINE_ID_DEC_0; - engines[1] = GAUDI2_DCORE3_ENGINE_ID_DEC_1; - engines[2] = GAUDI2_ENGINE_ID_NIC9_0; - engines[3] = GAUDI2_ENGINE_ID_NIC10_0; - engines[4] = GAUDI2_ENGINE_ID_NIC11_0; - engines[5] = GAUDI2_DCORE2_ENGINE_ID_EDMA_1; - engines[6] = GAUDI2_DCORE3_ENGINE_ID_EDMA_1; - engines[7] = GAUDI2_ENGINE_ID_ROT_1; - engines[8] = GAUDI2_ENGINE_ID_ROT_0; - return 9; - default: - return 0; - } -} - -static void gaudi2_razwi_unmapped_addr_hbw_printf_info(struct hl_device *hdev, u32 rtr_id, - u64 rtr_ctrl_base_addr, bool is_write, - u64 *event_mask) +static int gaudi2_psoc_razwi_get_engines(struct gaudi2_razwi_info *razwi_info, u32 array_size, + u32 axuser_xy, u32 *base, u16 *eng_id, + char *eng_name) { - u16 engines[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR], num_of_eng; - u32 razwi_hi, razwi_lo; - u8 rd_wr_flag; - - num_of_eng = gaudi2_get_razwi_initiators(rtr_id, &engines[0]); - if (is_write) { - razwi_hi = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_ADDR_HI); - razwi_lo = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_ADDR_LO); - rd_wr_flag = HL_RAZWI_WRITE; + int i, num_of_eng = 0; + u16 str_size = 0; - /* Clear set indication */ - WREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_SET, 0x1); - } else { - razwi_hi = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_ADDR_HI); - razwi_lo = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_ADDR_LO); - rd_wr_flag = HL_RAZWI_READ; + for (i = 0 ; i < array_size ; i++) { + if (axuser_xy != razwi_info[i].axuser_xy) + continue; - /* Clear set indication */ - WREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_SET, 0x1); + eng_id[num_of_eng] = razwi_info[i].eng_id; + base[num_of_eng] = razwi_info[i].rtr_ctrl; + if (!num_of_eng) + str_size += snprintf(eng_name + str_size, + PSOC_RAZWI_ENG_STR_SIZE - str_size, "%s", + razwi_info[i].eng_name); + else + str_size += snprintf(eng_name + str_size, + PSOC_RAZWI_ENG_STR_SIZE - str_size, " or %s", + razwi_info[i].eng_name); + num_of_eng++; } - hl_handle_razwi(hdev, (u64)razwi_hi << 32 | razwi_lo, &engines[0], num_of_eng, - rd_wr_flag | HL_RAZWI_HBW, event_mask); - dev_err_ratelimited(hdev->dev, - "RAZWI PSOC unmapped HBW %s error, rtr id %u, address %#llx\n", - is_write ? "WR" : "RD", rtr_id, (u64)razwi_hi << 32 | razwi_lo); - - dev_err_ratelimited(hdev->dev, - "Initiators: %s\n", gaudi2_get_initiators_name(rtr_id)); + return num_of_eng; } -static void gaudi2_razwi_unmapped_addr_lbw_printf_info(struct hl_device *hdev, u32 rtr_id, - u64 rtr_ctrl_base_addr, bool is_write, - u64 *event_mask) +static bool gaudi2_handle_psoc_razwi_happened(struct hl_device *hdev, u32 razwi_reg, + u64 *event_mask) { - u16 engines[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR], num_of_eng; - u64 razwi_addr = CFG_BASE; - u8 rd_wr_flag; + u32 axuser_xy = RAZWI_GET_AXUSER_XY(razwi_reg), addr_hi = 0, addr_lo = 0; + u32 base[PSOC_RAZWI_MAX_ENG_PER_RTR]; + u16 num_of_eng, eng_id[PSOC_RAZWI_MAX_ENG_PER_RTR]; + char eng_name_str[PSOC_RAZWI_ENG_STR_SIZE]; + bool razwi_happened = false; + int i; - num_of_eng = gaudi2_get_razwi_initiators(rtr_id, &engines[0]); + num_of_eng = gaudi2_psoc_razwi_get_engines(common_razwi_info, ARRAY_SIZE(common_razwi_info), + axuser_xy, base, eng_id, eng_name_str); - if (is_write) { - razwi_addr += RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AW_ADDR); - rd_wr_flag = HL_RAZWI_WRITE; + /* If no match for XY coordinates, try to find it in MME razwi table */ + if (!num_of_eng) { + axuser_xy = RAZWI_GET_AXUSER_LOW_XY(razwi_reg); + num_of_eng = gaudi2_psoc_razwi_get_engines(mme_razwi_info, + ARRAY_SIZE(mme_razwi_info), + axuser_xy, base, eng_id, + eng_name_str); + } - /* Clear set indication */ - WREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AW_SET, 0x1); - } else { - razwi_addr += RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AR_ADDR); - rd_wr_flag = HL_RAZWI_READ; + for (i = 0 ; i < num_of_eng ; i++) { + if (RREG32(base[i] + DEC_RAZWI_HBW_AW_SET)) { + addr_hi = RREG32(base[i] + DEC_RAZWI_HBW_AW_ADDR_HI); + addr_lo = RREG32(base[i] + DEC_RAZWI_HBW_AW_ADDR_LO); + dev_err(hdev->dev, + "PSOC HBW AW RAZWI: %s, address (aligned to 128 byte): 0x%llX\n", + eng_name_str, ((u64)addr_hi << 32) + addr_lo); + hl_handle_razwi(hdev, ((u64)addr_hi << 32) + addr_lo, &eng_id[0], + num_of_eng, HL_RAZWI_HBW | HL_RAZWI_WRITE, event_mask); + razwi_happened = true; + } - /* Clear set indication */ - WREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AR_SET, 0x1); - } + if (RREG32(base[i] + DEC_RAZWI_HBW_AR_SET)) { + addr_hi = RREG32(base[i] + DEC_RAZWI_HBW_AR_ADDR_HI); + addr_lo = RREG32(base[i] + DEC_RAZWI_HBW_AR_ADDR_LO); + dev_err(hdev->dev, + "PSOC HBW AR RAZWI: %s, address (aligned to 128 byte): 0x%llX\n", + eng_name_str, ((u64)addr_hi << 32) + addr_lo); + hl_handle_razwi(hdev, ((u64)addr_hi << 32) + addr_lo, &eng_id[0], + num_of_eng, HL_RAZWI_HBW | HL_RAZWI_READ, event_mask); + razwi_happened = true; + } - hl_handle_razwi(hdev, razwi_addr, &engines[0], num_of_eng, rd_wr_flag | HL_RAZWI_LBW, - event_mask); - dev_err_ratelimited(hdev->dev, - "RAZWI PSOC unmapped LBW %s error, rtr id %u, address 0x%llX\n", - is_write ? "WR" : "RD", rtr_id, razwi_addr); + if (RREG32(base[i] + DEC_RAZWI_LBW_AW_SET)) { + addr_lo = RREG32(base[i] + DEC_RAZWI_LBW_AW_ADDR); + dev_err(hdev->dev, + "PSOC LBW AW RAZWI: %s, address (aligned to 128 byte): 0x%X\n", + eng_name_str, addr_lo); + hl_handle_razwi(hdev, addr_lo, &eng_id[0], + num_of_eng, HL_RAZWI_LBW | HL_RAZWI_WRITE, event_mask); + razwi_happened = true; + } - dev_err_ratelimited(hdev->dev, - "Initiators: %s\n", gaudi2_get_initiators_name(rtr_id)); + if (RREG32(base[i] + DEC_RAZWI_LBW_AR_SET)) { + addr_lo = RREG32(base[i] + DEC_RAZWI_LBW_AR_ADDR); + dev_err(hdev->dev, + "PSOC LBW AR RAZWI: %s, address (aligned to 128 byte): 0x%X\n", + eng_name_str, addr_lo); + hl_handle_razwi(hdev, addr_lo, &eng_id[0], + num_of_eng, HL_RAZWI_LBW | HL_RAZWI_READ, event_mask); + razwi_happened = true; + } + /* In common case the loop will break, when there is only one engine id, or + * several engines with the same router. The exceptional case is with psoc razwi + * from EDMA, where it's possible to get axuser id which fits 2 routers (2 + * interfaces of sft router). In this case, maybe the first router won't hold info + * and we will need to iterate on the other router. + */ + if (razwi_happened) + break; + } + + return razwi_happened; } /* PSOC RAZWI interrupt occurs only when trying to access a bad address */ static int gaudi2_ack_psoc_razwi_event_handler(struct hl_device *hdev, u64 *event_mask) { - u32 hbw_aw_set, hbw_ar_set, lbw_aw_set, lbw_ar_set, rtr_id, dcore_id, dcore_rtr_id, xy, - razwi_mask_info, razwi_intr = 0, error_count = 0; - int rtr_map_arr_len = NUM_OF_RTR_PER_DCORE * NUM_OF_DCORES; - u64 rtr_ctrl_base_addr; + u32 razwi_mask_info, razwi_intr = 0, error_count = 0; if (hdev->pldm || !(hdev->fw_components & FW_TYPE_LINUX)) { razwi_intr = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT); @@ -7825,63 +8257,22 @@ static int gaudi2_ack_psoc_razwi_event_handler(struct hl_device *hdev, u64 *even } razwi_mask_info = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO); - xy = FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK, razwi_mask_info); dev_err_ratelimited(hdev->dev, "PSOC RAZWI interrupt: Mask %d, AR %d, AW %d, AXUSER_L 0x%x AXUSER_H 0x%x\n", FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK, razwi_mask_info), FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK, razwi_mask_info), FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK, razwi_mask_info), - xy, + FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK, razwi_mask_info), FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK, razwi_mask_info)); - if (xy == 0) { - dev_err_ratelimited(hdev->dev, - "PSOC RAZWI interrupt: received event from 0 rtr coordinates\n"); - goto clear; - } - - /* Find router id by router coordinates */ - for (rtr_id = 0 ; rtr_id < rtr_map_arr_len ; rtr_id++) - if (rtr_coordinates_to_rtr_id[rtr_id] == xy) - break; - - if (rtr_id == rtr_map_arr_len) { + if (gaudi2_handle_psoc_razwi_happened(hdev, razwi_mask_info, event_mask)) + error_count++; + else dev_err_ratelimited(hdev->dev, - "PSOC RAZWI interrupt: invalid rtr coordinates (0x%x)\n", xy); - goto clear; - } - - /* Find router mstr_if register base */ - dcore_id = rtr_id / NUM_OF_RTR_PER_DCORE; - dcore_rtr_id = rtr_id % NUM_OF_RTR_PER_DCORE; - rtr_ctrl_base_addr = mmDCORE0_RTR0_CTRL_BASE + dcore_id * DCORE_OFFSET + - dcore_rtr_id * DCORE_RTR_OFFSET; - - hbw_aw_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AW_SET); - hbw_ar_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_HBW_AR_SET); - lbw_aw_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AW_SET); - lbw_ar_set = RREG32(rtr_ctrl_base_addr + DEC_RAZWI_LBW_AR_SET); - - if (hbw_aw_set) - gaudi2_razwi_unmapped_addr_hbw_printf_info(hdev, rtr_id, - rtr_ctrl_base_addr, true, event_mask); - - if (hbw_ar_set) - gaudi2_razwi_unmapped_addr_hbw_printf_info(hdev, rtr_id, - rtr_ctrl_base_addr, false, event_mask); + "PSOC RAZWI interrupt: invalid razwi info (0x%x)\n", + razwi_mask_info); - if (lbw_aw_set) - gaudi2_razwi_unmapped_addr_lbw_printf_info(hdev, rtr_id, - rtr_ctrl_base_addr, true, event_mask); - - if (lbw_ar_set) - gaudi2_razwi_unmapped_addr_lbw_printf_info(hdev, rtr_id, - rtr_ctrl_base_addr, false, event_mask); - - error_count++; - -clear: /* Clear Interrupts only on pldm or if f/w doesn't handle interrupts */ if (hdev->pldm || !(hdev->fw_components & FW_TYPE_LINUX)) WREG32(mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT, razwi_intr); @@ -7976,7 +8367,7 @@ static int gaudi2_handle_qman_err(struct hl_device *hdev, u16 event_type, u64 *e { u32 qid_base, error_count = 0; u64 qman_base; - u8 index; + u8 index = 0; switch (event_type) { case GAUDI2_EVENT_TPC0_QM ... GAUDI2_EVENT_TPC5_QM: @@ -8318,14 +8709,13 @@ static int gaudi2_handle_kdma_core_event(struct hl_device *hdev, u16 event_type, return error_count; } -static int gaudi2_handle_dma_core_event(struct hl_device *hdev, u16 event_type, - u64 intr_cause_data) +static int gaudi2_handle_dma_core_event(struct hl_device *hdev, u16 event_type, int sts_addr) { - u32 error_count = 0; + u32 error_count = 0, sts_val = RREG32(sts_addr); int i; for (i = 0 ; i < GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE ; i++) - if (intr_cause_data & BIT(i)) { + if (sts_val & BIT(i)) { gaudi2_print_event(hdev, event_type, true, "err cause: %s", gaudi2_dma_core_interrupts_cause[i]); error_count++; @@ -8336,6 +8726,27 @@ static int gaudi2_handle_dma_core_event(struct hl_device *hdev, u16 event_type, return error_count; } +static int gaudi2_handle_pdma_core_event(struct hl_device *hdev, u16 event_type, int pdma_idx) +{ + u32 sts_addr; + + sts_addr = mmPDMA0_CORE_ERR_CAUSE + pdma_idx * PDMA_OFFSET; + return gaudi2_handle_dma_core_event(hdev, event_type, sts_addr); +} + +static int gaudi2_handle_edma_core_event(struct hl_device *hdev, u16 event_type, int edma_idx) +{ + static const int edma_event_index_map[] = {2, 3, 0, 1, 6, 7, 4, 5}; + u32 sts_addr, index; + + index = edma_event_index_map[edma_idx]; + + sts_addr = mmDCORE0_EDMA0_CORE_ERR_CAUSE + + DCORE_OFFSET * (index / NUM_OF_EDMA_PER_DCORE) + + DCORE_EDMA_OFFSET * (index % NUM_OF_EDMA_PER_DCORE); + return gaudi2_handle_dma_core_event(hdev, event_type, sts_addr); +} + static void gaudi2_print_pcie_mstr_rr_mstr_if_razwi_info(struct hl_device *hdev, u64 *event_mask) { u32 mstr_if_base_addr = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE, razwi_happened_addr; @@ -8453,7 +8864,7 @@ static void gaudi2_handle_page_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu ? "PMMU" : "HMMU", addr, ((u64)axid_h << 32) + axid_l); hl_handle_page_fault(hdev, addr, 0, is_pmmu, event_mask); - WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE), 0); + WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0); } static void gaudi2_handle_access_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu) @@ -8534,7 +8945,7 @@ static int gaudi2_handle_sm_err(struct hl_device *hdev, u16 event_type, u8 sm_in continue; gaudi2_print_event(hdev, event_type, true, - "err cause: %s. %s: 0x%X\n", + "err cause: %s. %s: 0x%X", gaudi2_sm_sei_cause[i].cause_name, gaudi2_sm_sei_cause[i].log_name, sei_cause_log); @@ -8740,12 +9151,12 @@ static bool gaudi2_handle_hbm_mc_sei_err(struct hl_device *hdev, u16 event_type, if (cause_idx > GAUDI2_NUM_OF_HBM_SEI_CAUSE - 1) { gaudi2_print_event(hdev, event_type, true, "err cause: %s", - "Invalid HBM SEI event cause (%d) provided by FW\n", cause_idx); + "Invalid HBM SEI event cause (%d) provided by FW", cause_idx); return true; } gaudi2_print_event(hdev, event_type, !sei_data->hdr.is_critical, - "System %s Error Interrupt - HBM(%u) MC(%u) MC_CH(%u) MC_PC(%u). Error cause: %s\n", + "System %s Error Interrupt - HBM(%u) MC(%u) MC_CH(%u) MC_PC(%u). Error cause: %s", sei_data->hdr.is_critical ? "Critical" : "Non-critical", hbm_id, mc_id, sei_data->hdr.mc_channel, sei_data->hdr.mc_pseudo_channel, hbm_mc_sei_cause[cause_idx]); @@ -8869,7 +9280,7 @@ static void gaudi2_print_out_of_sync_info(struct hl_device *hdev, u16 event_type struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ]; gaudi2_print_event(hdev, event_type, false, - "FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n", + "FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d", le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci)); } @@ -8883,7 +9294,7 @@ static int gaudi2_handle_pcie_p2p_msix(struct hl_device *hdev, u16 event_type) if (p2p_intr) { gaudi2_print_event(hdev, event_type, true, - "pcie p2p transaction terminated due to security, req_id(0x%x)\n", + "pcie p2p transaction terminated due to security, req_id(0x%x)", RREG32(mmPCIE_WRAP_P2P_REQ_ID)); WREG32(mmPCIE_WRAP_P2P_INTR, 0x1); @@ -8892,7 +9303,7 @@ static int gaudi2_handle_pcie_p2p_msix(struct hl_device *hdev, u16 event_type) if (msix_gw_intr) { gaudi2_print_event(hdev, event_type, true, - "pcie msi-x gen denied due to vector num check failure, vec(0x%X)\n", + "pcie msi-x gen denied due to vector num check failure, vec(0x%X)", RREG32(mmPCIE_WRAP_MSIX_GW_VEC)); WREG32(mmPCIE_WRAP_MSIX_GW_INTR, 0x1); @@ -8954,7 +9365,7 @@ static void gaudi2_print_cpu_pkt_failure_info(struct hl_device *hdev, u16 event_ struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ]; gaudi2_print_event(hdev, event_type, false, - "FW reported sanity check failure, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n", + "FW reported sanity check failure, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d", le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci)); } @@ -8974,11 +9385,11 @@ static int hl_arc_event_handle(struct hl_device *hdev, u16 event_type, q = (struct hl_engine_arc_dccm_queue_full_irq *) &payload; gaudi2_print_event(hdev, event_type, true, - "ARC DCCM Full event: EngId: %u, Intr_type: %u, Qidx: %u\n", + "ARC DCCM Full event: EngId: %u, Intr_type: %u, Qidx: %u", engine_id, intr_type, q->queue_index); return 1; default: - gaudi2_print_event(hdev, event_type, true, "Unknown ARC event type\n"); + gaudi2_print_event(hdev, event_type, true, "Unknown ARC event type"); return 0; } } @@ -8987,7 +9398,7 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent { struct gaudi2_device *gaudi2 = hdev->asic_specific; bool reset_required = false, is_critical = false; - u32 index, ctl, reset_flags = HL_DRV_RESET_HARD, error_count = 0; + u32 index, ctl, reset_flags = 0, error_count = 0; u64 event_mask = 0; u16 event_type; @@ -9153,9 +9564,15 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR; break; - case GAUDI2_EVENT_HDMA2_CORE ... GAUDI2_EVENT_PDMA1_CORE: - error_count = gaudi2_handle_dma_core_event(hdev, event_type, - le64_to_cpu(eq_entry->intr_cause.intr_cause_data)); + case GAUDI2_EVENT_HDMA2_CORE ... GAUDI2_EVENT_HDMA5_CORE: + index = event_type - GAUDI2_EVENT_HDMA2_CORE; + error_count = gaudi2_handle_edma_core_event(hdev, event_type, index); + event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR; + break; + + case GAUDI2_EVENT_PDMA0_CORE ... GAUDI2_EVENT_PDMA1_CORE: + index = event_type - GAUDI2_EVENT_PDMA0_CORE; + error_count = gaudi2_handle_pdma_core_event(hdev, event_type, index); event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR; break; @@ -9381,7 +9798,7 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent break; case GAUDI2_EVENT_CPU_FP32_NOT_SUPPORTED: - case GAUDI2_EVENT_DEV_RESET_REQ: + case GAUDI2_EVENT_CPU_DEV_RESET_REQ: event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR; error_count = GAUDI2_NA_EVENT_CAUSE; is_critical = true; @@ -9403,12 +9820,18 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent gaudi2_print_event(hdev, event_type, true, "%d", event_type); else if (error_count == 0) gaudi2_print_event(hdev, event_type, true, - "No error cause for H/W event %u\n", event_type); + "No error cause for H/W event %u", event_type); - if ((gaudi2_irq_map_table[event_type].reset || reset_required) && - (hdev->hard_reset_on_fw_events || - (hdev->asic_prop.fw_security_enabled && is_critical))) - goto reset_device; + if ((gaudi2_irq_map_table[event_type].reset != EVENT_RESET_TYPE_NONE) || + reset_required) { + if (reset_required || + (gaudi2_irq_map_table[event_type].reset == EVENT_RESET_TYPE_HARD)) + reset_flags |= HL_DRV_RESET_HARD; + + if (hdev->hard_reset_on_fw_events || + (hdev->asic_prop.fw_security_enabled && is_critical)) + goto reset_device; + } /* Send unmask irq only for interrupts not classified as MSG */ if (!gaudi2_irq_map_table[event_type].msg) @@ -9426,6 +9849,10 @@ reset_device: } else { reset_flags |= HL_DRV_RESET_DELAY; } + /* escalate general hw errors to critical/fatal error */ + if (event_mask & HL_NOTIFIER_EVENT_GENERAL_HW_ERR) + hl_handle_critical_hw_err(hdev, event_type, &event_mask); + event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET; hl_device_cond_reset(hdev, reset_flags, event_mask); } @@ -9832,16 +10259,23 @@ static int gaudi2_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, v /* Create mapping on asic side */ mutex_lock(&hdev->mmu_lock); + rc = hl_mmu_map_contiguous(ctx, reserved_va_base, host_mem_dma_addr, SZ_2M); - hl_mmu_invalidate_cache_range(hdev, false, + if (rc) { + dev_err(hdev->dev, "Failed to create mapping on asic mmu\n"); + goto unreserve_va; + } + + rc = hl_mmu_invalidate_cache_range(hdev, false, MMU_OP_USERPTR | MMU_OP_SKIP_LOW_CACHE_INV, ctx->asid, reserved_va_base, SZ_2M); - mutex_unlock(&hdev->mmu_lock); if (rc) { - dev_err(hdev->dev, "Failed to create mapping on asic mmu\n"); + hl_mmu_unmap_contiguous(ctx, reserved_va_base, SZ_2M); goto unreserve_va; } + mutex_unlock(&hdev->mmu_lock); + /* Enable MMU on KDMA */ gaudi2_kdma_set_mmbp_asid(hdev, false, ctx->asid); @@ -9870,11 +10304,16 @@ static int gaudi2_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, v gaudi2_kdma_set_mmbp_asid(hdev, true, HL_KERNEL_ASID_ID); mutex_lock(&hdev->mmu_lock); - hl_mmu_unmap_contiguous(ctx, reserved_va_base, SZ_2M); - hl_mmu_invalidate_cache_range(hdev, false, MMU_OP_USERPTR, + + rc = hl_mmu_unmap_contiguous(ctx, reserved_va_base, SZ_2M); + if (rc) + goto unreserve_va; + + rc = hl_mmu_invalidate_cache_range(hdev, false, MMU_OP_USERPTR, ctx->asid, reserved_va_base, SZ_2M); - mutex_unlock(&hdev->mmu_lock); + unreserve_va: + mutex_unlock(&hdev->mmu_lock); hl_unreserve_va_block(hdev, ctx, reserved_va_base, SZ_2M); free_data_buffer: hl_asic_dma_free_coherent(hdev, SZ_2M, host_mem_virtual_addr, host_mem_dma_addr); @@ -9927,17 +10366,24 @@ static int gaudi2_internal_cb_pool_init(struct hl_device *hdev, struct hl_ctx *c } mutex_lock(&hdev->mmu_lock); + rc = hl_mmu_map_contiguous(ctx, hdev->internal_cb_va_base, hdev->internal_cb_pool_dma_addr, HOST_SPACE_INTERNAL_CB_SZ); - hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR); - mutex_unlock(&hdev->mmu_lock); - if (rc) goto unreserve_internal_cb_pool; + rc = hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR); + if (rc) + goto unmap_internal_cb_pool; + + mutex_unlock(&hdev->mmu_lock); + return 0; +unmap_internal_cb_pool: + hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ); unreserve_internal_cb_pool: + mutex_unlock(&hdev->mmu_lock); hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ); destroy_internal_cb_pool: gen_pool_destroy(hdev->internal_cb_pool); @@ -10724,6 +11170,7 @@ static const struct hl_asic_funcs gaudi2_funcs = { .access_dev_mem = hl_access_dev_mem, .set_dram_bar_base = gaudi2_set_hbm_bar_base, .set_engine_cores = gaudi2_set_engine_cores, + .set_engines = gaudi2_set_engines, .send_device_activity = gaudi2_send_device_activity, .set_dram_properties = gaudi2_set_dram_properties, .set_binning_masks = gaudi2_set_binning_masks, diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2P.h b/drivers/accel/habanalabs/gaudi2/gaudi2P.h index 2687404d9d21..0742046810f9 100644 --- a/drivers/accel/habanalabs/gaudi2/gaudi2P.h +++ b/drivers/accel/habanalabs/gaudi2/gaudi2P.h @@ -387,6 +387,8 @@ enum gaudi2_edma_id { * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode */ #define GAUDI2_NUM_USER_INTERRUPTS 255 +#define GAUDI2_NUM_RESERVED_INTERRUPTS 1 +#define GAUDI2_TOTAL_USER_INTERRUPTS (GAUDI2_NUM_USER_INTERRUPTS + GAUDI2_NUM_RESERVED_INTERRUPTS) enum gaudi2_irq_num { GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX, @@ -410,12 +412,15 @@ enum gaudi2_irq_num { GAUDI2_IRQ_NUM_SHARED_DEC0_ABNRM, GAUDI2_IRQ_NUM_SHARED_DEC1_NRM, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM, + GAUDI2_IRQ_NUM_DEC_LAST = GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM, GAUDI2_IRQ_NUM_COMPLETION, GAUDI2_IRQ_NUM_NIC_PORT_FIRST, GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1), + GAUDI2_IRQ_NUM_TPC_ASSERT, GAUDI2_IRQ_NUM_RESERVED_FIRST, - GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_USER_INTERRUPTS - 1), - GAUDI2_IRQ_NUM_USER_FIRST, + GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_TOTAL_USER_INTERRUPTS - 1), + GAUDI2_IRQ_NUM_UNEXPECTED_ERROR = RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT, + GAUDI2_IRQ_NUM_USER_FIRST = GAUDI2_IRQ_NUM_UNEXPECTED_ERROR + 1, GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1), GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1) }; diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c index 1dfbe293ecec..25b5368f37dd 100644 --- a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c +++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c @@ -2657,7 +2657,7 @@ int gaudi2_coresight_init(struct hl_device *hdev) /* * Mask out all the disabled binned offsets. * so when user request to configure a binned or masked out component, - * driver will ignore programing it ( happens when offset value is set to 0x0 ) + * driver will ignore programming it ( happens when offset value is set to 0x0 ) * this is being set in gaudi2_coresight_set_disabled_components */ diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h b/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h index e9ac87828221..e6664c4a2cf5 100644 --- a/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h +++ b/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h @@ -79,7 +79,6 @@ DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK) #define TPC_IDLE_MASK (DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \ - DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \ DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK | \ DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK | \ DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK | \ @@ -87,6 +86,8 @@ #define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40 + /* CGM_IDLE_MASK is valid for all engines CGM idle check */ #define CGM_IDLE_MASK DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_security.c b/drivers/accel/habanalabs/gaudi2/gaudi2_security.c index a212f82e6604..694735f9e6e6 100644 --- a/drivers/accel/habanalabs/gaudi2/gaudi2_security.c +++ b/drivers/accel/habanalabs/gaudi2/gaudi2_security.c @@ -1595,6 +1595,7 @@ static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = { mmDCORE0_TPC0_CFG_KERNEL_SRF_30, mmDCORE0_TPC0_CFG_KERNEL_SRF_31, mmDCORE0_TPC0_CFG_TPC_SB_L0CD, + mmDCORE0_TPC0_CFG_TPC_ID, mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC, mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0, mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1, diff --git a/drivers/accel/habanalabs/goya/goya.c b/drivers/accel/habanalabs/goya/goya.c index df65e9bdc18a..07d67878eac5 100644 --- a/drivers/accel/habanalabs/goya/goya.c +++ b/drivers/accel/habanalabs/goya/goya.c @@ -472,6 +472,7 @@ int goya_set_fixed_properties(struct hl_device *hdev) prop->max_pending_cs = GOYA_MAX_PENDING_CS; prop->first_available_user_interrupt = USHRT_MAX; + prop->tpc_interrupt_id = USHRT_MAX; for (i = 0 ; i < HL_MAX_DCORES ; i++) prop->first_available_cq[i] = USHRT_MAX; @@ -668,13 +669,18 @@ pci_init: rc = hl_fw_read_preboot_status(hdev); if (rc) { if (hdev->reset_on_preboot_fail) + /* we are already on failure flow, so don't check if hw_fini fails. */ hdev->asic_funcs->hw_fini(hdev, true, false); goto pci_fini; } if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) { dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n"); - hdev->asic_funcs->hw_fini(hdev, true, false); + rc = hdev->asic_funcs->hw_fini(hdev, true, false); + if (rc) { + dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc); + goto pci_fini; + } } if (!hdev->pldm) { @@ -2782,7 +2788,7 @@ disable_queues: return rc; } -static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) +static int goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) { struct goya_device *goya = hdev->asic_specific; u32 reset_timeout_ms, cpu_timeout_ms, status; @@ -2828,17 +2834,17 @@ static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) msleep(reset_timeout_ms); status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM); - if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) - dev_err(hdev->dev, - "Timeout while waiting for device to reset 0x%x\n", - status); + if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) { + dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status); + return -ETIMEDOUT; + } if (!hard_reset && goya) { goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME | HW_CAP_GOLDEN | HW_CAP_TPC); WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GOYA_ASYNC_EVENT_ID_SOFT_RESET); - return; + return 0; } /* Chicken bit to re-initiate boot sequencer flow */ @@ -2857,6 +2863,7 @@ static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset) memset(goya->events_stat, 0, sizeof(goya->events_stat)); } + return 0; } int goya_suspend(struct hl_device *hdev) diff --git a/drivers/accel/habanalabs/include/common/cpucp_if.h b/drivers/accel/habanalabs/include/common/cpucp_if.h index d713252a4f13..8bbe685458c4 100644 --- a/drivers/accel/habanalabs/include/common/cpucp_if.h +++ b/drivers/accel/habanalabs/include/common/cpucp_if.h @@ -357,6 +357,7 @@ struct hl_eq_addr_dec_intr_data { struct hl_eq_entry { struct hl_eq_header hdr; union { + __le64 data_placeholder; struct hl_eq_ecc_data ecc_data; struct hl_eq_hbm_ecc_data hbm_ecc_data; /* Gaudi1 HBM */ struct hl_eq_sm_sei_data sm_sei_data; @@ -661,6 +662,9 @@ enum pq_init_status { * CPUCP_PACKET_ACTIVE_STATUS_SET - * LKD sends FW indication whether device is free or in use, this indication is reported * also to the BMC. + * + * CPUCP_PACKET_REGISTER_INTERRUPTS - + * Packet to register interrupts indicating LKD is ready to receive events from FW. */ enum cpucp_packet_id { @@ -725,6 +729,8 @@ enum cpucp_packet_id { CPUCP_PACKET_RESERVED9, /* not used */ CPUCP_PACKET_RESERVED10, /* not used */ CPUCP_PACKET_RESERVED11, /* not used */ + CPUCP_PACKET_RESERVED12, /* internal */ + CPUCP_PACKET_REGISTER_INTERRUPTS, /* internal */ CPUCP_PACKET_ID_MAX /* must be last */ }; @@ -1127,6 +1133,7 @@ struct cpucp_security_info { * (0 = functional 1 = binned) * @interposer_version: Interposer version programmed in eFuse * @substrate_version: Substrate version programmed in eFuse + * @fw_hbm_region_size: Size in bytes of FW reserved region in HBM. * @fw_os_version: Firmware OS Version */ struct cpucp_info { @@ -1154,7 +1161,7 @@ struct cpucp_info { __u8 substrate_version; __u8 reserved2; struct cpucp_security_info sec_info; - __le32 reserved3; + __le32 fw_hbm_region_size; __u8 pll_map[PLL_MAP_LEN]; __le64 mme_binning_mask; __u8 fw_os_version[VERSION_MAX_LEN]; diff --git a/drivers/accel/habanalabs/include/common/hl_boot_if.h b/drivers/accel/habanalabs/include/common/hl_boot_if.h index 2256add057c5..c58d76a2705c 100644 --- a/drivers/accel/habanalabs/include/common/hl_boot_if.h +++ b/drivers/accel/habanalabs/include/common/hl_boot_if.h @@ -770,15 +770,23 @@ enum hl_components { HL_COMPONENTS_ARMCP, HL_COMPONENTS_CPLD, HL_COMPONENTS_UBOOT, + HL_COMPONENTS_FUSE, HL_COMPONENTS_MAX_NUM = 16 }; +#define NAME_MAX_LEN 32 /* bytes */ +struct hl_module_data { + __u8 name[NAME_MAX_LEN]; + __u8 version[VERSION_MAX_LEN]; +}; + /** * struct hl_component_versions - versions associated with hl component. * @struct_size: size of all the struct (including dynamic size of modules). * @modules_offset: offset of the modules field in this struct. * @component: version of the component itself. * @fw_os: Firmware OS Version. + * @comp_name: Name of the component. * @modules_mask: i'th bit (from LSB) is a flag - on if module i in enum * hl_modules is used. * @modules_counter: number of set bits in modules_mask. @@ -791,45 +799,14 @@ struct hl_component_versions { __le16 modules_offset; __u8 component[VERSION_MAX_LEN]; __u8 fw_os[VERSION_MAX_LEN]; + __u8 comp_name[NAME_MAX_LEN]; __le16 modules_mask; __u8 modules_counter; __u8 reserved[1]; - __u8 modules[][VERSION_MAX_LEN]; -}; - -/** - * struct hl_fw_versions - all versions (fuse, cpucp's components with their - * modules) - * @struct_size: size of all the struct (including dynamic size of components). - * @components_offset: offset of the components field in this struct. - * @fuse: silicon production FUSE information. - * @components_mask: i'th bit (from LSB) is a flag - on if component i in enum - * hl_components is used. - * @components_counter: number of set bits in components_mask. - * @reserved: reserved for future use. - * @components: versions of hl components. Index i corresponds to the i'th bit - * that is *on* in components_mask. For example, if - * components_mask=0b101, then *components represents arcpid and - * *(hl_component_versions*)((char*)components + 1') represents - * preboot, where 1' = components[0].struct_size. - */ -struct hl_fw_versions { - __le16 struct_size; - __le16 components_offset; - __u8 fuse[VERSION_MAX_LEN]; - __le16 components_mask; - __u8 components_counter; - __u8 reserved[1]; - struct hl_component_versions components[]; + struct hl_module_data modules[]; }; -/* Max size of struct hl_component_versions */ -#define HL_COMPONENT_VERSIONS_MAX_SIZE \ - (sizeof(struct hl_component_versions) + HL_MODULES_MAX_NUM * \ - VERSION_MAX_LEN) - -/* Max size of struct hl_fw_versions */ -#define HL_FW_VERSIONS_MAX_SIZE (sizeof(struct hl_fw_versions) + \ - HL_COMPONENTS_MAX_NUM * HL_COMPONENT_VERSIONS_MAX_SIZE) +/* Max size of fit size */ +#define HL_FW_VERSIONS_FIT_SIZE 4096 #endif /* HL_BOOT_IF_H */ diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h index 0bf3092bfeea..452b379f39f6 100644 --- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h +++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h @@ -164,6 +164,8 @@ #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x4800040 +#define mmDCORE0_TPC0_EML_CFG_DBG_CNT 0x40000 + #define SM_OBJS_PROT_BITS_OFFS 0x14000 #define DCORE_OFFSET (mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE) @@ -185,7 +187,10 @@ #define TPC_CFG_STALL_ON_ERR_OFFSET (mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE) #define TPC_CFG_TPC_INTR_MASK_OFFSET (mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE) #define TPC_CFG_MSS_CONFIG_OFFSET (mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE) +#define TPC_EML_CFG_DBG_CNT_OFFSET (mmDCORE0_TPC0_EML_CFG_DBG_CNT - mmDCORE0_TPC0_EML_CFG_BASE) +#define EDMA_CORE_CFG_STALL_OFFSET (mmDCORE0_EDMA0_CORE_CFG_1 - mmDCORE0_EDMA0_CORE_BASE) +#define MME_CTRL_LO_QM_STALL_OFFSET (mmDCORE0_MME_CTRL_LO_QM_STALL - mmDCORE0_MME_CTRL_LO_BASE) #define MME_ACC_INTR_MASK_OFFSET (mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE) #define MME_ACC_WR_AXI_AGG_COUT0_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE) #define MME_ACC_WR_AXI_AGG_COUT1_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE) diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2.h index 5b4f9e108798..0231d6c55b4a 100644 --- a/drivers/accel/habanalabs/include/gaudi2/gaudi2.h +++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2.h @@ -63,6 +63,8 @@ #define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START 0xFFF0F80000000000ull #define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END 0xFFF0FFFFFFFFFFFFull +#define RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT 256 + #define GAUDI2_MSIX_ENTRIES 512 #define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h index 50852cc80373..f661068d0c5f 100644 --- a/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h +++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2018-2021 HabanaLabs, Ltd. + * Copyright 2018-2022 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -958,7 +958,7 @@ enum gaudi2_async_event_id { GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1 = 1318, GAUDI2_EVENT_ARC_DCCM_FULL = 1319, GAUDI2_EVENT_CPU_FP32_NOT_SUPPORTED = 1320, - GAUDI2_EVENT_DEV_RESET_REQ = 1321, + GAUDI2_EVENT_CPU_DEV_RESET_REQ = 1321, GAUDI2_EVENT_SIZE, }; diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h index 82be01bea98e..ad01fc4e9940 100644 --- a/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h +++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h @@ -10,6 +10,12 @@ ** DO NOT EDIT BELOW ** ************************************/ +enum event_reset_type { + EVENT_RESET_TYPE_NONE, + EVENT_RESET_TYPE_COMPUTE, + EVENT_RESET_TYPE_HARD, +}; + #ifndef __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ #define __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ @@ -23,2650 +29,2650 @@ struct gaudi2_async_events_ids_map { }; static struct gaudi2_async_events_ids_map gaudi2_irq_map_table[] = { - { .fc_id = 0, .cpu_id = 0, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1, .cpu_id = 1, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 2, .cpu_id = 2, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 3, .cpu_id = 3, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 4, .cpu_id = 4, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 5, .cpu_id = 5, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 6, .cpu_id = 6, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 7, .cpu_id = 7, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 8, .cpu_id = 8, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 9, .cpu_id = 9, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 10, .cpu_id = 10, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 11, .cpu_id = 11, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 12, .cpu_id = 12, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 13, .cpu_id = 13, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 14, .cpu_id = 14, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 15, .cpu_id = 15, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 16, .cpu_id = 16, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 17, .cpu_id = 17, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 18, .cpu_id = 18, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 19, .cpu_id = 19, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 20, .cpu_id = 20, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 21, .cpu_id = 21, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 22, .cpu_id = 22, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 23, .cpu_id = 23, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 24, .cpu_id = 24, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 25, .cpu_id = 25, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 26, .cpu_id = 26, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 27, .cpu_id = 27, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 28, .cpu_id = 28, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 29, .cpu_id = 29, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 30, .cpu_id = 30, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 31, .cpu_id = 31, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 32, .cpu_id = 32, .valid = 1, - .msg = 0, .reset = 0, .name = "PCIE_CORE_SERR" }, - { .fc_id = 33, .cpu_id = 33, .valid = 1, - .msg = 0, .reset = 1, .name = "PCIE_CORE_DERR" }, - { .fc_id = 34, .cpu_id = 34, .valid = 1, - .msg = 0, .reset = 0, .name = "PCIE_IF_SERR" }, - { .fc_id = 35, .cpu_id = 35, .valid = 1, - .msg = 0, .reset = 1, .name = "PCIE_IF_DERR" }, - { .fc_id = 36, .cpu_id = 36, .valid = 1, - .msg = 0, .reset = 0, .name = "PCIE_PHY_SERR" }, - { .fc_id = 37, .cpu_id = 37, .valid = 1, - .msg = 0, .reset = 1, .name = "PCIE_PHY_DERR" }, - { .fc_id = 38, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC0_ECC_SERR" }, - { .fc_id = 39, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC1_ECC_SERR" }, - { .fc_id = 40, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC2_ECC_SERR" }, - { .fc_id = 41, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC3_ECC_SERR" }, - { .fc_id = 42, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC4_ECC_SERR" }, - { .fc_id = 43, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC5_ECC_SERR" }, - { .fc_id = 44, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC6_ECC_SERR" }, - { .fc_id = 45, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC7_ECC_SERR" }, - { .fc_id = 46, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC8_ECC_SERR" }, - { .fc_id = 47, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC9_ECC_SERR" }, - { .fc_id = 48, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC10_ECC_SERR" }, - { .fc_id = 49, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC11_ECC_SERR" }, - { .fc_id = 50, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC12_ECC_SERR" }, - { .fc_id = 51, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC13_ECC_SERR" }, - { .fc_id = 52, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC14_ECC_SERR" }, - { .fc_id = 53, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC15_ECC_SERR" }, - { .fc_id = 54, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC16_ECC_SERR" }, - { .fc_id = 55, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC17_ECC_SERR" }, - { .fc_id = 56, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC18_ECC_SERR" }, - { .fc_id = 57, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC19_ECC_SERR" }, - { .fc_id = 58, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC20_ECC_SERR" }, - { .fc_id = 59, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC21_ECC_SERR" }, - { .fc_id = 60, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC22_ECC_SERR" }, - { .fc_id = 61, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC23_ECC_SERR" }, - { .fc_id = 62, .cpu_id = 38, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC24_ECC_SERR" }, - { .fc_id = 63, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC0_ECC_DERR" }, - { .fc_id = 64, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC1_ECC_DERR" }, - { .fc_id = 65, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC2_ECC_DERR" }, - { .fc_id = 66, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC3_ECC_DERR" }, - { .fc_id = 67, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC4_ECC_DERR" }, - { .fc_id = 68, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC5_ECC_DERR" }, - { .fc_id = 69, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC6_ECC_DERR" }, - { .fc_id = 70, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC7_ECC_DERR" }, - { .fc_id = 71, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC8_ECC_DERR" }, - { .fc_id = 72, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC9_ECC_DERR" }, - { .fc_id = 73, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC10_ECC_DERR" }, - { .fc_id = 74, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC11_ECC_DERR" }, - { .fc_id = 75, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC12_ECC_DERR" }, - { .fc_id = 76, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC13_ECC_DERR" }, - { .fc_id = 77, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC14_ECC_DERR" }, - { .fc_id = 78, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC15_ECC_DERR" }, - { .fc_id = 79, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC16_ECC_DERR" }, - { .fc_id = 80, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC17_ECC_DERR" }, - { .fc_id = 81, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC18_ECC_DERR" }, - { .fc_id = 82, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC19_ECC_DERR" }, - { .fc_id = 83, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC20_ECC_DERR" }, - { .fc_id = 84, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC21_ECC_DERR" }, - { .fc_id = 85, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC22_ECC_DERR" }, - { .fc_id = 86, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC23_ECC_DERR" }, - { .fc_id = 87, .cpu_id = 39, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC24_ECC_DERR" }, - { .fc_id = 88, .cpu_id = 40, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_SBTE0_ECC_SERR" }, - { .fc_id = 89, .cpu_id = 40, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_SBTE1_ECC_SERR" }, - { .fc_id = 90, .cpu_id = 40, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_SBTE2_ECC_SERR" }, - { .fc_id = 91, .cpu_id = 40, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_SBTE3_ECC_SERR" }, - { .fc_id = 92, .cpu_id = 40, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_SBTE4_ECC_SERR" }, - { .fc_id = 93, .cpu_id = 40, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_CTRL_ECC_SERR" }, - { .fc_id = 94, .cpu_id = 40, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_WAP_ECC_SERR" }, - { .fc_id = 95, .cpu_id = 41, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_SBTE0_ECC_SERR" }, - { .fc_id = 96, .cpu_id = 41, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_SBTE1_ECC_SERR" }, - { .fc_id = 97, .cpu_id = 41, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_SBTE2_ECC_SERR" }, - { .fc_id = 98, .cpu_id = 41, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_SBTE3_ECC_SERR" }, - { .fc_id = 99, .cpu_id = 41, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_SBTE4_ECC_SERR" }, - { .fc_id = 100, .cpu_id = 41, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_CTRL_ECC_SERR" }, - { .fc_id = 101, .cpu_id = 41, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_WAP_ECC_SERR" }, - { .fc_id = 102, .cpu_id = 42, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_SBTE0_ECC_SERR" }, - { .fc_id = 103, .cpu_id = 42, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_SBTE1_ECC_SERR" }, - { .fc_id = 104, .cpu_id = 42, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_SBTE2_ECC_SERR" }, - { .fc_id = 105, .cpu_id = 42, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_SBTE3_ECC_SERR" }, - { .fc_id = 106, .cpu_id = 42, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_SBTE4_ECC_SERR" }, - { .fc_id = 107, .cpu_id = 42, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_CTRL_ECC_SERR" }, - { .fc_id = 108, .cpu_id = 42, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_WAP_ECC_SERR" }, - { .fc_id = 109, .cpu_id = 43, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_SBTE0_ECC_SERR" }, - { .fc_id = 110, .cpu_id = 43, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_SBTE1_ECC_SERR" }, - { .fc_id = 111, .cpu_id = 43, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_SBTE2_ECC_SERR" }, - { .fc_id = 112, .cpu_id = 43, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_SBTE3_ECC_SERR" }, - { .fc_id = 113, .cpu_id = 43, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_SBTE4_ECC_SERR" }, - { .fc_id = 114, .cpu_id = 43, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_CTRL_ECC_SERR" }, - { .fc_id = 115, .cpu_id = 43, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_WAP_ECC_SERR" }, - { .fc_id = 116, .cpu_id = 44, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE0_ECC_DERR" }, - { .fc_id = 117, .cpu_id = 44, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE1_ECC_DERR" }, - { .fc_id = 118, .cpu_id = 44, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE2_ECC_DERR" }, - { .fc_id = 119, .cpu_id = 44, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE3_ECC_DERR" }, - { .fc_id = 120, .cpu_id = 44, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE4_ECC_DERR" }, - { .fc_id = 121, .cpu_id = 44, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_CTRL_ECC_DERR" }, - { .fc_id = 122, .cpu_id = 44, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_WAP_ECC_DERR" }, - { .fc_id = 123, .cpu_id = 45, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE0_ECC_DERR" }, - { .fc_id = 124, .cpu_id = 45, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE1_ECC_DERR" }, - { .fc_id = 125, .cpu_id = 45, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE2_ECC_DERR" }, - { .fc_id = 126, .cpu_id = 45, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE3_ECC_DERR" }, - { .fc_id = 127, .cpu_id = 45, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE4_ECC_DERR" }, - { .fc_id = 128, .cpu_id = 45, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_CTRL_ECC_DERR" }, - { .fc_id = 129, .cpu_id = 45, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_WAP_ECC_DERR" }, - { .fc_id = 130, .cpu_id = 46, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE0_ECC_DERR" }, - { .fc_id = 131, .cpu_id = 46, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE1_ECC_DERR" }, - { .fc_id = 132, .cpu_id = 46, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE2_ECC_DERR" }, - { .fc_id = 133, .cpu_id = 46, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE3_ECC_DERR" }, - { .fc_id = 134, .cpu_id = 46, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE4_ECC_DERR" }, - { .fc_id = 135, .cpu_id = 46, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_CTRL_ECC_DERR" }, - { .fc_id = 136, .cpu_id = 46, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_WAP_ECC_DERR" }, - { .fc_id = 137, .cpu_id = 47, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE0_ECC_DERR" }, - { .fc_id = 138, .cpu_id = 47, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE1_ECC_DERR" }, - { .fc_id = 139, .cpu_id = 47, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE2_ECC_DERR" }, - { .fc_id = 140, .cpu_id = 47, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE3_ECC_DERR" }, - { .fc_id = 141, .cpu_id = 47, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE4_ECC_DERR" }, - { .fc_id = 142, .cpu_id = 47, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_CTRL_ECC_DERR" }, - { .fc_id = 143, .cpu_id = 47, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_WAP_ECC_DERR" }, - { .fc_id = 144, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA2_ECC_SERR" }, - { .fc_id = 145, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA3_ECC_SERR" }, - { .fc_id = 146, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA0_ECC_SERR" }, - { .fc_id = 147, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA1_ECC_SERR" }, - { .fc_id = 148, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA6_ECC_SERR" }, - { .fc_id = 149, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA7_ECC_SERR" }, - { .fc_id = 150, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA4_ECC_SERR" }, - { .fc_id = 151, .cpu_id = 48, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA5_ECC_SERR" }, - { .fc_id = 152, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA2_ECC_DERR" }, - { .fc_id = 153, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA3_ECC_DERR" }, - { .fc_id = 154, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA0_ECC_DERR" }, - { .fc_id = 155, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA1_ECC_DERR" }, - { .fc_id = 156, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA6_ECC_DERR" }, - { .fc_id = 157, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA7_ECC_DERR" }, - { .fc_id = 158, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA4_ECC_DERR" }, - { .fc_id = 159, .cpu_id = 49, .valid = 1, - .msg = 0, .reset = 1, .name = "HDMA5_ECC_DERR" }, - { .fc_id = 160, .cpu_id = 50, .valid = 1, - .msg = 0, .reset = 0, .name = "KDMA0_ECC_SERR" }, - { .fc_id = 161, .cpu_id = 51, .valid = 1, - .msg = 0, .reset = 0, .name = "PDMA0_ECC_SERR" }, - { .fc_id = 162, .cpu_id = 51, .valid = 1, - .msg = 0, .reset = 0, .name = "PDMA1_ECC_SERR" }, - { .fc_id = 163, .cpu_id = 52, .valid = 1, - .msg = 0, .reset = 1, .name = "KDMA0_ECC_DERR" }, - { .fc_id = 164, .cpu_id = 53, .valid = 1, - .msg = 0, .reset = 1, .name = "PDMA0_ECC_DERR" }, - { .fc_id = 165, .cpu_id = 53, .valid = 1, - .msg = 0, .reset = 1, .name = "PDMA1_ECC_DERR" }, - { .fc_id = 166, .cpu_id = 54, .valid = 1, - .msg = 0, .reset = 0, .name = "CPU_IF_ECC_SERR" }, - { .fc_id = 167, .cpu_id = 55, .valid = 1, - .msg = 0, .reset = 1, .name = "CPU_IF_ECC_DERR" }, - { .fc_id = 168, .cpu_id = 56, .valid = 1, - .msg = 0, .reset = 0, .name = "PSOC_MEM_SERR" }, - { .fc_id = 169, .cpu_id = 57, .valid = 1, - .msg = 0, .reset = 1, .name = "PSOC_MEM_DERR" }, - { .fc_id = 170, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM0_ECC_SERR" }, - { .fc_id = 171, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM1_ECC_SERR" }, - { .fc_id = 172, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM2_ECC_SERR" }, - { .fc_id = 173, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM3_ECC_SERR" }, - { .fc_id = 174, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM4_ECC_SERR" }, - { .fc_id = 175, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM5_ECC_SERR" }, - { .fc_id = 176, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM6_ECC_SERR" }, - { .fc_id = 177, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM7_ECC_SERR" }, - { .fc_id = 178, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM8_ECC_SERR" }, - { .fc_id = 179, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM9_ECC_SERR" }, - { .fc_id = 180, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM10_ECC_SERR" }, - { .fc_id = 181, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM11_ECC_SERR" }, - { .fc_id = 182, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM12_ECC_SERR" }, - { .fc_id = 183, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM13_ECC_SERR" }, - { .fc_id = 184, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM14_ECC_SERR" }, - { .fc_id = 185, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM15_ECC_SERR" }, - { .fc_id = 186, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM16_ECC_SERR" }, - { .fc_id = 187, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM17_ECC_SERR" }, - { .fc_id = 188, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM18_ECC_SERR" }, - { .fc_id = 189, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM19_ECC_SERR" }, - { .fc_id = 190, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM20_ECC_SERR" }, - { .fc_id = 191, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM21_ECC_SERR" }, - { .fc_id = 192, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM22_ECC_SERR" }, - { .fc_id = 193, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM23_ECC_SERR" }, - { .fc_id = 194, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM24_ECC_SERR" }, - { .fc_id = 195, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM25_ECC_SERR" }, - { .fc_id = 196, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM26_ECC_SERR" }, - { .fc_id = 197, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM27_ECC_SERR" }, - { .fc_id = 198, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM28_ECC_SERR" }, - { .fc_id = 199, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM29_ECC_SERR" }, - { .fc_id = 200, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM30_ECC_SERR" }, - { .fc_id = 201, .cpu_id = 58, .valid = 1, - .msg = 0, .reset = 0, .name = "SRAM31_ECC_SERR" }, - { .fc_id = 202, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM0_ECC_DERR" }, - { .fc_id = 203, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM1_ECC_DERR" }, - { .fc_id = 204, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM2_ECC_DERR" }, - { .fc_id = 205, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM3_ECC_DERR" }, - { .fc_id = 206, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM4_ECC_DERR" }, - { .fc_id = 207, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM5_ECC_DERR" }, - { .fc_id = 208, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM6_ECC_DERR" }, - { .fc_id = 209, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM7_ECC_DERR" }, - { .fc_id = 210, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM8_ECC_DERR" }, - { .fc_id = 211, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM9_ECC_DERR" }, - { .fc_id = 212, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM10_ECC_DERR" }, - { .fc_id = 213, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM11_ECC_DERR" }, - { .fc_id = 214, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM12_ECC_DERR" }, - { .fc_id = 215, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM13_ECC_DERR" }, - { .fc_id = 216, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM14_ECC_DERR" }, - { .fc_id = 217, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM15_ECC_DERR" }, - { .fc_id = 218, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM16_ECC_DERR" }, - { .fc_id = 219, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM17_ECC_DERR" }, - { .fc_id = 220, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM18_ECC_DERR" }, - { .fc_id = 221, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM19_ECC_DERR" }, - { .fc_id = 222, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM20_ECC_DERR" }, - { .fc_id = 223, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM21_ECC_DERR" }, - { .fc_id = 224, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM22_ECC_DERR" }, - { .fc_id = 225, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM23_ECC_DERR" }, - { .fc_id = 226, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM24_ECC_DERR" }, - { .fc_id = 227, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM25_ECC_DERR" }, - { .fc_id = 228, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM26_ECC_DERR" }, - { .fc_id = 229, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM27_ECC_DERR" }, - { .fc_id = 230, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM28_ECC_DERR" }, - { .fc_id = 231, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM29_ECC_DERR" }, - { .fc_id = 232, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM30_ECC_DERR" }, - { .fc_id = 233, .cpu_id = 59, .valid = 1, - .msg = 0, .reset = 1, .name = "SRAM31_ECC_DERR" }, - { .fc_id = 234, .cpu_id = 60, .valid = 1, - .msg = 0, .reset = 1, .name = "GIC500" }, - { .fc_id = 235, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_0_MC0_ECC_SERR" }, - { .fc_id = 236, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_1_MC0_ECC_SERR" }, - { .fc_id = 237, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_2_MC0_ECC_SERR" }, - { .fc_id = 238, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_3_MC0_ECC_SERR" }, - { .fc_id = 239, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_4_MC0_ECC_SERR" }, - { .fc_id = 240, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_5_MC0_ECC_SERR" }, - { .fc_id = 241, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_0_MC1_ECC_SERR" }, - { .fc_id = 242, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_1_MC1_ECC_SERR" }, - { .fc_id = 243, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_2_MC1_ECC_SERR" }, - { .fc_id = 244, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_3_MC1_ECC_SERR" }, - { .fc_id = 245, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_4_MC1_ECC_SERR" }, - { .fc_id = 246, .cpu_id = 61, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM_5_MC1_ECC_SERR" }, - { .fc_id = 247, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_0_MC0_ECC_DERR" }, - { .fc_id = 248, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_1_MC0_ECC_DERR" }, - { .fc_id = 249, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_2_MC0_ECC_DERR" }, - { .fc_id = 250, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_3_MC0_ECC_DERR" }, - { .fc_id = 251, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_4_MC0_ECC_DERR" }, - { .fc_id = 252, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_5_MC0_ECC_DERR" }, - { .fc_id = 253, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_0_MC1_ECC_DERR" }, - { .fc_id = 254, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_1_MC1_ECC_DERR" }, - { .fc_id = 255, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_2_MC1_ECC_DERR" }, - { .fc_id = 256, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_3_MC1_ECC_DERR" }, - { .fc_id = 257, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_4_MC1_ECC_DERR" }, - { .fc_id = 258, .cpu_id = 62, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_5_MC1_ECC_DERR" }, - { .fc_id = 259, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_0_ECC_SERR" }, - { .fc_id = 260, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_1_ECC_SERR" }, - { .fc_id = 261, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_2_ECC_SERR" }, - { .fc_id = 262, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_3_ECC_SERR" }, - { .fc_id = 263, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_8_ECC_SERR" }, - { .fc_id = 264, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_9_ECC_SERR" }, - { .fc_id = 265, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_10_ECC_SERR" }, - { .fc_id = 266, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_11_ECC_SERR" }, - { .fc_id = 267, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_7_ECC_SERR" }, - { .fc_id = 268, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_6_ECC_SERR" }, - { .fc_id = 269, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_5_ECC_SERR" }, - { .fc_id = 270, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_4_ECC_SERR" }, - { .fc_id = 271, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_15_ECC_SERR" }, - { .fc_id = 272, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_14_ECC_SERR" }, - { .fc_id = 273, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_13_ECC_SERR" }, - { .fc_id = 274, .cpu_id = 63, .valid = 1, - .msg = 0, .reset = 0, .name = "HMMU_12_ECC_SERR" }, - { .fc_id = 275, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_0_ECC_DERR" }, - { .fc_id = 276, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_1_ECC_DERR" }, - { .fc_id = 277, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_2_ECC_DERR" }, - { .fc_id = 278, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_3_ECC_DERR" }, - { .fc_id = 279, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_8_ECC_DERR" }, - { .fc_id = 280, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_9_ECC_DERR" }, - { .fc_id = 281, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_10_ECC_DERR" }, - { .fc_id = 282, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_11_ECC_DERR" }, - { .fc_id = 283, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_7_ECC_DERR" }, - { .fc_id = 284, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_6_ECC_DERR" }, - { .fc_id = 285, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_5_ECC_DERR" }, - { .fc_id = 286, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_4_ECC_DERR" }, - { .fc_id = 287, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_15_ECC_DERR" }, - { .fc_id = 288, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_14_ECC_DERR" }, - { .fc_id = 289, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_13_ECC_DERR" }, - { .fc_id = 290, .cpu_id = 64, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_12_ECC_DERR" }, - { .fc_id = 291, .cpu_id = 65, .valid = 1, - .msg = 0, .reset = 0, .name = "PMMU_ECC_SERR" }, - { .fc_id = 292, .cpu_id = 66, .valid = 1, - .msg = 0, .reset = 1, .name = "PMMU_ECC_DERR" }, - { .fc_id = 293, .cpu_id = 67, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 294, .cpu_id = 68, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 295, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC0_VCD_ECC_SERR" }, - { .fc_id = 296, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC1_VCD_ECC_SERR" }, - { .fc_id = 297, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC2_VCD_ECC_SERR" }, - { .fc_id = 298, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC3_VCD_ECC_SERR" }, - { .fc_id = 299, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC4_VCD_ECC_SERR" }, - { .fc_id = 300, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC5_VCD_ECC_SERR" }, - { .fc_id = 301, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC6_VCD_ECC_SERR" }, - { .fc_id = 302, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC7_VCD_ECC_SERR" }, - { .fc_id = 303, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC8_VCD_ECC_SERR" }, - { .fc_id = 304, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC9_VCD_ECC_SERR" }, - { .fc_id = 305, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC0_L2C_ECC_SERR" }, - { .fc_id = 306, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC1_L2C_ECC_SERR" }, - { .fc_id = 307, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC2_L2C_ECC_SERR" }, - { .fc_id = 308, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC3_L2C_ECC_SERR" }, - { .fc_id = 309, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC4_L2C_ECC_SERR" }, - { .fc_id = 310, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC5_L2C_ECC_SERR" }, - { .fc_id = 311, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC6_L2C_ECC_SERR" }, - { .fc_id = 312, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC7_L2C_ECC_SERR" }, - { .fc_id = 313, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC8_L2C_ECC_SERR" }, - { .fc_id = 314, .cpu_id = 69, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC9_L2C_ECC_SERR" }, - { .fc_id = 315, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC0_VCD_ECC_DERR" }, - { .fc_id = 316, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC1_VCD_ECC_DERR" }, - { .fc_id = 317, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC2_VCD_ECC_DERR" }, - { .fc_id = 318, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC3_VCD_ECC_DERR" }, - { .fc_id = 319, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC4_VCD_ECC_DERR" }, - { .fc_id = 320, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC5_VCD_ECC_DERR" }, - { .fc_id = 321, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC6_VCD_ECC_DERR" }, - { .fc_id = 322, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC7_VCD_ECC_DERR" }, - { .fc_id = 323, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC8_VCD_ECC_DERR" }, - { .fc_id = 324, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC9_VCD_ECC_DERR" }, - { .fc_id = 325, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC0_L2C_ECC_DERR" }, - { .fc_id = 326, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC1_L2C_ECC_DERR" }, - { .fc_id = 327, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC2_L2C_ECC_DERR" }, - { .fc_id = 328, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC3_L2C_ECC_DERR" }, - { .fc_id = 329, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC4_L2C_ECC_DERR" }, - { .fc_id = 330, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC5_L2C_ECC_DERR" }, - { .fc_id = 331, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC6_L2C_ECC_DERR" }, - { .fc_id = 332, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC7_L2C_ECC_DERR" }, - { .fc_id = 333, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC8_L2C_ECC_DERR" }, - { .fc_id = 334, .cpu_id = 70, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC9_L2C_ECC_DERR" }, - { .fc_id = 335, .cpu_id = 71, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 336, .cpu_id = 72, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 337, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF0_ECC_SERR" }, - { .fc_id = 338, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF1_ECC_SERR" }, - { .fc_id = 339, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF2_ECC_SERR" }, - { .fc_id = 340, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF3_ECC_SERR" }, - { .fc_id = 341, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF8_ECC_SERR" }, - { .fc_id = 342, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF9_ECC_SERR" }, - { .fc_id = 343, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF10_ECC_SERR" }, - { .fc_id = 344, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF11_ECC_SERR" }, - { .fc_id = 345, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF7_ECC_SERR" }, - { .fc_id = 346, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF6_ECC_SERR" }, - { .fc_id = 347, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF5_ECC_SERR" }, - { .fc_id = 348, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF4_ECC_SERR" }, - { .fc_id = 349, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF15_ECC_SERR" }, - { .fc_id = 350, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF14_ECC_SERR" }, - { .fc_id = 351, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF13_ECC_SERR" }, - { .fc_id = 352, .cpu_id = 73, .valid = 1, - .msg = 0, .reset = 0, .name = "HIF12_ECC_SERR" }, - { .fc_id = 353, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF0_ECC_DERR" }, - { .fc_id = 354, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF1_ECC_DERR" }, - { .fc_id = 355, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF2_ECC_DERR" }, - { .fc_id = 356, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF3_ECC_DERR" }, - { .fc_id = 357, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF8_ECC_DERR" }, - { .fc_id = 358, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF9_ECC_DERR" }, - { .fc_id = 359, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF10_ECC_DERR" }, - { .fc_id = 360, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF11_ECC_DERR" }, - { .fc_id = 361, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF7_ECC_DERR" }, - { .fc_id = 362, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF6_ECC_DERR" }, - { .fc_id = 363, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF5_ECC_DERR" }, - { .fc_id = 364, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF4_ECC_DERR" }, - { .fc_id = 365, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF15_ECC_DERR" }, - { .fc_id = 366, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF14_ECC_DERR" }, - { .fc_id = 367, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF13_ECC_DERR" }, - { .fc_id = 368, .cpu_id = 74, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF12_ECC_DERR" }, - { .fc_id = 369, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC0_ECC_SERR" }, - { .fc_id = 370, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC1_ECC_SERR" }, - { .fc_id = 371, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC2_ECC_SERR" }, - { .fc_id = 372, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC3_ECC_SERR" }, - { .fc_id = 373, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC4_ECC_SERR" }, - { .fc_id = 374, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC5_ECC_SERR" }, - { .fc_id = 375, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC6_ECC_SERR" }, - { .fc_id = 376, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC7_ECC_SERR" }, - { .fc_id = 377, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC8_ECC_SERR" }, - { .fc_id = 378, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC9_ECC_SERR" }, - { .fc_id = 379, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC10_ECC_SERR" }, - { .fc_id = 380, .cpu_id = 75, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC11_ECC_SERR" }, - { .fc_id = 381, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC0_ECC_DERR" }, - { .fc_id = 382, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC1_ECC_DERR" }, - { .fc_id = 383, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC2_ECC_DERR" }, - { .fc_id = 384, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC3_ECC_DERR" }, - { .fc_id = 385, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC4_ECC_DERR" }, - { .fc_id = 386, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC5_ECC_DERR" }, - { .fc_id = 387, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC6_ECC_DERR" }, - { .fc_id = 388, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC7_ECC_DERR" }, - { .fc_id = 389, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC8_ECC_DERR" }, - { .fc_id = 390, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC9_ECC_DERR" }, - { .fc_id = 391, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC10_ECC_DERR" }, - { .fc_id = 392, .cpu_id = 76, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC11_ECC_DERR" }, - { .fc_id = 393, .cpu_id = 77, .valid = 1, - .msg = 0, .reset = 1, .name = "SM0_ECC_DERR" }, - { .fc_id = 394, .cpu_id = 77, .valid = 1, - .msg = 0, .reset = 1, .name = "SM1_ECC_DERR" }, - { .fc_id = 395, .cpu_id = 77, .valid = 1, - .msg = 0, .reset = 1, .name = "SM2_ECC_DERR" }, - { .fc_id = 396, .cpu_id = 77, .valid = 1, - .msg = 0, .reset = 1, .name = "SM3_ECC_DERR" }, - { .fc_id = 397, .cpu_id = 78, .valid = 1, - .msg = 0, .reset = 0, .name = "SM0_ECC_SERR" }, - { .fc_id = 398, .cpu_id = 78, .valid = 1, - .msg = 0, .reset = 0, .name = "SM1_ECC_SERR" }, - { .fc_id = 399, .cpu_id = 78, .valid = 1, - .msg = 0, .reset = 0, .name = "SM2_ECC_SERR" }, - { .fc_id = 400, .cpu_id = 78, .valid = 1, - .msg = 0, .reset = 0, .name = "SM3_ECC_SERR" }, - { .fc_id = 401, .cpu_id = 79, .valid = 1, - .msg = 0, .reset = 0, .name = "XBAR0_ECC_SERR" }, - { .fc_id = 402, .cpu_id = 79, .valid = 1, - .msg = 0, .reset = 0, .name = "XBAR1_ECC_SERR" }, - { .fc_id = 403, .cpu_id = 79, .valid = 1, - .msg = 0, .reset = 0, .name = "XBAR2_ECC_SERR" }, - { .fc_id = 404, .cpu_id = 79, .valid = 1, - .msg = 0, .reset = 0, .name = "XBAR3_ECC_SERR" }, - { .fc_id = 405, .cpu_id = 80, .valid = 1, - .msg = 0, .reset = 1, .name = "XBAR0_ECC_DERR" }, - { .fc_id = 406, .cpu_id = 80, .valid = 1, - .msg = 0, .reset = 1, .name = "XBAR1_ECC_DERR" }, - { .fc_id = 407, .cpu_id = 80, .valid = 1, - .msg = 0, .reset = 1, .name = "XBAR2_ECC_DERR" }, - { .fc_id = 408, .cpu_id = 80, .valid = 1, - .msg = 0, .reset = 1, .name = "XBAR3_ECC_DERR" }, - { .fc_id = 409, .cpu_id = 81, .valid = 1, - .msg = 0, .reset = 0, .name = "ARC0_ECC_SERR" }, - { .fc_id = 410, .cpu_id = 82, .valid = 1, - .msg = 0, .reset = 1, .name = "ARC0_ECC_DERR" }, - { .fc_id = 411, .cpu_id = 83, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 412, .cpu_id = 84, .valid = 1, - .msg = 0, .reset = 1, .name = "PCIE_ADDR_DEC_ERR" }, - { .fc_id = 413, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC0_AXI_ERR_RSP" }, - { .fc_id = 414, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC1_AXI_ERR_RSP" }, - { .fc_id = 415, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC2_AXI_ERR_RSP" }, - { .fc_id = 416, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC3_AXI_ERR_RSP" }, - { .fc_id = 417, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC4_AXI_ERR_RSP" }, - { .fc_id = 418, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC5_AXI_ERR_RSP" }, - { .fc_id = 419, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC6_AXI_ERR_RSP" }, - { .fc_id = 420, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC7_AXI_ERR_RSP" }, - { .fc_id = 421, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC8_AXI_ERR_RSP" }, - { .fc_id = 422, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC9_AXI_ERR_RSP" }, - { .fc_id = 423, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC10_AXI_ERR_RSP" }, - { .fc_id = 424, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC11_AXI_ERR_RSP" }, - { .fc_id = 425, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC12_AXI_ERR_RSP" }, - { .fc_id = 426, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC13_AXI_ERR_RSP" }, - { .fc_id = 427, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC14_AXI_ERR_RSP" }, - { .fc_id = 428, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC15_AXI_ERR_RSP" }, - { .fc_id = 429, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC16_AXI_ERR_RSP" }, - { .fc_id = 430, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC17_AXI_ERR_RSP" }, - { .fc_id = 431, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC18_AXI_ERR_RSP" }, - { .fc_id = 432, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC19_AXI_ERR_RSP" }, - { .fc_id = 433, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC20_AXI_ERR_RSP" }, - { .fc_id = 434, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC21_AXI_ERR_RSP" }, - { .fc_id = 435, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC22_AXI_ERR_RSP" }, - { .fc_id = 436, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC23_AXI_ERR_RSP" }, - { .fc_id = 437, .cpu_id = 85, .valid = 1, - .msg = 0, .reset = 1, .name = "TPC24_AXI_ERR_RSP" }, - { .fc_id = 438, .cpu_id = 86, .valid = 1, - .msg = 0, .reset = 1, .name = "AXI_ECC" }, - { .fc_id = 439, .cpu_id = 87, .valid = 1, - .msg = 0, .reset = 1, .name = "L2_RAM_ECC" }, - { .fc_id = 440, .cpu_id = 88, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE0_AXI_ERR_RSP" }, - { .fc_id = 441, .cpu_id = 88, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE1_AXI_ERR_RSP" }, - { .fc_id = 442, .cpu_id = 88, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE2_AXI_ERR_RSP" }, - { .fc_id = 443, .cpu_id = 88, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE3_AXI_ERR_RSP" }, - { .fc_id = 444, .cpu_id = 88, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_SBTE4_AXI_ERR_RSP" }, - { .fc_id = 445, .cpu_id = 88, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_CTRL_AXI_ERROR_RESPONSE" }, - { .fc_id = 446, .cpu_id = 88, .valid = 1, - .msg = 0, .reset = 1, .name = "MME0_QMAN_SW_ERROR" }, - { .fc_id = 447, .cpu_id = 89, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE0_AXI_ERR_RSP" }, - { .fc_id = 448, .cpu_id = 89, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE1_AXI_ERR_RSP" }, - { .fc_id = 449, .cpu_id = 89, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE2_AXI_ERR_RSP" }, - { .fc_id = 450, .cpu_id = 89, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE3_AXI_ERR_RSP" }, - { .fc_id = 451, .cpu_id = 89, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_SBTE4_AXI_ERR_RSP" }, - { .fc_id = 452, .cpu_id = 89, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_CTRL_AXI_ERROR_RESPONSE" }, - { .fc_id = 453, .cpu_id = 89, .valid = 1, - .msg = 0, .reset = 1, .name = "MME1_QMAN_SW_ERROR" }, - { .fc_id = 454, .cpu_id = 90, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE0_AXI_ERR_RSP" }, - { .fc_id = 455, .cpu_id = 90, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE1_AXI_ERR_RSP" }, - { .fc_id = 456, .cpu_id = 90, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE2_AXI_ERR_RSP" }, - { .fc_id = 457, .cpu_id = 90, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE3_AXI_ERR_RSP" }, - { .fc_id = 458, .cpu_id = 90, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_SBTE4_AXI_ERR_RSP" }, - { .fc_id = 459, .cpu_id = 90, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_CTRL_AXI_ERROR_RESPONSE" }, - { .fc_id = 460, .cpu_id = 90, .valid = 1, - .msg = 0, .reset = 1, .name = "MME2_QMAN_SW_ERROR" }, - { .fc_id = 461, .cpu_id = 91, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE0_AXI_ERR_RSP" }, - { .fc_id = 462, .cpu_id = 91, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE1_AXI_ERR_RSP" }, - { .fc_id = 463, .cpu_id = 91, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE2_AXI_ERR_RSP" }, - { .fc_id = 464, .cpu_id = 91, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE3_AXI_ERR_RSP" }, - { .fc_id = 465, .cpu_id = 91, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_SBTE4_AXI_ERR_RSP" }, - { .fc_id = 466, .cpu_id = 91, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_CTRL_AXI_ERROR_RESPONSE" }, - { .fc_id = 467, .cpu_id = 91, .valid = 1, - .msg = 0, .reset = 1, .name = "MME3_QMAN_SW_ERROR" }, - { .fc_id = 468, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "PSOC_MME_PLL_LOCK_ERR" }, - { .fc_id = 469, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "PSOC_CPU_PLL_LOCK_ERR" }, - { .fc_id = 470, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE3_TPC_PLL_LOCK_ERR" }, - { .fc_id = 471, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE3_NIC_PLL_LOCK_ERR" }, - { .fc_id = 472, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE3_XBAR_MMU_PLL_LOCK_ERR" }, - { .fc_id = 473, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE3_XBAR_DMA_PLL_LOCK_ERR" }, - { .fc_id = 474, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE3_XBAR_IF_PLL_LOCK_ERR" }, - { .fc_id = 475, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE3_XBAR_BANK_PLL_LOCK_ERR" }, - { .fc_id = 476, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_XBAR_MMU_PLL_LOCK_ERR" }, - { .fc_id = 477, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_XBAR_DMA_PLL_LOCK_ERR" }, - { .fc_id = 478, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_XBAR_IF_PLL_LOCK_ERR" }, - { .fc_id = 479, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_XBAR_MESH_PLL_LOCK_ERR" }, - { .fc_id = 480, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_TPC_PLL_LOCK_ERR" }, - { .fc_id = 481, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_NIC_PLL_LOCK_ERR" }, - { .fc_id = 482, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "PMMU_MME_PLL_LOCK_ERR" }, - { .fc_id = 483, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE0_TPC_PLL_LOCK_ERR" }, - { .fc_id = 484, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE0_PCI_PLL_LOCK_ERR" }, - { .fc_id = 485, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE0_XBAR_MMU_PLL_LOCK_ERR" }, - { .fc_id = 486, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE0_XBAR_DMA_PLL_LOCK_ERR" }, - { .fc_id = 487, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE0_XBAR_IF_PLL_LOCK_ERR" }, - { .fc_id = 488, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE0_XBAR_MESH_PLL_LOCK_ERR" }, - { .fc_id = 489, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE2_XBAR_MMU_PLL_LOCK_ERR" }, - { .fc_id = 490, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE2_XBAR_DMA_PLL_LOCK_ERR" }, - { .fc_id = 491, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE2_XBAR_IF_PLL_LOCK_ERR" }, - { .fc_id = 492, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE2_XBAR_BANK_PLL_LOCK_ERR" }, - { .fc_id = 493, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE2_TPC_PLL_LOCK_ERR" }, - { .fc_id = 494, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "PSOC_VID_PLL_LOCK_ERR" }, - { .fc_id = 495, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "PMMU_VID_PLL_LOCK_ERR" }, - { .fc_id = 496, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE3_HBM_PLL_LOCK_ERR" }, - { .fc_id = 497, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_XBAR_HBM_PLL_LOCK_ERR" }, - { .fc_id = 498, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE1_HBM_PLL_LOCK_ERR" }, - { .fc_id = 499, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE0_HBM_PLL_LOCK_ERR" }, - { .fc_id = 500, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE2_XBAR_HBM_PLL_LOCK_ERR" }, - { .fc_id = 501, .cpu_id = 92, .valid = 1, - .msg = 0, .reset = 1, .name = "DCORE2_HBM_PLL_LOCK_ERR" }, - { .fc_id = 502, .cpu_id = 93, .valid = 1, - .msg = 0, .reset = 1, .name = "CPU_AXI_ERR_RSP" }, - { .fc_id = 503, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_0_AXI_ERR_RSP" }, - { .fc_id = 504, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_1_AXI_ERR_RSP" }, - { .fc_id = 505, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_2_AXI_ERR_RSP" }, - { .fc_id = 506, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_3_AXI_ERR_RSP" }, - { .fc_id = 507, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_8_AXI_ERR_RSP" }, - { .fc_id = 508, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_9_AXI_ERR_RSP" }, - { .fc_id = 509, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_10_AXI_ERR_RSP" }, - { .fc_id = 510, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_11_AXI_ERR_RSP" }, - { .fc_id = 511, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_7_AXI_ERR_RSP" }, - { .fc_id = 512, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_6_AXI_ERR_RSP" }, - { .fc_id = 513, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_5_AXI_ERR_RSP" }, - { .fc_id = 514, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_4_AXI_ERR_RSP" }, - { .fc_id = 515, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_15_AXI_ERR_RSP" }, - { .fc_id = 516, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_14_AXI_ERR_RSP" }, - { .fc_id = 517, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_13_AXI_ERR_RSP" }, - { .fc_id = 518, .cpu_id = 94, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU_12_AXI_ERR_RSP" }, - { .fc_id = 519, .cpu_id = 95, .valid = 1, - .msg = 0, .reset = 1, .name = "PMMU_FATAL" }, - { .fc_id = 520, .cpu_id = 96, .valid = 1, - .msg = 0, .reset = 1, .name = "PMMU_AXI_ERR_RSP" }, - { .fc_id = 521, .cpu_id = 97, .valid = 1, - .msg = 0, .reset = 0, .name = "VM0_ALARM_A" }, - { .fc_id = 522, .cpu_id = 98, .valid = 1, - .msg = 0, .reset = 0, .name = "VM0_ALARM_B" }, - { .fc_id = 523, .cpu_id = 99, .valid = 1, - .msg = 0, .reset = 0, .name = "VM1_ALARM_A" }, - { .fc_id = 524, .cpu_id = 100, .valid = 1, - .msg = 0, .reset = 0, .name = "VM1_ALARM_B" }, - { .fc_id = 525, .cpu_id = 101, .valid = 1, - .msg = 0, .reset = 0, .name = "VM2_ALARM_A" }, - { .fc_id = 526, .cpu_id = 102, .valid = 1, - .msg = 0, .reset = 0, .name = "VM2_ALARM_B" }, - { .fc_id = 527, .cpu_id = 103, .valid = 1, - .msg = 0, .reset = 0, .name = "VM3_ALARM_A" }, - { .fc_id = 528, .cpu_id = 104, .valid = 1, - .msg = 0, .reset = 0, .name = "VM3_ALARM_B" }, - { .fc_id = 529, .cpu_id = 105, .valid = 1, - .msg = 0, .reset = 1, .name = "PSOC_AXI_ERR_RSP" }, - { .fc_id = 530, .cpu_id = 106, .valid = 1, - .msg = 0, .reset = 0, .name = "PSOC_PRSTN_FALL" }, - { .fc_id = 531, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 532, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 533, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 534, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 535, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 536, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 537, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 538, .cpu_id = 107, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 539, .cpu_id = 108, .valid = 1, - .msg = 0, .reset = 1, .name = "KDMA_CH0_AXI_ERR_RSP" }, - { .fc_id = 540, .cpu_id = 109, .valid = 1, - .msg = 0, .reset = 1, .name = "PDMA_CH0_AXI_ERR_RSP" }, - { .fc_id = 541, .cpu_id = 109, .valid = 1, - .msg = 0, .reset = 1, .name = "PDMA_CH1_AXI_ERR_RSP" }, - { .fc_id = 542, .cpu_id = 110, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_CATTRIP_0" }, - { .fc_id = 543, .cpu_id = 111, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_CATTRIP_1" }, - { .fc_id = 544, .cpu_id = 112, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_CATTRIP_2" }, - { .fc_id = 545, .cpu_id = 113, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_CATTRIP_3" }, - { .fc_id = 546, .cpu_id = 114, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_CATTRIP_4" }, - { .fc_id = 547, .cpu_id = 115, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM_CATTRIP_5" }, - { .fc_id = 548, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM0_MC0_SEI_SEVERE" }, - { .fc_id = 549, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM0_MC0_SEI_NON_SEVERE" }, - { .fc_id = 550, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM0_MC1_SEI_SEVERE" }, - { .fc_id = 551, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM0_MC1_SEI_NON_SEVERE" }, - { .fc_id = 552, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM1_MC0_SEI_SEVERE" }, - { .fc_id = 553, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM1_MC0_SEI_NON_SEVERE" }, - { .fc_id = 554, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM1_MC1_SEI_SEVERE" }, - { .fc_id = 555, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM1_MC1_SEI_NON_SEVERE" }, - { .fc_id = 556, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM2_MC0_SEI_SEVERE" }, - { .fc_id = 557, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM2_MC0_SEI_NON_SEVERE" }, - { .fc_id = 558, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM2_MC1_SEI_SEVERE" }, - { .fc_id = 559, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM2_MC1_SEI_NON_SEVERE" }, - { .fc_id = 560, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM3_MC0_SEI_SEVERE" }, - { .fc_id = 561, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM3_MC0_SEI_NON_SEVERE" }, - { .fc_id = 562, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM3_MC1_SEI_SEVERE" }, - { .fc_id = 563, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM3_MC1_SEI_NON_SEVERE" }, - { .fc_id = 564, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM4_MC0_SEI_SEVERE" }, - { .fc_id = 565, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM4_MC0_SEI_NON_SEVERE" }, - { .fc_id = 566, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM4_MC1_SEI_SEVERE" }, - { .fc_id = 567, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM4_MC1_SEI_NON_SEVERE" }, - { .fc_id = 568, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM5_MC0_SEI_SEVERE" }, - { .fc_id = 569, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM5_MC0_SEI_NON_SEVERE" }, - { .fc_id = 570, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 1, .name = "HBM5_MC1_SEI_SEVERE" }, - { .fc_id = 571, .cpu_id = 116, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM5_MC1_SEI_NON_SEVERE" }, - { .fc_id = 572, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC0_AXI_ERR_RSPONSE" }, - { .fc_id = 573, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC1_AXI_ERR_RSPONSE" }, - { .fc_id = 574, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC2_AXI_ERR_RSPONSE" }, - { .fc_id = 575, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC3_AXI_ERR_RSPONSE" }, - { .fc_id = 576, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC4_AXI_ERR_RSPONSE" }, - { .fc_id = 577, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC5_AXI_ERR_RSPONSE" }, - { .fc_id = 578, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC6_AXI_ERR_RSPONSE" }, - { .fc_id = 579, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC7_AXI_ERR_RSPONSE" }, - { .fc_id = 580, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC8_AXI_ERR_RSPONSE" }, - { .fc_id = 581, .cpu_id = 117, .valid = 1, - .msg = 0, .reset = 1, .name = "DEC9_AXI_ERR_RSPONSE" }, - { .fc_id = 582, .cpu_id = 118, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 583, .cpu_id = 119, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 584, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF0_FATAL" }, - { .fc_id = 585, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF1_FATAL" }, - { .fc_id = 586, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF2_FATAL" }, - { .fc_id = 587, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF3_FATAL" }, - { .fc_id = 588, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF8_FATAL" }, - { .fc_id = 589, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF9_FATAL" }, - { .fc_id = 590, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF10_FATAL" }, - { .fc_id = 591, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF11_FATAL" }, - { .fc_id = 592, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF7_FATAL" }, - { .fc_id = 593, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF6_FATAL" }, - { .fc_id = 594, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF5_FATAL" }, - { .fc_id = 595, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF4_FATAL" }, - { .fc_id = 596, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF15_FATAL" }, - { .fc_id = 597, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF14_FATAL" }, - { .fc_id = 598, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF13_FATAL" }, - { .fc_id = 599, .cpu_id = 120, .valid = 1, - .msg = 0, .reset = 1, .name = "HIF12_FATAL" }, - { .fc_id = 600, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC0_AXI_ERROR_RESPONSE" }, - { .fc_id = 601, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC1_AXI_ERROR_RESPONSE" }, - { .fc_id = 602, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC2_AXI_ERROR_RESPONSE" }, - { .fc_id = 603, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC3_AXI_ERROR_RESPONSE" }, - { .fc_id = 604, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC4_AXI_ERROR_RESPONSE" }, - { .fc_id = 605, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC5_AXI_ERROR_RESPONSE" }, - { .fc_id = 606, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC6_AXI_ERROR_RESPONSE" }, - { .fc_id = 607, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC7_AXI_ERROR_RESPONSE" }, - { .fc_id = 608, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC8_AXI_ERROR_RESPONSE" }, - { .fc_id = 609, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC9_AXI_ERROR_RESPONSE" }, - { .fc_id = 610, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC10_AXI_ERROR_RESPONSE" }, - { .fc_id = 611, .cpu_id = 121, .valid = 1, - .msg = 0, .reset = 1, .name = "NIC11_AXI_ERROR_RESPONSE" }, - { .fc_id = 612, .cpu_id = 122, .valid = 1, - .msg = 0, .reset = 1, .name = "SM0_AXI_ERROR_RESPONSE" }, - { .fc_id = 613, .cpu_id = 122, .valid = 1, - .msg = 0, .reset = 1, .name = "SM1_AXI_ERROR_RESPONSE" }, - { .fc_id = 614, .cpu_id = 122, .valid = 1, - .msg = 0, .reset = 1, .name = "SM2_AXI_ERROR_RESPONSE" }, - { .fc_id = 615, .cpu_id = 122, .valid = 1, - .msg = 0, .reset = 1, .name = "SM3_AXI_ERROR_RESPONSE" }, - { .fc_id = 616, .cpu_id = 123, .valid = 1, - .msg = 0, .reset = 1, .name = "ARC_AXI_ERROR_RESPONSE" }, - { .fc_id = 617, .cpu_id = 124, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 618, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 619, .cpu_id = 125, .valid = 1, - .msg = 0, .reset = 0, .name = "PCIE_FLR_REQUESTED" }, - { .fc_id = 620, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 621, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 622, .cpu_id = 125, .valid = 1, - .msg = 0, .reset = 1, .name = "PCIE_APB_TIMEOUT" }, - { .fc_id = 623, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 624, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 625, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 626, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 627, .cpu_id = 125, .valid = 1, - .msg = 0, .reset = 0, .name = "PCIE_FATAL_ERR" }, - { .fc_id = 628, .cpu_id = 125, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 629, .cpu_id = 126, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 630, .cpu_id = 127, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 631, .cpu_id = 128, .valid = 1, - .msg = 0, .reset = 0, .name = "PCIE_P2P_MSIX" }, - { .fc_id = 632, .cpu_id = 129, .valid = 1, - .msg = 0, .reset = 0, .name = "PCIE_DRAIN_COMPLETE" }, - { .fc_id = 633, .cpu_id = 130, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC0_BMON_SPMU" }, - { .fc_id = 634, .cpu_id = 131, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC0_KERNEL_ERR" }, - { .fc_id = 635, .cpu_id = 132, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC1_BMON_SPMU" }, - { .fc_id = 636, .cpu_id = 133, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC1_KERNEL_ERR" }, - { .fc_id = 637, .cpu_id = 134, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC2_BMON_SPMU" }, - { .fc_id = 638, .cpu_id = 135, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC2_KERNEL_ERR" }, - { .fc_id = 639, .cpu_id = 136, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC3_BMON_SPMU" }, - { .fc_id = 640, .cpu_id = 137, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC3_KERNEL_ERR" }, - { .fc_id = 641, .cpu_id = 138, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC4_BMON_SPMU" }, - { .fc_id = 642, .cpu_id = 139, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC4_KERNEL_ERR" }, - { .fc_id = 643, .cpu_id = 140, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC5_BMON_SPMU" }, - { .fc_id = 644, .cpu_id = 141, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC5_KERNEL_ERR" }, - { .fc_id = 645, .cpu_id = 150, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC6_BMON_SPMU" }, - { .fc_id = 646, .cpu_id = 151, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC6_KERNEL_ERR" }, - { .fc_id = 647, .cpu_id = 152, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC7_BMON_SPMU" }, - { .fc_id = 648, .cpu_id = 153, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC7_KERNEL_ERR" }, - { .fc_id = 649, .cpu_id = 146, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC8_BMON_SPMU" }, - { .fc_id = 650, .cpu_id = 147, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC8_KERNEL_ERR" }, - { .fc_id = 651, .cpu_id = 148, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC9_BMON_SPMU" }, - { .fc_id = 652, .cpu_id = 149, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC9_KERNEL_ERR" }, - { .fc_id = 653, .cpu_id = 142, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC10_BMON_SPMU" }, - { .fc_id = 654, .cpu_id = 143, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC10_KERNEL_ERR" }, - { .fc_id = 655, .cpu_id = 144, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC11_BMON_SPMU" }, - { .fc_id = 656, .cpu_id = 145, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC11_KERNEL_ERR" }, - { .fc_id = 657, .cpu_id = 162, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC12_BMON_SPMU" }, - { .fc_id = 658, .cpu_id = 163, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC12_KERNEL_ERR" }, - { .fc_id = 659, .cpu_id = 164, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC13_BMON_SPMU" }, - { .fc_id = 660, .cpu_id = 165, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC13_KERNEL_ERR" }, - { .fc_id = 661, .cpu_id = 158, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC14_BMON_SPMU" }, - { .fc_id = 662, .cpu_id = 159, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC14_KERNEL_ERR" }, - { .fc_id = 663, .cpu_id = 160, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC15_BMON_SPMU" }, - { .fc_id = 664, .cpu_id = 161, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC15_KERNEL_ERR" }, - { .fc_id = 665, .cpu_id = 154, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC16_BMON_SPMU" }, - { .fc_id = 666, .cpu_id = 155, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC16_KERNEL_ERR" }, - { .fc_id = 667, .cpu_id = 156, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC17_BMON_SPMU" }, - { .fc_id = 668, .cpu_id = 157, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC17_KERNEL_ERR" }, - { .fc_id = 669, .cpu_id = 166, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC18_BMON_SPMU" }, - { .fc_id = 670, .cpu_id = 167, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC18_KERNEL_ERR" }, - { .fc_id = 671, .cpu_id = 168, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC19_BMON_SPMU" }, - { .fc_id = 672, .cpu_id = 169, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC19_KERNEL_ERR" }, - { .fc_id = 673, .cpu_id = 170, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC20_BMON_SPMU" }, - { .fc_id = 674, .cpu_id = 171, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC20_KERNEL_ERR" }, - { .fc_id = 675, .cpu_id = 172, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC21_BMON_SPMU" }, - { .fc_id = 676, .cpu_id = 173, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC21_KERNEL_ERR" }, - { .fc_id = 677, .cpu_id = 174, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC22_BMON_SPMU" }, - { .fc_id = 678, .cpu_id = 175, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC22_KERNEL_ERR" }, - { .fc_id = 679, .cpu_id = 176, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC23_BMON_SPMU" }, - { .fc_id = 680, .cpu_id = 177, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC23_KERNEL_ERR" }, - { .fc_id = 681, .cpu_id = 178, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC24_BMON_SPMU" }, - { .fc_id = 682, .cpu_id = 179, .valid = 1, - .msg = 0, .reset = 0, .name = "TPC24_KERNEL_ERR" }, - { .fc_id = 683, .cpu_id = 180, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 684, .cpu_id = 180, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 685, .cpu_id = 180, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 686, .cpu_id = 180, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 687, .cpu_id = 180, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 688, .cpu_id = 180, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_CTRL_BMON_SPMU" }, - { .fc_id = 689, .cpu_id = 180, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_SBTE_BMON_SPMU" }, - { .fc_id = 690, .cpu_id = 180, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_WAP_BMON_SPMU" }, - { .fc_id = 691, .cpu_id = 180, .valid = 1, - .msg = 0, .reset = 0, .name = "MME0_WAP_SOURCE_RESULT_INVALID" }, - { .fc_id = 692, .cpu_id = 181, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 693, .cpu_id = 181, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 694, .cpu_id = 181, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 695, .cpu_id = 181, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 696, .cpu_id = 181, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 697, .cpu_id = 181, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_CTRL_BMON_SPMU" }, - { .fc_id = 698, .cpu_id = 181, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_SBTE_BMON_SPMU" }, - { .fc_id = 699, .cpu_id = 181, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_WAP_BMON_SPMU" }, - { .fc_id = 700, .cpu_id = 181, .valid = 1, - .msg = 0, .reset = 0, .name = "MME1_WAP_SOURCE_RESULT_INVALID" }, - { .fc_id = 701, .cpu_id = 182, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 702, .cpu_id = 182, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 703, .cpu_id = 182, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 704, .cpu_id = 182, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 705, .cpu_id = 182, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 706, .cpu_id = 182, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_CTRL_BMON_SPMU" }, - { .fc_id = 707, .cpu_id = 182, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_SBTE_BMON_SPMU" }, - { .fc_id = 708, .cpu_id = 182, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_WAP_BMON_SPMU" }, - { .fc_id = 709, .cpu_id = 182, .valid = 1, - .msg = 0, .reset = 0, .name = "MME2_WAP_SOURCE_RESULT_INVALID" }, - { .fc_id = 710, .cpu_id = 183, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 711, .cpu_id = 183, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 712, .cpu_id = 183, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 713, .cpu_id = 183, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 714, .cpu_id = 183, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 715, .cpu_id = 183, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_CTRL_BMON_SPMU" }, - { .fc_id = 716, .cpu_id = 183, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_SBTE_BMON_SPMU" }, - { .fc_id = 717, .cpu_id = 183, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_WAP_BMON_SPMU" }, - { .fc_id = 718, .cpu_id = 183, .valid = 1, - .msg = 0, .reset = 0, .name = "MME3_WAP_SOURCE_RESULT_INVALID" }, - { .fc_id = 719, .cpu_id = 184, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 720, .cpu_id = 184, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU0_PAGE_FAULT_OR_WR_PERM" }, - { .fc_id = 721, .cpu_id = 184, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU0_SECURITY_ERROR" }, - { .fc_id = 722, .cpu_id = 185, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 723, .cpu_id = 185, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU1_PAGE_FAULT_WR_PERM" }, - { .fc_id = 724, .cpu_id = 185, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU1_SECURITY_ERROR" }, - { .fc_id = 725, .cpu_id = 186, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 726, .cpu_id = 186, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU2_PAGE_FAULT_WR_PERM" }, - { .fc_id = 727, .cpu_id = 186, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU2_SECURITY_ERROR" }, - { .fc_id = 728, .cpu_id = 187, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 729, .cpu_id = 187, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU3_PAGE_FAULT_WR_PERM" }, - { .fc_id = 730, .cpu_id = 187, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU3_SECURITY_ERROR" }, - { .fc_id = 731, .cpu_id = 188, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 732, .cpu_id = 188, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU8_PAGE_FAULT_WR_PERM" }, - { .fc_id = 733, .cpu_id = 188, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU8_SECURITY_ERROR" }, - { .fc_id = 734, .cpu_id = 189, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 735, .cpu_id = 189, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU9_PAGE_FAULT_WR_PERM" }, - { .fc_id = 736, .cpu_id = 189, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU9_SECURITY_ERROR" }, - { .fc_id = 737, .cpu_id = 190, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 738, .cpu_id = 190, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU10_PAGE_FAULT_WR_PERM" }, - { .fc_id = 739, .cpu_id = 190, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU10_SECURITY_ERROR" }, - { .fc_id = 740, .cpu_id = 191, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 741, .cpu_id = 191, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU11_PAGE_FAULT_WR_PERM" }, - { .fc_id = 742, .cpu_id = 191, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU11_SECURITY_ERROR" }, - { .fc_id = 743, .cpu_id = 192, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 744, .cpu_id = 192, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU7_PAGE_FAULT_WR_PERM" }, - { .fc_id = 745, .cpu_id = 192, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU7_SECURITY_ERROR" }, - { .fc_id = 746, .cpu_id = 193, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 747, .cpu_id = 193, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU6_PAGE_FAULT_WR_PERM" }, - { .fc_id = 748, .cpu_id = 193, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU6_SECURITY_ERROR" }, - { .fc_id = 749, .cpu_id = 194, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 750, .cpu_id = 194, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU5_PAGE_FAULT_WR_PERM" }, - { .fc_id = 751, .cpu_id = 194, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU5_SECURITY_ERROR" }, - { .fc_id = 752, .cpu_id = 195, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 753, .cpu_id = 195, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU4_PAGE_FAULT_WR_PERM" }, - { .fc_id = 754, .cpu_id = 195, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU4_SECURITY_ERROR" }, - { .fc_id = 755, .cpu_id = 196, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 756, .cpu_id = 196, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU15_PAGE_FAULT_WR_PERM" }, - { .fc_id = 757, .cpu_id = 196, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU15_SECURITY_ERROR" }, - { .fc_id = 758, .cpu_id = 197, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 759, .cpu_id = 197, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU14_PAGE_FAULT_WR_PERM" }, - { .fc_id = 760, .cpu_id = 197, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU14_SECURITY_ERROR" }, - { .fc_id = 761, .cpu_id = 198, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 762, .cpu_id = 198, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU13_PAGE_FAULT_WR_PERM" }, - { .fc_id = 763, .cpu_id = 198, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU13_SECURITY_ERROR" }, - { .fc_id = 764, .cpu_id = 199, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 765, .cpu_id = 199, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU12_PAGE_FAULT_WR_PERM" }, - { .fc_id = 766, .cpu_id = 199, .valid = 1, - .msg = 0, .reset = 1, .name = "HMMU12_SECURITY_ERROR" }, - { .fc_id = 767, .cpu_id = 200, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 768, .cpu_id = 201, .valid = 1, - .msg = 0, .reset = 1, .name = "PMMU0_PAGE_FAULT_WR_PERM" }, - { .fc_id = 769, .cpu_id = 202, .valid = 1, - .msg = 0, .reset = 1, .name = "PMMU0_SECURITY_ERROR" }, - { .fc_id = 770, .cpu_id = 203, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA2_BM_SPMU" }, - { .fc_id = 771, .cpu_id = 204, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 772, .cpu_id = 205, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA3_BM_SPMU" }, - { .fc_id = 773, .cpu_id = 206, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 774, .cpu_id = 207, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA0_BM_SPMU" }, - { .fc_id = 775, .cpu_id = 208, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 776, .cpu_id = 209, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA1_BM_SPMU" }, - { .fc_id = 777, .cpu_id = 210, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 778, .cpu_id = 211, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA6_BM_SPMU" }, - { .fc_id = 779, .cpu_id = 212, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 780, .cpu_id = 213, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA7_BM_SPMU" }, - { .fc_id = 781, .cpu_id = 214, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 782, .cpu_id = 215, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA4_BM_SPMU" }, - { .fc_id = 783, .cpu_id = 216, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 784, .cpu_id = 217, .valid = 1, - .msg = 0, .reset = 0, .name = "HDMA5_BM_SPMU" }, - { .fc_id = 785, .cpu_id = 218, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 786, .cpu_id = 219, .valid = 1, - .msg = 0, .reset = 0, .name = "KDMA_BM_SPMU" }, - { .fc_id = 787, .cpu_id = 220, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 788, .cpu_id = 221, .valid = 1, - .msg = 0, .reset = 0, .name = "PDMA0_BM_SPMU" }, - { .fc_id = 789, .cpu_id = 222, .valid = 1, - .msg = 0, .reset = 0, .name = "PDMA1_BM_SPMU" }, - { .fc_id = 790, .cpu_id = 223, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM0_MC0_SPI" }, - { .fc_id = 791, .cpu_id = 224, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM0_MC1_SPI" }, - { .fc_id = 792, .cpu_id = 225, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM1_MC0_SPI" }, - { .fc_id = 793, .cpu_id = 226, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM1_MC1_SPI" }, - { .fc_id = 794, .cpu_id = 227, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM2_MC0_SPI" }, - { .fc_id = 795, .cpu_id = 228, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM2_MC1_SPI" }, - { .fc_id = 796, .cpu_id = 229, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM3_MC0_SPI" }, - { .fc_id = 797, .cpu_id = 230, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM3_MC1_SPI" }, - { .fc_id = 798, .cpu_id = 231, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM4_MC0_SPI" }, - { .fc_id = 799, .cpu_id = 232, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM4_MC1_SPI" }, - { .fc_id = 800, .cpu_id = 233, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM5_MC0_SPI" }, - { .fc_id = 801, .cpu_id = 234, .valid = 1, - .msg = 0, .reset = 0, .name = "HBM5_MC1_SPI" }, - { .fc_id = 802, .cpu_id = 235, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 803, .cpu_id = 236, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 804, .cpu_id = 237, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 805, .cpu_id = 238, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 806, .cpu_id = 239, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 807, .cpu_id = 240, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 808, .cpu_id = 241, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 809, .cpu_id = 242, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 810, .cpu_id = 243, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 811, .cpu_id = 244, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 812, .cpu_id = 245, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 813, .cpu_id = 246, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 814, .cpu_id = 247, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 815, .cpu_id = 248, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 816, .cpu_id = 249, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 817, .cpu_id = 250, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 818, .cpu_id = 251, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 819, .cpu_id = 252, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 820, .cpu_id = 253, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 821, .cpu_id = 254, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 822, .cpu_id = 255, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 823, .cpu_id = 256, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 824, .cpu_id = 257, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 825, .cpu_id = 258, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 826, .cpu_id = 259, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 827, .cpu_id = 260, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 828, .cpu_id = 261, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 829, .cpu_id = 262, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 830, .cpu_id = 263, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 831, .cpu_id = 264, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 832, .cpu_id = 265, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 833, .cpu_id = 266, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 834, .cpu_id = 267, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 835, .cpu_id = 268, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 836, .cpu_id = 269, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 837, .cpu_id = 270, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 838, .cpu_id = 271, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 839, .cpu_id = 272, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 840, .cpu_id = 273, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 841, .cpu_id = 274, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 842, .cpu_id = 275, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 843, .cpu_id = 276, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 844, .cpu_id = 277, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 845, .cpu_id = 278, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 846, .cpu_id = 279, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 847, .cpu_id = 280, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 848, .cpu_id = 281, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 849, .cpu_id = 282, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 850, .cpu_id = 283, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 851, .cpu_id = 284, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 852, .cpu_id = 285, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 853, .cpu_id = 286, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 854, .cpu_id = 287, .valid = 0, - .msg = 0, .reset = 1, .name = "" }, - { .fc_id = 855, .cpu_id = 288, .valid = 0, - .msg = 0, .reset = 1, .name = "" }, - { .fc_id = 856, .cpu_id = 289, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 857, .cpu_id = 290, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 858, .cpu_id = 291, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 859, .cpu_id = 292, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 860, .cpu_id = 293, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 861, .cpu_id = 294, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 862, .cpu_id = 295, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 863, .cpu_id = 296, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 864, .cpu_id = 297, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 865, .cpu_id = 298, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 866, .cpu_id = 299, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 867, .cpu_id = 300, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 868, .cpu_id = 301, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 869, .cpu_id = 302, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 870, .cpu_id = 303, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 871, .cpu_id = 304, .valid = 1, - .msg = 0, .reset = 1, .name = "RPM_ERROR_OR_DRAIN" }, - { .fc_id = 872, .cpu_id = 305, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 873, .cpu_id = 306, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 874, .cpu_id = 307, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 875, .cpu_id = 308, .valid = 1, - .msg = 0, .reset = 0, .name = "RAZWI_OR_PID_MIN_MAX_INTERRUPT" }, - { .fc_id = 876, .cpu_id = 309, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 877, .cpu_id = 310, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 878, .cpu_id = 311, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 879, .cpu_id = 312, .valid = 0, - .msg = 0, .reset = 1, .name = "" }, - { .fc_id = 880, .cpu_id = 313, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 881, .cpu_id = 314, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 882, .cpu_id = 315, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 883, .cpu_id = 316, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 884, .cpu_id = 317, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 885, .cpu_id = 318, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 886, .cpu_id = 319, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 887, .cpu_id = 320, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 888, .cpu_id = 321, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 889, .cpu_id = 322, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 890, .cpu_id = 323, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 891, .cpu_id = 324, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 892, .cpu_id = 325, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 893, .cpu_id = 326, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 894, .cpu_id = 327, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 895, .cpu_id = 328, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 896, .cpu_id = 329, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC0_SPI" }, - { .fc_id = 897, .cpu_id = 329, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC0_BMON_SPMU" }, - { .fc_id = 898, .cpu_id = 330, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC1_SPI" }, - { .fc_id = 899, .cpu_id = 330, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC1_BMON_SPMU" }, - { .fc_id = 900, .cpu_id = 331, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC2_SPI" }, - { .fc_id = 901, .cpu_id = 331, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC2_BMON_SPMU" }, - { .fc_id = 902, .cpu_id = 332, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC3_SPI" }, - { .fc_id = 903, .cpu_id = 332, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC3_BMON_SPMU" }, - { .fc_id = 904, .cpu_id = 333, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC4_SPI" }, - { .fc_id = 905, .cpu_id = 333, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC4_BMON_SPMU" }, - { .fc_id = 906, .cpu_id = 334, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC5_SPI" }, - { .fc_id = 907, .cpu_id = 334, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC5_BMON_SPMU" }, - { .fc_id = 908, .cpu_id = 335, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC6_SPI" }, - { .fc_id = 909, .cpu_id = 335, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC6_BMON_SPMU" }, - { .fc_id = 910, .cpu_id = 336, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC7_SPI" }, - { .fc_id = 911, .cpu_id = 336, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC7_BMON_SPMU" }, - { .fc_id = 912, .cpu_id = 337, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC8_SPI" }, - { .fc_id = 913, .cpu_id = 337, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC8_BMON_SPMU" }, - { .fc_id = 914, .cpu_id = 338, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC9_SPI" }, - { .fc_id = 915, .cpu_id = 338, .valid = 1, - .msg = 0, .reset = 0, .name = "DEC9_BMON_SPMU" }, - { .fc_id = 916, .cpu_id = 339, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 917, .cpu_id = 340, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 918, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 919, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 920, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 921, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 922, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 923, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 924, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 925, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 926, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 927, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 928, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 929, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 930, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 931, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 932, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 933, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 934, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 935, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 936, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 937, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 938, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 939, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 940, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 941, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 942, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 943, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 944, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 945, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 946, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 947, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 948, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 949, .cpu_id = 341, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 950, .cpu_id = 342, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 951, .cpu_id = 343, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC0_BMON_SPMU" }, - { .fc_id = 952, .cpu_id = 343, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC0_SW_ERROR" }, - { .fc_id = 953, .cpu_id = 343, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 954, .cpu_id = 343, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 955, .cpu_id = 344, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC1_BMON_SPMU" }, - { .fc_id = 956, .cpu_id = 344, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC1_SW_ERROR" }, - { .fc_id = 957, .cpu_id = 344, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 958, .cpu_id = 344, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 959, .cpu_id = 345, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC2_BMON_SPMU" }, - { .fc_id = 960, .cpu_id = 345, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC2_SW_ERROR" }, - { .fc_id = 961, .cpu_id = 345, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 962, .cpu_id = 345, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 963, .cpu_id = 346, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC3_BMON_SPMU" }, - { .fc_id = 964, .cpu_id = 346, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC3_SW_ERROR" }, - { .fc_id = 965, .cpu_id = 346, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 966, .cpu_id = 346, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 967, .cpu_id = 347, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC4_BMON_SPMU" }, - { .fc_id = 968, .cpu_id = 347, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC4_SW_ERROR" }, - { .fc_id = 969, .cpu_id = 347, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 970, .cpu_id = 347, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 971, .cpu_id = 348, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC5_BMON_SPMU" }, - { .fc_id = 972, .cpu_id = 348, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC5_SW_ERROR" }, - { .fc_id = 973, .cpu_id = 348, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 974, .cpu_id = 348, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 975, .cpu_id = 349, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC6_BMON_SPMU" }, - { .fc_id = 976, .cpu_id = 349, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC6_SW_ERROR" }, - { .fc_id = 977, .cpu_id = 349, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 978, .cpu_id = 349, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 979, .cpu_id = 350, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC7_BMON_SPMU" }, - { .fc_id = 980, .cpu_id = 350, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC7_SW_ERROR" }, - { .fc_id = 981, .cpu_id = 350, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 982, .cpu_id = 350, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 983, .cpu_id = 351, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC8_BMON_SPMU" }, - { .fc_id = 984, .cpu_id = 351, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC8_SW_ERROR" }, - { .fc_id = 985, .cpu_id = 351, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 986, .cpu_id = 351, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 987, .cpu_id = 352, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC9_BMON_SPMU" }, - { .fc_id = 988, .cpu_id = 352, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC9_SW_ERROR" }, - { .fc_id = 989, .cpu_id = 352, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 990, .cpu_id = 352, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 991, .cpu_id = 353, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC10_BMON_SPMU" }, - { .fc_id = 992, .cpu_id = 353, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC10_SW_ERROR" }, - { .fc_id = 993, .cpu_id = 353, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 994, .cpu_id = 353, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 995, .cpu_id = 354, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC11_BMON_SPMU" }, - { .fc_id = 996, .cpu_id = 354, .valid = 1, - .msg = 0, .reset = 0, .name = "NIC11_SW_ERROR" }, - { .fc_id = 997, .cpu_id = 354, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 998, .cpu_id = 354, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 999, .cpu_id = 355, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1000, .cpu_id = 356, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1001, .cpu_id = 357, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1002, .cpu_id = 358, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1003, .cpu_id = 359, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1004, .cpu_id = 360, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1005, .cpu_id = 361, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1006, .cpu_id = 362, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1007, .cpu_id = 363, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1008, .cpu_id = 368, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1009, .cpu_id = 369, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1010, .cpu_id = 366, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1011, .cpu_id = 367, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1012, .cpu_id = 364, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1013, .cpu_id = 365, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1014, .cpu_id = 374, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1015, .cpu_id = 375, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1016, .cpu_id = 372, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1017, .cpu_id = 373, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1018, .cpu_id = 370, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1019, .cpu_id = 371, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1020, .cpu_id = 376, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1021, .cpu_id = 377, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1022, .cpu_id = 378, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1023, .cpu_id = 379, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1024, .cpu_id = 380, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1025, .cpu_id = 381, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1026, .cpu_id = 382, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1027, .cpu_id = 383, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1028, .cpu_id = 384, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1029, .cpu_id = 385, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1030, .cpu_id = 386, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1031, .cpu_id = 387, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1032, .cpu_id = 388, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1033, .cpu_id = 389, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1034, .cpu_id = 390, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1035, .cpu_id = 391, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1036, .cpu_id = 392, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1037, .cpu_id = 393, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1038, .cpu_id = 394, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1039, .cpu_id = 395, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1040, .cpu_id = 396, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1041, .cpu_id = 397, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1042, .cpu_id = 398, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1043, .cpu_id = 399, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1044, .cpu_id = 400, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1045, .cpu_id = 401, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1046, .cpu_id = 402, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1047, .cpu_id = 403, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1048, .cpu_id = 404, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1049, .cpu_id = 405, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1050, .cpu_id = 406, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1051, .cpu_id = 407, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1052, .cpu_id = 408, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1053, .cpu_id = 409, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1054, .cpu_id = 410, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1055, .cpu_id = 411, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1056, .cpu_id = 412, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1057, .cpu_id = 413, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1058, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1059, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1060, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1061, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1062, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1063, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1064, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1065, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1066, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1067, .cpu_id = 414, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1068, .cpu_id = 415, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1069, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1070, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1071, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1072, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1073, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1074, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1075, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1076, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1077, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1078, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1079, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1080, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1081, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1082, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1083, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1084, .cpu_id = 416, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1085, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1086, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1087, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1088, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1089, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1090, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1091, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1092, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1093, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1094, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1095, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1096, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1097, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1098, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1099, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1100, .cpu_id = 417, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1101, .cpu_id = 418, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1102, .cpu_id = 419, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1103, .cpu_id = 420, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1104, .cpu_id = 421, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1105, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1106, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1107, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1108, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1109, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1110, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1111, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1112, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1113, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1114, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1115, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1116, .cpu_id = 422, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1117, .cpu_id = 423, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1118, .cpu_id = 424, .valid = 1, - .msg = 0, .reset = 0, .name = "ROTATOR0_SERR" }, - { .fc_id = 1119, .cpu_id = 425, .valid = 1, - .msg = 0, .reset = 0, .name = "ROTATOR1_SERR" }, - { .fc_id = 1120, .cpu_id = 426, .valid = 1, - .msg = 0, .reset = 1, .name = "ROTATOR0_DERR" }, - { .fc_id = 1121, .cpu_id = 427, .valid = 1, - .msg = 0, .reset = 1, .name = "ROTATOR1_DERR" }, - { .fc_id = 1122, .cpu_id = 428, .valid = 1, - .msg = 0, .reset = 1, .name = "ROTATOR0_AXI_ERROR_RESPONSE" }, - { .fc_id = 1123, .cpu_id = 429, .valid = 1, - .msg = 0, .reset = 1, .name = "ROTATOR1_AXI_ERROR_RESPONSE" }, - { .fc_id = 1124, .cpu_id = 430, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1125, .cpu_id = 431, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1126, .cpu_id = 432, .valid = 1, - .msg = 0, .reset = 0, .name = "ROTATOR0_BMON_SPMU" }, - { .fc_id = 1127, .cpu_id = 433, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1128, .cpu_id = 434, .valid = 1, - .msg = 0, .reset = 0, .name = "ROTATOR1_BMON_SPMU" }, - { .fc_id = 1129, .cpu_id = 435, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1130, .cpu_id = 436, .valid = 1, - .msg = 0, .reset = 0, .name = "SM0_BMON_SPMU" }, - { .fc_id = 1131, .cpu_id = 437, .valid = 1, - .msg = 0, .reset = 0, .name = "SM1_BMON_SPMU" }, - { .fc_id = 1132, .cpu_id = 438, .valid = 1, - .msg = 0, .reset = 0, .name = "SM2_BMON_SPMU" }, - { .fc_id = 1133, .cpu_id = 439, .valid = 1, - .msg = 0, .reset = 0, .name = "SM3_BMON_SPMU" }, - { .fc_id = 1134, .cpu_id = 440, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1135, .cpu_id = 441, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1136, .cpu_id = 442, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1137, .cpu_id = 443, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1138, .cpu_id = 444, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1139, .cpu_id = 445, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1140, .cpu_id = 446, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1141, .cpu_id = 447, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1142, .cpu_id = 448, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1143, .cpu_id = 449, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1144, .cpu_id = 450, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1145, .cpu_id = 451, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1146, .cpu_id = 452, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1147, .cpu_id = 453, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1148, .cpu_id = 454, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1149, .cpu_id = 455, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1150, .cpu_id = 456, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1151, .cpu_id = 457, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1152, .cpu_id = 458, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1153, .cpu_id = 459, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1154, .cpu_id = 460, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1155, .cpu_id = 461, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1156, .cpu_id = 462, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1157, .cpu_id = 463, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1158, .cpu_id = 464, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1159, .cpu_id = 465, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1160, .cpu_id = 466, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1161, .cpu_id = 467, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1162, .cpu_id = 468, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1163, .cpu_id = 469, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1164, .cpu_id = 470, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1165, .cpu_id = 471, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1166, .cpu_id = 472, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1167, .cpu_id = 473, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1168, .cpu_id = 474, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1169, .cpu_id = 475, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1170, .cpu_id = 476, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1171, .cpu_id = 477, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1172, .cpu_id = 478, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1173, .cpu_id = 479, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1174, .cpu_id = 480, .valid = 1, - .msg = 1, .reset = 0, .name = "PSOC_DMA_QM" }, - { .fc_id = 1175, .cpu_id = 481, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1176, .cpu_id = 482, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1177, .cpu_id = 483, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1178, .cpu_id = 484, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1179, .cpu_id = 485, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1180, .cpu_id = 486, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1181, .cpu_id = 487, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1182, .cpu_id = 488, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1183, .cpu_id = 489, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1184, .cpu_id = 490, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1185, .cpu_id = 491, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1186, .cpu_id = 492, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1187, .cpu_id = 493, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1188, .cpu_id = 494, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1189, .cpu_id = 495, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1190, .cpu_id = 496, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1191, .cpu_id = 497, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1192, .cpu_id = 498, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1193, .cpu_id = 499, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1194, .cpu_id = 500, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1195, .cpu_id = 501, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1196, .cpu_id = 502, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1197, .cpu_id = 503, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1198, .cpu_id = 504, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1199, .cpu_id = 505, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1200, .cpu_id = 506, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1201, .cpu_id = 507, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1202, .cpu_id = 508, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1203, .cpu_id = 509, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1204, .cpu_id = 510, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1205, .cpu_id = 511, .valid = 0, - .msg = 0, .reset = 0, .name = "" }, - { .fc_id = 1206, .cpu_id = 512, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC0_QM" }, - { .fc_id = 1207, .cpu_id = 513, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC1_QM" }, - { .fc_id = 1208, .cpu_id = 514, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC2_QM" }, - { .fc_id = 1209, .cpu_id = 515, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC3_QM" }, - { .fc_id = 1210, .cpu_id = 516, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC4_QM" }, - { .fc_id = 1211, .cpu_id = 517, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC5_QM" }, - { .fc_id = 1212, .cpu_id = 518, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC6_QM" }, - { .fc_id = 1213, .cpu_id = 519, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC7_QM" }, - { .fc_id = 1214, .cpu_id = 520, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC8_QM" }, - { .fc_id = 1215, .cpu_id = 521, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC9_QM" }, - { .fc_id = 1216, .cpu_id = 522, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC10_QM" }, - { .fc_id = 1217, .cpu_id = 523, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC11_QM" }, - { .fc_id = 1218, .cpu_id = 524, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC12_QM" }, - { .fc_id = 1219, .cpu_id = 525, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC13_QM" }, - { .fc_id = 1220, .cpu_id = 526, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC14_QM" }, - { .fc_id = 1221, .cpu_id = 527, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC15_QM" }, - { .fc_id = 1222, .cpu_id = 528, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC16_QM" }, - { .fc_id = 1223, .cpu_id = 529, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC17_QM" }, - { .fc_id = 1224, .cpu_id = 530, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC18_QM" }, - { .fc_id = 1225, .cpu_id = 531, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC19_QM" }, - { .fc_id = 1226, .cpu_id = 532, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC20_QM" }, - { .fc_id = 1227, .cpu_id = 533, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC21_QM" }, - { .fc_id = 1228, .cpu_id = 534, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC22_QM" }, - { .fc_id = 1229, .cpu_id = 535, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC23_QM" }, - { .fc_id = 1230, .cpu_id = 536, .valid = 1, - .msg = 1, .reset = 0, .name = "TPC24_QM" }, - { .fc_id = 1231, .cpu_id = 537, .valid = 0, - .msg = 1, .reset = 0, .name = "" }, - { .fc_id = 1232, .cpu_id = 538, .valid = 1, - .msg = 1, .reset = 0, .name = "MME0_QM" }, - { .fc_id = 1233, .cpu_id = 539, .valid = 1, - .msg = 1, .reset = 0, .name = "MME1_QM" }, - { .fc_id = 1234, .cpu_id = 540, .valid = 1, - .msg = 1, .reset = 0, .name = "MME2_QM" }, - { .fc_id = 1235, .cpu_id = 541, .valid = 1, - .msg = 1, .reset = 0, .name = "MME3_QM" }, - { .fc_id = 1236, .cpu_id = 542, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA2_QM" }, - { .fc_id = 1237, .cpu_id = 543, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA3_QM" }, - { .fc_id = 1238, .cpu_id = 544, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA0_QM" }, - { .fc_id = 1239, .cpu_id = 545, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA1_QM" }, - { .fc_id = 1240, .cpu_id = 546, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA6_QM" }, - { .fc_id = 1241, .cpu_id = 547, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA7_QM" }, - { .fc_id = 1242, .cpu_id = 548, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA4_QM" }, - { .fc_id = 1243, .cpu_id = 549, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA5_QM" }, - { .fc_id = 1244, .cpu_id = 550, .valid = 1, - .msg = 1, .reset = 0, .name = "PDMA0_QM" }, - { .fc_id = 1245, .cpu_id = 551, .valid = 1, - .msg = 1, .reset = 0, .name = "PDMA1_QM" }, - { .fc_id = 1246, .cpu_id = 552, .valid = 1, - .msg = 1, .reset = 0, .name = "PI_UPDATE" }, - { .fc_id = 1247, .cpu_id = 553, .valid = 1, - .msg = 1, .reset = 0, .name = "HALT_MACHINE" }, - { .fc_id = 1248, .cpu_id = 554, .valid = 1, - .msg = 1, .reset = 0, .name = "INTS_REGISTER" }, - { .fc_id = 1249, .cpu_id = 555, .valid = 1, - .msg = 1, .reset = 0, .name = "ROT0_QM" }, - { .fc_id = 1250, .cpu_id = 556, .valid = 1, - .msg = 1, .reset = 0, .name = "ROT1_QM" }, - { .fc_id = 1251, .cpu_id = 557, .valid = 1, - .msg = 1, .reset = 0, .name = "SOFT_RESET" }, - { .fc_id = 1252, .cpu_id = 558, .valid = 1, - .msg = 1, .reset = 0, .name = "CPLD_SHUTDOWN_CAUSE" }, - { .fc_id = 1253, .cpu_id = 559, .valid = 1, - .msg = 1, .reset = 0, .name = "FIX_POWER_ENV_S" }, - { .fc_id = 1254, .cpu_id = 560, .valid = 1, - .msg = 1, .reset = 0, .name = "FIX_POWER_ENV_E" }, - { .fc_id = 1255, .cpu_id = 561, .valid = 1, - .msg = 1, .reset = 0, .name = "FIX_THERMAL_ENV_S" }, - { .fc_id = 1256, .cpu_id = 562, .valid = 1, - .msg = 1, .reset = 0, .name = "FIX_THERMAL_ENV_E" }, - { .fc_id = 1257, .cpu_id = 563, .valid = 1, - .msg = 1, .reset = 0, .name = "CPLD_SHUTDOWN_EVENT" }, - { .fc_id = 1258, .cpu_id = 564, .valid = 1, - .msg = 1, .reset = 0, .name = "PKT_QUEUE_OUT_SYNC" }, - { .fc_id = 1259, .cpu_id = 565, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA2_CORE" }, - { .fc_id = 1260, .cpu_id = 566, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA3_CORE" }, - { .fc_id = 1261, .cpu_id = 567, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA0_CORE" }, - { .fc_id = 1262, .cpu_id = 568, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA1_CORE" }, - { .fc_id = 1263, .cpu_id = 569, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA6_CORE" }, - { .fc_id = 1264, .cpu_id = 570, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA7_CORE" }, - { .fc_id = 1265, .cpu_id = 571, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA4_CORE" }, - { .fc_id = 1266, .cpu_id = 572, .valid = 1, - .msg = 1, .reset = 0, .name = "HDMA5_CORE" }, - { .fc_id = 1267, .cpu_id = 573, .valid = 1, - .msg = 1, .reset = 0, .name = "PDMA0_CORE" }, - { .fc_id = 1268, .cpu_id = 574, .valid = 1, - .msg = 1, .reset = 0, .name = "PDMA1_CORE" }, - { .fc_id = 1269, .cpu_id = 575, .valid = 1, - .msg = 1, .reset = 0, .name = "KDMA0_CORE" }, - { .fc_id = 1270, .cpu_id = 576, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC0_QM0" }, - { .fc_id = 1271, .cpu_id = 577, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC0_QM1" }, - { .fc_id = 1272, .cpu_id = 578, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC1_QM0" }, - { .fc_id = 1273, .cpu_id = 579, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC1_QM1" }, - { .fc_id = 1274, .cpu_id = 580, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC2_QM0" }, - { .fc_id = 1275, .cpu_id = 581, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC2_QM1" }, - { .fc_id = 1276, .cpu_id = 582, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC3_QM0" }, - { .fc_id = 1277, .cpu_id = 583, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC3_QM1" }, - { .fc_id = 1278, .cpu_id = 584, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC4_QM0" }, - { .fc_id = 1279, .cpu_id = 585, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC4_QM1" }, - { .fc_id = 1280, .cpu_id = 586, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC5_QM0" }, - { .fc_id = 1281, .cpu_id = 587, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC5_QM1" }, - { .fc_id = 1282, .cpu_id = 588, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC6_QM0" }, - { .fc_id = 1283, .cpu_id = 589, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC6_QM1" }, - { .fc_id = 1284, .cpu_id = 590, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC7_QM0" }, - { .fc_id = 1285, .cpu_id = 591, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC7_QM1" }, - { .fc_id = 1286, .cpu_id = 592, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC8_QM0" }, - { .fc_id = 1287, .cpu_id = 593, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC8_QM1" }, - { .fc_id = 1288, .cpu_id = 594, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC9_QM0" }, - { .fc_id = 1289, .cpu_id = 595, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC9_QM1" }, - { .fc_id = 1290, .cpu_id = 596, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC10_QM0" }, - { .fc_id = 1291, .cpu_id = 597, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC10_QM1" }, - { .fc_id = 1292, .cpu_id = 598, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC11_QM0" }, - { .fc_id = 1293, .cpu_id = 599, .valid = 1, - .msg = 1, .reset = 0, .name = "NIC11_QM1" }, - { .fc_id = 1294, .cpu_id = 600, .valid = 1, - .msg = 1, .reset = 0, .name = "CPU_PKT_SANITY_FAILED" }, - { .fc_id = 1295, .cpu_id = 601, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC0_ENG0" }, - { .fc_id = 1296, .cpu_id = 602, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC0_ENG1" }, - { .fc_id = 1297, .cpu_id = 603, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC1_ENG0" }, - { .fc_id = 1298, .cpu_id = 604, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC1_ENG1" }, - { .fc_id = 1299, .cpu_id = 605, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC2_ENG0" }, - { .fc_id = 1300, .cpu_id = 606, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC2_ENG1" }, - { .fc_id = 1301, .cpu_id = 607, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC3_ENG0" }, - { .fc_id = 1302, .cpu_id = 608, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC3_ENG1" }, - { .fc_id = 1303, .cpu_id = 609, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC4_ENG0" }, - { .fc_id = 1304, .cpu_id = 610, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC4_ENG1" }, - { .fc_id = 1305, .cpu_id = 611, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC5_ENG0" }, - { .fc_id = 1306, .cpu_id = 612, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC5_ENG1" }, - { .fc_id = 1307, .cpu_id = 613, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC6_ENG0" }, - { .fc_id = 1308, .cpu_id = 614, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC6_ENG1" }, - { .fc_id = 1309, .cpu_id = 615, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC7_ENG0" }, - { .fc_id = 1310, .cpu_id = 616, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC7_ENG1" }, - { .fc_id = 1311, .cpu_id = 617, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC8_ENG0" }, - { .fc_id = 1312, .cpu_id = 618, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC8_ENG1" }, - { .fc_id = 1313, .cpu_id = 619, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC9_ENG0" }, - { .fc_id = 1314, .cpu_id = 620, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC9_ENG1" }, - { .fc_id = 1315, .cpu_id = 621, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC10_ENG0" }, - { .fc_id = 1316, .cpu_id = 622, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC10_ENG1" }, - { .fc_id = 1317, .cpu_id = 623, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC11_ENG0" }, - { .fc_id = 1318, .cpu_id = 624, .valid = 1, - .msg = 1, .reset = 0, .name = "STATUS_NIC11_ENG1" }, - { .fc_id = 1319, .cpu_id = 625, .valid = 1, - .msg = 1, .reset = 0, .name = "ARC_DCCM_FULL" }, - { .fc_id = 1320, .cpu_id = 626, .valid = 1, - .msg = 1, .reset = 1, .name = "FP32_NOT_SUPPORTED" }, - { .fc_id = 1321, .cpu_id = 627, .valid = 1, - .msg = 1, .reset = 1, .name = "DEV_RESET_REQ" }, + { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 9, .cpu_id = 9, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 10, .cpu_id = 10, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 11, .cpu_id = 11, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 12, .cpu_id = 12, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 13, .cpu_id = 13, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 14, .cpu_id = 14, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 15, .cpu_id = 15, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 16, .cpu_id = 16, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 17, .cpu_id = 17, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 18, .cpu_id = 18, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 19, .cpu_id = 19, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 20, .cpu_id = 20, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 21, .cpu_id = 21, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 22, .cpu_id = 22, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 23, .cpu_id = 23, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 24, .cpu_id = 24, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 25, .cpu_id = 25, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 26, .cpu_id = 26, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 27, .cpu_id = 27, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 28, .cpu_id = 28, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 29, .cpu_id = 29, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 30, .cpu_id = 30, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 31, .cpu_id = 31, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 32, .cpu_id = 32, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PCIE_CORE_SERR" }, + { .fc_id = 33, .cpu_id = 33, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PCIE_CORE_DERR" }, + { .fc_id = 34, .cpu_id = 34, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PCIE_IF_SERR" }, + { .fc_id = 35, .cpu_id = 35, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PCIE_IF_DERR" }, + { .fc_id = 36, .cpu_id = 36, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PCIE_PHY_SERR" }, + { .fc_id = 37, .cpu_id = 37, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PCIE_PHY_DERR" }, + { .fc_id = 38, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC0_ECC_SERR" }, + { .fc_id = 39, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC1_ECC_SERR" }, + { .fc_id = 40, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC2_ECC_SERR" }, + { .fc_id = 41, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC3_ECC_SERR" }, + { .fc_id = 42, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC4_ECC_SERR" }, + { .fc_id = 43, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC5_ECC_SERR" }, + { .fc_id = 44, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC6_ECC_SERR" }, + { .fc_id = 45, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC7_ECC_SERR" }, + { .fc_id = 46, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC8_ECC_SERR" }, + { .fc_id = 47, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC9_ECC_SERR" }, + { .fc_id = 48, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC10_ECC_SERR" }, + { .fc_id = 49, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC11_ECC_SERR" }, + { .fc_id = 50, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC12_ECC_SERR" }, + { .fc_id = 51, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC13_ECC_SERR" }, + { .fc_id = 52, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC14_ECC_SERR" }, + { .fc_id = 53, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC15_ECC_SERR" }, + { .fc_id = 54, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC16_ECC_SERR" }, + { .fc_id = 55, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC17_ECC_SERR" }, + { .fc_id = 56, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC18_ECC_SERR" }, + { .fc_id = 57, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC19_ECC_SERR" }, + { .fc_id = 58, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC20_ECC_SERR" }, + { .fc_id = 59, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC21_ECC_SERR" }, + { .fc_id = 60, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC22_ECC_SERR" }, + { .fc_id = 61, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC23_ECC_SERR" }, + { .fc_id = 62, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC24_ECC_SERR" }, + { .fc_id = 63, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC0_ECC_DERR" }, + { .fc_id = 64, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC1_ECC_DERR" }, + { .fc_id = 65, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC2_ECC_DERR" }, + { .fc_id = 66, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC3_ECC_DERR" }, + { .fc_id = 67, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC4_ECC_DERR" }, + { .fc_id = 68, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC5_ECC_DERR" }, + { .fc_id = 69, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC6_ECC_DERR" }, + { .fc_id = 70, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC7_ECC_DERR" }, + { .fc_id = 71, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC8_ECC_DERR" }, + { .fc_id = 72, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC9_ECC_DERR" }, + { .fc_id = 73, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC10_ECC_DERR" }, + { .fc_id = 74, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC11_ECC_DERR" }, + { .fc_id = 75, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC12_ECC_DERR" }, + { .fc_id = 76, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC13_ECC_DERR" }, + { .fc_id = 77, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC14_ECC_DERR" }, + { .fc_id = 78, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC15_ECC_DERR" }, + { .fc_id = 79, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC16_ECC_DERR" }, + { .fc_id = 80, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC17_ECC_DERR" }, + { .fc_id = 81, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC18_ECC_DERR" }, + { .fc_id = 82, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC19_ECC_DERR" }, + { .fc_id = 83, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC20_ECC_DERR" }, + { .fc_id = 84, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC21_ECC_DERR" }, + { .fc_id = 85, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC22_ECC_DERR" }, + { .fc_id = 86, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC23_ECC_DERR" }, + { .fc_id = 87, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "TPC24_ECC_DERR" }, + { .fc_id = 88, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_SBTE0_ECC_SERR" }, + { .fc_id = 89, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_SBTE1_ECC_SERR" }, + { .fc_id = 90, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_SBTE2_ECC_SERR" }, + { .fc_id = 91, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_SBTE3_ECC_SERR" }, + { .fc_id = 92, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_SBTE4_ECC_SERR" }, + { .fc_id = 93, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_CTRL_ECC_SERR" }, + { .fc_id = 94, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_WAP_ECC_SERR" }, + { .fc_id = 95, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_SBTE0_ECC_SERR" }, + { .fc_id = 96, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_SBTE1_ECC_SERR" }, + { .fc_id = 97, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_SBTE2_ECC_SERR" }, + { .fc_id = 98, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_SBTE3_ECC_SERR" }, + { .fc_id = 99, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_SBTE4_ECC_SERR" }, + { .fc_id = 100, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_CTRL_ECC_SERR" }, + { .fc_id = 101, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_WAP_ECC_SERR" }, + { .fc_id = 102, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_SBTE0_ECC_SERR" }, + { .fc_id = 103, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_SBTE1_ECC_SERR" }, + { .fc_id = 104, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_SBTE2_ECC_SERR" }, + { .fc_id = 105, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_SBTE3_ECC_SERR" }, + { .fc_id = 106, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_SBTE4_ECC_SERR" }, + { .fc_id = 107, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_CTRL_ECC_SERR" }, + { .fc_id = 108, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_WAP_ECC_SERR" }, + { .fc_id = 109, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_SBTE0_ECC_SERR" }, + { .fc_id = 110, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_SBTE1_ECC_SERR" }, + { .fc_id = 111, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_SBTE2_ECC_SERR" }, + { .fc_id = 112, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_SBTE3_ECC_SERR" }, + { .fc_id = 113, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_SBTE4_ECC_SERR" }, + { .fc_id = 114, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_CTRL_ECC_SERR" }, + { .fc_id = 115, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_WAP_ECC_SERR" }, + { .fc_id = 116, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME0_SBTE0_ECC_DERR" }, + { .fc_id = 117, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME0_SBTE1_ECC_DERR" }, + { .fc_id = 118, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME0_SBTE2_ECC_DERR" }, + { .fc_id = 119, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME0_SBTE3_ECC_DERR" }, + { .fc_id = 120, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME0_SBTE4_ECC_DERR" }, + { .fc_id = 121, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME0_CTRL_ECC_DERR" }, + { .fc_id = 122, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME0_WAP_ECC_DERR" }, + { .fc_id = 123, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME1_SBTE0_ECC_DERR" }, + { .fc_id = 124, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME1_SBTE1_ECC_DERR" }, + { .fc_id = 125, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME1_SBTE2_ECC_DERR" }, + { .fc_id = 126, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME1_SBTE3_ECC_DERR" }, + { .fc_id = 127, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME1_SBTE4_ECC_DERR" }, + { .fc_id = 128, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME1_CTRL_ECC_DERR" }, + { .fc_id = 129, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME1_WAP_ECC_DERR" }, + { .fc_id = 130, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME2_SBTE0_ECC_DERR" }, + { .fc_id = 131, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME2_SBTE1_ECC_DERR" }, + { .fc_id = 132, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME2_SBTE2_ECC_DERR" }, + { .fc_id = 133, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME2_SBTE3_ECC_DERR" }, + { .fc_id = 134, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME2_SBTE4_ECC_DERR" }, + { .fc_id = 135, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME2_CTRL_ECC_DERR" }, + { .fc_id = 136, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME2_WAP_ECC_DERR" }, + { .fc_id = 137, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME3_SBTE0_ECC_DERR" }, + { .fc_id = 138, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME3_SBTE1_ECC_DERR" }, + { .fc_id = 139, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME3_SBTE2_ECC_DERR" }, + { .fc_id = 140, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME3_SBTE3_ECC_DERR" }, + { .fc_id = 141, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME3_SBTE4_ECC_DERR" }, + { .fc_id = 142, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME3_CTRL_ECC_DERR" }, + { .fc_id = 143, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "MME3_WAP_ECC_DERR" }, + { .fc_id = 144, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA2_ECC_SERR" }, + { .fc_id = 145, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA3_ECC_SERR" }, + { .fc_id = 146, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA0_ECC_SERR" }, + { .fc_id = 147, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA1_ECC_SERR" }, + { .fc_id = 148, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA6_ECC_SERR" }, + { .fc_id = 149, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA7_ECC_SERR" }, + { .fc_id = 150, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HDMA4_ECC_SERR" }, + { .fc_id = 151, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HDMA5_ECC_SERR" }, + { .fc_id = 152, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA2_ECC_DERR" }, + { .fc_id = 153, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA3_ECC_DERR" }, + { .fc_id = 154, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA0_ECC_DERR" }, + { .fc_id = 155, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA1_ECC_DERR" }, + { .fc_id = 156, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA6_ECC_DERR" }, + { .fc_id = 157, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA7_ECC_DERR" }, + { .fc_id = 158, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA4_ECC_DERR" }, + { .fc_id = 159, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "EDMA5_ECC_DERR" }, + { .fc_id = 160, .cpu_id = 50, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "KDMA0_ECC_SERR" }, + { .fc_id = 161, .cpu_id = 51, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PDMA0_ECC_SERR" }, + { .fc_id = 162, .cpu_id = 51, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PDMA1_ECC_SERR" }, + { .fc_id = 163, .cpu_id = 52, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "KDMA0_ECC_DERR" }, + { .fc_id = 164, .cpu_id = 53, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PDMA0_ECC_DERR" }, + { .fc_id = 165, .cpu_id = 53, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PDMA1_ECC_DERR" }, + { .fc_id = 166, .cpu_id = 54, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "CPU_IF_ECC_SERR" }, + { .fc_id = 167, .cpu_id = 55, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "CPU_IF_ECC_DERR" }, + { .fc_id = 168, .cpu_id = 56, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PSOC_MEM_SERR" }, + { .fc_id = 169, .cpu_id = 57, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PSOC_MEM_DERR" }, + { .fc_id = 170, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM0_ECC_SERR" }, + { .fc_id = 171, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM1_ECC_SERR" }, + { .fc_id = 172, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM2_ECC_SERR" }, + { .fc_id = 173, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM3_ECC_SERR" }, + { .fc_id = 174, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM4_ECC_SERR" }, + { .fc_id = 175, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM5_ECC_SERR" }, + { .fc_id = 176, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM6_ECC_SERR" }, + { .fc_id = 177, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM7_ECC_SERR" }, + { .fc_id = 178, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM8_ECC_SERR" }, + { .fc_id = 179, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM9_ECC_SERR" }, + { .fc_id = 180, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM10_ECC_SERR" }, + { .fc_id = 181, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM11_ECC_SERR" }, + { .fc_id = 182, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM12_ECC_SERR" }, + { .fc_id = 183, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM13_ECC_SERR" }, + { .fc_id = 184, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM14_ECC_SERR" }, + { .fc_id = 185, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM15_ECC_SERR" }, + { .fc_id = 186, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM16_ECC_SERR" }, + { .fc_id = 187, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM17_ECC_SERR" }, + { .fc_id = 188, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM18_ECC_SERR" }, + { .fc_id = 189, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM19_ECC_SERR" }, + { .fc_id = 190, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM20_ECC_SERR" }, + { .fc_id = 191, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM21_ECC_SERR" }, + { .fc_id = 192, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM22_ECC_SERR" }, + { .fc_id = 193, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM23_ECC_SERR" }, + { .fc_id = 194, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM24_ECC_SERR" }, + { .fc_id = 195, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM25_ECC_SERR" }, + { .fc_id = 196, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM26_ECC_SERR" }, + { .fc_id = 197, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM27_ECC_SERR" }, + { .fc_id = 198, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM28_ECC_SERR" }, + { .fc_id = 199, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM29_ECC_SERR" }, + { .fc_id = 200, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM30_ECC_SERR" }, + { .fc_id = 201, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SRAM31_ECC_SERR" }, + { .fc_id = 202, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM0_ECC_DERR" }, + { .fc_id = 203, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM1_ECC_DERR" }, + { .fc_id = 204, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM2_ECC_DERR" }, + { .fc_id = 205, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM3_ECC_DERR" }, + { .fc_id = 206, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM4_ECC_DERR" }, + { .fc_id = 207, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM5_ECC_DERR" }, + { .fc_id = 208, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM6_ECC_DERR" }, + { .fc_id = 209, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM7_ECC_DERR" }, + { .fc_id = 210, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM8_ECC_DERR" }, + { .fc_id = 211, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM9_ECC_DERR" }, + { .fc_id = 212, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM10_ECC_DERR" }, + { .fc_id = 213, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM11_ECC_DERR" }, + { .fc_id = 214, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM12_ECC_DERR" }, + { .fc_id = 215, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM13_ECC_DERR" }, + { .fc_id = 216, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM14_ECC_DERR" }, + { .fc_id = 217, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM15_ECC_DERR" }, + { .fc_id = 218, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM16_ECC_DERR" }, + { .fc_id = 219, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM17_ECC_DERR" }, + { .fc_id = 220, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM18_ECC_DERR" }, + { .fc_id = 221, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM19_ECC_DERR" }, + { .fc_id = 222, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM20_ECC_DERR" }, + { .fc_id = 223, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM21_ECC_DERR" }, + { .fc_id = 224, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM22_ECC_DERR" }, + { .fc_id = 225, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM23_ECC_DERR" }, + { .fc_id = 226, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM24_ECC_DERR" }, + { .fc_id = 227, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM25_ECC_DERR" }, + { .fc_id = 228, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM26_ECC_DERR" }, + { .fc_id = 229, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM27_ECC_DERR" }, + { .fc_id = 230, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM28_ECC_DERR" }, + { .fc_id = 231, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM29_ECC_DERR" }, + { .fc_id = 232, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM30_ECC_DERR" }, + { .fc_id = 233, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SRAM31_ECC_DERR" }, + { .fc_id = 234, .cpu_id = 60, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "GIC500" }, + { .fc_id = 235, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_0_MC0_ECC_SERR" }, + { .fc_id = 236, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_1_MC0_ECC_SERR" }, + { .fc_id = 237, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_2_MC0_ECC_SERR" }, + { .fc_id = 238, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_3_MC0_ECC_SERR" }, + { .fc_id = 239, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_4_MC0_ECC_SERR" }, + { .fc_id = 240, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_5_MC0_ECC_SERR" }, + { .fc_id = 241, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_0_MC1_ECC_SERR" }, + { .fc_id = 242, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_1_MC1_ECC_SERR" }, + { .fc_id = 243, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_2_MC1_ECC_SERR" }, + { .fc_id = 244, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_3_MC1_ECC_SERR" }, + { .fc_id = 245, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_4_MC1_ECC_SERR" }, + { .fc_id = 246, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM_5_MC1_ECC_SERR" }, + { .fc_id = 247, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_0_MC0_ECC_DERR" }, + { .fc_id = 248, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_1_MC0_ECC_DERR" }, + { .fc_id = 249, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_2_MC0_ECC_DERR" }, + { .fc_id = 250, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_3_MC0_ECC_DERR" }, + { .fc_id = 251, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_4_MC0_ECC_DERR" }, + { .fc_id = 252, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_5_MC0_ECC_DERR" }, + { .fc_id = 253, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_0_MC1_ECC_DERR" }, + { .fc_id = 254, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_1_MC1_ECC_DERR" }, + { .fc_id = 255, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_2_MC1_ECC_DERR" }, + { .fc_id = 256, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_3_MC1_ECC_DERR" }, + { .fc_id = 257, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_4_MC1_ECC_DERR" }, + { .fc_id = 258, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_5_MC1_ECC_DERR" }, + { .fc_id = 259, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_0_ECC_SERR" }, + { .fc_id = 260, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_1_ECC_SERR" }, + { .fc_id = 261, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_2_ECC_SERR" }, + { .fc_id = 262, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_3_ECC_SERR" }, + { .fc_id = 263, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_8_ECC_SERR" }, + { .fc_id = 264, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_9_ECC_SERR" }, + { .fc_id = 265, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_10_ECC_SERR" }, + { .fc_id = 266, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_11_ECC_SERR" }, + { .fc_id = 267, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_7_ECC_SERR" }, + { .fc_id = 268, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_6_ECC_SERR" }, + { .fc_id = 269, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_5_ECC_SERR" }, + { .fc_id = 270, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_4_ECC_SERR" }, + { .fc_id = 271, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_15_ECC_SERR" }, + { .fc_id = 272, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_14_ECC_SERR" }, + { .fc_id = 273, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_13_ECC_SERR" }, + { .fc_id = 274, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU_12_ECC_SERR" }, + { .fc_id = 275, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_0_ECC_DERR" }, + { .fc_id = 276, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_1_ECC_DERR" }, + { .fc_id = 277, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_2_ECC_DERR" }, + { .fc_id = 278, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_3_ECC_DERR" }, + { .fc_id = 279, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_8_ECC_DERR" }, + { .fc_id = 280, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_9_ECC_DERR" }, + { .fc_id = 281, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_10_ECC_DERR" }, + { .fc_id = 282, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_11_ECC_DERR" }, + { .fc_id = 283, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_7_ECC_DERR" }, + { .fc_id = 284, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_6_ECC_DERR" }, + { .fc_id = 285, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_5_ECC_DERR" }, + { .fc_id = 286, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_4_ECC_DERR" }, + { .fc_id = 287, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_15_ECC_DERR" }, + { .fc_id = 288, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_14_ECC_DERR" }, + { .fc_id = 289, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_13_ECC_DERR" }, + { .fc_id = 290, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_12_ECC_DERR" }, + { .fc_id = 291, .cpu_id = 65, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PMMU_ECC_SERR" }, + { .fc_id = 292, .cpu_id = 66, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PMMU_ECC_DERR" }, + { .fc_id = 293, .cpu_id = 67, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 294, .cpu_id = 68, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 295, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC0_VCD_ECC_SERR" }, + { .fc_id = 296, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC1_VCD_ECC_SERR" }, + { .fc_id = 297, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC2_VCD_ECC_SERR" }, + { .fc_id = 298, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC3_VCD_ECC_SERR" }, + { .fc_id = 299, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC4_VCD_ECC_SERR" }, + { .fc_id = 300, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC5_VCD_ECC_SERR" }, + { .fc_id = 301, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC6_VCD_ECC_SERR" }, + { .fc_id = 302, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC7_VCD_ECC_SERR" }, + { .fc_id = 303, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC8_VCD_ECC_SERR" }, + { .fc_id = 304, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC9_VCD_ECC_SERR" }, + { .fc_id = 305, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC0_L2C_ECC_SERR" }, + { .fc_id = 306, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC1_L2C_ECC_SERR" }, + { .fc_id = 307, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC2_L2C_ECC_SERR" }, + { .fc_id = 308, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC3_L2C_ECC_SERR" }, + { .fc_id = 309, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC4_L2C_ECC_SERR" }, + { .fc_id = 310, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC5_L2C_ECC_SERR" }, + { .fc_id = 311, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC6_L2C_ECC_SERR" }, + { .fc_id = 312, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC7_L2C_ECC_SERR" }, + { .fc_id = 313, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC8_L2C_ECC_SERR" }, + { .fc_id = 314, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC9_L2C_ECC_SERR" }, + { .fc_id = 315, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC0_VCD_ECC_DERR" }, + { .fc_id = 316, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC1_VCD_ECC_DERR" }, + { .fc_id = 317, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC2_VCD_ECC_DERR" }, + { .fc_id = 318, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC3_VCD_ECC_DERR" }, + { .fc_id = 319, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC4_VCD_ECC_DERR" }, + { .fc_id = 320, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC5_VCD_ECC_DERR" }, + { .fc_id = 321, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC6_VCD_ECC_DERR" }, + { .fc_id = 322, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC7_VCD_ECC_DERR" }, + { .fc_id = 323, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC8_VCD_ECC_DERR" }, + { .fc_id = 324, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC9_VCD_ECC_DERR" }, + { .fc_id = 325, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC0_L2C_ECC_DERR" }, + { .fc_id = 326, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC1_L2C_ECC_DERR" }, + { .fc_id = 327, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC2_L2C_ECC_DERR" }, + { .fc_id = 328, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC3_L2C_ECC_DERR" }, + { .fc_id = 329, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC4_L2C_ECC_DERR" }, + { .fc_id = 330, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC5_L2C_ECC_DERR" }, + { .fc_id = 331, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC6_L2C_ECC_DERR" }, + { .fc_id = 332, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC7_L2C_ECC_DERR" }, + { .fc_id = 333, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC8_L2C_ECC_DERR" }, + { .fc_id = 334, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEC9_L2C_ECC_DERR" }, + { .fc_id = 335, .cpu_id = 71, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 336, .cpu_id = 72, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 337, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF0_ECC_SERR" }, + { .fc_id = 338, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF1_ECC_SERR" }, + { .fc_id = 339, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF2_ECC_SERR" }, + { .fc_id = 340, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF3_ECC_SERR" }, + { .fc_id = 341, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF8_ECC_SERR" }, + { .fc_id = 342, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF9_ECC_SERR" }, + { .fc_id = 343, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF10_ECC_SERR" }, + { .fc_id = 344, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF11_ECC_SERR" }, + { .fc_id = 345, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF7_ECC_SERR" }, + { .fc_id = 346, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF6_ECC_SERR" }, + { .fc_id = 347, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF5_ECC_SERR" }, + { .fc_id = 348, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF4_ECC_SERR" }, + { .fc_id = 349, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF15_ECC_SERR" }, + { .fc_id = 350, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF14_ECC_SERR" }, + { .fc_id = 351, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF13_ECC_SERR" }, + { .fc_id = 352, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HIF12_ECC_SERR" }, + { .fc_id = 353, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF0_ECC_DERR" }, + { .fc_id = 354, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF1_ECC_DERR" }, + { .fc_id = 355, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF2_ECC_DERR" }, + { .fc_id = 356, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF3_ECC_DERR" }, + { .fc_id = 357, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF8_ECC_DERR" }, + { .fc_id = 358, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF9_ECC_DERR" }, + { .fc_id = 359, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF10_ECC_DERR" }, + { .fc_id = 360, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF11_ECC_DERR" }, + { .fc_id = 361, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF7_ECC_DERR" }, + { .fc_id = 362, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF6_ECC_DERR" }, + { .fc_id = 363, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF5_ECC_DERR" }, + { .fc_id = 364, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF4_ECC_DERR" }, + { .fc_id = 365, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF15_ECC_DERR" }, + { .fc_id = 366, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF14_ECC_DERR" }, + { .fc_id = 367, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF13_ECC_DERR" }, + { .fc_id = 368, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF12_ECC_DERR" }, + { .fc_id = 369, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC0_ECC_SERR" }, + { .fc_id = 370, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC1_ECC_SERR" }, + { .fc_id = 371, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC2_ECC_SERR" }, + { .fc_id = 372, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC3_ECC_SERR" }, + { .fc_id = 373, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC4_ECC_SERR" }, + { .fc_id = 374, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC5_ECC_SERR" }, + { .fc_id = 375, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC6_ECC_SERR" }, + { .fc_id = 376, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC7_ECC_SERR" }, + { .fc_id = 377, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC8_ECC_SERR" }, + { .fc_id = 378, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC9_ECC_SERR" }, + { .fc_id = 379, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC10_ECC_SERR" }, + { .fc_id = 380, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC11_ECC_SERR" }, + { .fc_id = 381, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC0_ECC_DERR" }, + { .fc_id = 382, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC1_ECC_DERR" }, + { .fc_id = 383, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC2_ECC_DERR" }, + { .fc_id = 384, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC3_ECC_DERR" }, + { .fc_id = 385, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC4_ECC_DERR" }, + { .fc_id = 386, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC5_ECC_DERR" }, + { .fc_id = 387, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC6_ECC_DERR" }, + { .fc_id = 388, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC7_ECC_DERR" }, + { .fc_id = 389, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC8_ECC_DERR" }, + { .fc_id = 390, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC9_ECC_DERR" }, + { .fc_id = 391, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC10_ECC_DERR" }, + { .fc_id = 392, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC11_ECC_DERR" }, + { .fc_id = 393, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SM0_ECC_DERR" }, + { .fc_id = 394, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SM1_ECC_DERR" }, + { .fc_id = 395, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SM2_ECC_DERR" }, + { .fc_id = 396, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "SM3_ECC_DERR" }, + { .fc_id = 397, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM0_ECC_SERR" }, + { .fc_id = 398, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM1_ECC_SERR" }, + { .fc_id = 399, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM2_ECC_SERR" }, + { .fc_id = 400, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM3_ECC_SERR" }, + { .fc_id = 401, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "XBAR0_ECC_SERR" }, + { .fc_id = 402, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "XBAR1_ECC_SERR" }, + { .fc_id = 403, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "XBAR2_ECC_SERR" }, + { .fc_id = 404, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "XBAR3_ECC_SERR" }, + { .fc_id = 405, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "XBAR0_ECC_DERR" }, + { .fc_id = 406, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "XBAR1_ECC_DERR" }, + { .fc_id = 407, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "XBAR2_ECC_DERR" }, + { .fc_id = 408, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "XBAR3_ECC_DERR" }, + { .fc_id = 409, .cpu_id = 81, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "ARC0_ECC_SERR" }, + { .fc_id = 410, .cpu_id = 82, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "ARC0_ECC_DERR" }, + { .fc_id = 411, .cpu_id = 83, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 412, .cpu_id = 84, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PCIE_ADDR_DEC_ERR" }, + { .fc_id = 413, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC0_AXI_ERR_RSP" }, + { .fc_id = 414, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC1_AXI_ERR_RSP" }, + { .fc_id = 415, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC2_AXI_ERR_RSP" }, + { .fc_id = 416, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC3_AXI_ERR_RSP" }, + { .fc_id = 417, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC4_AXI_ERR_RSP" }, + { .fc_id = 418, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC5_AXI_ERR_RSP" }, + { .fc_id = 419, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC6_AXI_ERR_RSP" }, + { .fc_id = 420, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC7_AXI_ERR_RSP" }, + { .fc_id = 421, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC8_AXI_ERR_RSP" }, + { .fc_id = 422, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC9_AXI_ERR_RSP" }, + { .fc_id = 423, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC10_AXI_ERR_RSP" }, + { .fc_id = 424, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC11_AXI_ERR_RSP" }, + { .fc_id = 425, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC12_AXI_ERR_RSP" }, + { .fc_id = 426, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC13_AXI_ERR_RSP" }, + { .fc_id = 427, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC14_AXI_ERR_RSP" }, + { .fc_id = 428, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC15_AXI_ERR_RSP" }, + { .fc_id = 429, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC16_AXI_ERR_RSP" }, + { .fc_id = 430, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC17_AXI_ERR_RSP" }, + { .fc_id = 431, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC18_AXI_ERR_RSP" }, + { .fc_id = 432, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC19_AXI_ERR_RSP" }, + { .fc_id = 433, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC20_AXI_ERR_RSP" }, + { .fc_id = 434, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC21_AXI_ERR_RSP" }, + { .fc_id = 435, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC22_AXI_ERR_RSP" }, + { .fc_id = 436, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC23_AXI_ERR_RSP" }, + { .fc_id = 437, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC24_AXI_ERR_RSP" }, + { .fc_id = 438, .cpu_id = 86, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "AXI_ECC" }, + { .fc_id = 439, .cpu_id = 87, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "L2_RAM_ECC" }, + { .fc_id = 440, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 441, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 442, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 443, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 444, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 445, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 446, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_QMAN_SW_ERROR" }, + { .fc_id = 447, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 448, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 449, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 450, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 451, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 452, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 453, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_QMAN_SW_ERROR" }, + { .fc_id = 454, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 455, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 456, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 457, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 458, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 459, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 460, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_QMAN_SW_ERROR" }, + { .fc_id = 461, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_SBTE0_AXI_ERR_RSP" }, + { .fc_id = 462, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_SBTE1_AXI_ERR_RSP" }, + { .fc_id = 463, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_SBTE2_AXI_ERR_RSP" }, + { .fc_id = 464, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_SBTE3_AXI_ERR_RSP" }, + { .fc_id = 465, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_SBTE4_AXI_ERR_RSP" }, + { .fc_id = 466, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_CTRL_AXI_ERROR_RESPONSE" }, + { .fc_id = 467, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_QMAN_SW_ERROR" }, + { .fc_id = 468, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PSOC_MME_PLL_LOCK_ERR" }, + { .fc_id = 469, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PSOC_CPU_PLL_LOCK_ERR" }, + { .fc_id = 470, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE3_TPC_PLL_LOCK_ERR" }, + { .fc_id = 471, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE3_NIC_PLL_LOCK_ERR" }, + { .fc_id = 472, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE3_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 473, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE3_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 474, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE3_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 475, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE3_XBAR_BANK_PLL_LOCK_ERR" }, + { .fc_id = 476, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 477, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 478, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 479, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_XBAR_MESH_PLL_LOCK_ERR" }, + { .fc_id = 480, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_TPC_PLL_LOCK_ERR" }, + { .fc_id = 481, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_NIC_PLL_LOCK_ERR" }, + { .fc_id = 482, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PMMU_MME_PLL_LOCK_ERR" }, + { .fc_id = 483, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE0_TPC_PLL_LOCK_ERR" }, + { .fc_id = 484, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE0_PCI_PLL_LOCK_ERR" }, + { .fc_id = 485, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE0_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 486, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE0_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 487, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE0_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 488, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE0_XBAR_MESH_PLL_LOCK_ERR" }, + { .fc_id = 489, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE2_XBAR_MMU_PLL_LOCK_ERR" }, + { .fc_id = 490, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE2_XBAR_DMA_PLL_LOCK_ERR" }, + { .fc_id = 491, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE2_XBAR_IF_PLL_LOCK_ERR" }, + { .fc_id = 492, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE2_XBAR_BANK_PLL_LOCK_ERR" }, + { .fc_id = 493, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE2_TPC_PLL_LOCK_ERR" }, + { .fc_id = 494, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PSOC_VID_PLL_LOCK_ERR" }, + { .fc_id = 495, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PMMU_VID_PLL_LOCK_ERR" }, + { .fc_id = 496, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE3_HBM_PLL_LOCK_ERR" }, + { .fc_id = 497, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_XBAR_HBM_PLL_LOCK_ERR" }, + { .fc_id = 498, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE1_HBM_PLL_LOCK_ERR" }, + { .fc_id = 499, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE0_HBM_PLL_LOCK_ERR" }, + { .fc_id = 500, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE2_XBAR_HBM_PLL_LOCK_ERR" }, + { .fc_id = 501, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DCORE2_HBM_PLL_LOCK_ERR" }, + { .fc_id = 502, .cpu_id = 93, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "CPU_AXI_ERR_RSP" }, + { .fc_id = 503, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_0_AXI_ERR_RSP" }, + { .fc_id = 504, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_1_AXI_ERR_RSP" }, + { .fc_id = 505, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_2_AXI_ERR_RSP" }, + { .fc_id = 506, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_3_AXI_ERR_RSP" }, + { .fc_id = 507, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_8_AXI_ERR_RSP" }, + { .fc_id = 508, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_9_AXI_ERR_RSP" }, + { .fc_id = 509, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_10_AXI_ERR_RSP" }, + { .fc_id = 510, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_11_AXI_ERR_RSP" }, + { .fc_id = 511, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_7_AXI_ERR_RSP" }, + { .fc_id = 512, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_6_AXI_ERR_RSP" }, + { .fc_id = 513, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_5_AXI_ERR_RSP" }, + { .fc_id = 514, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_4_AXI_ERR_RSP" }, + { .fc_id = 515, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_15_AXI_ERR_RSP" }, + { .fc_id = 516, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_14_AXI_ERR_RSP" }, + { .fc_id = 517, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_13_AXI_ERR_RSP" }, + { .fc_id = 518, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU_12_AXI_ERR_RSP" }, + { .fc_id = 519, .cpu_id = 95, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PMMU_FATAL" }, + { .fc_id = 520, .cpu_id = 96, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PMMU_AXI_ERR_RSP" }, + { .fc_id = 521, .cpu_id = 97, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM0_ALARM_A" }, + { .fc_id = 522, .cpu_id = 98, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM0_ALARM_B" }, + { .fc_id = 523, .cpu_id = 99, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM1_ALARM_A" }, + { .fc_id = 524, .cpu_id = 100, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM1_ALARM_B" }, + { .fc_id = 525, .cpu_id = 101, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM2_ALARM_A" }, + { .fc_id = 526, .cpu_id = 102, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM2_ALARM_B" }, + { .fc_id = 527, .cpu_id = 103, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM3_ALARM_A" }, + { .fc_id = 528, .cpu_id = 104, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "VM3_ALARM_B" }, + { .fc_id = 529, .cpu_id = 105, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PSOC_AXI_ERR_RSP" }, + { .fc_id = 530, .cpu_id = 106, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PSOC_PRSTN_FALL" }, + { .fc_id = 531, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 532, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 533, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 534, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 535, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 536, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 537, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 538, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 539, .cpu_id = 108, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "KDMA_CH0_AXI_ERR_RSP" }, + { .fc_id = 540, .cpu_id = 109, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "PDMA_CH0_AXI_ERR_RSP" }, + { .fc_id = 541, .cpu_id = 109, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "PDMA_CH1_AXI_ERR_RSP" }, + { .fc_id = 542, .cpu_id = 110, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_CATTRIP_0" }, + { .fc_id = 543, .cpu_id = 111, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_CATTRIP_1" }, + { .fc_id = 544, .cpu_id = 112, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_CATTRIP_2" }, + { .fc_id = 545, .cpu_id = 113, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_CATTRIP_3" }, + { .fc_id = 546, .cpu_id = 114, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_CATTRIP_4" }, + { .fc_id = 547, .cpu_id = 115, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM_CATTRIP_5" }, + { .fc_id = 548, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM0_MC0_SEI_SEVERE" }, + { .fc_id = 549, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM0_MC0_SEI_NON_SEVERE" }, + { .fc_id = 550, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM0_MC1_SEI_SEVERE" }, + { .fc_id = 551, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM0_MC1_SEI_NON_SEVERE" }, + { .fc_id = 552, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM1_MC0_SEI_SEVERE" }, + { .fc_id = 553, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM1_MC0_SEI_NON_SEVERE" }, + { .fc_id = 554, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM1_MC1_SEI_SEVERE" }, + { .fc_id = 555, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM1_MC1_SEI_NON_SEVERE" }, + { .fc_id = 556, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM2_MC0_SEI_SEVERE" }, + { .fc_id = 557, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM2_MC0_SEI_NON_SEVERE" }, + { .fc_id = 558, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM2_MC1_SEI_SEVERE" }, + { .fc_id = 559, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM2_MC1_SEI_NON_SEVERE" }, + { .fc_id = 560, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM3_MC0_SEI_SEVERE" }, + { .fc_id = 561, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM3_MC0_SEI_NON_SEVERE" }, + { .fc_id = 562, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM3_MC1_SEI_SEVERE" }, + { .fc_id = 563, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM3_MC1_SEI_NON_SEVERE" }, + { .fc_id = 564, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM4_MC0_SEI_SEVERE" }, + { .fc_id = 565, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM4_MC0_SEI_NON_SEVERE" }, + { .fc_id = 566, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM4_MC1_SEI_SEVERE" }, + { .fc_id = 567, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM4_MC1_SEI_NON_SEVERE" }, + { .fc_id = 568, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM5_MC0_SEI_SEVERE" }, + { .fc_id = 569, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM5_MC0_SEI_NON_SEVERE" }, + { .fc_id = 570, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HBM5_MC1_SEI_SEVERE" }, + { .fc_id = 571, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM5_MC1_SEI_NON_SEVERE" }, + { .fc_id = 572, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC0_AXI_ERR_RSPONSE" }, + { .fc_id = 573, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC1_AXI_ERR_RSPONSE" }, + { .fc_id = 574, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC2_AXI_ERR_RSPONSE" }, + { .fc_id = 575, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC3_AXI_ERR_RSPONSE" }, + { .fc_id = 576, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC4_AXI_ERR_RSPONSE" }, + { .fc_id = 577, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC5_AXI_ERR_RSPONSE" }, + { .fc_id = 578, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC6_AXI_ERR_RSPONSE" }, + { .fc_id = 579, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC7_AXI_ERR_RSPONSE" }, + { .fc_id = 580, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC8_AXI_ERR_RSPONSE" }, + { .fc_id = 581, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC9_AXI_ERR_RSPONSE" }, + { .fc_id = 582, .cpu_id = 118, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 583, .cpu_id = 119, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 584, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF0_FATAL" }, + { .fc_id = 585, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF1_FATAL" }, + { .fc_id = 586, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF2_FATAL" }, + { .fc_id = 587, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF3_FATAL" }, + { .fc_id = 588, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF8_FATAL" }, + { .fc_id = 589, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF9_FATAL" }, + { .fc_id = 590, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF10_FATAL" }, + { .fc_id = 591, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF11_FATAL" }, + { .fc_id = 592, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF7_FATAL" }, + { .fc_id = 593, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF6_FATAL" }, + { .fc_id = 594, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF5_FATAL" }, + { .fc_id = 595, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF4_FATAL" }, + { .fc_id = 596, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF15_FATAL" }, + { .fc_id = 597, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF14_FATAL" }, + { .fc_id = 598, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF13_FATAL" }, + { .fc_id = 599, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HIF12_FATAL" }, + { .fc_id = 600, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC0_AXI_ERROR_RESPONSE" }, + { .fc_id = 601, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC1_AXI_ERROR_RESPONSE" }, + { .fc_id = 602, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC2_AXI_ERROR_RESPONSE" }, + { .fc_id = 603, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC3_AXI_ERROR_RESPONSE" }, + { .fc_id = 604, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC4_AXI_ERROR_RESPONSE" }, + { .fc_id = 605, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC5_AXI_ERROR_RESPONSE" }, + { .fc_id = 606, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC6_AXI_ERROR_RESPONSE" }, + { .fc_id = 607, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC7_AXI_ERROR_RESPONSE" }, + { .fc_id = 608, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC8_AXI_ERROR_RESPONSE" }, + { .fc_id = 609, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC9_AXI_ERROR_RESPONSE" }, + { .fc_id = 610, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC10_AXI_ERROR_RESPONSE" }, + { .fc_id = 611, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC11_AXI_ERROR_RESPONSE" }, + { .fc_id = 612, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "SM0_AXI_ERROR_RESPONSE" }, + { .fc_id = 613, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "SM1_AXI_ERROR_RESPONSE" }, + { .fc_id = 614, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "SM2_AXI_ERROR_RESPONSE" }, + { .fc_id = 615, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "SM3_AXI_ERROR_RESPONSE" }, + { .fc_id = 616, .cpu_id = 123, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "ARC_AXI_ERROR_RESPONSE" }, + { .fc_id = 617, .cpu_id = 124, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 618, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 619, .cpu_id = 125, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PCIE_FLR_REQUESTED" }, + { .fc_id = 620, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 621, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 622, .cpu_id = 125, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PCIE_APB_TIMEOUT" }, + { .fc_id = 623, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 624, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 625, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 626, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 627, .cpu_id = 125, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PCIE_FATAL_ERR" }, + { .fc_id = 628, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 629, .cpu_id = 126, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 630, .cpu_id = 127, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 631, .cpu_id = 128, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PCIE_P2P_MSIX" }, + { .fc_id = 632, .cpu_id = 129, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PCIE_DRAIN_COMPLETE" }, + { .fc_id = 633, .cpu_id = 130, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC0_BMON_SPMU" }, + { .fc_id = 634, .cpu_id = 131, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC0_KERNEL_ERR" }, + { .fc_id = 635, .cpu_id = 132, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC1_BMON_SPMU" }, + { .fc_id = 636, .cpu_id = 133, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC1_KERNEL_ERR" }, + { .fc_id = 637, .cpu_id = 134, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC2_BMON_SPMU" }, + { .fc_id = 638, .cpu_id = 135, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC2_KERNEL_ERR" }, + { .fc_id = 639, .cpu_id = 136, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC3_BMON_SPMU" }, + { .fc_id = 640, .cpu_id = 137, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC3_KERNEL_ERR" }, + { .fc_id = 641, .cpu_id = 138, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC4_BMON_SPMU" }, + { .fc_id = 642, .cpu_id = 139, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC4_KERNEL_ERR" }, + { .fc_id = 643, .cpu_id = 140, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC5_BMON_SPMU" }, + { .fc_id = 644, .cpu_id = 141, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC5_KERNEL_ERR" }, + { .fc_id = 645, .cpu_id = 150, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC6_BMON_SPMU" }, + { .fc_id = 646, .cpu_id = 151, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC6_KERNEL_ERR" }, + { .fc_id = 647, .cpu_id = 152, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC7_BMON_SPMU" }, + { .fc_id = 648, .cpu_id = 153, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC7_KERNEL_ERR" }, + { .fc_id = 649, .cpu_id = 146, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC8_BMON_SPMU" }, + { .fc_id = 650, .cpu_id = 147, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC8_KERNEL_ERR" }, + { .fc_id = 651, .cpu_id = 148, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC9_BMON_SPMU" }, + { .fc_id = 652, .cpu_id = 149, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC9_KERNEL_ERR" }, + { .fc_id = 653, .cpu_id = 142, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC10_BMON_SPMU" }, + { .fc_id = 654, .cpu_id = 143, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC10_KERNEL_ERR" }, + { .fc_id = 655, .cpu_id = 144, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC11_BMON_SPMU" }, + { .fc_id = 656, .cpu_id = 145, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC11_KERNEL_ERR" }, + { .fc_id = 657, .cpu_id = 162, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC12_BMON_SPMU" }, + { .fc_id = 658, .cpu_id = 163, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC12_KERNEL_ERR" }, + { .fc_id = 659, .cpu_id = 164, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC13_BMON_SPMU" }, + { .fc_id = 660, .cpu_id = 165, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC13_KERNEL_ERR" }, + { .fc_id = 661, .cpu_id = 158, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC14_BMON_SPMU" }, + { .fc_id = 662, .cpu_id = 159, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC14_KERNEL_ERR" }, + { .fc_id = 663, .cpu_id = 160, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC15_BMON_SPMU" }, + { .fc_id = 664, .cpu_id = 161, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC15_KERNEL_ERR" }, + { .fc_id = 665, .cpu_id = 154, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC16_BMON_SPMU" }, + { .fc_id = 666, .cpu_id = 155, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC16_KERNEL_ERR" }, + { .fc_id = 667, .cpu_id = 156, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC17_BMON_SPMU" }, + { .fc_id = 668, .cpu_id = 157, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC17_KERNEL_ERR" }, + { .fc_id = 669, .cpu_id = 166, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC18_BMON_SPMU" }, + { .fc_id = 670, .cpu_id = 167, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC18_KERNEL_ERR" }, + { .fc_id = 671, .cpu_id = 168, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC19_BMON_SPMU" }, + { .fc_id = 672, .cpu_id = 169, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC19_KERNEL_ERR" }, + { .fc_id = 673, .cpu_id = 170, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC20_BMON_SPMU" }, + { .fc_id = 674, .cpu_id = 171, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC20_KERNEL_ERR" }, + { .fc_id = 675, .cpu_id = 172, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC21_BMON_SPMU" }, + { .fc_id = 676, .cpu_id = 173, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC21_KERNEL_ERR" }, + { .fc_id = 677, .cpu_id = 174, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC22_BMON_SPMU" }, + { .fc_id = 678, .cpu_id = 175, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC22_KERNEL_ERR" }, + { .fc_id = 679, .cpu_id = 176, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC23_BMON_SPMU" }, + { .fc_id = 680, .cpu_id = 177, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC23_KERNEL_ERR" }, + { .fc_id = 681, .cpu_id = 178, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "TPC24_BMON_SPMU" }, + { .fc_id = 682, .cpu_id = 179, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC24_KERNEL_ERR" }, + { .fc_id = 683, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 684, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 685, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 686, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 687, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 688, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_CTRL_BMON_SPMU" }, + { .fc_id = 689, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_SBTE_BMON_SPMU" }, + { .fc_id = 690, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME0_WAP_BMON_SPMU" }, + { .fc_id = 691, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 692, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 693, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 694, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 695, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 696, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 697, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_CTRL_BMON_SPMU" }, + { .fc_id = 698, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_SBTE_BMON_SPMU" }, + { .fc_id = 699, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME1_WAP_BMON_SPMU" }, + { .fc_id = 700, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 701, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 702, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 703, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 704, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 705, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 706, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_CTRL_BMON_SPMU" }, + { .fc_id = 707, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_SBTE_BMON_SPMU" }, + { .fc_id = 708, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME2_WAP_BMON_SPMU" }, + { .fc_id = 709, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 710, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 711, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 712, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 713, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 714, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 715, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_CTRL_BMON_SPMU" }, + { .fc_id = 716, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_SBTE_BMON_SPMU" }, + { .fc_id = 717, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "MME3_WAP_BMON_SPMU" }, + { .fc_id = 718, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_WAP_SOURCE_RESULT_INVALID" }, + { .fc_id = 719, .cpu_id = 184, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 720, .cpu_id = 184, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU0_PAGE_FAULT_OR_WR_PERM" }, + { .fc_id = 721, .cpu_id = 184, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU0_SECURITY_ERROR" }, + { .fc_id = 722, .cpu_id = 185, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 723, .cpu_id = 185, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU1_PAGE_FAULT_WR_PERM" }, + { .fc_id = 724, .cpu_id = 185, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU1_SECURITY_ERROR" }, + { .fc_id = 725, .cpu_id = 186, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 726, .cpu_id = 186, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU2_PAGE_FAULT_WR_PERM" }, + { .fc_id = 727, .cpu_id = 186, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU2_SECURITY_ERROR" }, + { .fc_id = 728, .cpu_id = 187, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 729, .cpu_id = 187, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU3_PAGE_FAULT_WR_PERM" }, + { .fc_id = 730, .cpu_id = 187, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU3_SECURITY_ERROR" }, + { .fc_id = 731, .cpu_id = 188, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 732, .cpu_id = 188, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU8_PAGE_FAULT_WR_PERM" }, + { .fc_id = 733, .cpu_id = 188, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU8_SECURITY_ERROR" }, + { .fc_id = 734, .cpu_id = 189, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 735, .cpu_id = 189, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU9_PAGE_FAULT_WR_PERM" }, + { .fc_id = 736, .cpu_id = 189, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU9_SECURITY_ERROR" }, + { .fc_id = 737, .cpu_id = 190, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 738, .cpu_id = 190, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU10_PAGE_FAULT_WR_PERM" }, + { .fc_id = 739, .cpu_id = 190, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU10_SECURITY_ERROR" }, + { .fc_id = 740, .cpu_id = 191, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 741, .cpu_id = 191, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU11_PAGE_FAULT_WR_PERM" }, + { .fc_id = 742, .cpu_id = 191, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU11_SECURITY_ERROR" }, + { .fc_id = 743, .cpu_id = 192, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 744, .cpu_id = 192, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU7_PAGE_FAULT_WR_PERM" }, + { .fc_id = 745, .cpu_id = 192, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU7_SECURITY_ERROR" }, + { .fc_id = 746, .cpu_id = 193, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 747, .cpu_id = 193, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU6_PAGE_FAULT_WR_PERM" }, + { .fc_id = 748, .cpu_id = 193, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU6_SECURITY_ERROR" }, + { .fc_id = 749, .cpu_id = 194, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 750, .cpu_id = 194, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU5_PAGE_FAULT_WR_PERM" }, + { .fc_id = 751, .cpu_id = 194, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU5_SECURITY_ERROR" }, + { .fc_id = 752, .cpu_id = 195, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 753, .cpu_id = 195, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU4_PAGE_FAULT_WR_PERM" }, + { .fc_id = 754, .cpu_id = 195, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU4_SECURITY_ERROR" }, + { .fc_id = 755, .cpu_id = 196, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 756, .cpu_id = 196, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU15_PAGE_FAULT_WR_PERM" }, + { .fc_id = 757, .cpu_id = 196, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU15_SECURITY_ERROR" }, + { .fc_id = 758, .cpu_id = 197, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 759, .cpu_id = 197, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU14_PAGE_FAULT_WR_PERM" }, + { .fc_id = 760, .cpu_id = 197, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU14_SECURITY_ERROR" }, + { .fc_id = 761, .cpu_id = 198, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 762, .cpu_id = 198, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU13_PAGE_FAULT_WR_PERM" }, + { .fc_id = 763, .cpu_id = 198, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU13_SECURITY_ERROR" }, + { .fc_id = 764, .cpu_id = 199, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 765, .cpu_id = 199, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HMMU12_PAGE_FAULT_WR_PERM" }, + { .fc_id = 766, .cpu_id = 199, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "HMMU12_SECURITY_ERROR" }, + { .fc_id = 767, .cpu_id = 200, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 768, .cpu_id = 201, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PMMU0_PAGE_FAULT_WR_PERM" }, + { .fc_id = 769, .cpu_id = 202, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "PMMU0_SECURITY_ERROR" }, + { .fc_id = 770, .cpu_id = 203, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA2_BM_SPMU" }, + { .fc_id = 771, .cpu_id = 204, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 772, .cpu_id = 205, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA3_BM_SPMU" }, + { .fc_id = 773, .cpu_id = 206, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 774, .cpu_id = 207, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA0_BM_SPMU" }, + { .fc_id = 775, .cpu_id = 208, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 776, .cpu_id = 209, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA1_BM_SPMU" }, + { .fc_id = 777, .cpu_id = 210, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 778, .cpu_id = 211, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA6_BM_SPMU" }, + { .fc_id = 779, .cpu_id = 212, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 780, .cpu_id = 213, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA7_BM_SPMU" }, + { .fc_id = 781, .cpu_id = 214, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 782, .cpu_id = 215, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA4_BM_SPMU" }, + { .fc_id = 783, .cpu_id = 216, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 784, .cpu_id = 217, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "EDMA5_BM_SPMU" }, + { .fc_id = 785, .cpu_id = 218, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 786, .cpu_id = 219, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "KDMA_BM_SPMU" }, + { .fc_id = 787, .cpu_id = 220, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 788, .cpu_id = 221, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PDMA0_BM_SPMU" }, + { .fc_id = 789, .cpu_id = 222, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "PDMA1_BM_SPMU" }, + { .fc_id = 790, .cpu_id = 223, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM0_MC0_SPI" }, + { .fc_id = 791, .cpu_id = 224, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM0_MC1_SPI" }, + { .fc_id = 792, .cpu_id = 225, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM1_MC0_SPI" }, + { .fc_id = 793, .cpu_id = 226, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM1_MC1_SPI" }, + { .fc_id = 794, .cpu_id = 227, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM2_MC0_SPI" }, + { .fc_id = 795, .cpu_id = 228, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM2_MC1_SPI" }, + { .fc_id = 796, .cpu_id = 229, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM3_MC0_SPI" }, + { .fc_id = 797, .cpu_id = 230, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM3_MC1_SPI" }, + { .fc_id = 798, .cpu_id = 231, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM4_MC0_SPI" }, + { .fc_id = 799, .cpu_id = 232, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM4_MC1_SPI" }, + { .fc_id = 800, .cpu_id = 233, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM5_MC0_SPI" }, + { .fc_id = 801, .cpu_id = 234, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "HBM5_MC1_SPI" }, + { .fc_id = 802, .cpu_id = 235, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 803, .cpu_id = 236, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 804, .cpu_id = 237, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 805, .cpu_id = 238, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 806, .cpu_id = 239, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 807, .cpu_id = 240, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 808, .cpu_id = 241, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 809, .cpu_id = 242, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 810, .cpu_id = 243, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 811, .cpu_id = 244, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 812, .cpu_id = 245, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 813, .cpu_id = 246, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 814, .cpu_id = 247, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 815, .cpu_id = 248, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 816, .cpu_id = 249, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 817, .cpu_id = 250, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 818, .cpu_id = 251, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 819, .cpu_id = 252, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 820, .cpu_id = 253, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 821, .cpu_id = 254, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 822, .cpu_id = 255, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 823, .cpu_id = 256, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 824, .cpu_id = 257, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 825, .cpu_id = 258, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 826, .cpu_id = 259, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 827, .cpu_id = 260, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 828, .cpu_id = 261, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 829, .cpu_id = 262, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 830, .cpu_id = 263, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 831, .cpu_id = 264, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 832, .cpu_id = 265, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 833, .cpu_id = 266, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 834, .cpu_id = 267, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 835, .cpu_id = 268, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 836, .cpu_id = 269, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 837, .cpu_id = 270, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 838, .cpu_id = 271, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 839, .cpu_id = 272, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 840, .cpu_id = 273, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 841, .cpu_id = 274, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 842, .cpu_id = 275, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 843, .cpu_id = 276, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 844, .cpu_id = 277, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 845, .cpu_id = 278, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 846, .cpu_id = 279, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 847, .cpu_id = 280, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 848, .cpu_id = 281, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 849, .cpu_id = 282, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 850, .cpu_id = 283, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 851, .cpu_id = 284, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 852, .cpu_id = 285, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 853, .cpu_id = 286, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 854, .cpu_id = 287, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "" }, + { .fc_id = 855, .cpu_id = 288, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "" }, + { .fc_id = 856, .cpu_id = 289, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 857, .cpu_id = 290, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 858, .cpu_id = 291, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 859, .cpu_id = 292, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 860, .cpu_id = 293, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 861, .cpu_id = 294, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 862, .cpu_id = 295, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 863, .cpu_id = 296, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 864, .cpu_id = 297, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 865, .cpu_id = 298, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 866, .cpu_id = 299, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 867, .cpu_id = 300, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 868, .cpu_id = 301, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 869, .cpu_id = 302, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 870, .cpu_id = 303, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 871, .cpu_id = 304, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "RPM_ERROR_OR_DRAIN" }, + { .fc_id = 872, .cpu_id = 305, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 873, .cpu_id = 306, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 874, .cpu_id = 307, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 875, .cpu_id = 308, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "RAZWI_OR_PID_MIN_MAX_INTERRUPT" }, + { .fc_id = 876, .cpu_id = 309, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 877, .cpu_id = 310, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 878, .cpu_id = 311, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 879, .cpu_id = 312, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "" }, + { .fc_id = 880, .cpu_id = 313, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 881, .cpu_id = 314, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 882, .cpu_id = 315, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 883, .cpu_id = 316, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 884, .cpu_id = 317, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 885, .cpu_id = 318, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 886, .cpu_id = 319, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 887, .cpu_id = 320, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 888, .cpu_id = 321, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 889, .cpu_id = 322, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 890, .cpu_id = 323, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 891, .cpu_id = 324, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 892, .cpu_id = 325, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 893, .cpu_id = 326, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 894, .cpu_id = 327, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 895, .cpu_id = 328, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 896, .cpu_id = 329, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC0_SPI" }, + { .fc_id = 897, .cpu_id = 329, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC0_BMON_SPMU" }, + { .fc_id = 898, .cpu_id = 330, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC1_SPI" }, + { .fc_id = 899, .cpu_id = 330, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC1_SPI" }, + { .fc_id = 900, .cpu_id = 331, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC2_SPI" }, + { .fc_id = 901, .cpu_id = 331, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC2_BMON_SPMU" }, + { .fc_id = 902, .cpu_id = 332, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC3_SPI" }, + { .fc_id = 903, .cpu_id = 332, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC3_BMON_SPMU" }, + { .fc_id = 904, .cpu_id = 333, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC4_SPI" }, + { .fc_id = 905, .cpu_id = 333, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC4_BMON_SPMU" }, + { .fc_id = 906, .cpu_id = 334, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC5_SPI" }, + { .fc_id = 907, .cpu_id = 334, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC5_BMON_SPMU" }, + { .fc_id = 908, .cpu_id = 335, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC6_SPI" }, + { .fc_id = 909, .cpu_id = 335, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC6_BMON_SPMU" }, + { .fc_id = 910, .cpu_id = 336, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC7_SPI" }, + { .fc_id = 911, .cpu_id = 336, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC7_BMON_SPMU" }, + { .fc_id = 912, .cpu_id = 337, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC8_SPI" }, + { .fc_id = 913, .cpu_id = 337, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC8_BMON_SPMU" }, + { .fc_id = 914, .cpu_id = 338, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "DEC9_SPI" }, + { .fc_id = 915, .cpu_id = 338, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "DEC9_BMON_SPMU" }, + { .fc_id = 916, .cpu_id = 339, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 917, .cpu_id = 340, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 918, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 919, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 920, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 921, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 922, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 923, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 924, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 925, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 926, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 927, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 928, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 929, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 930, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 931, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 932, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 933, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 934, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 935, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 936, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 937, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 938, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 939, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 940, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 941, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 942, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 943, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 944, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 945, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 946, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 947, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 948, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 949, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 950, .cpu_id = 342, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 951, .cpu_id = 343, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC0_BMON_SPMU" }, + { .fc_id = 952, .cpu_id = 343, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC0_SW_ERROR" }, + { .fc_id = 953, .cpu_id = 343, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 954, .cpu_id = 343, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 955, .cpu_id = 344, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC1_BMON_SPMU" }, + { .fc_id = 956, .cpu_id = 344, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC1_SW_ERROR" }, + { .fc_id = 957, .cpu_id = 344, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 958, .cpu_id = 344, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 959, .cpu_id = 345, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC2_BMON_SPMU" }, + { .fc_id = 960, .cpu_id = 345, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC2_SW_ERROR" }, + { .fc_id = 961, .cpu_id = 345, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 962, .cpu_id = 345, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 963, .cpu_id = 346, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC3_BMON_SPMU" }, + { .fc_id = 964, .cpu_id = 346, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC3_SW_ERROR" }, + { .fc_id = 965, .cpu_id = 346, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 966, .cpu_id = 346, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 967, .cpu_id = 347, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC4_BMON_SPMU" }, + { .fc_id = 968, .cpu_id = 347, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC4_SW_ERROR" }, + { .fc_id = 969, .cpu_id = 347, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 970, .cpu_id = 347, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 971, .cpu_id = 348, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC5_BMON_SPMU" }, + { .fc_id = 972, .cpu_id = 348, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC5_SW_ERROR" }, + { .fc_id = 973, .cpu_id = 348, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 974, .cpu_id = 348, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 975, .cpu_id = 349, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC6_BMON_SPMU" }, + { .fc_id = 976, .cpu_id = 349, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC6_SW_ERROR" }, + { .fc_id = 977, .cpu_id = 349, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 978, .cpu_id = 349, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 979, .cpu_id = 350, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC7_BMON_SPMU" }, + { .fc_id = 980, .cpu_id = 350, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC7_SW_ERROR" }, + { .fc_id = 981, .cpu_id = 350, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 982, .cpu_id = 350, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 983, .cpu_id = 351, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC8_BMON_SPMU" }, + { .fc_id = 984, .cpu_id = 351, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC8_SW_ERROR" }, + { .fc_id = 985, .cpu_id = 351, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 986, .cpu_id = 351, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 987, .cpu_id = 352, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC9_BMON_SPMU" }, + { .fc_id = 988, .cpu_id = 352, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC9_SW_ERROR" }, + { .fc_id = 989, .cpu_id = 352, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 990, .cpu_id = 352, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 991, .cpu_id = 353, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC10_BMON_SPMU" }, + { .fc_id = 992, .cpu_id = 353, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC10_SW_ERROR" }, + { .fc_id = 993, .cpu_id = 353, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 994, .cpu_id = 353, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 995, .cpu_id = 354, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC11_BMON_SPMU" }, + { .fc_id = 996, .cpu_id = 354, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "NIC11_SW_ERROR" }, + { .fc_id = 997, .cpu_id = 354, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 998, .cpu_id = 354, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 999, .cpu_id = 355, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1000, .cpu_id = 356, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1001, .cpu_id = 357, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1002, .cpu_id = 358, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1003, .cpu_id = 359, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1004, .cpu_id = 360, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1005, .cpu_id = 361, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1006, .cpu_id = 362, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1007, .cpu_id = 363, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1008, .cpu_id = 368, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1009, .cpu_id = 369, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1010, .cpu_id = 366, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1011, .cpu_id = 367, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1012, .cpu_id = 364, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1013, .cpu_id = 365, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1014, .cpu_id = 374, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1015, .cpu_id = 375, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1016, .cpu_id = 372, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1017, .cpu_id = 373, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1018, .cpu_id = 370, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1019, .cpu_id = 371, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1020, .cpu_id = 376, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1021, .cpu_id = 377, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1022, .cpu_id = 378, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1023, .cpu_id = 379, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1024, .cpu_id = 380, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1025, .cpu_id = 381, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1026, .cpu_id = 382, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1027, .cpu_id = 383, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1028, .cpu_id = 384, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1029, .cpu_id = 385, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1030, .cpu_id = 386, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1031, .cpu_id = 387, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1032, .cpu_id = 388, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1033, .cpu_id = 389, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1034, .cpu_id = 390, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1035, .cpu_id = 391, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1036, .cpu_id = 392, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1037, .cpu_id = 393, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1038, .cpu_id = 394, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1039, .cpu_id = 395, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1040, .cpu_id = 396, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1041, .cpu_id = 397, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1042, .cpu_id = 398, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1043, .cpu_id = 399, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1044, .cpu_id = 400, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1045, .cpu_id = 401, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1046, .cpu_id = 402, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1047, .cpu_id = 403, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1048, .cpu_id = 404, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1049, .cpu_id = 405, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1050, .cpu_id = 406, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1051, .cpu_id = 407, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1052, .cpu_id = 408, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1053, .cpu_id = 409, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1054, .cpu_id = 410, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1055, .cpu_id = 411, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1056, .cpu_id = 412, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1057, .cpu_id = 413, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1058, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1059, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1060, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1061, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1062, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1063, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1064, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1065, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1066, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1067, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1068, .cpu_id = 415, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1069, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1070, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1071, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1072, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1073, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1074, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1075, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1076, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1077, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1078, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1079, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1080, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1081, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1082, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1083, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1084, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1085, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1086, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1087, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1088, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1089, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1090, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1091, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1092, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1093, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1094, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1095, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1096, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1097, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1098, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1099, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1100, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1101, .cpu_id = 418, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1102, .cpu_id = 419, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1103, .cpu_id = 420, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1104, .cpu_id = 421, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1105, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1106, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1107, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1108, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1109, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1110, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1111, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1112, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1113, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1114, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1115, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1116, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1117, .cpu_id = 423, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1118, .cpu_id = 424, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "ROTATOR0_SERR" }, + { .fc_id = 1119, .cpu_id = 425, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "ROTATOR1_SERR" }, + { .fc_id = 1120, .cpu_id = 426, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "ROTATOR0_DERR" }, + { .fc_id = 1121, .cpu_id = 427, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD, + .name = "ROTATOR1_DERR" }, + { .fc_id = 1122, .cpu_id = 428, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "ROTATOR0_AXI_ERROR_RESPONSE" }, + { .fc_id = 1123, .cpu_id = 429, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "ROTATOR1_AXI_ERROR_RESPONSE" }, + { .fc_id = 1124, .cpu_id = 430, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1125, .cpu_id = 431, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1126, .cpu_id = 432, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "ROTATOR0_BMON_SPMU" }, + { .fc_id = 1127, .cpu_id = 433, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1128, .cpu_id = 434, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "ROTATOR1_BMON_SPMU" }, + { .fc_id = 1129, .cpu_id = 435, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1130, .cpu_id = 436, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM0_BMON_SPMU" }, + { .fc_id = 1131, .cpu_id = 437, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM1_BMON_SPMU" }, + { .fc_id = 1132, .cpu_id = 438, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM2_BMON_SPMU" }, + { .fc_id = 1133, .cpu_id = 439, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "SM3_BMON_SPMU" }, + { .fc_id = 1134, .cpu_id = 440, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1135, .cpu_id = 441, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1136, .cpu_id = 442, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1137, .cpu_id = 443, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1138, .cpu_id = 444, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1139, .cpu_id = 445, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1140, .cpu_id = 446, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1141, .cpu_id = 447, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1142, .cpu_id = 448, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1143, .cpu_id = 449, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1144, .cpu_id = 450, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1145, .cpu_id = 451, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1146, .cpu_id = 452, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1147, .cpu_id = 453, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1148, .cpu_id = 454, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1149, .cpu_id = 455, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1150, .cpu_id = 456, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1151, .cpu_id = 457, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1152, .cpu_id = 458, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1153, .cpu_id = 459, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1154, .cpu_id = 460, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1155, .cpu_id = 461, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1156, .cpu_id = 462, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1157, .cpu_id = 463, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1158, .cpu_id = 464, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1159, .cpu_id = 465, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1160, .cpu_id = 466, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1161, .cpu_id = 467, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1162, .cpu_id = 468, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1163, .cpu_id = 469, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1164, .cpu_id = 470, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1165, .cpu_id = 471, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1166, .cpu_id = 472, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1167, .cpu_id = 473, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1168, .cpu_id = 474, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1169, .cpu_id = 475, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1170, .cpu_id = 476, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1171, .cpu_id = 477, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1172, .cpu_id = 478, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1173, .cpu_id = 479, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1174, .cpu_id = 480, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1175, .cpu_id = 481, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1176, .cpu_id = 482, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1177, .cpu_id = 483, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1178, .cpu_id = 484, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1179, .cpu_id = 485, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1180, .cpu_id = 486, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1181, .cpu_id = 487, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1182, .cpu_id = 488, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1183, .cpu_id = 489, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1184, .cpu_id = 490, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1185, .cpu_id = 491, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1186, .cpu_id = 492, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1187, .cpu_id = 493, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1188, .cpu_id = 494, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1189, .cpu_id = 495, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1190, .cpu_id = 496, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1191, .cpu_id = 497, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1192, .cpu_id = 498, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1193, .cpu_id = 499, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1194, .cpu_id = 500, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1195, .cpu_id = 501, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1196, .cpu_id = 502, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1197, .cpu_id = 503, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1198, .cpu_id = 504, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1199, .cpu_id = 505, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1200, .cpu_id = 506, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1201, .cpu_id = 507, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1202, .cpu_id = 508, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1203, .cpu_id = 509, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1204, .cpu_id = 510, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1205, .cpu_id = 511, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1206, .cpu_id = 512, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC0_QM" }, + { .fc_id = 1207, .cpu_id = 513, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC1_QM" }, + { .fc_id = 1208, .cpu_id = 514, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC2_QM" }, + { .fc_id = 1209, .cpu_id = 515, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC3_QM" }, + { .fc_id = 1210, .cpu_id = 516, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC4_QM" }, + { .fc_id = 1211, .cpu_id = 517, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC5_QM" }, + { .fc_id = 1212, .cpu_id = 518, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC6_QM" }, + { .fc_id = 1213, .cpu_id = 519, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC7_QM" }, + { .fc_id = 1214, .cpu_id = 520, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC8_QM" }, + { .fc_id = 1215, .cpu_id = 521, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC9_QM" }, + { .fc_id = 1216, .cpu_id = 522, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC10_QM" }, + { .fc_id = 1217, .cpu_id = 523, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC11_QM" }, + { .fc_id = 1218, .cpu_id = 524, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC12_QM" }, + { .fc_id = 1219, .cpu_id = 525, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC13_QM" }, + { .fc_id = 1220, .cpu_id = 526, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC14_QM" }, + { .fc_id = 1221, .cpu_id = 527, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC15_QM" }, + { .fc_id = 1222, .cpu_id = 528, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC16_QM" }, + { .fc_id = 1223, .cpu_id = 529, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC17_QM" }, + { .fc_id = 1224, .cpu_id = 530, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC18_QM" }, + { .fc_id = 1225, .cpu_id = 531, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC19_QM" }, + { .fc_id = 1226, .cpu_id = 532, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC20_QM" }, + { .fc_id = 1227, .cpu_id = 533, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC21_QM" }, + { .fc_id = 1228, .cpu_id = 534, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC22_QM" }, + { .fc_id = 1229, .cpu_id = 535, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC23_QM" }, + { .fc_id = 1230, .cpu_id = 536, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "TPC24_QM" }, + { .fc_id = 1231, .cpu_id = 537, .valid = 0, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "" }, + { .fc_id = 1232, .cpu_id = 538, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME0_QM" }, + { .fc_id = 1233, .cpu_id = 539, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME1_QM" }, + { .fc_id = 1234, .cpu_id = 540, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME2_QM" }, + { .fc_id = 1235, .cpu_id = 541, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "MME3_QM" }, + { .fc_id = 1236, .cpu_id = 542, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA2_QM" }, + { .fc_id = 1237, .cpu_id = 543, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA3_QM" }, + { .fc_id = 1238, .cpu_id = 544, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA0_QM" }, + { .fc_id = 1239, .cpu_id = 545, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA1_QM" }, + { .fc_id = 1240, .cpu_id = 546, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA6_QM" }, + { .fc_id = 1241, .cpu_id = 547, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA7_QM" }, + { .fc_id = 1242, .cpu_id = 548, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA4_QM" }, + { .fc_id = 1243, .cpu_id = 549, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA5_QM" }, + { .fc_id = 1244, .cpu_id = 550, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "PDMA0_QM" }, + { .fc_id = 1245, .cpu_id = 551, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "PDMA1_QM" }, + { .fc_id = 1246, .cpu_id = 552, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "PI_UPDATE" }, + { .fc_id = 1247, .cpu_id = 553, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "HALT_MACHINE" }, + { .fc_id = 1248, .cpu_id = 554, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "INTS_REGISTER" }, + { .fc_id = 1249, .cpu_id = 555, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "ROT0_QM" }, + { .fc_id = 1250, .cpu_id = 556, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "ROT1_QM" }, + { .fc_id = 1251, .cpu_id = 557, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "SOFT_RESET" }, + { .fc_id = 1252, .cpu_id = 558, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "CPLD_SHUTDOWN_CAUSE" }, + { .fc_id = 1253, .cpu_id = 559, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "FIX_POWER_ENV_S" }, + { .fc_id = 1254, .cpu_id = 560, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "FIX_POWER_ENV_E" }, + { .fc_id = 1255, .cpu_id = 561, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "FIX_THERMAL_ENV_S" }, + { .fc_id = 1256, .cpu_id = 562, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "FIX_THERMAL_ENV_E" }, + { .fc_id = 1257, .cpu_id = 563, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "CPLD_SHUTDOWN_EVENT" }, + { .fc_id = 1258, .cpu_id = 564, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "PKT_QUEUE_OUT_SYNC" }, + { .fc_id = 1259, .cpu_id = 565, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA2_CORE" }, + { .fc_id = 1260, .cpu_id = 566, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA3_CORE" }, + { .fc_id = 1261, .cpu_id = 567, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA0_CORE" }, + { .fc_id = 1262, .cpu_id = 568, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA1_CORE" }, + { .fc_id = 1263, .cpu_id = 569, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA6_CORE" }, + { .fc_id = 1264, .cpu_id = 570, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA7_CORE" }, + { .fc_id = 1265, .cpu_id = 571, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA4_CORE" }, + { .fc_id = 1266, .cpu_id = 572, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "EDMA5_CORE" }, + { .fc_id = 1267, .cpu_id = 573, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "PDMA0_CORE" }, + { .fc_id = 1268, .cpu_id = 574, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "PDMA1_CORE" }, + { .fc_id = 1269, .cpu_id = 575, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "KDMA0_CORE" }, + { .fc_id = 1270, .cpu_id = 576, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC0_QM0" }, + { .fc_id = 1271, .cpu_id = 577, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC0_QM1" }, + { .fc_id = 1272, .cpu_id = 578, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC1_QM0" }, + { .fc_id = 1273, .cpu_id = 579, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC1_QM1" }, + { .fc_id = 1274, .cpu_id = 580, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC2_QM0" }, + { .fc_id = 1275, .cpu_id = 581, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC2_QM1" }, + { .fc_id = 1276, .cpu_id = 582, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC3_QM0" }, + { .fc_id = 1277, .cpu_id = 583, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC3_QM1" }, + { .fc_id = 1278, .cpu_id = 584, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC4_QM0" }, + { .fc_id = 1279, .cpu_id = 585, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC4_QM1" }, + { .fc_id = 1280, .cpu_id = 586, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC5_QM0" }, + { .fc_id = 1281, .cpu_id = 587, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC5_QM1" }, + { .fc_id = 1282, .cpu_id = 588, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC6_QM0" }, + { .fc_id = 1283, .cpu_id = 589, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC6_QM1" }, + { .fc_id = 1284, .cpu_id = 590, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC7_QM0" }, + { .fc_id = 1285, .cpu_id = 591, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC7_QM1" }, + { .fc_id = 1286, .cpu_id = 592, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC8_QM0" }, + { .fc_id = 1287, .cpu_id = 593, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC8_QM1" }, + { .fc_id = 1288, .cpu_id = 594, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC9_QM0" }, + { .fc_id = 1289, .cpu_id = 595, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC9_QM1" }, + { .fc_id = 1290, .cpu_id = 596, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC10_QM0" }, + { .fc_id = 1291, .cpu_id = 597, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC10_QM1" }, + { .fc_id = 1292, .cpu_id = 598, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC11_QM0" }, + { .fc_id = 1293, .cpu_id = 599, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "NIC11_QM1" }, + { .fc_id = 1294, .cpu_id = 600, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "CPU_PKT_SANITY_FAILED" }, + { .fc_id = 1295, .cpu_id = 601, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC0_ENG0" }, + { .fc_id = 1296, .cpu_id = 602, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC0_ENG1" }, + { .fc_id = 1297, .cpu_id = 603, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC1_ENG0" }, + { .fc_id = 1298, .cpu_id = 604, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC1_ENG1" }, + { .fc_id = 1299, .cpu_id = 605, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC2_ENG0" }, + { .fc_id = 1300, .cpu_id = 606, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC2_ENG1" }, + { .fc_id = 1301, .cpu_id = 607, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC3_ENG0" }, + { .fc_id = 1302, .cpu_id = 608, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC3_ENG1" }, + { .fc_id = 1303, .cpu_id = 609, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC4_ENG0" }, + { .fc_id = 1304, .cpu_id = 610, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC4_ENG1" }, + { .fc_id = 1305, .cpu_id = 611, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC5_ENG0" }, + { .fc_id = 1306, .cpu_id = 612, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC5_ENG1" }, + { .fc_id = 1307, .cpu_id = 613, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC6_ENG0" }, + { .fc_id = 1308, .cpu_id = 614, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC6_ENG1" }, + { .fc_id = 1309, .cpu_id = 615, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC7_ENG0" }, + { .fc_id = 1310, .cpu_id = 616, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC7_ENG1" }, + { .fc_id = 1311, .cpu_id = 617, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC8_ENG0" }, + { .fc_id = 1312, .cpu_id = 618, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC8_ENG1" }, + { .fc_id = 1313, .cpu_id = 619, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC9_ENG0" }, + { .fc_id = 1314, .cpu_id = 620, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC9_ENG1" }, + { .fc_id = 1315, .cpu_id = 621, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC10_ENG0" }, + { .fc_id = 1316, .cpu_id = 622, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC10_ENG1" }, + { .fc_id = 1317, .cpu_id = 623, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC11_ENG0" }, + { .fc_id = 1318, .cpu_id = 624, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE, + .name = "STATUS_NIC11_ENG1" }, + { .fc_id = 1319, .cpu_id = 625, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE, + .name = "ARC_DCCM_FULL" }, + { .fc_id = 1320, .cpu_id = 626, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "FP32_NOT_SUPPORTED" }, + { .fc_id = 1321, .cpu_id = 627, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD, + .name = "DEV_RESET_REQ" }, }; #endif /* __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ */ diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h index 82f3ca2a3966..8522f24deac0 100644 --- a/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h +++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h @@ -63,7 +63,10 @@ struct gaudi2_cold_rst_data { u32 fake_sig_validation_en : 1; u32 bist_skip_enable : 1; u32 bist_need_iatu_config : 1; - u32 reserved : 24; + u32 fake_bis_compliant : 1; + u32 wd_rst_cause_arm : 1; + u32 wd_rst_cause_arcpid : 1; + u32 reserved : 21; }; __le32 data; }; diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h index 0d1f853092ab..ecffe24e2b1b 100644 --- a/include/drm/drm_file.h +++ b/include/drm/drm_file.h @@ -408,7 +408,8 @@ static inline bool drm_is_render_client(const struct drm_file *file_priv) * Returns true if this is an open file of the compute acceleration node, i.e. * &drm_file.minor of @file_priv is a accel minor. * - * See also the :ref:`section on accel nodes <drm_accel_node>`. + * See also :doc:`Introduction to compute accelerators subsystem + * </accel/introduction>`. */ static inline bool drm_is_accel_client(const struct drm_file *file_priv) { diff --git a/include/uapi/drm/habanalabs_accel.h b/include/uapi/drm/habanalabs_accel.h index 331567ec9e79..c139aab17c8a 100644 --- a/include/uapi/drm/habanalabs_accel.h +++ b/include/uapi/drm/habanalabs_accel.h @@ -723,6 +723,10 @@ enum hl_server_type { * HL_NOTIFIER_EVENT_GENERAL_HW_ERR - Indicates device HW error * HL_NOTIFIER_EVENT_RAZWI - Indicates razwi happened * HL_NOTIFIER_EVENT_PAGE_FAULT - Indicates page fault happened + * HL_NOTIFIER_EVENT_CRITICAL_HW_ERR - Indicates a HW error that requires SW abort and + * HW reset + * HL_NOTIFIER_EVENT_CRITICAL_FW_ERR - Indicates a FW error that requires SW abort and + * HW reset */ #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0) #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1) @@ -733,6 +737,8 @@ enum hl_server_type { #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6) #define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7) #define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8) +#define HL_NOTIFIER_EVENT_CRITICL_HW_ERR (1ULL << 9) +#define HL_NOTIFIER_EVENT_CRITICL_FW_ERR (1ULL << 10) /* Opcode for management ioctl * @@ -790,6 +796,8 @@ enum hl_server_type { * HL_INFO_PAGE_FAULT_EVENT - Retrieve parameters of captured page fault. * HL_INFO_USER_MAPPINGS - Retrieve user mappings, captured after page fault event. * HL_INFO_FW_GENERIC_REQ - Send generic request to FW. + * HL_INFO_HW_ERR_EVENT - Retrieve information on the reported HW error. + * HL_INFO_FW_ERR_EVENT - Retrieve information on the reported FW error. */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -824,6 +832,8 @@ enum hl_server_type { #define HL_INFO_PAGE_FAULT_EVENT 33 #define HL_INFO_USER_MAPPINGS 34 #define HL_INFO_FW_GENERIC_REQ 35 +#define HL_INFO_HW_ERR_EVENT 36 +#define HL_INFO_FW_ERR_EVENT 37 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -875,6 +885,12 @@ enum hl_server_type { * application to use. Relevant for Gaudi2 and later. * @device_mem_alloc_default_page_size: default page size used in device memory allocation. * @revision_id: PCI revision ID of the ASIC. + * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host. + * @rotator_enabled_mask: Bit-mask that represents which rotators are enabled. + * Relevant for Gaudi3 and later. + * @engine_core_interrupt_reg_addr: interrupt register address for engine core to use + * in order to raise events toward FW. + * @reserved_dram_size: DRAM size reserved for driver and firmware. */ struct hl_info_hw_ip_info { __u64 sram_base_address; @@ -902,15 +918,20 @@ struct hl_info_hw_ip_info { __u64 dram_page_size; __u32 edma_enabled_mask; __u16 number_of_user_interrupts; - __u16 pad2; - __u64 reserved4; + __u8 reserved1; + __u8 reserved2; + __u64 reserved3; __u64 device_mem_alloc_default_page_size; + __u64 reserved4; __u64 reserved5; - __u64 reserved6; - __u32 reserved7; - __u8 reserved8; + __u32 reserved6; + __u8 reserved7; __u8 revision_id; - __u8 pad[2]; + __u16 tpc_interrupt_id; + __u32 rotator_enabled_mask; + __u32 reserved9; + __u64 engine_core_interrupt_reg_addr; + __u64 reserved_dram_size; }; struct hl_info_dram_usage { @@ -1162,6 +1183,39 @@ struct hl_info_undefined_opcode_event { }; /** + * struct hl_info_hw_err_event - info about HW error + * @timestamp: timestamp of error occurrence + * @event_id: The async event ID (specific to each device type). + * @pad: size padding for u64 granularity. + */ +struct hl_info_hw_err_event { + __s64 timestamp; + __u16 event_id; + __u16 pad[3]; +}; + +/* FW error definition for event_type in struct hl_info_fw_err_event */ +enum hl_info_fw_err_type { + HL_INFO_FW_HEARTBEAT_ERR, + HL_INFO_FW_REPORTED_ERR, +}; + +/** + * struct hl_info_fw_err_event - info about FW error + * @timestamp: time-stamp of error occurrence + * @err_type: The type of event as defined in hl_info_fw_err_type. + * @event_id: The async event ID (specific to each device type, applicable only when event type is + * HL_INFO_FW_REPORTED_ERR). + * @pad: size padding for u64 granularity. + */ +struct hl_info_fw_err_event { + __s64 timestamp; + __u16 err_type; + __u16 event_id; + __u32 pad; +}; + +/** * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size * (e.g. 0x2100000 means that 1MB and 32MB pages are supported). @@ -1486,17 +1540,31 @@ struct hl_cs_chunk { */ #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000 +/* + * The engines CS is merged into the existing CS ioctls. + * Use it to control engines modes. + */ +#define HL_CS_FLAGS_ENGINES_COMMAND 0x10000 + #define HL_CS_STATUS_SUCCESS 0 #define HL_MAX_JOBS_PER_CS 512 -/* HL_ENGINE_CORE_ values +/* + * enum hl_engine_command - engine command * - * HL_ENGINE_CORE_HALT: engine core halt - * HL_ENGINE_CORE_RUN: engine core run + * @HL_ENGINE_CORE_HALT: engine core halt + * @HL_ENGINE_CORE_RUN: engine core run + * @HL_ENGINE_STALL: user engine/s stall + * @HL_ENGINE_RESUME: user engine/s resume */ -#define HL_ENGINE_CORE_HALT (1 << 0) -#define HL_ENGINE_CORE_RUN (1 << 1) +enum hl_engine_command { + HL_ENGINE_CORE_HALT = 1, + HL_ENGINE_CORE_RUN = 2, + HL_ENGINE_STALL = 3, + HL_ENGINE_RESUME = 4, + HL_ENGINE_COMMAND_MAX +}; struct hl_cs_in { @@ -1520,6 +1588,18 @@ struct hl_cs_in { /* the core command to be sent towards engine cores */ __u32 core_command; }; + + /* Valid only when HL_CS_FLAGS_ENGINES_COMMAND is set */ + struct { + /* this holds address of array of uint32 for engines */ + __u64 engines; + + /* number of engines in engines array */ + __u32 num_engines; + + /* the engine command to be sent towards engines */ + __u32 engine_command; + }; }; union { |