diff options
25 files changed, 1286 insertions, 84 deletions
diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index fcafef8d5a33..dedfad526666 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -9,6 +9,7 @@ title: Microchip Sparx5 Ethernet switch controller maintainers: - Steen Hegelund <steen.hegelund@microchip.com> - Lars Povlsen <lars.povlsen@microchip.com> + - Daniel Machon <daniel.machon@microchip.com> description: | The SparX-5 Enterprise Ethernet switch family provides a rich set of @@ -34,7 +35,24 @@ properties: pattern: "^switch@[0-9a-f]+$" compatible: - const: microchip,sparx5-switch + oneOf: + - enum: + - microchip,lan9691-switch + - microchip,sparx5-switch + - items: + - enum: + - microchip,lan969c-switch + - microchip,lan969b-switch + - microchip,lan969a-switch + - microchip,lan9699-switch + - microchip,lan9698-switch + - microchip,lan9697-switch + - microchip,lan9696-switch + - microchip,lan9695-switch + - microchip,lan9694-switch + - microchip,lan9693-switch + - microchip,lan9692-switch + - const: microchip,lan9691-switch reg: items: diff --git a/MAINTAINERS b/MAINTAINERS index c08624a073bc..c4027397286b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15091,6 +15091,13 @@ S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml F: drivers/irqchip/irq-lan966x-oic.c +MICROCHIP LAN969X ETHERNET DRIVER +M: Daniel Machon <daniel.machon@microchip.com> +M: UNGLinuxDriver@microchip.com +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/microchip/lan969x/* + MICROCHIP LCDFB DRIVER M: Nicolas Ferre <nicolas.ferre@microchip.com> L: linux-fbdev@vger.kernel.org diff --git a/drivers/net/ethernet/microchip/Kconfig b/drivers/net/ethernet/microchip/Kconfig index ee046468652c..73832fb2bc32 100644 --- a/drivers/net/ethernet/microchip/Kconfig +++ b/drivers/net/ethernet/microchip/Kconfig @@ -59,6 +59,7 @@ config LAN743X source "drivers/net/ethernet/microchip/lan865x/Kconfig" source "drivers/net/ethernet/microchip/lan966x/Kconfig" +source "drivers/net/ethernet/microchip/lan969x/Kconfig" source "drivers/net/ethernet/microchip/sparx5/Kconfig" source "drivers/net/ethernet/microchip/vcap/Kconfig" source "drivers/net/ethernet/microchip/fdma/Kconfig" diff --git a/drivers/net/ethernet/microchip/Makefile b/drivers/net/ethernet/microchip/Makefile index 3c65baed9fd8..7770df82200f 100644 --- a/drivers/net/ethernet/microchip/Makefile +++ b/drivers/net/ethernet/microchip/Makefile @@ -11,6 +11,7 @@ lan743x-objs := lan743x_main.o lan743x_ethtool.o lan743x_ptp.o obj-$(CONFIG_LAN865X) += lan865x/ obj-$(CONFIG_LAN966X_SWITCH) += lan966x/ +obj-$(CONFIG_LAN969X_SWITCH) += lan969x/ obj-$(CONFIG_SPARX5_SWITCH) += sparx5/ obj-$(CONFIG_VCAP) += vcap/ obj-$(CONFIG_FDMA) += fdma/ diff --git a/drivers/net/ethernet/microchip/lan969x/Kconfig b/drivers/net/ethernet/microchip/lan969x/Kconfig new file mode 100644 index 000000000000..728180d3fa33 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/Kconfig @@ -0,0 +1,5 @@ +config LAN969X_SWITCH + tristate "Lan969x switch driver" + depends on SPARX5_SWITCH + help + This driver supports the lan969x family of network switch devices. diff --git a/drivers/net/ethernet/microchip/lan969x/Makefile b/drivers/net/ethernet/microchip/lan969x/Makefile new file mode 100644 index 000000000000..82d318a7219c --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for the Microchip lan969x network device drivers. +# + +obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o + +lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o + +# Provide include files +ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma +ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net/ethernet/microchip/lan969x/lan969x.c new file mode 100644 index 000000000000..79e5bcefbd73 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + */ + +#include "lan969x.h" + +#define LAN969X_SDLB_GRP_CNT 5 +#define LAN969X_HSCH_LEAK_GRP_CNT 4 + +static const struct sparx5_main_io_resource lan969x_main_iomap[] = { + { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ + { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ + { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ + { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ + { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ + { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ + { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ + { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ + { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ + { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ + { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ + { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ + { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ + { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ + { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ + { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ + { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ + { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ + { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ + { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ + { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ + { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ + { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ + { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ + { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ + { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ + { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ + { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ + { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ + { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ + { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ + { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ + { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ + { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ + { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ + { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ + { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ + { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ + { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ + { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ + { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ + { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ + { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ + { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ + { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ + { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ + { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ + { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ + { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ + { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ + { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ + { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ + { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ + { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ + { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ + { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ + { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ + { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ + { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ + { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ + { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ + { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ + { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ + { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ + { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ + { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ + { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ + { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ + { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ + { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ + { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ + { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ + { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ + { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ + { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ + { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ + { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ + { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ + { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ + { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ + { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ + { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ + { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ +}; + +static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { + { 1000000000, 8192 / 2, 64 }, /* 1 G */ + { 500000000, 8192 / 2, 64 }, /* 500 M */ + { 100000000, 8192 / 4, 64 }, /* 100 M */ + { 50000000, 8192 / 4, 64 }, /* 50 M */ + { 5000000, 8192 / 8, 64 }, /* 10 M */ +}; + +static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { + 655355, 1048568, 6553550, 10485680 +}; + +static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) +{ + return &lan969x_sdlb_groups[idx]; +} + +static u32 lan969x_get_hsch_max_group_rate(int grp) +{ + return lan969x_hsch_max_group_rate[grp]; +} + +static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) +{ + if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) + return port; + + /* 10G */ + switch (port) { + case 0: + return 12; + case 4: + return 13; + case 8: + return 14; + case 12: + return 0; + default: + return port; + } +} + +static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) +{ + if (lan969x_port_is_5g(port)) { + switch (port) { + case 9: + return 0; + case 13: + return 1; + case 17: + return 2; + case 21: + return 3; + } + } + + if (lan969x_port_is_10g(port)) { + switch (port) { + case 0: + return 0; + case 4: + return 1; + case 8: + return 2; + case 12: + return 3; + case 16: + return 4; + case 20: + return 5; + case 24: + return 6; + case 25: + return 7; + case 26: + return 8; + case 27: + return 9; + } + } + + /* 2g5 port */ + return port; +} + +static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, + struct sparx5_port_config *conf) +{ + u32 portno = port->portno; + u32 inst; + + if (port->conf.portmode == conf->portmode) + return 0; /* Nothing to do */ + + switch (conf->portmode) { + case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ + inst = (portno - portno % 4) / 4; + spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); + break; + default: + break; + } + return 0; +} + +static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) +{ + int budget = SPARX5_MAX_PTP_ID; + struct sparx5 *sparx5 = args; + + while (budget--) { + struct sk_buff *skb, *skb_tmp, *skb_match = NULL; + struct skb_shared_hwtstamps shhwtstamps; + struct sparx5_port *port; + struct timespec64 ts; + unsigned long flags; + u32 val, id, txport; + u32 delay; + + val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); + + /* Check if a timestamp can be retrieved */ + if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) + break; + + WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); + + if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) + continue; + + /* Retrieve the ts Tx port */ + txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); + + /* Retrieve its associated skb */ + port = sparx5->ports[txport]; + + /* Retrieve the delay */ + delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); + delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); + + /* Get next timestamp from fifo, which needs to be the + * rx timestamp which represents the id of the frame + */ + spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), + PTP_TWOSTEP_CTRL_PTP_NXT, + sparx5, PTP_TWOSTEP_CTRL); + + val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); + + /* Check if a timestamp can be retrieved */ + if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) + break; + + /* Read RX timestamping to get the ID */ + id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); + id <<= 8; + id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); + + spin_lock_irqsave(&port->tx_skbs.lock, flags); + skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { + if (SPARX5_SKB_CB(skb)->ts_id != id) + continue; + + __skb_unlink(skb, &port->tx_skbs); + skb_match = skb; + break; + } + spin_unlock_irqrestore(&port->tx_skbs.lock, flags); + + /* Next ts */ + spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), + PTP_TWOSTEP_CTRL_PTP_NXT, + sparx5, PTP_TWOSTEP_CTRL); + + if (WARN_ON(!skb_match)) + continue; + + spin_lock(&sparx5->ptp_ts_id_lock); + sparx5->ptp_skbs--; + spin_unlock(&sparx5->ptp_ts_id_lock); + + /* Get the h/w timestamp */ + sparx5_get_hwtimestamp(sparx5, &ts, delay); + + /* Set the timestamp in the skb */ + shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); + skb_tstamp_tx(skb_match, &shhwtstamps); + + dev_kfree_skb_any(skb_match); + } + + return IRQ_HANDLED; +} + +static const struct sparx5_regs lan969x_regs = { + .tsize = lan969x_tsize, + .gaddr = lan969x_gaddr, + .gcnt = lan969x_gcnt, + .gsize = lan969x_gsize, + .raddr = lan969x_raddr, + .rcnt = lan969x_rcnt, + .fpos = lan969x_fpos, + .fsize = lan969x_fsize, +}; + +static const struct sparx5_consts lan969x_consts = { + .n_ports = 30, + .n_ports_all = 35, + .n_hsch_l1_elems = 32, + .n_hsch_queues = 4, + .n_lb_groups = 5, + .n_pgids = 1054, /* (1024 + n_ports) */ + .n_sio_clks = 1, + .n_own_upsids = 1, + .n_auto_cals = 4, + .n_filters = 256, + .n_gates = 256, + .n_sdlbs = 496, + .n_dsm_cal_taxis = 5, + .buf_size = 1572864, + .qres_max_prio_idx = 315, + .qres_max_colour_idx = 323, + .tod_pin = 4, +}; + +static const struct sparx5_ops lan969x_ops = { + .is_port_2g5 = &lan969x_port_is_2g5, + .is_port_5g = &lan969x_port_is_5g, + .is_port_10g = &lan969x_port_is_10g, + .is_port_25g = &lan969x_port_is_25g, + .get_port_dev_index = &lan969x_port_dev_mapping, + .get_port_dev_bit = &lan969x_get_dev_mode_bit, + .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, + .get_sdlb_group = &lan969x_get_sdlb_group, + .set_port_mux = &lan969x_port_mux_set, + .ptp_irq_handler = &lan969x_ptp_irq_handler, + .dsm_calendar_calc = &lan969x_dsm_calendar_calc, +}; + +const struct sparx5_match_data lan969x_desc = { + .iomap = lan969x_main_iomap, + .iomap_size = ARRAY_SIZE(lan969x_main_iomap), + .ioranges = 2, + .regs = &lan969x_regs, + .consts = &lan969x_consts, + .ops = &lan969x_ops, +}; +EXPORT_SYMBOL_GPL(lan969x_desc); + +MODULE_DESCRIPTION("Microchip lan969x switch driver"); +MODULE_AUTHOR("Daniel Machon <daniel.machon@microchip.com>"); +MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net/ethernet/microchip/lan969x/lan969x.h new file mode 100644 index 000000000000..7ce047ad9ca4 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + */ + +#ifndef __LAN969X_H__ +#define __LAN969X_H__ + +#include "../sparx5/sparx5_main.h" +#include "../sparx5/sparx5_regs.h" + +/* lan969x.c */ +extern const struct sparx5_match_data lan969x_desc; + +/* lan969x_regs.c */ +extern const unsigned int lan969x_tsize[TSIZE_LAST]; +extern const unsigned int lan969x_raddr[RADDR_LAST]; +extern const unsigned int lan969x_rcnt[RCNT_LAST]; +extern const unsigned int lan969x_gaddr[GADDR_LAST]; +extern const unsigned int lan969x_gcnt[GCNT_LAST]; +extern const unsigned int lan969x_gsize[GSIZE_LAST]; +extern const unsigned int lan969x_fpos[FPOS_LAST]; +extern const unsigned int lan969x_fsize[FSIZE_LAST]; + +static inline bool lan969x_port_is_2g5(int portno) +{ + return portno == 1 || portno == 2 || portno == 3 || + portno == 5 || portno == 6 || portno == 7 || + portno == 10 || portno == 11 || portno == 14 || + portno == 15 || portno == 18 || portno == 19 || + portno == 22 || portno == 23; +} + +static inline bool lan969x_port_is_5g(int portno) +{ + return portno == 9 || portno == 13 || portno == 17 || + portno == 21; +} + +static inline bool lan969x_port_is_10g(int portno) +{ + return portno == 0 || portno == 4 || portno == 8 || + portno == 12 || portno == 16 || portno == 20 || + portno == 24 || portno == 25 || portno == 26 || + portno == 27; +} + +static inline bool lan969x_port_is_25g(int portno) +{ + return false; +} + +/* lan969x_calendar.c */ +int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data); +#endif diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c b/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c new file mode 100644 index 000000000000..e857640df185 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. + */ + +#include "lan969x.h" + +#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 +#define LAN969X_DSM_CAL_TAXIS 5 + +enum lan969x_dsm_cal_dev { + DSM_CAL_DEV_2G5, + DSM_CAL_DEV_5G, + DSM_CAL_DEV_10G, + DSM_CAL_DEV_OTHER, /* 1G or less */ + DSM_CAL_DEV_MAX +}; + +/* Each entry in the following struct defines properties for a given speed + * (10G, 5G, 2.5G, or 1G or less). + */ +struct lan969x_dsm_cal_dev_speed { + /* Number of devices that requires this speed. */ + u32 n_devs; + + /* Array of devices that requires this speed. */ + u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; + + /* Number of slots required for one device running this speed. */ + u32 n_slots; + + /* Gap between two slots for one device running this speed. */ + u32 gap; +}; + +static u32 +lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { + { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, + { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, + { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, + { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, + { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } +}; + +static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) +{ + if (*cal_idx >= cal_len) + return -EINVAL; + + do { + if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) + return 0; + + (*cal_idx)++; + } while (*cal_idx < cal_len); + + return -ENOENT; +} + +static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) +{ + return (speed == 10000 ? DSM_CAL_DEV_10G : + speed == 5000 ? DSM_CAL_DEV_5G : + speed == 2500 ? DSM_CAL_DEV_2G5 : + DSM_CAL_DEV_OTHER); +} + +static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) +{ + return (dev == DSM_CAL_DEV_10G ? 10000 : + dev == DSM_CAL_DEV_5G ? 5000 : + dev == DSM_CAL_DEV_2G5 ? 2500 : + 1000); +} + +int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data) +{ + struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; + u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; + struct lan969x_dsm_cal_dev_speed *speed; + int err; + + /* Maximum bandwidth for this taxi */ + taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); + + memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], + LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); + + for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { + u32 portno = data->taxi_ports[i]; + enum sparx5_cal_bw bw; + + bw = sparx5_get_port_cal_speed(sparx5, portno); + + if (portno < sparx5->data->consts->n_ports_all) + data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); + else + data->taxi_speeds[i] = 0; + } + + /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the + * this taxi map. + */ + for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { + u32 taxi_speed = data->taxi_speeds[i]; + enum lan969x_dsm_cal_dev dev; + + if (taxi_speed == 0) + continue; + + required_bw += taxi_speed; + + dev = lan969x_dsm_cal_get_dev(taxi_speed); + speed = &dev_speeds[dev]; + speed->devs[speed->n_devs++] = i; + n_devs++; + } + + if (required_bw > taxi_bw) { + pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", + required_bw, taxi_bw); + return -EINVAL; + } + + if (n_devs == 0) { + data->schedule[0] = SPX5_DSM_CAL_EMPTY; + return 0; + } + + cal_len = n_devs; + + /* Search for a calendar length that fits all active devices. */ + while (cal_len < SPX5_DSM_CAL_LEN) { + u32 bw_per_slot = taxi_bw / cal_len; + + n_slots = 0; + + for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { + speed = &dev_speeds[i]; + + if (speed->n_devs == 0) + continue; + + required_bw = lan969x_dsm_cal_get_speed(i); + speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); + + if (speed->n_slots) + speed->gap = DIV_ROUND_UP(cal_len, + speed->n_slots); + else + speed->gap = 0; + + n_slots += speed->n_slots * speed->n_devs; + } + + if (n_slots <= cal_len) + break; /* Found a suitable calendar length. */ + + /* Not good enough yet. */ + cal_len = n_slots; + } + + if (cal_len > SPX5_DSM_CAL_LEN) { + pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); + return -EINVAL; + } + + for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) + data->schedule[i] = SPX5_DSM_CAL_EMPTY; + + /* Place the remaining devices */ + for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { + speed = &dev_speeds[i]; + for (u32 dev = 0; dev < speed->n_devs; dev++) { + u32 idx = 0; + + for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { + err = lan969x_dsm_cal_idx_get(data->schedule, + cal_len, &idx); + if (err) + return err; + data->schedule[idx] = speed->devs[dev]; + idx += speed->gap; + } + } + } + + return 0; +} diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c b/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c new file mode 100644 index 000000000000..ace4ba21eec4 --- /dev/null +++ b/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip lan969x Switch driver + * + * Copyright (c) 2024 Microchip Technology Inc. + */ + +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b + */ + +#include "lan969x.h" + +const unsigned int lan969x_tsize[TSIZE_LAST] = { + [TC_DEV10G] = 10, + [TC_DEV2G5] = 28, + [TC_DEV5G] = 4, + [TC_PCS10G_BR] = 10, + [TC_PCS5G_BR] = 4, +}; + +const unsigned int lan969x_raddr[RADDR_LAST] = { + [RA_CPU_PROC_CTRL] = 160, + [RA_GCB_SOFT_RST] = 12, + [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, +}; + +const unsigned int lan969x_rcnt[RCNT_LAST] = { + [RC_ANA_AC_OWN_UPSID] = 1, + [RC_ANA_ACL_VCAP_S2_CFG] = 35, + [RC_ANA_ACL_OWN_UPSID] = 1, + [RC_ANA_CL_OWN_UPSID] = 1, + [RC_ANA_L2_OWN_UPSID] = 1, + [RC_ASM_PORT_CFG] = 32, + [RC_DSM_BUF_CFG] = 32, + [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, + [RC_DSM_RX_PAUSE_CFG] = 32, + [RC_DSM_MAC_CFG] = 32, + [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, + [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, + [RC_DSM_TAXI_CAL_CFG] = 6, + [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, + [RC_HSCH_PORT_MODE] = 35, + [RC_QFWD_SWITCH_PORT_MODE] = 35, + [RC_QSYS_PAUSE_CFG] = 35, + [RC_QSYS_ATOP] = 35, + [RC_QSYS_FWD_PRESSURE] = 35, + [RC_QSYS_CAL_AUTO] = 4, + [RC_REW_OWN_UPSID] = 1, + [RC_REW_RTAG_ETAG_CTRL] = 35, +}; + +const unsigned int lan969x_gaddr[GADDR_LAST] = { + [GA_ANA_AC_RAM_CTRL] = 202000, + [GA_ANA_AC_PS_COMMON] = 202880, + [GA_ANA_AC_MIRROR_PROBE] = 203232, + [GA_ANA_AC_SRC] = 201728, + [GA_ANA_AC_PGID] = 131072, + [GA_ANA_AC_TSN_SF] = 202028, + [GA_ANA_AC_TSN_SF_CFG] = 148480, + [GA_ANA_AC_TSN_SF_STATUS] = 147936, + [GA_ANA_AC_SG_ACCESS] = 202032, + [GA_ANA_AC_SG_CONFIG] = 202752, + [GA_ANA_AC_SG_STATUS] = 147952, + [GA_ANA_AC_SG_STATUS_STICKY] = 202044, + [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, + [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, + [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, + [GA_ANA_ACL_COMMON] = 8192, + [GA_ANA_ACL_KEY_SEL] = 9204, + [GA_ANA_ACL_CNT_B] = 4096, + [GA_ANA_ACL_STICKY] = 10852, + [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, + [GA_ANA_AC_POL_COMMON_BDLB] = 19464, + [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, + [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, + [GA_ANA_CL_PORT] = 65536, + [GA_ANA_CL_COMMON] = 87040, + [GA_ANA_L2_COMMON] = 561928, + [GA_ANA_L3_COMMON] = 370752, + [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, + [GA_ASM_CFG] = 18304, + [GA_ASM_PFC_TIMER_CFG] = 15568, + [GA_ASM_LBK_WM_CFG] = 15596, + [GA_ASM_LBK_MISC_CFG] = 15608, + [GA_ASM_RAM_CTRL] = 15684, + [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, + [GA_EACL_CNT_TBL] = 30720, + [GA_EACL_POL_CFG] = 38400, + [GA_EACL_ES2_STICKY] = 29072, + [GA_EACL_RAM_CTRL] = 29112, + [GA_GCB_SIO_CTRL] = 560, + [GA_HSCH_HSCH_DWRR] = 36480, + [GA_HSCH_HSCH_MISC] = 36608, + [GA_HSCH_HSCH_LEAK_LISTS] = 37256, + [GA_HSCH_SYSTEM] = 37384, + [GA_HSCH_MMGT] = 36260, + [GA_HSCH_TAS_CONFIG] = 37696, + [GA_PTP_PTP_CFG] = 512, + [GA_PTP_PTP_TOD_DOMAINS] = 528, + [GA_PTP_PHASE_DETECTOR_CTRL] = 628, + [GA_QSYS_CALCFG] = 2164, + [GA_QSYS_RAM_CTRL] = 2204, + [GA_REW_COMMON] = 98304, + [GA_REW_PORT] = 49152, + [GA_REW_VOE_PORT_LM_CNT] = 90112, + [GA_REW_RAM_CTRL] = 93992, + [GA_VOP_RAM_CTRL] = 16368, + [GA_XQS_SYSTEM] = 5744, + [GA_XQS_QLIMIT_SHR] = 6912, +}; + +const unsigned int lan969x_gcnt[GCNT_LAST] = { + [GC_ANA_AC_SRC] = 67, + [GC_ANA_AC_PGID] = 1054, + [GC_ANA_AC_TSN_SF_CFG] = 256, + [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, + [GC_ANA_ACL_KEY_SEL] = 99, + [GC_ANA_ACL_CNT_A] = 1024, + [GC_ANA_ACL_CNT_B] = 1024, + [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, + [GC_ANA_AC_SDLB_LBSET_TBL] = 496, + [GC_ANA_CL_PORT] = 35, + [GC_ANA_L2_ISDX_LIMIT] = 256, + [GC_ANA_L2_ISDX] = 1024, + [GC_ANA_L3_VLAN] = 4608, + [GC_ASM_DEV_STATISTICS] = 30, + [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, + [GC_EACL_CNT_TBL] = 512, + [GC_GCB_SIO_CTRL] = 1, + [GC_HSCH_HSCH_CFG] = 1120, + [GC_HSCH_HSCH_DWRR] = 32, + [GC_PTP_PTP_PINS] = 8, + [GC_PTP_PHASE_DETECTOR_CTRL] = 8, + [GC_REW_PORT] = 35, + [GC_REW_VOE_PORT_LM_CNT] = 240, +}; + +const unsigned int lan969x_gsize[GSIZE_LAST] = { + [GW_ANA_AC_SRC] = 4, + [GW_ANA_L2_COMMON] = 712, + [GW_ASM_CFG] = 1092, + [GW_CPU_CPU_REGS] = 180, + [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, + [GW_FDMA_FDMA] = 448, + [GW_GCB_CHIP_REGS] = 180, + [GW_HSCH_TAS_CONFIG] = 16, + [GW_PTP_PHASE_DETECTOR_CTRL] = 12, + [GW_QSYS_PAUSE_CFG] = 988, +}; + +const unsigned int lan969x_fpos[FPOS_LAST] = { + [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, + [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, + [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, + [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, + [FP_CPU_PROC_CTRL_VINITHI] = 3, + [FP_CPU_PROC_CTRL_CFGTE] = 2, + [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, + [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, + [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, + [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, + [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, + [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, + [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, + [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, + [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, + [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, + [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, +}; + +const unsigned int lan969x_fsize[FSIZE_LAST] = { + [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, + [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, + [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, + [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, + [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, + [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, + [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, + [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, + [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, + [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, + [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, + [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, + [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, + [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, + [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, + [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, + [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, + [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, + [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, + [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, + [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, + [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, + [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, + [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, + [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, + [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, + [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, + [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, + [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, + [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, + [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, + [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, + [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, + [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, + [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, + [FW_QRES_RES_CFG_WM_HIGH] = 11, + [FW_QRES_RES_STAT_MAXUSE] = 19, + [FW_QRES_RES_STAT_CUR_INUSE] = 19, + [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, + [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, + [FW_QSYS_ATOP_ATOP] = 11, + [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, + [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, + [FW_XQS_STAT_CFG_STAT_VIEW] = 10, + [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, + [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, + [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, + [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, +}; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c index b2a8d04ab509..5fe941c66c17 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c @@ -15,7 +15,6 @@ #define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar register */ /* DSM calendar information */ -#define SPX5_DSM_CAL_EMPTY 0xFFFF #define SPX5_DSM_CAL_TAXIS 8 #define SPX5_DSM_CAL_BW_LOSS 553 @@ -53,27 +52,32 @@ static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) case SPX5_TARGET_CT_7558: case SPX5_TARGET_CT_7558TSN: return 201000; + case SPX5_TARGET_CT_LAN9691VAO: + return 46000; + case SPX5_TARGET_CT_LAN9694RED: + case SPX5_TARGET_CT_LAN9694TSN: + case SPX5_TARGET_CT_LAN9694: + return 68000; + case SPX5_TARGET_CT_LAN9696RED: + case SPX5_TARGET_CT_LAN9696TSN: + case SPX5_TARGET_CT_LAN9692VAO: + case SPX5_TARGET_CT_LAN9696: + return 88000; + case SPX5_TARGET_CT_LAN9698RED: + case SPX5_TARGET_CT_LAN9698TSN: + case SPX5_TARGET_CT_LAN9693VAO: + case SPX5_TARGET_CT_LAN9698: + return 101000; default: return 0; } } -/* This is used in calendar configuration */ -enum sparx5_cal_bw { - SPX5_CAL_SPEED_NONE = 0, - SPX5_CAL_SPEED_1G = 1, - SPX5_CAL_SPEED_2G5 = 2, - SPX5_CAL_SPEED_5G = 3, - SPX5_CAL_SPEED_10G = 4, - SPX5_CAL_SPEED_25G = 5, - SPX5_CAL_SPEED_0G5 = 6, - SPX5_CAL_SPEED_12G5 = 7 -}; - static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock) { switch (cclock) { case SPX5_CORE_CLOCK_250MHZ: return 83000; /* 250000 / 3 */ + case SPX5_CORE_CLOCK_328MHZ: return 109375; /* 328000 / 3 */ case SPX5_CORE_CLOCK_500MHZ: return 166000; /* 500000 / 3 */ case SPX5_CORE_CLOCK_625MHZ: return 208000; /* 625000 / 3 */ default: return 0; @@ -81,7 +85,7 @@ static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock) return 0; } -static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) +u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) { switch (speed) { case SPX5_CAL_SPEED_1G: return 1000; @@ -94,6 +98,7 @@ static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) default: return 0; } } +EXPORT_SYMBOL_GPL(sparx5_cal_speed_to_value); static u32 sparx5_bandwidth_to_calendar(u32 bw) { @@ -111,8 +116,7 @@ static u32 sparx5_bandwidth_to_calendar(u32 bw) } } -static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, - u32 portno) +enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno) { struct sparx5_port *port; @@ -146,6 +150,7 @@ static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, return SPX5_CAL_SPEED_NONE; return sparx5_bandwidth_to_calendar(port->conf.bandwidth); } +EXPORT_SYMBOL_GPL(sparx5_get_port_cal_speed); /* Auto configure the QSYS calendar based on port configuration */ int sparx5_config_auto_calendar(struct sparx5 *sparx5) @@ -526,12 +531,23 @@ check_err: static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi, struct sparx5_calendar_data *data) { - u32 idx; - u32 cal_len = sparx5_dsm_cal_len(data->schedule), len; + u32 cal_len = sparx5_dsm_cal_len(data->schedule), len, idx; + + if (!is_sparx5(sparx5)) { + u32 val, act; + + val = spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi)); + act = DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val); + + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act), + DSM_TAXI_CAL_CFG_CAL_PGM_SEL, + sparx5, DSM_TAXI_CAL_CFG(taxi)); + } - spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), - sparx5, - DSM_TAXI_CAL_CFG(taxi)); + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), + DSM_TAXI_CAL_CFG_CAL_PGM_ENA, + sparx5, + DSM_TAXI_CAL_CFG(taxi)); for (idx = 0; idx < cal_len; idx++) { spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx), DSM_TAXI_CAL_CFG_CAL_IDX, @@ -542,13 +558,21 @@ static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi, sparx5, DSM_TAXI_CAL_CFG(taxi)); } - spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), - sparx5, - DSM_TAXI_CAL_CFG(taxi)); + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), + DSM_TAXI_CAL_CFG_CAL_PGM_ENA, + sparx5, + DSM_TAXI_CAL_CFG(taxi)); len = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi))); if (len != cal_len - 1) goto update_err; + + if (!is_sparx5(sparx5)) { + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1), + DSM_TAXI_CAL_CFG_CAL_SWITCH, + sparx5, DSM_TAXI_CAL_CFG(taxi)); + } + return 0; update_err: dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c index 88f7509f0980..0027144a2af2 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c @@ -154,7 +154,7 @@ static bool sparx5_fdma_rx_get_frame(struct sparx5 *sparx5, struct sparx5_rx *rx skb = rx->skb[fdma->dcb_index][fdma->db_index]; skb_put(skb, fdma_db_len_get(db_hw)); /* Now do the normal processing of the skb */ - sparx5_ifh_parse((u32 *)skb->data, &fi); + sparx5_ifh_parse(sparx5, (u32 *)skb->data, &fi); /* Map to port netdev */ port = fi.src_port < sparx5->data->consts->n_ports ? sparx5->ports[fi.src_port] : diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c index d1e9bc030c80..4f2d5413a64f 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -24,6 +24,8 @@ #include <linux/types.h> #include <linux/reset.h> +#include "../lan969x/lan969x.h" /* for lan969x match data */ + #include "sparx5_main_regs.h" #include "sparx5_main.h" #include "sparx5_port.h" @@ -227,6 +229,40 @@ bool is_sparx5(struct sparx5 *sparx5) } } +static void sparx5_init_features(struct sparx5 *sparx5) +{ + switch (sparx5->target_ct) { + case SPX5_TARGET_CT_7546: + case SPX5_TARGET_CT_7549: + case SPX5_TARGET_CT_7552: + case SPX5_TARGET_CT_7556: + case SPX5_TARGET_CT_7558: + case SPX5_TARGET_CT_7546TSN: + case SPX5_TARGET_CT_7549TSN: + case SPX5_TARGET_CT_7552TSN: + case SPX5_TARGET_CT_7556TSN: + case SPX5_TARGET_CT_7558TSN: + case SPX5_TARGET_CT_LAN9691VAO: + case SPX5_TARGET_CT_LAN9694TSN: + case SPX5_TARGET_CT_LAN9694RED: + case SPX5_TARGET_CT_LAN9692VAO: + case SPX5_TARGET_CT_LAN9696TSN: + case SPX5_TARGET_CT_LAN9696RED: + case SPX5_TARGET_CT_LAN9693VAO: + case SPX5_TARGET_CT_LAN9698TSN: + case SPX5_TARGET_CT_LAN9698RED: + sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); + break; + default: + break; + } +} + +bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) +{ + return sparx5->features & feature; +} + static int sparx5_create_targets(struct sparx5 *sparx5) { const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; @@ -475,6 +511,20 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) freq = 0; /* Not supported */ break; + case SPX5_TARGET_CT_LAN9694: + case SPX5_TARGET_CT_LAN9691VAO: + case SPX5_TARGET_CT_LAN9694TSN: + case SPX5_TARGET_CT_LAN9694RED: + case SPX5_TARGET_CT_LAN9696: + case SPX5_TARGET_CT_LAN9692VAO: + case SPX5_TARGET_CT_LAN9696TSN: + case SPX5_TARGET_CT_LAN9696RED: + case SPX5_TARGET_CT_LAN9698: + case SPX5_TARGET_CT_LAN9693VAO: + case SPX5_TARGET_CT_LAN9698TSN: + case SPX5_TARGET_CT_LAN9698RED: + freq = SPX5_CORE_CLOCK_328MHZ; + break; default: dev_err(sparx5->dev, "Target (%#04x) not supported\n", sparx5->target_ct); @@ -516,16 +566,19 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); + } else { + pol_upd_int = 820; // SPX5_CORE_CLOCK_328MHZ } /* Update state with chosen frequency */ sparx5->coreclock = freq; clk_period = sparx5_clk_period(freq); - spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), - HSCH_SYS_CLK_PER_100PS, - sparx5, - HSCH_SYS_CLK_PER); + if (is_sparx5(sparx5)) + spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), + HSCH_SYS_CLK_PER_100PS, + sparx5, + HSCH_SYS_CLK_PER); spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, @@ -715,15 +768,17 @@ static int sparx5_start(struct sparx5 *sparx5) if (err) return err; - err = sparx5_vcap_init(sparx5); - if (err) { - sparx5_unregister_notifier_blocks(sparx5); - return err; + if (is_sparx5(sparx5)) { + err = sparx5_vcap_init(sparx5); + if (err) { + sparx5_unregister_notifier_blocks(sparx5); + return err; + } } /* Start Frame DMA with fallback to register based INJ/XTR */ err = -ENXIO; - if (sparx5->fdma_irq >= 0) { + if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) { if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) err = devm_request_threaded_irq(sparx5->dev, sparx5->fdma_irq, @@ -750,7 +805,8 @@ static int sparx5_start(struct sparx5 *sparx5) sparx5->xtr_irq = -ENXIO; } - if (sparx5->ptp_irq >= 0) { + if (sparx5->ptp_irq >= 0 && + sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) { err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, NULL, ops->ptp_irq_handler, IRQF_ONESHOT, "sparx5-ptp", @@ -894,6 +950,9 @@ static int mchp_sparx5_probe(struct platform_device *pdev) sparx5->target_ct = (enum spx5_target_chiptype) GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); + /* Initialize the features based on the target */ + sparx5_init_features(sparx5); + /* Initialize Switchcore and internal RAMs */ err = sparx5_init_switchcore(sparx5); if (err) { @@ -1031,6 +1090,9 @@ static const struct sparx5_match_data sparx5_desc = { static const struct of_device_id mchp_sparx5_match[] = { { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, +#if IS_ENABLED(CONFIG_LAN969X_SWITCH) + { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc }, +#endif { } }; MODULE_DEVICE_TABLE(of, mchp_sparx5_match); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h index 364ae92969bc..146bdc938adc 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -26,16 +26,28 @@ /* Target chip type */ enum spx5_target_chiptype { - SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ - SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ - SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ - SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ - SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ - SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ - SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ - SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ - SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ - SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ + SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ + SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ + SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ + SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ + SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ + SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ + SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ + SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ + SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ + SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ + SPX5_TARGET_CT_LAN9694 = 0x9694, /* lan969x-40 */ + SPX5_TARGET_CT_LAN9691VAO = 0x9691, /* lan969x-40-VAO */ + SPX5_TARGET_CT_LAN9694TSN = 0x9695, /* lan969x-40-TSN */ + SPX5_TARGET_CT_LAN9694RED = 0x969A, /* lan969x-40-RED */ + SPX5_TARGET_CT_LAN9696 = 0x9696, /* lan969x-60 */ + SPX5_TARGET_CT_LAN9692VAO = 0x9692, /* lan969x-65-VAO */ + SPX5_TARGET_CT_LAN9696TSN = 0x9697, /* lan969x-60-TSN */ + SPX5_TARGET_CT_LAN9696RED = 0x969B, /* lan969x-60-RED */ + SPX5_TARGET_CT_LAN9698 = 0x9698, /* lan969x-100 */ + SPX5_TARGET_CT_LAN9693VAO = 0x9693, /* lan969x-100-VAO */ + SPX5_TARGET_CT_LAN9698TSN = 0x9699, /* lan969x-100-TSN */ + SPX5_TARGET_CT_LAN9698RED = 0x969C, /* lan969x-100-RED */ }; enum sparx5_port_max_tags { @@ -51,6 +63,23 @@ enum sparx5_vlan_port_type { SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ }; +/* This is used in calendar configuration */ +enum sparx5_cal_bw { + SPX5_CAL_SPEED_NONE = 0, + SPX5_CAL_SPEED_1G = 1, + SPX5_CAL_SPEED_2G5 = 2, + SPX5_CAL_SPEED_5G = 3, + SPX5_CAL_SPEED_10G = 4, + SPX5_CAL_SPEED_25G = 5, + SPX5_CAL_SPEED_0G5 = 6, + SPX5_CAL_SPEED_12G5 = 7 +}; + +enum sparx5_feature { + SPX5_FEATURE_PSFP = BIT(0), + SPX5_FEATURE_PTP = BIT(1), +}; + #define SPX5_PORTS 65 #define SPX5_PORTS_ALL 70 /* Total number of ports */ @@ -101,6 +130,9 @@ enum sparx5_vlan_port_type { #define SPX5_DSM_CAL_LEN 64 #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 +#define SPX5_DSM_CAL_EMPTY 0xFFFF + +#define SPARX5_MAX_PTP_ID 512 struct sparx5; @@ -192,6 +224,7 @@ struct sparx5_port { enum sparx5_core_clockfreq { SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ + SPX5_CORE_CLOCK_328MHZ, /* 328MHZ core clock frequency */ SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ }; @@ -309,6 +342,7 @@ struct sparx5 { struct device *dev; u32 chip_id; enum spx5_target_chiptype target_ct; + u32 features; void __iomem *regs[NUM_TARGETS]; int port_count; struct mutex lock; /* MAC reg lock */ @@ -376,6 +410,7 @@ struct sparx5 { /* sparx5_main.c */ bool is_sparx5(struct sparx5 *sparx5); +bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature); /* sparx5_switchdev.c */ int sparx5_register_notifier_blocks(struct sparx5 *sparx5); @@ -388,7 +423,7 @@ struct frame_info { }; void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); -void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); +void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info); irqreturn_t sparx5_xtr_handler(int irq, void *_priv); netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); int sparx5_manual_injection_mode(struct sparx5 *sparx5); @@ -439,6 +474,8 @@ int sparx5_config_auto_calendar(struct sparx5 *sparx5); int sparx5_config_dsm_calendar(struct sparx5 *sparx5); int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, struct sparx5_calendar_data *data); +u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed); +enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno); /* sparx5_ethtool.c */ @@ -456,10 +493,13 @@ static inline int sparx5_dcb_init(struct sparx5 *sparx5) #endif /* sparx5_netdev.c */ -void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); +void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, + u64 timestamp); void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); -void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); -void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); +void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_type); +void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_w16_offset); void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); bool sparx5_netdevice_check(const struct net_device *dev); struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); @@ -483,6 +523,9 @@ void sparx5_ptp_txtstamp_release(struct sparx5_port *port, struct sk_buff *skb); irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); +void sparx5_get_hwtimestamp(struct sparx5 *sparx5, + struct timespec64 *ts, + u32 nsec); /* sparx5_vcap_impl.c */ int sparx5_vcap_init(struct sparx5 *sparx5); @@ -539,7 +582,7 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx); int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate); -int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); +u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); @@ -641,6 +684,8 @@ static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) switch (cclock) { case SPX5_CORE_CLOCK_250MHZ: return 4000; + case SPX5_CORE_CLOCK_328MHZ: + return 3048; case SPX5_CORE_CLOCK_500MHZ: return 2000; case SPX5_CORE_CLOCK_625MHZ: diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h index 0e8b18bcf179..561344f19062 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h @@ -2666,6 +2666,44 @@ extern const struct sparx5_regs *regs; #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) +/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ +#define DEV2G5_PHAD_CTRL(t, g) \ + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ + regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) + +#define DEV2G5_PHAD_CTRL_PHAD_ENA\ + BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ + spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ + spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) + +/* LAN969X ONLY */ +#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) +#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ + FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) +#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ + FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) + +/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ +#define DEV2G5_PHAD_CTRL(t, g) \ + __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ + regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) + +#define DEV2G5_PHAD_CTRL_PHAD_ENA\ + BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ + spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) +#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ + spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) + +/* LAN969X ONLY */ +#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) +#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ + FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) +#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ + FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) + /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ #define DEV10G_MAC_ENA_CFG(t) \ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ @@ -2869,6 +2907,11 @@ extern const struct sparx5_regs *regs; #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) +/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ +#define DEV10G_PTP_STAMPER_CFG(t) \ + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \ + 1, 4) + /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ #define DEV10G_PCS25G_CFG(t) \ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ @@ -4267,6 +4310,11 @@ extern const struct sparx5_regs *regs; #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) +/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ +#define DEV5G_PTP_STAMPER_CFG(t) \ + __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \ + 4) + /* DSM:RAM_CTRL:RAM_INIT */ #define DSM_RAM_INIT \ __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) @@ -4444,6 +4492,27 @@ extern const struct sparx5_regs *regs; #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) +/* LAN969X ONLY */ +#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23) +#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\ + FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) +#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) + +/* LAN969X ONLY */ +#define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22) +#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\ + FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) +#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) + +/* LAN969X ONLY */ +#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21) +#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\ + FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) +#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) + /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ #define EACL_VCAP_ES2_KEY_SEL(g, r) \ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ @@ -6720,6 +6789,69 @@ extern const struct sparx5_regs *regs; regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) +/* LAN969X ONLY */ +/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ +#define PTP_TWOSTEP_CTRL \ + __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4) + +#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) +#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) +#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) + +#define PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) +#define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x) +#define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x) + +#define PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) +#define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x) +#define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x) + +#define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) +#define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) +#define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) + +#define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) +#define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) +#define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) + +#define PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) +#define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x) +#define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ + FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x) + +/* LAN969X ONLY */ +/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */ +#define PTP_TWOSTEP_STAMP_NSEC \ + __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4) + +#define PTP_TWOSTEP_STAMP_NSEC_NS GENMASK(29, 0) +#define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x) +#define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\ + FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x) + +/* LAN969X ONLY */ +/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */ +#define PTP_TWOSTEP_STAMP_SUBNS \ + __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4) + +#define PTP_TWOSTEP_STAMP_SUBNS_NS GENMASK(7, 0) +#define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\ + FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x) +#define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\ + FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x) + /* QFWD:SYSTEM:SWITCH_PORT_MODE */ #define QFWD_SWITCH_PORT_MODE(r) \ __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c index 459a53676ae9..9806729e9c62 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c @@ -24,8 +24,14 @@ static u32 sparx5_mirror_to_dir(bool ingress) /* Get ports belonging to this mirror */ static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) { - return (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32 | - spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); + u64 val; + + val = spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); + + if (is_sparx5(sparx5)) + val |= (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; + + return val; } /* Add port to mirror (only front ports) */ diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c index d4e9986ef16a..1d34af78166a 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c @@ -64,16 +64,16 @@ void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno) /* MISC.CPU_MASK/DPORT = Destination port */ ifh_encode_bitfield(ifh_hdr, portno, 29, 8); /* MISC.PIPELINE_PT */ - ifh_encode_bitfield(ifh_hdr, 16, 37, 5); + ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5); /* MISC.PIPELINE_ACT */ ifh_encode_bitfield(ifh_hdr, 1, 42, 3); /* FWD.SRC_PORT = CPU */ ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), - 46, 7); + 46, is_sparx5(sparx5) ? 7 : 6); /* FWD.SFLOW_ID (disable SFlow sampling) */ - ifh_encode_bitfield(ifh_hdr, 124, 57, 7); + ifh_encode_bitfield(ifh_hdr, 124, is_sparx5(sparx5) ? 57 : 56, 7); /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ - ifh_encode_bitfield(ifh_hdr, 1, 67, 1); + ifh_encode_bitfield(ifh_hdr, 1, is_sparx5(sparx5) ? 67 : 66, 1); } void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) @@ -81,19 +81,25 @@ void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32, 10); } -void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type) +void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_type) { - ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); + ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190, + 4); } -void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset) +void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_w16_offset) { - ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); + ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, + is_sparx5(sparx5) ? 195 : 194, 6); } -void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp) +void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, + u64 timestamp) { - ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); + ifh_encode_bitfield(ifh_hdr, timestamp, 232, + is_sparx5(sparx5) ? 40 : 38); } static int sparx5_port_open(struct net_device *ndev) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c index 5bfa86a71ac8..b6f635d85820 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c @@ -32,7 +32,7 @@ void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) spx5_wr(0, sparx5, QS_XTR_FLUSH); } -void sparx5_ifh_parse(u32 *ifh, struct frame_info *info) +void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info) { u8 *xtr_hdr = (u8 *)ifh; @@ -43,7 +43,8 @@ void sparx5_ifh_parse(u32 *ifh, struct frame_info *info) ((u32)xtr_hdr[29] << 8) | ((u32)xtr_hdr[30] << 0); fwd = (fwd >> 5); - info->src_port = FIELD_GET(GENMASK(7, 1), fwd); + info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), + fwd); /* * Bit 270-271 are occasionally unexpectedly set by the hardware, @@ -72,7 +73,7 @@ static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap) ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); /* Decode IFH (what's needed) */ - sparx5_ifh_parse(ifh, &fi); + sparx5_ifh_parse(sparx5, ifh, &fi); /* Map to port netdev */ port = fi.src_port < sparx5->data->consts->n_ports ? @@ -242,9 +243,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev) return NETDEV_TX_BUSY; sparx5_set_port_ifh_rew_op(ifh, SPARX5_SKB_CB(skb)->rew_op); - sparx5_set_port_ifh_pdu_type(ifh, SPARX5_SKB_CB(skb)->pdu_type); - sparx5_set_port_ifh_pdu_w16_offset(ifh, SPARX5_SKB_CB(skb)->pdu_w16_offset); - sparx5_set_port_ifh_timestamp(ifh, SPARX5_SKB_CB(skb)->ts_id); + sparx5_set_port_ifh_pdu_type(sparx5, ifh, + SPARX5_SKB_CB(skb)->pdu_type); + sparx5_set_port_ifh_pdu_w16_offset(sparx5, ifh, + SPARX5_SKB_CB(skb)->pdu_w16_offset); + sparx5_set_port_ifh_timestamp(sparx5, ifh, + SPARX5_SKB_CB(skb)->ts_id); } skb_tx_timestamp(skb); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c index 0b38b4cb0929..1401761c6251 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -476,6 +476,9 @@ static int sparx5_port_fifo_sz(struct sparx5 *sparx5, u32 mac_width = 8; u32 addition = 0; + if (!is_sparx5(sparx5)) + return 0; + switch (speed) { case SPEED_25000: return 0; @@ -921,6 +924,20 @@ static int sparx5_port_config_low_set(struct sparx5 *sparx5, sparx5, DEV2G5_DEV_RST_CTRL(port->portno)); + /* Enable PHAD_CTRL for better timestamping */ + if (!is_sparx5(sparx5)) { + for (int i = 0; i < 2; ++i) { + /* Divide the port clock by three for the two + * phase detection registers. + */ + spx5_rmw(DEV2G5_PHAD_CTRL_DIV_CFG_SET(3) | + DEV2G5_PHAD_CTRL_PHAD_ENA_SET(1), + DEV2G5_PHAD_CTRL_DIV_CFG | + DEV2G5_PHAD_CTRL_PHAD_ENA, + sparx5, DEV2G5_PHAD_CTRL(port->portno, i)); + } + } + return 0; } @@ -978,6 +995,7 @@ int sparx5_port_config(struct sparx5 *sparx5, struct sparx5_port_config *conf) { bool high_speed_dev = sparx5_is_baser(conf->portmode); + const struct sparx5_ops *ops = sparx5->data->ops; int err, urgency, stop_wm; err = sparx5_port_verify_speed(sparx5, port, conf); @@ -993,6 +1011,13 @@ int sparx5_port_config(struct sparx5 *sparx5, if (err) return err; + if (!is_sparx5(sparx5) && ops->is_port_10g(port->portno) && + conf->speed < SPEED_10000) + spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), + DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, + sparx5, + DSM_DEV_TX_STOP_WM_CFG(port->portno)); + /* Set the DSM stop watermark */ stop_wm = sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(stop_wm), @@ -1144,6 +1169,27 @@ int sparx5_port_init(struct sparx5 *sparx5, DEV25G_PCS25G_SD_CFG(pix)); } + if (!is_sparx5(sparx5)) { + void __iomem *inst; + u32 dev, tinst; + + if (ops->is_port_10g(port->portno)) { + dev = sparx5_to_high_dev(sparx5, port->portno); + tinst = sparx5_port_dev_index(sparx5, port->portno); + inst = spx5_inst_get(sparx5, dev, tinst); + + spx5_inst_wr(5, inst, + DEV10G_PTP_STAMPER_CFG(port->portno)); + } else if (ops->is_port_5g(port->portno)) { + dev = sparx5_to_high_dev(sparx5, port->portno); + tinst = sparx5_port_dev_index(sparx5, port->portno); + inst = spx5_inst_get(sparx5, dev, tinst); + + spx5_inst_wr(5, inst, + DEV5G_PTP_STAMPER_CFG(port->portno)); + } + } + return 0; } diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c index 9b15e44f9e64..1c2903700a9c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c @@ -11,8 +11,6 @@ #include "sparx5_main_regs.h" #include "sparx5_main.h" -#define SPARX5_MAX_PTP_ID 512 - #define TOD_ACC_PIN 0x4 enum { @@ -38,6 +36,9 @@ static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) case SPX5_CORE_CLOCK_250MHZ: res = 2301339409586; break; + case SPX5_CORE_CLOCK_328MHZ: + res = 1756832768924; + break; case SPX5_CORE_CLOCK_500MHZ: res = 1150669704793; break; @@ -60,6 +61,9 @@ static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5) case SPX5_CORE_CLOCK_250MHZ: res = 0x1FF0000000000000; break; + case SPX5_CORE_CLOCK_328MHZ: + res = 0x18604697DD0F9B5B; + break; case SPX5_CORE_CLOCK_500MHZ: res = 0x0FF8000000000000; break; @@ -269,9 +273,9 @@ void sparx5_ptp_txtstamp_release(struct sparx5_port *port, spin_unlock_irqrestore(&sparx5->ptp_ts_id_lock, flags); } -static void sparx5_get_hwtimestamp(struct sparx5 *sparx5, - struct timespec64 *ts, - u32 nsec) +void sparx5_get_hwtimestamp(struct sparx5 *sparx5, + struct timespec64 *ts, + u32 nsec) { /* Read current PTP time to get seconds */ const struct sparx5_consts *consts = sparx5->data->consts; @@ -299,6 +303,7 @@ static void sparx5_get_hwtimestamp(struct sparx5 *sparx5, spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); } +EXPORT_SYMBOL_GPL(sparx5_get_hwtimestamp); irqreturn_t sparx5_ptp_irq_handler(int irq, void *args) { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c index d065f8c40d37..e580670f3992 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c @@ -367,9 +367,10 @@ static u32 sparx5_weight_to_hw_cost(u32 weight_min, u32 weight) static int sparx5_dwrr_conf_set(struct sparx5_port *port, struct sparx5_dwrr *dwrr) { + u32 layer = is_sparx5(port->sparx5) ? 2 : 1; int i; - spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) | + spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer) | HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(port->portno), HSCH_HSCH_CFG_CFG_HSCH_LAYER | HSCH_HSCH_CFG_CFG_CFG_SE_IDX, port->sparx5, HSCH_HSCH_CFG_CFG); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c index 1db212ce3df7..220e81b714d4 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c @@ -4,7 +4,7 @@ * Copyright (c) 2024 Microchip Technology Inc. */ -/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b */ @@ -140,6 +140,7 @@ const unsigned int sparx5_gsize[GSIZE_LAST] = { [GW_ANA_L2_COMMON] = 700, [GW_ASM_CFG] = 1088, [GW_CPU_CPU_REGS] = 204, + [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 8, [GW_FDMA_FDMA] = 428, [GW_GCB_CHIP_REGS] = 424, [GW_HSCH_TAS_CONFIG] = 12, @@ -157,6 +158,8 @@ const unsigned int sparx5_fpos[FPOS_LAST] = { [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6, [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5, [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1, + [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 7, + [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 6, [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7, [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6, [FP_FDMA_CH_CFG_CH_INJ_PORT] = 5, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h index c4e8b581c1f3..ea28130c2341 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h @@ -4,7 +4,7 @@ * Copyright (c) 2024 Microchip Technology Inc. */ -/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. +/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b */ @@ -151,6 +151,7 @@ enum sparx5_gsize_enum { GW_ANA_L2_COMMON, GW_ASM_CFG, GW_CPU_CPU_REGS, + GW_DEV2G5_PHASE_DETECTOR_CTRL, GW_FDMA_FDMA, GW_GCB_CHIP_REGS, GW_HSCH_TAS_CONFIG, @@ -169,6 +170,8 @@ enum sparx5_fpos_enum { FP_CPU_PROC_CTRL_CP15S_DISABLE, FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, FP_CPU_PROC_CTRL_L2_FLUSH_REQ, + FP_DEV2G5_PHAD_CTRL_PHAD_ENA, + FP_DEV2G5_PHAD_CTRL_PHAD_FAILED, FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, FP_FDMA_CH_CFG_CH_INJ_PORT, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c index df1d15600aad..98a3f44c569c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c @@ -25,17 +25,13 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx) return &sdlb_groups[idx]; } -int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) +u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) { - u32 clk_per_100ps; u64 clk_hz; - clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5, - HSCH_SYS_CLK_PER)); - if (!clk_per_100ps) - clk_per_100ps = SPX5_CLK_PER_100PS_DEFAULT; + clk_hz = (10 * 1000 * 1000) / + (sparx5_clk_period(sparx5->coreclock) / 100); - clk_hz = (10 * 1000 * 1000) / clk_per_100ps; return clk_hz *= 1000; } diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c b/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c index c3bbed140554..4dc1ebd5d510 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c @@ -1284,6 +1284,11 @@ static int sparx5_tc_flower_replace(struct net_device *ndev, /* Setup PSFP */ if (tc_sg_idx >= 0 || tc_pol_idx >= 0) { + if (!sparx5_has_feature(sparx5, SPX5_FEATURE_PSFP)) { + err = -EOPNOTSUPP; + goto out; + } + err = sparx5_tc_flower_psfp_setup(sparx5, vrule, tc_sg_idx, tc_pol_idx, &sg, &fm, &sf); if (err) |