diff options
Diffstat (limited to 'Documentation/devicetree/bindings/timer')
47 files changed, 1153 insertions, 566 deletions
diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt b/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt deleted file mode 100644 index e698e3488735..000000000000 --- a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt +++ /dev/null @@ -1,18 +0,0 @@ -Altera Timer - -Required properties: - -- compatible : should be "altr,timer-1.0" -- reg : Specifies base physical address and size of the registers. -- interrupts : Should contain the timer interrupt number -- clock-frequency : The frequency of the clock that drives the counter, in Hz. - -Example: - -timer { - compatible = "altr,timer-1.0"; - reg = <0x00400000 0x00000020>; - interrupt-parent = <&cpu>; - interrupts = <11>; - clock-frequency = <125000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml b/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml new file mode 100644 index 000000000000..576260c72d42 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/altr,timer-1.0.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/altr,timer-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Timer + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + compatible: + const: altr,timer-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + description: Frequency of the clock that drives the counter, in Hz. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@400000 { + compatible = "altr,timer-1.0"; + reg = <0x00400000 0x00000020>; + interrupts = <11>; + clock-frequency = <125000000>; + }; diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt b/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt deleted file mode 100644 index 48f84d74edde..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -ARM MPS2 timer - -The MPS2 platform has simple general-purpose 32 bits timers. - -Required properties: -- compatible : Should be "arm,mps2-timer" -- reg : Address and length of the register set -- interrupts : Reference to the timer interrupt - -Required clocking property, have to be one of: -- clocks : The input clock of the timer -- clock-frequency : The rate in HZ in input of the ARM MPS2 timer - -Examples: - -timer1: mps2-timer@40000000 { - compatible = "arm,mps2-timer"; - reg = <0x40000000 0x1000>; - interrupts = <8>; - clocks = <&sysclk>; -}; - -timer2: mps2-timer@40001000 { - compatible = "arm,mps2-timer"; - reg = <0x40001000 0x1000>; - interrupts = <9>; - clock-frequency = <25000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml b/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml new file mode 100644 index 000000000000..64c6aedd7e8e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,mps2-timer.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm,mps2-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM MPS2 timer + +maintainers: + - Vladimir Murzin <vladimir.murzin@arm.com> + +description: + The MPS2 platform has simple general-purpose 32 bits timers. + +properties: + compatible: + const: arm,mps2-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Rate in Hz of the timer input clock + +oneOf: + - required: [clocks] + - required: [clock-frequency] + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@40000000 { + compatible = "arm,mps2-timer"; + reg = <0x40000000 0x1000>; + interrupts = <8>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt deleted file mode 100644 index d4c62e7b1714..000000000000 --- a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Cirrus Logic CLPS711X Timer Counter - -Required properties: -- compatible: Shall contain "cirrus,ep7209-timer". -- reg : Address and length of the register set. -- interrupts: The interrupt number of the timer. -- clocks : phandle of timer reference clock. - -Note: Each timer should have an alias correctly numbered in "aliases" node. - -Example: - aliases { - timer0 = &timer1; - timer1 = &timer2; - }; - - timer1: timer@80000300 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000300 0x4>; - interrupts = <8>; - clocks = <&clks 5>; - }; - - timer2: timer@80000340 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000340 0x4>; - interrupts = <9>; - clocks = <&clks 6>; - }; diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml new file mode 100644 index 000000000000..507b777e16bc --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/cirrus,clps711x-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Timer Counter + +maintainers: + - Alexander Shiyan <shc_work@mail.ru> + +properties: + compatible: + oneOf: + - items: + - enum: + - cirrus,ep7312-timer + - const: cirrus,ep7209-timer + - const: cirrus,ep7209-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@80000300 { + compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; + reg = <0x80000300 0x4>; + interrupts = <8>; + clocks = <&clks 5>; + }; diff --git a/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml b/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml new file mode 100644 index 000000000000..8f1a5af32a36 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cnxt,cx92755-timer.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cnxt,cx92755-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor SoCs Timer Controller + +maintainers: + - Baruch Siach <baruch@tkos.co.il> + +properties: + compatible: + const: cnxt,cx92755-timer + + reg: + maxItems: 1 + + interrupts: + description: Contains 8 interrupts, one for each timer + items: + - description: interrupt for timer 0 + - description: interrupt for timer 1 + - description: interrupt for timer 2 + - description: interrupt for timer 3 + - description: interrupt for timer 4 + - description: interrupt for timer 5 + - description: interrupt for timer 6 + - description: interrupt for timer 7 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@f0000fc0 { + compatible = "cnxt,cx92755-timer"; + reg = <0xf0000fc0 0x40>; + interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; + clocks = <&main_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt deleted file mode 100644 index 6b04344f4bea..000000000000 --- a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt +++ /dev/null @@ -1,42 +0,0 @@ -================= -gx6605s SOC Timer -================= - -The timer is used in gx6605s soc as system timer and the driver -contain clk event and clk source. - -============================== -timer node bindings definition -============================== - - Description: Describes gx6605s SOC timer - - PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: must be "csky,gx6605s-timer" - - reg - Usage: required - Value type: <u32 u32> - Definition: <phyaddr size> in soc from cpu view - - clocks - Usage: required - Value type: phandle + clock specifier cells - Definition: must be input clk node - - interrupt - Usage: required - Value type: <u32> - Definition: must be timer irq num defined by soc - -Examples: ---------- - - timer0: timer@20a000 { - compatible = "csky,gx6605s-timer"; - reg = <0x0020a000 0x400>; - clocks = <&dummy_apb_clk>; - interrupts = <10>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml new file mode 100644 index 000000000000..888fc8113996 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,gx6605s-timer.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/csky,gx6605s-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: gx6605s SOC Timer + +maintainers: + - Guo Ren <guoren@kernel.org> + +properties: + compatible: + const: csky,gx6605s-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@20a000 { + compatible = "csky,gx6605s-timer"; + reg = <0x0020a000 0x400>; + clocks = <&dummy_apb_clk>; + interrupts = <10>; + }; diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.txt b/Documentation/devicetree/bindings/timer/csky,mptimer.txt deleted file mode 100644 index f5c7e99cf52b..000000000000 --- a/Documentation/devicetree/bindings/timer/csky,mptimer.txt +++ /dev/null @@ -1,42 +0,0 @@ -============================ -C-SKY Multi-processors Timer -============================ - -C-SKY multi-processors timer is designed for C-SKY SMP system and the -regs is accessed by cpu co-processor 4 registers with mtcr/mfcr. - - - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. - - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. - - PTIM_CCVR "cr<3, 14>" Current counter value reg. - - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event. - -============================== -timer node bindings definition -============================== - - Description: Describes SMP timer - - PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: must be "csky,mptimer" - - clocks - Usage: required - Value type: <node> - Definition: must be input clk node - - interrupts - Usage: required - Value type: <u32> - Definition: must be timer irq num defined by soc - -Examples: ---------- - - timer: timer { - compatible = "csky,mptimer"; - clocks = <&dummy_apb_clk>; - interrupts = <16>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/timer/csky,mptimer.yaml b/Documentation/devicetree/bindings/timer/csky,mptimer.yaml new file mode 100644 index 000000000000..12cc5282c8f8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/csky,mptimer.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/csky,mptimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: C-SKY Multi-processors Timer + +maintainers: + - Flavio Suligoi <f.suligoi@asem.it> + - Guo Ren <guoren@kernel.org> + +description: | + C-SKY multi-processors timer is designed for C-SKY SMP system and the regs are + accessed by cpu co-processor 4 registers with mtcr/mfcr. + + - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. + - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. + - PTIM_CCVR "cr<3, 14>" Current counter value reg. + - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event. + +properties: + compatible: + items: + - const: csky,mptimer + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer { + compatible = "csky,mptimer"; + clocks = <&dummy_apb_clk>; + interrupts = <16>; + }; diff --git a/Documentation/devicetree/bindings/timer/digicolor-timer.txt b/Documentation/devicetree/bindings/timer/digicolor-timer.txt deleted file mode 100644 index d1b659bbc29f..000000000000 --- a/Documentation/devicetree/bindings/timer/digicolor-timer.txt +++ /dev/null @@ -1,18 +0,0 @@ -Conexant Digicolor SoCs Timer Controller - -Required properties: - -- compatible : should be "cnxt,cx92755-timer" -- reg : Specifies base physical address and size of the "Agent Communication" - timer registers -- interrupts : Contains 8 interrupts, one for each timer -- clocks: phandle to the main clock - -Example: - - timer@f0000fc0 { - compatible = "cnxt,cx92755-timer"; - reg = <0xf0000fc0 0x40>; - interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; - clocks = <&main_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml new file mode 100644 index 000000000000..c1e7c2b6afde --- /dev/null +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet EN751221 High Precision Timer (HPT) + +maintainers: + - Caleb James DeLisle <cjd@cjdns.fr> + +description: + The EcoNet High Precision Timer (HPT) is a timer peripheral found in various + EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE + count/compare registers and a per-CPU control register, with a single interrupt + line using a percpu-devid interrupt mechanism. + +properties: + compatible: + oneOf: + - const: econet,en751221-timer + - items: + - const: econet,en751627-timer + - const: econet,en751221-timer + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + description: A percpu-devid timer interrupt shared across CPUs. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: econet,en751627-timer + then: + properties: + reg: + items: + - description: VPE timers 0 and 1 + - description: VPE timers 2 and 3 + else: + properties: + reg: + items: + - description: VPE timers 0 and 1 + +additionalProperties: false + +examples: + - | + timer@1fbf0400 { + compatible = "econet,en751627-timer", "econet,en751221-timer"; + reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; + - | + timer@1fbf0400 { + compatible = "econet,en751221-timer"; + reg = <0x1fbe0400 0x100>; + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; +... diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml new file mode 100644 index 000000000000..317c5010c4c1 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ezchip,nps400-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EZChip NPS400 Timers + +maintainers: + - Noam Camus <noamca@mellanox.com> + +properties: + compatible: + enum: + - ezchip,nps400-timer0 + - ezchip,nps400-timer1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: ezchip,nps400-timer0 + then: + required: [ interrupts ] + +examples: + - | + timer { + compatible = "ezchip,nps400-timer0"; + interrupts = <3>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt deleted file mode 100644 index e3cfce8fecc5..000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt +++ /dev/null @@ -1,17 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer0" - -Clocks required for compatible = "ezchip,nps400-timer0": -- interrupts : The interrupt of the first timer -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer0"; - interrupts = <3>; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt deleted file mode 100644 index c0ab4190b8fb..000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt +++ /dev/null @@ -1,15 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer1" - -Clocks required for compatible = "ezchip,nps400-timer1": -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer1"; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.txt b/Documentation/devicetree/bindings/timer/fsl,gtm.txt deleted file mode 100644 index fc1c571f7412..000000000000 --- a/Documentation/devicetree/bindings/timer/fsl,gtm.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale General-purpose Timers Module - -Required properties: - - compatible : should be - "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs - "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs - "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs - - reg : should contain gtm registers location and length (0x40). - - interrupts : should contain four interrupts. - - clock-frequency : specifies the frequency driving the timer. - -Example: - -timer@500 { - compatible = "fsl,mpc8360-gtm", "fsl,gtm"; - reg = <0x500 0x40>; - interrupts = <90 8 78 8 84 8 72 8>; - interrupt-parent = <&ipic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; - -timer@440 { - compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; - reg = <0x440 0x40>; - interrupts = <12 13 14 15>; - interrupt-parent = <&qeic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.yaml b/Documentation/devicetree/bindings/timer/fsl,gtm.yaml new file mode 100644 index 000000000000..1f35f1ee0be2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,gtm.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,gtm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale General-purpose Timers Module + +maintainers: + - J. Neuschäfer <j.ne@posteo.net> + +properties: + compatible: + oneOf: + # for SoC GTMs + - items: + - enum: + - fsl,mpc8308-gtm + - fsl,mpc8313-gtm + - fsl,mpc8315-gtm + - fsl,mpc8360-gtm + - const: fsl,gtm + + # for QE GTMs + - items: + - enum: + - fsl,mpc8360-qe-gtm + - fsl,mpc8569-qe-gtm + - const: fsl,qe-gtm + - const: fsl,gtm + + # for CPM2 GTMs (no known examples) + - items: + # - enum: + # - fsl,<chip>-cpm2-gtm + - const: fsl,cpm2-gtm + - const: fsl,gtm + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for timer 1 (e.g. GTM1 or GTM5) + - description: Interrupt for timer 2 (e.g. GTM2 or GTM6) + - description: Interrupt for timer 3 (e.g. GTM3 or GTM7) + - description: Interrupt for timer 4 (e.g. GTM4 or GTM8) + + clock-frequency: true + +required: + - compatible + - reg + - interrupts + - clock-frequency + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + timer@500 { + compatible = "fsl,mpc8360-gtm", "fsl,gtm"; + reg = <0x500 0x40>; + interrupts = <90 IRQ_TYPE_LEVEL_LOW>, + <78 IRQ_TYPE_LEVEL_LOW>, + <84 IRQ_TYPE_LEVEL_LOW>, + <72 IRQ_TYPE_LEVEL_LOW>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + - | + timer@440 { + compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; + reg = <0x440 0x40>; + interrupts = <12>, <13>, <14>, <15>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml new file mode 100644 index 000000000000..bee2c35bd0e2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,vf610-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Periodic Interrupt Timer (PIT) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The PIT module is an array of timers that can be used to raise interrupts + and trigger DMA channels. + +properties: + compatible: + enum: + - fsl,vf610-pit + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pit + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/vf610-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + + timer@40037000 { + compatible = "fsl,vf610-pit"; + reg = <0x40037000 0x1000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_PIT>; + clock-names = "pit"; + }; diff --git a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt deleted file mode 100644 index 7afce80bf6a0..000000000000 --- a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Pistachio general-purpose timer based clocksource - -Required properties: - - compatible: "img,pistachio-gptimer". - - reg: Address range of the timer registers. - - interrupts: An interrupt for each of the four timers - - clocks: Should contain a clock specifier for each entry in clock-names - - clock-names: Should contain the following entries: - "sys", interface clock - "slow", slow counter clock - "fast", fast counter clock - - img,cr-periph: Must contain a phandle to the peripheral control - syscon node. - -Example: - timer: timer@18102000 { - compatible = "img,pistachio-gptimer"; - reg = <0x18102000 0x100>; - interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, - <&clk_periph PERIPH_CLK_COUNTER_SLOW>, - <&cr_periph SYS_CLK_TIMER>; - clock-names = "fast", "slow", "sys"; - img,cr-periph = <&cr_periph>; - }; diff --git a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml new file mode 100644 index 000000000000..a8654bcf68a9 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/img,pistachio-gptimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pistachio general-purpose timer + +maintainers: + - Ezequiel Garcia <ezequiel.garcia@imgtec.com> + +properties: + compatible: + const: img,pistachio-gptimer + + reg: + maxItems: 1 + + interrupts: + items: + - description: Timer0 interrupt + - description: Timer1 interrupt + - description: Timer2 interrupt + - description: Timer3 interrupt + + clocks: + items: + - description: Fast counter clock + - description: Slow counter clock + - description: Interface clock + + clock-names: + items: + - const: fast + - const: slow + - const: sys + + img,cr-periph: + description: Peripheral control syscon phandle + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - img,cr-periph + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/clock/pistachio-clk.h> + + timer@18102000 { + compatible = "img,pistachio-gptimer"; + reg = <0x18102000 0x100>; + interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, + <&clk_periph PERIPH_CLK_COUNTER_SLOW>, + <&cr_periph SYS_CLK_TIMER>; + clock-names = "fast", "slow", "sys"; + img,cr-periph = <&cr_periph>; + }; diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt deleted file mode 100644 index af5dd35469d7..000000000000 --- a/Documentation/devicetree/bindings/timer/jcore,pit.txt +++ /dev/null @@ -1,24 +0,0 @@ -J-Core Programmable Interval Timer and Clocksource - -Required properties: - -- compatible: Must be "jcore,pit". - -- reg: Memory region(s) for timer/clocksource registers. For SMP, - there should be one region per cpu, indexed by the sequential, - zero-based hardware cpu number. - -- interrupts: An interrupt to assign for the timer. The actual pit - core is integrated with the aic and allows the timer interrupt - assignment to be programmed by software, but this property is - required in order to reserve an interrupt number that doesn't - conflict with other devices. - - -Example: - -timer@200 { - compatible = "jcore,pit"; - reg = < 0x200 0x30 0x500 0x30 >; - interrupts = < 0x48 >; -}; diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.yaml b/Documentation/devicetree/bindings/timer/jcore,pit.yaml new file mode 100644 index 000000000000..9e6e25b75293 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/jcore,pit.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/jcore,pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: J-Core Programmable Interval Timer and Clocksource + +maintainers: + - Rich Felker <dalias@libc.org> + +properties: + compatible: + const: jcore,pit + + reg: + description: + Memory region(s) for timer/clocksource registers. For SMP, there should be + one region per cpu, indexed by the sequential, zero-based hardware cpu + number. + + interrupts: + description: + An interrupt to assign for the timer. The actual pit core is integrated + with the aic and allows the timer interrupt assignment to be programmed by + software, but this property is required in order to reserve an interrupt + number that doesn't conflict with other devices. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@200 { + compatible = "jcore,pit"; + reg = <0x200 0x30 0x500 0x30>; + interrupts = <0x48>; + }; diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt deleted file mode 100644 index b2d07ad90e9a..000000000000 --- a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt +++ /dev/null @@ -1,33 +0,0 @@ -TI-NSPIRE timer - -Required properties: - -- compatible : should be "lsi,zevio-timer". -- reg : The physical base address and size of the timer (always first). -- clocks: phandle to the source clock. - -Optional properties: - -- interrupts : The interrupt number of the first timer. -- reg : The interrupt acknowledgement registers - (always after timer base address) - -If any of the optional properties are not given, the timer is added as a -clock-source only. - -Example: - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; - interrupts = <19>; - clocks = <&timer_clk>; -}; - -Example (no clock-events): - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>; - clocks = <&timer_clk>; -}; diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml new file mode 100644 index 000000000000..358455d8e7a8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/lsi,zevio-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE timer + +maintainers: + - Daniel Tang <dt.tangr@gmail.com> + +properties: + compatible: + const: lsi,zevio-timer + + reg: + minItems: 1 + items: + - description: Timer registers + - description: Interrupt acknowledgement registers (optional) + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + required: [ interrupts ] + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + timer@900d0000 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; + interrupts = <19>; + clocks = <&timer_clk>; + }; + - | + timer@900d0000 { + compatible = "lsi,zevio-timer"; + reg = <0x900D0000 0x1000>; + clocks = <&timer_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml new file mode 100644 index 000000000000..bc0677fe86eb --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,armada-370-timer.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/marvell,armada-370-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370, 375, 380 and XP Timers + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + oneOf: + - items: + - const: marvell,armada-380-timer + - const: marvell,armada-xp-timer + - items: + - const: marvell,armada-375-timer + - const: marvell,armada-370-timer + - enum: + - marvell,armada-370-timer + - marvell,armada-xp-timer + + reg: + items: + - description: Global timer registers + - description: Local/private timer registers + + interrupts: + items: + - description: Global timer interrupt 0 + - description: Global timer interrupt 1 + - description: Global timer interrupt 2 + - description: Global timer interrupt 3 + - description: First private timer interrupt + - description: Second private timer interrupt + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: nbclk + - const: fixed + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-375-timer + - marvell,armada-xp-timer + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +examples: + - | + timer@20300 { + compatible = "marvell,armada-xp-timer"; + reg = <0x20300 0x30>, <0x21040 0x30>; + interrupts = <37>, <38>, <39>, <40>, <5>, <6>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt deleted file mode 100644 index e9c78ce880e6..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt +++ /dev/null @@ -1,44 +0,0 @@ -Marvell Armada 370 and Armada XP Timers ---------------------------------------- - -Required properties: -- compatible: Should be one of the following - "marvell,armada-370-timer", - "marvell,armada-375-timer", - "marvell,armada-xp-timer". -- interrupts: Should contain the list of Global Timer interrupts and - then local timer interrupts -- reg: Should contain location and length for timers register. First - pair for the Global Timer registers, second pair for the - local/private timers. - -Clocks required for compatible = "marvell,armada-370-timer": -- clocks : Must contain a single entry describing the clock input - -Clocks required for compatibles = "marvell,armada-xp-timer", - "marvell,armada-375-timer": -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "nbclk" (L2/coherency fabric clock), - "fixed" (Reference 25 MHz fixed-clock). - -Examples: - -- Armada 370: - - timer { - compatible = "marvell,armada-370-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>; - }; - -- Armada XP: - - timer { - compatible = "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt deleted file mode 100644 index cd1a0c256f94..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -Marvell Orion SoC timer - -Required properties: -- compatible: shall be "marvell,orion-timer" -- reg: base address of the timer register starting with TIMERS CONTROL register -- interrupts: should contain the interrupts for Timer0 and Timer1 -- clocks: phandle of timer reference clock (tclk) - -Example: - timer: timer { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml new file mode 100644 index 000000000000..f973afffa5ba --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/marvell,orion-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion SoC timer + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + const: marvell,orion-timer + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: Timer0 interrupt + - description: Timer1 interrupt + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; diff --git a/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml new file mode 100644 index 000000000000..b44b9794bb85 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nxp,s32g2-stm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP System Timer Module (STM) + +maintainers: + - Daniel Lezcano <daniel.lezcano@kernel.org> + +description: + The System Timer Module supports commonly required system and application + software timing functions. STM includes a 32-bit count-up timer and four + 32-bit compare channels with a separate interrupt source for each channel. + The timer is driven by the STM module clock divided by an 8-bit prescale + value. + +properties: + compatible: + oneOf: + - const: nxp,s32g2-stm + - items: + - const: nxp,s32g3-stm + - const: nxp,s32g2-stm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Counter clock + - description: Module clock + - description: Register clock + + clock-names: + items: + - const: counter + - const: module + - const: register + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@4011c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + }; diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml index 891cca009528..6b80b060672e 100644 --- a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml @@ -18,9 +18,14 @@ description: | properties: compatible: - enum: - - nxp,imx95-sysctr-timer - - nxp,sysctr-timer + oneOf: + - enum: + - nxp,imx95-sysctr-timer + - nxp,sysctr-timer + - items: + - enum: + - nxp,imx94-sysctr-timer + - const: nxp,imx95-sysctr-timer reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml index 9ba858f094ab..0983c1efec80 100644 --- a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five - renesas,r9a07g044-ostm # RZ/G2{L,LC} - renesas,r9a07g054-ostm # RZ/V2L + - renesas,r9a09g056-ostm # RZ/V2N - renesas,r9a09g057-ostm # RZ/V2H(P) - const: renesas,ostm # Generic @@ -54,12 +55,11 @@ required: if: properties: compatible: - contains: - enum: - - renesas,r9a07g043-ostm - - renesas,r9a07g044-ostm - - renesas,r9a07g054-ostm - - renesas,r9a09g057-ostm + not: + contains: + enum: + - renesas,r7s72100-ostm + - renesas,r7s9210-ostm then: required: - resets diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.yaml b/Documentation/devicetree/bindings/timer/renesas,tpu.yaml deleted file mode 100644 index 7a473b302775..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,tpu.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Renesas H8/300 Timer Pulse Unit - -maintainers: - - Yoshinori Sato <ysato@users.sourceforge.jp> - -description: - The TPU is a 16bit timer/counter with configurable clock inputs and - programmable compare match. - This implementation supports only cascade mode. - -select: - properties: - compatible: - contains: - const: renesas,tpu - '#pwm-cells': false - required: - - compatible - -properties: - compatible: - const: renesas,tpu - - reg: - items: - - description: First channel - - description: Second channel - - clocks: - maxItems: 1 - - clock-names: - const: fck - -required: - - compatible - - reg - - clocks - - clock-names - -additionalProperties: false - -examples: - - | - tpu: tpu@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&pclk>; - clock-names = "fck"; - }; diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 653e2e0ca878..d85a1a088b35 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - canaan,k210-clint # Canaan Kendryte K210 + - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 - starfive,jh7100-clint # StarFive JH7100 diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt deleted file mode 100644 index b02ab0af10ce..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt +++ /dev/null @@ -1,27 +0,0 @@ -Synopsys ARC Local Timer with Interrupt Capabilities -- Found on all ARC CPUs (ARC700/ARCHS) -- Can be optionally programmed to interrupt on Limit -- Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically - TIMER0 used as clockevent provider (true for all ARC cores) - TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) - -Required properties: - -- compatible : should be "snps,arc-timer" -- interrupts : single Interrupt going into parent intc - (16 for ARCHS cores, 3 for ARC700 cores) -- clocks : phandle to the source clock - -Example: - - timer0 { - compatible = "snps,arc-timer"; - interrupts = <3>; - interrupt-parent = <&core_intc>; - clocks = <&core_clk>; - }; - - timer1 { - compatible = "snps,arc-timer"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml b/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml new file mode 100644 index 000000000000..0d1e37db6f8e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,arc-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Local Timer + +maintainers: + - Vineet Gupta <vgupta@synopsys.com> + +description: > + Synopsys ARC Local Timer with Interrupt Capabilities + + - Found on all ARC CPUs (ARC700/ARCHS) + - Can be optionally programmed to interrupt on Limit + - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically + TIMER0 used as clockevent provider (true for all ARC cores) + TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) + +properties: + compatible: + const: snps,arc-timer + + interrupts: + maxItems: 1 + description: A single timer interrupt going into the parent interrupt controller. + Use <16> for ARCHS cores, <3> for ARC700 cores. + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + timer0 { + compatible = "snps,arc-timer"; + interrupts = <3>; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt deleted file mode 100644 index b6cd1b3922de..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs -- clocksource provider for SMP SoC - -Required properties: - -- compatible : should be "snps,archs-gfrc" -- clocks : phandle to the source clock - -Example: - - gfrc { - compatible = "snps,archs-gfrc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml new file mode 100644 index 000000000000..fb16f4aba1c5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-gfrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs + +maintainers: + - Vineet Gupta <vgupta@synopsys.com> + +properties: + compatible: + const: snps,archs-gfrc + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + timer { + compatible = "snps,archs-gfrc"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt deleted file mode 100644 index 47bd7a702f3f..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs -- clocksource provider for UP SoC - -Required properties: - -- compatible : should be "snps,archs-rtc" -- clocks : phandle to the source clock - -Example: - - rtc { - compatible = "snps,arc-rtc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml b/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml new file mode 100644 index 000000000000..7478810eb24a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/snps,archs-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs + +maintainers: + - Vineet Gupta <vgupta@synopsys.com> + +properties: + compatible: + const: snps,archs-rtc + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + rtc { + compatible = "snps,archs-rtc"; + clocks = <&core_clk>; + }; diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt deleted file mode 100644 index ac44c4b67530..000000000000 --- a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Milbeaut SoCs Timer Controller - -Required properties: - -- compatible : should be "socionext,milbeaut-timer". -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer. -- clocks: phandle to the input clk. - -Example: - -timer { - compatible = "socionext,milbeaut-timer"; - reg = <0x1e000050 0x20> - interrupts = <0 91 4>; - clocks = <&clk 4>; -}; diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml new file mode 100644 index 000000000000..9ab72b762314 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/socionext,milbeaut-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut SoCs Timer Controller + +maintainers: + - Sugaya Taichi <sugaya.taichi@socionext.com> + +properties: + compatible: + const: socionext,milbeaut-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer@1e000050 { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + clocks = <&clk 4>; + }; diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.txt b/Documentation/devicetree/bindings/timer/st,spear-timer.txt deleted file mode 100644 index b5238a07da17..000000000000 --- a/Documentation/devicetree/bindings/timer/st,spear-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -* SPEAr ARM Timer - -** Timer node required properties: - -- compatible : Should be: - "st,spear-timer" -- reg: Address range of the timer registers -- interrupt: Should contain the timer interrupt number - -Example: - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupts = <2>; - }; diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.yaml b/Documentation/devicetree/bindings/timer/st,spear-timer.yaml new file mode 100644 index 000000000000..9f26b5f2b38a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,spear-timer.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/st,spear-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPEAr ARM Timer + +maintainers: + - Viresh Kumar <vireshk@kernel.org> + - Shiraz Hashim <shiraz.linux.kernel@gmail.com> + +properties: + compatible: + const: st,spear-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml index 2e92bcdeb423..4ed30efe4052 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - sophgo,sg2042-aclint-mtimer + - sophgo,sg2044-aclint-mtimer - const: thead,c900-aclint-mtimer reg: diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt deleted file mode 100644 index d3905a5412b8..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Device tree bindings for Texas instruments Keystone timer - -This document provides bindings for the 64-bit timer in the KeyStone -architecture devices. The timer can be configured as a general-purpose 64-bit -timer, dual general-purpose 32-bit timers. When configured as dual 32-bit -timers, each half can operate in conjunction (chain mode) or independently -(unchained mode) of each other. - -It is global timer is a free running up-counter and can generate interrupt -when the counter reaches preset counter values. - -Documentation: -https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf - -Required properties: - -- compatible : should be "ti,keystone-timer". -- reg : specifies base physical address and count of the registers. -- interrupts : interrupt generated by the timer. -- clocks : the clock feeding the timer clock. - -Example: - -timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; - clocks = <&clktimer15>; -}; diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml b/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml new file mode 100644 index 000000000000..1caf5ce64f01 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ti,keystone-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone timer + +maintainers: + - Alexander A. Klimov <grandmaster@al2klimov.de> + - Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> + +description: > + A 64-bit timer in the KeyStone architecture devices. The timer can be + configured as a general-purpose 64-bit timer, dual general-purpose 32-bit + timers. When configured as dual 32-bit timers, each half can operate in + conjunction (chain mode) or independently (unchained mode) of each other. + + It is global timer is a free running up-counter and can generate interrupt + when the counter reaches preset counter values. + + Documentation: + https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf + +properties: + compatible: + const: ti,keystone-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: irq + + clocks: + maxItems: 1 + + clock-names: + items: + - const: timer + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = <110 IRQ_TYPE_EDGE_RISING>; + clocks = <&clktimer15>; + }; |