diff options
Diffstat (limited to 'arch/arm/boot/dts')
186 files changed, 9735 insertions, 1776 deletions
diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 0f0b5b707654..9adf9278dc94 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -39,6 +39,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-facebook-yosemite4.dtb \ + aspeed-bmc-facebook-yosemite5.dtb \ + aspeed-bmc-ibm-balcones.dtb \ aspeed-bmc-ibm-blueridge.dtb \ aspeed-bmc-ibm-bonnell.dtb \ aspeed-bmc-ibm-everest.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts index ecef44d89977..450446913e36 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -95,6 +95,11 @@ label = "bmc_ready_cpld_noled"; gpios = <&gpio0 ASPEED_GPIO(P, 5) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; }; + + led-hdd { + label = "hdd_led"; + gpios = <&io_expander13 1 GPIO_ACTIVE_LOW>; + }; }; memory@80000000 { @@ -642,12 +647,14 @@ power-monitor@12 { compatible = "ti,lm5066i"; reg = <0x12>; + shunt-resistor-micro-ohms = <183>; }; // PDB power-monitor@14 { compatible = "ti,lm5066i"; reg = <0x14>; + shunt-resistor-micro-ohms = <183>; }; // Module 0 @@ -1197,7 +1204,7 @@ #gpio-cells = <2>; gpio-line-names = "rmc_en_dc_pwr_on", - "", + "HDD_LED_N", "", "", "", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index b733efe31e8d..1c50e4a367b2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -240,6 +240,14 @@ &i2c1 { status = "okay"; + mctp-controller; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + temperature-sensor@4b { compatible = "ti,tmp75"; reg = <0x4b>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts index 72c84f31bdf6..f74f463cc878 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts @@ -39,6 +39,38 @@ i2c37 = &i2c12mux0ch5; i2c38 = &i2c12mux0ch6; i2c39 = &i2c12mux0ch7; + i2c48 = &i2c6mux0ch0; + i2c49 = &i2c6mux0ch1; + i2c50 = &i2c6mux0ch2; + i2c51 = &i2c6mux0ch3; + i2c52 = &i2c8mux0ch0; + i2c53 = &i2c8mux0ch1; + i2c54 = &i2c8mux0ch2; + i2c55 = &i2c8mux0ch3; + i2c56 = &i2c10mux0ch0; + i2c57 = &i2c10mux0ch1; + i2c58 = &i2c10mux0ch2; + i2c59 = &i2c10mux0ch3; + i2c60 = &i2c13mux0ch0; + i2c61 = &i2c13mux0ch1; + i2c62 = &i2c13mux0ch2; + i2c63 = &i2c13mux0ch3; + i2c64 = &i2c6mux1ch0; + i2c65 = &i2c6mux1ch1; + i2c66 = &i2c6mux1ch2; + i2c67 = &i2c6mux1ch3; + i2c68 = &i2c8mux1ch0; + i2c69 = &i2c8mux1ch1; + i2c70 = &i2c8mux1ch2; + i2c71 = &i2c8mux1ch3; + i2c72 = &i2c10mux1ch0; + i2c73 = &i2c10mux1ch1; + i2c74 = &i2c10mux1ch2; + i2c75 = &i2c10mux1ch3; + i2c76 = &i2c13mux1ch0; + i2c77 = &i2c13mux1ch1; + i2c78 = &i2c13mux1ch2; + i2c79 = &i2c13mux1ch3; }; chosen { @@ -72,6 +104,11 @@ default-state = "off"; gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; }; + + led-3 { + label = "bmc_ready_noled"; + gpios = <&gpio0 ASPEED_GPIO(B, 3) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; + }; }; memory@80000000 { @@ -171,7 +208,7 @@ "led-postcode-2","led-postcode-3", "led-postcode-4","led-postcode-5", "led-postcode-6","led-postcode-7", - /*O0-O7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","debug-card-mux", /*P0-P7*/ "power-button","","reset-button","", "led-power","","","", /*Q0-Q7*/ "","","","","","","","", @@ -292,6 +329,20 @@ }; }; +&i2c3 { + status = "okay"; + + sbrmi@3c { + compatible = "amd,sbrmi"; + reg = <0x3c>; + }; + + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; +}; + &i2c4 { status = "okay"; @@ -319,16 +370,19 @@ reg = <0x53>; }; }; + i2c4mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -380,16 +434,19 @@ reg = <0x4e>; }; }; + i2c4mux0ch4: i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch5: i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch6: i2c@6 { reg = <6>; #address-cells = <1>; @@ -424,6 +481,7 @@ reg = <0x48>; }; }; + i2c4mux0ch7: i2c@7 { reg = <7>; #address-cells = <1>; @@ -469,16 +527,19 @@ #address-cells = <1>; #size-cells = <0>; }; + i2c5mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; + i2c5mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; + i2c5mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -503,6 +564,7 @@ reg = <0x48>; }; }; + i2c5mux1ch1: i2c@1 { reg = <1>; #address-cells = <1>; @@ -513,6 +575,7 @@ reg = <0x48>; }; }; + i2c5mux1ch2: i2c@2 { reg = <2>; #address-cells = <1>; @@ -542,6 +605,7 @@ shunt-resistor = <2000>; }; }; + i2c5mux1ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -574,6 +638,210 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c6mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c6mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c6mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c6mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c6mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c6mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c7 { @@ -588,6 +856,210 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c8mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c8mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c8mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c8mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c8mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c9 { @@ -604,6 +1076,11 @@ reg = <0x50>; }; + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + // BSM FRU eeprom@56 { compatible = "atmel,24c64"; @@ -619,11 +1096,222 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c10mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c10mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c10mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c10mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c10mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c10mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c11 { + multi-master; + mctp-controller; status = "okay"; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + // OCP NIC TEMP temperature-sensor@1f { compatible = "ti,tmp421"; @@ -663,6 +1351,7 @@ reg = <0x48>; }; }; + i2c12mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; @@ -678,6 +1367,7 @@ reg = <0x43>; }; }; + i2c12mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; @@ -695,6 +1385,7 @@ shunt-resistor = <2000>; }; }; + i2c12mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -712,6 +1403,7 @@ shunt-resistor = <2000>; }; }; + i2c12mux0ch4: i2c@4 { reg = <4>; #address-cells = <1>; @@ -722,16 +1414,19 @@ reg = <0x49>; }; }; + i2c12mux0ch5: i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; }; + i2c12mux0ch6: i2c@6 { reg = <6>; #address-cells = <1>; #size-cells = <0>; }; + i2c12mux0ch7: i2c@7 { reg = <7>; #address-cells = <1>; @@ -748,6 +1443,210 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c13mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c13mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c13mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c13mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c13mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c13mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c14 { @@ -864,7 +1763,9 @@ "FM_IOEXP_U541_INT_N","", /*H4-H7 line 120-127*/ "FM_IOEXP_PDB2_U1003_INT_N","", - "","","","","","", + "","", + "","", + "FM_MAIN_PWREN_RMC_EN_ISO_R","", /*I0-I3 line 128-135*/ "","","","", "PDB_IRQ_PMBUS_ALERT_ISO_R_N","", @@ -873,7 +1774,7 @@ "P12V_SCM_ADC_ALERT","", "CPU0_REGS_I2C_ALERT_N","", "FM_RTC_ALERT_N","", - "APML_CPU0_ALERT_R_N","", + "P0_I3C_APML_ALERT_L","", /*J0-J3 line 144-151*/ "SMB_RJ45_FIO_TMP_ALERT","", "FM_SMB_ALERT_MCIO_0A_N","", @@ -924,11 +1825,17 @@ "PRSNT_LEAK_CABLE_1_R_N","", "PRSNT_LEAK_CABLE_2_R_N","", "PRSNT_HDT_N","", - "","", + "LEAK_SWB_COLDPLATE","", /*P0-P3 line 240-247*/ - "","","","","","","","", + "LEAK_R3_COLDPLATE","", + "LEAK_R2_COLDPLATE","", + "LEAK_R1_COLDPLATE","", + "LEAK_R0_COLDPLATE","", /*P4-P7 line 248-255*/ - "","","","","","","",""; + "LEAK_MB_COLDPLATE","", + "LEAK_PDB1_RIGHT_MANIFOLD","", + "LEAK_PDB1_LEFT_MANIFOLD","", + "LEAK_MB_MANIFOLD",""; status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts index 60b98d602e80..e4172be84e7f 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts @@ -49,6 +49,20 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + ramoops@b8dfa000 { + compatible = "ramoops"; + reg = <0xb8dfa000 0x6000>; + record-size = <0x2000>; + console-size = <0x2000>; + pmsg-size = <0x2000>; + max-reason = <1>; + }; + }; + iio-hwmon { compatible = "iio-hwmon"; io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts new file mode 100644 index 000000000000..2486981f3d6b --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts @@ -0,0 +1,1067 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2025 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "Facebook Yosemite 5 BMC"; + compatible = "facebook,yosemite5-bmc", "aspeed,ast2600"; + + aliases { + i2c16 = &i2c5mux0ch0; + i2c17 = &i2c5mux0ch1; + i2c18 = &i2c5mux0ch2; + i2c19 = &i2c5mux0ch3; + i2c20 = &i2c5mux1ch0; + i2c21 = &i2c5mux1ch1; + i2c22 = &i2c5mux1ch2; + i2c23 = &i2c5mux1ch3; + i2c24 = &i2c6mux0ch0; + i2c25 = &i2c6mux0ch1; + i2c26 = &i2c6mux0ch2; + i2c27 = &i2c6mux0ch3; + i2c28 = &i2c8mux0ch0; + i2c29 = &i2c8mux0ch1; + i2c30 = &i2c8mux0ch2; + i2c31 = &i2c8mux0ch3; + i2c32 = &i2c30mux0ch0; + i2c33 = &i2c30mux0ch1; + i2c34 = &i2c30mux0ch2; + i2c35 = &i2c30mux0ch3; + serial0 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "fp_id_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "power_blue"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default>; + status = "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc10_default>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BATTERY_DETECT","","BMC_I2C1_FPGA_ALERT","BMC_READY", + "IOEXP_INT_3V3","FM_ID_LED","","", + /*C0-C7*/ "","","","", + "PMBUS_REQ_N","PSU_FW_UPDATE_REQ_N","","BMC_I2C_SSIF_ALERT", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "FM_BMC_MUX1_SEL","","","", + "","","FM_DEBUG_PORT_PRSNT_N","FM_BMC_DBP_PRESENT_N", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","FLASH_WP_STATUS","BMC_JTAG_MUX_SEL","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "PCIE_EP_RST_EN","BMC_FRU_WP","SCM_HPM_STBY_RST_N", + "SCM_HPM_STBY_EN","STBY_POWER_PG_3V3","TH500_SHDN_OK","","", + /*N0-N7*/ "led-postcode-0","led-postcode-1","led-postcode-2", + "led-postcode-3","led-postcode-4","led-postcode-5", + "led-postcode-6","led-postcode-7", + /*O0-O7*/ "RUN_POWER_PG","PWR_BRAKE","CHASSIS_AC_LOSS","BSM_PRSNT_N", + "PSU_SMB_ALERT","FM_TPM_PRSNT_0_N","PSU_FW_UPDATING_N","", + /*P0-P7*/ "PWR_BTN_BMC_N","IPEX_CABLE_PRSNT","ID_RST_BTN_BMC_N", + "RST_BMC_RSTBTN_OUT_N","BMC_PWR_LED","RUN_POWER_EN","SHDN_FORCE","", + /*Q0-Q7*/ "IRQ_PCH_TPM_SPI_LV3_N","USB_OC0_REAR_N","UART_MUX_SEL", + "I2C_MUX_RESET","RSVD_NV_PLT_DETECT","SPI_TPM_INT", + "CPU_JTAG_MUX_SELECT","THERM_BB_OVERT", + /*R0-R7*/ "THERM_BB_WARN","SPI_BMC_FPGA_INT","CPU_BOOT_DONE","PMBUS_GNT", + "CHASSIS_PWR_BRK","PCIE_WAKE","PDB_THERM_OVERT","SHDN_REQ", + /*S0-S7*/ "","","SYS_BMC_PWRBTN_N","FM_TPM_PRSNT_1_N", + "FM_BMC_DEBUG_SW_N","UID_LED_N","SYS_FAULT_LED_N","RUN_POWER_FAULT", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "FM_DBP_BMC_PRDY_N","","","","","","","", + /*V0-V7*/ "L2_RST_REQ_OUT","L0L1_RST_REQ_OUT","BMC_ID_BEEP_SEL", + "BMC_I2C0_FPGA_ALERT","SMB_BMC_TMP_ALERT","PWR_LED_N", + "SYS_RST_OUT","IRQ_TPM_SPI_N", + /*W0-W7*/ "","","","","","","IRQ_ESPI_LPC_SERIRQ_ALERT0_N","", + /*X0-X7*/ "","FM_DBP_CPU_PREQ_GF_N","","","","","","", + /*Y0-Y7*/ "","","FM_FLASH_LATCH_N","BMC_EMMC_RST_N","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","FM_BOARD_BMC_REV_ID0", + "FM_BOARD_BMC_REV_ID1","FM_BOARD_BMC_REV_ID2","", + /*18C0-18C7*/ "","","SPI_BMC_BIOS_ROM_IRQ0_N","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "FM_BMC_PROT_LS_EN","AC_PWR_BMC_BTN_N","",""; +}; + +/* MB CPLD I2C */ +&i2c0 { + status = "okay"; +}; + +/* CPU I2C */ +&i2c1 { + status = "okay"; +}; + +/* MCIO 2A I2C */ +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + /* Socket 0 SBRMI */ + sbrmi@3c { + compatible = "amd,sbrmi"; + reg = <0x3c>; + }; + + /* Socket 0 SBTSI */ + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; +}; + +&i2c4 { + multi-master; + mctp-controller; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + /* OCP NIC TEMP */ + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + + /* OCP NIC FRU EEPROM */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c5 { + status = "okay"; + + /* I2C MUX for MCIO 1A */ + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + /* I2C MUX for MCIO 0A */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + /* I2C MUX for PWRPIC #13 ~ #16 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #13 */ + i2c6mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #14 */ + i2c6mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #16 */ + i2c6mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #15 */ + i2c6mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* SCM CPLD I2C */ +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + power-monitor@14 { + compatible = "infineon,xdp710"; + reg = <0x14>; + }; + + adc@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + power-sensor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + /* PADDLE BD IOEXP */ + gpio-expander@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "HSC_OC_GPIO0", "HSC_OC_GPIO1", + "HSC_OC_GPIO2", "HSC_OC_GPIO3"; + }; + + power-sensor@42 { + compatible = "ti,ina238"; + reg = <0x42>; + shunt-resistor = <1000>; + }; + + power-monitor@43 { + compatible = "lltc,ltc4287"; + reg = <0x43>; + shunt-resistor-micro-ohms = <250>; + }; + + power-sensor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-sensor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + power-monitor@47 { + compatible = "ti,tps25990"; + reg = <0x47>; + ti,rimon-micro-ohms = <430000000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + /* PDB FRU */ + eeprom@56 { + compatible = "atmel,24c128"; + reg = <0x56>; + }; + + /* Paddle BD FRU */ + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + }; + + power-monitor@58 { + compatible = "renesas,isl28022"; + reg = <0x58>; + shunt-resistor-micro-ohms = <1000>; + }; + + power-monitor@59 { + compatible = "renesas,isl28022"; + reg = <0x59>; + shunt-resistor-micro-ohms = <1000>; + }; + + power-monitor@5a { + compatible = "renesas,isl28022"; + reg = <0x5a>; + shunt-resistor-micro-ohms = <1000>; + }; + + power-monitor@5b { + compatible = "renesas,isl28022"; + reg = <0x5b>; + shunt-resistor-micro-ohms = <1000>; + }; + + psu@5c { + compatible = "renesas,raa228006"; + reg = <0x5c>; + }; + + fan-controller@5e{ + compatible = "maxim,max31790"; + reg = <0x5e>; + }; + + /* I2C MUX for PWRPIC #1, #2, #11, #12 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #1 */ + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #2 */ + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #12 (Connector to CXL BD) */ + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c30mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c30mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c30mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1e { + compatible = "ti,adc128d818"; + reg = <0x1e>; + ti,mode = /bits/ 8 <1>; + }; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + + /* CXL BD IOEXP */ + gpio-expander@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "IRQ_TEMP_0_ALERT_N","IRQ_TEMP_1_ALERT_N", + "ALERT_PMBUS_0_N","ALERT_PMBUS_1_N", + "ALERT_PMBUS_2_N","IRQ_INA230_12V_ALERT_N", + "RST_IOX_CXL_N","DEBUG_UART_SEL_0", + "DEBUG_UART_SEL_1","BMC_REMOTEJTAG_EN_N", + "JTAG_BMC_3V3_CTL_CLR_N","DDR_CH02_I2C_MUX_SEL", + "DDR_CH13_I2C_MUX_SEL","SYS_OK", + "CXL_VRHOT_ALERT_R1_N",""; + }; + + temperature-sensor@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp432"; + reg = <0x4c>; + }; + + power-sensor@4d { + compatible = "ti,ina230"; + reg = <0x4d>; + shunt-resistor = <2000>; + }; + + temperature-sensor@4e { + compatible = "ti,tmp75"; + reg = <0x4e>; + }; + + /* CXL FRU */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c30mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* PWRPIC #11 */ + i2c8mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c9 { + status = "okay"; + + temperature-sensor@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + + /* SCM FRU */ + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + /* BSM FRU */ + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +/* MCIO 0A I2C */ +&i2c10 { + status = "okay"; + + /* E1S EB IOEXP0 */ + gpio-expander@21 { + compatible = "nxp,pca9535"; + interrupt-parent = <&sgpiom0>; + interrupts = <172 IRQ_TYPE_EDGE_FALLING>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "RST_SMB_E1S_0","LED_ACTIVE_E1S_0", + "E1S_0_PRSNT_N","RST_PCIE_E1S_0_PERST", + "E1S_0_PWRDIS","ALERT_INA_0", + "","", + "RST_SMB_E1S_1","LED_ACTIVE_E1S_1", + "E1S_1_PRSNT_N","RST_PCIE_E1S_1_PERST", + "E1S_1_PWRDIS","ALERT_INA_1", + "",""; + }; + + /* E1S EB IOEXP1 */ + gpio-expander@22 { + compatible = "nxp,pca9535"; + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_EDGE_FALLING>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "P12V_E1S_EN_0","PWRGD_P12V_E1S_0", + "P12V_E1S_FLTB_0","PWRGD_P3V3_E1S_0", + "FM_P3V3_E1S_0_FAULT","P12V_E1S_EN_1", + "PWRGD_P12V_E1S_1","P12V_E1S_FLTB_1", + "PWRGD_P3V3_E1S_1","FM_P3V3_E1S_1_FAULT", + "","", + "","", + "PWRGD_P3V3_AUX","ALERT_TEMP"; + }; + + power-sensor@40 { + compatible = "ti,ina233"; + reg = <0x40>; + shunt-resistor = <2000>; + ti,maximum-expected-current-microamp = <32768000>; + }; + + power-sensor@45 { + compatible = "ti,ina233"; + reg = <0x45>; + shunt-resistor = <2000>; + ti,maximum-expected-current-microamp = <32768000>; + }; + + adc@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + /* E1S EB FRU */ + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c11 { + status = "okay"; + + /* MB IOEXP */ + gpio-expander@21 { + compatible = "nxp,pca9535"; + interrupt-parent = <&sgpiom0>; + interrupts = <170 IRQ_TYPE_EDGE_FALLING>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "ALERT_CLKMUX_0_LOSS_N","ALERT_CLKMUX_1_LOSS_N", + "ALERT_CLKMUX_2_LOSS_N","ALERT_CLKMUX_3_LOSS_N", + "FM_CLKMUX_0_SEL","FM_CLKMUX_1_SEL", + "FM_CLKMUX_2_SEL","FM_CLKMUX_3_SEL", + "RST_USB_HUB_0_N","FM_CLKGEN_GPIO2", + "","FM_BMC_RTC_RST", + "FM_P3V_BAT_SCALED_EN","", + "FM_CLKGEN_GPIO4","RST_USB_HUB_1_N"; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + + power-sensor@42 { + compatible = "ti,ina230"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + + power-sensor@43 { + compatible = "ti,ina230"; + reg = <0x43>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + adc@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + adc@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + adc@4b { + compatible = "ti,ads7830"; + reg = <0x4b>; + }; +}; + +/* MCIO 4A I2C */ +&i2c12 { + multi-master; + mctp-controller; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; +}; + +&i2c13 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + temperature-sensor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "national,lm75b"; + reg = <0x49>; + }; + + /* CLKGEN FRU */ + eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + }; + + /* MB FRU */ + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + /* CPU FRU */ + eeprom@53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +/* PROT reserve */ +&i2c14 { + status = "okay"; +}; + +/* MCIO 3A I2C */ +&i2c15 { + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + status = "okay"; +}; + +&mac2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; + status = "okay"; +}; + +&pinctrl { + pinctrl_ncsi3_default: ncsi3_default { + function = "RMII3"; + groups = "NCSI3"; + }; +}; + +&sgpiom0 { + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*"input pin","output pin"*/ + /*bit0-bit7*/ + "PWRGD_CPU_PWROK","SGPIO_RSTBTN_OUT", + "PWRGD_CPU_PWROK_1","SGPIO_BMC_READY", + "PWRGD_CPU_PWROK_2","IBB_BMC_SRST", + "host0-ready","FM_I3C_SPD_AH_SEL_R", + "PCIe_HP_BOOT","FM_I3C_SPD_IP_SEL_R", + "PCIe_HP_DATA","FM_JTAG_BMC_MUX_S0_R", + "PCIe_HP_NIC","FM_JTAG_BMC_MUX_S1_R", + "","FM_JTAG_BMC_OE_1_R_N", + /*bit8-bit15*/ + "PWRGD_PVDDCR_CPU0_P0","FM_JTAG_BMC_OE_R_N", + "PWRGD_PVDDCR_SOC_P0","FM_REMOTEJTAG_EN_R_N", + "PWRGD_PVDDCR_CPU1_P0","FM_CPU_FORCE_SELFREFRESH_R", + "PWRGD_P3V3_STBY","FM_CPU_NMI_SYNC_FLOOD_R_N", + "PWRGD_PVDD33_S5","FM_CPU_TRIGGERTSC_OE_R_N", + "PWRGD_PVDD18_S5_P0","FM_PASSWORD_CLEAR_R_N", + "PWRGD_PVDDIO_P0","FM_BIOS_USB_RECOVERY_N", + "PWRGD_PVDDIO_MEM_S3_P0","FM_USB_MUX_OE_R_N", + /*bit16-bit23*/ + "PWRGD_P1V8_STBY","FM_USB_MUX_SEL_R", + "PWRGD_P1V0_STBY","RST_SMB_BOOT_R_N", + "PWRGD_P1V2_STBY","RST_SMB_MCIO0A_R_N", + "IBB_BMC_SRST","RST_SMB_NIC_R_N", + "PWRGD_P12V_E1S_0","FM_PPS_NIC_IN_BUF_OE_R_N", + "PWRGD_P12V_E1S_1","FM_PPS_NIC_IN_EN_R", + "RST_PCIE_BOOT_PERST_N","FM_PPS_NIC_IN_OE_R_N", + "PWRGD_P12V_NIC","FM_PPS_NIC_IN_S0_R", + /*bit24-bit31*/ + "PWRGD_P12V_SCM","FM_PPS_NIC_IN_S1_R", + "PWRGD_P12V_DIMM","FM_PPS_NIC_OUT_BUF_OE_R_N", + "PWRGD_CPU_DIMM0_AH","FM_PPS_NIC_OUT_CPU_OE_R_N", + "PWRGD_CPU_DIMM1_IP","FM_PPS_NIC_OUT_EN_R", + "PWRGD_NIC_CPLD","JTAG_CPLD_DBREQ_R_N", + "ALERT_INA230_DIMM_0_N","HDT_HDR_RESET_R_N", + "ALERT_INA230_DIMM_1_N","FM_SMB_AUTH_MUX_OE_R_N", + "ALERT_INA230_E1S_0_N","FM_SCM_LED_R_N", + /*bit32-bit39*/ + "ALERT_INA230_E1S_1_N","", + "ALERT_INA230_FAN0_N","", + "ALERT_INA230_FAN1_N","", + "ALERT_INA230_FAN2_N","", + "ALERT_INA230_FAN3_N","", + "ALERT_INA230_NIC_N","", + "ALERT_INA230_SCM_N","", + "ALERT_IRQ_PMBUS_PWR11_N","", + /*bit40-bit47*/ + "ALERT_MCIO2A_LEAK_DETECT_N","", + "ALERT_MCIO3A_LEAK_DETECT_N","", + "ALERT_MCIO4A_LEAK_DETECT_N","", + "ALERT_OC_PADDLE2_N","", + "ALERT_OC_PWR2_N","", + "ALERT_OC_PWR11_N","", + "ALERT_PADDLE2_SMB_N","", + "ALERT_PWR14_SB2_LEAK_DETECT_N","", + /*bit48-bit55*/ + "ALERT_PWR14_SB3_LEAK_DETECT_N","", + "ALERT_PWR15_SB2_LEAK_DETECT_N","", + "ALERT_PWR15_SB3_LEAK_DETECT_N","", + "ALERT_SMB_MCIO0A_N","", + "ALERT_SMB_MCIO1A_N","", + "ALERT_SMB_MCIO2A_N","", + "ALERT_SMB_MCIO2B_N","", + "ALERT_SMB_MCIO3A_N","", + /*bit56-bit63*/ + "ALERT_SMB_MCIO3B_N","", + "ALERT_SMB_MCIO4A_N","", + "ALERT_SMB_MCIO4B_N","", + "ALERT_THERMALTRIP_MCIO1A_N","", + "ALERT_THERMALTRIP_MCIO2A_N","", + "ALERT_THERMALTRIP_MCIO3A_N","", + "ALERT_THERMALTRIP_MCIO4A_N","", + "ALERT_UV_PADDLE2_N","", + /*bit64-bit71*/ + "ALERT_UV_PWR2_N","", + "ALERT_UV_PWR11_N","", + "ALERT_VR_SMB_N","", + "FAULT_FAN_0_N","", + "FAULT_FAN_1_N","", + "FAULT_FAN_2_N","", + "FAULT_FAN_3_N","", + "FAULT_P3V3_E1S_0_N","", + /*bit72-bit79*/ + "FAULT_P3V3_E1S_1_N","", + "FAULT_P3V3_NIC_N","", + "FAULT_P12V_NIC_N","", + "FAULT_P12V_SCM_N","", + "P0_I3C_APML_ALERT_L","", + "ALERT_INLET_TEMP_N","", + "FM_CPU_PROCHOT_R_N","", + "FM_CPU_THERMTRIP_N","", + /*bit80-bit87*/ + "ALERT_OUTLET_TEMP_N","", + "ALERT_RTC_N","", + "PVDDCR_CPU0_P0_OCP_N","", + "PVDDCR_CPU1_P0_OCP_N","", + "PVDDCR_SOC_P0_OCP_N","", + "MB_IOEXP_INT","", + "E1S_0_BD_IOEXP","", + "E1S_1_BD_IOEXP","", + /*bit88-bit95*/ + "PADDLE_BD_IOEXP_INT","", + "FM_BOARD_REV_ID0","", + "FM_BOARD_REV_ID1","", + "FM_BOARD_REV_ID2","", + "FM_VR_TYPE_ID0","", + "FM_VR_TYPE_ID1","", + "PRSNT_BOOT_N_IOEXP","", + "PRSNT_DATA_N_IOEXP","", + /*bit96-bit103*/ + "PRSNT_NIC_N_IOEXP","", + "PRSNT_BOOT_N_FF","", + "PRSNT_MCIO1A_N_FF","", + "NIC_PRSNT_N","", + "","", + "","", + "","", + "","", + /*bit104-bit111*/ + "","","","","","","","","","","","","","","","", + /*bit112-bit119*/ + "","","","","","","","","","","","","","","","", + /*bit120-bit127*/ + "","","","","","","","","","","","","","","",""; + status = "okay"; +}; + +/* BIOS Flash */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + status = "okay"; + + flash@0 { + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <12000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + status = "okay"; + }; +}; + +/* Host Console */ +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +/* SOL */ +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +/* BMC Console */ +&uart5 { + status = "okay"; +}; + +&wdt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-balcones.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-balcones.dts new file mode 100644 index 000000000000..63fcb7a7619a --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-balcones.dts @@ -0,0 +1,609 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2025 IBM Corp. +/dts-v1/; + +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> +#include <dt-bindings/leds/leds-pca955x.h> +#include "aspeed-g6.dtsi" +#include "ibm-power11-dual.dtsi" + +/ { + model = "Balcones"; + compatible = "ibm,balcones-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + i2c16 = &i2c11mux0chn0; + i2c17 = &i2c11mux0chn1; + i2c18 = &i2c11mux0chn2; + i2c19 = &i2c11mux0chn3; + }; + + chosen { + stdout-path = &uart5; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + gpios = <&gpio0 ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; + label = "fan0-presence"; + linux,code = <6>; + }; + + event-fan1-presence { + gpios = <&gpio0 ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>; + label = "fan1-presence"; + linux,code = <7>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 7>; + }; + + leds { + compatible = "gpio-leds"; + + led-fan0 { + gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>; + }; + + led-fan1 { + gpios = <&gpio0 ASPEED_GPIO(G, 1) GPIO_ACTIVE_LOW>; + }; + + led-rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + led-rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + event_log: region@b3d00000 { + reg = <0xb3d00000 0x100000>; + no-map; + }; + + ramoops@b3e00000 { + compatible = "ramoops"; + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + reg = <0xb4000000 0x04000000>; /* 64M */ + no-map; + }; + + /* VGA region is dictated by hardware strapping */ + vga_memory: region@bf000000 { + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + no-map; + }; + }; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emmc { + clk-phase-mmc-hs200 = <180>, <180>; + status = "okay"; +}; + +&emmc_controller { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","checkstop","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","fan-ctlr-reset","rtc-battery-voltage-read-enable", + "reset-cause-pinhole","","","","", + /*G0-G7*/ "fan0","fan1","","","","","","", + /*H0-H7*/ "","","rear-enc-id0","rear-enc-fault0","","","","", + /*I0-I7*/ "","","","","","","bmc-secure-boot","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", + /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","", + "","","", + /*S0-S7*/ "presence-ps0","presence-ps1","","","power-ffs-sync-history","","", + "", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; + + usb-power-hog { + gpio-hog; + gpios = <ASPEED_GPIO(O, 3) GPIO_ACTIVE_LOW>; + output-high; + }; +}; + +&i2c0 { + status = "okay"; + + gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", + "RUSSEL_FW_I2C_ENABLE_N", + "RUSSEL_OPPANEL_PRESENCE_N", + "BLYTH_OPPANEL_PRESENCE_N", + "CPU_TPM_CARD_PRESENT_N", + "", + "", + "DASD_BP_PRESENT_N"; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + pmic@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c3 { + status = "okay"; + + power-supply@5a { + compatible = "acbel,fsg032"; + reg = <0x5a>; + }; + + power-supply@5b { + compatible = "acbel,fsg032"; + reg = <0x5b>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + led-controller@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + led@0 { + reg = <0>; + default-state = "keep"; + label = "cablecard2-cxp-top"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + reg = <1>; + default-state = "keep"; + label = "cablecard2-cxp-bot"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + }; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + multi-master; + status = "okay"; + + temperature-sensor@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pwm@53 { + compatible = "maxim,max31785a"; + reg = <0x53>; + }; + + led-controller@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + led@0 { + reg = <0>; + default-state = "keep"; + label = "front-sys-id0"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + reg = <1>; + default-state = "keep"; + label = "front-check-log0"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + reg = <2>; + default-state = "keep"; + label = "front-enc-fault1"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + reg = <3>; + default-state = "keep"; + label = "front-sys-pwron0"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + }; + + lcd-controller@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + pressure-sensor@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; +}; + +&i2c8 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + led-controller@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", + "APSS_RESET_N", + "", + "N_MODE_CPU_N", + "", + "", + "P10_DCM_PRESENT", + ""; + }; + + led-controller@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", + "", + "SLOT2_PRSNT_EN_RSVD", + "", + "", + "", + "", + "SLOT2_EXPANDER_PRSNT_N", + "", + "", + "", + "", + "", + "", + "", + ""; + }; +}; + +&i2c9 { + status = "okay"; + + temperature-sensor@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "BOOT_RCVRY_TWI", + "BOOT_RCVRY_UART", + "", + "", + "", + "", + "", + "PE_SWITCH_RSTB_N"; + }; + + temperature-sensor@4c { + compatible = "ti,tmp435"; + reg = <0x4c>; + }; + + i2c-mux@75 { + compatible = "nxp,pca9849"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c11mux0chn0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0chn1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0chn2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0chn3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c12 { + status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + memory-region = <&event_log>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c13 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + led-controller@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + led@0 { + reg = <0>; + default-state = "keep"; + label = "nvme3"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + reg = <1>; + default-state = "keep"; + label = "nvme2"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + reg = <2>; + default-state = "keep"; + label = "nvme1"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + reg = <3>; + default-state = "keep"; + label = "nvme0"; + retain-state-shutdown; + type = <PCA955X_TYPE_LED>; + }; + }; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8 0xcac>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; +}; + +&lpc_ctrl { + memory-region = <&flash_memory>; + status = "okay"; +}; + +&mac2 { + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + use-ncsi; + status = "okay"; +}; + +&pinctrl_emmc_default { + bias-disable; +}; + +&uart2 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&vuart2 { + status = "okay"; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts index 2f5d4075a64a..a37399ff3cea 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts @@ -277,15 +277,11 @@ #size-cells = <0>; fan0: fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; }; fan1: fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts index 9f144f527f03..5a0975d52492 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts @@ -2066,27 +2066,19 @@ reg = <0x52>; fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; }; fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; }; fan@2 { - compatible = "pmbus-fan"; reg = <2>; - tach-pulses = <2>; }; fan@3 { - compatible = "pmbus-fan"; reg = <3>; - tach-pulses = <2>; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts index c5fb5d410001..e90421bf7e3a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts @@ -1080,39 +1080,27 @@ #size-cells = <0>; fan0: fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; }; fan1: fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; }; fan2: fan@2 { - compatible = "pmbus-fan"; reg = <2>; - tach-pulses = <2>; }; fan3: fan@3 { - compatible = "pmbus-fan"; reg = <3>; - tach-pulses = <2>; }; fan4: fan@4 { - compatible = "pmbus-fan"; reg = <4>; - tach-pulses = <2>; }; fan5: fan@5 { - compatible = "pmbus-fan"; reg = <5>; - tach-pulses = <2>; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts index b31eb8e58c6b..6fe7023599e8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts @@ -481,55 +481,19 @@ #size-cells = <0>; fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; fan@2 { - compatible = "pmbus-fan"; reg = <2>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; fan@3 { - compatible = "pmbus-fan"; reg = <3>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; }; diff --git a/arch/arm/boot/dts/aspeed/ibm-power11-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power11-dual.dtsi new file mode 100644 index 000000000000..6db02d475380 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/ibm-power11-dual.dtsi @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2025 IBM Corp. + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + + sbefifo100 = &sbefifo100; + sbefifo101 = &sbefifo101; + sbefifo110 = &sbefifo110; + sbefifo111 = &sbefifo111; + sbefifo112 = &sbefifo112; + sbefifo113 = &sbefifo113; + sbefifo114 = &sbefifo114; + sbefifo115 = &sbefifo115; + sbefifo202 = &sbefifo202; + sbefifo203 = &sbefifo203; + sbefifo210 = &sbefifo210; + sbefifo211 = &sbefifo211; + sbefifo214 = &sbefifo214; + sbefifo215 = &sbefifo215; + sbefifo216 = &sbefifo216; + sbefifo217 = &sbefifo217; + + scom100 = &scom100; + scom101 = &scom101; + scom110 = &scom110; + scom111 = &scom111; + scom112 = &scom112; + scom113 = &scom113; + scom114 = &scom114; + scom115 = &scom115; + scom202 = &scom202; + scom203 = &scom203; + scom210 = &scom210; + scom211 = &scom211; + scom214 = &scom214; + scom215 = &scom215; + scom216 = &scom216; + scom217 = &scom217; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + }; +}; + +&fsim0 { + bus-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <0>; + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + status = "okay"; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; /* OMI01 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom100: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo100: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; /* OMI23 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom101: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo101: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom110: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo110: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom111: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo111: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom112: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo112: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom113: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo113: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom114: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo114: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom115: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo115: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi1: spi@20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi2: spi@40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi3: spi@60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: fsi@3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; /* OMI45 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom202: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo202: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; /* OMI67 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom203: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo203: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom210: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo210: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom211: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo211: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom214: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo214: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom215: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo215: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom216: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo216: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom217: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo217: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi1: spi@20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi2: spi@40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi3: spi@60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi@3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + no-scan-on-init; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi b/arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi index 68c941a194b6..7aa4113d3026 100644 --- a/arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi +++ b/arch/arm/boot/dts/aspeed/ibm-power11-quad.dtsi @@ -1,24 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-or-later // Copyright 2024 IBM Corp. +#include "ibm-power11-dual.dtsi" + / { aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; i2c300 = &cfam2_i2c0; i2c301 = &cfam2_i2c1; i2c310 = &cfam2_i2c10; @@ -36,22 +22,6 @@ i2c416 = &cfam3_i2c16; i2c417 = &cfam3_i2c17; - sbefifo100 = &sbefifo100; - sbefifo101 = &sbefifo101; - sbefifo110 = &sbefifo110; - sbefifo111 = &sbefifo111; - sbefifo112 = &sbefifo112; - sbefifo113 = &sbefifo113; - sbefifo114 = &sbefifo114; - sbefifo115 = &sbefifo115; - sbefifo202 = &sbefifo202; - sbefifo203 = &sbefifo203; - sbefifo210 = &sbefifo210; - sbefifo211 = &sbefifo211; - sbefifo214 = &sbefifo214; - sbefifo215 = &sbefifo215; - sbefifo216 = &sbefifo216; - sbefifo217 = &sbefifo217; sbefifo300 = &sbefifo300; sbefifo301 = &sbefifo301; sbefifo310 = &sbefifo310; @@ -69,22 +39,6 @@ sbefifo416 = &sbefifo416; sbefifo417 = &sbefifo417; - scom100 = &scom100; - scom101 = &scom101; - scom110 = &scom110; - scom111 = &scom111; - scom112 = &scom112; - scom113 = &scom113; - scom114 = &scom114; - scom115 = &scom115; - scom202 = &scom202; - scom203 = &scom203; - scom210 = &scom210; - scom211 = &scom211; - scom214 = &scom214; - scom215 = &scom215; - scom216 = &scom216; - scom217 = &scom217; scom300 = &scom300; scom301 = &scom301; scom310 = &scom310; @@ -102,14 +56,6 @@ scom416 = &scom416; scom417 = &scom417; - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; spi30 = &cfam2_spi0; spi31 = &cfam2_spi1; spi32 = &cfam2_spi2; @@ -121,718 +67,7 @@ }; }; -&fsim0 { - #address-cells = <2>; - #size-cells = <0>; - status = "okay"; - bus-frequency = <100000000>; - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,p9-scom"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,i2c-fsi"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom100: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo100: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom101: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo101: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom110: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo110: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom111: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo111: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom112: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo112: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom113: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo113: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom114: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo114: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom115: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo115: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - compatible = "ibm,spi-fsi"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam0_spi1: spi@20 { - compatible = "ibm,spi-fsi"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam0_spi2: spi@40 { - compatible = "ibm,spi-fsi"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam0_spi3: spi@60 { - compatible = "ibm,spi-fsi"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - - occ { - compatible = "ibm,p10-occ"; - - hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub0: fsi@3400 { - compatible = "ibm,p9-fsi-controller"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; -}; - &fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,p9-scom"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,i2c-fsi"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom202: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo202: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom203: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo203: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom210: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo210: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom211: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo211: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom214: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo214: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom215: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo215: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom216: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo216: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom217: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo217: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_spi0: spi@0 { - compatible = "ibm,spi-fsi"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam1_spi1: spi@20 { - compatible = "ibm,spi-fsi"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam1_spi2: spi@40 { - compatible = "ibm,spi-fsi"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam1_spi3: spi@60 { - compatible = "ibm,spi-fsi"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - - occ { - compatible = "ibm,p10-occ"; - - hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi@3400 { - compatible = "ibm,p9-fsi-controller"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - no-scan-on-init; - }; - }; - cfam@2,0 { reg = <2 0>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile index 7f69a0355ea5..8df0976da01c 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,7 +2,30 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ + socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_st1_emmc.dtb \ + socfpga_arria10_mercury_aa1_st1_qspi.dtb \ + socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi index 41f865c8c098..c80201bce793 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -7,12 +7,14 @@ / { - model = "Enclustra Mercury AA1"; - compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; + model = "Enclustra Mercury+ AA1"; + compatible = "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; serial1 = &uart1; + spi0 = &qspi; }; memory@0 { @@ -24,52 +26,102 @@ chosen { stdout-path = "serial1:115200n8"; }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; +}; + +&i2c_encl { + status = "okay"; + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; }; &gmac0 { - phy-mode = "rgmii"; + status = "okay"; + phy-mode = "rgmii-id"; phy-addr = <0xffffffff>; /* probe for phy addr */ - max-frame-size = <3800>; - phy-handle = <&phy3>; + /delete-property/ mac-address; + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy3: ethernet-phy@3 { - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; /* 780ps */ rxd0-skew-ps = <420>; /* 0ps */ rxd1-skew-ps = <420>; /* 0ps */ rxd2-skew-ps = <420>; /* 0ps */ rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - reg = <3>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; /* 960ps */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + txen-skew-ps = <0>; /* -420ps */ }; }; }; -&i2c1 { - atsha204a: crypto@64 { - compatible = "atmel,atsha204a"; - reg = <0x64>; - }; +&gpio0 { + status = "okay"; +}; - isl12022: isl12022@6f { - compatible = "isil,isl12022"; - reg = <0x6f>; - }; +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; }; /* Following mappings are taken from arria10 socdk dts */ &mmc { + status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; @@ -79,3 +131,50 @@ &osc1 { clock-frequency = <33330000>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + status = "okay"; + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&watchdog1 { + status = "disabled"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts new file mode 100644 index 000000000000..b6cca0b5fd09 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts new file mode 100644 index 000000000000..6ad023477cd2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts new file mode 100644 index 000000000000..653c9a86516b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts new file mode 100644 index 000000000000..ae9c7c6a2370 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts new file mode 100644 index 000000000000..c3a0c30a07a5 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts new file mode 100644 index 000000000000..dc1e1ad20381 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts new file mode 100644 index 000000000000..61d5e4c85d9b --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts new file mode 100644 index 000000000000..a3b99c9b16fd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts new file mode 100644 index 000000000000..5deb289e2b55 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a9fd..000000000000 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar <kernel@pengutronix.de> - */ -/dts-v1/; -#include "socfpga_arria10_mercury_aa1.dtsi" - -/ { - model = "Enclustra Mercury+ PE1"; - compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1", - "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial0 = &uart0; - serial1 = &uart1; - }; -}; - -&gmac0 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&mmc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi new file mode 100644 index 000000000000..49944f9632f9 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Enclustra Mercury SA1"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&osc1 { + clock-frequency = <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + status = "okay"; + + isl12020: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&mmc0 { + status = "okay"; + /delete-property/ cap-mmc-highspeed; + /delete-property/ cap-sd-highspeed; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii-id"; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts new file mode 100644 index 000000000000..85d6146da0da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts new file mode 100644 index 000000000000..770ab680a18c --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts new file mode 100644 index 000000000000..990ca0fec61e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts new file mode 100644 index 000000000000..6c8fd5b0d6eb --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts new file mode 100644 index 000000000000..3292426078a1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts new file mode 100644 index 000000000000..1eb10b5244dd --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts new file mode 100644 index 000000000000..8c97b5b3adea --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts new file mode 100644 index 000000000000..e6d14b22e41d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts new file mode 100644 index 000000000000..beaeca94d4df --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 000000000000..0b28964e0378 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Enclustra Mercury+ SA2"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency = <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + status = "okay"; + + isl12020: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; + + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&mmc0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii-id"; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts new file mode 100644 index 000000000000..6f79d9ed1d36 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts new file mode 100644 index 000000000000..b94bd8bafc26 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts new file mode 100644 index 000000000000..51fc4a22937a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts new file mode 100644 index 000000000000..e4209209f4fa --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts new file mode 100644 index 000000000000..ab4549a0d455 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts new file mode 100644 index 000000000000..ebe62879c3fb --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi new file mode 100644 index 000000000000..d79cb64da0de --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status = "disabled"; +}; + +&mmc { + bus-width = <8>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi new file mode 100644 index 000000000000..5ba21dd8f5ba --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&mmc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi new file mode 100644 index 000000000000..2b102e0b6217 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 000000000000..abc4bfb7fccf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status = "okay"; + + eeprom@57 { + status = "okay"; + compatible = "microchip,24c128"; + reg = <0x57>; + pagesize = <64>; + label = "user eeprom"; + address-width = <16>; + }; + + lm96080: temperature-sensor@2f { + status = "okay"; + compatible = "national,lm80"; + reg = <0x2f>; + }; + + si5338: clock-controller@70 { + compatible = "silabs,si5338"; + reg = <0x70>; + }; + +}; + +&i2c_encl_fpga { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 000000000000..bc57b0680878 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status = "okay"; + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@56 { + status = "okay"; + compatible = "microchip,24c128"; + reg = <0x56>; + pagesize = <64>; + label = "user eeprom"; + address-width = <16>; + }; + + lm96080: temperature-sensor@2f { + status = "okay"; + compatible = "national,lm80"; + reg = <0x2f>; + }; + + pcal6416: gpio@20 { + status = "okay"; + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status = "okay"; + + i2c-mux@75 { + status = "okay"; + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 000000000000..4c00475f4303 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338: clock-controller@70 { + compatible = "silabs,si5338"; + reg = <0x70>; + }; +}; + +&i2c_encl_fpga { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/marvell/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi index 1181b13deabc..1d616edda322 100644 --- a/arch/arm/boot/dts/marvell/armada-38x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-38x.dtsi @@ -247,7 +247,7 @@ marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp41"; marvell,function = "nand"; }; diff --git a/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi index 7a7e2066c498..a9a71326aafc 100644 --- a/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi @@ -322,7 +322,7 @@ marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp19"; marvell,function = "nand"; }; diff --git a/arch/arm/boot/dts/mediatek/Makefile b/arch/arm/boot/dts/mediatek/Makefile index e48de3efeb3b..37c4cded0eae 100644 --- a/arch/arm/boot/dts/mediatek/Makefile +++ b/arch/arm/boot/dts/mediatek/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt6572-jty-d101.dtb \ mt6572-lenovo-a369i.dtb \ mt6580-evbp1.dtb \ + mt6582-alcatel-yarisxl.dtb \ mt6582-prestigio-pmt5008-3g.dtb \ mt6589-aquaris5.dtb \ mt6589-fairphone-fp1.dtb \ diff --git a/arch/arm/boot/dts/mediatek/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi index ce6a4015fed5..128b87229f3d 100644 --- a/arch/arm/boot/dts/mediatek/mt2701.dtsi +++ b/arch/arm/boot/dts/mediatek/mt2701.dtsi @@ -597,7 +597,7 @@ }; hifsys: syscon@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; + compatible = "mediatek,mt2701-hifsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/mediatek/mt6582-alcatel-yarisxl.dts b/arch/arm/boot/dts/mediatek/mt6582-alcatel-yarisxl.dts new file mode 100644 index 000000000000..f55d8edad1ac --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6582-alcatel-yarisxl.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Cristian Cozzolino <cristian_ci@protonmail.com> + */ + +/dts-v1/; +#include "mt6582.dtsi" + +/ { + model = "Alcatel One Touch Pop C7 (OT-7041D)"; + compatible = "alcatel,yarisxl", "mediatek,mt6582"; + + aliases { + serial0 = &uart0; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + stdout-path = "serial0:921600n8"; + + framebuffer: framebuffer@9fa00000 { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_reserved>; + width = <480>; + height = <854>; + stride = <(480 * 4)>; + format = "r5g6b5"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + connsys@9f900000 { + reg = <0x9f900000 0x100000>; + no-map; + }; + + modem@9e000000 { + reg = <0x9e000000 0x1800000>; + no-map; + }; + + framebuffer_reserved: framebuffer@9fa00000 { + reg = <0x9fa00000 0x600000>; + no-map; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6582.dtsi b/arch/arm/boot/dts/mediatek/mt6582.dtsi index 4263371784cd..f941ea44898a 100644 --- a/arch/arm/boot/dts/mediatek/mt6582.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6582.dtsi @@ -9,12 +9,12 @@ / { #address-cells = <1>; #size-cells = <1>; - compatible = "mediatek,mt6582"; interrupt-parent = <&sysirq>; cpus { - #address-cells = <1>; #size-cells = <0>; + #address-cells = <1>; + enable-method = "mediatek,mt6589-smp"; cpu@0 { device_type = "cpu"; @@ -38,91 +38,95 @@ }; }; - system_clk: dummy13m { + uart_clk: dummy26m { compatible = "fixed-clock"; - clock-frequency = <13000000>; #clock-cells = <0>; + clock-frequency = <26000000>; }; - rtc_clk: dummy32k { + system_clk: dummy13m { compatible = "fixed-clock"; - clock-frequency = <32000>; #clock-cells = <0>; + clock-frequency = <13000000>; }; - uart_clk: dummy26m { + rtc_clk: dummy32k { compatible = "fixed-clock"; - clock-frequency = <26000000>; #clock-cells = <0>; + clock-frequency = <32000>; }; - timer: timer@11008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6582-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6582-wdt", "mediatek,mt6589-wdt"; + reg = <0x10007000 0x100>; + }; - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; + timer: timer@10008000 { + compatible = "mediatek,mt6582-timer", "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>, <&rtc_clk>; + }; - uart0: serial@11002000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; - }; + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq"; + reg = <0x10200100 0x1c>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + }; - uart1: serial@11003000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; - }; + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; - uart2: serial@11004000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart0: serial@11002000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; - uart3: serial@11005000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart1: serial@11003000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; - watchdog: watchdog@10007000 { - compatible = "mediatek,mt6582-wdt", - "mediatek,mt6589-wdt"; - reg = <0x10007000 0x100>; + uart2: serial@11004000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index fd7a89cc337d..4b1685b93989 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -744,8 +744,7 @@ hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; + "mediatek,mt2701-hifsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi index 17430d7f2055..fde890f18d20 100644 --- a/arch/arm/boot/dts/microchip/sama5d2.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -571,7 +571,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -642,7 +642,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -854,7 +854,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -925,7 +925,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -997,7 +997,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index e53e2dd6d530..cd2cf9a6f40b 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -557,7 +557,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; status = "disabled"; }; @@ -618,7 +618,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "usart"; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; }; @@ -643,7 +643,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 381cbcfcb34a..03ef3d9aaeec 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -824,7 +824,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; }; @@ -850,7 +850,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/Makefile index 2ed2d923c8f9..faf591485ada 100644 --- a/arch/arm/boot/dts/nvidia/Makefile +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -11,7 +11,8 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-nyan-big.dtb \ tegra124-nyan-big-fhd.dtb \ tegra124-nyan-blaze.dtb \ - tegra124-venice2.dtb + tegra124-venice2.dtb \ + tegra124-xiaomi-mocha.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ tegra20-asus-sl101.dtb \ diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index a2a50f959927..a98667641be2 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -48,6 +48,45 @@ ranges = <0x54000000 0x54000000 0x01000000>; + vi@54080000 { + compatible = "nvidia,tegra114-vi"; + reg = <0x54080000 0x00040000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + + iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; + }; + + epp@540c0000 { + compatible = "nvidia,tegra114-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_EPP>; + resets = <&tegra_car TEGRA114_CLK_EPP>; + reset-names = "epp"; + + iommus = <&mc TEGRA_SWGROUP_EPP>; + + status = "disabled"; + }; + + isp@54100000 { + compatible = "nvidia,tegra114-isp"; + reg = <0x54100000 0x00040000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_ISP>; + resets = <&tegra_car TEGRA114_CLK_ISP>; + reset-names = "isp"; + + iommus = <&mc TEGRA_SWGROUP_ISP>; + + status = "disabled"; + }; + gr2d@54140000 { compatible = "nvidia,tegra114-gr2d"; reg = <0x54140000 0x00040000>; @@ -150,6 +189,31 @@ #address-cells = <1>; #size-cells = <0>; }; + + msenc@544c0000 { + compatible = "nvidia,tegra114-msenc"; + reg = <0x544c0000 0x00040000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_MSENC>; + resets = <&tegra_car TEGRA114_CLK_MSENC>; + reset-names = "mpe"; + + iommus = <&mc TEGRA_SWGROUP_MSENC>; + + status = "disabled"; + }; + + tsec@54500000 { + compatible = "nvidia,tegra114-tsec"; + reg = <0x54500000 0x00040000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_TSEC>; + resets = <&tegra_car TEGRA114_CLK_TSEC>; + + iommus = <&mc TEGRA_SWGROUP_TSEC>; + + status = "disabled"; + }; }; gic: interrupt-controller@50041000 { diff --git a/arch/arm/boot/dts/nvidia/tegra124-xiaomi-mocha.dts b/arch/arm/boot/dts/nvidia/tegra124-xiaomi-mocha.dts new file mode 100644 index 000000000000..18c9cdf45eca --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra124-xiaomi-mocha.dts @@ -0,0 +1,2790 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/ti-drv260x.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/thermal/thermal.h> + +#include "tegra124.dtsi" + +/ { + model = "Xiaomi Mi Pad A0101"; + compatible = "xiaomi,mocha", "nvidia,tegra124"; + chassis-type = "tablet"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &palmas; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0 0x80000000 0 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + nvidia,ganged-mode = <&dsib>; + + panel@0 { + compatible = "sharp,lq079l1sx01"; + reg = <0>; + + reset-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_LOW>; + + avdd-supply = <&avdd_lcd>; + vddio-supply = <&vdd_lcd_io>; + + vsp-supply = <&vsp_5v5_lcd>; + vsn-supply = <&vsn_5v5_lcd>; + + backlight = <&lp8556>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_link0: endpoint { + remote-endpoint = <&dsia_out>; + }; + }; + + port@1 { + reg = <1>; + + panel_link1: endpoint { + remote-endpoint = <&dsib_out>; + }; + }; + }; + }; + + port { + dsia_out: endpoint { + remote-endpoint = <&panel_link0>; + }; + }; + }; + + dsib: dsi@54400000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + port { + dsib_out: endpoint { + remote-endpoint = <&panel_link1>; + }; + }; + }; + }; + + gpu@57000000 { + vdd-supply = <&vdd_gpu>; + }; + + clock@60006000 { + emc-timings-0 { + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Keys pinmux */ + keys { + nvidia,pins = "kb_col0_pq0", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + hall-front { + nvidia,pins = "pi5"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + hall-back { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Leds pinmux */ + bl-en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + keys-led { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + rgb-led-en { + nvidia,pins = "pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Panel pinmux */ + lcd-rst { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + lcd-vsp-en { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + lcd-vsn-en { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + lcd-id { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd-pwm { + nvidia,pins = "ph2"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC1 pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc3-cd { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + usd-pwr { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-B pinmux */ + uartb-cts { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + uartb-rts { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D pinmux */ + uartd-txd { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + uartd-rxd { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + + ts-irq { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ts-rst { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ts-en { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + hapt-en { + nvidia,pins = "pg6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + charger-irq { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + bat-irq { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + compass-rst { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + als-irq { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + therm-irq { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + wlan-reg-on { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + wlan-host-wake { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + bt-reg-on { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + bt-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + bt-dev-wake { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + imu-irq { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + imu-sync { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + cdc-mclk1 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cdc-din { + nvidia,pins = "dap1_din_pn1", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + cdc-dout { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spkr-rl-rst { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spkr-rl-irq { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dvfs-pwm { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dvfs-clk { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cam-mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cam-mclk2 { + nvidia,pins = "pbb0"; + nvidia,function = "vimclk2_alt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vbrtr-pwm { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + soc-pins { + nvidia,pins = "pj2", "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + lcd-id-det0 { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + cdc-rst { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cdc-det-irq { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + hph-pa-sd { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + hph-en { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cam-rear-rst-n { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cam-af-pwdn { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cam-front-pwdn { + nvidia,pins = "pbb6"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cam-front-rst-n { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gps-en { + nvidia,pins = "ph5"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + boot-select { + nvidia,pins = "pg0", "pg1", "pg2", "pg3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ram-select { + nvidia,pins = "pg4", "pg5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + line-in-det { + nvidia,pins = "pk2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gpadc-sync { + nvidia,pins = "pi0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gpu-pwr-req { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ear-uart-sw { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dsi-b { + nvidia,pins = "mipi_pad_ctrl_dsi_b"; + nvidia,function = "dsi_b"; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <32>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <1>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + bluetooth { + compatible = "brcm,bcm43540-bt"; + max-speed = <4000000>; + + clocks = <&clk32k_pmic>; + clock-names = "lpo"; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + uartd: serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + /* Console */ + }; + + pwm@7000a000 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + lp8556: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x83>; + init-brt = /bits/ 8 <0x1f>; + + power-supply = <&vdd_3v3_sys>; + enable-supply = <&vddio_1v8_bl>; + + rom-98h { + rom-addr = /bits/ 8 <0x98>; + rom-val = /bits/ 8 <0x80>; + }; + + rom-9eh { + rom-addr = /bits/ 8 <0x9e>; + rom-val = /bits/ 8 <0x21>; + }; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; + }; + + rom-a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + + rom-a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x00>; + }; + + rom-a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x72>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + + rom-a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + + rom-a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf5>; + }; + + rom-a8h { + rom-addr = /bits/ 8 <0xa8>; + rom-val = /bits/ 8 <0x24>; + }; + + rom-a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0xb2>; + }; + + rom-aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x8f>; + }; + + rom-aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; + + led-controller@32 { + compatible = "national,lp5521"; + reg = <0x32>; + + enable-gpios = <&gpio TEGRA_GPIO(G, 7) GPIO_ACTIVE_HIGH>; + clock-mode = /bits/ 8 <2>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + + led-cur = /bits/ 8 <0x14>; + max-cur = /bits/ 8 <0xff>; + + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + }; + + led@1 { + reg = <1>; + + led-cur = /bits/ 8 <0x14>; + max-cur = /bits/ 8 <0xff>; + + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + }; + + led@2 { + reg = <2>; + + led-cur = /bits/ 8 <0x14>; + max-cur = /bits/ 8 <0xff>; + + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + }; + }; + + audio-codec@34 { + compatible = "nxp,tfa9890"; + reg = <0x34>; + + sound-name-prefix = "Speaker Right"; + vddd-supply = <&vdd_1v8_vio>; + + #sound-dai-cells = <0>; + }; + + audio-codec@37 { + compatible = "nxp,tfa9890"; + reg = <0x37>; + + sound-name-prefix = "Speaker Left"; + vddd-supply = <&vdd_1v8_vio>; + + #sound-dai-cells = <0>; + }; + + light-sensor@44 { + compatible = "isil,isl29035"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vdd_3v3_sys>; + }; + + temp_sensor: temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&vdd_1v8_vio>; + #thermal-sensor-cells = <1>; + }; + + haptic-engine@5a { + compatible = "ti,drv2604"; + reg = <0x5a>; + + enable-gpios = <&gpio TEGRA_GPIO(G, 6) GPIO_ACTIVE_HIGH>; + + mode = <DRV260X_ERM_MODE>; + library-sel = <DRV260X_ERM_LIB_A>; + + vib-rated-mv = <3200>; + vib-overdrive-mv = <3400>; + + vbat-supply = <&vdd_3v3_sys>; + }; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + + vs-supply = <&vdd_hv_sdmmc>; + #io-channel-cells = <1>; + }; + + fuel-gauge@55 { + compatible = "ti,bq27520g4"; + reg = <0x55>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Q, 5) IRQ_TYPE_EDGE_FALLING>; + + monitored-battery = <&battery>; + power-supplies = <&bq24192>; + }; + + bq24192: charger@6b { + compatible = "ti,bq24192"; + reg = <0x6b>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_EDGE_FALLING>; + + ce-gpios = <&palmas_gpio 7 GPIO_ACTIVE_LOW>; + + monitored-battery = <&battery>; + + omit-battery-class; + ti,system-minimum-microvolt = <3500000>; + + usb_otg_vbus: usb-otg-vbus { + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <400000>; + + /* Atmel mxT1664T/mxT1066T touchscreen */ + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(R, 7) IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>; + + linux,keycodes = <KEY_BACK KEY_HOME KEY_MENU>; + + vdda-supply = <&avdd_3v3_ts>; + vdd-supply = <&vdd_2v8_tp>; + }; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + adc { + compatible = "ti,palmas-gpadc"; + interrupts = <18 IRQ_TYPE_NONE>, + <16 IRQ_TYPE_NONE>, + <17 IRQ_TYPE_NONE>; + + ti,channel0-current-microamp = <20>; + #io-channel-cells = <1>; + }; + + palmas_extcon: extcon { + compatible = "ti,palmas-usb-vid"; + + ti,enable-vbus-detection; + ti,enable-id-detection; + + ti,wakeup; + }; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + clk32k_pmic: palmas-clk32k@0 { + compatible = "ti,palmas-clk32kg"; + #clock-cells = <0>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio0 { + pins = "gpio0"; + function = "id"; + bias-pull-up; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + /* GPIO3 is not used */ + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "clk32kgaudio"; + }; + + /* GPIO6 is not used */ + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldo1-in-supply = <&vdd_1v8_vio>; + ldo2-in-supply = <&vdd_3v3_sys>; + ldo3-in-supply = <&vdd_smps10_out2>; + ldo4-in-supply = <&vdd_3v3_sys>; + ldo5-in-supply = <&vdd_1v8_vio>; + ldo6-in-supply = <&vdd_3v3_sys>; + ldo7-in-supply = <&vdd_3v3_sys>; + ldo8-in-supply = <&vdd_3v3_sys>; + ldo9-in-supply = <&vdd_hv_sdmmc>; + ldousb-in-supply = <&vdd_smps10_out2>; + ldoln-in-supply = <&vdd_smps10_out2>; + + regulators { + vdd_cpu: smps123 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <1>; + ti,mode-sleep = <3>; + }; + + vdd_gpu: smps45 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + }; + + vddio_ddr: smps6 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_core: smps7 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_hv_sdmmc: smps9 { + regulator-name = "vdd_hv_sdmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out1 { + regulator-name = "vd_smps10_out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out2: smps10_out2 { + regulator-name = "vd_smps10_out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_pll: ldo1 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + avdd_lcd: ldo2 { + regulator-name = "avdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + avdd_3v3_ts: ldo3 { + regulator-name = "avdd_3v3_ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + avdd_2v7_cam: ldo4 { + regulator-name = "avdd_2v7_cam"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + avdd_dsi_csi: ldo5 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ldo6 { + regulator-name = "vdd_1v8_fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + avdd_2v7_vcm: ldo7 { + regulator-name = "avdd_2v7_vcm"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo8 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln { + regulator-name = "vddio_hv"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 IRQ_TYPE_NONE>; + }; + }; + }; + + pmc@7000e400 { + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <2000>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Clear DEV_ON bit in DEV_CTRL register of TPS65913 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x58>; + nvidia,reg-addr = <0xa0>; + nvidia,reg-data = <0x00>; + }; + }; + + memory-controller@70019000 { + emc-timings-0 { + /* Hynix H9CKNNNBKTMTDR DDR3 924MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x40040001 0x8000000a + 0x00000001 0x00000002 0x00000004 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000b0604 0x77230305 0x70000f03 + 0x001f0000 >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < 0x40020001 0x80000012 + 0x00000001 0x00000002 0x00000004 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000b0604 0x75a30305 0x70000f03 + 0x001f0000 >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < 0xa0000001 0x80000017 + 0x00000001 0x00000002 0x00000004 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000b0604 0x74030305 0x70000f03 + 0x001f0000 >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < 0x00000001 0x8000001e + 0x00000001 0x00000002 0x00000003 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000a0503 0x73830404 0x70000f03 + 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x08000001 0x80000026 + 0x00000001 0x00000002 0x00000004 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000a0504 0x73430505 0x70000f03 + 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x01000003 0x80000040 + 0x00000001 0x00000002 0x00000007 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000007 + 0x00000003 0x00000001 0x00000005 0x00000005 + 0x05050103 0x000b0607 0x72e40a08 0x70000f03 + 0x001f0000 >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < 0x08000004 0x80000040 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000007 + 0x00000003 0x00000001 0x00000005 0x00000005 + 0x05050103 0x000c0709 0x72c50e0a 0x70000f03 + 0x001f0000 >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < 0x0f000005 0x80000040 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000007 + 0x00000003 0x00000001 0x00000005 0x00000005 + 0x05050103 0x000e090c 0x72c6120d 0x70000f03 + 0x001f0000 >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < 0x0f000007 0x80000040 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000009 + 0x00000003 0x00000001 0x00000006 0x00000006 + 0x06060103 0x00120b10 0x72c81811 0x70000f03 + 0x001f0000 >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < 0x00000009 0x80000040 + 0x00000004 0x00000005 0x00000012 0x0000000b + 0x0000000e 0x00000002 0x00000003 0x0000000a + 0x00000003 0x00000001 0x00000006 0x00000007 + 0x07060103 0x00140d12 0x72c91b13 0x70000f03 + 0x001f0000 >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < 0x0e00000b 0x80000040 + 0x00000006 0x00000007 0x00000018 0x0000000f + 0x00000013 0x00000003 0x00000003 0x0000000c + 0x00000003 0x00000001 0x00000008 0x00000008 + 0x08080103 0x001a1118 0x72ac2419 0x70000f02 + 0x001f0000 >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < 0x0e00000d 0x80000040 + 0x00000007 0x00000008 0x0000001b 0x00000012 + 0x00000017 0x00000004 0x00000004 0x0000000e + 0x00000004 0x00000001 0x00000009 0x00000009 + 0x09090104 0x001e141b 0x72ae2a1c 0x70000f02 + 0x001f0000 >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-0 { + /* Hynix H9CKNNNBKTMTDR DDR3 924MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x000d0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000000 0x00000002 0x00000000 0x00000002 + 0x00000005 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x00000030 + 0x00000000 0x0000000c 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000003 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000006 0x00000003 + 0x00000003 0x00000056 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000011 0x000d0011 0x00000000 0x00000003 + 0x0000f3f3 0x80000164 0x0000000a >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00150011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000001 0x00000004 0x00000000 0x00000002 + 0x00000005 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x0000004d + 0x00000000 0x00000013 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000005 0x00000005 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000006 0x00000003 + 0x00000003 0x0000008a 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000011 0x00150011 0x00000000 0x00000003 + 0x0000f3f3 0x8000019f 0x0000000a >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00290011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000002 0x00000008 0x00000000 0x00000002 + 0x00000005 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x0000009a + 0x00000000 0x00000026 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000009 0x00000009 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000007 0x00000003 + 0x00000003 0x00000113 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000011 0x00290011 0x00000000 0x00000003 + 0x0000f3f3 0x8000023a 0x0000000a >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00440011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000004 0x00000010 0x00000000 0x00000002 + 0x00000004 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x00000101 + 0x00000000 0x00000040 0x00000002 0x00000002 + 0x00000004 0x00000000 0x00000001 0x0000000c + 0x0000000f 0x0000000f 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000005 0x00000003 + 0x00000003 0x000001c9 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000019 0x00440011 0x00000000 0x00000003 + 0x0000f3f3 0x80000309 0x0000000a >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00660011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000006 0x00000015 0x00000000 0x00000004 + 0x00000004 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x00000182 + 0x00000000 0x00000060 0x00000002 0x00000002 + 0x00000004 0x00000000 0x00000001 0x0000000c + 0x00000017 0x00000017 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000005 0x00000003 + 0x00000003 0x000002ae 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000025 0x00660011 0x00000000 0x00000003 + 0x0000f3f3 0x8000040b 0x0000000a >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008cf>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00cc0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000017>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x0000000c 0x0000002a 0x00000000 0x00000008 + 0x00000005 0x00000007 0x00000008 0x00000003 + 0x0000000a 0x00000003 0x00000003 0x00000002 + 0x00000003 0x00000000 0x00000002 0x00000002 + 0x00000005 0x00000003 0x00000000 0x00000003 + 0x00000007 0x00010000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x0000000e 0x0000000f 0x00000011 0x00000304 + 0x00000000 0x000000c1 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x0000002d 0x0000002d 0x00000003 0x00000004 + 0x00000003 0x00000009 0x00000006 0x00000003 + 0x00000003 0x0000055b 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00098000 0x00098000 0x00000000 0x00098000 + 0x00098000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x0008c000 0x00088000 + 0x00088000 0x00088000 0x00008800 0x00008800 + 0x00008800 0x00008800 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000004a 0x00cc0011 0x00000000 0x00000004 + 0x0000d3b3 0x80000713 0x0000000a >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x000008d7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x012c0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x01231239>; + nvidia,emc-zcal-cnt-long = <0x0000001f>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000011 0x0000003e 0x00000000 0x0000000c + 0x00000005 0x00000007 0x00000008 0x00000003 + 0x0000000a 0x00000005 0x00000005 0x00000002 + 0x00000003 0x00000000 0x00000002 0x00000002 + 0x00000006 0x00000003 0x00000000 0x00000003 + 0x00000008 0x00030000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x0000000f 0x00000012 0x00000014 0x0000046e + 0x00000000 0x0000011b 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000042 0x00000042 0x00000003 0x00000005 + 0x00000003 0x0000000d 0x00000007 0x00000003 + 0x00000003 0x000007e0 0x00000000 0x00000000 + 0x00000000 0x1363a096 0x005800a0 0x00008000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00060000 0x00060000 0x00000000 0x00060000 + 0x00060000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00048000 0x00048000 + 0x00048000 0x00048000 0x00004800 0x00004800 + 0x00004800 0x00004800 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000006c 0x012c0011 0x00000000 0x00000004 + 0x000052a3 0x800009ed 0x0000000b >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x00000897>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x018c0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x01231239>; + nvidia,emc-zcal-cnt-long = <0x00000028>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000017 0x00000053 0x00000000 0x00000010 + 0x00000007 0x00000008 0x00000008 0x00000003 + 0x0000000a 0x00000007 0x00000007 0x00000003 + 0x00000003 0x00000000 0x00000002 0x00000002 + 0x00000006 0x00000003 0x00000000 0x00000002 + 0x00000009 0x00030000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000001 + 0x00000010 0x00000012 0x00000014 0x000005d9 + 0x00000000 0x00000176 0x00000002 0x00000002 + 0x00000007 0x00000000 0x00000001 0x0000000e + 0x00000058 0x00000058 0x00000003 0x00000006 + 0x00000003 0x00000012 0x00000009 0x00000003 + 0x00000003 0x00000a66 0x00000000 0x00000000 + 0x00000000 0x1363a096 0x005800a0 0x00008000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00048000 0x00048000 0x00000000 0x00048000 + 0x00048000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00038000 0x00038000 + 0x00038000 0x00038000 0x00003800 0x00003800 + 0x00003800 0x00003800 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000008f 0x018c0011 0x00000000 0x00000004 + 0x000052a3 0x80000cc7 0x0000000b >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x800100c3>; + nvidia,emc-mode-2 = <0x80020006>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x02100013>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0123123d>; + nvidia,emc-zcal-cnt-long = <0x00000034>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x0000001f 0x0000006e 0x00000000 0x00000016 + 0x00000009 0x00000009 0x00000009 0x00000003 + 0x0000000d 0x00000009 0x00000009 0x00000005 + 0x00000004 0x00000000 0x00000002 0x00000002 + 0x00000008 0x00000003 0x00000000 0x00000003 + 0x0000000a 0x00050000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x00000011 0x00000015 0x00000017 0x000007cd + 0x00000000 0x000001f3 0x00000003 0x00000003 + 0x00000009 0x00000000 0x00000001 0x00000011 + 0x00000075 0x00000075 0x00000004 0x00000008 + 0x00000004 0x00000019 0x0000000c 0x00000003 + 0x00000003 0x00000ddd 0x00000000 0x00000000 + 0x00000000 0x1363a096 0xe01200b9 0x00008000 + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00004010 0x00004010 0x00000000 0x00004010 + 0x00004010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x0000000c 0x0000000c + 0x0000000c 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000c 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x000000bf 0x02100013 0x00000000 0x00000004 + 0x000042a0 0x800010b3 0x0000000d >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x800100e3>; + nvidia,emc-mode-2 = <0x80020007>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x02580014>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0121103d>; + nvidia,emc-zcal-cnt-long = <0x0000003a>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000023 0x0000007d 0x00000000 0x00000019 + 0x0000000a 0x0000000a 0x0000000b 0x00000004 + 0x0000000f 0x0000000a 0x0000000a 0x00000005 + 0x00000004 0x00000000 0x00000004 0x00000004 + 0x0000000a 0x00000004 0x00000000 0x00000003 + 0x0000000d 0x00070000 0x00000005 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x00000014 0x00000018 0x0000001a 0x000008e4 + 0x00000000 0x00000239 0x00000004 0x00000004 + 0x0000000a 0x00000000 0x00000001 0x00000013 + 0x00000084 0x00000084 0x00000005 0x00000009 + 0x00000005 0x0000001c 0x0000000d 0x00000003 + 0x00000003 0x00000fc0 0x00000000 0x00000000 + 0x00000000 0x1363a096 0xe00e00b9 0x00008000 + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000010 0x00000010 0x00000000 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000001 + 0x00000000 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000000 0x00000000 0x00000001 + 0x00000000 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000000 0x0000000c 0x0000000b + 0x0000000b 0x0000000b 0x0000000b 0x0000000b + 0x0000000b 0x0000000b 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x000000d8 0x02580014 0x00000000 0x00000005 + 0x000040a0 0x800012d6 0x00000010 >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010043>; + nvidia,emc-mode-2 = <0x8002001a>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x03180017>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0120103d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x0000002f 0x000000a6 0x00000000 0x00000021 + 0x0000000e 0x0000000d 0x0000000d 0x00000005 + 0x00000013 0x0000000e 0x0000000e 0x00000007 + 0x00000004 0x00000000 0x00000005 0x00000005 + 0x0000000e 0x00000004 0x00000000 0x00000005 + 0x0000000f 0x000b0000 0x00000006 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x00000016 0x0000001d 0x0000001f 0x00000bd1 + 0x00000000 0x000002f4 0x00000005 0x00000005 + 0x0000000e 0x00000000 0x00000001 0x00000017 + 0x000000af 0x000000af 0x00000006 0x0000000c + 0x00000006 0x00000026 0x00000011 0x00000003 + 0x00000003 0x000014cb 0x00000000 0x00000000 + 0x00000000 0x1363a096 0xe00700b9 0x00008000 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00008012 0x00008012 0x00000000 0x00008012 + 0x00008012 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000002 0x00000005 + 0x00000002 0x00000004 0x00000005 0x00000004 + 0x00000004 0x00000003 0x00000002 0x00000005 + 0x00000002 0x00000004 0x00000005 0x00000004 + 0x00000004 0x00000003 0x0000000b 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000808 0x81f1f008 0x07070000 0x00000000 + 0x015ddddd 0x61861820 0x00514514 0x00514514 + 0x61861800 0x0000003f 0x00000000 0x00000000 + 0x0000011e 0x03180017 0x00000000 0x00000006 + 0x00004080 0x8000188b 0x00000014 >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x8002001c>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x039c0019>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0120103d>; + nvidia,emc-zcal-cnt-long = <0x00000058>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000037 0x000000c2 0x00000000 0x00000026 + 0x00000010 0x0000000f 0x00000010 0x00000006 + 0x00000017 0x00000010 0x00000010 0x00000009 + 0x00000005 0x00000000 0x00000007 0x00000007 + 0x00000010 0x00000005 0x00000000 0x00000005 + 0x00000012 0x000d0000 0x00000007 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x00000019 0x00000020 0x00000022 0x00000dd4 + 0x00000000 0x00000375 0x00000006 0x00000006 + 0x00000010 0x00000000 0x00000001 0x0000001b + 0x000000cc 0x000000cc 0x00000007 0x0000000e + 0x00000007 0x0000002d 0x00000014 0x00000003 + 0x00000003 0x00001842 0x00000000 0x00000000 + 0x00000000 0x1363a896 0xe00400b9 0x00008000 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x0000000f 0x0000000f 0x00000000 0x00000011 + 0x00000012 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000004 0x00000006 + 0x00000004 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000005 0x00000004 0x00000006 + 0x00000004 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000005 0x0000000a 0x00000009 + 0x00000009 0x0000000a 0x00000009 0x00000009 + 0x00000009 0x00000009 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000404 0x81f1f008 0x07070000 0x00000000 + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000014d 0x039c0019 0x00000000 0x00000007 + 0x00004080 0x80001c77 0x00000017 >; + }; + }; + }; + + padctl@7009f000 { + status = "disabled"; + }; + + /* WiFi */ + sdmmc1: mmc@700b0000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_P>; + assigned-clock-rates = <204000000>; + + max-frequency = <82000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + sd-uhs-sdr104; + mmc-ddr-1_8v; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* BCM4354XKUBG */ + wifi@1 { + compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + clocks = <&clk32k_pmic>; + clock-names = "lpo"; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; + }; + + /* MicroSD */ + sdmmc3: mmc@700b0400 { + status = "okay"; + bus-width = <4>; + + sd-uhs-sdr104; + mmc-ddr-1_8v; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_hv_sdmmc>; + vqmmc-supply = <&vddio_usd>; + }; + + /* eMMC */ + sdmmc4: mmc@700b0600 { + status = "okay"; + bus-width = <8>; + + mmc-hs200-1_8v; + non-removable; + + vmmc-supply = <&vdd_hv_sdmmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + + ahub@70300000 { + /* HIFI CODEC */ + i2s@70301000 { /* i2s0 */ + status = "okay"; + }; + + /* LEFT SPK */ + i2s@70301100 { /* i2s1 */ + status = "okay"; + }; + + /* RIGHT SPK */ + i2s@70301200 { /* i2s2 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70301300 { /* i2s3 */ + status = "okay"; + }; + }; + + usb1: usb@7d000000 { + compatible = "nvidia,tegra124-udc"; + status = "okay"; + dr_mode = "otg"; + + hnp-disable; + srp-disable; + adp-disable; + + usb-role-switch; + extcon = <&bq24192>, <&palmas_extcon>; /* vbus, id */ + vbus-supply = <&usb_otg_vbus>; + + port { + usb_in: endpoint { + remote-endpoint = <&connector_out>; + }; + }; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&avdd_usb>; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + + charge-full-design-microamp-hours = <6520000>; + energy-full-design-microwatt-hours = <2478000>; + + voltage-min-design-microvolt = <4300000>; + voltage-max-design-microvolt = <4350000>; + + precharge-current-microamp = <256000>; + charge-term-current-microamp = <400000>; + + operating-range-celsius = <0 45>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + connector { + compatible = "usb-b-connector"; + type = "micro"; + + port { + connector_out: endpoint { + remote-endpoint = <&usb_in>; + }; + }; + }; + + cpus { + cpu0: cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-back-hall-sensor { + label = "Hall sensor (back)"; + gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + linux,can-disable; + wakeup-source; + }; + + switch-front-hall-sensor { + label = "Hall sensor (front)"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + linux,can-disable; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + }; + }; + + led-controller { + compatible = "pwm-leds"; + + led-button { + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_BACKLIGHT; + + pwms = <&pwm 1 10000>; + max-brightness = <100>; + }; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_3v3_sys: regulator-3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vddio_1v8_bl: regulator-bl-io { + compatible = "regulator-fixed"; + regulator-name = "vddio_1v8_bl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + vdd_lcd_io: regulator-lcd-vio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + vsp_5v5_lcd: regulator-vsp { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd_vsp"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vsn_5v5_lcd: regulator-vsn { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd_vsn"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_2v8_tp: regulator-vtp { + compatible = "regulator-fixed"; + regulator-name = "vdd_2v8_tp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_smps10_out2>; + }; + + iovdd_1v8_cam: regulator-iovdd-cam { + compatible = "regulator-fixed"; + regulator-name = "iovdd_1v8_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + dvdd_1v2_cam: regulator-dvdd-cam { + compatible = "regulator-fixed"; + regulator-name = "dvdd_1v2_cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&palmas_gpio 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + vdd_3v3_hph: regulator-hph { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_hph"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + thermal-zones { + /* + * TMP451 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * tablet from getting too hot from a user's tactile + * perspective. The CPU zone is intended to protect + * silicon from damage. + */ + + tmp451-skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <10000>; /* milliseconds */ + + thermal-sensors = <&temp_sensor 0>; + + trips { + skip_alert_trip: skin-alert { + /* throttle at 50C until temperature drops to 49.5C */ + temperature = <50000>; + hysteresis = <500>; + type = "passive"; + }; + + skin-crit { + /* shut down at 85C */ + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map-skip { + trip = <&skip_alert_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + tmp451-cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <10000>; /* milliseconds */ + + thermal-sensors = <&temp_sensor 1>; + + trips { + cpu_alert_trip: cpu-alert { + /* throttle at 85C until temperature drops to 84.5C */ + temperature = <85000>; + hysteresis = <500>; + type = "passive"; + }; + + cpu-crit { + /* shut down at 95C */ + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map-cpu { + trip = <&cpu_alert_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi index ec4f0e346b2b..ce4efa1de509 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -103,6 +103,45 @@ ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; + vi@54080000 { + compatible = "nvidia,tegra124-vi"; + reg = <0x0 0x54080000 0x0 0x00040000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + + iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; + }; + + isp@54600000 { + compatible = "nvidia,tegra124-isp"; + reg = <0x0 0x54600000 0x0 0x00040000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_ISP>; + resets = <&tegra_car TEGRA124_CLK_ISP>; + reset-names = "isp"; + + iommus = <&mc TEGRA_SWGROUP_ISP2>; + + status = "disabled"; + }; + + isp@54680000 { + compatible = "nvidia,tegra124-isp"; + reg = <0x0 0x54680000 0x0 0x00040000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_ISPB>; + resets = <&tegra_car TEGRA124_CLK_ISPB>; + reset-names = "isp"; + + iommus = <&mc TEGRA_SWGROUP_ISP2B>; + + status = "disabled"; + }; + dc@54200000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; @@ -209,6 +248,31 @@ #size-cells = <0>; }; + msenc@544c0000 { + compatible = "nvidia,tegra124-msenc"; + reg = <0x0 0x544c0000 0x0 0x00040000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_MSENC>; + resets = <&tegra_car TEGRA124_CLK_MSENC>; + reset-names = "mpe"; + + iommus = <&mc TEGRA_SWGROUP_MSENC>; + + status = "disabled"; + }; + + tsec@54500000 { + compatible = "nvidia,tegra124-tsec"; + reg = <0x0 0x54500000 0x0 0x00040000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_TSEC>; + resets = <&tegra_car TEGRA124_CLK_TSEC>; + + iommus = <&mc TEGRA_SWGROUP_TSEC>; + + status = "disabled"; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi index 882adb7f2f26..c60fc1971188 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -64,7 +64,7 @@ vi@54080000 { compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; + reg = <0x54080000 0x00000800>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 20>; @@ -72,6 +72,23 @@ power-domains = <&pd_venc>; operating-points-v2 = <&vi_dvfs_opp_table>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible = "nvidia,tegra20-csi"; + reg = <0x800 0x200>; + clocks = <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_venc>; + #nvidia,mipi-calibrate-cells = <1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; epp@540c0000 { diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi index 2a4d93db8134..4c4e6097c916 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -150,8 +150,8 @@ }; vi@54080000 { - compatible = "nvidia,tegra30-vi"; - reg = <0x54080000 0x00040000>; + compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi"; + reg = <0x54080000 0x00000800>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_VI>; resets = <&tegra_car 20>; @@ -162,6 +162,26 @@ iommus = <&mc TEGRA_SWGROUP_VI>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible = "nvidia,tegra30-csi"; + reg = <0x800 0x200>; + clocks = <&tegra_car TEGRA30_CLK_CSI>, + <&tegra_car TEGRA30_CLK_CSIA_PAD>, + <&tegra_car TEGRA30_CLK_CSIB_PAD>; + clock-names = "csi", "csia-pad", "csib-pad"; + power-domains = <&pd_venc>; + #nvidia,mipi-calibrate-cells = <1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; epp@540c0000 { diff --git a/arch/arm/boot/dts/nxp/imx/e70k02.dtsi b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi index dcc3c9d488a8..3bb11c5a6353 100644 --- a/arch/arm/boot/dts/nxp/imx/e70k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi @@ -69,6 +69,14 @@ reg = <0x80000000 0x20000000>; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; + reg_wifi: regulator-wifi { compatible = "regulator-fixed"; regulator-name = "SD3_SPWR"; @@ -133,7 +141,22 @@ vdd-supply = <&ldo5_reg>; }; - /* TODO: SY7636 PMIC for E Ink at 0x62 */ + sy7636: pmic@62 { + compatible = "silergy,sy7636a"; + reg = <0x62>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + vcom-en-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + epd-pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + vin-supply = <&epd_pmic_supply>; + + #thermal-sensor-cells = <0>; + + regulators { + reg_epdpmic: vcom { + regulator-name = "vcom"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts index 2892e457fea7..e45a97d3f449 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts @@ -537,6 +537,8 @@ mpl3115: pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; }; eeprom: eeprom@50 { diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts b/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts index 2f06ad61a766..6938ad6dbc2c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts @@ -28,6 +28,7 @@ reg = <0x08>; interrupt-parent = <&gpio5>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; regulators { sw1_reg: sw1a { regulator-name = "SW1"; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts b/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts index acc44010d510..3ad9db4b1442 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * USB armory MkI device tree file * https://inversepath.com/usbarmory * * Copyright (C) 2015, Inverse Path * Andrej Rosano <andrej@inversepath.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts index a7400d42475b..bf8e07f97143 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts @@ -20,6 +20,7 @@ panel: panel { compatible = "lg,lb070wv8"; backlight = <&backlight>; + power-supply = <®_3p3v>; enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; port { diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi index 590dcc0953cc..5dc7f1f9ca17 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi @@ -47,7 +47,8 @@ mpl3115a2: pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; - + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; /* * The MPL3115 interrupts are connected to pin 22 and 23 * of &tca6424a, but the binding does not yet support diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts index 7c62db91173b..47a6d63c8e04 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts @@ -72,6 +72,7 @@ panel { compatible = "edt,etm0700g0bdh6"; backlight = <&backlight>; + power-supply = <®_panel>; port { panel_in: endpoint { @@ -89,6 +90,13 @@ enable-active-high; }; + reg_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts index dfa8110b1d97..0ef24a07dedf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts @@ -123,7 +123,7 @@ }; }; - touch-thermal0 { + touch-0-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; @@ -137,7 +137,7 @@ }; }; - touch-thermal1 { + touch-1-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts index 29dc6875ab66..353f7097cb7e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts @@ -55,7 +55,7 @@ iio-hwmon { compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>; + io-channels = <&vdiv_vaccu 0>; }; keys { @@ -256,7 +256,7 @@ }; }; - touch-thermal0 { + touch-0-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; @@ -270,7 +270,7 @@ }; }; - touch-thermal1 { + touch-1-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; @@ -318,7 +318,7 @@ io-channels = <&adc_ts 2>; output-ohms = <2500>; full-ohms = <64000>; - #io-channel-cells = <0>; + #io-channel-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi index 7a3b96315eaf..d5baec5e7a78 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi @@ -14,6 +14,7 @@ / { memory@10000000 { reg = <0x10000000 0x40000000>; + device_type = "memory"; }; reg_3p3v: 3p3v { diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts index 4875afadb630..76b0007d20ad 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts @@ -35,7 +35,7 @@ iio-hwmon { compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; + io-channels = <&vdiv_vaccu 0>, <&vdiv_hitch_pos 0>; }; panel { @@ -84,7 +84,7 @@ }; }; - touch-thermal0 { + touch-0-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; @@ -98,7 +98,7 @@ }; }; - touch-thermal1 { + touch-1-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; @@ -147,7 +147,7 @@ io-channels = <&adc_ts 2>; output-ohms = <2500>; full-ohms = <64000>; - #io-channel-cells = <0>; + #io-channel-cells = <1>; }; vdiv_hitch_pos: voltage-divider-hitch-pos { @@ -155,7 +155,7 @@ io-channels = <&adc_ts 6>; output-ohms = <3300>; full-ohms = <13300>; - #io-channel-cells = <0>; + #io-channel-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi index 8bc6376d0dc1..4a5736526927 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi @@ -279,28 +279,32 @@ #size-cells = <0>; status = "disabled"; - led@0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <0>; - color = <LED_COLOR_ID_RED>; - }; + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + + led@0 { + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; - led@1 { - chan-name = "G"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <1>; - color = <LED_COLOR_ID_GREEN>; - }; + led@1 { + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; - led@2 { - chan-name = "B"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <2>; - color = <LED_COLOR_ID_BLUE>; + led@2 { + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts index 5c2cd517589b..0a6b668428a3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts @@ -21,6 +21,10 @@ status = "okay"; }; +&beeper { + status = "okay"; +}; + &lcd_display { status = "okay"; }; @@ -37,6 +41,10 @@ status = "okay"; }; +&pwm3 { + status = "okay"; +}; + ®_usb_h1_vbus { status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi index 2f42c56c21f6..6e49e1ccf6fc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi @@ -26,6 +26,12 @@ status = "disabled"; }; + beeper: beeper { + compatible = "pwm-beeper"; + pwms = <&pwm3 0 500000 0>; + status = "disabled"; + }; + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -272,28 +278,32 @@ #size-cells = <0>; status = "disabled"; - led@0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x6e>; - max-cur = /bits/ 8 <0xc8>; - reg = <0>; - color = <LED_COLOR_ID_RED>; - }; + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + + led@0 { + led-cur = /bits/ 8 <0x6e>; + max-cur = /bits/ 8 <0xc8>; + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; - led@1 { - chan-name = "G"; - led-cur = /bits/ 8 <0xbe>; - max-cur = /bits/ 8 <0xc8>; - reg = <1>; - color = <LED_COLOR_ID_GREEN>; - }; + led@1 { + led-cur = /bits/ 8 <0xbe>; + max-cur = /bits/ 8 <0xc8>; + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; - led@2 { - chan-name = "B"; - led-cur = /bits/ 8 <0xbe>; - max-cur = /bits/ 8 <0xc8>; - reg = <2>; - color = <LED_COLOR_ID_BLUE>; + led@2 { + led-cur = /bits/ 8 <0xbe>; + max-cur = /bits/ 8 <0xc8>; + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; }; }; @@ -466,6 +476,13 @@ >; }; + pinctrl_sound: soundgrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x8 + >; + }; + pinctrl_touch: touchgrp { fsl,pins = < MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 @@ -551,6 +568,12 @@ status = "disabled"; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sound>; + status = "disabled"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts index d3f14b4d3b51..929def2bb35e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts @@ -46,6 +46,7 @@ panel { compatible = "dataimage,fg1001l0dsswmg01"; backlight = <&backlight_lvds>; + power-supply = <®_lcd>; port { panel_in: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi index e1d0c6e123fd..1e2266a2368b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi @@ -195,6 +195,8 @@ mma8453: mma8453@1c { compatible = "fsl,mma8453"; reg = <0x1c>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; @@ -211,6 +213,8 @@ mpl3115: mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts index 299106fbe51c..13245af8f74d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts @@ -73,7 +73,7 @@ reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; }; - reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { + reg_pcie_power_on_gpio: regulator-pcie-power-on { compatible = "regulator-fixed"; regulator-name = "regulator-pcie-power-on-gpio"; regulator-min-microvolt = <3300000>; @@ -99,6 +99,34 @@ enable-active-high; }; + avdd_reg: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "avdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hpvdd_reg: regulator-hpvdd { + compatible = "regulator-fixed"; + regulator-name = "hpvdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + dcvdd_reg: regulator-dcvdd { + compatible = "regulator-fixed"; + regulator-name = "dcvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + dbvdd_reg: regulator-dbvdd { + compatible = "regulator-fixed"; + regulator-name = "dbvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + sound-analog { compatible = "simple-audio-card"; simple-audio-card,name = "On-board analog audio"; @@ -307,6 +335,10 @@ #sound-dai-cells = <0>; compatible = "wlf,wm8731"; reg = <0x1a>; + AVDD-supply = <&avdd_reg>; + HPVDD-supply = <&hpvdd_reg>; + DCVDD-supply = <&dcvdd_reg>; + DBVDD-supply = <&dbvdd_reg>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts index 17fabff80e90..cbe580dec182 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts @@ -236,9 +236,12 @@ vcc-supply = <&sw2_reg>; vio-supply = <&sw2_reg>; - stmpe_gpio1: stmpe_gpio { + stmpe_gpio1: gpio { #gpio-cells = <2>; compatible = "st,stmpe-gpio"; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; }; @@ -250,9 +253,12 @@ vcc-supply = <&sw2_reg>; vio-supply = <&sw2_reg>; - stmpe_gpio2: stmpe_gpio { + stmpe_gpio2: gpio { #gpio-cells = <2>; compatible = "st,stmpe-gpio"; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts index 78d941fef5df..c936180ed32a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts @@ -55,6 +55,13 @@ reg = <0x10000000 0x40000000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usbh1_vbus: regulator-usbhubreset { compatible = "regulator-fixed"; regulator-name = "usbh1_vbus"; @@ -81,6 +88,7 @@ panel { compatible = "sharp,lq101k1ly04"; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -124,7 +132,7 @@ pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>; status = "okay"; - eeprom: m95m02@1 { + eeprom: eeprom@1 { compatible = "st,m95m02", "atmel,at25"; size = <262144>; pagesize = <256>; @@ -134,7 +142,7 @@ }; pb_rtc: rtc@3 { - compatible = "nxp,rtc-pcf2123"; + compatible = "nxp,pcf2123"; spi-max-frequency = <2450000>; spi-cs-high; reg = <3>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts index 02aca1e28ce3..1ad3bdcea4a3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts @@ -16,6 +16,7 @@ panel { compatible = "ampire,am-1280800n3tzqw-t00h"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts index 241811c52b62..9e1c64da0b30 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts @@ -16,6 +16,7 @@ panel { compatible = "koe,tx31d200vm0baa"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts index 56b77cc0af2b..b8567167779c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts @@ -145,6 +145,7 @@ panel { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { @@ -324,8 +325,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts index fb81bd8ba035..73ed40ae5a7b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts @@ -57,6 +57,7 @@ panel { compatible = "kyo,tcg121xglp"; backlight = <&backlight_lcd>; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -72,6 +73,13 @@ regulator-max-microvolt = <1800000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_wifi: regulator-wifi { compatible = "regulator-fixed"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts index 5353a0c24420..3bd0e2c9e57a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts @@ -37,7 +37,7 @@ 3000 1>; }; - ir_recv { + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts index aae81feee00d..c78f101c3cc1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts @@ -326,11 +326,14 @@ &pcie { pcie@0,0 { reg = <0x000000 0 0 0 0>; + device_type = "pci"; #address-cells = <3>; #size-cells = <2>; + bus-range = <0x00 0xff>; + ranges; /* non-removable i211 ethernet card */ - eth1: intel,i211@pcie0,0 { + eth1: ethernet@0,0 { reg = <0x010000 0 0 0 0>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts index 18a620832a2a..a55644529c67 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "imx6q.dtsi" #include "imx6qdl-var-som.dtsi" #include <dt-bindings/pwm/pwm.h> diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts index ec6651ba4ba2..7332f2718982 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts @@ -17,6 +17,10 @@ }; }; +&beeper { + status = "okay"; +}; + &gpio_oled { status = "okay"; }; @@ -37,6 +41,10 @@ status = "okay"; }; +&pwm3 { + status = "okay"; +}; + ®_pu { regulator-always-on; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi index 419d85b5a660..8a0ce250e576 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi @@ -589,7 +589,7 @@ st,touch-det-delay = <5>; }; - stmpe_adc: stmpe_adc { + stmpe_adc: adc { compatible = "st,stmpe-adc"; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi index ea92b2b5c50d..e9d5bbb43145 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi @@ -462,7 +462,6 @@ regulator-ramp-delay = <7000>; regulator-boot-on; regulator-always-on; - linux,phandle = <®_vdd_arm>; }; /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi index b518bcb6b7a9..01f77142e153 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi @@ -360,7 +360,6 @@ regulator-ramp-delay = <7000>; regulator-boot-on; regulator-always-on; - linux,phandle = <®_vdd_arm>; }; /* VDD_SOC (1+R1/R2 = 1.635) */ @@ -372,7 +371,6 @@ regulator-ramp-delay = <7000>; regulator-boot-on; regulator-always-on; - linux,phandle = <®_vdd_soc>; }; /* VDD_1P0 (1+R1/R2 = 1.38): */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi index 8d471450d5c5..610b2a72fe82 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -127,6 +127,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; + power-supply = <®_3p3v>; port { panel_in_lvds0: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index c727aac257f9..ef0c26688446 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -135,13 +135,13 @@ i2c-parent = <&i2c2>; idle-state = <0>; - i2c2mux@1 { + i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; - i2c2mux@2 { + i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; @@ -158,7 +158,7 @@ i2c-parent = <&i2c3>; idle-state = <0>; - i2c3mux@1 { + i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -237,6 +237,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -248,6 +249,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; + power-supply = <®_3p3v>; port { panel_in_lvds0: endpoint { @@ -259,6 +261,7 @@ panel-lvds1 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds1>; + power-supply = <®_3p3v>; port { panel_in_lvds1: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi index 806af7f60419..03fe053880ca 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -114,6 +114,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -125,6 +126,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; + power-supply = <®_3p3v>; port { panel_in_lvds0: endpoint { @@ -136,6 +138,7 @@ panel-lvds1 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds1>; + power-supply = <®_3p3v>; port { panel_in_lvds1: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi index c71aa7498acf..6a353a99e13d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -179,6 +179,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -190,6 +191,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi index f7abc17c7c93..3b7d01065e87 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/imx6qdl-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/media/video-interfaces.h> / { chosen { @@ -207,6 +208,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -218,6 +220,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { @@ -360,7 +363,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ov5642>; clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-names = "xclk"; reg = <0x42>; reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; @@ -370,6 +372,7 @@ port { ov5642_to_ipu1_csi0_mux: endpoint { remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-type = <MEDIA_BUS_TYPE_PARALLEL>; bus-width = <8>; hsync-active = <1>; vsync-active = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index e8368c6b27ef..ba29720e3f72 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/imx6qdl-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/media/video-interfaces.h> / { chosen { @@ -17,6 +18,13 @@ reg = <0x10000000 0x40000000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -139,6 +147,7 @@ panel { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -278,7 +287,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ov5642>; clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; reg = <0x3c>; DOVDD-supply = <&vgen4_reg>; /* 1.8v */ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 @@ -291,6 +299,7 @@ port { ov5642_to_ipu1_csi0_mux: endpoint { remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-type = <MEDIA_BUS_TYPE_PARALLEL>; bus-width = <8>; hsync-active = <1>; vsync-active = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi index 6ab71a729fd8..c93dbc595ef6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -69,7 +69,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_switch>; interrupt-parent = <&gpio3>; - interrupt = <30 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; reg = <0>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi index f88da757edda..948b612496a5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi @@ -140,7 +140,7 @@ reg = <0x28>; #gpio-cells = <2>; gpio-controller; - ngpio = <32>; + ngpios = <32>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi index dd4e5bce4a55..8232f4ea2752 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi @@ -16,16 +16,19 @@ lcd-panel { compatible = "edt,et057090dhu"; + power-supply = <®_lcd1_pwr>; pixelclk-active = <0>; }; lvds0-panel { compatible = "edt,etml1010g0dka"; + power-supply = <®_lcd1_pwr>; pixelclk-active = <0>; }; lvds1-panel { compatible = "edt,etml1010g0dka"; + power-supply = <®_lcd1_pwr>; pixelclk-active = <0>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi index 2bff5f92242a..fef34ce961d5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi @@ -9,9 +9,6 @@ * Copyright 2022 Bootlin */ -/dts-v1/; - -#include "imx6q.dtsi" #include <dt-bindings/clock/imx6qdl-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/sound/fsl-imx-audmux.h> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts index 4a961a33bf2d..770a85e0561c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts @@ -17,6 +17,10 @@ }; }; +&beeper { + status = "okay"; +}; + &gpio_oled { status = "okay"; }; @@ -37,6 +41,10 @@ status = "okay"; }; +&pwm3 { + status = "okay"; +}; + ®_pu { regulator-always-on; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts index 2694fe18a91b..7cda1f21e418 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts @@ -227,7 +227,6 @@ }; &usbotg1 { - pinctrl-names = "default"; disable-over-current; srp-disable; hnp-disable; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts index a2534c422a52..f8709a952409 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts @@ -26,6 +26,11 @@ compatible = "kobo,tolino-vision5", "fsl,imx6sl"; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -59,6 +64,12 @@ >; }; + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */ @@ -159,6 +170,14 @@ >; }; + pinctrl_sy7636_gpio: sy7636-gpiogrp { + fsl,pins = < + MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* VCOM_CTRL */ + MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* PWR_GOOD */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 @@ -329,6 +348,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&sy7636 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sy7636_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts index 660620d226f7..19bbe60331b3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts @@ -36,6 +36,11 @@ soc-supply = <&dcdc1_reg>; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -69,6 +74,12 @@ >; }; + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ @@ -169,6 +180,14 @@ >; }; + pinctrl_sy7636_gpio: sy7636-gpiogrp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* VCOM_CTRL */ + MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x17059 /* PWR_GOOD */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 @@ -319,6 +338,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&sy7636 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sy7636_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index c7aeb99d8f00..3e238d8118fa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -119,7 +119,7 @@ regulator-always-on; }; - reg_pcie_gpio: regulator-pcie-gpio { + reg_pcie_gpio: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_reg>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 73c9cfbdba62..3d147b160ecf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -43,6 +43,13 @@ regulator-max-microvolt = <2800000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -157,6 +164,7 @@ panel { compatible = "innolux,at043tn24"; backlight = <&backlight_display>; + power-supply = <®_3v3>; port { panel_in: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi index 4c09bb312696..e34c8cbe36ae 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi @@ -122,15 +122,21 @@ VDDD-supply = <®_1p8v>; }; - stmpe811: gpio-expander@44 { + gpio-expander@44 { compatible = "st,stmpe811"; reg = <0x44>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_stmpe>; interrupt-parent = <&gpio1>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; + + gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; stmpe: touchscreen { compatible = "st,stmpe-ts"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts index fb206c1d8aca..fbab126f95b9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts @@ -49,5 +49,7 @@ pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts index b29713831a74..04e570d76e42 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts @@ -199,7 +199,7 @@ reg = <0x38>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - power-supply = <®_panel_3v3>; + vcc-supply = <®_panel_3v3>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi index 7ee25b141627..6fd68970c0b4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -126,7 +126,7 @@ s25fl064: flash@2 { #address-cells = <1>; #size-cells = <1>; - compatible = " jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <2>; spi-max-frequency = <40000000>; m25p,fast-read; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts index 7acd28658e6f..2192f105ec81 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts @@ -35,6 +35,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -61,6 +62,13 @@ enable-active-high; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_can2_3v3: regulator-can2-3v3 { compatible = "regulator-fixed"; regulator-name = "can2-3v3"; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts index 1b965652291b..347dd0fe4f82 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts @@ -49,6 +49,8 @@ pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index 17236f90ab33..a370e868cafe 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -406,6 +406,8 @@ mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_audio_3v3>; + vddio-supply = <®_audio_3v3>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts index 56dedd4fb8f0..92b6258059ee 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts @@ -31,6 +31,13 @@ }; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_peri_3p15v: regulator-peri-3p15v { compatible = "regulator-fixed"; regulator-name = "peri_3p15v_reg"; @@ -228,6 +235,8 @@ mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts b/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts index eff51e113db4..88d7dc005fa0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts @@ -92,7 +92,6 @@ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 >; - bias-pull-up; }; pinctrl_pwm0: pwm0grp { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts b/arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts index af59211842fb..ddb64f3d0471 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-amarula-rmm.dts @@ -112,6 +112,29 @@ enable-active-high; regulator-always-on; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx28-mrmmi-tlv320aic3x-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPROUT", + "Headphone Jack", "HPRCOM"; + simple-audio-card,mclk-fs = <512>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&saif0>; + clocks = <&saif0>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&tlv320aic3x>; + }; + }; }; &auart0 { @@ -154,6 +177,19 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + tlv320aic3x: audio-codec@18 { + compatible = "ti,tlv320aic3x"; + pinctrl-names = "default"; + pinctrl-0 = <&tlv320aic3x_pins>; + reg = <0x18>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + DVDD-supply = <®_1v8>; + IOVDD-supply = <®_3v3>; + AVDD-supply = <®_3v3>; + DRVDD-supply = <®_3v3>; + }; + touchscreen: touchscreen@38 { compatible = "edt,edt-ft5306"; reg = <0x38>; @@ -246,6 +282,14 @@ fsl,voltage = <MXS_VOLTAGE_HIGH>; }; + tlv320aic3x_pins: tlv320aic3x-pins@0 { + reg = <0>; + fsl,pinmux-ids = <MX28_PAD_SSP0_DATA4__GPIO_2_4>; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + }; + usb0_vbus_enable_pin: usb0-vbus-enable@0 { reg = <0>; fsl,pinmux-ids = <MX28_PAD_SSP0_DATA5__GPIO_2_5>; @@ -269,6 +313,12 @@ status = "okay"; }; +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + /* microSD */ &ssp0 { compatible = "fsl,imx28-mmc"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts index 08b50dc63923..80fe2916501a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts @@ -13,13 +13,37 @@ chassis-type = "handset"; aliases { + display0 = &framebuffer0; mmc0 = &sdhc_1; /* SDC1 eMMC slot */ mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &blsp1_uart3; }; chosen { - stdout-path = "serial0:115200n8"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + memory-region = <&cont_splash_region>; + + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; + }; }; gpio-hall-sensor { @@ -93,6 +117,11 @@ }; reserved-memory { + cont_splash_region: cont-splash@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + smem_region: smem@fa00000 { reg = <0x0fa00000 0x100000>; no-map; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts index 36f4c997b0b3..1df078d7d89b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts @@ -19,7 +19,7 @@ ext_l2: gpio-regulator { compatible = "regulator-fixed"; regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; + gpio = <&tlmm 91 0>; startup-delay-us = <10000>; enable-active-high; }; @@ -38,12 +38,12 @@ ethernet@0 { compatible = "micrel,ks8851"; reg = <0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <90 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency = <5400000>; vdd-supply = <&ext_l2>; vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; + reset-gpios = <&tlmm 89 0>; }; }; @@ -56,7 +56,7 @@ status = "okay"; }; -&msmgpio { +&tlmm { spi1_default: spi1-default-state { mosi-pins { pins = "gpio6"; @@ -90,7 +90,7 @@ }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &pm8921_keypad { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi deleted file mode 100644 index f18753e9f5ef..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&msmgpio { - i2c3_default_state: i2c3-default-state { - i2c3-pins { - pins = "gpio16", "gpio17"; - function = "gsbi3"; - drive-strength = <8>; - bias-disable; - }; - }; - - i2c3_sleep_state: i2c3-sleep-state { - i2c3-pins { - pins = "gpio16", "gpio17"; - function = "gpio"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - - sdcc3_default_state: sdcc3-default-state { - clk-pins { - pins = "sdc3_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "sdc3_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "sdc3_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - sdcc3_sleep_state: sdcc3-sleep-state { - clk-pins { - pins = "sdc3_clk"; - drive-strength = <2>; - bias-disable; - }; - - cmd-pins { - pins = "sdc3_cmd"; - drive-strength = <2>; - bias-pull-up; - }; - - data-pins { - pins = "sdc3_data"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index 49d117ea033a..5ee919dce75b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -31,7 +31,7 @@ key-home { label = "Home"; - gpios = <&msmgpio 40 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 40 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = <KEY_HOMEPAGE>; wakeup-event-action = <EV_ACT_ASSERTED>; @@ -40,14 +40,14 @@ key-volume-up { label = "Volume Up"; - gpios = <&msmgpio 50 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = <KEY_VOLUMEUP>; }; key-volume-down { label = "Volume Down"; - gpios = <&msmgpio 81 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = <KEY_VOLUMEDOWN>; }; @@ -102,7 +102,7 @@ touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; vdda-supply = <&pm8921_lvs6>; vdd-supply = <&pm8921_l17>; @@ -111,7 +111,7 @@ }; }; -&msmgpio { +&tlmm { spi1_default: spi1-default-state { mosi-pins { pins = "gpio6"; @@ -160,7 +160,7 @@ }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &rpm { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts index f2f59fc8b9b6..591dc837e600 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts @@ -54,7 +54,7 @@ }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &pm8921_gpio { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 6e272d5345a8..38bd4fd8dda5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -15,6 +15,35 @@ compatible = "qcom,msm8960"; interrupt-parent = <&intc>; + clocks { + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "cxo_board"; + }; + + pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "pxo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "sleep_clk"; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + qcom,no-pc-write; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -22,9 +51,9 @@ cpu@0 { compatible = "qcom,krait"; + reg = <0>; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; - reg = <0>; next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; @@ -32,9 +61,9 @@ cpu@1 { compatible = "qcom,krait"; + reg = <1>; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; - reg = <1>; next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; @@ -52,111 +81,29 @@ reg = <0x80000000 0>; }; - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsens 0>; - - trips { - cpu_alert0: trip0 { - temperature = <60000>; - hysteresis = <10000>; - type = "passive"; - }; - - cpu_crit0: trip1 { - temperature = <95000>; - hysteresis = <10000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsens 1>; - - trips { - cpu_alert1: trip0 { - temperature = <60000>; - hysteresis = <10000>; - type = "passive"; - }; - - cpu_crit1: trip1 { - temperature = <95000>; - hysteresis = <10000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - qcom,no-pc-write; - }; - - clocks { - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "cxo_board"; - }; - - pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "pxo_board"; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - soc: soc { + compatible = "simple-bus"; + ranges; #address-cells = <1>; #size-cells = <1>; - ranges; - compatible = "simple-bus"; - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; + rpm: rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", + "err", + "wakeup"; }; - timer@200a000 { - compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x80000>; + ssbi: ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; }; qfprom: efuse@700000 { @@ -174,26 +121,158 @@ }; }; - msmgpio: pinctrl@800000 { + tlmm: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; + reg = <0x800000 0x4000>; gpio-controller; - gpio-ranges = <&msmgpio 0 0 152>; + gpio-ranges = <&tlmm 0 0 152>; #gpio-cells = <2>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; - reg = <0x800000 0x4000>; + + i2c1_default_state: i2c1-default-state { + i2c1-pins { + pins = "gpio8", "gpio9"; + function = "gsbi1"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c1_sleep_state: i2c1-sleep-state { + i2c1-pins { + pins = "gpio8", "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c3_default_state: i2c3-default-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c3_sleep_state: i2c3-sleep-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c8_default_state: i2c8-default-state { + i2c8-pins { + pins = "gpio36", "gpio37"; + function = "gsbi8"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c8_sleep_state: i2c8-sleep-state { + i2c8-pins { + pins = "gpio36", "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c10_default_state: i2c10-default-state { + i2c10-pins { + pins = "gpio73", "gpio74"; + function = "gsbi10"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c10_sleep_state: i2c10-sleep-state { + i2c10-pins { + pins = "gpio73", "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c12_default_state: i2c12-default-state { + i2c12-pins { + pins = "gpio44", "gpio45"; + function = "gsbi12"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c12_sleep_state: i2c12-sleep-state { + i2c12-pins { + pins = "gpio44", "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + sdcc3_default_state: sdcc3-default-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdcc3_sleep_state: sdcc3-sleep-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8960", "syscon"; + reg = <0x900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - reg = <0x900000 0x4000>; clocks = <&cxo_board>, <&pxo_board>, <&lcc PLL4>; - clock-names = "cxo", "pxo", "pll4"; + clock-names = "cxo", + "pxo", + "pll4"; tsens: thermal-sensor { compatible = "qcom,msm8960-tsens"; @@ -208,49 +287,25 @@ }; }; - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-msm8960"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL4_VOTE>, - <0>, - <0>, <0>, - <0>, <0>, - <0>; - clock-names = "pxo", - "pll4_vote", - "mi2s_codec_clk", - "codec_i2s_mic_codec_clk", - "spare_i2s_mic_codec_clk", - "codec_i2s_spkr_codec_clk", - "spare_i2s_spkr_codec_clk", - "pcm_codec_clk"; + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; }; - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL3>, - <&gcc PLL8_VOTE>, - <0>, - <0>, - <0>, - <0>, - <0>; - clock-names = "pxo", - "pll3", - "pll8_vote", - "dsi1pll", - "dsi1pllbyte", - "dsi2pll", - "dsi2pllbyte", - "hdmipll"; + timer@200a000 { + compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; + reg = <0x0200a000 0x100>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; + clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; + cpu-offset = <0x80000>; }; l2cc: clock-controller@2011000 { @@ -261,17 +316,6 @@ #clock-cells = <0>; }; - rpm: rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; - }; - acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; @@ -281,15 +325,6 @@ #clock-cells = <0>; }; - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu1_aux"; - #clock-cells = <0>; - }; - saw0: power-manager@2089000 { compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; @@ -300,6 +335,15 @@ }; }; + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; + }; + saw1: power-manager@2099000 { compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; @@ -310,77 +354,34 @@ }; }; - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi8: gsbi@1a000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <8>; - reg = <0x1a000000 0x100>; - clocks = <&gcc GSBI8_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi8_serial: serial@1a040000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a040000 0x1000>, - <0x1a000000 0x1000>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI8_UART_CLK>, - <&gcc GSBI8_H_CLK>; - clock-names = "core", - "iface"; - - status = "disabled"; - }; - }; - - ssbi: ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; sdcc3: mmc@12180000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; reg = <0x12180000 0x2000>; + arm,primecell-periphid = <0x00051180>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -392,6 +393,8 @@ vmmc-supply = <&vsdcc_fixed>; dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names = "tx", "rx"; + + status = "disabled"; }; sdcc3bam: dma-controller@12182000 { @@ -405,10 +408,9 @@ }; sdcc1: mmc@12400000 { - status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; reg = <0x12400000 0x2000>; + arm,primecell-periphid = <0x00051180>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -420,6 +422,8 @@ vmmc-supply = <&vsdcc_fixed>; dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; dma-names = "tx", "rx"; + + status = "disabled"; }; sdcc1bam: dma-controller@12402000 { @@ -432,33 +436,32 @@ qcom,ee = <0>; }; - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8960", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gsbi1: gsbi@16000000 { + gsbi12: gsbi@12480000 { compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x16000000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; + reg = <0x12480000 0x100>; + ranges; + cell-index = <12>; + clocks = <&gcc GSBI12_H_CLK>; clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; - ranges; status = "disabled"; - gsbi1_spi: spi@16080000 { - compatible = "qcom,spi-qup-v1.1.1"; + gsbi12_i2c: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + pinctrl-0 = <&i2c12_default_state>; + pinctrl-1 = <&i2c12_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI12_QUP_CLK>, + <&gcc GSBI12_H_CLK>; + clock-names = "core", + "iface"; #address-cells = <1>; #size-cells = <0>; - reg = <0x16080000 0x1000>; - interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - cs-gpios = <&msmgpio 8 0>; - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; status = "disabled"; }; }; @@ -479,6 +482,7 @@ phys = <&usb_hs1_phy>; phy-names = "usb-phy"; #reset-cells = <1>; + status = "disabled"; ulpi { @@ -494,6 +498,51 @@ }; }; + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16000000 0x100>; + ranges; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi1_i2c: i2c@16080000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + pinctrl-0 = <&i2c1_default_state>; + pinctrl-1 = <&i2c1_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + cs-gpios = <&tlmm 8 0>; + clocks = <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + gsbi3: gsbi@16200000 { compatible = "qcom,gsbi-v1.0.0"; reg = <0x16200000 0x100>; @@ -503,6 +552,7 @@ clock-names = "iface"; #address-cells = <1>; #size-cells = <1>; + status = "disabled"; gsbi3_i2c: i2c@16280000 { @@ -514,12 +564,200 @@ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; + clock-names = "core", + "iface"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16400000 0x100>; + ranges; + cell-index = <5>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI5_UART_CLK>, + <&gcc GSBI5_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + + gsbi8: gsbi@1a000000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a000000 0x100>; + ranges; + cell-index = <8>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi8_serial: serial@1a040000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a040000 0x1000>, + <0x1a000000 0x1000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI8_UART_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + + gsbi8_i2c: i2c@1a080000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a080000 0x1000>; + pinctrl-0 = <&i2c8_default_state>; + pinctrl-1 = <&i2c8_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI8_QUP_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gsbi10: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a200000 0x100>; + ranges; + cell-index = <10>; + clocks = <&gcc GSBI10_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi10_i2c: i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + pinctrl-0 = <&i2c10_default_state>; + pinctrl-1 = <&i2c10_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI10_QUP_CLK>, + <&gcc GSBI10_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-msm8960"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 0>; + + trips { + cpu_alert0: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 1>; + + trips { + cpu_alert1: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; }; }; -#include "qcom-msm8960-pins.dtsi" diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index a1e4e9ac8f62..245c26bb8e03 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r7s72100"; #address-cells = <1>; #size-cells = <1>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -84,7 +85,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; }; rtc_x1_clk: rtc_x1 { @@ -103,7 +104,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/renesas/r7s9210.dtsi b/arch/arm/boot/dts/renesas/r7s9210.dtsi index fdeb0bc12cb7..2b349b51003b 100644 --- a/arch/arm/boot/dts/renesas/r7s9210.dtsi +++ b/arch/arm/boot/dts/renesas/r7s9210.dtsi @@ -52,7 +52,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi index 9083d288cc33..4220b2349b40 100644 --- a/arch/arm/boot/dts/renesas/r8a7742.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7742.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7742"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -208,19 +209,19 @@ pmu-0 { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; pmu-1 { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; @@ -234,7 +235,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1932,10 +1932,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7743.dtsi b/arch/arm/boot/dts/renesas/r8a7743.dtsi index 58a06cf37784..c697942387e1 100644 --- a/arch/arm/boot/dts/renesas/r8a7743.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7743.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7743"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -115,8 +116,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -130,7 +131,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1841,10 +1841,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7744.dtsi b/arch/arm/boot/dts/renesas/r8a7744.dtsi index 034244648d18..fed46345807c 100644 --- a/arch/arm/boot/dts/renesas/r8a7744.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7744.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7744"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -115,8 +116,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -130,7 +131,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1827,10 +1827,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7745.dtsi b/arch/arm/boot/dts/renesas/r8a7745.dtsi index 704fa6f3cbd0..5424a73562dd 100644 --- a/arch/arm/boot/dts/renesas/r8a7745.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7745.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7745"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -105,8 +106,8 @@ pmu { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -120,7 +121,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1631,10 +1631,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a77470.dtsi b/arch/arm/boot/dts/renesas/r8a77470.dtsi index a8a12275c98a..c61790e7667f 100644 --- a/arch/arm/boot/dts/renesas/r8a77470.dtsi +++ b/arch/arm/boot/dts/renesas/r8a77470.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a77470"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -66,8 +67,8 @@ pmu { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -81,7 +82,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1057,10 +1057,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index 4f97c09dbc9f..12cce9bdc449 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -16,6 +16,7 @@ compatible = "renesas,r8a7790"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -239,19 +240,19 @@ pmu-0 { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; pmu-1 { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; @@ -265,7 +266,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -2012,10 +2012,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index e9f90fa44d55..61ea438eb6af 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -301,6 +301,16 @@ clock-frequency = <12000000>; }; + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -383,13 +393,25 @@ }; composite-in@20 { - compatible = "adi,adv7180"; + compatible = "adi,adv7180cp"; reg = <0x20>; - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + remote-endpoint = <&vin1ep>; + }; }; }; }; @@ -900,7 +922,7 @@ port { vin1ep: endpoint { - remote-endpoint = <&adv7180>; + remote-endpoint = <&adv7180_out>; bus-width = <8>; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index 5023b41c28b3..35313e8da426 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -16,6 +16,7 @@ compatible = "renesas,r8a7791"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -137,8 +138,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -152,7 +153,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -1939,10 +1939,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 7513afc1c958..9e0de69ac3a3 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7792"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -94,8 +95,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -109,7 +110,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -992,10 +992,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts index 45b267ec2679..5c6928c941ac 100644 --- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -373,7 +373,6 @@ port@3 { reg = <3>; adv7180_out: endpoint { - bus-width = <8>; remote-endpoint = <&vin1ep>; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index fc6d3bcca296..1ad50070a1a7 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7793"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -122,8 +123,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -137,7 +138,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -1518,10 +1518,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index 92010d09f6c4..7669a67377c9 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -15,6 +15,7 @@ compatible = "renesas,r8a7794"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -104,8 +105,8 @@ pmu { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -119,7 +120,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -1485,10 +1485,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index 3258b2e27434..4a72aa7663f2 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -308,8 +308,6 @@ &switch { status = "okay"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 13a60656b044..8debb77803bb 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r9a06g032"; #address-cells = <1>; #size-cells = <1>; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -63,7 +64,6 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&gic>; ranges; rtc0: rtc@40006000 { @@ -290,6 +290,16 @@ status = "disabled"; }; + adc: adc@40065000 { + compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc"; + reg = <0x40065000 0x200>; + clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; + clock-names = "pclk", "adc"; + power-domains = <&sysctrl>; + #io-channel-cells = <1>; + status = "disabled"; + }; + pinctrl: pinctrl@40067000 { compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; reg = <0x40067000 0x1000>, <0x51000000 0x480>; @@ -522,7 +532,6 @@ timer { compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; arm,cpu-registers-not-fw-configured; always-on; interrupts = diff --git a/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts b/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts index 1ce07d0878dc..0a9cd61bcb5f 100644 --- a/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts @@ -209,6 +209,7 @@ reg = <0x1d>; interrupts-extended = <&irqpin3 2 IRQ_TYPE_LEVEL_HIGH>, <&irqpin3 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1", "INT2"; }; rtc@32 { diff --git a/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts index c227691013ea..65f8bc804d21 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts @@ -80,26 +80,33 @@ clock-frequency = <400000>; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + vcc5-supply = <&vcc_io>; vcc6-supply = <&vcc_io>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -107,7 +114,7 @@ regulator-always-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -115,42 +122,42 @@ regulator-always-on; }; - vcc18_cif: regulator@5 { + vcc18_cif: vdig1 { regulator-name = "vcc18_cif"; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-always-on; }; - vcc_18: regulator@8 { + vcc_18: vdac { regulator-name = "vcc_18"; regulator-always-on; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-always-on; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-always-on; }; - vcc_tp: regulator@11 { + vcc_tp: vaux33 { regulator-name = "vcc_tp"; regulator-always-on; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-always-on; }; @@ -158,9 +165,6 @@ }; }; -/* must be included after &tps gets defined */ -#include "../tps65910.dtsi" - &mmc0 { /* sdmmc */ status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts index de42d1855121..15dbe1677e30 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -96,11 +96,18 @@ clock-frequency = <400000>; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + vcc1-supply = <&vsys>; vcc2-supply = <&vsys>; vcc3-supply = <&vsys>; @@ -111,17 +118,17 @@ vccio-supply = <&vsys>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -129,7 +136,7 @@ regulator-always-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -137,41 +144,41 @@ regulator-always-on; }; - vcc18_cif: regulator@5 { + vcc18_cif: vdig1 { regulator-name = "vcc18_cif"; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-always-on; }; - vcc_18: regulator@8 { + vcc_18: vdac { regulator-name = "vcc_18"; regulator-always-on; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-always-on; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-always-on; }; - vcc_rmii: regulator@11 { + vcc_rmii: vaux33 { regulator-name = "vcc_rmii"; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-always-on; }; @@ -179,9 +186,6 @@ }; }; -/* must be included after &tps gets defined */ -#include "../tps65910.dtsi" - &emac { phy = <&phy0>; phy-supply = <&vcc_rmii>; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts index b0b029f14643..07c03ed6fac6 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts @@ -198,9 +198,18 @@ status = "okay"; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = <RK_PA4 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; pinctrl-0 = <&pmic_int>, <&pwr_hold>; @@ -214,19 +223,19 @@ vccio-supply = <&vsys>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -234,7 +243,7 @@ regulator-boot-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -242,52 +251,52 @@ regulator-boot-on; }; - vcc18: regulator@5 { + vcc18: vdig1 { regulator-name = "vcc18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - vccio_wl: regulator@8 { + vccio_wl: vdac { regulator-name = "vccio_wl"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_rmii: regulator@11 { + vcc_rmii: vaux33 { regulator-name = "vcc_rmii"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -296,8 +305,6 @@ }; }; -#include "../tps65910.dtsi" - &i2c2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi index 260d6c92cfd1..2d6cf08d00f9 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi @@ -388,7 +388,7 @@ rx-sample-delay-ns = <12>; - flash@0 { + spi_flash: flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 42d705b544ec..7477fc5da3ec 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -34,10 +34,6 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -745,9 +741,6 @@ #address-cells = <1>; #size-cells = <0>; - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - /* * Note: Although SCLK_* are the working clocks * of device without including on the NOC, needed for @@ -1197,6 +1190,8 @@ compatible = "rockchip,rk3288-dp"; reg = <0x0 0xff970000 0x0 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_EDP_24M>; + assigned-clock-parents = <&xin24m>; clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; phys = <&edp_phy>; diff --git a/arch/arm/boot/dts/samsung/exynos4210-i9100.dts b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts index df229fb8a16b..8a635bee59fa 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts @@ -853,6 +853,7 @@ #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; vmmc-supply = <&vtf_reg>; diff --git a/arch/arm/boot/dts/samsung/exynos4210-trats.dts b/arch/arm/boot/dts/samsung/exynos4210-trats.dts index 95e0e01b6ff6..6bd902cb8f4a 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-trats.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-trats.dts @@ -518,6 +518,7 @@ #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; vmmc-supply = <&tflash_reg>; diff --git a/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts index bdc30f8cf748..91490693432b 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts @@ -610,6 +610,7 @@ #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; vmmc-supply = <&ldo5_reg>; diff --git a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi index 05ddddb565ee..48245b1665a6 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi @@ -1440,6 +1440,7 @@ #address-cells = <1>; #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi index d56343f44fda..07da9b48ccac 100644 --- a/arch/arm/boot/dts/st/stih410.dtsi +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -34,6 +34,41 @@ status = "disabled"; }; + display-subsystem { + compatible = "st,sti-display-subsystem"; + ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>; + + assigned-clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>; + + assigned-clock-parents = <0>, + <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + + assigned-clock-rates = <297000000>, + <297000000>, + <0>, + <400000000>, + <400000000>; + }; + soc { ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; @@ -99,151 +134,174 @@ status = "disabled"; }; - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, + compositor: display-controller@9d11000 { + compatible = "st,stih407-compositor"; + reg = <0x9d11000 0x1000>; + + clock-names = "compo_main", + "compo_aux", + "pix_main", + "pix_aux", + "pix_gdp1", + "pix_gdp2", + "pix_gdp3", + "pix_gdp4", + "main_parent", + "aux_parent"; + + clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + reset-names = "compo-main", "compo-aux"; + resets = <&softreset STIH407_COMPO_SOFTRESET>, + <&softreset STIH407_COMPO_SOFTRESET>; + st,vtg = <&vtg_main>, <&vtg_aux>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + compo_main_out: endpoint { + remote-endpoint = <&tvout_in0>; + }; + }; + + port@1 { + reg = <1>; + compo_aux_out: endpoint { + remote-endpoint = <&tvout_in1>; + }; + }; + }; + }; + + tvout: encoder@8d08000 { + compatible = "st,stih407-tvout"; + reg = <0x8d08000 0x1000>; + reg-names = "tvout-reg"; + reset-names = "tvout"; + resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; + assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>; + + assigned-clock-parents = <&clk_s_d2_quadfs 0>, + <&clk_tmdsout_hdmi>, <&clk_s_d2_quadfs 0>, + <&clk_s_d0_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, - <297000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; + ports { #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tvout_in0: endpoint { + remote-endpoint = <&compo_main_out>; + }; + }; + + port@1 { + reg = <1>; + tvout_in1: endpoint { + remote-endpoint = <&compo_aux_out>; + }; + }; + + port@2 { + reg = <2>; + tvout_out0: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + + port@3 { + reg = <3>; + tvout_out1: endpoint { + remote-endpoint = <&hda_in>; + }; + }; }; + }; - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; + sti_hdmi: hdmi@8d04000 { + compatible = "st,stih407-hdmi"; + reg = <0x8d04000 0x1000>; + reg-names = "hdmi-reg"; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq"; + clock-names = "pix", + "tmds", + "phy", + "audio", + "main_parent", + "aux_parent"; + + clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; + reset-names = "hdmi"; + resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; + ddc = <&hdmiddc>; + + port { + hdmi_in: endpoint { + remote-endpoint = <&tvout_out0>; + }; }; + }; - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - status = "disabled"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; + analog@8d02000 { + compatible = "st,stih407-hda"; + status = "disabled"; + reg = <0x8d02000 0x400>, <0x92b0120 0x4>; + reg-names = "hda-reg", "video-dacs-ctrl"; + clock-names = "pix", + "hddac", + "main_parent", + "aux_parent"; + clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + port { + hda_in: endpoint { + remote-endpoint = <&tvout_out1>; + }; }; + }; - sti-hqvdp@9c00000 { - compatible = "st,stih407-hqvdp"; - reg = <0x9C00000 0x100000>; - clock-names = "hqvdp", "pix_main"; - clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; - reset-names = "hqvdp"; - resets = <&softreset STIH407_HDQVDP_SOFTRESET>; - st,vtg = <&vtg_main>; - }; + hqvdp: plane@9c00000 { + compatible = "st,stih407-hqvdp"; + reg = <0x9C00000 0x100000>; + clock-names = "hqvdp", "pix_main"; + clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; + reset-names = "hqvdp"; + resets = <&softreset STIH407_HDQVDP_SOFTRESET>; + st,vtg = <&vtg_main>; }; bdisp0:bdisp@9f10000 { diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index fd730aa37c22..b9657ff91c23 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -29,6 +29,12 @@ interrupt-parent = <&intc>; }; + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + firmware { optee { method = "smc"; @@ -1000,6 +1006,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; @@ -1657,6 +1664,16 @@ reg = <1>; }; }; + + iwdg1: watchdog@5c003000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5c003000 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc IWDG1>, <&scmi_clk CK_SCMI_LSI>; + clock-names = "pclk", "lsi"; + access-controllers = <&etzpc 12>; + status = "disabled"; + }; }; /* diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 9764a6bfa5b4..f894ee35b3db 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -161,6 +161,11 @@ }; }; +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + &crc1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi index 9eeb9d6b5eb0..7d3a6a3b5d09 100644 --- a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi @@ -374,9 +374,6 @@ baseboard_eeprom: &sip_eeprom { phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; - vusb_d-supply = <&vdd_usb>; - vusb_a-supply = <®18>; - status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi index bf0c32027baf..370b2afbf15b 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi @@ -185,13 +185,13 @@ interrupt-parent = <&gpioi>; vio-supply = <&v3v3>; vcc-supply = <&v3v3>; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; touchscreen { compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; st,ave-ctrl = <1>; st,touch-det-delay = <2>; st,settling = <2>; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index 154698f87b0e..ab13f0c39892 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -493,9 +493,6 @@ baseboard_eeprom: &sip_eeprom { phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; - vusb_d-supply = <&vdd_usb>; - vusb_a-supply = <®18>; - g-rx-fifo-size = <512>; g-np-tx-fifo-size = <32>; g-tx-fifo-size = <128 128 64 16 16 16 16 16>; diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile index 1aef60eef671..14e500846875 100644 --- a/arch/arm/boot/dts/ti/omap/Makefile +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-guardian.dtb \ am335x-icev2.dtb \ am335x-lxm.dtb \ + am335x-mba335x.dtb \ am335x-moxa-uc-2101.dtb \ am335x-moxa-uc-8100-me-t.dtb \ am335x-myirtech-myd.dtb \ diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi index 049fd8e1b40f..ed194469973e 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi @@ -17,18 +17,18 @@ compatible = "gpio-leds"; - led-power { + led_power: led-power { label = "onrisc:red:power"; linux,default-trigger = "default-on"; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; default-state = "on"; }; - led-wlan { + led_wlan: led-wlan { label = "onrisc:blue:wlan"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led-app { + led_app: led-app { label = "onrisc:green:app"; gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi index ea47f9960c35..afb38f023b83 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi @@ -45,6 +45,23 @@ startup-delay-us = <70000>; enable-active-high; }; + + mpcie_regulator: mpcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "mpcie-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 4 0>; + enable-active-high; + regulator-boot-on; + }; + + mpcie_power_switch: mpcie-power-switch { + compatible = "regulator-output"; + regulator-name = "mpcie-power-switch"; + regulator-supplies = "vcc"; + vout-supply = <&mpcie_regulator>; + }; }; &am33xx_pinmux { diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi index ad1e60a9b6fd..1d83fc116b66 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -16,7 +16,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { @@ -217,7 +217,7 @@ }; baseboard_eeprom: eeprom@50 { - compatible = "atmel,24c256"; + compatible = "atmel,24c32"; reg = <0x50>; vcc-supply = <&ldo4_reg>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts index f579df4c2c54..d430f0bef165 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts @@ -13,7 +13,7 @@ compatible = "ti,am335x-bone-blue", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts b/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts index 648e97fe1dfd..ae5bc5898497 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts @@ -12,7 +12,7 @@ "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/arch/arm/boot/dts/ti/omap/am335x-evm.dts b/arch/arm/boot/dts/ti/omap/am335x-evm.dts index 20222f82f21b..856fa1191ed2 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evm.dts @@ -23,7 +23,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; vbat: fixedregulator0 { diff --git a/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts index eba888dcd60e..d8baccdf8bc4 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts @@ -30,7 +30,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; vbat: fixedregulator0 { diff --git a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts index 4b070e634b28..6ce3a2d029ee 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -14,7 +14,7 @@ compatible = "bosch,am335x-guardian", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; tick-timer = &timer2; }; diff --git a/arch/arm/boot/dts/ti/omap/am335x-icev2.dts b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts index 6f0f4fba043b..ba488bba6925 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-icev2.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts @@ -22,7 +22,7 @@ }; chosen { - stdout-path = &uart3; + stdout-path = "serial3:115200n8"; }; vbat: fixedregulator0 { diff --git a/arch/arm/boot/dts/ti/omap/am335x-mba335x.dts b/arch/arm/boot/dts/ti/omap/am335x-mba335x.dts new file mode 100644 index 000000000000..8c0b2a1c99b1 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-mba335x.dts @@ -0,0 +1,633 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. + * Authors: Gregor Herburger, Matthias Schiffer + * + * Based on: + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "am335x-tqma335x.dtsi" + +/ { + model = "TQ-Systems TQMa335x[L] SoM on MBa335x carrier board"; + compatible = "tq,tqma3359-mba335x", "tq,tqma3359", "ti,am33xx"; + chassis-type = "embedded"; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 58 61 66 75 90 125 170 255>; + default-brightness-level = <7>; + enable-gpios = <&expander1 4 GPIO_ACTIVE_HIGH>; + power-supply = <®_mba335x_12v>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-s5 { + label = "S5"; + linux,code = <BTN_0>; + gpios = <&expander2 0 GPIO_ACTIVE_LOW>; + }; + + button-s6 { + label = "S6"; + linux,code = <BTN_1>; + gpios = <&expander2 1 GPIO_ACTIVE_LOW>; + }; + + button-s7 { + label = "S7"; + linux,code = <BTN_2>; + gpios = <&expander2 2 GPIO_ACTIVE_LOW>; + }; + }; + + reg_mba335x_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "MBa335x-V12"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "tqm-tlv320aic32"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Line", "Line Out", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Line Out", "LOL", + "Line Out", "LOR", + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "Line In", "IN1_L", + "Line In", "IN1_R"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + #sound-dai-cells = <0>; + system-clock-direction-out; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic32x4>; + system-clock-frequency = <24000000>; + system-clock-direction-out; + }; + }; +}; + +&am33xx_pinmux { + codec_pins: codec-pins { + pinctrl-single,pins = < + /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) + >; + }; + + cpsw_default_pins: cpsw-default-pins { + pinctrl-single,pins = < + /* Port 1 */ + /* mii1_tx_en.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rx_dv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_tx_clk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rx_clk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) + + /* Port 2 */ + /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a11.rgmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) + >; + }; + + cpsw_sleep_pins: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Port 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + + /* Port 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default_pins: davinci_mdio-default-pins { + pinctrl-single,pins = < + /* mdio.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + /* mdc.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep_pins: davinci_mdio-sleep-pins { + pinctrl-single,pins = < + /* mdio.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP, MUX_MODE7) + /* mdc.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + davinci_mdio_phy0_pins: davinci_mdio-phy0-pins { + pinctrl-single,pins = < + /* usb0_drvvbus.gpio0_18 - PHY interrupt */ + AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_INPUT, MUX_MODE7) + >; + }; + + davinci_mdio_phy1_pins: davinci_mdio-phy1-pins { + pinctrl-single,pins = < + /* gpmc_csn0.gpio1_29 - PHY interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) + >; + }; + + dcan0_pins: dcan0-pins { + pinctrl-single,pins = < + /* uart1_ctsn.d_can0_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* uart1_rtsn.d_can0_rx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + dcan1_pins: dcan1-pins { + pinctrl-single,pins = < + /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + ecap2_pins: ecap2-pins { + pinctrl-single,pins = < + /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE4) + >; + }; + + expander1_pins: expander1-pins { + pinctrl-single,pins = < + /* gpmc_csn3.gpio2_0 - interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE7 ) + >; + }; + + expander2_pins: expander2-pins { + pinctrl-single,pins = < + /* gpmc_ben1.gpio1_28 - interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + /* uart1_rxd.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE3) + /* uart1_txd.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE3) + >; + }; + + lcd_pins: lcd-pins { + pinctrl-single,pins = < + /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) + /* lcd_data0.lcd_data0 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + /* lcd_data1.lcd_data1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + /* lcd_data2.lcd_data2 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + /* lcd_data3.lcd_data3 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + /* lcd_data4.lcd_data4 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + /* lcd_data5.lcd_data5 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + /* lcd_data6.lcd_data6 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + /* lcd_data7.lcd_data7 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + /* lcd_data8.lcd_data8 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + /* lcd_data9.lcd_data9 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + /* lcd_data10.lcd_data10 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + /* lcd_data11.lcd_data11 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + /* lcd_data12.lcd_data12 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + /* lcd_data13.lcd_data13 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + /* lcd_data14.lcd_data14 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + /* lcd_data15.lcd_data15 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + /* lcd_vsync.lcd_vsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + /* lcd_hsync.lcd_hsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + /* lcd_pclk.lcd_pclk */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_aclkx.mcasp0_aclkx*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_axr1.mcasp0_axr1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_aclkr.mcasp0_aclkr */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_fsr.mcasp0_fsr */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + /* mmc0_dat3.mmc0_dat3 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat2.mmc0_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat1.mmc0_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat0.mmc0_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_cmd.mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + polytouch_pins: polytouch-pins { + pinctrl-single,pins = < + /* gpmc_clk.gpio2_1 - touch interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + /* uart0_rxd.uart0_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) + /* ecap0_in_pwm0_out.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins = < + /* gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) + /* gpmc_wpn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) + >; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default_pins>; + pinctrl-1 = <&davinci_mdio_sleep_pins>; + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_phy0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-ps = <1860>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_phy1_pins>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-ps = <1860>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; +}; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +&ds1339 { + interrupt-parent = <&expander2>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; +}; + +&ecap2 { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; +}; + +&i2c0 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&codec_pins>; + clocks = <&clk_24mhz>; + clock-names = "mclk"; + iov-supply = <&vcc3v3>; + ldoin-supply = <&vcc3v3>; + #sound-dai-cells = <0>; + }; + + jc42_2: temperature-sensor@19 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander1: gpio@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&expander1_pins>; + vcc-supply = <&vcc3v3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + + expander2: gpio@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&expander2_pins>; + vcc-supply = <&vcc3v3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom3: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + vcc-supply = <&vcc3v3>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +&lcdc { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + blue-and-red-wiring = "crossed"; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default_pins>; + pinctrl-1 = <&cpsw_sleep_pins>; + status = "okay"; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + #sound-dai-cells = <0>; + op-mode = <0>; + tdm-slots = <2>; + /* 16 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 2 1 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&tps { + interrupt-parent = <&expander2>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1 { + /* Should be "otg", but role switching currently doesn't work */ + dr_mode = "peripheral"; +}; + +/* SOM supply */ +&vcc3v3in { + vin-supply = <&vcc3v3>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts index 06a352f98b22..476a6bdaf43f 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts @@ -15,7 +15,7 @@ compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; clk12m: clk12m { diff --git a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts index f66d57bb685e..f0519ab30141 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts @@ -222,10 +222,10 @@ "ModeA1", "ModeA2", "ModeA3", - "NC", - "NC", - "NC", - "NC", + "ModeB0", + "ModeB1", + "ModeB2", + "ModeB3", "NC", "NC", "NC", diff --git a/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts index d28d39728847..23caaaabf351 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts @@ -147,7 +147,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts index c9ccb9de21ad..9f611debc209 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -21,7 +21,7 @@ compatible = "ti,am33xx"; chosen { - stdout-path = &uart3; + stdout-path = "serial3:115200n8"; }; cpus { diff --git a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts index e7d561a527fd..10d54e0ad15a 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts @@ -347,7 +347,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wireless_pins>; - vmmmc-supply = <&v3v3c_reg>; + vmmc-supply = <&v3v3c_reg>; bus-width = <4>; non-removable; dmas = <&edma_xbar 12 0 1 diff --git a/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts index 78ce860e59b3..24d9f90fad01 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts @@ -15,7 +15,7 @@ compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts index 7c9f65126c63..8b47f45a9959 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts @@ -87,7 +87,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts index f3524e5ee43e..1dc4e344efd6 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -25,7 +25,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/arch/arm/boot/dts/ti/omap/am335x-tqma335x.dtsi b/arch/arm/boot/dts/ti/omap/am335x-tqma335x.dtsi new file mode 100644 index 000000000000..b75949f0f023 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-tqma335x.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. + * Authors: Gregor Herburger, Matthias Schiffer + * + * Based on: + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include "am33xx.dtsi" + +/ { + compatible = "tq,tqma3359", "ti,am33xx"; + + aliases { + mmc0 = &mmc2; + mmc1 = &mmc1; + /delete-property/ mmc2; + rtc0 = &tps; + rtc1 = &ds1339; + rtc2 = &rtc; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* SOM input voltage */ + vcc3v3in: regulator-vcc3v3in { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3IN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* + * Regulator is enabled by PMIC power sequence. The supplied voltage + * rail is also usable on baseboard. + */ + vddshv: regulator-vddshv { + compatible = "regulator-fixed"; + regulator-name = "VDDSHV"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc3v3in>; + }; +}; + +&am33xx_pinmux { + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) + /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + /* spi0_sclk.spi0_sclk */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + /* spi0_d0.spi0_d0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* spi0_d1.spi0_d1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE0) + /* spi0_cs0.spi0_cs0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) + >; + }; +}; + +&cpu { + cpu0-supply = <&vdd1_reg>; +}; + +&elm { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + /* optional, not on TQMa335xL */ + jc42_1: temperature-sensor@1f { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1f>; + }; + + tps: pmic@2d { + reg = <0x2d>; + ti,en-ck32k-xtal; + /* Filled in by tps65910.dtsi */ + }; + + /* optional, not on TQMa335xL */ + eeprom: eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&vddshv>; + }; + + /* optional, not on TQMa335xL */ + se97btp: eeprom@57 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + vcc-supply = <&vddshv>; + }; + + /* optional, not on TQMa335xL */ + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +#include "../../tps65910.dtsi" + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + bus-width = <8>; + no-1-8-v; + no-sd; + no-sdio; + vmmc-supply = <&vddshv>; + non-removable; + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&tps { + vcc1-supply = <&vcc3v3in>; + vcc2-supply = <&vcc3v3in>; + vcc3-supply = <&vcc3v3in>; + vcc4-supply = <&vcc3v3in>; + vcc5-supply = <&vcc3v3in>; + vcc6-supply = <&vcc3v3in>; + vcc7-supply = <&vcc3v3in>; + vccio-supply = <&vcc3v3in>; +}; + +/* TPS outputs */ +&vrtc_reg { + regulator-always-on; +}; + +&vio_reg { + regulator-always-on; +}; + +&vdd1_reg { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; +}; + +&vdd2_reg { + regulator-name = "vdd_core"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; +}; + +&vdd3_reg { + regulator-always-on; +}; + +&vdig1_reg { + regulator-always-on; +}; + +&vdig2_reg { + regulator-always-on; +}; + +&vpll_reg { + regulator-always-on; +}; + +&vdac_reg { + regulator-always-on; +}; + +&vaux1_reg { + regulator-always-on; +}; + +&vaux2_reg { + regulator-always-on; +}; + +&vaux33_reg { + regulator-always-on; +}; + +&vmmc_reg { + regulator-always-on; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <24000000>; + vcc-supply = <&vddshv>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&usb0_phy { + vcc-supply = <&vaux1_reg>; +}; + +&usb1_phy { + vcc-supply = <&vaux1_reg>; +}; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi index 18ad52e93955..89d16fcc773e 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -1501,7 +1501,6 @@ mmc1: mmc@0 { compatible = "ti,am335-sdhci"; - ti,needs-special-reset; dmas = <&edma 24 0>, <&edma 25 0>; dma-names = "tx", "rx"; interrupts = <64>; @@ -1987,7 +1986,6 @@ mmc2: mmc@0 { compatible = "ti,am335-sdhci"; - ti,needs-special-reset; dmas = <&edma 2 0 &edma 3 0>; dma-names = "tx", "rx"; diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi index 43ec2a95f4bb..ca3e7f5d7d0d 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -45,7 +45,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu: cpu@0 { compatible = "arm,cortex-a8"; enable-method = "ti,am3352"; device_type = "cpu"; @@ -338,7 +338,6 @@ mmc3: mmc@0 { compatible = "ti,am335-sdhci"; - ti,needs-special-reset; interrupts = <29>; reg = <0x0 0x1000>; status = "disabled"; diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi index 0a1df30f2818..504fa6b57d39 100644 --- a/arch/arm/boot/dts/ti/omap/am4372.dtsi +++ b/arch/arm/boot/dts/ti/omap/am4372.dtsi @@ -321,7 +321,6 @@ mmc3: mmc@0 { compatible = "ti,am437-sdhci"; - ti,needs-special-reset; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0x1000>; status = "disabled"; diff --git a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi index fd4634f8c629..e08f356e71cb 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi @@ -1103,7 +1103,6 @@ mmc1: mmc@0 { compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; - ti,needs-special-reset; dmas = <&edma 24 0>, <&edma 25 0>; dma-names = "tx", "rx"; @@ -1620,7 +1619,6 @@ mmc2: mmc@0 { compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; - ti,needs-special-reset; dmas = <&edma 2 0>, <&edma 3 0>; dma-names = "tx", "rx"; diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts index e6a18954e449..43cf4ade950b 100644 --- a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts @@ -545,7 +545,6 @@ non-removable; mmc-pwrseq = <&emmc_pwrseq>; - ti,needs-special-reset; dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; dma-names = "tx", "rx"; @@ -561,7 +560,6 @@ /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ status = "okay"; - ti,needs-special-reset; vmmc-supply = <&vdd_3v3>; cap-power-off-card; keep-power-in-suspend; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts index 3dd898955e76..77c9fbb3bfbd 100644 --- a/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts @@ -481,7 +481,6 @@ vmmc-supply = <&vdd_3v3>; bus-width = <8>; ti,non-removable; - cap-mmc-dual-data-rate; }; &qspi { diff --git a/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts index 08ee0f8ea68f..71b39a923d37 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts @@ -291,7 +291,7 @@ }; twl_power: power { - compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; + compatible = "ti,twl4030-power-idle-osc-off"; ti,use_poweroff; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap3-n900.dts b/arch/arm/boot/dts/ti/omap/omap3-n900.dts index c50ca572d1b9..7db73d9bed9e 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-n900.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-n900.dts @@ -508,7 +508,7 @@ }; twl_power: power { - compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; + compatible = "ti,twl4030-power-idle-osc-off"; ti,use_poweroff; }; }; |