diff options
Diffstat (limited to 'arch/arm64/include/asm/el2_setup.h')
| -rw-r--r-- | arch/arm64/include/asm/el2_setup.h | 38 | 
1 files changed, 32 insertions, 6 deletions
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index b37da3ee8529..99a7c0235e6d 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -24,22 +24,48 @@  	 * ID_AA64MMFR4_EL1.E2H0 < 0. On such CPUs HCR_EL2.E2H is RES1, but it  	 * can reset into an UNKNOWN state and might not read as 1 until it has  	 * been initialized explicitly. -	 * -	 * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but -	 * don't advertise it (they predate this relaxation). -	 *  	 * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H  	 * indicating whether the CPU is running in E2H mode.  	 */  	mrs_s	x1, SYS_ID_AA64MMFR4_EL1  	sbfx	x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH  	cmp	x1, #0 -	b.ge	.LnVHE_\@ +	b.lt	.LnE2H0_\@ +	/* +	 * Unfortunately, HCR_EL2.E2H can be RES1 even if not advertised +	 * as such via ID_AA64MMFR4_EL1.E2H0: +	 * +	 * - Fruity CPUs predate the !FEAT_E2H0 relaxation, and seem to +	 *   have HCR_EL2.E2H implemented as RAO/WI. +	 * +	 * - On CPUs that lack FEAT_FGT, a hypervisor can't trap guest +	 *   reads of ID_AA64MMFR4_EL1 to advertise !FEAT_E2H0. NV +	 *   guests on these hosts can write to HCR_EL2.E2H without +	 *   trapping to the hypervisor, but these writes have no +	 *   functional effect. +	 * +	 * Handle both cases by checking for an essential VHE property +	 * (system register remapping) to decide whether we're +	 * effectively VHE-only or not. +	 */ +	msr_hcr_el2 x0		// Setup HCR_EL2 as nVHE +	isb +	mov	x1, #1		// Write something to FAR_EL1 +	msr	far_el1, x1 +	isb +	mov	x1, #2		// Try to overwrite it via FAR_EL2 +	msr	far_el2, x1 +	isb +	mrs	x1, far_el1	// If we see the latest write in FAR_EL1, +	cmp	x1, #2		// we can safely assume we are VHE only. +	b.ne	.LnVHE_\@	// Otherwise, we know that nVHE works. + +.LnE2H0_\@:  	orr	x0, x0, #HCR_E2H -.LnVHE_\@:  	msr_hcr_el2 x0  	isb +.LnVHE_\@:  .endm  .macro __init_el2_sctlr  | 
