diff options
Diffstat (limited to 'drivers/media/platform/mediatek')
21 files changed, 950 insertions, 526 deletions
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index 834d2a354692..7eb12449b63a 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -1026,6 +1026,7 @@ static void mtk_jpeg_dec_device_run(void *priv) spin_lock_irqsave(&jpeg->hw_lock, flags); mtk_jpeg_dec_reset(jpeg->reg_base); mtk_jpeg_dec_set_config(jpeg->reg_base, + jpeg->variant->support_34bit, &jpeg_src_buf->dec_param, jpeg_src_buf->bs_size, &bs, @@ -1570,7 +1571,8 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg) src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base); + result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base, + jpeg->variant->support_34bit); vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size); buf_state = VB2_BUF_STATE_DONE; @@ -1770,6 +1772,7 @@ retry_select: ctx->total_frame_num++; mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, + jpeg->variant->support_34bit, &jpeg_src_buf->dec_param, jpeg_src_buf->bs_size, &bs, diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h index 8877eb39e807..02ed0ed5b736 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -34,6 +34,8 @@ #define MTK_JPEG_MAX_EXIF_SIZE (64 * 1024) +#define MTK_JPEG_ADDR_MASK GENMASK(1, 0) + /** * enum mtk_jpeg_ctx_state - states of the context state machine * @MTK_JPEG_INIT: current state is initialized @@ -62,6 +64,7 @@ enum mtk_jpeg_ctx_state { * @cap_q_default_fourcc: capture queue default fourcc * @multi_core: mark jpeg hw is multi_core or not * @jpeg_worker: jpeg dec or enc worker + * @support_34bit: flag to check support for 34-bit DMA address */ struct mtk_jpeg_variant { struct clk_bulk_data *clks; @@ -78,6 +81,7 @@ struct mtk_jpeg_variant { u32 cap_q_default_fourcc; bool multi_core; void (*jpeg_worker)(struct work_struct *work); + bool support_34bit; }; struct mtk_jpeg_src_buf { diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index 2c5d74939d0a..e78e1d11093c 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -5,6 +5,8 @@ * Rick Chang <rick.chang@mediatek.com> */ +#include <linux/bitfield.h> +#include <linux/bits.h> #include <linux/clk.h> #include <linux/interrupt.h> #include <linux/irq.h> @@ -279,23 +281,43 @@ static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, writel(val, base + JPGDEC_REG_BRZ_FACTOR); } -static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y, - u32 addr_u, u32 addr_v) +static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, bool support_34bit, + dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v) { + u32 val; + mtk_jpeg_verify_align(addr_y, 16, JPGDEC_REG_DEST_ADDR0_Y); - writel(addr_y, base + JPGDEC_REG_DEST_ADDR0_Y); + writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR0_Y); mtk_jpeg_verify_align(addr_u, 16, JPGDEC_REG_DEST_ADDR0_U); - writel(addr_u, base + JPGDEC_REG_DEST_ADDR0_U); + writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR0_U); mtk_jpeg_verify_align(addr_v, 16, JPGDEC_REG_DEST_ADDR0_V); - writel(addr_v, base + JPGDEC_REG_DEST_ADDR0_V); + writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR0_V); + if (support_34bit) { + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y)); + writel(val, base + JPGDEC_REG_DEST_ADDR0_Y_EXT); + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u)); + writel(val, base + JPGDEC_REG_DEST_ADDR0_U_EXT); + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v)); + writel(val, base + JPGDEC_REG_DEST_ADDR0_V_EXT); + } } -static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y, - u32 addr_u, u32 addr_v) +static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, bool support_34bit, + dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v) { - writel(addr_y, base + JPGDEC_REG_DEST_ADDR1_Y); - writel(addr_u, base + JPGDEC_REG_DEST_ADDR1_U); - writel(addr_v, base + JPGDEC_REG_DEST_ADDR1_V); + u32 val; + + writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR1_Y); + writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR1_U); + writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR1_V); + if (support_34bit) { + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y)); + writel(val, base + JPGDEC_REG_DEST_ADDR1_Y_EXT); + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u)); + writel(val, base + JPGDEC_REG_DEST_ADDR1_U_EXT); + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v)); + writel(val, base + JPGDEC_REG_DEST_ADDR1_V_EXT); + } } static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y, @@ -322,18 +344,30 @@ static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode) writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE); } -static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr) +static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, bool support_34bit, dma_addr_t ptr) { + u32 val; + mtk_jpeg_verify_align(ptr, 16, JPGDEC_REG_FILE_BRP); - writel(ptr, base + JPGDEC_REG_FILE_BRP); + writel(lower_32_bits(ptr), base + JPGDEC_REG_FILE_BRP); + if (support_34bit) { + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(ptr)); + writel(val, base + JPGDEC_REG_FILE_BRP_EXT); + } } -static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size, - u32 bitstream_size) +static void mtk_jpeg_dec_set_bs_info(void __iomem *base, bool support_34bit, + dma_addr_t addr, u32 size, u32 bitstream_size) { + u32 val; + mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR); mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE); - writel(addr, base + JPGDEC_REG_FILE_ADDR); + writel(lower_32_bits(addr), base + JPGDEC_REG_FILE_ADDR); + if (support_34bit) { + val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr)); + writel(val, base + JPGDEC_REG_FILE_ADDR_EXT); + } writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE); writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE); } @@ -404,6 +438,7 @@ static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num, } void mtk_jpeg_dec_set_config(void __iomem *base, + bool support_34bits, struct mtk_jpeg_dec_param *cfg, u32 bitstream_size, struct mtk_jpeg_bs *bs, @@ -413,8 +448,8 @@ void mtk_jpeg_dec_set_config(void __iomem *base, mtk_jpeg_dec_set_dec_mode(base, 0); mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num); mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu); - mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size, bitstream_size); - mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr); + mtk_jpeg_dec_set_bs_info(base, support_34bits, bs->str_addr, bs->size, bitstream_size); + mtk_jpeg_dec_set_bs_write_ptr(base, support_34bits, bs->end_addr); mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1, (cfg->comp_num == 1) ? 1 : 0); mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1], @@ -432,9 +467,9 @@ void mtk_jpeg_dec_set_config(void __iomem *base, cfg->mem_stride[1]); mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0], cfg->img_stride[1]); - mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0], + mtk_jpeg_dec_set_dst_bank0(base, support_34bits, fb->plane_addr[0], fb->plane_addr[1], fb->plane_addr[2]); - mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0); + mtk_jpeg_dec_set_dst_bank1(base, support_34bits, 0, 0, 0); mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group, cfg->dma_last_mcu); mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h index 8c31c6b12417..2948c9c300a4 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h @@ -71,6 +71,7 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param); u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base); u32 mtk_jpeg_dec_enum_result(u32 irq_result); void mtk_jpeg_dec_set_config(void __iomem *base, + bool support_34bits, struct mtk_jpeg_dec_param *cfg, u32 bitstream_size, struct mtk_jpeg_bs *bs, diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h index 27b7711ca341..e94f52de7c69 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h @@ -46,5 +46,13 @@ #define JPGDEC_REG_INTERRUPT_STATUS 0x0274 #define JPGDEC_REG_STATUS 0x0278 #define JPGDEC_REG_BIT_STREAM_SIZE 0x0344 +#define JPGDEC_REG_DEST_ADDR0_Y_EXT 0x0360 +#define JPGDEC_REG_DEST_ADDR0_U_EXT 0x0364 +#define JPGDEC_REG_DEST_ADDR0_V_EXT 0x0368 +#define JPGDEC_REG_DEST_ADDR1_Y_EXT 0x036c +#define JPGDEC_REG_DEST_ADDR1_U_EXT 0x0370 +#define JPGDEC_REG_DEST_ADDR1_V_EXT 0x0374 +#define JPGDEC_REG_FILE_ADDR_EXT 0x0378 +#define JPGDEC_REG_FILE_BRP_EXT 0x037c #endif /* _MTK_JPEG_REG_H */ diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index f8fa3b841ccf..9ab27aee302a 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -5,6 +5,8 @@ * */ +#include <linux/bitfield.h> +#include <linux/bits.h> #include <linux/clk.h> #include <linux/interrupt.h> #include <linux/irq.h> @@ -62,9 +64,9 @@ void mtk_jpeg_enc_reset(void __iomem *base) } EXPORT_SYMBOL_GPL(mtk_jpeg_enc_reset); -u32 mtk_jpeg_enc_get_file_size(void __iomem *base) +u32 mtk_jpeg_enc_get_file_size(void __iomem *base, bool support_34bit) { - return readl(base + JPEG_ENC_DMA_ADDR0) - + return (readl(base + JPEG_ENC_DMA_ADDR0) << ((support_34bit) ? 2 : 0)) - readl(base + JPEG_ENC_DST_ADDR0); } EXPORT_SYMBOL_GPL(mtk_jpeg_enc_get_file_size); @@ -84,14 +86,24 @@ void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base, { int i; dma_addr_t dma_addr; + u32 addr_ext; + bool support_34bit = ctx->jpeg->variant->support_34bit; for (i = 0; i < src_buf->num_planes; i++) { dma_addr = vb2_dma_contig_plane_dma_addr(src_buf, i) + src_buf->planes[i].data_offset; - if (!i) - writel(dma_addr, base + JPEG_ENC_SRC_LUMA_ADDR); + if (i == 0) + writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_LUMA_ADDR); else - writel(dma_addr, base + JPEG_ENC_SRC_CHROMA_ADDR); + writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_CHROMA_ADDR); + + if (support_34bit) { + addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr)); + if (i == 0) + writel(addr_ext, base + JPEG_ENC_SRC_LUMA_ADDR_EXT); + else + writel(addr_ext, base + JPEG_ENC_SRC_CHRO_ADDR_EXT); + } } } EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_src); @@ -103,6 +115,8 @@ void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base, size_t size; u32 dma_addr_offset; u32 dma_addr_offsetmask; + u32 addr_ext; + bool support_34bit = ctx->jpeg->variant->support_34bit; dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0); dma_addr_offset = ctx->enable_exif ? MTK_JPEG_MAX_EXIF_SIZE : 0; @@ -113,6 +127,12 @@ void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base, writel(dma_addr_offsetmask & 0xf, base + JPEG_ENC_BYTE_OFFSET_MASK); writel(dma_addr & ~0xf, base + JPEG_ENC_DST_ADDR0); writel((dma_addr + size) & ~0xf, base + JPEG_ENC_STALL_ADDR0); + + if (support_34bit) { + addr_ext = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(dma_addr)); + writel(addr_ext, base + JPEG_ENC_DEST_ADDR0_EXT); + writel(addr_ext + size, base + JPEG_ENC_STALL_ADDR0_EXT); + } } EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_dst); @@ -278,7 +298,8 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) if (!(irq_status & JPEG_ENC_INT_STATUS_DONE)) dev_warn(jpeg->dev, "Jpg Enc occurs unknown Err."); - result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base); + result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base, + ctx->jpeg->variant->support_34bit); vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size); buf_state = VB2_BUF_STATE_DONE; v4l2_m2m_buf_done(src_buf, buf_state); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h index 61c60e4e58ea..31ec9030ae88 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h @@ -68,6 +68,11 @@ #define JPEG_ENC_DCM_CTRL 0x300 #define JPEG_ENC_CODEC_SEL 0x314 #define JPEG_ENC_ULTRA_THRES 0x318 +#define JPEG_ENC_SRC_LUMA_ADDR_EXT 0x584 +#define JPEG_ENC_SRC_CHRO_ADDR_EXT 0x588 +#define JPEG_ENC_Q_TBL_ADDR_EXT 0x58C +#define JPEG_ENC_DEST_ADDR0_EXT 0x590 +#define JPEG_ENC_STALL_ADDR0_EXT 0x594 /** * struct mtk_jpeg_enc_qlt - JPEG encoder quality data @@ -80,7 +85,7 @@ struct mtk_jpeg_enc_qlt { }; void mtk_jpeg_enc_reset(void __iomem *base); -u32 mtk_jpeg_enc_get_file_size(void __iomem *base); +u32 mtk_jpeg_enc_get_file_size(void __iomem *base, bool support_34bit); void mtk_jpeg_enc_start(void __iomem *enc_reg_base); void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base, struct vb2_buffer *src_buf); diff --git a/drivers/media/platform/mediatek/mdp/mtk_mdp_m2m.c b/drivers/media/platform/mediatek/mdp/mtk_mdp_m2m.c index 28c998bd3a81..d0fd77dcf8e2 100644 --- a/drivers/media/platform/mediatek/mdp/mtk_mdp_m2m.c +++ b/drivers/media/platform/mediatek/mdp/mtk_mdp_m2m.c @@ -342,7 +342,7 @@ static int mtk_mdp_try_crop(struct mtk_mdp_ctx *ctx, u32 type, if (r->left & 1) r->left -= 1; - mtk_mdp_dbg(2, "[%d] crop l,t,w,h:%d,%d,%d,%d, max:%dx%d", ctx->id, + mtk_mdp_dbg(2, "[%d] crop (%d,%d)/%ux%u, max:%dx%d", ctx->id, r->left, r->top, r->width, r->height, max_w, max_h); return 0; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index ea2ea119dd2a..e5ccf673e152 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -114,19 +114,15 @@ static struct img_config *__get_config_offset(struct mdp_dev *mdp, if (pp_idx >= mdp->mdp_data->pp_used) goto err_param; - if (CFG_CHECK(MT8183, p_id)) + if (CFG_CHECK(MT8183, p_id)) { cfg_c = CFG_OFST(MT8183, param->config, pp_idx); - else if (CFG_CHECK(MT8195, p_id)) - cfg_c = CFG_OFST(MT8195, param->config, pp_idx); - else - goto err_param; - - if (CFG_CHECK(MT8183, p_id)) cfg_n = CFG_OFST(MT8183, param->config, pp_idx + 1); - else if (CFG_CHECK(MT8195, p_id)) + } else if (CFG_CHECK(MT8195, p_id)) { + cfg_c = CFG_OFST(MT8195, param->config, pp_idx); cfg_n = CFG_OFST(MT8195, param->config, pp_idx + 1); - else + } else { goto err_param; + } if ((long)cfg_n - (long)mdp->vpu.config > bound) { dev_err(dev, "config offset %ld OOB %ld\n", (long)cfg_n, bound); @@ -325,8 +321,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, /* Enable mux settings */ for (index = 0; index < ctrl->num_sets; index++) { set = &ctrl->sets[index]; - cmdq_pkt_write_mask(&cmd->pkt, set->subsys_id, set->reg, - set->value, 0xFFFFFFFF); + cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, set->value); } /* Config sub-frame information */ for (index = (num_comp - 1); index >= 0; index--) { @@ -381,8 +376,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, /* Disable mux settings */ for (index = 0; index < ctrl->num_sets; index++) { set = &ctrl->sets[index]; - cmdq_pkt_write_mask(&cmd->pkt, set->subsys_id, set->reg, - 0, 0xFFFFFFFF); + cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, 0); } return 0; @@ -471,43 +465,6 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, return 0; } -static int mdp_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, - size_t size) -{ - struct device *dev; - dma_addr_t dma_addr; - - pkt->va_base = kzalloc(size, GFP_KERNEL); - if (!pkt->va_base) - return -ENOMEM; - - pkt->buf_size = size; - pkt->cl = (void *)client; - - dev = client->chan->mbox->dev; - dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, - DMA_TO_DEVICE); - if (dma_mapping_error(dev, dma_addr)) { - dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); - kfree(pkt->va_base); - return -ENOMEM; - } - - pkt->pa_base = dma_addr; - - return 0; -} - -static void mdp_cmdq_pkt_destroy(struct cmdq_pkt *pkt) -{ - struct cmdq_client *client = (struct cmdq_client *)pkt->cl; - - dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, - DMA_TO_DEVICE); - kfree(pkt->va_base); - pkt->va_base = NULL; -} - static void mdp_auto_release_work(struct work_struct *work) { struct mdp_cmdq_cmd *cmd; @@ -538,7 +495,7 @@ static void mdp_auto_release_work(struct work_struct *work) wake_up(&mdp->callback_wq); } - mdp_cmdq_pkt_destroy(&cmd->pkt); + cmdq_pkt_destroy(mdp->cmdq_clt[cmd->pp_idx], &cmd->pkt); kfree(cmd->comps); cmd->comps = NULL; kfree(cmd); @@ -578,7 +535,7 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) if (refcount_dec_and_test(&mdp->job_count)) wake_up(&mdp->callback_wq); - mdp_cmdq_pkt_destroy(&cmd->pkt); + cmdq_pkt_destroy(mdp->cmdq_clt[cmd->pp_idx], &cmd->pkt); kfree(cmd->comps); cmd->comps = NULL; kfree(cmd); @@ -607,20 +564,13 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp, goto err_uninit; } - if (CFG_CHECK(MT8183, p_id)) - num_comp = CFG_GET(MT8183, config, num_components); - else if (CFG_CHECK(MT8195, p_id)) - num_comp = CFG_GET(MT8195, config, num_components); - else - goto err_uninit; - cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); if (!cmd) { ret = -ENOMEM; goto err_uninit; } - ret = mdp_cmdq_pkt_create(mdp->cmdq_clt[pp_idx], &cmd->pkt, SZ_16K); + ret = cmdq_pkt_create(mdp->cmdq_clt[pp_idx], &cmd->pkt, SZ_16K); if (ret) goto err_free_cmd; @@ -632,6 +582,7 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp, ret = -EINVAL; goto err_destroy_pkt; } + comps = kcalloc(num_comp, sizeof(*comps), GFP_KERNEL); if (!comps) { ret = -ENOMEM; @@ -676,7 +627,8 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp, dev_err(dev, "mdp_path_config error %d\n", pp_idx); goto err_free_path; } - cmdq_pkt_finalize(&cmd->pkt); + cmdq_pkt_eoc(&cmd->pkt); + cmdq_pkt_jump_rel(&cmd->pkt, CMDQ_INST_SIZE, mdp->cmdq_shift_pa[pp_idx]); for (i = 0; i < num_comp; i++) { s32 inner_id = MDP_COMP_NONE; @@ -699,6 +651,7 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp, cmd->comps = comps; cmd->num_comps = num_comp; cmd->mdp_ctx = param->mdp_ctx; + cmd->pp_idx = pp_idx; kfree(path); return cmd; @@ -710,7 +663,7 @@ err_free_path: err_free_comps: kfree(comps); err_destroy_pkt: - mdp_cmdq_pkt_destroy(&cmd->pkt); + cmdq_pkt_destroy(mdp->cmdq_clt[pp_idx], &cmd->pkt); err_free_cmd: kfree(cmd); err_uninit: diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h index 53a30ad7e0b0..222611e03a06 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h @@ -12,8 +12,6 @@ #include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk-img-ipi.h" -struct platform_device *mdp_get_plat_device(struct platform_device *pdev); - struct mdp_cmdq_param { struct img_config *config; struct img_ipi_frameparam *param; @@ -35,6 +33,7 @@ struct mdp_cmdq_cmd { struct mdp_comp *comps; void *mdp_ctx; u8 num_comps; + u8 pp_idx; }; struct mdp_dev; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 8f62fb167156..683c066ed975 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -72,14 +72,14 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) /* Disable RSZ1 */ if (ctx->comp->inner_id == rdma0 && prz1) - MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE, - 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, prz1->reg_base, + PRZ_ENABLE, 0x0, BIT(0)); } /* Reset RDMA */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); - MM_REG_POLL(cmd, subsys_id, base, MDP_RDMA_MON_STA_1, BIT(8), BIT(8)); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); + MM_REG_POLL_MASK(cmd, subsys_id, base, MDP_RDMA_MON_STA_1, BIT(8), BIT(8)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); return 0; } @@ -98,26 +98,25 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, if (mdp_cfg && mdp_cfg->rdma_support_10bit) { if (block10bit) - MM_REG_WRITE(cmd, subsys_id, base, - MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); + MM_REG_WRITE_MASK(cmd, subsys_id, base, + MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); else - MM_REG_WRITE(cmd, subsys_id, base, - MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); + MM_REG_WRITE_MASK(cmd, subsys_id, base, + MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); } /* Setup smi control */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON, - (7 << 4) + //burst type to 8 - (1 << 16), //enable pre-ultra - 0x00030071); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON, + (7 << 4) + //burst type to 8 + (1 << 16), //enable pre-ultra + 0x00030071); /* Setup source frame info */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, - 0x03C8FE0F); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 0x03C8FE0F); if (mdp_cfg) if (mdp_cfg->rdma_support_10bit && en_ufo) { @@ -126,17 +125,15 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y); - MM_REG_WRITE(cmd, subsys_id, - base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c); - MM_REG_WRITE(cmd, subsys_id, - base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_RDMA_UFO_DEC_LENGTH_BASE_C, reg); /* Set 10bit source frame pitch */ if (block10bit) { @@ -144,9 +141,9 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl); - MM_REG_WRITE(cmd, subsys_id, - base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, - reg, 0x001FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, + MDP_RDMA_MF_BKGD_SIZE_IN_PXL, + reg, 0x001FFFFF); } } @@ -157,128 +154,121 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8195, ctx->param, rdma.control); rdma_con_mask = 0x1130; } - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, - rdma_con_mask); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_CON, reg, rdma_con_mask); /* Setup source buffer base */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg); /* Setup source buffer end */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, reg); /* Setup source frame pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, - reg, 0x001FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, + reg, 0x001FFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, - reg, 0x001FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, + reg, 0x001FFFFF); /* Setup color transform */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.transform); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.transform); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, - reg, 0x0F110000); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, + reg, 0x0F110000); if (!mdp_cfg || !mdp_cfg->rdma_esl_setting) goto rdma_config_done; if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, - reg, 0x0FFF00FF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, + reg, 0x0FFF00FF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, - reg, 0x3FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, + reg, 0x3FFFFFFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, - reg, 0x3FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, + reg, 0x3FFFFFFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, - reg, 0x0F7F007F); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, + reg, 0x0F7F007F); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, - reg, 0x3FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, + reg, 0x3FFFFFFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, - reg, 0x3FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, + reg, 0x3FFFFFFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, - reg, 0x0F3F003F); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, + reg, 0x0F3F003F); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, - reg, 0x3FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, + reg, 0x3FFFFFFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, - reg, 0x3FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, + reg, 0x3FFFFFFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, - reg, 0x0F3F003F); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, + reg, 0x0F3F003F); rdma_config_done: return 0; @@ -297,15 +287,14 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, u32 reg = 0; /* Enable RDMA */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); /* Set Y pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, reg); /* Set 10bit UFO mode */ if (mdp_cfg) { @@ -315,8 +304,7 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p); MM_REG_WRITE(cmd, subsys_id, base, - MDP_RDMA_SRC_OFFSET_0_P, - reg, 0xFFFFFFFF); + MDP_RDMA_SRC_OFFSET_0_P, reg); } } @@ -325,40 +313,38 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, reg); /* Set V pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, - reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, reg); /* Set source size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, - 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, + 0x1FFF1FFF); /* Set target size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, - reg, 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, + reg, 0x1FFF1FFF); /* Set crop offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, - reg, 0x003F001F); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, + reg, 0x003F001F); if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); @@ -369,8 +355,8 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, } if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) if ((csf_r - csf_l + 1) > 320) - MM_REG_WRITE(cmd, subsys_id, base, - MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, + MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2)); return 0; } @@ -393,7 +379,7 @@ static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); /* Disable RDMA */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); return 0; } @@ -411,10 +397,10 @@ static int init_rsz(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) u8 subsys_id = ctx->comp->subsys_id; /* Reset RSZ */ - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); /* Enable RSZ */ - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); if (CFG_CHECK(MT8195, p_id)) { struct device *dev; @@ -437,7 +423,7 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, u32 reg = 0; if (mdp_cfg && mdp_cfg->rsz_etc_control) - MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0); if (CFG_CHECK(MT8183, p_id)) bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); @@ -446,7 +432,7 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, if (bypass) { /* Disable RSZ */ - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); return 0; } @@ -454,29 +440,27 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, rsz.control1); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.control1); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, - 0x03FFFDF3); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 0x03FFFDF3); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.control2); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.control2); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, - 0x0FFFC290); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x0FFFC290); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, - reg, 0x007FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, reg, + 0x007FFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, - reg, 0x007FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, reg, + 0x007FFFFF); return 0; } @@ -495,15 +479,13 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, - 0x00003800); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x00003800); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg); if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); @@ -514,60 +496,56 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, } if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) if ((csf_r - csf_l + 1) <= 16) - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, - BIT(27), BIT(27)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, + BIT(27), BIT(27)); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, - reg, 0xFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, + reg, 0xFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix); - MM_REG_WRITE(cmd, subsys_id, - base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, - reg, 0x1FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, + reg, 0x1FFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, - reg, 0xFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, + reg, 0xFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, - reg, 0x1FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, + reg, 0x1FFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left); - MM_REG_WRITE(cmd, subsys_id, - base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, - reg, 0xFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, + reg, 0xFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix); - MM_REG_WRITE(cmd, subsys_id, - base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, - reg, 0x1FFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, + reg, 0x1FFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg); if (CFG_CHECK(MT8195, p_id)) { struct device *dev; @@ -596,19 +574,19 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg); MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, - MDP_MERGE_CFG_0, reg, 0xFFFFFFFF); + MDP_MERGE_CFG_0, reg); MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, - MDP_MERGE_CFG_4, reg, 0xFFFFFFFF); + MDP_MERGE_CFG_4, reg); MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, - MDP_MERGE_CFG_24, reg, 0xFFFFFFFF); + MDP_MERGE_CFG_24, reg); MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, - MDP_MERGE_CFG_25, reg, 0xFFFFFFFF); + MDP_MERGE_CFG_25, reg); /* Bypass mode */ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, - MDP_MERGE_CFG_12, BIT(0), 0xFFFFFFFF); + MDP_MERGE_CFG_12, BIT(0)); MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, - MDP_MERGE_ENABLE, BIT(0), 0xFFFFFFFF); + MDP_MERGE_ENABLE, BIT(0)); } rsz_subfrm_done: @@ -634,8 +612,8 @@ static int advance_rsz_subfrm(struct mdp_comp_ctx *ctx, } if ((csf_r - csf_l + 1) <= 16) - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, - BIT(27)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, + BIT(27)); } return 0; @@ -655,15 +633,15 @@ static int init_wrot(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) u8 subsys_id = ctx->comp->subsys_id; /* Reset WROT */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); - MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); + MM_REG_POLL_MASK(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); /* Reset setting */ if (CFG_CHECK(MT8195, p_id)) - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); - MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); + MM_REG_POLL_MASK(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); return 0; } @@ -681,39 +659,36 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg); if (mdp_cfg && mdp_cfg->wrot_support_10bit) { if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, - reg, 0x0000000F); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SCAN_10BIT, + reg, 0x0000000F); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, - reg, 0x04000000); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_PENDING_ZERO, + reg, 0x04000000); } if (CFG_CHECK(MT8195, p_id)) { reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, - reg, 0x00000007); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CTRL_2, + reg, 0x00000007); } /* Write frame related registers */ @@ -721,14 +696,13 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, wrot.control); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.control); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, - 0xF131510F); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CTRL, reg, 0xF131510F); /* Write pre-ultra threshold */ if (CFG_CHECK(MT8195, p_id)) { reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, - 0x00FFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, + 0x00FFFFFF); } /* Write frame Y pitch */ @@ -736,37 +710,34 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, - 0x0000FFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE, reg, 0x0000FFFF); /* Write frame UV pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, - 0xFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 0xFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, - 0xFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 0xFFFF); /* Write matrix control */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); /* Set the fixed ALPHA as 0xFF */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, - 0xFF000000); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, + 0xFF000000); /* Set VIDO_EOL_SEL */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); /* Set VIDO_FIFO_TEST */ if (CFG_CHECK(MT8183, p_id)) @@ -775,8 +746,8 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test); if (reg != 0) - MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, - reg, 0xFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_FIFO_TEST, reg, + 0xFFF); /* Filter enable */ if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { @@ -784,13 +755,13 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, wrot.filter); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.filter); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, - reg, 0x77); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, + 0x77); /* Turn off WROT DMA DCM */ if (CFG_CHECK(MT8195, p_id)) - MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, - (0x1 << 23) + (0x1 << 20), 0x900000); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, + (0x1 << 23) + (0x1 << 20), 0x900000); } return 0; @@ -808,57 +779,52 @@ static int config_wrot_subfrm(struct mdp_comp_ctx *ctx, reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, - reg, 0x0FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR, reg, 0x0FFFFFFF); /* Write U pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, - reg, 0x0FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR_C, reg, 0x0FFFFFFF); /* Write V pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, - reg, 0x0FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR_V, reg, + 0x0FFFFFFF); /* Write source size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, - 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 0x1FFF1FFF); /* Write target size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, - 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 0x1FFF1FFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, - 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 0x1FFF1FFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); else if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, - reg, 0x1FFF7F00); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, + 0x1FFF7F00); /* Enable WROT */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); return 0; } @@ -881,11 +847,11 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); if (mdp_cfg && mdp_cfg->wrot_filter_constraint) - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, - 0x77); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, + 0x77); /* Disable WROT */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); return 0; } @@ -904,9 +870,9 @@ static int init_wdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) u8 subsys_id = ctx->comp->subsys_id; /* Reset WDMA */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); - MM_REG_POLL(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0)); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); + MM_REG_POLL_MASK(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); return 0; } @@ -918,40 +884,35 @@ static int config_wdma_frame(struct mdp_comp_ctx *ctx, u8 subsys_id = ctx->comp->subsys_id; u32 reg = 0; - MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050); /* Setup frame information */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, reg, - 0x0F01B8F0); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CFG, reg, 0x0F01B8F0); /* Setup frame base address */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg, - 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg); /* Setup Y pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, - reg, 0x0000FFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, reg, + 0x0000FFFF); /* Setup UV pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_UV_PITCH, - reg, 0x0000FFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_UV_PITCH, reg, + 0x0000FFFF); /* Set the fixed ALPHA as 0xFF */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, - 0x800000FF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, + 0x800000FF); return 0; } @@ -966,36 +927,33 @@ static int config_wdma_subfrm(struct mdp_comp_ctx *ctx, /* Write Y pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, - reg, 0x0FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, reg, + 0x0FFFFFFF); /* Write U pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, - reg, 0x0FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, reg, + 0x0FFFFFFF); /* Write V pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, - reg, 0x0FFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, reg, + 0x0FFFFFFF); /* Write source size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, - 0x3FFF3FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, 0x3FFF3FFF); /* Write target size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, - 0x3FFF3FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, 0x3FFF3FFF); /* Write clip offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, - 0x3FFF3FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, 0x3FFF3FFF); /* Enable WDMA */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); return 0; } @@ -1007,7 +965,7 @@ static int wait_wdma_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); /* Disable WDMA */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); return 0; } @@ -1033,19 +991,17 @@ static int reset_luma_hist(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) /* Reset histogram */ for (i = 0; i <= hist_num; i++) - MM_REG_WRITE_MASK(cmd, subsys_id, base, - (MDP_LUMA_HIST_INIT + (i << 2)), - 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + (MDP_LUMA_HIST_INIT + (i << 2)), 0); if (mdp_cfg->tdshp_constrain) MM_REG_WRITE(cmd, subsys_id, base, - MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF); + MDP_DC_TWO_D_W1_RESULT_INIT, 0); if (mdp_cfg->tdshp_contour) for (i = 0; i < hist_num; i++) - MM_REG_WRITE_MASK(cmd, subsys_id, base, - (MDP_CONTOUR_HIST_INIT + (i << 2)), - 0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + (MDP_CONTOUR_HIST_INIT + (i << 2)), 0); return 0; } @@ -1055,9 +1011,9 @@ static int init_tdshp(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u16 subsys_id = ctx->comp->subsys_id; - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); /* Enable FIFO */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); return reset_luma_hist(ctx, cmd); } @@ -1072,7 +1028,7 @@ static int config_tdshp_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg); - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); return 0; } @@ -1086,26 +1042,24 @@ static int config_tdshp_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src); - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, - reg, MDP_TDSHP_INPUT_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, reg); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst); - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, - reg, 0x00FF00FF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, reg, + 0x00FF00FF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip); - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, - reg, MDP_TDSHP_OUTPUT_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, reg); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg); return 0; } @@ -1122,21 +1076,19 @@ static int init_color(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u16 subsys_id = ctx->comp->subsys_id; - MM_REG_WRITE(cmd, subsys_id, base, - MDP_COLOR_START, 0x1, BIT(1) | BIT(0)); - MM_REG_WRITE(cmd, subsys_id, base, - MDP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, - MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_START, 0x1, + BIT(1) | BIT(0)); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_WIN_X_MAIN, 0xFFFF0000); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000); /* Reset color matrix */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); /* Enable interrupt */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); return 0; } @@ -1151,8 +1103,7 @@ static int config_color_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, color.start); - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, - reg, MDP_COLOR_START_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, reg); return 0; } @@ -1166,13 +1117,13 @@ static int config_color_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize); - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, - reg, 0x00003FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, + reg, 0x00003FFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize); - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, - reg, 0x00003FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, + reg, 0x00003FFF); return 0; } @@ -1190,9 +1141,9 @@ static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) u8 subsys_id = ctx->comp->subsys_id; /* CCORR enable */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); /* Relay mode */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); return 0; } @@ -1214,8 +1165,8 @@ static int config_ccorr_subfrm(struct mdp_comp_ctx *ctx, hsize = csf_r - csf_l + 1; vsize = csf_b - csf_t + 1; - MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_SIZE, - (hsize << 16) + (vsize << 0), 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_SIZE, + (hsize << 16) + (vsize << 0), 0x1FFF1FFF); return 0; } @@ -1231,7 +1182,7 @@ static int init_aal(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) u16 subsys_id = ctx->comp->subsys_id; /* Always set MDP_AAL enable to 1 */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); return 0; } @@ -1246,11 +1197,11 @@ static int config_aal_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main); - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, aal.cfg); - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); return 0; } @@ -1264,18 +1215,16 @@ static int config_aal_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src); - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, - reg, MDP_AAL_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, reg); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst); - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, - reg, 0x00FF00FF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, reg, + 0x00FF00FF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip); - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, - reg, MDP_AAL_OUTPUT_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, reg); return 0; } @@ -1293,7 +1242,7 @@ static int init_hdr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) u16 subsys_id = ctx->comp->subsys_id; /* Always set MDP_HDR enable to 1 */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); return 0; } @@ -1308,11 +1257,11 @@ static int config_hdr_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.top); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.relay); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); return 0; } @@ -1326,37 +1275,36 @@ static int config_hdr_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, - reg, MDP_HDR_TILE_POS_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, reg); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); /* Enable histogram */ if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr); - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); return 0; } @@ -1373,8 +1321,8 @@ static int init_fg(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u16 subsys_id = ctx->comp->subsys_id; - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); return 0; } @@ -1389,11 +1337,11 @@ static int config_fg_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, fg.ck_en); - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); return 0; } @@ -1407,11 +1355,11 @@ static int config_fg_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0); - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1); - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg); return 0; } @@ -1428,14 +1376,11 @@ static int init_ovl(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u16 subsys_id = ctx->comp->subsys_id; - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, - BIT(0), MDP_OVL_EN_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, BIT(0)); /* Set to relay mode */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, - BIT(9), MDP_OVL_SRC_CON_MASK); - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, - BIT(0), MDP_OVL_DP_CON_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, BIT(9)); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, BIT(0)); return 0; } @@ -1450,11 +1395,11 @@ static int config_ovl_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con); - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, ovl.src_con); - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); return 0; } @@ -1468,14 +1413,12 @@ static int config_ovl_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size); - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, - reg, MDP_OVL_L0_SRC_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, reg); /* Setup output size */ if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size); - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, - reg, MDP_OVL_ROI_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, reg); return 0; } @@ -1492,13 +1435,10 @@ static int init_pad(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u16 subsys_id = ctx->comp->subsys_id; - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, - BIT(1), MDP_PAD_CON_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, BIT(1)); /* Reset */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, - 0, MDP_PAD_W_SIZE_MASK); - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, - 0, MDP_PAD_H_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, 0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, 0); return 0; } @@ -1512,8 +1452,7 @@ static int config_pad_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8195, p_id)) reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size); - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, - reg, MDP_PAD_PIC_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, reg); return 0; } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index 3e5d2da1c807..681906c16419 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -9,18 +9,18 @@ #include "mtk-mdp3-cmdq.h" -#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask, ...) \ - cmdq_pkt_write_mask(&((cmd)->pkt), id, \ - (base) + (ofst), (val), (mask), ##__VA_ARGS__) - -#define MM_REG_WRITE(cmd, id, base, ofst, val, mask, ...) \ +#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask) \ do { \ typeof(mask) (m) = (mask); \ - MM_REG_WRITE_MASK(cmd, id, base, ofst, val, \ + cmdq_pkt_write_mask(&((cmd)->pkt), id, (base) + (ofst), \ + (val), \ (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ - (0xffffffff) : (m), ##__VA_ARGS__); \ + (0xffffffff) : (m)); \ } while (0) +#define MM_REG_WRITE(cmd, id, base, ofst, val) \ + cmdq_pkt_write(&((cmd)->pkt), id, (base) + (ofst), (val)) + #define MM_REG_WAIT(cmd, evt) \ do { \ typeof(cmd) (c) = (cmd); \ @@ -49,20 +49,17 @@ do { \ cmdq_pkt_set_event(&((c)->pkt), (e)); \ } while (0) -#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask, ...) \ +#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask) \ do { \ typeof(_mask) (_m) = (_mask); \ cmdq_pkt_poll_mask(&((cmd)->pkt), id, \ - (base) + (ofst), (val), (_m), ##__VA_ARGS__); \ + (base) + (ofst), (val), \ + (((_m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ + (0xffffffff) : (_m)); \ } while (0) -#define MM_REG_POLL(cmd, id, base, ofst, val, mask, ...) \ -do { \ - typeof(mask) (m) = (mask); \ - MM_REG_POLL_MASK((cmd), id, base, ofst, val, \ - (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ - (0xffffffff) : (m), ##__VA_ARGS__); \ -} while (0) +#define MM_REG_POLL(cmd, id, base, ofst, val) \ + cmdq_pkt_poll(&((cmd)->pkt), id, (base) + (ofst), (val)) enum mtk_mdp_comp_id { MDP_COMP_NONE = -1, /* Invalid engine */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 5e94ff0d0756..8de2c8e4d333 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -79,25 +79,6 @@ static struct platform_device *__get_pdev_by_id(struct platform_device *pdev, return mdp_pdev; } -struct platform_device *mdp_get_plat_device(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *mdp_node; - struct platform_device *mdp_pdev; - - mdp_node = of_parse_phandle(dev->of_node, MDP_PHANDLE_NAME, 0); - if (!mdp_node) { - dev_err(dev, "can't get node %s\n", MDP_PHANDLE_NAME); - return NULL; - } - - mdp_pdev = of_find_device_by_node(mdp_node); - of_node_put(mdp_node); - - return mdp_pdev; -} -EXPORT_SYMBOL_GPL(mdp_get_plat_device); - int mdp_vpu_get_locked(struct mdp_dev *mdp) { int ret = 0; @@ -312,6 +293,8 @@ static int mdp_probe(struct platform_device *pdev) ret = PTR_ERR(mdp->cmdq_clt[i]); goto err_mbox_destroy; } + + mdp->cmdq_shift_pa[i] = cmdq_get_shift_pa(mdp->cmdq_clt[i]->chan); } init_waitqueue_head(&mdp->callback_wq); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 430251f63754..05cade1d098e 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -126,6 +126,7 @@ struct mdp_dev { u32 id_count; struct ida mdp_ida; struct cmdq_client *cmdq_clt[MDP_PP_MAX]; + u8 cmdq_shift_pa[MDP_PP_MAX]; wait_queue_head_t callback_wq; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c index 657356f87743..644b223b2877 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c @@ -236,7 +236,7 @@ int mdp_try_crop(struct mdp_m2m_ctx *ctx, struct v4l2_rect *r, u32 framew, frameh, walign, halign; int ret; - dev_dbg(dev, "%d target:%d, set:(%d,%d) %ux%u", ctx->id, + dev_dbg(dev, "%d target:%d, set:(%d,%d)/%ux%u", ctx->id, s->target, s->r.left, s->r.top, s->r.width, s->r.height); left = s->r.left; @@ -275,7 +275,7 @@ int mdp_try_crop(struct mdp_m2m_ctx *ctx, struct v4l2_rect *r, r->width = right - left; r->height = bottom - top; - dev_dbg(dev, "%d crop:(%d,%d) %ux%u", ctx->id, + dev_dbg(dev, "%d crop:(%d,%d)/%ux%u", ctx->id, r->left, r->top, r->width, r->height); return 0; } diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_scp.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_scp.c index ff23b225db70..1b0bc47355c0 100644 --- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_scp.c +++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_scp.c @@ -79,8 +79,11 @@ struct mtk_vcodec_fw *mtk_vcodec_fw_scp_init(void *priv, enum mtk_vcodec_fw_use } fw = devm_kzalloc(&plat_dev->dev, sizeof(*fw), GFP_KERNEL); - if (!fw) + if (!fw) { + scp_put(scp); return ERR_PTR(-ENOMEM); + } + fw->type = SCP; fw->ops = &mtk_vcodec_rproc_msg; fw->scp = scp; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index ac568ed14fa2..aececca7ecf8 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -17,6 +17,7 @@ #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE) #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING) +#define IS_VDEC_SUPPORT_EXT(capability) ((capability) & MTK_VDEC_IS_SUPPORT_EXT) enum mtk_vcodec_dec_chip_name { MTK_VDEC_INVAL = 0, @@ -42,6 +43,7 @@ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_HEVC_FRAME = 0x1000, MTK_VCODEC_INNER_RACING = 0x20000, MTK_VDEC_IS_SUPPORT_10BIT = 0x40000, + MTK_VDEC_IS_SUPPORT_EXT = 0x80000, }; /* diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index afa224da0f41..d873159b9b30 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -152,8 +152,6 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, - .menu_skip_mask = - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), }, .codec_type = V4L2_PIX_FMT_HEVC_SLICE, }, diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c index 1ed0ccec5665..5b25e1679b51 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c @@ -30,6 +30,7 @@ enum vdec_h264_core_dec_err_type { /** * struct vdec_h264_slice_lat_dec_param - parameters for decode current frame + * (shared data between host and firmware) * * @sps: h264 sps syntax parameters * @pps: h264 pps syntax parameters @@ -48,7 +49,7 @@ struct vdec_h264_slice_lat_dec_param { }; /** - * struct vdec_h264_slice_info - decode information + * struct vdec_h264_slice_info - decode information (shared data between host and firmware) * * @nal_info: nal info of current picture * @timeout: Decode timeout: 1 timeout, 0 no timeout @@ -72,23 +73,22 @@ struct vdec_h264_slice_info { /** * struct vdec_h264_slice_vsi - shared memory for decode information exchange - * between SCP and Host. + * between SCP and Host (shared data between host and firmware). * - * @wdma_err_addr: wdma error dma address - * @wdma_start_addr: wdma start dma address - * @wdma_end_addr: wdma end dma address - * @slice_bc_start_addr: slice bc start dma address - * @slice_bc_end_addr: slice bc end dma address - * @row_info_start_addr: row info start dma address - * @row_info_end_addr: row info end dma address - * @trans_start: trans start dma address - * @trans_end: trans end dma address - * @wdma_end_addr_offset: wdma end address offset + * @wdma_err_addr: wdma error dma address + * @wdma_start_addr: wdma start dma address + * @wdma_end_addr: wdma end dma address + * @slice_bc_start_addr: slice bc start dma address + * @slice_bc_end_addr: slice bc end dma address + * @row_info_start_addr: row info start dma address + * @row_info_end_addr: row info end dma address + * @trans_start: trans start dma address + * @trans_end: trans end dma address + * @wdma_end_addr_offset: wdma end address offset * - * @mv_buf_dma: HW working motion vector buffer - * dma address (AP-W, VPU-R) - * @dec: decode information (AP-R, VPU-W) - * @h264_slice_params: decode parameters for hw used + * @mv_buf_dma: HW working motion vector buffer + * @dec: decode information (AP-R, VPU-W) + * @h264_slice_params: decode parameters for hw used */ struct vdec_h264_slice_vsi { /* LAT dec addr */ @@ -112,12 +112,12 @@ struct vdec_h264_slice_vsi { * struct vdec_h264_slice_share_info - shared information used to exchange * message between lat and core * - * @sps: sequence header information from user space - * @dec_params: decoder params from user space - * @h264_slice_params: decoder params used for hardware - * @trans_start: trans start dma address - * @trans_end: trans end dma address - * @nal_info: nal info of current picture + * @sps: sequence header information from user space + * @dec_params: decoder params from user space + * @h264_slice_params: decoder params used for hardware + * @trans_start: trans start dma address + * @trans_end: trans end dma address + * @nal_info: nal info of current picture */ struct vdec_h264_slice_share_info { struct v4l2_ctrl_h264_sps sps; @@ -128,6 +128,86 @@ struct vdec_h264_slice_share_info { u16 nal_info; }; +/* + * struct vdec_h264_slice_mem - memory address and size + * (shared data between host and firmware) + */ +struct vdec_h264_slice_mem { + union { + u64 buf; + u64 dma_addr; + }; + union { + size_t size; + u64 dma_addr_end; + }; +}; + +/** + * struct vdec_h264_slice_fb - frame buffer for decoding + * (shared data between host and firmware) + * + * @y: current luma buffer address info + * @c: current chroma buffer address info + */ +struct vdec_h264_slice_fb { + struct vdec_h264_slice_mem y; + struct vdec_h264_slice_mem c; +}; + +/** + * struct vdec_h264_slice_info_ext - extend decode information + * (shared data between host and firmware) + * + * @wdma_end_addr_offset: offset from buffer start + * @nal_info: nal info of current picture + * @timeout: toggles whether a decode operation is timeout + * @reserved: reserved + * @vdec_fb_va: vdec frame buffer struct virtual address + * @crc: displays the hardware status + */ +struct vdec_h264_slice_info_ext { + u64 wdma_end_addr_offset; + u16 nal_info; + u16 timeout; + u32 reserved; + u64 vdec_fb_va; + u32 crc[8]; +}; + +/** + * struct vdec_h264_slice_vsi_ext - extend shared memory for decode information exchange + * between SCP and Host (shared data between host and firmware). + * + * @bs: input buffer info + * @fb: current y/c buffer + * + * @ube: buffer used to share date between lat and core + * @trans: transcoded buffer used for core decode + * @row_info: row info buffer + * @err_map: error map buffer + * @slice_bc: slice buffer + * + * @mv_buf_dma: store hardware motion vector data + * @dec: decode information (AP-R, VPU-W) + * @h264_slice_params: decode parameters used for the hw + */ +struct vdec_h264_slice_vsi_ext { + /* LAT dec addr */ + struct vdec_h264_slice_mem bs; + struct vdec_h264_slice_fb fb; + + struct vdec_h264_slice_mem ube; + struct vdec_h264_slice_mem trans; + struct vdec_h264_slice_mem row_info; + struct vdec_h264_slice_mem err_map; + struct vdec_h264_slice_mem slice_bc; + + struct vdec_h264_slice_mem mv_buf_dma[H264_MAX_MV_NUM]; + struct vdec_h264_slice_info_ext dec; + struct vdec_h264_slice_lat_dec_param h264_slice_params; +}; + /** * struct vdec_h264_slice_inst - h264 decoder instance * @@ -138,17 +218,21 @@ struct vdec_h264_slice_share_info { * @vpu: VPU instance * @vsi: vsi used for lat * @vsi_core: vsi used for core - * - * @vsi_ctx: Local VSI data for this decoding context + * @vsi_ctx: vsi data for this decoding context + * @vsi_ext: extended vsi used for lat + * @vsi_core_ext: extended vsi used for core + * @vsi_ctx_ext: extended vsi data for this decoding context * @h264_slice_param: the parameters that hardware use to decode * - * @resolution_changed:resolution changed + * @resolution_changed: resolution changed * @realloc_mv_buf: reallocate mv buffer * @cap_num_planes: number of capture queue plane * * @dpb: decoded picture buffer used to store reference * buffer information - *@is_field_bitstream: is field bitstream + * @is_field_bitstream: not support field bitstream, only support frame + * + * @decode: lat decoder pointer for different architectures */ struct vdec_h264_slice_inst { unsigned int slice_dec_num; @@ -156,10 +240,18 @@ struct vdec_h264_slice_inst { struct mtk_vcodec_mem pred_buf; struct mtk_vcodec_mem mv_buf[H264_MAX_MV_NUM]; struct vdec_vpu_inst vpu; - struct vdec_h264_slice_vsi *vsi; - struct vdec_h264_slice_vsi *vsi_core; - - struct vdec_h264_slice_vsi vsi_ctx; + union { + struct { + struct vdec_h264_slice_vsi *vsi; + struct vdec_h264_slice_vsi *vsi_core; + struct vdec_h264_slice_vsi vsi_ctx; + }; + struct { + struct vdec_h264_slice_vsi_ext *vsi_ext; + struct vdec_h264_slice_vsi_ext *vsi_core_ext; + struct vdec_h264_slice_vsi_ext vsi_ctx_ext; + }; + }; struct vdec_h264_slice_lat_dec_param h264_slice_param; unsigned int resolution_changed; @@ -168,12 +260,15 @@ struct vdec_h264_slice_inst { struct v4l2_h264_dpb_entry dpb[16]; bool is_field_bitstream; + + int (*decode)(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *unused, bool *res_chg); }; static int vdec_h264_slice_fill_decode_parameters(struct vdec_h264_slice_inst *inst, - struct vdec_h264_slice_share_info *share_info) + struct vdec_h264_slice_share_info *share_info, + struct vdec_h264_slice_lat_dec_param *slice_param) { - struct vdec_h264_slice_lat_dec_param *slice_param = &inst->vsi->h264_slice_params; const struct v4l2_ctrl_h264_decode_params *dec_params; const struct v4l2_ctrl_h264_scaling_matrix *src_matrix; const struct v4l2_ctrl_h264_sps *sps; @@ -266,9 +361,6 @@ static int get_vdec_sig_decode_parameters(struct vdec_h264_slice_inst *inst) mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.num_valid); mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.num_valid); - memcpy(&inst->vsi_ctx.h264_slice_params, slice_param, - sizeof(inst->vsi_ctx.h264_slice_params)); - return 0; } @@ -392,68 +484,148 @@ static void vdec_h264_slice_get_crop_info(struct vdec_h264_slice_inst *inst, cr->left, cr->top, cr->width, cr->height); } -static int vdec_h264_slice_init(struct mtk_vcodec_dec_ctx *ctx) +static void vdec_h264_slice_setup_lat_buffer_ext(struct vdec_h264_slice_inst *inst, + struct mtk_vcodec_mem *bs, + struct vdec_lat_buf *lat_buf) { - struct vdec_h264_slice_inst *inst; - int err, vsi_size; + struct mtk_vcodec_mem *mem; + int i; - inst = kzalloc(sizeof(*inst), GFP_KERNEL); - if (!inst) - return -ENOMEM; + inst->vsi_ext->bs.dma_addr = (u64)bs->dma_addr; + inst->vsi_ext->bs.size = bs->size; - inst->ctx = ctx; + for (i = 0; i < H264_MAX_MV_NUM; i++) { + mem = &inst->mv_buf[i]; + inst->vsi_ext->mv_buf_dma[i].dma_addr = mem->dma_addr; + inst->vsi_ext->mv_buf_dma[i].size = mem->size; + } + inst->vsi_ext->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi_ext->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size; - inst->vpu.id = SCP_IPI_VDEC_LAT; - inst->vpu.core_id = SCP_IPI_VDEC_CORE; - inst->vpu.ctx = ctx; - inst->vpu.codec_type = ctx->current_codec; - inst->vpu.capture_type = ctx->capture_fourcc; + inst->vsi_ext->row_info.dma_addr = 0; + inst->vsi_ext->row_info.size = 0; - err = vpu_dec_init(&inst->vpu); - if (err) { - mtk_vdec_err(ctx, "vdec_h264 init err=%d", err); - goto error_free_inst; + inst->vsi_ext->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr; + inst->vsi_ext->err_map.size = lat_buf->wdma_err_addr.size; + + inst->vsi_ext->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr; + inst->vsi_ext->slice_bc.size = lat_buf->slice_bc_addr.size; + + inst->vsi_ext->trans.dma_addr_end = inst->ctx->msg_queue.wdma_rptr_addr; + inst->vsi_ext->trans.dma_addr = inst->ctx->msg_queue.wdma_wptr_addr; +} + +static int vdec_h264_slice_setup_core_buffer_ext(struct vdec_h264_slice_inst *inst, + struct vdec_h264_slice_share_info *share_info, + struct vdec_lat_buf *lat_buf) +{ + struct mtk_vcodec_mem *mem; + struct mtk_vcodec_dec_ctx *ctx = inst->ctx; + struct vb2_v4l2_buffer *vb2_v4l2; + struct vdec_fb *fb; + u64 y_fb_dma, c_fb_dma = 0; + int i; + + fb = ctx->dev->vdec_pdata->get_cap_buffer(ctx); + if (!fb) { + mtk_vdec_err(ctx, "Unable to get a CAPTURE buffer for CAPTURE queue is empty."); + return -EBUSY; } - vsi_size = round_up(sizeof(struct vdec_h264_slice_vsi), VCODEC_DEC_ALIGNED_64); - inst->vsi = inst->vpu.vsi; - inst->vsi_core = - (struct vdec_h264_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size); - inst->resolution_changed = true; - inst->realloc_mv_buf = true; + y_fb_dma = (u64)fb->base_y.dma_addr; + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1) + c_fb_dma = y_fb_dma + ctx->picinfo.fb_sz[0]; + else + c_fb_dma = (u64)fb->base_c.dma_addr; - mtk_vdec_debug(ctx, "lat struct size = %d,%d,%d,%d vsi: %d\n", - (int)sizeof(struct mtk_h264_sps_param), - (int)sizeof(struct mtk_h264_pps_param), - (int)sizeof(struct vdec_h264_slice_lat_dec_param), - (int)sizeof(struct mtk_h264_dpb_info), - vsi_size); - mtk_vdec_debug(ctx, "lat H264 instance >> %p, codec_type = 0x%x", - inst, inst->vpu.codec_type); + mtk_vdec_debug(ctx, "[h264-core] y/c addr = 0x%llx 0x%llx", y_fb_dma, c_fb_dma); - ctx->drv_handle = inst; - return 0; + inst->vsi_core_ext->fb.y.dma_addr = y_fb_dma; + inst->vsi_core_ext->fb.y.size = ctx->picinfo.fb_sz[0]; + inst->vsi_core_ext->fb.c.dma_addr = c_fb_dma; + inst->vsi_core_ext->fb.c.size = ctx->picinfo.fb_sz[1]; -error_free_inst: - kfree(inst); - return err; + inst->vsi_core_ext->dec.vdec_fb_va = (unsigned long)fb; + inst->vsi_core_ext->dec.nal_info = share_info->nal_info; + + inst->vsi_core_ext->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi_core_ext->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size; + + inst->vsi_core_ext->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr; + inst->vsi_core_ext->err_map.size = lat_buf->wdma_err_addr.size; + + inst->vsi_core_ext->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr; + inst->vsi_core_ext->slice_bc.size = lat_buf->slice_bc_addr.size; + + inst->vsi_core_ext->row_info.dma_addr = 0; + inst->vsi_core_ext->row_info.size = 0; + + inst->vsi_core_ext->trans.dma_addr = share_info->trans_start; + inst->vsi_core_ext->trans.dma_addr_end = share_info->trans_end; + + for (i = 0; i < H264_MAX_MV_NUM; i++) { + mem = &inst->mv_buf[i]; + inst->vsi_core_ext->mv_buf_dma[i].dma_addr = mem->dma_addr; + inst->vsi_core_ext->mv_buf_dma[i].size = mem->size; + } + + vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, vb2_v4l2, true); + + return 0; } -static void vdec_h264_slice_deinit(void *h_vdec) +static int vdec_h264_slice_core_decode_ext(struct vdec_lat_buf *lat_buf) { - struct vdec_h264_slice_inst *inst = h_vdec; + int err, timeout; + struct mtk_vcodec_dec_ctx *ctx = lat_buf->ctx; + struct vdec_h264_slice_inst *inst = ctx->drv_handle; + struct vdec_h264_slice_share_info *share_info = lat_buf->private_data; + struct vdec_vpu_inst *vpu = &inst->vpu; - vpu_dec_deinit(&inst->vpu); - vdec_h264_slice_free_mv_buf(inst); - vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); + memcpy(&inst->vsi_core_ext->h264_slice_params, &share_info->h264_slice_params, + sizeof(share_info->h264_slice_params)); - kfree(inst); + err = vdec_h264_slice_setup_core_buffer_ext(inst, share_info, lat_buf); + if (err) + goto vdec_dec_end; + + vdec_h264_slice_fill_decode_reflist(inst, &inst->vsi_core_ext->h264_slice_params, + share_info); + err = vpu_dec_core(vpu); + if (err) { + mtk_vdec_err(ctx, "core decode err=%d", err); + goto vdec_dec_end; + } + + /* wait decoder done interrupt */ + timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + if (timeout) + mtk_vdec_err(ctx, "core decode timeout: pic_%d", ctx->decoded_frame_cnt); + inst->vsi_core_ext->dec.timeout = !!timeout; + + vpu_dec_core_end(vpu); + + /* crc is hardware checksum, can be used to check whether the decoder result is right.*/ + mtk_vdec_debug(ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", + ctx->decoded_frame_cnt, + inst->vsi_core_ext->dec.crc[0], inst->vsi_core_ext->dec.crc[1], + inst->vsi_core_ext->dec.crc[2], inst->vsi_core_ext->dec.crc[3], + inst->vsi_core_ext->dec.crc[4], inst->vsi_core_ext->dec.crc[5], + inst->vsi_core_ext->dec.crc[6], inst->vsi_core_ext->dec.crc[7]); + +vdec_dec_end: + vdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, share_info->trans_end); + ctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req); + mtk_vdec_debug(ctx, "core decode done err=%d", err); + ctx->decoded_frame_cnt++; + return 0; } static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) { struct vdec_fb *fb; - u64 vdec_fb_va; u64 y_fb_dma, c_fb_dma; int err, timeout, i; struct mtk_vcodec_dec_ctx *ctx = lat_buf->ctx; @@ -463,22 +635,19 @@ static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) struct mtk_vcodec_mem *mem; struct vdec_vpu_inst *vpu = &inst->vpu; - mtk_vdec_debug(ctx, "[h264-core] vdec_h264 core decode"); memcpy(&inst->vsi_core->h264_slice_params, &share_info->h264_slice_params, sizeof(share_info->h264_slice_params)); fb = ctx->dev->vdec_pdata->get_cap_buffer(ctx); if (!fb) { err = -EBUSY; - mtk_vdec_err(ctx, "fb buffer is NULL"); + mtk_vdec_err(ctx, "Unable to get a CAPTURE buffer for CAPTURE queue is empty."); goto vdec_dec_end; } - vdec_fb_va = (unsigned long)fb; y_fb_dma = (u64)fb->base_y.dma_addr; if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1) - c_fb_dma = - y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; + c_fb_dma = y_fb_dma + ctx->picinfo.fb_sz[0]; else c_fb_dma = (u64)fb->base_c.dma_addr; @@ -486,7 +655,7 @@ static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) inst->vsi_core->dec.y_fb_dma = y_fb_dma; inst->vsi_core->dec.c_fb_dma = c_fb_dma; - inst->vsi_core->dec.vdec_fb_va = vdec_fb_va; + inst->vsi_core->dec.vdec_fb_va = (unsigned long)fb; inst->vsi_core->dec.nal_info = share_info->nal_info; inst->vsi_core->wdma_start_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr; @@ -524,6 +693,8 @@ static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) inst->vsi_core->dec.timeout = !!timeout; vpu_dec_core_end(vpu); + + /* crc is hardware checksum, can be used to check whether the decoder result is right.*/ mtk_vdec_debug(ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", ctx->decoded_frame_cnt, inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1], @@ -536,6 +707,7 @@ vdec_dec_end: ctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req); mtk_vdec_debug(ctx, "core decode done err=%d", err); ctx->decoded_frame_cnt++; + return 0; } @@ -562,6 +734,128 @@ static void vdec_h264_insert_startcode(struct mtk_vcodec_dec_dev *vcodec_dev, un (*bs_size) += 4; } +static int vdec_h264_slice_lat_decode_ext(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_h264_slice_inst *inst = h_vdec; + struct vdec_vpu_inst *vpu = &inst->vpu; + struct mtk_video_dec_buf *src_buf_info; + int err, timeout = 0; + unsigned int data[2]; + struct vdec_lat_buf *lat_buf; + struct vdec_h264_slice_share_info *share_info; + + if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx, + vdec_h264_slice_core_decode_ext, + sizeof(*share_info))) + return -ENOMEM; + + /* bs NULL means flush decoder */ + if (!bs) { + vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue); + return vpu_dec_reset(vpu); + } + + if (inst->is_field_bitstream) + return -EINVAL; + + lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx); + if (!lat_buf) { + mtk_vdec_debug(inst->ctx, "failed to get lat buffer"); + return -EAGAIN; + } + share_info = lat_buf->private_data; + src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer); + + lat_buf->src_buf_req = src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req; + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, true); + + err = vdec_h264_slice_fill_decode_parameters(inst, share_info, + &inst->vsi_ext->h264_slice_params); + if (err) + goto err_free_fb_out; + + vdec_h264_insert_startcode(inst->ctx->dev, bs->va, &bs->size, + &share_info->h264_slice_params.pps); + + *res_chg = inst->resolution_changed; + if (inst->resolution_changed) { + mtk_vdec_debug(inst->ctx, "- resolution changed -"); + if (inst->realloc_mv_buf) { + err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); + inst->realloc_mv_buf = false; + if (err) + goto err_free_fb_out; + } + inst->resolution_changed = false; + } + + vdec_h264_slice_setup_lat_buffer_ext(inst, bs, lat_buf); + mtk_vdec_debug(inst->ctx, "lat:trans(0x%llx 0x%lx) err:0x%llx", + inst->vsi_ext->ube.dma_addr, (unsigned long)inst->vsi_ext->ube.size, + inst->vsi_ext->err_map.dma_addr); + + mtk_vdec_debug(inst->ctx, "slice(0x%llx 0x%lx) rprt((0x%llx 0x%llx))", + inst->vsi_ext->slice_bc.dma_addr, + (unsigned long)inst->vsi_ext->slice_bc.size, + inst->vsi_ext->trans.dma_addr, inst->vsi_ext->trans.dma_addr_end); + + err = vpu_dec_start(vpu, data, 2); + if (err) { + mtk_vdec_debug(inst->ctx, "lat decode err: %d", err); + goto err_free_fb_out; + } + + share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr + + inst->vsi_ext->dec.wdma_end_addr_offset; + + share_info->trans_start = inst->ctx->msg_queue.wdma_wptr_addr; + share_info->nal_info = inst->vsi_ext->dec.nal_info; + + if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { + memcpy(&share_info->h264_slice_params, &inst->vsi_ext->h264_slice_params, + sizeof(share_info->h264_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); + } + + /* wait decoder done interrupt */ + timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); + if (timeout) + mtk_vdec_err(inst->ctx, "lat decode timeout: pic_%d", inst->slice_dec_num); + inst->vsi_ext->dec.timeout = !!timeout; + + err = vpu_dec_end(vpu); + if (err == SLICE_HEADER_FULL || err == TRANS_BUFFER_FULL) { + if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); + inst->slice_dec_num++; + mtk_vdec_err(inst->ctx, "lat dec fail: pic_%d err:%d", inst->slice_dec_num, err); + return -EINVAL; + } + + share_info->trans_end = inst->ctx->msg_queue.wdma_addr.dma_addr + + inst->vsi_ext->dec.wdma_end_addr_offset; + + vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, share_info->trans_end); + + if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { + memcpy(&share_info->h264_slice_params, &inst->vsi_ext->h264_slice_params, + sizeof(share_info->h264_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); + } + mtk_vdec_debug(inst->ctx, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num, + inst->vsi_ext->dec.crc[0], inst->vsi_ext->dec.crc[1], + inst->vsi_ext->dec.crc[2]); + + inst->slice_dec_num++; + return 0; +err_free_fb_out: + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); + mtk_vdec_err(inst->ctx, "slice dec number: %d err: %d", inst->slice_dec_num, err); + return err; +} + static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, struct vdec_fb *fb, bool *res_chg) { @@ -608,7 +902,8 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs, lat_buf->src_buf_req = src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req; v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, true); - err = vdec_h264_slice_fill_decode_parameters(inst, share_info); + err = vdec_h264_slice_fill_decode_parameters(inst, share_info, + &inst->vsi->h264_slice_params); if (err) goto err_free_fb_out; @@ -706,6 +1001,101 @@ err_free_fb_out: return err; } +static int vdec_h264_slice_single_decode_ext(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *unused, bool *res_chg) +{ + struct vdec_h264_slice_inst *inst = h_vdec; + struct vdec_vpu_inst *vpu = &inst->vpu; + struct mtk_video_dec_buf *src_buf_info, *dst_buf_info; + struct vdec_fb *fb; + unsigned int data[2], i; + u64 y_fb_dma, c_fb_dma; + struct mtk_vcodec_mem *mem; + int err; + + /* bs NULL means flush decoder */ + if (!bs) + return vpu_dec_reset(vpu); + + fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); + if (!fb) { + mtk_vdec_err(inst->ctx, + "Unable to get a CAPTURE buffer for CAPTURE queue is empty."); + return -ENOMEM; + } + + src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer); + dst_buf_info = container_of(fb, struct mtk_video_dec_buf, frame_buffer); + + y_fb_dma = fb->base_y.dma_addr; + c_fb_dma = fb->base_c.dma_addr; + mtk_vdec_debug(inst->ctx, "[h264-dec] [%d] y_dma=%llx c_dma=%llx", + inst->ctx->decoded_frame_cnt, y_fb_dma, c_fb_dma); + + inst->vsi_ctx_ext.bs.dma_addr = (u64)bs->dma_addr; + inst->vsi_ctx_ext.bs.size = bs->size; + inst->vsi_ctx_ext.fb.y.dma_addr = y_fb_dma; + inst->vsi_ctx_ext.fb.c.dma_addr = c_fb_dma; + inst->vsi_ctx_ext.dec.vdec_fb_va = (u64)(uintptr_t)fb; + + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, + &dst_buf_info->m2m_buf.vb, true); + err = get_vdec_sig_decode_parameters(inst); + if (err) + goto err_free_fb_out; + + memcpy(&inst->vsi_ctx_ext.h264_slice_params, &inst->h264_slice_param, + sizeof(inst->vsi_ctx_ext.h264_slice_params)); + + *res_chg = inst->resolution_changed; + if (inst->resolution_changed) { + mtk_vdec_debug(inst->ctx, "- resolution changed -"); + if (inst->realloc_mv_buf) { + err = vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); + inst->realloc_mv_buf = false; + if (err) + goto err_free_fb_out; + } + inst->resolution_changed = false; + + for (i = 0; i < H264_MAX_MV_NUM; i++) { + mem = &inst->mv_buf[i]; + inst->vsi_ctx_ext.mv_buf_dma[i].dma_addr = mem->dma_addr; + } + } + + memcpy(inst->vpu.vsi, &inst->vsi_ctx_ext, sizeof(inst->vsi_ctx_ext)); + err = vpu_dec_start(vpu, data, 2); + if (err) + goto err_free_fb_out; + + /* wait decoder done interrupt */ + err = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + if (err) + mtk_vdec_err(inst->ctx, "decode timeout: pic_%d", inst->ctx->decoded_frame_cnt); + + inst->vsi_ext->dec.timeout = !!err; + err = vpu_dec_end(vpu); + if (err) + goto err_free_fb_out; + + memcpy(&inst->vsi_ctx_ext, inst->vpu.vsi, sizeof(inst->vsi_ctx_ext)); + mtk_vdec_debug(inst->ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", + inst->ctx->decoded_frame_cnt, + inst->vsi_ctx_ext.dec.crc[0], inst->vsi_ctx_ext.dec.crc[1], + inst->vsi_ctx_ext.dec.crc[2], inst->vsi_ctx_ext.dec.crc[3], + inst->vsi_ctx_ext.dec.crc[4], inst->vsi_ctx_ext.dec.crc[5], + inst->vsi_ctx_ext.dec.crc[6], inst->vsi_ctx_ext.dec.crc[7]); + + inst->ctx->decoded_frame_cnt++; + return 0; + +err_free_fb_out: + mtk_vdec_err(inst->ctx, "dec frame number: %d err: %d", inst->ctx->decoded_frame_cnt, err); + return err; +} + static int vdec_h264_slice_single_decode(void *h_vdec, struct mtk_vcodec_mem *bs, struct vdec_fb *unused, bool *res_chg) { @@ -725,7 +1115,8 @@ static int vdec_h264_slice_single_decode(void *h_vdec, struct mtk_vcodec_mem *bs fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); if (!fb) { - mtk_vdec_err(inst->ctx, "fb buffer is NULL"); + mtk_vdec_err(inst->ctx, + "Unable to get a CAPTURE buffer for CAPTURE queue is empty."); return -ENOMEM; } @@ -749,6 +1140,9 @@ static int vdec_h264_slice_single_decode(void *h_vdec, struct mtk_vcodec_mem *bs if (err) goto err_free_fb_out; + memcpy(&inst->vsi_ctx.h264_slice_params, &inst->h264_slice_param, + sizeof(inst->vsi_ctx.h264_slice_params)); + buf = (unsigned char *)bs->va; nal_start_idx = mtk_vdec_h264_find_start_code(buf, bs->size); if (nal_start_idx < 0) { @@ -806,21 +1200,95 @@ err_free_fb_out: return err; } +static int vdec_h264_slice_init(struct mtk_vcodec_dec_ctx *ctx) +{ + struct vdec_h264_slice_inst *inst; + int err, vsi_size; + unsigned char *temp; + + inst = kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->ctx = ctx; + + inst->vpu.id = SCP_IPI_VDEC_LAT; + inst->vpu.core_id = SCP_IPI_VDEC_CORE; + inst->vpu.ctx = ctx; + inst->vpu.codec_type = ctx->current_codec; + inst->vpu.capture_type = ctx->capture_fourcc; + + err = vpu_dec_init(&inst->vpu); + if (err) { + mtk_vdec_err(ctx, "vdec_h264 init err=%d", err); + goto error_free_inst; + } + + if (IS_VDEC_SUPPORT_EXT(ctx->dev->dec_capability)) { + vsi_size = sizeof(struct vdec_h264_slice_vsi_ext); + + vsi_size = round_up(vsi_size, VCODEC_DEC_ALIGNED_64); + inst->vsi_ext = inst->vpu.vsi; + temp = (unsigned char *)inst->vsi_ext; + inst->vsi_core_ext = (struct vdec_h264_slice_vsi_ext *)(temp + vsi_size); + + if (inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE) + inst->decode = vdec_h264_slice_single_decode_ext; + else + inst->decode = vdec_h264_slice_lat_decode_ext; + } else { + vsi_size = sizeof(struct vdec_h264_slice_vsi); + + vsi_size = round_up(vsi_size, VCODEC_DEC_ALIGNED_64); + inst->vsi = inst->vpu.vsi; + temp = (unsigned char *)inst->vsi; + inst->vsi_core = (struct vdec_h264_slice_vsi *)(temp + vsi_size); + + if (inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE) + inst->decode = vdec_h264_slice_single_decode; + else + inst->decode = vdec_h264_slice_lat_decode; + } + inst->resolution_changed = true; + inst->realloc_mv_buf = true; + + mtk_vdec_debug(ctx, "lat struct size = %d,%d,%d,%d vsi: %d\n", + (int)sizeof(struct mtk_h264_sps_param), + (int)sizeof(struct mtk_h264_pps_param), + (int)sizeof(struct vdec_h264_slice_lat_dec_param), + (int)sizeof(struct mtk_h264_dpb_info), + vsi_size); + mtk_vdec_debug(ctx, "lat H264 instance >> %p, codec_type = 0x%x", + inst, inst->vpu.codec_type); + + ctx->drv_handle = inst; + return 0; + +error_free_inst: + kfree(inst); + return err; +} + +static void vdec_h264_slice_deinit(void *h_vdec) +{ + struct vdec_h264_slice_inst *inst = h_vdec; + + vpu_dec_deinit(&inst->vpu); + vdec_h264_slice_free_mv_buf(inst); + vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); + + kfree(inst); +} + static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, struct vdec_fb *unused, bool *res_chg) { struct vdec_h264_slice_inst *inst = h_vdec; - int ret; if (!h_vdec) return -EINVAL; - if (inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE) - ret = vdec_h264_slice_single_decode(h_vdec, bs, unused, res_chg); - else - ret = vdec_h264_slice_lat_decode(h_vdec, bs, unused, res_chg); - - return ret; + return inst->decode(h_vdec, bs, unused, res_chg); } static int vdec_h264_slice_get_param(void *h_vdec, enum vdec_get_param_type type, diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c index aa721cc43647..2725db882e5b 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c @@ -821,7 +821,7 @@ static int vdec_hevc_slice_setup_core_buffer(struct vdec_hevc_slice_inst *inst, inst->vsi_core->fb.y.dma_addr = y_fb_dma; inst->vsi_core->fb.y.size = ctx->picinfo.fb_sz[0]; inst->vsi_core->fb.c.dma_addr = c_fb_dma; - inst->vsi_core->fb.y.size = ctx->picinfo.fb_sz[1]; + inst->vsi_core->fb.c.size = ctx->picinfo.fb_sz[1]; inst->vsi_core->dec.vdec_fb_va = (unsigned long)fb; diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c index f8145998fcaf..0f63657d8bad 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c @@ -515,7 +515,7 @@ static int h264_encode_frame(struct venc_h264_inst *inst, struct venc_frame_info frame_info; struct mtk_vcodec_enc_ctx *ctx = inst->ctx; - mtk_venc_debug(ctx, "frm_cnt = %d\n ", inst->frm_cnt); + mtk_venc_debug(ctx, "frm_cnt = %d\n", inst->frm_cnt); if (MTK_ENC_IOVA_IS_34BIT(ctx)) { gop_size = inst->vsi_34->config.gop_size; @@ -594,7 +594,11 @@ static int h264_enc_init(struct mtk_vcodec_enc_ctx *ctx) inst->ctx = ctx; inst->vpu_inst.ctx = ctx; - inst->vpu_inst.id = is_ext ? SCP_IPI_VENC_H264 : IPI_VENC_H264; + if (is_ext) + inst->vpu_inst.id = SCP_IPI_VENC_H264; + else + inst->vpu_inst.id = IPI_VENC_H264; + inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx->dev->reg_base, VENC_SYS); ret = vpu_enc_init(&inst->vpu_inst); |