diff options
Diffstat (limited to 'drivers/platform/x86/intel/pmc')
| -rw-r--r-- | drivers/platform/x86/intel/pmc/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/Makefile | 8 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/adl.c | 56 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/arl.c | 147 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/cnp.c | 36 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/core.c | 364 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/core.h | 213 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/core_ssram.c | 332 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/icl.c | 24 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/lnl.c | 67 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/mtl.c | 119 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/ptl.c | 550 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/spt.c | 45 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/ssram_telemetry.c | 204 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/ssram_telemetry.h | 24 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/pmc/tgl.c | 59 |
16 files changed, 1412 insertions, 840 deletions
diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/intel/pmc/Kconfig index d2f651fbec2c..c6ef0bcf76af 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -8,6 +8,7 @@ config INTEL_PMC_CORE depends on PCI depends on ACPI depends on INTEL_PMT_TELEMETRY + select INTEL_PMC_SSRAM_TELEMETRY help The Intel Platform Controller Hub for Intel Core SoCs provides access to Power Management Controller registers via various interfaces. This @@ -24,3 +25,6 @@ config INTEL_PMC_CORE - SLPS0 Debug registers (Cannonlake/Icelake PCH) - Low Power Mode registers (Tigerlake and beyond) - PMC quirks as needed to enable SLPS0/S0ix + +config INTEL_PMC_SSRAM_TELEMETRY + tristate diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86/intel/pmc/Makefile index 389e5419dadf..5f68c8503a56 100644 --- a/drivers/platform/x86/intel/pmc/Makefile +++ b/drivers/platform/x86/intel/pmc/Makefile @@ -3,8 +3,12 @@ # Intel x86 Platform-Specific Drivers # -intel_pmc_core-y := core.o core_ssram.o spt.o cnp.o \ - icl.o tgl.o adl.o mtl.o arl.o lnl.o +intel_pmc_core-y := core.o spt.o cnp.o icl.o \ + tgl.o adl.o mtl.o arl.o lnl.o ptl.o obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o intel_pmc_core_pltdrv-y := pltdrv.o obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o + +# Intel PMC SSRAM driver +intel_pmc_ssram_telemetry-y += ssram_telemetry.o +obj-$(CONFIG_INTEL_PMC_SSRAM_TELEMETRY) += intel_pmc_ssram_telemetry.o diff --git a/drivers/platform/x86/intel/pmc/adl.c b/drivers/platform/x86/intel/pmc/adl.c index e7878558fd90..9e7dfd6e3310 100644 --- a/drivers/platform/x86/intel/pmc/adl.c +++ b/drivers/platform/x86/intel/pmc/adl.c @@ -11,7 +11,7 @@ #include "core.h" /* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */ -const struct pmc_bit_map adl_pfear_map[] = { +static const struct pmc_bit_map adl_pfear_map[] = { {"SPI/eSPI", BIT(2)}, {"XHCI", BIT(3)}, {"SPA", BIT(4)}, @@ -54,7 +54,7 @@ const struct pmc_bit_map adl_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_adl_pfear_map[] = { +static const struct pmc_bit_map *ext_adl_pfear_map[] = { /* * Check intel_pmc_core_ids[] users of cnp_reg_map for * a list of core SoCs using this. @@ -63,7 +63,7 @@ const struct pmc_bit_map *ext_adl_pfear_map[] = { NULL }; -const struct pmc_bit_map adl_ltr_show_map[] = { +static const struct pmc_bit_map adl_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, {"SATA", CNP_PMC_LTR_SATA}, @@ -100,7 +100,7 @@ const struct pmc_bit_map adl_ltr_show_map[] = { {} }; -const struct pmc_bit_map adl_clocksource_status_map[] = { +static const struct pmc_bit_map adl_clocksource_status_map[] = { {"CLKPART1_OFF_STS", BIT(0)}, {"CLKPART2_OFF_STS", BIT(1)}, {"CLKPART3_OFF_STS", BIT(2)}, @@ -128,7 +128,7 @@ const struct pmc_bit_map adl_clocksource_status_map[] = { {} }; -const struct pmc_bit_map adl_power_gating_status_0_map[] = { +static const struct pmc_bit_map adl_power_gating_status_0_map[] = { {"PMC_PGD0_PG_STS", BIT(0)}, {"DMI_PGD0_PG_STS", BIT(1)}, {"ESPISPI_PGD0_PG_STS", BIT(2)}, @@ -158,7 +158,7 @@ const struct pmc_bit_map adl_power_gating_status_0_map[] = { {} }; -const struct pmc_bit_map adl_power_gating_status_1_map[] = { +static const struct pmc_bit_map adl_power_gating_status_1_map[] = { {"USBR0_PGD0_PG_STS", BIT(0)}, {"SMT1_PGD0_PG_STS", BIT(2)}, {"CSMERTC_PGD0_PG_STS", BIT(6)}, @@ -170,14 +170,14 @@ const struct pmc_bit_map adl_power_gating_status_1_map[] = { {} }; -const struct pmc_bit_map adl_power_gating_status_2_map[] = { +static const struct pmc_bit_map adl_power_gating_status_2_map[] = { {"THC0_PGD0_PG_STS", BIT(7)}, {"THC1_PGD0_PG_STS", BIT(8)}, {"SPF_PGD0_PG_STS", BIT(14)}, {} }; -const struct pmc_bit_map adl_d3_status_0_map[] = { +static const struct pmc_bit_map adl_d3_status_0_map[] = { {"ISH_D3_STS", BIT(2)}, {"LPSS_D3_STS", BIT(3)}, {"XDCI_D3_STS", BIT(4)}, @@ -193,13 +193,13 @@ const struct pmc_bit_map adl_d3_status_0_map[] = { {} }; -const struct pmc_bit_map adl_d3_status_1_map[] = { +static const struct pmc_bit_map adl_d3_status_1_map[] = { {"GBE_D3_STS", BIT(19)}, {"CNVI_D3_STS", BIT(27)}, {} }; -const struct pmc_bit_map adl_d3_status_2_map[] = { +static const struct pmc_bit_map adl_d3_status_2_map[] = { {"CSMERTC_D3_STS", BIT(1)}, {"CSE_D3_STS", BIT(4)}, {"KVMCC_D3_STS", BIT(5)}, @@ -210,20 +210,20 @@ const struct pmc_bit_map adl_d3_status_2_map[] = { {} }; -const struct pmc_bit_map adl_d3_status_3_map[] = { +static const struct pmc_bit_map adl_d3_status_3_map[] = { {"THC0_D3_STS", BIT(14)}, {"THC1_D3_STS", BIT(15)}, {} }; -const struct pmc_bit_map adl_vnn_req_status_0_map[] = { +static const struct pmc_bit_map adl_vnn_req_status_0_map[] = { {"ISH_VNN_REQ_STS", BIT(2)}, {"ESPISPI_VNN_REQ_STS", BIT(18)}, {"DSP_VNN_REQ_STS", BIT(19)}, {} }; -const struct pmc_bit_map adl_vnn_req_status_1_map[] = { +static const struct pmc_bit_map adl_vnn_req_status_1_map[] = { {"NPK_VNN_REQ_STS", BIT(4)}, {"EXI_VNN_REQ_STS", BIT(9)}, {"GBE_VNN_REQ_STS", BIT(19)}, @@ -232,7 +232,7 @@ const struct pmc_bit_map adl_vnn_req_status_1_map[] = { {} }; -const struct pmc_bit_map adl_vnn_req_status_2_map[] = { +static const struct pmc_bit_map adl_vnn_req_status_2_map[] = { {"CSMERTC_VNN_REQ_STS", BIT(1)}, {"CSE_VNN_REQ_STS", BIT(4)}, {"SMT1_VNN_REQ_STS", BIT(8)}, @@ -245,12 +245,12 @@ const struct pmc_bit_map adl_vnn_req_status_2_map[] = { {} }; -const struct pmc_bit_map adl_vnn_req_status_3_map[] = { +static const struct pmc_bit_map adl_vnn_req_status_3_map[] = { {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, {} }; -const struct pmc_bit_map adl_vnn_misc_status_map[] = { +static const struct pmc_bit_map adl_vnn_misc_status_map[] = { {"CPU_C10_REQ_STS", BIT(0)}, {"PCIe_LPM_En_REQ_STS", BIT(3)}, {"ITH_REQ_STS", BIT(5)}, @@ -265,7 +265,7 @@ const struct pmc_bit_map adl_vnn_misc_status_map[] = { {} }; -const struct pmc_bit_map *adl_lpm_maps[] = { +static const struct pmc_bit_map *adl_lpm_maps[] = { adl_clocksource_status_map, adl_power_gating_status_0_map, adl_power_gating_status_1_map, @@ -311,20 +311,8 @@ const struct pmc_reg_map adl_reg_map = { .pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP, }; -int adl_core_init(struct pmc_dev *pmcdev) -{ - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; - int ret; - - pmcdev->suspend = cnl_suspend; - pmcdev->resume = cnl_resume; - - pmc->map = &adl_reg_map; - ret = get_primary_reg_base(pmc); - if (ret) - return ret; - - pmc_core_get_low_power_modes(pmcdev); - - return 0; -} +struct pmc_dev_info adl_pmc_dev = { + .map = &adl_reg_map, + .suspend = cnl_suspend, + .resume = cnl_resume, +}; diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c index 05dec4f5019f..9d66d65e7577 100644 --- a/drivers/platform/x86/intel/pmc/arl.c +++ b/drivers/platform/x86/intel/pmc/arl.c @@ -10,16 +10,16 @@ #include <linux/pci.h> #include "core.h" -#include "../pmt/telemetry.h" /* PMC SSRAM PMT Telemetry GUID */ #define IOEP_LPM_REQ_GUID 0x5077612 #define SOCS_LPM_REQ_GUID 0x8478657 #define PCHS_LPM_REQ_GUID 0x9684572 +#define SOCM_LPM_REQ_GUID 0x2625030 static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; -const struct pmc_bit_map arl_socs_ltr_show_map[] = { +static const struct pmc_bit_map arl_socs_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, {"SATA", CNP_PMC_LTR_SATA}, @@ -59,7 +59,7 @@ const struct pmc_bit_map arl_socs_ltr_show_map[] = { {} }; -const struct pmc_bit_map arl_socs_clocksource_status_map[] = { +static const struct pmc_bit_map arl_socs_clocksource_status_map[] = { {"AON2_OFF_STS", BIT(0)}, {"AON3_OFF_STS", BIT(1)}, {"AON4_OFF_STS", BIT(2)}, @@ -87,7 +87,7 @@ const struct pmc_bit_map arl_socs_clocksource_status_map[] = { {} }; -const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = { +static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = { {"PMC_PGD0_PG_STS", BIT(0)}, {"DMI_PGD0_PG_STS", BIT(1)}, {"ESPISPI_PGD0_PG_STS", BIT(2)}, @@ -123,7 +123,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = { {} }; -const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = { +static const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = { {"USBR0_PGD0_PG_STS", BIT(0)}, {"SUSRAM_PGD0_PG_STS", BIT(1)}, {"SMT1_PGD0_PG_STS", BIT(2)}, @@ -159,7 +159,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = { {} }; -const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = { +static const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = { {"PSF8_PGD0_PG_STS", BIT(0)}, {"FIA_PGD0_PG_STS", BIT(1)}, {"SOC_D2D_PGD3_PG_STS", BIT(2)}, @@ -187,7 +187,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = { {} }; -const struct pmc_bit_map arl_socs_d3_status_2_map[] = { +static const struct pmc_bit_map arl_socs_d3_status_2_map[] = { {"CSMERTC_D3_STS", BIT(1)}, {"SUSRAM_D3_STS", BIT(2)}, {"CSE_D3_STS", BIT(4)}, @@ -206,7 +206,7 @@ const struct pmc_bit_map arl_socs_d3_status_2_map[] = { {} }; -const struct pmc_bit_map arl_socs_d3_status_3_map[] = { +static const struct pmc_bit_map arl_socs_d3_status_3_map[] = { {"GBETSN_D3_STS", BIT(13)}, {"THC0_D3_STS", BIT(14)}, {"THC1_D3_STS", BIT(15)}, @@ -214,13 +214,13 @@ const struct pmc_bit_map arl_socs_d3_status_3_map[] = { {} }; -const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = { +static const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = { {"DTS0_VNN_REQ_STS", BIT(7)}, {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, {} }; -const struct pmc_bit_map *arl_socs_lpm_maps[] = { +static const struct pmc_bit_map *arl_socs_lpm_maps[] = { arl_socs_clocksource_status_map, arl_socs_power_gating_status_0_map, arl_socs_power_gating_status_1_map, @@ -238,7 +238,7 @@ const struct pmc_bit_map *arl_socs_lpm_maps[] = { NULL }; -const struct pmc_bit_map arl_socs_pfear_map[] = { +static const struct pmc_bit_map arl_socs_pfear_map[] = { {"RSVD64", BIT(0)}, {"RSVD65", BIT(1)}, {"RSVD66", BIT(2)}, @@ -249,13 +249,13 @@ const struct pmc_bit_map arl_socs_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_arl_socs_pfear_map[] = { +static const struct pmc_bit_map *ext_arl_socs_pfear_map[] = { mtl_socm_pfear_map, arl_socs_pfear_map, NULL }; -const struct pmc_reg_map arl_socs_reg_map = { +static const struct pmc_reg_map arl_socs_reg_map = { .pfear_sts = ext_arl_socs_pfear_map, .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, @@ -283,7 +283,7 @@ const struct pmc_reg_map arl_socs_reg_map = { .pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP, }; -const struct pmc_bit_map arl_pchs_ltr_show_map[] = { +static const struct pmc_bit_map arl_pchs_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, {"SATA", CNP_PMC_LTR_SATA}, @@ -323,7 +323,7 @@ const struct pmc_bit_map arl_pchs_ltr_show_map[] = { {} }; -const struct pmc_bit_map arl_pchs_clocksource_status_map[] = { +static const struct pmc_bit_map arl_pchs_clocksource_status_map[] = { {"AON2_OFF_STS", BIT(0)}, {"AON3_OFF_STS", BIT(1)}, {"AON4_OFF_STS", BIT(2)}, @@ -358,7 +358,7 @@ const struct pmc_bit_map arl_pchs_clocksource_status_map[] = { {} }; -const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = { +static const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = { {"PMC_PGD0_PG_STS", BIT(0)}, {"DMI_PGD0_PG_STS", BIT(1)}, {"ESPISPI_PGD0_PG_STS", BIT(2)}, @@ -394,7 +394,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = { {} }; -const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = { +static const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = { {"USBR0_PGD0_PG_STS", BIT(0)}, {"SUSRAM_PGD0_PG_STS", BIT(1)}, {"SMT1_PGD0_PG_STS", BIT(2)}, @@ -430,7 +430,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = { {} }; -const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = { +static const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = { {"U3FPW2_PGD0_PG_STS", BIT(0)}, {"FIA_PGD0_PG_STS", BIT(1)}, {"FIACPCB_X_PGD0_PG_STS", BIT(2)}, @@ -457,7 +457,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = { {} }; -const struct pmc_bit_map arl_pchs_d3_status_0_map[] = { +static const struct pmc_bit_map arl_pchs_d3_status_0_map[] = { {"SPF_D3_STS", BIT(0)}, {"LPSS_D3_STS", BIT(3)}, {"XDCI_D3_STS", BIT(4)}, @@ -474,7 +474,7 @@ const struct pmc_bit_map arl_pchs_d3_status_0_map[] = { {} }; -const struct pmc_bit_map arl_pchs_d3_status_1_map[] = { +static const struct pmc_bit_map arl_pchs_d3_status_1_map[] = { {"GBETSN1_D3_STS", BIT(14)}, {"GBE_D3_STS", BIT(19)}, {"ITSS_D3_STS", BIT(23)}, @@ -483,7 +483,7 @@ const struct pmc_bit_map arl_pchs_d3_status_1_map[] = { {} }; -const struct pmc_bit_map arl_pchs_d3_status_2_map[] = { +static const struct pmc_bit_map arl_pchs_d3_status_2_map[] = { {"CSMERTC_D3_STS", BIT(1)}, {"SUSRAM_D3_STS", BIT(2)}, {"CSE_D3_STS", BIT(4)}, @@ -504,7 +504,7 @@ const struct pmc_bit_map arl_pchs_d3_status_2_map[] = { {} }; -const struct pmc_bit_map arl_pchs_d3_status_3_map[] = { +static const struct pmc_bit_map arl_pchs_d3_status_3_map[] = { {"ESE_D3_STS", BIT(3)}, {"GBETSN_D3_STS", BIT(13)}, {"THC0_D3_STS", BIT(14)}, @@ -513,13 +513,13 @@ const struct pmc_bit_map arl_pchs_d3_status_3_map[] = { {} }; -const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = { +static const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = { {"FIA_VNN_REQ_STS", BIT(17)}, {"ESPISPI_VNN_REQ_STS", BIT(18)}, {} }; -const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = { +static const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = { {"NPK_VNN_REQ_STS", BIT(4)}, {"DFXAGG_VNN_REQ_STS", BIT(8)}, {"EXI_VNN_REQ_STS", BIT(9)}, @@ -530,7 +530,7 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = { {} }; -const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = { +static const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = { {"FIA2_VNN_REQ_STS", BIT(0)}, {"CSMERTC_VNN_REQ_STS", BIT(1)}, {"CSE_VNN_REQ_STS", BIT(4)}, @@ -548,7 +548,7 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = { {} }; -const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = { +static const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = { {"ESE_VNN_REQ_STS", BIT(3)}, {"DTS0_VNN_REQ_STS", BIT(7)}, {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, @@ -556,7 +556,7 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = { {} }; -const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = { +static const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = { {"CPU_C10_REQ_STS", BIT(0)}, {"TS_OFF_REQ_STS", BIT(1)}, {"PNDE_MET_REQ_STS", BIT(2)}, @@ -586,7 +586,7 @@ const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = { {} }; -const struct pmc_bit_map arl_pchs_signal_status_map[] = { +static const struct pmc_bit_map arl_pchs_signal_status_map[] = { {"LSX_Wake0_STS", BIT(0)}, {"LSX_Wake1_STS", BIT(1)}, {"LSX_Wake2_STS", BIT(2)}, @@ -606,7 +606,7 @@ const struct pmc_bit_map arl_pchs_signal_status_map[] = { {} }; -const struct pmc_bit_map *arl_pchs_lpm_maps[] = { +static const struct pmc_bit_map *arl_pchs_lpm_maps[] = { arl_pchs_clocksource_status_map, arl_pchs_power_gating_status_0_map, arl_pchs_power_gating_status_1_map, @@ -624,7 +624,7 @@ const struct pmc_bit_map *arl_pchs_lpm_maps[] = { NULL }; -const struct pmc_reg_map arl_pchs_reg_map = { +static const struct pmc_reg_map arl_pchs_reg_map = { .pfear_sts = ext_arl_socs_pfear_map, .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, @@ -650,30 +650,34 @@ const struct pmc_reg_map arl_pchs_reg_map = { .etr3_offset = ETR3_OFFSET, }; -#define PMC_DEVID_SOCS 0xae7f -#define PMC_DEVID_IOEP 0x7ecf -#define PMC_DEVID_PCHS 0x7f27 static struct pmc_info arl_pmc_info_list[] = { { .guid = IOEP_LPM_REQ_GUID, - .devid = PMC_DEVID_IOEP, + .devid = PMC_DEVID_ARL_IOEP, .map = &mtl_ioep_reg_map, }, { .guid = SOCS_LPM_REQ_GUID, - .devid = PMC_DEVID_SOCS, + .devid = PMC_DEVID_ARL_SOCS, .map = &arl_socs_reg_map, }, { .guid = PCHS_LPM_REQ_GUID, - .devid = PMC_DEVID_PCHS, + .devid = PMC_DEVID_ARL_PCHS, .map = &arl_pchs_reg_map, }, + { + .guid = SOCM_LPM_REQ_GUID, + .devid = PMC_DEVID_ARL_SOCM, + .map = &mtl_socm_reg_map, + }, {} }; #define ARL_NPU_PCI_DEV 0xad1d #define ARL_GNA_PCI_DEV 0xae4c +#define ARL_H_NPU_PCI_DEV 0x7d1d +#define ARL_H_GNA_PCI_DEV 0x774c /* * Set power state of select devices that do not have drivers to D3 * so that they do not block Package C entry. @@ -684,6 +688,12 @@ static void arl_d3_fixup(void) pmc_core_set_device_d3(ARL_GNA_PCI_DEV); } +static void arl_h_d3_fixup(void) +{ + pmc_core_set_device_d3(ARL_H_NPU_PCI_DEV); + pmc_core_set_device_d3(ARL_H_GNA_PCI_DEV); +} + static int arl_resume(struct pmc_dev *pmcdev) { arl_d3_fixup(); @@ -691,40 +701,41 @@ static int arl_resume(struct pmc_dev *pmcdev) return cnl_resume(pmcdev); } -int arl_core_init(struct pmc_dev *pmcdev) +static int arl_h_resume(struct pmc_dev *pmcdev) { - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; - int ret; - int func = 0; - bool ssram_init = true; + arl_h_d3_fixup(); + return cnl_resume(pmcdev); +} + +static int arl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) +{ arl_d3_fixup(); - pmcdev->suspend = cnl_suspend; - pmcdev->resume = arl_resume; - pmcdev->regmap_list = arl_pmc_info_list; + return generic_core_init(pmcdev, pmc_dev_info); +} - /* - * If ssram init fails use legacy method to at least get the - * primary PMC - */ - ret = pmc_core_ssram_init(pmcdev, func); - if (ret) { - ssram_init = false; - pmc->map = &arl_socs_reg_map; - - ret = get_primary_reg_base(pmc); - if (ret) - return ret; - } - - pmc_core_get_low_power_modes(pmcdev); - pmc_core_punit_pmt_init(pmcdev, ARL_PMT_DMU_GUID); - - if (ssram_init) { - ret = pmc_core_ssram_get_lpm_reqs(pmcdev); - if (ret) - return ret; - } - - return 0; +static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) +{ + arl_h_d3_fixup(); + return generic_core_init(pmcdev, pmc_dev_info); } + +struct pmc_dev_info arl_pmc_dev = { + .pci_func = 0, + .dmu_guid = ARL_PMT_DMU_GUID, + .regmap_list = arl_pmc_info_list, + .map = &arl_socs_reg_map, + .suspend = cnl_suspend, + .resume = arl_resume, + .init = arl_core_init, +}; + +struct pmc_dev_info arl_h_pmc_dev = { + .pci_func = 2, + .dmu_guid = ARL_PMT_DMU_GUID, + .regmap_list = arl_pmc_info_list, + .map = &mtl_socm_reg_map, + .suspend = cnl_suspend, + .resume = arl_h_resume, + .init = arl_h_core_init, +}; diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/intel/pmc/cnp.c index fc5193fdf8a8..efea4e1ba52b 100644 --- a/drivers/platform/x86/intel/pmc/cnp.c +++ b/drivers/platform/x86/intel/pmc/cnp.c @@ -10,6 +10,7 @@ #include <linux/smp.h> #include <linux/suspend.h> +#include <asm/msr.h> #include "core.h" /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */ @@ -88,7 +89,7 @@ const struct pmc_bit_map cnp_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_cnp_pfear_map[] = { +static const struct pmc_bit_map *ext_cnp_pfear_map[] = { /* * Check intel_pmc_core_ids[] users of cnp_reg_map for * a list of core SoCs using this. @@ -97,7 +98,7 @@ const struct pmc_bit_map *ext_cnp_pfear_map[] = { NULL }; -const struct pmc_bit_map cnp_slps0_dbg0_map[] = { +static const struct pmc_bit_map cnp_slps0_dbg0_map[] = { {"AUDIO_D3", BIT(0)}, {"OTG_D3", BIT(1)}, {"XHCI_D3", BIT(2)}, @@ -110,7 +111,7 @@ const struct pmc_bit_map cnp_slps0_dbg0_map[] = { {} }; -const struct pmc_bit_map cnp_slps0_dbg1_map[] = { +static const struct pmc_bit_map cnp_slps0_dbg1_map[] = { {"SDIO_PLL_OFF", BIT(0)}, {"USB2_PLL_OFF", BIT(1)}, {"AUDIO_PLL_OFF", BIT(2)}, @@ -127,7 +128,7 @@ const struct pmc_bit_map cnp_slps0_dbg1_map[] = { {} }; -const struct pmc_bit_map cnp_slps0_dbg2_map[] = { +static const struct pmc_bit_map cnp_slps0_dbg2_map[] = { {"MPHY_CORE_GATED", BIT(0)}, {"CSME_GATED", BIT(1)}, {"USB2_SUS_GATED", BIT(2)}, @@ -227,10 +228,10 @@ static void disable_c1_auto_demote(void *unused) int cpunum = smp_processor_id(); u64 val; - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, val); + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, val); per_cpu(pkg_cst_config, cpunum) = val; val &= ~NHM_C1_AUTO_DEMOTE; - wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, val); + wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, val); pr_debug("%s: cpu:%d cst %llx\n", __func__, cpunum, val); } @@ -239,7 +240,7 @@ static void restore_c1_auto_demote(void *unused) { int cpunum = smp_processor_id(); - wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, per_cpu(pkg_cst_config, cpunum)); + wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, per_cpu(pkg_cst_config, cpunum)); pr_debug("%s: cpu:%d cst %llx\n", __func__, cpunum, per_cpu(pkg_cst_config, cpunum)); @@ -274,20 +275,9 @@ int cnl_resume(struct pmc_dev *pmcdev) return pmc_core_resume_common(pmcdev); } -int cnp_core_init(struct pmc_dev *pmcdev) -{ - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; - int ret; - - pmcdev->suspend = cnl_suspend; - pmcdev->resume = cnl_resume; - - pmc->map = &cnp_reg_map; - ret = get_primary_reg_base(pmc); - if (ret) - return ret; - - pmc_core_get_low_power_modes(pmcdev); +struct pmc_dev_info cnp_pmc_dev = { + .map = &cnp_reg_map, + .suspend = cnl_suspend, + .resume = cnl_resume, +}; - return 0; -} diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 3e7f99ac8c94..540cd2fb0673 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -22,12 +22,14 @@ #include <linux/suspend.h> #include <linux/units.h> +#include <asm/cpuid/api.h> #include <asm/cpu_device_id.h> #include <asm/intel-family.h> #include <asm/msr.h> #include <asm/tsc.h> #include "core.h" +#include "ssram_telemetry.h" #include "../pmt/telemetry.h" /* Maximum number of modes supported by platfoms that has low power mode capability */ @@ -625,8 +627,8 @@ static u32 convert_ltr_scale(u32 val) static int pmc_core_ltr_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; - u64 decoded_snoop_ltr, decoded_non_snoop_ltr; - u32 ltr_raw_data, scale, val; + u64 decoded_snoop_ltr, decoded_non_snoop_ltr, val; + u32 ltr_raw_data, scale; u16 snoop_ltr, nonsnoop_ltr; unsigned int i, index, ltr_index = 0; @@ -935,13 +937,13 @@ static unsigned int pmc_core_get_crystal_freq(void) { unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; - if (boot_cpu_data.cpuid_level < 0x15) + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) return 0; eax_denominator = ebx_numerator = ecx_hz = edx = 0; - /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); + /* TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); if (ebx_numerator == 0 || eax_denominator == 0) return 0; @@ -1081,7 +1083,7 @@ static int pmc_core_pkgc_show(struct seq_file *s, void *unused) unsigned int index; for (index = 0; map[index].name ; index++) { - if (rdmsrl_safe(map[index].bit_mask, &pcstate_count)) + if (rdmsrq_safe(map[index].bit_mask, &pcstate_count)) continue; pcstate_count *= 1000; @@ -1344,40 +1346,296 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) } } +static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map) +{ + for (; list->map; ++list) + if (list->map == map) + return list->guid; + + return 0; +} + +/* + * This function retrieves low power mode requirement data from PMC Low + * Power Mode (LPM) table. + * + * In telemetry space, the LPM table contains a 4 byte header followed + * by 8 consecutive mode blocks (one for each LPM mode). Each block + * has a 4 byte header followed by a set of registers that describe the + * IP state requirements for the given mode. The IP mapping is platform + * specific but the same for each block, making for easy analysis. + * Platforms only use a subset of the space to track the requirements + * for their IPs. Callers provide the requirement registers they use as + * a list of indices. Each requirement register is associated with an + * IP map that's maintained by the caller. + * + * Header + * +----+----------------------------+----------------------------+ + * | 0 | REVISION | ENABLED MODES | + * +----+--------------+-------------+-------------+--------------+ + * + * Low Power Mode 0 Block + * +----+--------------+-------------+-------------+--------------+ + * | 1 | SUB ID | SIZE | MAJOR | MINOR | + * +----+--------------+-------------+-------------+--------------+ + * | 2 | LPM0 Requirements 0 | + * +----+---------------------------------------------------------+ + * | | ... | + * +----+---------------------------------------------------------+ + * | 29 | LPM0 Requirements 27 | + * +----+---------------------------------------------------------+ + * + * ... + * + * Low Power Mode 7 Block + * +----+--------------+-------------+-------------+--------------+ + * | | SUB ID | SIZE | MAJOR | MINOR | + * +----+--------------+-------------+-------------+--------------+ + * | 60 | LPM7 Requirements 0 | + * +----+---------------------------------------------------------+ + * | | ... | + * +----+---------------------------------------------------------+ + * | 87 | LPM7 Requirements 27 | + * +----+---------------------------------------------------------+ + * + */ +static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc, struct pci_dev *pcidev) +{ + struct telem_endpoint *ep; + const u8 *lpm_indices; + int num_maps, mode_offset = 0; + int ret, mode; + int lpm_size; + u32 guid; + + lpm_indices = pmc->map->lpm_reg_index; + num_maps = pmc->map->lpm_num_maps; + lpm_size = LPM_MAX_NUM_MODES * num_maps; + + guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map); + if (!guid) + return -ENXIO; + + ep = pmt_telem_find_and_register_endpoint(pcidev, guid, 0); + if (IS_ERR(ep)) { + dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %pe", ep); + return -EPROBE_DEFER; + } + + pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev, + lpm_size * sizeof(u32), + GFP_KERNEL); + if (!pmc->lpm_req_regs) { + ret = -ENOMEM; + goto unregister_ep; + } + + mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET; + pmc_for_each_mode(mode, pmcdev) { + u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps); + int m; + + for (m = 0; m < num_maps; m++) { + u8 sample_id = lpm_indices[m] + mode_offset; + + ret = pmt_telem_read32(ep, sample_id, req_offset, 1); + if (ret) { + dev_err(&pmcdev->pdev->dev, + "couldn't read Low Power Mode requirements: %d\n", ret); + goto unregister_ep; + } + ++req_offset; + } + mode_offset += LPM_REG_COUNT + LPM_MODE_OFFSET; + } + +unregister_ep: + pmt_telem_unregister_endpoint(ep); + + return ret; +} + +static int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev, int func) +{ + struct pci_dev *pcidev __free(pci_dev_put) = NULL; + unsigned int i; + int ret; + + pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, func)); + if (!pcidev) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + if (!pmcdev->pmcs[i]) + continue; + + ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i], pcidev); + if (ret) + return ret; + } + + return 0; +} + +static const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid) +{ + for (; list->map; ++list) + if (devid == list->devid) + return list->map; + + return NULL; +} + +static int pmc_core_pmc_add(struct pmc_dev *pmcdev, unsigned int pmc_index) + +{ + struct pmc_ssram_telemetry pmc_ssram_telemetry; + const struct pmc_reg_map *map; + struct pmc *pmc; + int ret; + + ret = pmc_ssram_telemetry_get_pmc_info(pmc_index, &pmc_ssram_telemetry); + if (ret) + return ret; + + map = pmc_core_find_regmap(pmcdev->regmap_list, pmc_ssram_telemetry.devid); + if (!map) + return -ENODEV; + + pmc = pmcdev->pmcs[pmc_index]; + /* Memory for primary PMC has been allocated */ + if (!pmc) { + pmc = devm_kzalloc(&pmcdev->pdev->dev, sizeof(*pmc), GFP_KERNEL); + if (!pmc) + return -ENOMEM; + } + + pmc->map = map; + pmc->base_addr = pmc_ssram_telemetry.base_addr; + pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length); + + if (!pmc->regbase) { + devm_kfree(&pmcdev->pdev->dev, pmc); + return -ENOMEM; + } + + pmcdev->pmcs[pmc_index] = pmc; + + return 0; +} + +static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev) +{ + int ret; + + ret = pmc_core_pmc_add(pmcdev, PMC_IDX_MAIN); + if (ret) + return ret; + + pmc_core_pmc_add(pmcdev, PMC_IDX_IOE); + pmc_core_pmc_add(pmcdev, PMC_IDX_PCH); + + return 0; +} + +/* + * When supported, ssram init is used to achieve all available PMCs. + * If ssram init fails, this function uses legacy method to at least get the + * primary PMC. + */ +int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) +{ + struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; + bool ssram; + int ret; + + pmcdev->suspend = pmc_dev_info->suspend; + pmcdev->resume = pmc_dev_info->resume; + + ssram = pmc_dev_info->regmap_list != NULL; + if (ssram) { + pmcdev->regmap_list = pmc_dev_info->regmap_list; + ret = pmc_core_ssram_get_reg_base(pmcdev); + /* + * EAGAIN error code indicates Intel PMC SSRAM Telemetry driver + * has not finished probe and PMC info is not available yet. Try + * again later. + */ + if (ret == -EAGAIN) + return -EPROBE_DEFER; + + if (ret) { + dev_warn(&pmcdev->pdev->dev, + "Failed to get PMC info from SSRAM, %d, using legacy init\n", ret); + ssram = false; + } + } + + if (!ssram) { + pmc->map = pmc_dev_info->map; + ret = get_primary_reg_base(pmc); + if (ret) + return ret; + } + + pmc_core_get_low_power_modes(pmcdev); + if (pmc_dev_info->dmu_guid) + pmc_core_punit_pmt_init(pmcdev, pmc_dev_info->dmu_guid); + + if (ssram) { + ret = pmc_core_ssram_get_lpm_reqs(pmcdev, pmc_dev_info->pci_func); + if (ret) + goto unmap_regbase; + } + + return 0; + +unmap_regbase: + for (unsigned int i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + struct pmc *pmc = pmcdev->pmcs[i]; + + if (pmc && pmc->regbase) + iounmap(pmc->regbase); + } + + if (pmcdev->punit_ep) + pmt_telem_unregister_endpoint(pmcdev->punit_ep); + + return ret; +} + static const struct x86_cpu_id intel_pmc_core_ids[] = { - X86_MATCH_VFM(INTEL_SKYLAKE_L, spt_core_init), - X86_MATCH_VFM(INTEL_SKYLAKE, spt_core_init), - X86_MATCH_VFM(INTEL_KABYLAKE_L, spt_core_init), - X86_MATCH_VFM(INTEL_KABYLAKE, spt_core_init), - X86_MATCH_VFM(INTEL_CANNONLAKE_L, cnp_core_init), - X86_MATCH_VFM(INTEL_ICELAKE_L, icl_core_init), - X86_MATCH_VFM(INTEL_ICELAKE_NNPI, icl_core_init), - X86_MATCH_VFM(INTEL_COMETLAKE, cnp_core_init), - X86_MATCH_VFM(INTEL_COMETLAKE_L, cnp_core_init), - X86_MATCH_VFM(INTEL_TIGERLAKE_L, tgl_l_core_init), - X86_MATCH_VFM(INTEL_TIGERLAKE, tgl_core_init), - X86_MATCH_VFM(INTEL_ATOM_TREMONT, tgl_l_core_init), - X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, icl_core_init), - X86_MATCH_VFM(INTEL_ROCKETLAKE, tgl_core_init), - X86_MATCH_VFM(INTEL_ALDERLAKE_L, tgl_l_core_init), - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, tgl_l_core_init), - X86_MATCH_VFM(INTEL_ALDERLAKE, adl_core_init), - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, tgl_l_core_init), - X86_MATCH_VFM(INTEL_RAPTORLAKE, adl_core_init), - X86_MATCH_VFM(INTEL_RAPTORLAKE_S, adl_core_init), - X86_MATCH_VFM(INTEL_METEORLAKE_L, mtl_core_init), - X86_MATCH_VFM(INTEL_ARROWLAKE, arl_core_init), - X86_MATCH_VFM(INTEL_LUNARLAKE_M, lnl_core_init), + X86_MATCH_VFM(INTEL_SKYLAKE_L, &spt_pmc_dev), + X86_MATCH_VFM(INTEL_SKYLAKE, &spt_pmc_dev), + X86_MATCH_VFM(INTEL_KABYLAKE_L, &spt_pmc_dev), + X86_MATCH_VFM(INTEL_KABYLAKE, &spt_pmc_dev), + X86_MATCH_VFM(INTEL_CANNONLAKE_L, &cnp_pmc_dev), + X86_MATCH_VFM(INTEL_ICELAKE_L, &icl_pmc_dev), + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &icl_pmc_dev), + X86_MATCH_VFM(INTEL_COMETLAKE, &cnp_pmc_dev), + X86_MATCH_VFM(INTEL_COMETLAKE_L, &cnp_pmc_dev), + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &tgl_l_pmc_dev), + X86_MATCH_VFM(INTEL_TIGERLAKE, &tgl_pmc_dev), + X86_MATCH_VFM(INTEL_ATOM_TREMONT, &tgl_l_pmc_dev), + X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &icl_pmc_dev), + X86_MATCH_VFM(INTEL_ROCKETLAKE, &tgl_pmc_dev), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &tgl_l_pmc_dev), + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &tgl_l_pmc_dev), + X86_MATCH_VFM(INTEL_ALDERLAKE, &adl_pmc_dev), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &tgl_l_pmc_dev), + X86_MATCH_VFM(INTEL_RAPTORLAKE, &adl_pmc_dev), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &adl_pmc_dev), + X86_MATCH_VFM(INTEL_METEORLAKE_L, &mtl_pmc_dev), + X86_MATCH_VFM(INTEL_ARROWLAKE, &arl_pmc_dev), + X86_MATCH_VFM(INTEL_ARROWLAKE_H, &arl_h_pmc_dev), + X86_MATCH_VFM(INTEL_ARROWLAKE_U, &arl_h_pmc_dev), + X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_pmc_dev), + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &ptl_pmc_dev), {} }; MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids); -static const struct pci_device_id pmc_pci_ids[] = { - { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) }, - { } -}; - /* * This quirk can be used on those platforms where * the platform BIOS enforces 24Mhz crystal to shutdown @@ -1430,20 +1688,14 @@ static void pmc_core_clean_structure(struct platform_device *pdev) for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { struct pmc *pmc = pmcdev->pmcs[i]; - if (pmc) + if (pmc && pmc->regbase) iounmap(pmc->regbase); } - if (pmcdev->ssram_pcidev) { - pci_dev_put(pmcdev->ssram_pcidev); - pci_disable_device(pmcdev->ssram_pcidev); - } - if (pmcdev->punit_ep) pmt_telem_unregister_endpoint(pmcdev->punit_ep); platform_set_drvdata(pdev, NULL); - mutex_destroy(&pmcdev->lock); } static int pmc_core_probe(struct platform_device *pdev) @@ -1451,7 +1703,7 @@ static int pmc_core_probe(struct platform_device *pdev) static bool device_initialized; struct pmc_dev *pmcdev; const struct x86_cpu_id *cpu_id; - int (*core_init)(struct pmc_dev *pmcdev); + struct pmc_dev_info *pmc_dev_info; struct pmc *primary_pmc; int ret; @@ -1471,7 +1723,7 @@ static int pmc_core_probe(struct platform_device *pdev) if (!cpu_id) return -ENODEV; - core_init = (int (*)(struct pmc_dev *))cpu_id->driver_data; + pmc_dev_info = (struct pmc_dev_info *)cpu_id->driver_data; /* Primary PMC */ primary_pmc = devm_kzalloc(&pdev->dev, sizeof(*primary_pmc), GFP_KERNEL); @@ -1488,18 +1740,17 @@ static int pmc_core_probe(struct platform_device *pdev) if (!pmcdev->pkgc_res_cnt) return -ENOMEM; - /* - * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here - * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap - * in this case. - */ - if (core_init == spt_core_init && !pci_dev_present(pmc_pci_ids)) - core_init = cnp_core_init; + ret = devm_mutex_init(&pdev->dev, &pmcdev->lock); + if (ret) + return ret; + + if (pmc_dev_info->init) + ret = pmc_dev_info->init(pmcdev, pmc_dev_info); + else + ret = generic_core_init(pmcdev, pmc_dev_info); - mutex_init(&pmcdev->lock); - ret = core_init(pmcdev); if (ret) { - pmc_core_clean_structure(pdev); + platform_set_drvdata(pdev, NULL); return ret; } @@ -1549,7 +1800,7 @@ static __maybe_unused int pmc_core_suspend(struct device *dev) /* Save PKGC residency for checking later */ for (i = 0; i < pmcdev->num_of_pkgc; i++) { - if (rdmsrl_safe(msr_map[i].bit_mask, &pmcdev->pkgc_res_cnt[i])) + if (rdmsrq_safe(msr_map[i].bit_mask, &pmcdev->pkgc_res_cnt[i])) return -EIO; } @@ -1565,7 +1816,7 @@ static inline bool pmc_core_is_deepest_pkgc_failed(struct pmc_dev *pmcdev) u32 deepest_pkgc_msr = msr_map[pmcdev->num_of_pkgc - 1].bit_mask; u64 deepest_pkgc_residency; - if (rdmsrl_safe(deepest_pkgc_msr, &deepest_pkgc_residency)) + if (rdmsrq_safe(deepest_pkgc_msr, &deepest_pkgc_residency)) return false; if (deepest_pkgc_residency == pmcdev->pkgc_res_cnt[pmcdev->num_of_pkgc - 1]) @@ -1617,7 +1868,7 @@ int pmc_core_resume_common(struct pmc_dev *pmcdev) for (i = 0; i < pmcdev->num_of_pkgc; i++) { u64 pc_cnt; - if (!rdmsrl_safe(msr_map[i].bit_mask, &pc_cnt)) { + if (!rdmsrq_safe(msr_map[i].bit_mask, &pc_cnt)) { dev_info(dev, "Prev %s cnt = 0x%llx, Current %s cnt = 0x%llx\n", msr_map[i].name, pmcdev->pkgc_res_cnt[i], msr_map[i].name, pc_cnt); @@ -1681,5 +1932,6 @@ static struct platform_driver pmc_core_driver = { module_platform_driver(pmc_core_driver); +MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY"); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("Intel PMC Core Driver"); diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index b9d3291d0bf2..e136d18b1d38 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -24,6 +24,11 @@ struct telem_endpoint; #define MAX_NUM_PMC 3 #define S0IX_BLK_SIZE 4 +/* PCH query */ +#define LPM_HEADER_OFFSET 1 +#define LPM_REG_COUNT 28 +#define LPM_MODE_OFFSET 1 + /* Sunrise Point Power Management Controller PCI Device ID */ #define SPT_PMC_PCI_DEVICE_ID 0x9d21 #define SPT_PMC_BASE_ADDR_OFFSET 0x48 @@ -285,6 +290,26 @@ enum ppfear_regs { #define LNL_PPFEAR_NUM_ENTRIES 12 #define LNL_S0IX_BLOCKER_OFFSET 0x2004 +/* Panther Lake Power Management Controller register offsets */ +#define PTL_LPM_NUM_MAPS 14 +#define PTL_PMC_LTR_SATA2 0x1B90 +#define PTL_PMC_LTR_PMC 0x1BA8 +#define PTL_PMC_LTR_CUR_ASLT 0x1C28 +#define PTL_PMC_LTR_CUR_PLT 0x1C2C +#define PTL_PCD_PMC_MMIO_REG_LEN 0x31A8 + +/* SSRAM PMC Device ID */ +/* ARL */ +#define PMC_DEVID_ARL_SOCM 0x777f +#define PMC_DEVID_ARL_SOCS 0xae7f +#define PMC_DEVID_ARL_IOEP 0x7ecf +#define PMC_DEVID_ARL_PCHS 0x7f27 + +/* MTL */ +#define PMC_DEVID_MTL_SOCM 0x7e7f +#define PMC_DEVID_MTL_IOEP 0x7ecf +#define PMC_DEVID_MTL_IOEM 0x7ebf + extern const char *pmc_lpm_modes[]; struct pmc_bit_map { @@ -388,7 +413,6 @@ struct pmc { * struct pmc_dev - pmc device structure * @devs: pointer to an array of pmc pointers * @pdev: pointer to platform_device struct - * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM * @crystal_freq: crystal frequency from cpuid * @dbgfs_dir: path to debugfs interface * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers @@ -408,7 +432,6 @@ struct pmc_dev { struct pmc *pmcs[MAX_NUM_PMC]; struct dentry *dbgfs_dir; struct platform_device *pdev; - struct pci_dev *ssram_pcidev; unsigned int crystal_freq; int pmc_xram_read_bit; struct mutex lock; /* generic mutex lock for PMC Core */ @@ -430,178 +453,74 @@ struct pmc_dev { enum pmc_index { PMC_IDX_MAIN, - PMC_IDX_SOC = PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_PCH, PMC_IDX_MAX }; +/** + * struct pmc_dev_info - Structure to keep PMC device info + * @pci_func: Function number of the primary PMC + * @dmu_guid: Die Management Unit GUID + * @regmap_list: Pointer to a list of pmc_info structure that could be + * available for the platform. When set, this field implies + * SSRAM support. + * @map: Pointer to a pmc_reg_map struct that contains platform + * specific attributes of the primary PMC + * @suspend: Function to perform platform specific suspend + * @resume: Function to perform platform specific resume + * @init: Function to perform platform specific init action + */ +struct pmc_dev_info { + u8 pci_func; + u32 dmu_guid; + struct pmc_info *regmap_list; + const struct pmc_reg_map *map; + void (*suspend)(struct pmc_dev *pmcdev); + int (*resume)(struct pmc_dev *pmcdev); + int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info); +}; + extern const struct pmc_bit_map msr_map[]; -extern const struct pmc_bit_map spt_pll_map[]; -extern const struct pmc_bit_map spt_mphy_map[]; -extern const struct pmc_bit_map spt_pfear_map[]; -extern const struct pmc_bit_map *ext_spt_pfear_map[]; -extern const struct pmc_bit_map spt_ltr_show_map[]; -extern const struct pmc_reg_map spt_reg_map; extern const struct pmc_bit_map cnp_pfear_map[]; -extern const struct pmc_bit_map *ext_cnp_pfear_map[]; -extern const struct pmc_bit_map cnp_slps0_dbg0_map[]; -extern const struct pmc_bit_map cnp_slps0_dbg1_map[]; -extern const struct pmc_bit_map cnp_slps0_dbg2_map[]; extern const struct pmc_bit_map *cnp_slps0_dbg_maps[]; extern const struct pmc_bit_map cnp_ltr_show_map[]; extern const struct pmc_reg_map cnp_reg_map; -extern const struct pmc_bit_map icl_pfear_map[]; -extern const struct pmc_bit_map *ext_icl_pfear_map[]; -extern const struct pmc_reg_map icl_reg_map; -extern const struct pmc_bit_map tgl_pfear_map[]; -extern const struct pmc_bit_map *ext_tgl_pfear_map[]; -extern const struct pmc_bit_map tgl_clocksource_status_map[]; -extern const struct pmc_bit_map tgl_power_gating_status_map[]; -extern const struct pmc_bit_map tgl_d3_status_map[]; -extern const struct pmc_bit_map tgl_vnn_req_status_map[]; -extern const struct pmc_bit_map tgl_vnn_misc_status_map[]; extern const struct pmc_bit_map tgl_signal_status_map[]; -extern const struct pmc_bit_map *tgl_lpm_maps[]; -extern const struct pmc_reg_map tgl_reg_map; -extern const struct pmc_reg_map tgl_h_reg_map; -extern const struct pmc_bit_map adl_pfear_map[]; -extern const struct pmc_bit_map *ext_adl_pfear_map[]; -extern const struct pmc_bit_map adl_ltr_show_map[]; -extern const struct pmc_bit_map adl_clocksource_status_map[]; -extern const struct pmc_bit_map adl_power_gating_status_0_map[]; -extern const struct pmc_bit_map adl_power_gating_status_1_map[]; -extern const struct pmc_bit_map adl_power_gating_status_2_map[]; -extern const struct pmc_bit_map adl_d3_status_0_map[]; -extern const struct pmc_bit_map adl_d3_status_1_map[]; -extern const struct pmc_bit_map adl_d3_status_2_map[]; -extern const struct pmc_bit_map adl_d3_status_3_map[]; -extern const struct pmc_bit_map adl_vnn_req_status_0_map[]; -extern const struct pmc_bit_map adl_vnn_req_status_1_map[]; -extern const struct pmc_bit_map adl_vnn_req_status_2_map[]; -extern const struct pmc_bit_map adl_vnn_req_status_3_map[]; -extern const struct pmc_bit_map adl_vnn_misc_status_map[]; -extern const struct pmc_bit_map *adl_lpm_maps[]; extern const struct pmc_reg_map adl_reg_map; extern const struct pmc_bit_map mtl_socm_pfear_map[]; -extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[]; -extern const struct pmc_bit_map mtl_socm_ltr_show_map[]; -extern const struct pmc_bit_map mtl_socm_clocksource_status_map[]; -extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[]; -extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[]; -extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[]; extern const struct pmc_bit_map mtl_socm_d3_status_0_map[]; extern const struct pmc_bit_map mtl_socm_d3_status_1_map[]; -extern const struct pmc_bit_map mtl_socm_d3_status_2_map[]; -extern const struct pmc_bit_map mtl_socm_d3_status_3_map[]; extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[]; extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[]; extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[]; -extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[]; extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[]; extern const struct pmc_bit_map mtl_socm_signal_status_map[]; -extern const struct pmc_bit_map *mtl_socm_lpm_maps[]; extern const struct pmc_reg_map mtl_socm_reg_map; -extern const struct pmc_bit_map mtl_ioep_pfear_map[]; -extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[]; -extern const struct pmc_bit_map mtl_ioep_ltr_show_map[]; -extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[]; -extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[]; -extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[]; -extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[]; -extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[]; -extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[]; -extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[]; -extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[]; -extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[]; -extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[]; -extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[]; -extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[]; -extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[]; -extern const struct pmc_bit_map *mtl_ioep_lpm_maps[]; extern const struct pmc_reg_map mtl_ioep_reg_map; -extern const struct pmc_bit_map mtl_ioem_pfear_map[]; -extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[]; -extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[]; -extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[]; -extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; -extern const struct pmc_reg_map mtl_ioem_reg_map; -extern const struct pmc_reg_map lnl_socm_reg_map; - -/* LNL */ -extern const struct pmc_bit_map lnl_ltr_show_map[]; -extern const struct pmc_bit_map lnl_clocksource_status_map[]; -extern const struct pmc_bit_map lnl_power_gating_status_0_map[]; -extern const struct pmc_bit_map lnl_power_gating_status_1_map[]; -extern const struct pmc_bit_map lnl_power_gating_status_2_map[]; -extern const struct pmc_bit_map lnl_d3_status_0_map[]; -extern const struct pmc_bit_map lnl_d3_status_1_map[]; -extern const struct pmc_bit_map lnl_d3_status_2_map[]; -extern const struct pmc_bit_map lnl_d3_status_3_map[]; -extern const struct pmc_bit_map lnl_vnn_req_status_0_map[]; -extern const struct pmc_bit_map lnl_vnn_req_status_1_map[]; -extern const struct pmc_bit_map lnl_vnn_req_status_2_map[]; -extern const struct pmc_bit_map lnl_vnn_req_status_3_map[]; -extern const struct pmc_bit_map lnl_vnn_misc_status_map[]; -extern const struct pmc_bit_map *lnl_lpm_maps[]; -extern const struct pmc_bit_map *lnl_blk_maps[]; -extern const struct pmc_bit_map lnl_pfear_map[]; -extern const struct pmc_bit_map *ext_lnl_pfear_map[]; -extern const struct pmc_bit_map lnl_signal_status_map[]; -/* ARL */ -extern const struct pmc_bit_map arl_socs_ltr_show_map[]; -extern const struct pmc_bit_map arl_socs_clocksource_status_map[]; -extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[]; -extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[]; -extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[]; -extern const struct pmc_bit_map arl_socs_d3_status_2_map[]; -extern const struct pmc_bit_map arl_socs_d3_status_3_map[]; -extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[]; -extern const struct pmc_bit_map *arl_socs_lpm_maps[]; -extern const struct pmc_bit_map arl_socs_pfear_map[]; -extern const struct pmc_bit_map *ext_arl_socs_pfear_map[]; -extern const struct pmc_reg_map arl_socs_reg_map; -extern const struct pmc_bit_map arl_pchs_ltr_show_map[]; -extern const struct pmc_bit_map arl_pchs_clocksource_status_map[]; -extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[]; -extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[]; -extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[]; -extern const struct pmc_bit_map arl_pchs_d3_status_0_map[]; -extern const struct pmc_bit_map arl_pchs_d3_status_1_map[]; -extern const struct pmc_bit_map arl_pchs_d3_status_2_map[]; -extern const struct pmc_bit_map arl_pchs_d3_status_3_map[]; -extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[]; -extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[]; -extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[]; -extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[]; -extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[]; -extern const struct pmc_bit_map arl_pchs_signal_status_map[]; -extern const struct pmc_bit_map *arl_pchs_lpm_maps[]; -extern const struct pmc_reg_map arl_pchs_reg_map; - -extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); -extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev); +void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore); int pmc_core_resume_common(struct pmc_dev *pmcdev); int get_primary_reg_base(struct pmc *pmc); -extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); -extern void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid); -extern void pmc_core_set_device_d3(unsigned int device); - -extern int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func); - -int spt_core_init(struct pmc_dev *pmcdev); -int cnp_core_init(struct pmc_dev *pmcdev); -int icl_core_init(struct pmc_dev *pmcdev); -int tgl_core_init(struct pmc_dev *pmcdev); -int tgl_l_core_init(struct pmc_dev *pmcdev); -int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp); -int adl_core_init(struct pmc_dev *pmcdev); -int mtl_core_init(struct pmc_dev *pmcdev); -int arl_core_init(struct pmc_dev *pmcdev); -int lnl_core_init(struct pmc_dev *pmcdev); +void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); +void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid); +void pmc_core_set_device_d3(unsigned int device); + +int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info); + +extern struct pmc_dev_info spt_pmc_dev; +extern struct pmc_dev_info cnp_pmc_dev; +extern struct pmc_dev_info icl_pmc_dev; +extern struct pmc_dev_info tgl_l_pmc_dev; +extern struct pmc_dev_info tgl_pmc_dev; +extern struct pmc_dev_info adl_pmc_dev; +extern struct pmc_dev_info mtl_pmc_dev; +extern struct pmc_dev_info arl_pmc_dev; +extern struct pmc_dev_info arl_h_pmc_dev; +extern struct pmc_dev_info lnl_pmc_dev; +extern struct pmc_dev_info ptl_pmc_dev; void cnl_suspend(struct pmc_dev *pmcdev); int cnl_resume(struct pmc_dev *pmcdev); diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c deleted file mode 100644 index 739569803017..000000000000 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ /dev/null @@ -1,332 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This file contains functions to handle discovery of PMC metrics located - * in the PMC SSRAM PCI device. - * - * Copyright (c) 2023, Intel Corporation. - * All Rights Reserved. - * - */ - -#include <linux/cleanup.h> -#include <linux/intel_vsec.h> -#include <linux/pci.h> -#include <linux/io-64-nonatomic-lo-hi.h> - -#include "core.h" -#include "../pmt/telemetry.h" - -#define SSRAM_HDR_SIZE 0x100 -#define SSRAM_PWRM_OFFSET 0x14 -#define SSRAM_DVSEC_OFFSET 0x1C -#define SSRAM_DVSEC_SIZE 0x10 -#define SSRAM_PCH_OFFSET 0x60 -#define SSRAM_IOE_OFFSET 0x68 -#define SSRAM_DEVID_OFFSET 0x70 - -/* PCH query */ -#define LPM_HEADER_OFFSET 1 -#define LPM_REG_COUNT 28 -#define LPM_MODE_OFFSET 1 - -DEFINE_FREE(pmc_core_iounmap, void __iomem *, if (_T) iounmap(_T)) - -static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map) -{ - for (; list->map; ++list) - if (list->map == map) - return list->guid; - - return 0; -} - -static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc) -{ - struct telem_endpoint *ep; - const u8 *lpm_indices; - int num_maps, mode_offset = 0; - int ret, mode; - int lpm_size; - u32 guid; - - lpm_indices = pmc->map->lpm_reg_index; - num_maps = pmc->map->lpm_num_maps; - lpm_size = LPM_MAX_NUM_MODES * num_maps; - - guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map); - if (!guid) - return -ENXIO; - - ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0); - if (IS_ERR(ep)) { - dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld", - PTR_ERR(ep)); - return -EPROBE_DEFER; - } - - pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev, - lpm_size * sizeof(u32), - GFP_KERNEL); - if (!pmc->lpm_req_regs) { - ret = -ENOMEM; - goto unregister_ep; - } - - /* - * PMC Low Power Mode (LPM) table - * - * In telemetry space, the LPM table contains a 4 byte header followed - * by 8 consecutive mode blocks (one for each LPM mode). Each block - * has a 4 byte header followed by a set of registers that describe the - * IP state requirements for the given mode. The IP mapping is platform - * specific but the same for each block, making for easy analysis. - * Platforms only use a subset of the space to track the requirements - * for their IPs. Callers provide the requirement registers they use as - * a list of indices. Each requirement register is associated with an - * IP map that's maintained by the caller. - * - * Header - * +----+----------------------------+----------------------------+ - * | 0 | REVISION | ENABLED MODES | - * +----+--------------+-------------+-------------+--------------+ - * - * Low Power Mode 0 Block - * +----+--------------+-------------+-------------+--------------+ - * | 1 | SUB ID | SIZE | MAJOR | MINOR | - * +----+--------------+-------------+-------------+--------------+ - * | 2 | LPM0 Requirements 0 | - * +----+---------------------------------------------------------+ - * | | ... | - * +----+---------------------------------------------------------+ - * | 29 | LPM0 Requirements 27 | - * +----+---------------------------------------------------------+ - * - * ... - * - * Low Power Mode 7 Block - * +----+--------------+-------------+-------------+--------------+ - * | | SUB ID | SIZE | MAJOR | MINOR | - * +----+--------------+-------------+-------------+--------------+ - * | 60 | LPM7 Requirements 0 | - * +----+---------------------------------------------------------+ - * | | ... | - * +----+---------------------------------------------------------+ - * | 87 | LPM7 Requirements 27 | - * +----+---------------------------------------------------------+ - * - */ - mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET; - pmc_for_each_mode(mode, pmcdev) { - u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps); - int m; - - for (m = 0; m < num_maps; m++) { - u8 sample_id = lpm_indices[m] + mode_offset; - - ret = pmt_telem_read32(ep, sample_id, req_offset, 1); - if (ret) { - dev_err(&pmcdev->pdev->dev, - "couldn't read Low Power Mode requirements: %d\n", ret); - devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs); - goto unregister_ep; - } - ++req_offset; - } - mode_offset += LPM_REG_COUNT + LPM_MODE_OFFSET; - } - -unregister_ep: - pmt_telem_unregister_endpoint(ep); - - return ret; -} - -int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev) -{ - int ret, i; - - if (!pmcdev->ssram_pcidev) - return -ENODEV; - - for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { - if (!pmcdev->pmcs[i]) - continue; - - ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]); - if (ret) - return ret; - } - - return 0; -} - -static void -pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram) -{ - struct pci_dev *pcidev = pmcdev->ssram_pcidev; - struct intel_vsec_platform_info info = {}; - struct intel_vsec_header *headers[2] = {}; - struct intel_vsec_header header; - void __iomem *dvsec; - u32 dvsec_offset; - u32 table, hdr; - - ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); - if (!ssram) - return; - - dvsec_offset = readl(ssram + SSRAM_DVSEC_OFFSET); - iounmap(ssram); - - dvsec = ioremap(ssram_base + dvsec_offset, SSRAM_DVSEC_SIZE); - if (!dvsec) - return; - - hdr = readl(dvsec + PCI_DVSEC_HEADER1); - header.id = readw(dvsec + PCI_DVSEC_HEADER2); - header.rev = PCI_DVSEC_HEADER1_REV(hdr); - header.length = PCI_DVSEC_HEADER1_LEN(hdr); - header.num_entries = readb(dvsec + INTEL_DVSEC_ENTRIES); - header.entry_size = readb(dvsec + INTEL_DVSEC_SIZE); - - table = readl(dvsec + INTEL_DVSEC_TABLE); - header.tbir = INTEL_DVSEC_TABLE_BAR(table); - header.offset = INTEL_DVSEC_TABLE_OFFSET(table); - iounmap(dvsec); - - headers[0] = &header; - info.caps = VSEC_CAP_TELEMETRY; - info.headers = headers; - info.base_addr = ssram_base; - info.parent = &pmcdev->pdev->dev; - - intel_vsec_register(pcidev, &info); -} - -static const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid) -{ - for (; list->map; ++list) - if (devid == list->devid) - return list->map; - - return NULL; -} - -static inline u64 get_base(void __iomem *addr, u32 offset) -{ - return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3); -} - -static int -pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base, - const struct pmc_reg_map *reg_map, int pmc_index) -{ - struct pmc *pmc = pmcdev->pmcs[pmc_index]; - - if (!pwrm_base) - return -ENODEV; - - /* Memory for primary PMC has been allocated in core.c */ - if (!pmc) { - pmc = devm_kzalloc(&pmcdev->pdev->dev, sizeof(*pmc), GFP_KERNEL); - if (!pmc) - return -ENOMEM; - } - - pmc->map = reg_map; - pmc->base_addr = pwrm_base; - pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length); - - if (!pmc->regbase) { - devm_kfree(&pmcdev->pdev->dev, pmc); - return -ENOMEM; - } - - pmcdev->pmcs[pmc_index] = pmc; - - return 0; -} - -static int -pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, int pmc_idx, u32 offset) -{ - struct pci_dev *ssram_pcidev = pmcdev->ssram_pcidev; - void __iomem __free(pmc_core_iounmap) *tmp_ssram = NULL; - void __iomem __free(pmc_core_iounmap) *ssram = NULL; - const struct pmc_reg_map *map; - u64 ssram_base, pwrm_base; - u16 devid; - - if (!pmcdev->regmap_list) - return -ENOENT; - - ssram_base = ssram_pcidev->resource[0].start; - tmp_ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); - if (!tmp_ssram) - return -ENOMEM; - - if (pmc_idx != PMC_IDX_MAIN) { - /* - * The secondary PMC BARS (which are behind hidden PCI devices) - * are read from fixed offsets in MMIO of the primary PMC BAR. - * If a device is not present, the value will be 0. - */ - ssram_base = get_base(tmp_ssram, offset); - if (!ssram_base) - return 0; - - ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); - if (!ssram) - return -ENOMEM; - - } else { - ssram = no_free_ptr(tmp_ssram); - } - - pwrm_base = get_base(ssram, SSRAM_PWRM_OFFSET); - devid = readw(ssram + SSRAM_DEVID_OFFSET); - - /* Find and register and PMC telemetry entries */ - pmc_add_pmt(pmcdev, ssram_base, ssram); - - map = pmc_core_find_regmap(pmcdev->regmap_list, devid); - if (!map) - return -ENODEV; - - return pmc_core_pmc_add(pmcdev, pwrm_base, map, pmc_idx); -} - -int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func) -{ - struct pci_dev *pcidev; - int ret; - - pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, func)); - if (!pcidev) - return -ENODEV; - - ret = pcim_enable_device(pcidev); - if (ret) - goto release_dev; - - pmcdev->ssram_pcidev = pcidev; - - ret = pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_MAIN, 0); - if (ret) - goto disable_dev; - - pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); - pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); - - return 0; - -disable_dev: - pmcdev->ssram_pcidev = NULL; - pci_disable_device(pcidev); -release_dev: - pci_dev_put(pcidev); - - return ret; -} -MODULE_IMPORT_NS("INTEL_VSEC"); -MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY"); diff --git a/drivers/platform/x86/intel/pmc/icl.c b/drivers/platform/x86/intel/pmc/icl.c index 71b0fd6cb7d8..db7ed15bf863 100644 --- a/drivers/platform/x86/intel/pmc/icl.c +++ b/drivers/platform/x86/intel/pmc/icl.c @@ -10,7 +10,7 @@ #include "core.h" -const struct pmc_bit_map icl_pfear_map[] = { +static const struct pmc_bit_map icl_pfear_map[] = { {"RES_65", BIT(0)}, {"RES_66", BIT(1)}, {"RES_67", BIT(2)}, @@ -22,7 +22,7 @@ const struct pmc_bit_map icl_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_icl_pfear_map[] = { +static const struct pmc_bit_map *ext_icl_pfear_map[] = { /* * Check intel_pmc_core_ids[] users of icl_reg_map for * a list of core SoCs using this. @@ -32,7 +32,7 @@ const struct pmc_bit_map *ext_icl_pfear_map[] = { NULL }; -const struct pmc_reg_map icl_reg_map = { +static const struct pmc_reg_map icl_reg_map = { .pfear_sts = ext_icl_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP, @@ -50,18 +50,6 @@ const struct pmc_reg_map icl_reg_map = { .etr3_offset = ETR3_OFFSET, }; -int icl_core_init(struct pmc_dev *pmcdev) -{ - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; - int ret; - - pmc->map = &icl_reg_map; - - ret = get_primary_reg_base(pmc); - if (ret) - return ret; - - pmc_core_get_low_power_modes(pmcdev); - - return ret; -} +struct pmc_dev_info icl_pmc_dev = { + .map = &icl_reg_map, +}; diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c index be029f12cdf4..da513c234714 100644 --- a/drivers/platform/x86/intel/pmc/lnl.c +++ b/drivers/platform/x86/intel/pmc/lnl.c @@ -13,7 +13,7 @@ #include "core.h" -const struct pmc_bit_map lnl_ltr_show_map[] = { +static const struct pmc_bit_map lnl_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, {"SATA", CNP_PMC_LTR_SATA}, @@ -55,7 +55,7 @@ const struct pmc_bit_map lnl_ltr_show_map[] = { {} }; -const struct pmc_bit_map lnl_power_gating_status_0_map[] = { +static const struct pmc_bit_map lnl_power_gating_status_0_map[] = { {"PMC_PGD0_PG_STS", BIT(0), 0}, {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0}, {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, @@ -91,7 +91,7 @@ const struct pmc_bit_map lnl_power_gating_status_0_map[] = { {} }; -const struct pmc_bit_map lnl_power_gating_status_1_map[] = { +static const struct pmc_bit_map lnl_power_gating_status_1_map[] = { {"USBR0_PGD0_PG_STS", BIT(0), 1}, {"SUSRAM_PGD0_PG_STS", BIT(1), 1}, {"SMT1_PGD0_PG_STS", BIT(2), 1}, @@ -127,7 +127,7 @@ const struct pmc_bit_map lnl_power_gating_status_1_map[] = { {} }; -const struct pmc_bit_map lnl_power_gating_status_2_map[] = { +static const struct pmc_bit_map lnl_power_gating_status_2_map[] = { {"PSF8_PGD0_PG_STS", BIT(0), 0}, {"SBR16B2_PGD0_PG_STS", BIT(1), 0}, {"D2D_IPU_PGD0_PG_STS", BIT(2), 1}, @@ -163,7 +163,7 @@ const struct pmc_bit_map lnl_power_gating_status_2_map[] = { {} }; -const struct pmc_bit_map lnl_d3_status_0_map[] = { +static const struct pmc_bit_map lnl_d3_status_0_map[] = { {"LPSS_D3_STS", BIT(3), 1}, {"XDCI_D3_STS", BIT(4), 1}, {"XHCI_D3_STS", BIT(5), 1}, @@ -175,7 +175,7 @@ const struct pmc_bit_map lnl_d3_status_0_map[] = { {} }; -const struct pmc_bit_map lnl_d3_status_1_map[] = { +static const struct pmc_bit_map lnl_d3_status_1_map[] = { {"OSSE_SMT1_D3_STS", BIT(7), 0}, {"GBE_D3_STS", BIT(19), 0}, {"ITSS_D3_STS", BIT(23), 0}, @@ -185,7 +185,7 @@ const struct pmc_bit_map lnl_d3_status_1_map[] = { {} }; -const struct pmc_bit_map lnl_d3_status_2_map[] = { +static const struct pmc_bit_map lnl_d3_status_2_map[] = { {"ESE_D3_STS", BIT(0), 0}, {"CSMERTC_D3_STS", BIT(1), 0}, {"SUSRAM_D3_STS", BIT(2), 0}, @@ -205,7 +205,7 @@ const struct pmc_bit_map lnl_d3_status_2_map[] = { {} }; -const struct pmc_bit_map lnl_d3_status_3_map[] = { +static const struct pmc_bit_map lnl_d3_status_3_map[] = { {"THC0_D3_STS", BIT(14), 1}, {"THC1_D3_STS", BIT(15), 1}, {"OSSE_SMT3_D3_STS", BIT(21), 0}, @@ -213,14 +213,14 @@ const struct pmc_bit_map lnl_d3_status_3_map[] = { {} }; -const struct pmc_bit_map lnl_vnn_req_status_0_map[] = { +static const struct pmc_bit_map lnl_vnn_req_status_0_map[] = { {"LPSS_VNN_REQ_STS", BIT(3), 1}, {"OSSE_VNN_REQ_STS", BIT(15), 1}, {"ESPISPI_VNN_REQ_STS", BIT(18), 1}, {} }; -const struct pmc_bit_map lnl_vnn_req_status_1_map[] = { +static const struct pmc_bit_map lnl_vnn_req_status_1_map[] = { {"NPK_VNN_REQ_STS", BIT(4), 1}, {"OSSE_SMT1_VNN_REQ_STS", BIT(7), 1}, {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, @@ -232,7 +232,7 @@ const struct pmc_bit_map lnl_vnn_req_status_1_map[] = { {} }; -const struct pmc_bit_map lnl_vnn_req_status_2_map[] = { +static const struct pmc_bit_map lnl_vnn_req_status_2_map[] = { {"eSE_VNN_REQ_STS", BIT(0), 1}, {"CSMERTC_VNN_REQ_STS", BIT(1), 1}, {"CSE_VNN_REQ_STS", BIT(4), 1}, @@ -249,14 +249,14 @@ const struct pmc_bit_map lnl_vnn_req_status_2_map[] = { {} }; -const struct pmc_bit_map lnl_vnn_req_status_3_map[] = { +static const struct pmc_bit_map lnl_vnn_req_status_3_map[] = { {"DISP_SHIM_VNN_REQ_STS", BIT(2), 0}, {"DTS0_VNN_REQ_STS", BIT(7), 0}, {"GPIOCOM5_VNN_REQ_STS", BIT(11), 2}, {} }; -const struct pmc_bit_map lnl_vnn_misc_status_map[] = { +static const struct pmc_bit_map lnl_vnn_misc_status_map[] = { {"CPU_C10_REQ_STS", BIT(0), 0}, {"TS_OFF_REQ_STS", BIT(1), 0}, {"PNDE_MET_REQ_STS", BIT(2), 1}, @@ -292,7 +292,7 @@ const struct pmc_bit_map lnl_vnn_misc_status_map[] = { {} }; -const struct pmc_bit_map lnl_clocksource_status_map[] = { +static const struct pmc_bit_map lnl_clocksource_status_map[] = { {"AON2_OFF_STS", BIT(0), 0}, {"AON3_OFF_STS", BIT(1), 1}, {"AON4_OFF_STS", BIT(2), 1}, @@ -317,7 +317,7 @@ const struct pmc_bit_map lnl_clocksource_status_map[] = { {} }; -const struct pmc_bit_map lnl_signal_status_map[] = { +static const struct pmc_bit_map lnl_signal_status_map[] = { {"LSX_Wake0_STS", BIT(0), 0}, {"LSX_Wake1_STS", BIT(1), 0}, {"LSX_Wake2_STS", BIT(2), 0}, @@ -337,7 +337,7 @@ const struct pmc_bit_map lnl_signal_status_map[] = { {} }; -const struct pmc_bit_map lnl_rsc_status_map[] = { +static const struct pmc_bit_map lnl_rsc_status_map[] = { {"Memory", 0, 1}, {"PSF0", 0, 1}, {"PSF4", 0, 1}, @@ -349,7 +349,7 @@ const struct pmc_bit_map lnl_rsc_status_map[] = { {} }; -const struct pmc_bit_map *lnl_lpm_maps[] = { +static const struct pmc_bit_map *lnl_lpm_maps[] = { lnl_clocksource_status_map, lnl_power_gating_status_0_map, lnl_power_gating_status_1_map, @@ -367,7 +367,7 @@ const struct pmc_bit_map *lnl_lpm_maps[] = { NULL }; -const struct pmc_bit_map *lnl_blk_maps[] = { +static const struct pmc_bit_map *lnl_blk_maps[] = { lnl_power_gating_status_0_map, lnl_power_gating_status_1_map, lnl_power_gating_status_2_map, @@ -386,7 +386,7 @@ const struct pmc_bit_map *lnl_blk_maps[] = { NULL }; -const struct pmc_bit_map lnl_pfear_map[] = { +static const struct pmc_bit_map lnl_pfear_map[] = { {"PMC_0", BIT(0)}, {"FUSE_OSSE", BIT(1)}, {"ESPISPI", BIT(2)}, @@ -498,12 +498,12 @@ const struct pmc_bit_map lnl_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_lnl_pfear_map[] = { +static const struct pmc_bit_map *ext_lnl_pfear_map[] = { lnl_pfear_map, NULL }; -const struct pmc_reg_map lnl_socm_reg_map = { +static const struct pmc_reg_map lnl_socm_reg_map = { .pfear_sts = ext_lnl_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, @@ -550,22 +550,15 @@ static int lnl_resume(struct pmc_dev *pmcdev) return cnl_resume(pmcdev); } -int lnl_core_init(struct pmc_dev *pmcdev) +static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) { - int ret; - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; - lnl_d3_fixup(); - - pmcdev->suspend = cnl_suspend; - pmcdev->resume = lnl_resume; - - pmc->map = &lnl_socm_reg_map; - ret = get_primary_reg_base(pmc); - if (ret) - return ret; - - pmc_core_get_low_power_modes(pmcdev); - - return 0; + return generic_core_init(pmcdev, pmc_dev_info); } + +struct pmc_dev_info lnl_pmc_dev = { + .map = &lnl_socm_reg_map, + .suspend = cnl_suspend, + .resume = lnl_resume, + .init = lnl_core_init, +}; diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c index 02949fed76e9..faa13a7ee688 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -10,7 +10,6 @@ #include <linux/pci.h> #include "core.h" -#include "../pmt/telemetry.h" /* PMC SSRAM PMT Telemetry GUIDS */ #define SOCP_LPM_REQ_GUID 0x2625030 @@ -102,12 +101,12 @@ const struct pmc_bit_map mtl_socm_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = { +static const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = { mtl_socm_pfear_map, NULL }; -const struct pmc_bit_map mtl_socm_ltr_show_map[] = { +static const struct pmc_bit_map mtl_socm_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, {"SATA", CNP_PMC_LTR_SATA}, @@ -141,7 +140,7 @@ const struct pmc_bit_map mtl_socm_ltr_show_map[] = { {} }; -const struct pmc_bit_map mtl_socm_clocksource_status_map[] = { +static const struct pmc_bit_map mtl_socm_clocksource_status_map[] = { {"AON2_OFF_STS", BIT(0)}, {"AON3_OFF_STS", BIT(1)}, {"AON4_OFF_STS", BIT(2)}, @@ -167,7 +166,7 @@ const struct pmc_bit_map mtl_socm_clocksource_status_map[] = { {} }; -const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = { +static const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = { {"PMC_PGD0_PG_STS", BIT(0)}, {"DMI_PGD0_PG_STS", BIT(1)}, {"ESPISPI_PGD0_PG_STS", BIT(2)}, @@ -203,7 +202,7 @@ const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = { {} }; -const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = { +static const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = { {"USBR0_PGD0_PG_STS", BIT(0)}, {"SUSRAM_PGD0_PG_STS", BIT(1)}, {"SMT1_PGD0_PG_STS", BIT(2)}, @@ -239,7 +238,7 @@ const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = { {} }; -const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = { +static const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = { {"PSF8_PGD0_PG_STS", BIT(0)}, {"FIA_PGD0_PG_STS", BIT(1)}, {"SOC_D2D_PGD1_PG_STS", BIT(2)}, @@ -291,7 +290,7 @@ const struct pmc_bit_map mtl_socm_d3_status_1_map[] = { {} }; -const struct pmc_bit_map mtl_socm_d3_status_2_map[] = { +static const struct pmc_bit_map mtl_socm_d3_status_2_map[] = { {"GNA_D3_STS", BIT(0)}, {"CSMERTC_D3_STS", BIT(1)}, {"SUSRAM_D3_STS", BIT(2)}, @@ -310,7 +309,7 @@ const struct pmc_bit_map mtl_socm_d3_status_2_map[] = { {} }; -const struct pmc_bit_map mtl_socm_d3_status_3_map[] = { +static const struct pmc_bit_map mtl_socm_d3_status_3_map[] = { {"ESE_D3_STS", BIT(2)}, {"GBETSN_D3_STS", BIT(13)}, {"THC0_D3_STS", BIT(14)}, @@ -353,7 +352,7 @@ const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[] = { {} }; -const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = { +static const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = { {"ESE_VNN_REQ_STS", BIT(2)}, {"DTS0_VNN_REQ_STS", BIT(7)}, {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, @@ -432,7 +431,7 @@ const struct pmc_bit_map mtl_socm_signal_status_map[] = { {} }; -const struct pmc_bit_map *mtl_socm_lpm_maps[] = { +static const struct pmc_bit_map *mtl_socm_lpm_maps[] = { mtl_socm_clocksource_status_map, mtl_socm_power_gating_status_0_map, mtl_socm_power_gating_status_1_map, @@ -476,7 +475,7 @@ const struct pmc_reg_map mtl_socm_reg_map = { .lpm_reg_index = MTL_LPM_REG_INDEX, }; -const struct pmc_bit_map mtl_ioep_pfear_map[] = { +static const struct pmc_bit_map mtl_ioep_pfear_map[] = { {"PMC_0", BIT(0)}, {"OPI", BIT(1)}, {"TCSS", BIT(2)}, @@ -563,12 +562,12 @@ const struct pmc_bit_map mtl_ioep_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = { +static const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = { mtl_ioep_pfear_map, NULL }; -const struct pmc_bit_map mtl_ioep_ltr_show_map[] = { +static const struct pmc_bit_map mtl_ioep_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, {"SATA", CNP_PMC_LTR_SATA}, @@ -600,7 +599,7 @@ const struct pmc_bit_map mtl_ioep_ltr_show_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = { +static const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = { {"AON2_OFF_STS", BIT(0)}, {"AON3_OFF_STS", BIT(1)}, {"AON4_OFF_STS", BIT(2)}, @@ -623,7 +622,7 @@ const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = { +static const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = { {"PMC_PGD0_PG_STS", BIT(0)}, {"DMI_PGD0_PG_STS", BIT(1)}, {"TCSS_PGD0_PG_STS", BIT(2)}, @@ -650,7 +649,7 @@ const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = { +static const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = { {"PSF9_PGD0_PG_STS", BIT(0)}, {"MPFPW4_PGD0_PG_STS", BIT(1)}, {"SBR0_PGD0_PG_STS", BIT(8)}, @@ -668,7 +667,7 @@ const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = { +static const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = { {"FIA_PGD0_PG_STS", BIT(1)}, {"FIA_P_PGD0_PG_STS", BIT(3)}, {"TAM_PGD0_PG_STS", BIT(4)}, @@ -680,7 +679,7 @@ const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = { +static const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = { {"SPF_D3_STS", BIT(0)}, {"SPA_D3_STS", BIT(12)}, {"SPB_D3_STS", BIT(13)}, @@ -691,43 +690,43 @@ const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = { +static const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = { {"GBETSN1_D3_STS", BIT(14)}, {"P2S_D3_STS", BIT(24)}, {} }; -const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = { +static const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = { +static const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = { {"GBETSN_D3_STS", BIT(13)}, {"ACE_D3_STS", BIT(23)}, {} }; -const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = { +static const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = { {"FIA_VNN_REQ_STS", BIT(17)}, {} }; -const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = { +static const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = { {"DFXAGG_VNN_REQ_STS", BIT(8)}, {} }; -const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = { +static const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = { {} }; -const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = { +static const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = { {"DTS0_VNN_REQ_STS", BIT(7)}, {"DISP_VNN_REQ_STS", BIT(19)}, {} }; -const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = { +static const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = { {"CPU_C10_REQ_STS", BIT(0)}, {"TS_OFF_REQ_STS", BIT(1)}, {"PNDE_MET_REQ_STS", BIT(2)}, @@ -762,7 +761,7 @@ const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = { {} }; -const struct pmc_bit_map *mtl_ioep_lpm_maps[] = { +static const struct pmc_bit_map *mtl_ioep_lpm_maps[] = { mtl_ioep_clocksource_status_map, mtl_ioep_power_gating_status_0_map, mtl_ioep_power_gating_status_1_map, @@ -800,7 +799,7 @@ const struct pmc_reg_map mtl_ioep_reg_map = { .lpm_reg_index = MTL_LPM_REG_INDEX, }; -const struct pmc_bit_map mtl_ioem_pfear_map[] = { +static const struct pmc_bit_map mtl_ioem_pfear_map[] = { {"PMC_0", BIT(0)}, {"OPI", BIT(1)}, {"TCSS", BIT(2)}, @@ -887,12 +886,12 @@ const struct pmc_bit_map mtl_ioem_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = { +static const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = { mtl_ioem_pfear_map, NULL }; -const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = { +static const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = { {"PSF9_PGD0_PG_STS", BIT(0)}, {"MPFPW4_PGD0_PG_STS", BIT(1)}, {"SBR0_PGD0_PG_STS", BIT(8)}, @@ -909,7 +908,7 @@ const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = { {} }; -const struct pmc_bit_map *mtl_ioem_lpm_maps[] = { +static const struct pmc_bit_map *mtl_ioem_lpm_maps[] = { mtl_ioep_clocksource_status_map, mtl_ioep_power_gating_status_0_map, mtl_ioem_power_gating_status_1_map, @@ -927,7 +926,7 @@ const struct pmc_bit_map *mtl_ioem_lpm_maps[] = { NULL }; -const struct pmc_reg_map mtl_ioem_reg_map = { +static const struct pmc_reg_map mtl_ioem_reg_map = { .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN, .pfear_sts = ext_mtl_ioem_pfear_map, .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, @@ -947,23 +946,20 @@ const struct pmc_reg_map mtl_ioem_reg_map = { .lpm_reg_index = MTL_LPM_REG_INDEX, }; -#define PMC_DEVID_SOCM 0x7e7f -#define PMC_DEVID_IOEP 0x7ecf -#define PMC_DEVID_IOEM 0x7ebf static struct pmc_info mtl_pmc_info_list[] = { { .guid = SOCP_LPM_REQ_GUID, - .devid = PMC_DEVID_SOCM, + .devid = PMC_DEVID_MTL_SOCM, .map = &mtl_socm_reg_map, }, { .guid = IOEP_LPM_REQ_GUID, - .devid = PMC_DEVID_IOEP, + .devid = PMC_DEVID_MTL_IOEP, .map = &mtl_ioep_reg_map, }, { .guid = IOEM_LPM_REQ_GUID, - .devid = PMC_DEVID_IOEM, + .devid = PMC_DEVID_MTL_IOEM, .map = &mtl_ioem_reg_map }, {} @@ -990,39 +986,18 @@ static int mtl_resume(struct pmc_dev *pmcdev) return cnl_resume(pmcdev); } -int mtl_core_init(struct pmc_dev *pmcdev) +static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) { - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; - int ret; - int func = 2; - bool ssram_init = true; - mtl_d3_fixup(); - - pmcdev->suspend = cnl_suspend; - pmcdev->resume = mtl_resume; - pmcdev->regmap_list = mtl_pmc_info_list; - - /* - * If ssram init fails use legacy method to at least get the - * primary PMC - */ - ret = pmc_core_ssram_init(pmcdev, func); - if (ret) { - ssram_init = false; - dev_warn(&pmcdev->pdev->dev, - "ssram init failed, %d, using legacy init\n", ret); - pmc->map = &mtl_socm_reg_map; - ret = get_primary_reg_base(pmc); - if (ret) - return ret; - } - - pmc_core_get_low_power_modes(pmcdev); - pmc_core_punit_pmt_init(pmcdev, MTL_PMT_DMU_GUID); - - if (ssram_init) - return pmc_core_ssram_get_lpm_reqs(pmcdev); - - return 0; + return generic_core_init(pmcdev, pmc_dev_info); } + +struct pmc_dev_info mtl_pmc_dev = { + .pci_func = 2, + .dmu_guid = MTL_PMT_DMU_GUID, + .regmap_list = mtl_pmc_info_list, + .map = &mtl_socm_reg_map, + .suspend = cnl_suspend, + .resume = mtl_resume, + .init = mtl_core_init, +}; diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c new file mode 100644 index 000000000000..394515af60d6 --- /dev/null +++ b/drivers/platform/x86/intel/pmc/ptl.c @@ -0,0 +1,550 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file contains platform specific structure definitions + * and init function used by Panther Lake PCH. + * + * Copyright (c) 2025, Intel Corporation. + */ + +#include <linux/pci.h> + +#include "core.h" + +static const struct pmc_bit_map ptl_pcdp_pfear_map[] = { + {"PMC_0", BIT(0)}, + {"FUSE_OSSE", BIT(1)}, + {"ESPISPI", BIT(2)}, + {"XHCI", BIT(3)}, + {"SPA", BIT(4)}, + {"SPB", BIT(5)}, + {"MPFPW2", BIT(6)}, + {"GBE", BIT(7)}, + + {"SBR16B20", BIT(0)}, + {"SBR8B20", BIT(1)}, + {"SBR16B21", BIT(2)}, + {"DBG_SBR16B", BIT(3)}, + {"OSSE_HOTHAM", BIT(4)}, + {"D2D_DISP_1", BIT(5)}, + {"LPSS", BIT(6)}, + {"LPC", BIT(7)}, + + {"SMB", BIT(0)}, + {"ISH", BIT(1)}, + {"SBR16B2", BIT(2)}, + {"NPK_0", BIT(3)}, + {"D2D_NOC_1", BIT(4)}, + {"SBR8B2", BIT(5)}, + {"FUSE", BIT(6)}, + {"SBR16B0", BIT(7)}, + + {"PSF0", BIT(0)}, + {"XDCI", BIT(1)}, + {"EXI", BIT(2)}, + {"CSE", BIT(3)}, + {"KVMCC", BIT(4)}, + {"PMT", BIT(5)}, + {"CLINK", BIT(6)}, + {"PTIO", BIT(7)}, + + {"USBR0", BIT(0)}, + {"SUSRAM", BIT(1)}, + {"SMT1", BIT(2)}, + {"MPFPW1", BIT(3)}, + {"SMS2", BIT(4)}, + {"SMS1", BIT(5)}, + {"CSMERTC", BIT(6)}, + {"CSMEPSF", BIT(7)}, + + {"D2D_NOC_0", BIT(0)}, + {"ESE", BIT(1)}, + {"P2SB8B", BIT(2)}, + {"SBR16B7", BIT(3)}, + {"SBR16B3", BIT(4)}, + {"OSSE_SMT1", BIT(5)}, + {"D2D_DISP", BIT(6)}, + {"DBG_SBR", BIT(7)}, + + {"U3FPW1", BIT(0)}, + {"FIA_X", BIT(1)}, + {"PSF4", BIT(2)}, + {"CNVI", BIT(3)}, + {"UFSX2", BIT(4)}, + {"ENDBG", BIT(5)}, + {"DBC", BIT(6)}, + {"FIA_PG", BIT(7)}, + + {"D2D_IPU", BIT(0)}, + {"NPK1", BIT(1)}, + {"FIACPCB_X", BIT(2)}, + {"SBR8B4", BIT(3)}, + {"DBG_PSF", BIT(4)}, + {"PSF6", BIT(5)}, + {"UFSPW1", BIT(6)}, + {"FIA_U", BIT(7)}, + + {"PSF8", BIT(0)}, + {"SBR16B4", BIT(1)}, + {"SBR16B5", BIT(2)}, + {"FIACPCB_U", BIT(3)}, + {"TAM", BIT(4)}, + {"D2D_NOC_2", BIT(5)}, + {"TBTLSX", BIT(6)}, + {"THC0", BIT(7)}, + + {"THC1", BIT(0)}, + {"PMC_1", BIT(1)}, + {"SBR8B1", BIT(2)}, + {"TCSS", BIT(3)}, + {"DISP_PGA", BIT(4)}, + {"SBR16B1", BIT(5)}, + {"SBRG", BIT(6)}, + {"PSF5", BIT(7)}, + + {"P2SB16B", BIT(0)}, + {"ACE_0", BIT(1)}, + {"ACE_1", BIT(2)}, + {"ACE_2", BIT(3)}, + {"ACE_3", BIT(4)}, + {"ACE_4", BIT(5)}, + {"ACE_5", BIT(6)}, + {"ACE_6", BIT(7)}, + + {"ACE_7", BIT(0)}, + {"ACE_8", BIT(1)}, + {"ACE_9", BIT(2)}, + {"ACE_10", BIT(3)}, + {"FIACPCB_PG", BIT(4)}, + {"SBR16B6", BIT(5)}, + {"OSSE", BIT(6)}, + {"SBR8B0", BIT(7)}, + {} +}; + +static const struct pmc_bit_map *ext_ptl_pcdp_pfear_map[] = { + ptl_pcdp_pfear_map, + NULL +}; + +static const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = { + {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, + {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, + {"SATA", CNP_PMC_LTR_SATA}, + {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, + {"XHCI", CNP_PMC_LTR_XHCI}, + {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, + {"ME", CNP_PMC_LTR_ME}, + {"SATA1", CNP_PMC_LTR_EVA}, + {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, + {"HD_AUDIO", CNP_PMC_LTR_AZ}, + {"CNV", CNP_PMC_LTR_CNV}, + {"LPSS", CNP_PMC_LTR_LPSS}, + {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, + {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, + {"SATA2", PTL_PMC_LTR_SATA2}, + {"ESPI", CNP_PMC_LTR_ESPI}, + {"SCC", CNP_PMC_LTR_SCC}, + {"ISH", CNP_PMC_LTR_ISH}, + {"UFSX2", CNP_PMC_LTR_UFSX2}, + {"EMMC", CNP_PMC_LTR_EMMC}, + {"WIGIG", ICL_PMC_LTR_WIGIG}, + {"THC0", TGL_PMC_LTR_THC0}, + {"THC1", TGL_PMC_LTR_THC1}, + {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, + {"ESE", MTL_PMC_LTR_ESE}, + {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, + {"DMI3", ARL_PMC_LTR_DMI3}, + {"OSSE", LNL_PMC_LTR_OSSE}, + + /* Below two cannot be used for LTR_IGNORE */ + {"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT}, + {"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_clocksource_status_map[] = { + {"AON2_OFF_STS", BIT(0), 1}, + {"AON3_OFF_STS", BIT(1), 0}, + {"AON4_OFF_STS", BIT(2), 1}, + {"AON5_OFF_STS", BIT(3), 1}, + {"AON1_OFF_STS", BIT(4), 0}, + {"XTAL_LVM_OFF_STS", BIT(5), 0}, + {"MPFPW1_0_PLL_OFF_STS", BIT(6), 1}, + {"USB3_PLL_OFF_STS", BIT(8), 1}, + {"AON3_SPL_OFF_STS", BIT(9), 1}, + {"MPFPW2_0_PLL_OFF_STS", BIT(12), 1}, + {"XTAL_AGGR_OFF_STS", BIT(17), 1}, + {"USB2_PLL_OFF_STS", BIT(18), 0}, + {"SAF_PLL_OFF_STS", BIT(19), 1}, + {"SE_TCSS_PLL_OFF_STS", BIT(20), 1}, + {"DDI_PLL_OFF_STS", BIT(21), 1}, + {"FILTER_PLL_OFF_STS", BIT(22), 1}, + {"ACE_PLL_OFF_STS", BIT(24), 0}, + {"FABRIC_PLL_OFF_STS", BIT(25), 1}, + {"SOC_PLL_OFF_STS", BIT(26), 1}, + {"REF_PLL_OFF_STS", BIT(28), 1}, + {"IMG_PLL_OFF_STS", BIT(29), 1}, + {"RTC_PLL_OFF_STS", BIT(31), 0}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_power_gating_status_0_map[] = { + {"PMC_PGD0_PG_STS", BIT(0), 0}, + {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0}, + {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, + {"XHCI_PGD0_PG_STS", BIT(3), 1}, + {"SPA_PGD0_PG_STS", BIT(4), 1}, + {"SPB_PGD0_PG_STS", BIT(5), 1}, + {"MPFPW2_PGD0_PG_STS", BIT(6), 0}, + {"GBE_PGD0_PG_STS", BIT(7), 1}, + {"SBR16B20_PGD0_PG_STS", BIT(8), 0}, + {"SBR8B20_PGD0_PG_STS", BIT(9), 0}, + {"SBR16B21_PGD0_PG_STS", BIT(10), 0}, + {"DBG_PGD0_PG_STS", BIT(11), 0}, + {"OSSE_HOTHAM_PGD0_PG_STS", BIT(12), 1}, + {"D2D_DISP_PGD1_PG_STS", BIT(13), 1}, + {"LPSS_PGD0_PG_STS", BIT(14), 1}, + {"LPC_PGD0_PG_STS", BIT(15), 0}, + {"SMB_PGD0_PG_STS", BIT(16), 0}, + {"ISH_PGD0_PG_STS", BIT(17), 0}, + {"SBR16B2_PGD0_PG_STS", BIT(18), 0}, + {"NPK_PGD0_PG_STS", BIT(19), 0}, + {"D2D_NOC_PGD1_PG_STS", BIT(20), 1}, + {"SBR8B2_PGD0_PG_STS", BIT(21), 0}, + {"FUSE_PGD0_PG_STS", BIT(22), 0}, + {"SBR16B0_PGD0_PG_STS", BIT(23), 0}, + {"PSF0_PGD0_PG_STS", BIT(24), 0}, + {"XDCI_PGD0_PG_STS", BIT(25), 1}, + {"EXI_PGD0_PG_STS", BIT(26), 0}, + {"CSE_PGD0_PG_STS", BIT(27), 1}, + {"KVMCC_PGD0_PG_STS", BIT(28), 1}, + {"PMT_PGD0_PG_STS", BIT(29), 1}, + {"CLINK_PGD0_PG_STS", BIT(30), 1}, + {"PTIO_PGD0_PG_STS", BIT(31), 1}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_power_gating_status_1_map[] = { + {"USBR0_PGD0_PG_STS", BIT(0), 1}, + {"SUSRAM_PGD0_PG_STS", BIT(1), 1}, + {"SMT1_PGD0_PG_STS", BIT(2), 1}, + {"MPFPW1_PGD0_PG_STS", BIT(3), 0}, + {"SMS2_PGD0_PG_STS", BIT(4), 1}, + {"SMS1_PGD0_PG_STS", BIT(5), 1}, + {"CSMERTC_PGD0_PG_STS", BIT(6), 0}, + {"CSMEPSF_PGD0_PG_STS", BIT(7), 0}, + {"D2D_NOC_PGD0_PG_STS", BIT(8), 0}, + {"ESE_PGD0_PG_STS", BIT(9), 1}, + {"P2SB8B_PGD0_PG_STS", BIT(10), 1}, + {"SBR16B7_PGD0_PG_STS", BIT(11), 0}, + {"SBR16B3_PGD0_PG_STS", BIT(12), 0}, + {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1}, + {"D2D_DISP_PGD0_PG_STS", BIT(14), 1}, + {"DBG_SBR_PGD0_PG_STS", BIT(15), 0}, + {"U3FPW1_PGD0_PG_STS", BIT(16), 0}, + {"FIA_X_PGD0_PG_STS", BIT(17), 0}, + {"PSF4_PGD0_PG_STS", BIT(18), 0}, + {"CNVI_PGD0_PG_STS", BIT(19), 0}, + {"UFSX2_PGD0_PG_STS", BIT(20), 1}, + {"ENDBG_PGD0_PG_STS", BIT(21), 0}, + {"DBC_PGD0_PG_STS", BIT(22), 0}, + {"FIA_PG_PGD0_PG_STS", BIT(23), 0}, + {"D2D_IPU_PGD0_PG_STS", BIT(24), 1}, + {"NPK_PGD1_PG_STS", BIT(25), 0}, + {"FIACPCB_X_PGD0_PG_STS", BIT(26), 0}, + {"SBR8B4_PGD0_PG_STS", BIT(27), 0}, + {"DBG_PSF_PGD0_PG_STS", BIT(28), 0}, + {"PSF6_PGD0_PG_STS", BIT(29), 0}, + {"UFSPW1_PGD0_PG_STS", BIT(30), 0}, + {"FIA_U_PGD0_PG_STS", BIT(31), 0}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_power_gating_status_2_map[] = { + {"PSF8_PGD0_PG_STS", BIT(0), 0}, + {"SBR16B4_PGD0_PG_STS", BIT(1), 0}, + {"SBR16B5_PGD0_PG_STS", BIT(2), 0}, + {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0}, + {"TAM_PGD0_PG_STS", BIT(4), 1}, + {"D2D_NOC_PGD0_PG_STS", BIT(5), 1}, + {"TBTLSX_PGD0_PG_STS", BIT(6), 1}, + {"THC0_PGD0_PG_STS", BIT(7), 1}, + {"THC1_PGD0_PG_STS", BIT(8), 1}, + {"PMC_PGD1_PG_STS", BIT(9), 0}, + {"SBR8B1_PGD0_PG_STS", BIT(10), 0}, + {"TCSS_PGD0_PG_STS", BIT(11), 0}, + {"DISP_PGA_PGD0_PG_STS", BIT(12), 0}, + {"SBR16B1_PGD0_PG_STS", BIT(13), 0}, + {"SBRG_PGD0_PG_STS", BIT(14), 0}, + {"PSF5_PGD0_PG_STS", BIT(15), 0}, + {"P2SB16B_PGD0_PG_STS", BIT(16), 1}, + {"ACE_PGD0_PG_STS", BIT(17), 0}, + {"ACE_PGD1_PG_STS", BIT(18), 0}, + {"ACE_PGD2_PG_STS", BIT(19), 0}, + {"ACE_PGD3_PG_STS", BIT(20), 0}, + {"ACE_PGD4_PG_STS", BIT(21), 0}, + {"ACE_PGD5_PG_STS", BIT(22), 0}, + {"ACE_PGD6_PG_STS", BIT(23), 0}, + {"ACE_PGD7_PG_STS", BIT(24), 0}, + {"ACE_PGD8_PG_STS", BIT(25), 0}, + {"ACE_PGD9_PG_STS", BIT(26), 0}, + {"ACE_PGD10_PG_STS", BIT(27), 0}, + {"FIACPCB_PG_PGD0_PG_STS", BIT(28), 0}, + {"SBR16B6_PGD0_PG_STS", BIT(29), 0}, + {"OSSE_PGD0_PG_STS", BIT(30), 1}, + {"SBR8B0_PGD0_PG_STS", BIT(31), 0}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_d3_status_0_map[] = { + {"LPSS_D3_STS", BIT(3), 1}, + {"XDCI_D3_STS", BIT(4), 1}, + {"XHCI_D3_STS", BIT(5), 1}, + {"OSSE_D3_STS", BIT(6), 0}, + {"SPA_D3_STS", BIT(12), 0}, + {"SPB_D3_STS", BIT(13), 0}, + {"ESPISPI_D3_STS", BIT(18), 0}, + {"PSTH_D3_STS", BIT(21), 0}, + {"OSSE_SMT1_D3_STS", BIT(30), 0}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_d3_status_1_map[] = { + {"GBE_D3_STS", BIT(19), 0}, + {"ITSS_D3_STS", BIT(23), 0}, + {"CNVI_D3_STS", BIT(27), 0}, + {"UFSX2_D3_STS", BIT(28), 1}, + {"OSSE_HOTHAM_D3_STS", BIT(29), 0}, + {"ESE_D3_STS", BIT(30), 0}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_d3_status_2_map[] = { + {"CSMERTC_D3_STS", BIT(1), 0}, + {"SUSRAM_D3_STS", BIT(2), 0}, + {"CSE_D3_STS", BIT(4), 0}, + {"KVMCC_D3_STS", BIT(5), 0}, + {"USBR0_D3_STS", BIT(6), 0}, + {"ISH_D3_STS", BIT(7), 0}, + {"SMT1_D3_STS", BIT(8), 0}, + {"SMT2_D3_STS", BIT(9), 0}, + {"SMT3_D3_STS", BIT(10), 0}, + {"OSSE_SMT2_D3_STS", BIT(12), 0}, + {"CLINK_D3_STS", BIT(14), 0}, + {"PTIO_D3_STS", BIT(16), 0}, + {"PMT_D3_STS", BIT(17), 0}, + {"SMS1_D3_STS", BIT(18), 0}, + {"SMS2_D3_STS", BIT(19), 0}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_d3_status_3_map[] = { + {"THC0_D3_STS", BIT(14), 1}, + {"THC1_D3_STS", BIT(15), 1}, + {"OSSE_SMT3_D3_STS", BIT(18), 0}, + {"ACE_D3_STS", BIT(23), 0}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_vnn_req_status_0_map[] = { + {"LPSS_VNN_REQ_STS", BIT(3), 1}, + {"OSSE_VNN_REQ_STS", BIT(6), 1}, + {"ESPISPI_VNN_REQ_STS", BIT(18), 1}, + {"OSSE_SMT1_VNN_REQ_STS", BIT(30), 1}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_vnn_req_status_1_map[] = { + {"NPK_VNN_REQ_STS", BIT(4), 1}, + {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, + {"EXI_VNN_REQ_STS", BIT(9), 1}, + {"P2D_VNN_REQ_STS", BIT(18), 1}, + {"GBE_VNN_REQ_STS", BIT(19), 1}, + {"SMB_VNN_REQ_STS", BIT(25), 1}, + {"LPC_VNN_REQ_STS", BIT(26), 0}, + {"ESE_VNN_REQ_STS", BIT(30), 1}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_vnn_req_status_2_map[] = { + {"CSMERTC_VNN_REQ_STS", BIT(1), 1}, + {"CSE_VNN_REQ_STS", BIT(4), 1}, + {"ISH_VNN_REQ_STS", BIT(7), 1}, + {"SMT1_VNN_REQ_STS", BIT(8), 1}, + {"CLINK_VNN_REQ_STS", BIT(14), 1}, + {"SMS1_VNN_REQ_STS", BIT(18), 1}, + {"SMS2_VNN_REQ_STS", BIT(19), 1}, + {"GPIOCOM4_VNN_REQ_STS", BIT(20), 1}, + {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1}, + {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1}, + {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1}, + {"DISP_SHIM_VNN_REQ_STS", BIT(26), 1}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_vnn_req_status_3_map[] = { + {"DTS0_VNN_REQ_STS", BIT(7), 0}, + {"GPIOCOM5_VNN_REQ_STS", BIT(11), 1}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_vnn_misc_status_map[] = { + {"CPU_C10_REQ_STS", BIT(0), 0}, + {"TS_OFF_REQ_STS", BIT(1), 0}, + {"PNDE_MET_REQ_STS", BIT(2), 1}, + {"PG5_PMA0_REQ_STS", BIT(3), 0}, + {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0}, + {"VNN_SOC_REQ_STS", BIT(6), 1}, + {"ISH_VNNAON_REQ_STS", BIT(7), 0}, + {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1}, + {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1}, + {"D2D_IPU_QACTIVE_REQ_STS", BIT(10), 1}, + {"PLT_GREATER_REQ_STS", BIT(11), 1}, + {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0}, + {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0}, + {"PM_SYNC_STATES_REQ_STS", BIT(14), 0}, + {"EA_REQ_STS", BIT(15), 0}, + {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0}, + {"BRK_EV_EN_REQ_STS", BIT(17), 0}, + {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0}, + {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1}, + {"ARC_IDLE_REQ_STS", BIT(21), 0}, + {"PG5_PMA1_REQ_STS", BIT(22), 0}, + {"FIA_DEEP_PM_REQ_STS", BIT(23), 0}, + {"XDCI_ATTACHED_REQ_STS", BIT(24), 1}, + {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0}, + {"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1}, + {"PRE_WAKE0_REQ_STS", BIT(27), 1}, + {"PRE_WAKE1_REQ_STS", BIT(28), 1}, + {"PRE_WAKE2_REQ_STS", BIT(29), 1}, + {"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31), 1}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_signal_status_map[] = { + {"LSX_Wake0_STS", BIT(0), 0}, + {"LSX_Wake1_STS", BIT(1), 0}, + {"LSX_Wake2_STS", BIT(2), 0}, + {"LSX_Wake3_STS", BIT(3), 0}, + {"LSX_Wake4_STS", BIT(4), 0}, + {"LSX_Wake5_STS", BIT(5), 0}, + {"LSX_Wake6_STS", BIT(6), 0}, + {"LSX_Wake7_STS", BIT(7), 0}, + {"LPSS_Wake0_STS", BIT(8), 1}, + {"LPSS_Wake1_STS", BIT(9), 1}, + {"Int_Timer_SS_Wake0_STS", BIT(10), 1}, + {"Int_Timer_SS_Wake1_STS", BIT(11), 1}, + {"Int_Timer_SS_Wake2_STS", BIT(12), 1}, + {"Int_Timer_SS_Wake3_STS", BIT(13), 1}, + {"Int_Timer_SS_Wake4_STS", BIT(14), 1}, + {"Int_Timer_SS_Wake5_STS", BIT(15), 1}, + {} +}; + +static const struct pmc_bit_map ptl_pcdp_rsc_status_map[] = { + {"Memory", 0, 1}, + {"PSF0", 0, 1}, + {"PSF4", 0, 1}, + {"PSF5", 0, 1}, + {"PSF6", 0, 1}, + {"PSF8", 0, 1}, + {"SAF_CFI_LINK", 0, 1}, + {"SB", 0, 1}, + {} +}; + +static const struct pmc_bit_map *ptl_pcdp_lpm_maps[] = { + ptl_pcdp_clocksource_status_map, + ptl_pcdp_power_gating_status_0_map, + ptl_pcdp_power_gating_status_1_map, + ptl_pcdp_power_gating_status_2_map, + ptl_pcdp_d3_status_0_map, + ptl_pcdp_d3_status_1_map, + ptl_pcdp_d3_status_2_map, + ptl_pcdp_d3_status_3_map, + ptl_pcdp_vnn_req_status_0_map, + ptl_pcdp_vnn_req_status_1_map, + ptl_pcdp_vnn_req_status_2_map, + ptl_pcdp_vnn_req_status_3_map, + ptl_pcdp_vnn_misc_status_map, + ptl_pcdp_signal_status_map, + NULL +}; + +static const struct pmc_bit_map *ptl_pcdp_blk_maps[] = { + ptl_pcdp_power_gating_status_0_map, + ptl_pcdp_power_gating_status_1_map, + ptl_pcdp_power_gating_status_2_map, + ptl_pcdp_rsc_status_map, + ptl_pcdp_vnn_req_status_0_map, + ptl_pcdp_vnn_req_status_1_map, + ptl_pcdp_vnn_req_status_2_map, + ptl_pcdp_vnn_req_status_3_map, + ptl_pcdp_d3_status_0_map, + ptl_pcdp_d3_status_1_map, + ptl_pcdp_d3_status_2_map, + ptl_pcdp_d3_status_3_map, + ptl_pcdp_clocksource_status_map, + ptl_pcdp_vnn_misc_status_map, + ptl_pcdp_signal_status_map, + NULL +}; + +static const struct pmc_reg_map ptl_pcdp_reg_map = { + .pfear_sts = ext_ptl_pcdp_pfear_map, + .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, + .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, + .ltr_show_sts = ptl_pcdp_ltr_show_map, + .msr_sts = msr_map, + .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, + .regmap_length = PTL_PCD_PMC_MMIO_REG_LEN, + .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, + .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, + .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, + .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, + .lpm_num_maps = PTL_LPM_NUM_MAPS, + .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, + .etr3_offset = ETR3_OFFSET, + .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, + .lpm_priority_offset = MTL_LPM_PRI_OFFSET, + .lpm_en_offset = MTL_LPM_EN_OFFSET, + .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, + .lpm_sts = ptl_pcdp_lpm_maps, + .lpm_status_offset = MTL_LPM_STATUS_OFFSET, + .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, + .s0ix_blocker_maps = ptl_pcdp_blk_maps, + .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, +}; + +#define PTL_NPU_PCI_DEV 0xb03e +#define PTL_IPU_PCI_DEV 0xb05d + +/* + * Set power state of select devices that do not have drivers to D3 + * so that they do not block Package C entry. + */ +static void ptl_d3_fixup(void) +{ + pmc_core_set_device_d3(PTL_IPU_PCI_DEV); + pmc_core_set_device_d3(PTL_NPU_PCI_DEV); +} + +static int ptl_resume(struct pmc_dev *pmcdev) +{ + ptl_d3_fixup(); + return cnl_resume(pmcdev); +} + +static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) +{ + ptl_d3_fixup(); + return generic_core_init(pmcdev, pmc_dev_info); +} + +struct pmc_dev_info ptl_pmc_dev = { + .map = &ptl_pcdp_reg_map, + .suspend = cnl_suspend, + .resume = ptl_resume, + .init = ptl_core_init, +}; diff --git a/drivers/platform/x86/intel/pmc/spt.c b/drivers/platform/x86/intel/pmc/spt.c index ab993a69e33e..b50534aa2cba 100644 --- a/drivers/platform/x86/intel/pmc/spt.c +++ b/drivers/platform/x86/intel/pmc/spt.c @@ -8,9 +8,11 @@ * */ +#include <linux/pci.h> + #include "core.h" -const struct pmc_bit_map spt_pll_map[] = { +static const struct pmc_bit_map spt_pll_map[] = { {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0}, {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1}, {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2}, @@ -18,7 +20,7 @@ const struct pmc_bit_map spt_pll_map[] = { {} }; -const struct pmc_bit_map spt_mphy_map[] = { +static const struct pmc_bit_map spt_mphy_map[] = { {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0}, {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1}, {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2}, @@ -38,7 +40,7 @@ const struct pmc_bit_map spt_mphy_map[] = { {} }; -const struct pmc_bit_map spt_pfear_map[] = { +static const struct pmc_bit_map spt_pfear_map[] = { {"PMC", SPT_PMC_BIT_PMC}, {"OPI-DMI", SPT_PMC_BIT_OPI}, {"SPI / eSPI", SPT_PMC_BIT_SPI}, @@ -82,7 +84,7 @@ const struct pmc_bit_map spt_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_spt_pfear_map[] = { +static const struct pmc_bit_map *ext_spt_pfear_map[] = { /* * Check intel_pmc_core_ids[] users of spt_reg_map for * a list of core SoCs using this. @@ -91,7 +93,7 @@ const struct pmc_bit_map *ext_spt_pfear_map[] = { NULL }; -const struct pmc_bit_map spt_ltr_show_map[] = { +static const struct pmc_bit_map spt_ltr_show_map[] = { {"SOUTHPORT_A", SPT_PMC_LTR_SPA}, {"SOUTHPORT_B", SPT_PMC_LTR_SPB}, {"SATA", SPT_PMC_LTR_SATA}, @@ -116,7 +118,7 @@ const struct pmc_bit_map spt_ltr_show_map[] = { {} }; -const struct pmc_reg_map spt_reg_map = { +static const struct pmc_reg_map spt_reg_map = { .pfear_sts = ext_spt_pfear_map, .mphy_sts = spt_mphy_map, .pll_sts = spt_pll_map, @@ -134,18 +136,25 @@ const struct pmc_reg_map spt_reg_map = { .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET, }; -int spt_core_init(struct pmc_dev *pmcdev) -{ - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; - int ret; - - pmc->map = &spt_reg_map; - - ret = get_primary_reg_base(pmc); - if (ret) - return ret; +static const struct pci_device_id spt_pmc_pci_id[] = { + { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) }, + { } +}; - pmc_core_get_low_power_modes(pmcdev); +static int spt_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) +{ + /* + * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here + * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap + * in this case. + */ + if (!pci_dev_present(spt_pmc_pci_id)) + return generic_core_init(pmcdev, &cnp_pmc_dev); - return ret; + return generic_core_init(pmcdev, pmc_dev_info); } + +struct pmc_dev_info spt_pmc_dev = { + .map = &spt_reg_map, + .init = spt_core_init, +}; diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.c b/drivers/platform/x86/intel/pmc/ssram_telemetry.c new file mode 100644 index 000000000000..b207247eb5dd --- /dev/null +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel PMC SSRAM TELEMETRY PCI Driver + * + * Copyright (c) 2023, Intel Corporation. + */ + +#include <linux/cleanup.h> +#include <linux/intel_vsec.h> +#include <linux/pci.h> +#include <linux/types.h> +#include <linux/io-64-nonatomic-lo-hi.h> + +#include "core.h" +#include "ssram_telemetry.h" + +#define SSRAM_HDR_SIZE 0x100 +#define SSRAM_PWRM_OFFSET 0x14 +#define SSRAM_DVSEC_OFFSET 0x1C +#define SSRAM_DVSEC_SIZE 0x10 +#define SSRAM_PCH_OFFSET 0x60 +#define SSRAM_IOE_OFFSET 0x68 +#define SSRAM_DEVID_OFFSET 0x70 + +DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_T)) + +static struct pmc_ssram_telemetry *pmc_ssram_telems; +static bool device_probed; + +static int +pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64 ssram_base, void __iomem *ssram) +{ + struct intel_vsec_platform_info info = {}; + struct intel_vsec_header *headers[2] = {}; + struct intel_vsec_header header; + void __iomem *dvsec; + u32 dvsec_offset; + u32 table, hdr; + + dvsec_offset = readl(ssram + SSRAM_DVSEC_OFFSET); + dvsec = ioremap(ssram_base + dvsec_offset, SSRAM_DVSEC_SIZE); + if (!dvsec) + return -ENOMEM; + + hdr = readl(dvsec + PCI_DVSEC_HEADER1); + header.id = readw(dvsec + PCI_DVSEC_HEADER2); + header.rev = PCI_DVSEC_HEADER1_REV(hdr); + header.length = PCI_DVSEC_HEADER1_LEN(hdr); + header.num_entries = readb(dvsec + INTEL_DVSEC_ENTRIES); + header.entry_size = readb(dvsec + INTEL_DVSEC_SIZE); + + table = readl(dvsec + INTEL_DVSEC_TABLE); + header.tbir = INTEL_DVSEC_TABLE_BAR(table); + header.offset = INTEL_DVSEC_TABLE_OFFSET(table); + iounmap(dvsec); + + headers[0] = &header; + info.caps = VSEC_CAP_TELEMETRY; + info.headers = headers; + info.base_addr = ssram_base; + info.parent = &pcidev->dev; + + return intel_vsec_register(pcidev, &info); +} + +static inline u64 get_base(void __iomem *addr, u32 offset) +{ + return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3); +} + +static int +pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, unsigned int pmc_idx, u32 offset) +{ + void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram = NULL; + void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram = NULL; + u64 ssram_base, pwrm_base; + u16 devid; + + ssram_base = pci_resource_start(pcidev, 0); + tmp_ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!tmp_ssram) + return -ENOMEM; + + if (pmc_idx != PMC_IDX_MAIN) { + /* + * The secondary PMC BARS (which are behind hidden PCI devices) + * are read from fixed offsets in MMIO of the primary PMC BAR. + * If a device is not present, the value will be 0. + */ + ssram_base = get_base(tmp_ssram, offset); + if (!ssram_base) + return 0; + + ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!ssram) + return -ENOMEM; + + } else { + ssram = no_free_ptr(tmp_ssram); + } + + pwrm_base = get_base(ssram, SSRAM_PWRM_OFFSET); + devid = readw(ssram + SSRAM_DEVID_OFFSET); + + pmc_ssram_telems[pmc_idx].devid = devid; + pmc_ssram_telems[pmc_idx].base_addr = pwrm_base; + + /* Find and register and PMC telemetry entries */ + return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram); +} + +/** + * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr information + * @pmc_idx: Index of the PMC + * @pmc_ssram_telemetry: pmc_ssram_telemetry structure to store the PMC information + * + * Return: + * * 0 - Success + * * -EAGAIN - Probe function has not finished yet. Try again. + * * -EINVAL - Invalid pmc_idx + * * -ENODEV - PMC device is not available + */ +int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx, + struct pmc_ssram_telemetry *pmc_ssram_telemetry) +{ + /* + * PMCs are discovered in probe function. If this function is called before + * probe function complete, the result would be invalid. Use device_probed + * variable to avoid this case. Return -EAGAIN to inform the consumer to call + * again later. + */ + if (!device_probed) + return -EAGAIN; + + /* + * Memory barrier is used to ensure the correct read order between + * device_probed variable and PMC info. + */ + smp_rmb(); + if (pmc_idx >= MAX_NUM_PMC) + return -EINVAL; + + if (!pmc_ssram_telems || !pmc_ssram_telems[pmc_idx].devid) + return -ENODEV; + + pmc_ssram_telemetry->devid = pmc_ssram_telems[pmc_idx].devid; + pmc_ssram_telemetry->base_addr = pmc_ssram_telems[pmc_idx].base_addr; + return 0; +} +EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info); + +static int intel_pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct pci_device_id *id) +{ + int ret; + + pmc_ssram_telems = devm_kzalloc(&pcidev->dev, sizeof(*pmc_ssram_telems) * MAX_NUM_PMC, + GFP_KERNEL); + if (!pmc_ssram_telems) { + ret = -ENOMEM; + goto probe_finish; + } + + ret = pcim_enable_device(pcidev); + if (ret) { + dev_dbg(&pcidev->dev, "failed to enable PMC SSRAM device\n"); + goto probe_finish; + } + + ret = pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_MAIN, 0); + if (ret) + goto probe_finish; + + pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); + pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); + +probe_finish: + /* + * Memory barrier is used to ensure the correct write order between PMC info + * and device_probed variable. + */ + smp_wmb(); + device_probed = true; + return ret; +} + +static const struct pci_device_id intel_pmc_ssram_telemetry_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) }, + { } +}; +MODULE_DEVICE_TABLE(pci, intel_pmc_ssram_telemetry_pci_ids); + +static struct pci_driver intel_pmc_ssram_telemetry_driver = { + .name = "intel_pmc_ssram_telemetry", + .id_table = intel_pmc_ssram_telemetry_pci_ids, + .probe = intel_pmc_ssram_telemetry_probe, +}; +module_pci_driver(intel_pmc_ssram_telemetry_driver); + +MODULE_IMPORT_NS("INTEL_VSEC"); +MODULE_AUTHOR("Xi Pardee <xi.pardee@intel.com>"); +MODULE_DESCRIPTION("Intel PMC SSRAM Telemetry driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/platform/x86/intel/pmc/ssram_telemetry.h b/drivers/platform/x86/intel/pmc/ssram_telemetry.h new file mode 100644 index 000000000000..daf8aeeb2275 --- /dev/null +++ b/drivers/platform/x86/intel/pmc/ssram_telemetry.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Intel PMC SSRAM Telemetry PCI Driver Header File + * + * Copyright (c) 2024, Intel Corporation. + */ + +#ifndef PMC_SSRAM_H +#define PMC_SSRAM_H + +/** + * struct pmc_ssram_telemetry - Structure to keep pmc info in ssram device + * @devid: device id of the pmc device + * @base_addr: contains PWRM base address + */ +struct pmc_ssram_telemetry { + u16 devid; + u64 base_addr; +}; + +int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx, + struct pmc_ssram_telemetry *pmc_ssram_telemetry); + +#endif /* PMC_SSRAM_H */ diff --git a/drivers/platform/x86/intel/pmc/tgl.c b/drivers/platform/x86/intel/pmc/tgl.c index e0580de18077..02e731ed3391 100644 --- a/drivers/platform/x86/intel/pmc/tgl.c +++ b/drivers/platform/x86/intel/pmc/tgl.c @@ -18,7 +18,7 @@ enum pch_type { PCH_LP }; -const struct pmc_bit_map tgl_pfear_map[] = { +static const struct pmc_bit_map tgl_pfear_map[] = { {"PSF9", BIT(0)}, {"RES_66", BIT(1)}, {"RES_67", BIT(2)}, @@ -29,7 +29,7 @@ const struct pmc_bit_map tgl_pfear_map[] = { {} }; -const struct pmc_bit_map *ext_tgl_pfear_map[] = { +static const struct pmc_bit_map *ext_tgl_pfear_map[] = { /* * Check intel_pmc_core_ids[] users of tgl_reg_map for * a list of core SoCs using this. @@ -39,7 +39,7 @@ const struct pmc_bit_map *ext_tgl_pfear_map[] = { NULL }; -const struct pmc_bit_map tgl_clocksource_status_map[] = { +static const struct pmc_bit_map tgl_clocksource_status_map[] = { {"USB2PLL_OFF_STS", BIT(18)}, {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)}, {"PCIe_Gen3PLL_OFF_STS", BIT(20)}, @@ -55,7 +55,7 @@ const struct pmc_bit_map tgl_clocksource_status_map[] = { {} }; -const struct pmc_bit_map tgl_power_gating_status_map[] = { +static const struct pmc_bit_map tgl_power_gating_status_map[] = { {"CSME_PG_STS", BIT(0)}, {"SATA_PG_STS", BIT(1)}, {"xHCI_PG_STS", BIT(2)}, @@ -83,7 +83,7 @@ const struct pmc_bit_map tgl_power_gating_status_map[] = { {} }; -const struct pmc_bit_map tgl_d3_status_map[] = { +static const struct pmc_bit_map tgl_d3_status_map[] = { {"ADSP_D3_STS", BIT(0)}, {"SATA_D3_STS", BIT(1)}, {"xHCI0_D3_STS", BIT(2)}, @@ -98,7 +98,7 @@ const struct pmc_bit_map tgl_d3_status_map[] = { {} }; -const struct pmc_bit_map tgl_vnn_req_status_map[] = { +static const struct pmc_bit_map tgl_vnn_req_status_map[] = { {"GPIO_COM0_VNN_REQ_STS", BIT(1)}, {"GPIO_COM1_VNN_REQ_STS", BIT(2)}, {"GPIO_COM2_VNN_REQ_STS", BIT(3)}, @@ -123,7 +123,7 @@ const struct pmc_bit_map tgl_vnn_req_status_map[] = { {} }; -const struct pmc_bit_map tgl_vnn_misc_status_map[] = { +static const struct pmc_bit_map tgl_vnn_misc_status_map[] = { {"CPU_C10_REQ_STS_0", BIT(0)}, {"PCIe_LPM_En_REQ_STS_3", BIT(3)}, {"ITH_REQ_STS_5", BIT(5)}, @@ -175,7 +175,7 @@ const struct pmc_bit_map tgl_signal_status_map[] = { {} }; -const struct pmc_bit_map *tgl_lpm_maps[] = { +static const struct pmc_bit_map *tgl_lpm_maps[] = { tgl_clocksource_status_map, tgl_power_gating_status_map, tgl_d3_status_map, @@ -185,7 +185,7 @@ const struct pmc_bit_map *tgl_lpm_maps[] = { NULL }; -const struct pmc_reg_map tgl_reg_map = { +static const struct pmc_reg_map tgl_reg_map = { .pfear_sts = ext_tgl_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, @@ -210,7 +210,7 @@ const struct pmc_reg_map tgl_reg_map = { .etr3_offset = ETR3_OFFSET, }; -const struct pmc_reg_map tgl_h_reg_map = { +static const struct pmc_reg_map tgl_h_reg_map = { .pfear_sts = ext_tgl_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, @@ -285,35 +285,28 @@ free_acpi_obj: ACPI_FREE(out_obj); } -int tgl_l_core_init(struct pmc_dev *pmcdev) +static int tgl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) { - return tgl_core_generic_init(pmcdev, PCH_LP); -} - -int tgl_core_init(struct pmc_dev *pmcdev) -{ - return tgl_core_generic_init(pmcdev, PCH_H); -} - -int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp) -{ - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; int ret; - if (pch_tp == PCH_H) - pmc->map = &tgl_h_reg_map; - else - pmc->map = &tgl_reg_map; - - pmcdev->suspend = cnl_suspend; - pmcdev->resume = cnl_resume; - - ret = get_primary_reg_base(pmc); + ret = generic_core_init(pmcdev, pmc_dev_info); if (ret) return ret; - pmc_core_get_low_power_modes(pmcdev); pmc_core_get_tgl_lpm_reqs(pmcdev->pdev); - return 0; } + +struct pmc_dev_info tgl_l_pmc_dev = { + .map = &tgl_reg_map, + .suspend = cnl_suspend, + .resume = cnl_resume, + .init = tgl_core_init, +}; + +struct pmc_dev_info tgl_pmc_dev = { + .map = &tgl_h_reg_map, + .suspend = cnl_suspend, + .resume = cnl_resume, + .init = tgl_core_init, +}; |