diff options
Diffstat (limited to 'drivers/rtc/rtc-rzn1.c')
| -rw-r--r-- | drivers/rtc/rtc-rzn1.c | 71 |
1 files changed, 60 insertions, 11 deletions
diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c index eeb9612a666f..c4ed43735457 100644 --- a/drivers/rtc/rtc-rzn1.c +++ b/drivers/rtc/rtc-rzn1.c @@ -12,6 +12,7 @@ */ #include <linux/bcd.h> +#include <linux/clk.h> #include <linux/init.h> #include <linux/iopoll.h> #include <linux/module.h> @@ -22,9 +23,9 @@ #include <linux/spinlock.h> #define RZN1_RTC_CTL0 0x00 -#define RZN1_RTC_CTL0_SLSB_SUBU 0 #define RZN1_RTC_CTL0_SLSB_SCMP BIT(4) #define RZN1_RTC_CTL0_AMPM BIT(5) +#define RZN1_RTC_CTL0_CEST BIT(6) #define RZN1_RTC_CTL0_CE BIT(7) #define RZN1_RTC_CTL1 0x04 @@ -49,6 +50,8 @@ #define RZN1_RTC_SUBU_DEV BIT(7) #define RZN1_RTC_SUBU_DECR BIT(6) +#define RZN1_RTC_SCMP 0x3c + #define RZN1_RTC_ALM 0x40 #define RZN1_RTC_ALH 0x44 #define RZN1_RTC_ALW 0x48 @@ -356,7 +359,7 @@ static int rzn1_rtc_set_offset(struct device *dev, long offset) return 0; } -static const struct rtc_class_ops rzn1_rtc_ops = { +static const struct rtc_class_ops rzn1_rtc_ops_subu = { .read_time = rzn1_rtc_read_time, .set_time = rzn1_rtc_set_time, .read_alarm = rzn1_rtc_read_alarm, @@ -366,11 +369,21 @@ static const struct rtc_class_ops rzn1_rtc_ops = { .set_offset = rzn1_rtc_set_offset, }; +static const struct rtc_class_ops rzn1_rtc_ops_scmp = { + .read_time = rzn1_rtc_read_time, + .set_time = rzn1_rtc_set_time, + .read_alarm = rzn1_rtc_read_alarm, + .set_alarm = rzn1_rtc_set_alarm, + .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, +}; + static int rzn1_rtc_probe(struct platform_device *pdev) { struct rzn1_rtc *rtc; - int irq; - int ret; + u32 val, scmp_val = 0; + struct clk *xtal; + unsigned long rate; + int irq, ret; rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); if (!rtc) @@ -393,7 +406,6 @@ static int rzn1_rtc_probe(struct platform_device *pdev) rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000; rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099; rtc->rtcdev->alarm_offset_max = 7 * 86400; - rtc->rtcdev->ops = &rzn1_rtc_ops; ret = devm_pm_runtime_enable(&pdev->dev); if (ret < 0) @@ -402,12 +414,44 @@ static int rzn1_rtc_probe(struct platform_device *pdev) if (ret < 0) return ret; - /* - * Ensure the clock counter is enabled. - * Set 24-hour mode and possible oscillator offset compensation in SUBU mode. - */ - writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU, - rtc->base + RZN1_RTC_CTL0); + /* Only switch to scmp if we have an xtal clock with a valid rate and != 32768 */ + xtal = devm_clk_get_optional(&pdev->dev, "xtal"); + if (IS_ERR(xtal)) { + ret = PTR_ERR(xtal); + goto dis_runtime_pm; + } else if (xtal) { + rate = clk_get_rate(xtal); + + if (rate < 32000 || rate > BIT(22)) { + ret = -EOPNOTSUPP; + goto dis_runtime_pm; + } + + if (rate != 32768) + scmp_val = RZN1_RTC_CTL0_SLSB_SCMP; + } + + /* Disable controller during SUBU/SCMP setup */ + val = readl(rtc->base + RZN1_RTC_CTL0) & ~RZN1_RTC_CTL0_CE; + writel(val, rtc->base + RZN1_RTC_CTL0); + /* Wait 2-4 32k clock cycles for the disabled controller */ + ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL0, val, + !(val & RZN1_RTC_CTL0_CEST), 62, 123); + if (ret) + goto dis_runtime_pm; + + /* Set desired modes leaving the controller disabled */ + writel(RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0); + + if (scmp_val) { + writel(rate - 1, rtc->base + RZN1_RTC_SCMP); + rtc->rtcdev->ops = &rzn1_rtc_ops_scmp; + } else { + rtc->rtcdev->ops = &rzn1_rtc_ops_subu; + } + + /* Enable controller finally */ + writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0); /* Disable all interrupts */ writel(0, rtc->base + RZN1_RTC_CTL1); @@ -444,6 +488,11 @@ dis_runtime_pm: static void rzn1_rtc_remove(struct platform_device *pdev) { + struct rzn1_rtc *rtc = platform_get_drvdata(pdev); + + /* Disable all interrupts */ + writel(0, rtc->base + RZN1_RTC_CTL1); + pm_runtime_put(&pdev->dev); } |