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path: root/drivers/clk/mediatek
AgeCommit message (Expand)Author
2025-10-06Merge branch 'clk-determine-rate' into clk-nextStephen Boyd
2025-09-21clk: mediatek: Add MT8196 vencsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 vdecsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 ovl1 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 ovl0 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 disp-ao clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 disp1 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 disp0 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 mfg clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 mdpsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 mcu clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 I2C clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 pextpsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 ufssys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 peripheral clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 vlpckgen clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 topckgen2 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 topckgen clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 apmixedsys clock supportLaura Nao
2025-09-21clk: mediatek: clk-mtk: Add MUX_DIV_GATE macroLaura Nao
2025-09-21clk: mediatek: clk-gate: Add ops for gates with HW voterLaura Nao
2025-09-21clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate structLaura Nao
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENCLaura Nao
2025-09-21clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()Laura Nao
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENCLaura Nao
2025-09-21clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENCLaura Nao
2025-09-21clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable controlLaura Nao
2025-09-21clk: mediatek: clk-mux: Do not pass flags to clk_mux_determine_rate_flags()Chen-Yu Tsai
2025-09-21clk: mediatek: mt7622-aud: Add missing AFE_MRGIF clockAngeloGioacchino Del Regno
2025-09-21clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26mAngeloGioacchino Del Regno
2025-09-08clk: mediatek: pll: convert from round_rate() to determine_rate()Brian Masney
2025-02-27clk: mediatek: Add SMI LARBs reset for MT8188Friday Yang
2025-02-26clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitxAngeloGioacchino Del Regno
2024-12-17clk: mediatek: mt2701-img: add missing dummy clkDaniel Golle
2024-12-17clk: mediatek: mt2701-mm: add missing dummy clkDaniel Golle
2024-12-17clk: mediatek: mt2701-bdp: add missing dummy clkDaniel Golle
2024-12-17clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probeDaniel Golle
2024-12-17clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probeDaniel Golle
2024-11-14clk: mediatek: Add drivers for MT6735 syscon clock and reset controllersYassine Oudjana
2024-11-14clk: mediatek: mt6735-apmixedsys: Fix an error handling path in clk_mt6735_ap...Christophe JAILLET
2024-10-17clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmpPablo Sun
2024-10-17clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset driversYassine Oudjana
2024-10-09clk: mediatek: drop two dead config optionsLukas Bulwahn
2024-09-21clk: Switch back to struct platform_driver::remove()Uwe Kleine-König
2024-07-29clk: mediatek: reset: Remove unused mtk_register_reset_controller()AngeloGioacchino Del Regno
2024-07-29clk: mediatek: reset: Return regmap's error codeFei Shao
2024-07-19Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2024-07-08clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when moduleAlper Nebi Yasak
2024-07-01clk: mediatek: mt8183: Only enable runtime PM on mt8183-mfgcfgPin-yen Lin
2024-06-03clk: mediatek: Add a module description where missingAngeloGioacchino Del Regno
generated by cgit (git 2.34.1) at 2025-12-29 02:42:06 +0000