summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
2025-05-08clk: renesas: r9a09g047: Add XSPI clock/resetBiju Das
2025-05-08clk: renesas: r9a09g047: Add support for xspi mux and dividerBiju Das
2025-05-05clk: renesas: Use str_on_off() helperGeert Uytterhoeven
2025-04-22clk: renesas: r9a09g057: Add clock and reset entries for USB2Lad Prabhakar
2025-04-22clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validationLad Prabhakar
2025-04-22clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()Lad Prabhakar
2025-04-22clk: renesas: rzv2h: Support static dividers without RMWBiju Das
2025-04-22clk: renesas: rzv2h: Add macro for defining static dividersLad Prabhakar
2025-04-22clk: renesas: rzv2h: Add support for static mux clocksLad Prabhakar
2025-04-22clk: renesas: r9a09g047: Add clock and reset entries for GE3DTommaso Merciai
2025-04-22clk: renesas: rzv2h: Fix a typoBiju Das
2025-04-14clk: renesas: rzv2h: Add support for RZ/V2N SoCLad Prabhakar
2025-04-14clk: renesas: rzv2h: Sort compatible list based on SoC part numberLad Prabhakar
2025-04-14clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()Tommaso Merciai
2025-04-14clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()Tommaso Merciai
2025-04-08clk: renesas: r9a09g057: Add clock and reset entries for GE3DLad Prabhakar
2025-04-08clk: renesas: rzv2h: Rename PLL field macros for consistencyLad Prabhakar
2025-04-08clk: renesas: rzv2h: Add support for enabling PLLsLad Prabhakar
2025-04-08clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`Lad Prabhakar
2025-04-08clk: renesas: rzv2h: Refactor PLL configuration handlingLad Prabhakar
2025-03-06clk: renesas: r9a09g047: Add clock and reset signals for the TSU IPJohn Madieu
2025-03-06clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1Biju Das
2025-03-04clk: renesas: r7s9210: Distinguish clocks by clock typeGeert Uytterhoeven
2025-03-04clk: renesas: rzg2l: Remove unneeded nullify checksGeert Uytterhoeven
2025-03-04clk: renesas: cpg-mssr: Remove obsolete nullify checkGeert Uytterhoeven
2025-03-04clk: renesas: r9a09g057: Add entries for the DMACsFabrizio Castro
2025-02-20clk: renesas: r9a09g047: Add CANFD clocks and resetsBiju Das
2025-02-20clk: renesas: r9a09g047: Add CRU0 clocks and resetsTommaso Merciai
2025-02-18clk: renesas: rzv2h: Update error messageLad Prabhakar
2025-02-18clk: renesas: rzg2l: Update error messageLad Prabhakar
2025-02-03clk: renesas: r9a09g047: Add ICU clock/resetBiju Das
2025-02-03clk: renesas: r9a07g043: Fix HP clock source for RZ/FiveLad Prabhakar
2025-02-03clk: renesas: r9a09g047: Add SDHI clocks/resetsBiju Das
2025-02-03clk: renesas: r8a779h0: Add VSPX clockNiklas Söderlund
2025-02-03clk: renesas: r8a779h0: Add FCPVX clockNiklas Söderlund
2025-02-03clk: renesas: r8a08g045: Check the source of the CPU PLL settingsClaudiu Beznea
2025-02-03clk: renesas: r9a09g047: Add WDT clocks and resetsBiju Das
2025-02-03clk: renesas: r8a779h0: Add ISP core clocksNiklas Söderlund
2025-02-03clk: renesas: r8a779g0: Add ISP core clocksNiklas Söderlund
2025-02-03clk: renesas: r8a779a0: Add ISP core clocksNiklas Söderlund
2025-02-03clk: renesas: r8a779a0: Add FCPVX clocksNiklas Söderlund
2025-02-03clk: renesas: r9a07g044: Add clock and reset entry for DRP-AILad Prabhakar
2025-02-03clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ...Claudiu Beznea
2025-02-03clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validationLad Prabhakar
2025-01-07clk: renesas: r9a09g057: Add clock and reset entries for GICLad Prabhakar
2025-01-07clk: renesas: r9a09g057: Add reset entry for SYSLad Prabhakar
2025-01-07clk: renesas: r8a779g0: Add VSPX clocksJacopo Mondi
2025-01-07clk: renesas: r8a779g0: Add FCPVX clocksJacopo Mondi
2025-01-07clk: renesas: r9a09g047: Add I2C clocks/resetsBiju Das
2025-01-07clk: renesas: r9a09g047: Add CA55 core clocksBiju Das
generated by cgit (git 2.34.1) at 2025-07-16 06:35:11 +0000