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2025-06-18Merge tag 'drm-msm-fixes-2025-06-16' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/msm into drm-fixes Fixes for v6.16-rc3 Display: - Fixed DP output on SDM845 - Fixed 10nm DSI PLL init GPU: - SUBMIT ioctl error path leak fixes - drm half of stall-on-fault fixes. Note there is a soft dependency, to get correct mmu fault devcoredumps, on arm-smmu changes which are not in this branch, but have already been merged by Linus. So by the time Linus merges this, everything should be peachy. - a7xx: Missing CP_RESET_CONTEXT_STATE - Skip GPU component bind if GPU is not in the device table. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://lore.kernel.org/r/CACSVV03=OH74ip8O1xqb8RJWGyM4HFuUnWuR=p3zJR+-ko_AJA@mail.gmail.com
2025-06-09drm/msm/disp: Correct porch timing for SDM845James A. MacInnes
Type-C DisplayPort inoperable due to incorrect porch settings. - Re-used wide_bus_en as flag to prevent porch shifting Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") Signed-off-by: James A. MacInnes <james.a.macinnes@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/636945/ Link: https://lore.kernel.org/r/20250212-sdm845_dp-v2-2-4954e51458f4@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-06-08treewide, timers: Rename from_timer() to timer_container_of()Ingo Molnar
Move this API to the canonical timer_*() namespace. [ tglx: Redone against pre rc1 ] Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/aB2X0jCKQO56WdMt@gmail.com
2025-05-12drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from SAR2130P CTL blocksDmitry Baryshkov
Follow the changes in the commit a2649952f66e ("drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0") and remove DPU_CTL_SPLIT_DISPLAY from the CTL blocks on the SAR2130P platform. Single CTL is used for all interfaces used by a single path Fixes: 178575173472 ("drm/msm/dpu: add catalog entry for SAR2130P") Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/651883/ Link: https://lore.kernel.org/r/20250506-dpu-sar2130p-no-split-display-v1-1-b619c0fddea5@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush maskKrzysztof Kozlowski
MDSS/MDP v12 comes with new bits in flush registers (e.g. MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651260/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-13-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Add LM_7, DSC_[67], PP_[67] and MERGE_3D_5Krzysztof Kozlowski
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and MERGE_3D blocks. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651262/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-12-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Drop useless commentsKrzysztof Kozlowski
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given SoC because it's duplicating the actual name of structure. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651251/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-11-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE before blend setupKrzysztof Kozlowski
Before blend setup, all existing blend stages are cleared, so shall be active fetch pipes. Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch active in ctl path") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651263/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-10-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on ctl_path resetKrzysztof Kozlowski
Resetting entire CTL path should also include resetting active fetch pipes. Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_ctl") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651252/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-9-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on mixer resetKrzysztof Kozlowski
Resetting mixers should also include resetting active fetch pipes. Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw blocks") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651246/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-8-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Add missing "fetch" name to set_active_pipes()Krzysztof Kozlowski
The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to set_active_fetch_pipes() to better match the purpose. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651261/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-7-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: remove DSC feature bit for PINGPONG on SDM630Dmitry Baryshkov
The SDM630 platform doesn't have DSC blocks nor does have it DSC registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit from the PINGPONG's feature mask, replacing PINGPONG_SDM845_MASK with BIT(DPU_PINGPONG_DITHER). Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms") Reported-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640308/ Link: https://lore.kernel.org/r/20250301-dpu-fix-catalog-v2-5-498271be8b50@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: drop TE2 definitionsDmitry Baryshkov
Neither DPU driver nor vendor SDE driver do not use TE2 definitions (and, in case of SDE driver, never did). Semantics of the TE2 feature bit and .te2 sblk are not completely clear. Drop these bits from the catalog with the possibility of reintroducing them later if we need to support ppsplit. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640305/ Link: https://lore.kernel.org/r/20250301-dpu-fix-catalog-v2-4-498271be8b50@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: remove DSC feature bit for PINGPONG on MSM8953Dmitry Baryshkov
The MSM8953 platform doesn't have DSC blocks nor does have it DSC registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit from the PINGPONG's feature mask and, as it is the only remaining bit, drop the .features assignment completely. Fixes: 7a6109ce1c2c ("drm/msm/dpu: Add support for MSM8953") Reported-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640303/ Link: https://lore.kernel.org/r/20250301-dpu-fix-catalog-v2-3-498271be8b50@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: remove DSC feature bit for PINGPONG on MSM8917Dmitry Baryshkov
The MSM8917 platform doesn't have DSC blocks nor does have it DSC registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit from the PINGPONG's feature mask and, as it is the only remaining bit, drop the .features assignment completely. Fixes: 62af6e1cb596 ("drm/msm/dpu: Add support for MSM8917") Reported-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640301/ Link: https://lore.kernel.org/r/20250301-dpu-fix-catalog-v2-2-498271be8b50@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: remove DSC feature bit for PINGPONG on MSM8937Dmitry Baryshkov
The MSM8937 platform doesn't have DSC blocks nor does have it DSC registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit from the PINGPONG's feature mask and, as it is the only remaining bit, drop the .features assignment completely. Fixes: c079680bb0fa ("drm/msm/dpu: Add support for MSM8937") Reported-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640299/ Link: https://lore.kernel.org/r/20250301-dpu-fix-catalog-v2-1-498271be8b50@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: add catalog entry for SAR2130PDmitry Baryshkov
Add DPU driver support for the Qualcomm SAR2130P platform. It is mostly the same as SM8550, minor differences in the CDP configuration. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/649258/ Link: https://lore.kernel.org/r/20250418-sar2130p-display-v5-8-442c905cb3a4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: rename non-SmartDMA feature masks to be more explicitDmitry Baryshkov
It is easy to skip or ignore the fact that the default SSPP feature masks for SDM845+ don't include the SmartDMA bit (both during development and during the review stage). Rename SSPP feature masks to make it more explicit that using non-SmartDMA masks should not be an exception rather than the rule. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/650425/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-5-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SM8550Dmitry Baryshkov
In order to support more versatile configuration of the display pipes on SM8550, enable SmartDMA for this platform. Patchwork: https://patchwork.freedesktop.org/patch/650424/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-4-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SC8280XPDmitry Baryshkov
In order to support more versatile configuration of the display pipes on SC8280XP, enable SmartDMA for this platform. Patchwork: https://patchwork.freedesktop.org/patch/650420/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-3-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SC8180XDmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SC8180X platform. Renable SmartDMA support on this SoC. Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/650421/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-2-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SM8150Dmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SM8150 platform. Renable SmartDMA support on this SoC. Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/650418/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-1-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: allow sharing SSPP between planesDmitry Baryshkov
Since SmartDMA planes provide two rectangles, it is possible to use them to drive two different DRM planes, first plane getting the rect_0, another one using rect_1 of the same SSPP. The sharing algorithm is pretty simple, it requires that each of the planes can be driven by the single rectangle and only consecutive planes are considered. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650441/ Link: https://lore.kernel.org/r/20250426-dpu-share-sspp-v7-1-6f4c719e373c@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: switch LVDS to use drm_bridge/_connectorDmitry Baryshkov
LVDS support in MDP4 driver makes use of drm_connector directly. However LCDC encoder and LVDS connector are wrappers around drm_panel. Switch them to use drm_panel_bridge/drm_bridge_connector. This allows using standard interface for the drm_panel and also inserting additional bridges between encoder and panel. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650290/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-6-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: move move_valid callback to lcdc_encoderDmitry Baryshkov
We can check the LCDC clock directly from the LCDC encoder driver, so remove it from the LVDS connector. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650285/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-5-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: use parent_data for LVDS PLLDmitry Baryshkov
Instead of using .parent_names, use .parent_data, which binds parent clocks by using relative names specified in DT in addition to using global system clock names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/650284/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-4-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: register the LVDS PLL as a clock providerDmitry Baryshkov
The LVDS/LCDC controller uses pixel clock coming from the multimedia controller (mmcc) rather than using the PLL directly. Stop using LVDS PLL directly and register it as a clock provider. Use lcdc_clk as a pixel clock for the LCDC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650280/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-3-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: drop mpd4_lvds_pll_init stubDmitry Baryshkov
Drop the !COMMON_CLK stub for mpd4_lvds_pll_init(), the DRM_MSM driver depends on COMMON_CLK. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650281/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-2-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: drop now-unused condition for has_legacy_ctlsDmitry Baryshkov
Now as we have dropped the DPU_CTL_SPLIT_DISPLAY from DPU >= 5.0 configuration, drop the rm->has_legacy_ctl condition which short-cutted the check for those platforms. Suggested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641586/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-8-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0Dmitry Baryshkov
Since DPU 5.0 CTL blocks do not require DPU_CTL_SPLIT_DISPLAY, as single CTL is used for both interfaces. As both RM and encoder now handle active CTLs, drop that feature bit. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641592/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-7-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: allocate single CTL for DPU >= 5.0Dmitry Baryshkov
Unlike previous generation, since DPU 5.0 it is possible to use just one CTL to handle all INTF and WB blocks for a single output. And one has to use single CTL to support bonded DSI config. Allocate single CTL for these DPU versions. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641587/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-6-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: don't select single flush for active CTL blocksDmitry Baryshkov
In case of ACTIVE CTLs, a single CTL is being used for flushing all INTF blocks. Don't skip programming the CTL on those targets. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641585/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-5-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: use single CTL if it is the only CTL returned by RMDmitry Baryshkov
On DPU >= 5.0 CTL blocks were reworked in order to support using a single CTL for all outputs. In preparation of reworking the RM code to return single CTL make sure that dpu_encoder can cope with that. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/641582/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-4-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: pass master interface to CTL configurationDmitry Baryshkov
Active controls require setup of the master interface. Pass the selected interface to CTL configuration. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641583/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-3-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: program master INTF valueDmitry Baryshkov
If several interfaces are being handled through a single CTL, a main ('master') INTF needs to be programmed into a separate register. Write corresponding value into that register. Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/641581/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-2-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE registerDmitry Baryshkov
In case of complex pipelines (e.g. the forthcoming quad-pipe) the DPU might use more that one MERGE_3D block for a single output. Follow the pattern and extend the CTL_MERGE_3D_ACTIVE active register instead of simply writing new value there. Currently at most one MERGE_3D block is being used, so this has no impact on existing targets. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/641580/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-1-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-04-29Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-nextRob Clark
Merge drm-misc-next to get commit Fixes: fec450ca15af ("drm/display: hdmi: provide central data authority for ACR params"). Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-04-10drm/msm/dpu: drop rogue intr_tear_rd_ptr valuesDmitry Baryshkov
The commit 5a9d50150c2c ("drm/msm/dpu: shift IRQ indices by 1") shifted IRQ indices by 1, making 'NO_IRQ' to be 0 rather than -1 (and allowing to skip the definition if the IRQ is not present). Several platform files were sketched before that commit, but got applied afterwards. As such, they inherited historical (and currently incorrect) setting of .intr_tear_rd_ptr = -1 for 'NO_IRQ' value. Drop that setting for all the affected platforms. Fixes: 62af6e1cb596 ("drm/msm/dpu: Add support for MSM8917") Fixes: c079680bb0fa ("drm/msm/dpu: Add support for MSM8937") Fixes: 7a6109ce1c2c ("drm/msm/dpu: Add support for MSM8953") Fixes: daf9a92daeb8 ("drm/msm/dpu: Add support for MSM8996") Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/647486/ Link: https://lore.kernel.org/r/20250408-dpu-drop-intr-rd-ptr-v1-1-eeac337d88f8@oss.qualcomm.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2025-04-10drm/msm/dpu: reorder pointer operations after sanity checks to avoid NULL derefQasim Ijaz
_dpu_encoder_trigger_start dereferences "struct dpu_encoder_phys *phys" before the sanity checks which can lead to a NULL pointer dereference if phys is NULL. Fix this by reordering the dereference after the sanity checks. Fixes: 8144d17a81d9 ("drm/msm/dpu: Skip trigger flush and start for CWB") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Qasim Ijaz <qasdev00@gmail.com> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/647536/ Link: https://lore.kernel.org/r/20250408172223.10827-1-qasdev00@gmail.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2025-04-10drm/msm/dpu: Fix error pointers in dpu_plane_virtual_atomic_checkChenyuan Yang
The function dpu_plane_virtual_atomic_check was dereferencing pointers returned by drm_atomic_get_plane_state without checking for errors. This could lead to undefined behavior if the function returns an error pointer. This commit adds checks using IS_ERR to ensure that plane_state is valid before dereferencing them. Similar to commit da29abe71e16 ("drm/amd/display: Fix error pointers in amdgpu_dm_crtc_mem_type_changed"). Fixes: 774bcfb73176 ("drm/msm/dpu: add support for virtual planes") Signed-off-by: Chenyuan Yang <chenyuan0y@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/643132/ Link: https://lore.kernel.org/r/20250314011004.663804-1-chenyuan0y@gmail.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2025-04-10drm/msm/dpu: check every pipe per capabilityJun Nie
The capability stored in sblk and pipe_hw_caps is checked only for SSPP of the first pipe in the pair with current implementation. That of the 2nd pipe, r_pipe, is not checked and may violate hardware capability. Move requirement check to dpu_plane_atomic_check_pipe() for the check of every pipe. Fixes: ("dbbf57dfd04e6 drm/msm/dpu: split dpu_plane_atomic_check()") Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640513/ Link: https://lore.kernel.org/r/20250303-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v8-1-eb5df105c807@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2025-04-05treewide: Switch/rename to timer_delete[_sync]()Thomas Gleixner
timer_delete[_sync]() replaces del_timer[_sync](). Convert the whole tree over and remove the historical wrapper inlines. Conversion was done with coccinelle plus manual fixups where necessary. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-03-08drm/msm/dpu: drop wb2_formats_rgbDmitry Baryshkov
After enabling YUV support for writeback on a variety of DPU hardware, the wb2_formats_rgb is now unused. Drop it following the report of LKP. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202503071857.oZbQsPaE-lkp@intel.com/ Reviewed-by: Rob Clark <robdclark@gmail.com> # on IRC Patchwork: https://patchwork.freedesktop.org/patch/641848/ Link: https://lore.kernel.org/r/20250308-dpu-drop-wb2-rgb-v1-1-f5503fcd1bc2@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-08drm/msm/dpu: Fix uninitialized variable in dpu_crtc_kickoff_clone_mode()Dan Carpenter
After the loop there is a check for whether "wb_encoder" has been set to non-NULL, however it was never set to NULL. Initialize it to NULL. Fixes: ad06972d5365 ("drm/msm/dpu: Reorder encoder kickoff for CWB") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641631/ Link: https://lore.kernel.org/r/f8ba03dc-0f90-4781-8d54-c16b3251ecb1@stanley.mountain Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-08drm/msm/dpu: correct struct dpu_encoder_virt docsDmitry Baryshkov
Fix a typo in struct dpu_encoder_virt kerneldoc, which made it ignore description of the cwb_mask field. Fixes: dd331404ac7c ("drm/msm/dpu: Configure CWB in writeback encoder") Signed-off-by: Dmitry Baryshkov <lumag@kernel.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/641315/ Link: https://lore.kernel.org/r/20250306-dpu-fix-docs-v1-2-e51b71e8ad84@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-08drm/msm/dpu: correct dpu_crtc_check_mode_changed docsDmitry Baryshkov
Correct commit 20972609d12c ("drm/msm/dpu: Require modeset if clone mode status changes") and describe old_crtc_state and new_crtc_state params instead of the single previously used parameter crtc_state. Fixes: 20972609d12c ("drm/msm/dpu: Require modeset if clone mode status changes") Signed-off-by: Dmitry Baryshkov <lumag@kernel.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/641313/ Link: https://lore.kernel.org/r/20250306-dpu-fix-docs-v1-1-e51b71e8ad84@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-07drm/msm/dpu: Remove duplicate dpu_hw_cwb.h headerJiapeng Chong
./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c: dpu_hw_cwb.h is included more than once. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=19239 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: dd331404ac7c ("drm/msm/dpu: Configure CWB in writeback encoder") Patchwork: https://patchwork.freedesktop.org/patch/641543/ Link: https://lore.kernel.org/r/20250307015030.86282-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-07drm/msm/dpu: Adjust CDM_MUX to support CWB PINGPONGJessica Zhang
Similar to WB_MUX, CDM_MUX also needs to be adjusted to support dedicated CWB PINGPONGs Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641272/ Link: https://lore.kernel.org/r/20250305-cdm-cwb-mux-fix-v1-1-16148ca6e4d2@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-06drm/msm/dpu: Support YUV formats on writeback for DPU 5.x+Jessica Zhang
Now that CDM_0 has been enabled for DPU 5.x+, add support for YUV formats on writeback Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641270/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-03-06drm/msm/dpu: Clear perf params before calculating bwJessica Zhang
To prevent incorrect BW calculation, zero out dpu_core_perf_params before it is passed into dpu_core_perf_aggregate(). Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Fixes: 795aef6f3653 ("drm/msm/dpu: remove duplicate code calculating sum of bandwidths") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641278/ Signed-off-by: Rob Clark <robdclark@chromium.org>
generated by cgit (git 2.34.1) at 2025-07-15 21:25:26 +0000