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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andes machine-level timer
description:
The Andes machine-level timer device (PLMT0) provides machine-level timer
functionality for a set of HARTs on a RISC-V platform. It has a single
fixed-frequency monotonic time counter (MTIME) register and a time compare
register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
generated if MTIME >= MTIMECMP.
maintainers:
- Ben Zong-You Xie <ben717@andestech.com>
properties:
compatible:
items:
- enum:
- andestech,qilai-plmt
- const: andestech,plmt0
reg:
maxItems: 1
interrupts-extended:
minItems: 1
maxItems: 32
description:
Specifies which harts are connected to the PLMT0. Each item must points
to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
PLMT0 supports 1 hart up to 32 harts.
additionalProperties: false
required:
- compatible
- reg
- interrupts-extended
examples:
- |
interrupt-controller@100000 {
compatible = "andestech,qilai-plmt", "andestech,plmt0";
reg = <0x100000 0x100000>;
interrupts-extended = <&cpu0intc 7>,
<&cpu1intc 7>,
<&cpu2intc 7>,
<&cpu3intc 7>;
};
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