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|
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
npu-binary@84000000 {
no-map;
reg = <0x0 0x84000000 0x0 0xa00000>;
};
npu-flag@84b0000 {
no-map;
reg = <0x0 0x84b00000 0x0 0x100000>;
};
npu-pkt@85000000 {
no-map;
reg = <0x0 0x85000000 0x0 0x1a00000>;
};
npu-phyaddr@86b00000 {
no-map;
reg = <0x0 0x86b00000 0x0 0x100000>;
};
npu-rxdesc@86d00000 {
no-map;
reg = <0x0 0x86d00000 0x0 0x100000>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-level = <2>;
cache-unified;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
clk20m: clock-20000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@9000000 {
compatible = "arm,gic-v3";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x09000000 0x0 0x20000>,
<0x0 0x09080000 0x0 0x80000>,
<0x0 0x09400000 0x0 0x2000>,
<0x0 0x09500000 0x0 0x2000>,
<0x0 0x09600000 0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
spi@1fa10000 {
compatible = "airoha,en7581-snand";
reg = <0x0 0x1fa10000 0x0 0x140>,
<0x0 0x1fa11000 0x0 0x160>;
clocks = <&scuclk EN7523_CLK_SPI>;
clock-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
spi_nand: nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <2>;
};
};
scuclk: clock-controller@1fb00000 {
compatible = "airoha,en7581-scu";
reg = <0x0 0x1fb00000 0x0 0x970>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pbus_csr: syscon@1fbe3400 {
compatible = "airoha,en7581-pbus-csr", "syscon";
reg = <0x0 0x1fbe3400 0x0 0xff>;
};
pciephy: phy@1fa5a000 {
compatible = "airoha,en7581-pcie-phy";
reg = <0x0 0x1fa5a000 0x0 0xfff>,
<0x0 0x1fa5b000 0x0 0xfff>,
<0x0 0x1fa5c000 0x0 0xfff>,
<0x0 0x1fc10044 0x0 0x4>,
<0x0 0x1fc30044 0x0 0x4>,
<0x0 0x1fc15030 0x0 0x104>;
reg-names = "csr-2l", "pma0", "pma1",
"p0-xr-dtime", "p1-xr-dtime",
"rx-aeq";
#phy-cells = <0>;
};
pcie0: pcie@1fc00000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fc00000 0x0 0x1670>;
reg-names = "pcie-mac";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys-ck";
phys = <&pciephy>;
phy-names = "pcie-phy";
ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>;
resets = <&scuclk EN7581_PCIE0_RST>,
<&scuclk EN7581_PCIE1_RST>,
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
status = "disabled";
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1fc20000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fc20000 0x0 0x1670>;
reg-names = "pcie-mac";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys-ck";
phys = <&pciephy>;
phy-names = "pcie-phy";
ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
resets = <&scuclk EN7581_PCIE0_RST>,
<&scuclk EN7581_PCIE1_RST>,
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
status = "disabled";
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
uart1: serial@1fbf0000 {
compatible = "ns16550";
reg = <0x0 0x1fbf0000 0x0 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <1843200>;
};
rng@1faa1000 {
compatible = "airoha,en7581-trng";
reg = <0x0 0x1faa1000 0x0 0xc04>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
};
system-controller@1fbf0200 {
compatible = "airoha,en7581-gpio-sysctl", "syscon",
"simple-mfd";
reg = <0x0 0x1fbf0200 0x0 0xc0>;
en7581_pinctrl: pinctrl {
compatible = "airoha,en7581-pinctrl";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
i2c0: i2c@1fbf8000 {
compatible = "mediatek,mt7621-i2c";
reg = <0x0 0x1fbf8000 0x0 0x100>;
resets = <&scuclk EN7581_I2C2_RST>;
clocks = <&clk20m>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@1fbf8100 {
compatible = "mediatek,mt7621-i2c";
reg = <0x0 0x1fbf8100 0x0 0x100>;
resets = <&scuclk EN7581_I2C_MASTER_RST>;
clocks = <&clk20m>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
|
