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path: root/scripts/objdiff
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#!/bin/bash
# SPDX-License-Identifier: GPL-2.0-only

# objdiff - a small script for validating that a commit or series of commits
# didn't change object code.
#
# Copyright 2014, Jason Cooper <jason@lakedaemon.net>
#

# usage example:
#
# $ git checkout COMMIT_A
# $ <your fancy build command here>
# $ ./scripts/objdiff record path/to/*.o
#
# $ git checkout COMMIT_B
# $ <your fancy build command here>
# $ ./scripts/objdiff record path/to/*.o
#
# $ ./scripts/objdiff diff COMMIT_A COMMIT_B
# $

# And to clean up (everything is in .tmp_objdiff/*)
# $ ./scripts/objdiff clean all
#
# Note: 'make mrproper' will also remove .tmp_objdiff

SRCTREE=$(cd $(git rev-parse --show-toplevel 2>/dev/null); pwd)

if [ -z "$SRCTREE" ]; then
	echo >&2 "ERROR: Not a git repository."
	exit 1
fi

TMPD=$SRCTREE/.tmp_objdiff

usage() {
	echo >&2 "Usage: $0 <command> <args>"
	echo >&2 "  record    <list of object files or directories>"
	echo >&2 "  diff      <commitA> <commitB>"
	echo >&2 "  clean     all | <commit>"
	exit 1
}

get_output_dir() {
	dir=${1%/*}

	if [ "$dir" = "$1" ]; then
		dir=.
	fi

	dir=$(cd $dir; pwd)

	echo $TMPD/$CMT${dir#$SRCTREE}
}

do_objdump() {
	dir=$(get_output_dir $1)
	base=${1##*/}
	stripped=$dir/${base%.o}.stripped
	dis=$dir/${base%.o}.dis

	[ ! -d "$dir" ] && mkdir -p $dir

	# remove addresses for a cleaner diff
	# http://dummdida.tumblr.com/post/60924060451/binary-diff-between-libc-from-scientificlinux-and
	$STRIP -g $1 -R __bug_table -R .note -R .comment -o $stripped
	$OBJDUMP -D $stripped | sed -e "s/^[[:space:]]\+[0-9a-f]\+//" -e "s:^$stripped:$1:" > $dis
}

dorecord() {
	[ $# -eq 0 ] && usage

	FILES="$*"

	CMT="`git rev-parse --short HEAD`"

	STRIP="${CROSS_COMPILE}strip"
	OBJDUMP="${CROSS_COMPILE}objdump"

	for d in $FILES; do
		if [ -d "$d" ]; then
			for f in $(find $d -name '*.o')
			do
				do_objdump $f
			done
		else
			do_objdump $d
		fi
	done
}

dodiff() {
	[ $# -ne 2 ] && [ $# -ne 0 ] && usage

	if [ $# -eq 0 ]; then
		SRC="`git rev-parse --short HEAD^`"
		DST="`git rev-parse --short HEAD`"
	else
		SRC="`git rev-parse --short $1`"
		DST="`git rev-parse --short $2`"
	fi

	DIFF="`which colordiff`"

	if [ ${#DIFF} -eq 0 ] || [ ! -x "$DIFF" ]; then
		DIFF="`which diff`"
	fi

	SRCD="$TMPD/$SRC"
	DSTD="$TMPD/$DST"

	if [ ! -d "$SRCD" ]; then
		echo >&2 "ERROR: $SRCD doesn't exist"
		exit 1
	fi

	if [ ! -d "$DSTD" ]; then
		echo >&2 "ERROR: $DSTD doesn't exist"
		exit 1
	fi

	$DIFF -Nurd $SRCD $DSTD
}

doclean() {
	[ $# -eq 0 ] && usage
	[ $# -gt 1 ] && usage

	if [ "x$1" = "xall" ]; then
		rm -rf $TMPD/*
	else
		CMT="`git rev-parse --short $1`"

		if [ -d "$TMPD/$CMT" ]; then
			rm -rf $TMPD/$CMT
		else
			echo >&2 "$CMT not found"
		fi
	fi
}

[ $# -eq 0 ] &&	usage

case "$1" in
	record)
		shift
		dorecord $*
		;;
	diff)
		shift
		dodiff $*
		;;
	clean)
		shift
		doclean $*
		;;
	*)
		echo >&2 "Unrecognized command '$1'"
		exit 1
		;;
esac
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-rw-r--r--arch/xtensa/include/asm/thread_info.h11
-rw-r--r--arch/xtensa/include/asm/timex.h6
-rw-r--r--arch/xtensa/include/asm/traps.h40
-rw-r--r--arch/xtensa/include/uapi/asm/mman.h2
-rw-r--r--arch/xtensa/include/uapi/asm/ptrace.h4
-rw-r--r--arch/xtensa/kernel/Makefile5
-rw-r--r--arch/xtensa/kernel/asm-offsets.c19
-rw-r--r--arch/xtensa/kernel/coprocessor.S234
-rw-r--r--arch/xtensa/kernel/entry.S335
-rw-r--r--arch/xtensa/kernel/hibernate.c25
-rw-r--r--arch/xtensa/kernel/irq.c7
-rw-r--r--arch/xtensa/kernel/jump_label.c2
-rw-r--r--arch/xtensa/kernel/process.c130
-rw-r--r--arch/xtensa/kernel/ptrace.c7
-rw-r--r--arch/xtensa/kernel/s32c1i_selftest.c7
-rw-r--r--arch/xtensa/kernel/signal.c7
-rw-r--r--arch/xtensa/kernel/smp.c13
-rw-r--r--arch/xtensa/kernel/syscall.c18
-rw-r--r--arch/xtensa/kernel/time.c1
-rw-r--r--arch/xtensa/kernel/traps.c161
-rw-r--r--arch/xtensa/kernel/vmlinux.lds.S1
-rw-r--r--arch/xtensa/kernel/xtensa_ksyms.c2
-rw-r--r--arch/xtensa/lib/Makefile4
-rw-r--r--arch/xtensa/lib/kcsan-stubs.c54
-rw-r--r--arch/xtensa/lib/memcopy.S20
-rw-r--r--arch/xtensa/lib/umulsidi3.S230
-rw-r--r--arch/xtensa/mm/Makefile3
-rw-r--r--arch/xtensa/mm/fault.c120
-rw-r--r--arch/xtensa/mm/init.c22
-rw-r--r--arch/xtensa/mm/mmu.c2
-rw-r--r--arch/xtensa/platforms/iss/console.c8
-rw-r--r--arch/xtensa/platforms/iss/network.c213
-rw-r--r--arch/xtensa/platforms/iss/simdisk.c22
-rw-r--r--arch/xtensa/platforms/xt2000/setup.c2
-rw-r--r--arch/xtensa/platforms/xtfpga/setup.c1
7835 files changed, 438177 insertions, 251332 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index 29b0167c088b..205fd23e0cad 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -24,17 +24,25 @@ config KEXEC_ELF
config HAVE_IMA_KEXEC
bool
+config ARCH_HAS_SUBPAGE_FAULTS
+ bool
+ help
+ Select if the architecture can check permissions at sub-page
+ granularity (e.g. arm64 MTE). The probe_user_*() functions
+ must be implemented.
+
config HOTPLUG_SMT
bool
config GENERIC_ENTRY
- bool
+ bool
config KPROBES
bool "Kprobes"
depends on MODULES
depends on HAVE_KPROBES
select KALLSYMS
+ select TASKS_RCU if PREEMPTION
help
Kprobes allows you to trap at almost any kernel address and
execute a callback function. register_kprobe() establishes
@@ -45,28 +53,28 @@ config KPROBES
config JUMP_LABEL
bool "Optimize very unlikely/likely branches"
depends on HAVE_ARCH_JUMP_LABEL
- depends on CC_HAS_ASM_GOTO
+ select OBJTOOL if HAVE_JUMP_LABEL_HACK
help
- This option enables a transparent branch optimization that
- makes certain almost-always-true or almost-always-false branch
- conditions even cheaper to execute within the kernel.
+ This option enables a transparent branch optimization that
+ makes certain almost-always-true or almost-always-false branch
+ conditions even cheaper to execute within the kernel.
- Certain performance-sensitive kernel code, such as trace points,
- scheduler functionality, networking code and KVM have such
- branches and include support for this optimization technique.
+ Certain performance-sensitive kernel code, such as trace points,
+ scheduler functionality, networking code and KVM have such
+ branches and include support for this optimization technique.
- If it is detected that the compiler has support for "asm goto",
- the kernel will compile such branches with just a nop
- instruction. When the condition flag is toggled to true, the
- nop will be converted to a jump instruction to execute the
- conditional block of instructions.
+ If it is detected that the compiler has support for "asm goto",
+ the kernel will compile such branches with just a nop
+ instruction. When the condition flag is toggled to true, the
+ nop will be converted to a jump instruction to execute the
+ conditional block of instructions.
- This technique lowers overhead and stress on the branch prediction
- of the processor and generally makes the kernel faster. The update
- of the condition is slower, but those are always very rare.
+ This technique lowers overhead and stress on the branch prediction
+ of the processor and generally makes the kernel faster. The update
+ of the condition is slower, but those are always very rare.
- ( On 32-bit x86, the necessary options added to the compiler
- flags may increase the size of the kernel slightly. )
+ ( On 32-bit x86, the necessary options added to the compiler
+ flags may increase the size of the kernel slightly. )
config STATIC_KEYS_SELFTEST
bool "Static key selftest"
@@ -90,9 +98,9 @@ config KPROBES_ON_FTRACE
depends on KPROBES && HAVE_KPROBES_ON_FTRACE
depends on DYNAMIC_FTRACE_WITH_REGS
help
- If function tracer is enabled and the arch supports full
- passing of pt_regs to function tracing, then kprobes can
- optimize on top of function tracing.
+ If function tracer is enabled and the arch supports full
+ passing of pt_regs to function tracing, then kprobes can
+ optimize on top of function tracing.
config UPROBES
def_bool n
@@ -146,21 +154,21 @@ config HAVE_EFFICIENT_UNALIGNED_ACCESS
config ARCH_USE_BUILTIN_BSWAP
bool
help
- Modern versions of GCC (since 4.4) have builtin functions
- for handling byte-swapping. Using these, instead of the old
- inline assembler that the architecture code provides in the
- __arch_bswapXX() macros, allows the compiler to see what's
- happening and offers more opportunity for optimisation. In
- particular, the compiler will be able to combine the byteswap
- with a nearby load or store and use load-and-swap or
- store-and-swap instructions if the architecture has them. It
- should almost *never* result in code which is worse than the
- hand-coded assembler in <asm/swab.h>. But just in case it
- does, the use of the builtins is optional.
+ Modern versions of GCC (since 4.4) have builtin functions
+ for handling byte-swapping. Using these, instead of the old
+ inline assembler that the architecture code provides in the
+ __arch_bswapXX() macros, allows the compiler to see what's
+ happening and offers more opportunity for optimisation. In
+ particular, the compiler will be able to combine the byteswap
+ with a nearby load or store and use load-and-swap or
+ store-and-swap instructions if the architecture has them. It
+ should almost *never* result in code which is worse than the
+ hand-coded assembler in <asm/swab.h>. But just in case it
+ does, the use of the builtins is optional.
- Any architecture with load-and-swap or store-and-swap
- instructions should set this. And it shouldn't hurt to set it
- on architectures that don't have such instructions.
+ Any architecture with load-and-swap or store-and-swap
+ instructions should set this. And it shouldn't hurt to set it
+ on architectures that don't have such instructions.
config KRETPROBES
def_bool y
@@ -214,6 +222,9 @@ config HAVE_FUNCTION_DESCRIPTORS
config TRACE_IRQFLAGS_SUPPORT
bool
+config TRACE_IRQFLAGS_NMI_SUPPORT
+ bool
+
#
# An arch should select this if it provides all these things:
#
@@ -344,6 +355,12 @@ config HAVE_RSEQ
This symbol should be selected by an architecture if it
supports an implementation of restartable sequences.
+config HAVE_RUST
+ bool
+ help
+ This symbol should be selected by an architecture if it
+ supports Rust.
+
config HAVE_FUNCTION_ARG_ACCESS_API
bool
help
@@ -429,6 +446,13 @@ config MMU_GATHER_PAGE_SIZE
config MMU_GATHER_NO_RANGE
bool
+ select MMU_GATHER_MERGE_VMAS
+
+config MMU_GATHER_NO_FLUSH_CACHE
+ bool
+
+config MMU_GATHER_MERGE_VMAS
+ bool
config MMU_GATHER_NO_GATHER
bool
@@ -441,9 +465,44 @@ config ARCH_WANT_IRQS_OFF_ACTIVATE_MM
irqs disabled over activate_mm. Architectures that do IPI based TLB
shootdowns should enable this.
+# Use normal mm refcounting for MMU_LAZY_TLB kernel thread references.
+# MMU_LAZY_TLB_REFCOUNT=n can improve the scalability of context switching
+# to/from kernel threads when the same mm is running on a lot of CPUs (a large
+# multi-threaded application), by reducing contention on the mm refcount.
+#
+# This can be disabled if the architecture ensures no CPUs are using an mm as a
+# "lazy tlb" beyond its final refcount (i.e., by the time __mmdrop frees the mm
+# or its kernel page tables). This could be arranged by arch_exit_mmap(), or
+# final exit(2) TLB flush, for example.
+#
+# To implement this, an arch *must*:
+# Ensure the _lazy_tlb variants of mmgrab/mmdrop are used when manipulating
+# the lazy tlb reference of a kthread's ->active_mm (non-arch code has been
+# converted already).
+config MMU_LAZY_TLB_REFCOUNT
+ def_bool y
+ depends on !MMU_LAZY_TLB_SHOOTDOWN
+
+# This option allows MMU_LAZY_TLB_REFCOUNT=n. It ensures no CPUs are using an
+# mm as a lazy tlb beyond its last reference count, by shooting down these
+# users before the mm is deallocated. __mmdrop() first IPIs all CPUs that may
+# be using the mm as a lazy tlb, so that they may switch themselves to using
+# init_mm for their active mm. mm_cpumask(mm) is used to determine which CPUs
+# may be using mm as a lazy tlb mm.
+#
+# To implement this, an arch *must*:
+# - At the time of the final mmdrop of the mm, ensure mm_cpumask(mm) contains
+# at least all possible CPUs in which the mm is lazy.
+# - It must meet the requirements for MMU_LAZY_TLB_REFCOUNT=n (see above).
+config MMU_LAZY_TLB_SHOOTDOWN
+ bool
+
config ARCH_HAVE_NMI_SAFE_CMPXCHG
bool
+config ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
+ bool
+
config HAVE_ALIGNED_STRUCT_PAGE
bool
help
@@ -611,7 +670,7 @@ config ARCH_SUPPORTS_SHADOW_CALL_STACK
config SHADOW_CALL_STACK
bool "Shadow Call Stack"
depends on ARCH_SUPPORTS_SHADOW_CALL_STACK
- depends on DYNAMIC_FTRACE_WITH_REGS || !FUNCTION_GRAPH_TRACER
+ depends on DYNAMIC_FTRACE_WITH_ARGS || DYNAMIC_FTRACE_WITH_REGS || !FUNCTION_GRAPH_TRACER
help
This option enables the compiler's Shadow Call Stack, which
uses a shadow stack to protect function return addresses from
@@ -627,6 +686,13 @@ config SHADOW_CALL_STACK
reading and writing arbitrary memory may be able to locate them
and hijack control flow by modifying the stacks.
+config DYNAMIC_SCS
+ bool
+ help
+ Set by the arch code if it relies on code patching to insert the
+ shadow call stack push and pop instructions rather than on the
+ compiler.
+
config LTO
bool
help
@@ -686,13 +752,13 @@ config LTO_CLANG_FULL
depends on !COMPILE_TEST
select LTO_CLANG
help
- This option enables Clang's full Link Time Optimization (LTO), which
- allows the compiler to optimize the kernel globally. If you enable
- this option, the compiler generates LLVM bitcode instead of ELF
- object files, and the actual compilation from bitcode happens at
- the LTO link step, which may take several minutes depending on the
- kernel configuration. More information can be found from LLVM's
- documentation:
+ This option enables Clang's full Link Time Optimization (LTO), which
+ allows the compiler to optimize the kernel globally. If you enable
+ this option, the compiler generates LLVM bitcode instead of ELF
+ object files, and the actual compilation from bitcode happens at
+ the LTO link step, which may take several minutes depending on the
+ kernel configuration. More information can be found from LLVM's
+ documentation:
https://llvm.org/docs/LinkTimeOptimization.html
@@ -720,14 +786,13 @@ config ARCH_SUPPORTS_CFI_CLANG
An architecture should select this option if it can support Clang's
Control-Flow Integrity (CFI) checking.
+config ARCH_USES_CFI_TRAPS
+ bool
+
config CFI_CLANG
bool "Use Clang's Control Flow Integrity (CFI)"
- depends on LTO_CLANG && ARCH_SUPPORTS_CFI_CLANG
- # Clang >= 12:
- # - https://bugs.llvm.org/show_bug.cgi?id=46258
- # - https://bugs.llvm.org/show_bug.cgi?id=47479
- depends on CLANG_VERSION >= 120000
- select KALLSYMS
+ depends on ARCH_SUPPORTS_CFI_CLANG
+ depends on $(cc-option,-fsanitize=kcfi)
help
This option enables Clang’s forward-edge Control Flow Integrity
(CFI) checking, where the compiler injects a runtime check to each
@@ -739,16 +804,6 @@ config CFI_CLANG
https://clang.llvm.org/docs/ControlFlowIntegrity.html
-config CFI_CLANG_SHADOW
- bool "Use CFI shadow to speed up cross-module checks"
- default y
- depends on CFI_CLANG && MODULES
- help
- If you select this option, the kernel builds a fast look-up table of
- CFI check functions in loaded modules to reduce performance overhead.
-
- If unsure, say Y.
-
config CFI_PERMISSIVE
bool "Use CFI in permissive mode"
depends on CFI_CLANG
@@ -768,7 +823,7 @@ config HAVE_ARCH_WITHIN_STACK_FRAMES
and similar) by implementing an inline arch_within_stack_frames(),
which is used by CONFIG_HARDENED_USERCOPY.
-config HAVE_CONTEXT_TRACKING
+config HAVE_CONTEXT_TRACKING_USER
bool
help
Provide kernel/user boundaries probes necessary for subsystems
@@ -776,10 +831,10 @@ config HAVE_CONTEXT_TRACKING
Syscalls need to be wrapped inside user_exit()-user_enter(), either
optimized behind static key or through the slow path using TIF_NOHZ
flag. Exceptions handlers must be wrapped as well. Irqs are already
- protected inside rcu_irq_enter/rcu_irq_exit() but preemption or signal
+ protected inside ct_irq_enter/ct_irq_exit() but preemption or signal
handling on irq exit still need to be protected.
-config HAVE_CONTEXT_TRACKING_OFFSTACK
+config HAVE_CONTEXT_TRACKING_USER_OFFSTACK
bool
help
Architecture neither relies on exception_enter()/exception_exit()
@@ -791,7 +846,7 @@ config HAVE_CONTEXT_TRACKING_OFFSTACK
- Critical entry code isn't preemptible (or better yet:
not interruptible).
- - No use of RCU read side critical sections, unless rcu_nmi_enter()
+ - No use of RCU read side critical sections, unless ct_nmi_enter()
got called.
- No use of instrumentation, unless instrumentation_begin() got
called.
@@ -854,10 +909,8 @@ config HAVE_ARCH_HUGE_VMAP
#
# Archs that select this would be capable of PMD-sized vmaps (i.e.,
-# arch_vmap_pmd_supported() returns true), and they must make no assumptions
-# that vmalloc memory is mapped with PAGE_SIZE ptes. The VM_NO_HUGE_VMAP flag
-# can be used to prohibit arch-specific allocations from using hugepages to
-# help with this (e.g., modules may require it).
+# arch_vmap_pmd_supported() returns true). The VM_ALLOW_HUGE_VMAP flag
+# must be used to enable allocations to use hugepages.
#
config HAVE_ARCH_HUGE_VMALLOC
depends on HAVE_ARCH_HUGE_VMAP
@@ -888,6 +941,12 @@ config MODULES_USE_ELF_REL
Modules only use ELF REL relocations. Modules with ELF RELA
relocations will give an error.
+config ARCH_WANTS_MODULES_DATA_IN_VMALLOC
+ bool
+ help
+ For architectures like powerpc/32 which have constraints on module
+ allocation and need to allocate module data outside of module area.
+
config HAVE_IRQ_EXIT_ON_IRQ_STACK
bool
help
@@ -904,6 +963,9 @@ config HAVE_SOFTIRQ_ON_OWN_STACK
Architecture provides a function to run __do_softirq() on a
separate stack.
+config SOFTIRQ_ON_OWN_STACK
+ def_bool HAVE_SOFTIRQ_ON_OWN_STACK && !PREEMPT_RT
+
config ALTERNATE_USER_ADDRESS_SPACE
bool
help
@@ -1009,12 +1071,10 @@ config PAGE_SIZE_LESS_THAN_64KB
depends on !IA64_PAGE_SIZE_64KB
depends on !PAGE_SIZE_64KB
depends on !PARISC_PAGE_SIZE_64KB
- depends on !PPC_64K_PAGES
depends on PAGE_SIZE_LESS_THAN_256KB
config PAGE_SIZE_LESS_THAN_256KB
def_bool y
- depends on !PPC_256K_PAGES
depends on !PAGE_SIZE_256KB
# This allows to use a set of generic functions to determine mmap base
@@ -1028,11 +1088,27 @@ config ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
depends on MMU
select ARCH_HAS_ELF_RANDOMIZE
+config HAVE_OBJTOOL
+ bool
+
+config HAVE_JUMP_LABEL_HACK
+ bool
+
+config HAVE_NOINSTR_HACK
+ bool
+
+config HAVE_NOINSTR_VALIDATION
+ bool
+
+config HAVE_UACCESS_VALIDATION
+ bool
+ select OBJTOOL
+
config HAVE_STACK_VALIDATION
bool
help
- Architecture supports the 'objtool check' host tool command, which
- performs compile-time stack metadata validation.
+ Architecture supports objtool compile-time frame pointer rule
+ validation.
config HAVE_RELIABLE_STACKTRACE
bool
@@ -1286,9 +1362,9 @@ config ARCH_HAS_CC_PLATFORM
bool
config HAVE_SPARSE_SYSCALL_NR
- bool
- help
- An architecture should select this if its syscall numbering is sparse
+ bool
+ help
+ An architecture should select this if its syscall numbering is sparse
to save space. For example, MIPS architecture has a syscall array with
entries at 4000, 5000 and 6000 locations. This option turns on syscall
related optimizations for a given architecture.
@@ -1302,6 +1378,7 @@ config HAVE_STATIC_CALL
config HAVE_STATIC_CALL_INLINE
bool
depends on HAVE_STATIC_CALL
+ select OBJTOOL
config HAVE_PREEMPT_DYNAMIC
bool
@@ -1311,35 +1388,35 @@ config HAVE_PREEMPT_DYNAMIC_CALL
depends on HAVE_STATIC_CALL
select HAVE_PREEMPT_DYNAMIC
help
- An architecture should select this if it can handle the preemption
- model being selected at boot time using static calls.
+ An architecture should select this if it can handle the preemption
+ model being selected at boot time using static calls.
- Where an architecture selects HAVE_STATIC_CALL_INLINE, any call to a
- preemption function will be patched directly.
+ Where an architecture selects HAVE_STATIC_CALL_INLINE, any call to a
+ preemption function will be patched directly.
- Where an architecture does not select HAVE_STATIC_CALL_INLINE, any
- call to a preemption function will go through a trampoline, and the
- trampoline will be patched.
+ Where an architecture does not select HAVE_STATIC_CALL_INLINE, any
+ call to a preemption function will go through a trampoline, and the
+ trampoline will be patched.
- It is strongly advised to support inline static call to avoid any
- overhead.
+ It is strongly advised to support inline static call to avoid any
+ overhead.
config HAVE_PREEMPT_DYNAMIC_KEY
bool
- depends on HAVE_ARCH_JUMP_LABEL && CC_HAS_ASM_GOTO
+ depends on HAVE_ARCH_JUMP_LABEL
select HAVE_PREEMPT_DYNAMIC
help
- An architecture should select this if it can handle the preemption
- model being selected at boot time using static keys.
+ An architecture should select this if it can handle the preemption
+ model being selected at boot time using static keys.
- Each preemption function will be given an early return based on a
- static key. This should have slightly lower overhead than non-inline
- static calls, as this effectively inlines each trampoline into the
- start of its callee. This may avoid redundant work, and may
- integrate better with CFI schemes.
+ Each preemption function will be given an early return based on a
+ static key. This should have slightly lower overhead than non-inline
+ static calls, as this effectively inlines each trampoline into the
+ start of its callee. This may avoid redundant work, and may
+ integrate better with CFI schemes.
- This will have greater overhead than using inline static calls as
- the call to the preemption function cannot be entirely elided.
+ This will have greater overhead than using inline static calls as
+ the call to the preemption function cannot be entirely elided.
config ARCH_WANT_LD_ORPHAN_WARN
bool
@@ -1362,8 +1439,8 @@ config ARCH_SUPPORTS_PAGE_TABLE_CHECK
config ARCH_SPLIT_ARG64
bool
help
- If a 32-bit architecture requires 64-bit arguments to be split into
- pairs of 32-bit arguments, select this option.
+ If a 32-bit architecture requires 64-bit arguments to be split into
+ pairs of 32-bit arguments, select this option.
config ARCH_HAS_ELFCORE_COMPAT
bool
@@ -1371,6 +1448,9 @@ config ARCH_HAS_ELFCORE_COMPAT
config ARCH_HAS_PARANOID_L1D_FLUSH
bool
+config ARCH_HAVE_TRACE_MMIO_ACCESS
+ bool
+
config DYNAMIC_SIGFRAME
bool
@@ -1378,8 +1458,40 @@ config DYNAMIC_SIGFRAME
config HAVE_ARCH_NODE_DEV_GROUP
bool
+config ARCH_HAS_NONLEAF_PMD_YOUNG
+ bool
+ help
+ Architectures that select this option are capable of setting the
+ accessed bit in non-leaf PMD entries when using them as part of linear
+ address translations. Page table walkers that clear the accessed bit
+ may use this capability to reduce their search space.
+
source "kernel/gcov/Kconfig"
source "scripts/gcc-plugins/Kconfig"
+config FUNCTION_ALIGNMENT_4B
+ bool
+
+config FUNCTION_ALIGNMENT_8B
+ bool
+
+config FUNCTION_ALIGNMENT_16B
+ bool
+
+config FUNCTION_ALIGNMENT_32B
+ bool
+
+config FUNCTION_ALIGNMENT_64B
+ bool
+
+config FUNCTION_ALIGNMENT
+ int
+ default 64 if FUNCTION_ALIGNMENT_64B
+ default 32 if FUNCTION_ALIGNMENT_32B
+ default 16 if FUNCTION_ALIGNMENT_16B
+ default 8 if FUNCTION_ALIGNMENT_8B
+ default 4 if FUNCTION_ALIGNMENT_4B
+ default 0
+
endmenu
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 7d0d26b5b3f5..a5c2b1aa46b0 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -3,6 +3,7 @@ config ALPHA
bool
default y
select ARCH_32BIT_USTAT_F_TINODE
+ select ARCH_HAS_CURRENT_STACK_POINTER
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_MIGHT_HAVE_PC_SERIO
select ARCH_NO_PREEMPT
@@ -17,7 +18,6 @@ config ALPHA
select HAVE_PERF_EVENTS
select NEED_DMA_MAP_STATE
select NEED_SG_DMA_LENGTH
- select VIRT_TO_BUS
select GENERIC_IRQ_PROBE
select GENERIC_PCI_IOMAP
select AUTO_IRQ_AFFINITY if SMP
@@ -27,6 +27,7 @@ config ALPHA
select AUDIT_ARCH
select GENERIC_CPU_VULNERABILITIES
select GENERIC_SMP_IDLE_THREAD
+ select HAS_IOPORT
select HAVE_ARCH_AUDITSYSCALL
select HAVE_MOD_ARCH_SPECIFIC
select MODULES_USE_ELF_RELA
diff --git a/arch/alpha/Makefile b/arch/alpha/Makefile
index 881cb913e23a..45158024085e 100644
--- a/arch/alpha/Makefile
+++ b/arch/alpha/Makefile
@@ -36,8 +36,6 @@ cflags-y += $(cpuflags-y)
# BWX is most important, but we don't really want any emulation ever.
KBUILD_CFLAGS += $(cflags-y) -Wa,-mev6
-head-y := arch/alpha/kernel/head.o
-
libs-y += arch/alpha/lib/
# export what is needed by arch/alpha/boot/Makefile
diff --git a/arch/alpha/boot/bootp.c b/arch/alpha/boot/bootp.c
index b4faba2432d5..842e85776cc0 100644
--- a/arch/alpha/boot/bootp.c
+++ b/arch/alpha/boot/bootp.c
@@ -18,7 +18,7 @@
#include <asm/hwrpb.h>
#include <asm/io.h>
-#include <stdarg.h>
+#include <linux/stdarg.h>
#include "ksize.h"
diff --git a/arch/alpha/boot/bootpz.c b/arch/alpha/boot/bootpz.c
index 90a2b341e9c0..c6079308eab3 100644
--- a/arch/alpha/boot/bootpz.c
+++ b/arch/alpha/boot/bootpz.c
@@ -20,7 +20,7 @@
#include <asm/hwrpb.h>
#include <asm/io.h>
-#include <stdarg.h>
+#include <linux/stdarg.h>
#include "kzsize.h"
diff --git a/arch/alpha/boot/main.c b/arch/alpha/boot/main.c
index e5347a080008..22a1cb0264af 100644
--- a/arch/alpha/boot/main.c
+++ b/arch/alpha/boot/main.c
@@ -15,7 +15,7 @@
#include <asm/console.h>
#include <asm/hwrpb.h>
-#include <stdarg.h>
+#include <linux/stdarg.h>
#include "ksize.h"
diff --git a/arch/alpha/boot/misc.c b/arch/alpha/boot/misc.c
index 325d4dd4f904..1ab91852d9f7 100644
--- a/arch/alpha/boot/misc.c
+++ b/arch/alpha/boot/misc.c
@@ -89,8 +89,6 @@ static ulg output_ptr;
static ulg bytes_out;
static void error(char *m);
-static void gzip_mark(void **);
-static void gzip_release(void **);
extern int end;
static ulg free_mem_ptr;
diff --git a/arch/alpha/boot/stdio.c b/arch/alpha/boot/stdio.c
index 60f73ccd2e89..faa5234b90b8 100644
--- a/arch/alpha/boot/stdio.c
+++ b/arch/alpha/boot/stdio.c
@@ -2,8 +2,8 @@
/*
* Copyright (C) Paul Mackerras 1997.
*/
-#include <stdarg.h>
-#include <stddef.h>
+#include <linux/string.h>
+#include <linux/stdarg.h>
size_t strnlen(const char * s, size_t count)
{
@@ -42,8 +42,8 @@ static int skip_atoi(const char **s)
static char * number(char * str, unsigned long long num, int base, int size, int precision, int type)
{
- char c,sign,tmp[66];
- const char *digits="0123456789abcdefghijklmnopqrstuvwxyz";
+ char c, sign, tmp[66];
+ const char *digits = "0123456789abcdefghijklmnopqrstuvwxyz";
int i;
if (type & LARGE)
@@ -83,14 +83,14 @@ static char * number(char * str, unsigned long long num, int base, int size, int
precision = i;
size -= precision;
if (!(type&(ZEROPAD+LEFT)))
- while(size-->0)
+ while (size-- > 0)
*str++ = ' ';
if (sign)
*str++ = sign;
if (type & SPECIAL) {
if (base==8)
*str++ = '0';
- else if (base==16) {
+ else if (base == 16) {
*str++ = '0';
*str++ = digits[33];
}
@@ -125,7 +125,7 @@ int vsprintf(char *buf, const char *fmt, va_list args)
/* 'z' changed to 'Z' --davidm 1/25/99 */
- for (str=buf ; *fmt ; ++fmt) {
+ for (str = buf ; *fmt ; ++fmt) {
if (*fmt != '%') {
*str++ = *fmt;
continue;
@@ -296,7 +296,7 @@ int sprintf(char * buf, const char *fmt, ...)
int i;
va_start(args, fmt);
- i=vsprintf(buf,fmt,args);
+ i = vsprintf(buf, fmt, args);
va_end(args);
return i;
}
diff --git a/arch/alpha/boot/tools/objstrip.c b/arch/alpha/boot/tools/objstrip.c
index 08b430d25a31..7cf92d172dce 100644
--- a/arch/alpha/boot/tools/objstrip.c
+++ b/arch/alpha/boot/tools/objstrip.c
@@ -148,7 +148,7 @@ main (int argc, char *argv[])
#ifdef __ELF__
elf = (struct elfhdr *) buf;
- if (elf->e_ident[0] == 0x7f && str_has_prefix((char *)elf->e_ident + 1, "ELF")) {
+ if (memcmp(&elf->e_ident[EI_MAG0], ELFMAG, SELFMAG) == 0) {
if (elf->e_type != ET_EXEC) {
fprintf(stderr, "%s: %s is not an ELF executable\n",
prog_name, inname);
diff --git a/arch/alpha/configs/defconfig b/arch/alpha/configs/defconfig
index 7e9336930880..1816c1dc22b1 100644
--- a/arch/alpha/configs/defconfig
+++ b/arch/alpha/configs/defconfig
@@ -39,14 +39,12 @@ CONFIG_PATA_CYPRESS=y
CONFIG_ATA_GENERIC=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=m
-CONFIG_NET_ETHERNET=y
CONFIG_NET_VENDOR_3COM=y
CONFIG_VORTEX=y
CONFIG_NET_TULIP=y
CONFIG_DE2104X=m
CONFIG_TULIP=y
CONFIG_TULIP_MMIO=y
-CONFIG_NET_PCI=y
CONFIG_YELLOWFIN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@@ -65,7 +63,7 @@ CONFIG_NFSD=m
CONFIG_NLS_CODEPAGE_437=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_ALPHA_LEGACY_START_ADDRESS=y
CONFIG_MATHEMU=y
CONFIG_CRYPTO_HMAC=y
diff --git a/arch/alpha/include/asm/Kbuild b/arch/alpha/include/asm/Kbuild
index 42911c8340c7..dd31e97edae8 100644
--- a/arch/alpha/include/asm/Kbuild
+++ b/arch/alpha/include/asm/Kbuild
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
generated-y += syscall_table.h
+generic-y += agp.h
+generic-y += asm-offsets.h
generic-y += export.h
generic-y += kvm_para.h
generic-y += mcs_spinlock.h
diff --git a/arch/alpha/include/asm/a.out.h b/arch/alpha/include/asm/a.out.h
deleted file mode 100644
index d2346b7caff1..000000000000
--- a/arch/alpha/include/asm/a.out.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ALPHA_A_OUT_H__
-#define __ALPHA_A_OUT_H__
-
-#include <uapi/asm/a.out.h>
-
-
-/* Assume that start addresses below 4G belong to a TASO application.
- Unfortunately, there is no proper bit in the exec header to check.
- Worse, we have to notice the start address before swapping to use
- /sbin/loader, which of course is _not_ a TASO application. */
-#define SET_AOUT_PERSONALITY(BFPM, EX) \
- set_personality (((BFPM->taso || EX.ah.entry < 0x100000000L \
- ? ADDR_LIMIT_32BIT : 0) | PER_OSF4))
-
-#endif /* __A_OUT_GNU_H__ */
diff --git a/arch/alpha/include/asm/agp.h b/arch/alpha/include/asm/agp.h
deleted file mode 100644
index 7874f063d000..000000000000
--- a/arch/alpha/include/asm/agp.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef AGP_H
-#define AGP_H 1
-
-#include <asm/io.h>
-
-/* dummy for now */
-
-#define map_page_into_agp(page) do { } while (0)
-#define unmap_page_from_agp(page) do { } while (0)
-#define flush_agp_cache() mb()
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order) \
- ((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order) \
- free_pages((unsigned long)(table), (order))
-
-#endif
diff --git a/arch/alpha/include/asm/asm-offsets.h b/arch/alpha/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/alpha/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/alpha/include/asm/bitops.h b/arch/alpha/include/asm/bitops.h
index e1d8483a45f2..bafb1c1f0fdc 100644
--- a/arch/alpha/include/asm/bitops.h
+++ b/arch/alpha/include/asm/bitops.h
@@ -46,8 +46,8 @@ set_bit(unsigned long nr, volatile void * addr)
/*
* WARNING: non atomic version.
*/
-static inline void
-__set_bit(unsigned long nr, volatile void * addr)
+static __always_inline void
+arch___set_bit(unsigned long nr, volatile unsigned long *addr)
{
int *m = ((int *) addr) + (nr >> 5);
@@ -82,8 +82,8 @@ clear_bit_unlock(unsigned long nr, volatile void * addr)
/*
* WARNING: non atomic version.
*/
-static __inline__ void
-__clear_bit(unsigned long nr, volatile void * addr)
+static __always_inline void
+arch___clear_bit(unsigned long nr, volatile unsigned long *addr)
{
int *m = ((int *) addr) + (nr >> 5);
@@ -94,7 +94,7 @@ static inline void
__clear_bit_unlock(unsigned long nr, volatile void * addr)
{
smp_mb();
- __clear_bit(nr, addr);
+ arch___clear_bit(nr, addr);
}
static inline void
@@ -118,8 +118,8 @@ change_bit(unsigned long nr, volatile void * addr)
/*
* WARNING: non atomic version.
*/
-static __inline__ void
-__change_bit(unsigned long nr, volatile void * addr)
+static __always_inline void
+arch___change_bit(unsigned long nr, volatile unsigned long *addr)
{
int *m = ((int *) addr) + (nr >> 5);
@@ -186,8 +186,8 @@ test_and_set_bit_lock(unsigned long nr, volatile void *addr)
/*
* WARNING: non atomic version.
*/
-static inline int
-__test_and_set_bit(unsigned long nr, volatile void * addr)
+static __always_inline bool
+arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
int *m = ((int *) addr) + (nr >> 5);
@@ -230,8 +230,8 @@ test_and_clear_bit(unsigned long nr, volatile void * addr)
/*
* WARNING: non atomic version.
*/
-static inline int
-__test_and_clear_bit(unsigned long nr, volatile void * addr)
+static __always_inline bool
+arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
int *m = ((int *) addr) + (nr >> 5);
@@ -272,8 +272,8 @@ test_and_change_bit(unsigned long nr, volatile void * addr)
/*
* WARNING: non atomic version.
*/
-static __inline__ int
-__test_and_change_bit(unsigned long nr, volatile void * addr)
+static __always_inline bool
+arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
int *m = ((int *) addr) + (nr >> 5);
@@ -283,11 +283,8 @@ __test_and_change_bit(unsigned long nr, volatile void * addr)
return (old & mask) != 0;
}
-static inline int
-test_bit(int nr, const volatile void * addr)
-{
- return (1UL & (((const int *) addr)[nr >> 5] >> (nr & 31))) != 0UL;
-}
+#define arch_test_bit generic_test_bit
+#define arch_test_bit_acquire generic_test_bit_acquire
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
@@ -450,6 +447,8 @@ sched_find_first_bit(const unsigned long b[2])
return __ffs(tmp) + ofs;
}
+#include <asm-generic/bitops/non-instrumented-non-atomic.h>
+
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic-setbit.h>
diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h
index 6e0a850aa9d3..91d4a4d9258c 100644
--- a/arch/alpha/include/asm/cmpxchg.h
+++ b/arch/alpha/include/asm/cmpxchg.h
@@ -6,15 +6,15 @@
* Atomic exchange routines.
*/
-#define ____xchg(type, args...) __xchg ## type ## _local(args)
+#define ____xchg(type, args...) __arch_xchg ## type ## _local(args)
#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
#include <asm/xchg.h>
#define xchg_local(ptr, x) \
({ \
__typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \
- sizeof(*(ptr))); \
+ (__typeof__(*(ptr))) __arch_xchg_local((ptr), (unsigned long)_x_,\
+ sizeof(*(ptr))); \
})
#define arch_cmpxchg_local(ptr, o, n) \
@@ -34,7 +34,7 @@
#undef ____xchg
#undef ____cmpxchg
-#define ____xchg(type, args...) __xchg ##type(args)
+#define ____xchg(type, args...) __arch_xchg ##type(args)
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
#include <asm/xchg.h>
@@ -48,7 +48,7 @@
__typeof__(*(ptr)) _x_ = (x); \
smp_mb(); \
__ret = (__typeof__(*(ptr))) \
- __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
+ __arch_xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
smp_mb(); \
__ret; \
})
diff --git a/arch/alpha/include/asm/core_apecs.h b/arch/alpha/include/asm/core_apecs.h
index 2d9726fc02ef..69a2fc62c9c3 100644
--- a/arch/alpha/include/asm/core_apecs.h
+++ b/arch/alpha/include/asm/core_apecs.h
@@ -384,7 +384,7 @@ struct el_apecs_procdata
} \
} while (0)
-__EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr)
+__EXTERN_INLINE u8 apecs_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@@ -420,7 +420,7 @@ __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
-__EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr)
+__EXTERN_INLINE u16 apecs_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@@ -456,7 +456,7 @@ __EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
-__EXTERN_INLINE unsigned int apecs_ioread32(const void __iomem *xaddr)
+__EXTERN_INLINE u32 apecs_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < APECS_DENSE_MEM)
@@ -472,6 +472,22 @@ __EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
+__EXTERN_INLINE u64 apecs_ioread64(const void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long) xaddr;
+ if (addr < APECS_DENSE_MEM)
+ addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
+ return *(vulp)addr;
+}
+
+__EXTERN_INLINE void apecs_iowrite64(u64 b, void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long) xaddr;
+ if (addr < APECS_DENSE_MEM)
+ addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
+ *(vulp)addr = b;
+}
+
__EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)
{
return (void __iomem *)(addr + APECS_IO);
diff --git a/arch/alpha/include/asm/core_cia.h b/arch/alpha/include/asm/core_cia.h
index cb22991f6761..d26bdfb7ca3b 100644
--- a/arch/alpha/include/asm/core_cia.h
+++ b/arch/alpha/include/asm/core_cia.h
@@ -342,7 +342,7 @@ struct el_CIA_sysdata_mcheck {
#define vuip volatile unsigned int __force *
#define vulp volatile unsigned long __force *
-__EXTERN_INLINE unsigned int cia_ioread8(const void __iomem *xaddr)
+__EXTERN_INLINE u8 cia_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@@ -374,7 +374,7 @@ __EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
-__EXTERN_INLINE unsigned int cia_ioread16(const void __iomem *xaddr)
+__EXTERN_INLINE u16 cia_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@@ -404,7 +404,7 @@ __EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
-__EXTERN_INLINE unsigned int cia_ioread32(const void __iomem *xaddr)
+__EXTERN_INLINE u32 cia_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < CIA_DENSE_MEM)
@@ -420,6 +420,22 @@ __EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
+__EXTERN_INLINE u64 cia_ioread64(const void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long) xaddr;
+ if (addr < CIA_DENSE_MEM)
+ addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
+ return *(vulp)addr;
+}
+
+__EXTERN_INLINE void cia_iowrite64(u64 b, void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long) xaddr;
+ if (addr < CIA_DENSE_MEM)
+ addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
+ *(vulp)addr = b;
+}
+
__EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
{
return (void __iomem *)(addr + CIA_IO);
diff --git a/arch/alpha/include/asm/core_lca.h b/arch/alpha/include/asm/core_lca.h
index ec86314418cb..d8c3e72ef8f6 100644
--- a/arch/alpha/include/asm/core_lca.h
+++ b/arch/alpha/include/asm/core_lca.h
@@ -230,7 +230,7 @@ union el_lca {
} while (0)
-__EXTERN_INLINE unsigned int lca_ioread8(const void __iomem *xaddr)
+__EXTERN_INLINE u8 lca_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@@ -266,7 +266,7 @@ __EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
-__EXTERN_INLINE unsigned int lca_ioread16(const void __iomem *xaddr)
+__EXTERN_INLINE u16 lca_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@@ -302,7 +302,7 @@ __EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
-__EXTERN_INLINE unsigned int lca_ioread32(const void __iomem *xaddr)
+__EXTERN_INLINE u32 lca_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < LCA_DENSE_MEM)
@@ -318,6 +318,22 @@ __EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
+__EXTERN_INLINE u64 lca_ioread64(const void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long) xaddr;
+ if (addr < LCA_DENSE_MEM)
+ addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
+ return *(vulp)addr;
+}
+
+__EXTERN_INLINE void lca_iowrite64(u64 b, void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long) xaddr;
+ if (addr < LCA_DENSE_MEM)
+ addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
+ *(vulp)addr = b;
+}
+
__EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr)
{
return (void __iomem *)(addr + LCA_IO);
diff --git a/arch/alpha/include/asm/core_marvel.h b/arch/alpha/include/asm/core_marvel.h
index b266e02e284b..d99f3a82e0e5 100644
--- a/arch/alpha/include/asm/core_marvel.h
+++ b/arch/alpha/include/asm/core_marvel.h
@@ -332,10 +332,10 @@ struct io7 {
#define vucp volatile unsigned char __force *
#define vusp volatile unsigned short __force *
-extern unsigned int marvel_ioread8(const void __iomem *);
+extern u8 marvel_ioread8(const void __iomem *);
extern void marvel_iowrite8(u8 b, void __iomem *);
-__EXTERN_INLINE unsigned int marvel_ioread16(const void __iomem *addr)
+__EXTERN_INLINE u16 marvel_ioread16(const void __iomem *addr)
{
return __kernel_ldwu(*(vusp)addr);
}
diff --git a/arch/alpha/include/asm/core_mcpcia.h b/arch/alpha/include/asm/core_mcpcia.h
index cb24d1bd6141..ed2bf8ad40ed 100644
--- a/arch/alpha/include/asm/core_mcpcia.h
+++ b/arch/alpha/include/asm/core_mcpcia.h
@@ -248,6 +248,7 @@ struct el_MCPCIA_uncorrected_frame_mcheck {
#define vip volatile int __force *
#define vuip volatile unsigned int __force *
+#define vulp volatile unsigned long __force *
#ifndef MCPCIA_ONE_HAE_WINDOW
#define MCPCIA_FROB_MMIO \
@@ -267,7 +268,7 @@ extern inline int __mcpcia_is_mmio(unsigned long addr)
return (addr & 0x80000000UL) == 0;
}
-__EXTERN_INLINE unsigned int mcpcia_ioread8(const void __iomem *xaddr)
+__EXTERN_INLINE u8 mcpcia_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
@@ -291,7 +292,7 @@ __EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + hose + 0x00) = w;
}
-__EXTERN_INLINE unsigned int mcpcia_ioread16(const void __iomem *xaddr)
+__EXTERN_INLINE u16 mcpcia_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
@@ -315,7 +316,7 @@ __EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + hose + 0x08) = w;
}
-__EXTERN_INLINE unsigned int mcpcia_ioread32(const void __iomem *xaddr)
+__EXTERN_INLINE u32 mcpcia_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr;
@@ -335,6 +336,26 @@ __EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
+__EXTERN_INLINE u64 mcpcia_ioread64(const void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long)xaddr;
+
+ if (!__mcpcia_is_mmio(addr))
+ addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
+
+ return *(vulp)addr;
+}
+
+__EXTERN_INLINE void mcpcia_iowrite64(u64 b, void __iomem *xaddr)
+{
+ unsigned long addr = (unsigned long)xaddr;
+
+ if (!__mcpcia_is_mmio(addr))
+ addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
+
+ *(vulp)addr = b;
+}
+
__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
{
@@ -362,6 +383,7 @@ __EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
#undef vip
#undef vuip
+#undef vulp
#undef __IO_PREFIX
#define __IO_PREFIX mcpcia
diff --git a/arch/alpha/include/asm/core_t2.h b/arch/alpha/include/asm/core_t2.h
index 12bb7addc789..ab956b1625b5 100644
--- a/arch/alpha/include/asm/core_t2.h
+++ b/arch/alpha/include/asm/core_t2.h
@@ -360,6 +360,7 @@ struct el_t2_frame_corrected {
#define vip volatile int *
#define vuip volatile unsigned int *
+#define vulp volatile unsigned long *
extern inline u8 t2_inb(unsigned long addr)
{
@@ -402,6 +403,17 @@ extern inline void t2_outl(u32 b, unsigned long addr)
mb();
}
+extern inline u64 t2_inq(unsigned long addr)
+{
+ return *(vulp) ((addr << 5) + T2_IO + 0x18);
+}
+
+extern inline void t2_outq(u64 b, unsigned long addr)
+{
+ *(vulp) ((addr << 5) + T2_IO + 0x18) = b;
+ mb();
+}
+
/*
* Memory functions.
@@ -572,7 +584,7 @@ __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
it doesn't make sense to merge the pio and mmio routines. */
#define IOPORT(OS, NS) \
-__EXTERN_INLINE unsigned int t2_ioread##NS(const void __iomem *xaddr) \
+__EXTERN_INLINE u##NS t2_ioread##NS(const void __iomem *xaddr) \
{ \
if (t2_is_mmio(xaddr)) \
return t2_read##OS(xaddr); \
@@ -590,11 +602,13 @@ __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \
IOPORT(b, 8)
IOPORT(w, 16)
IOPORT(l, 32)
+IOPORT(q, 64)
#undef IOPORT
#undef vip
#undef vuip
+#undef vulp
#undef __IO_PREFIX
#define __IO_PREFIX t2
diff --git a/arch/alpha/include/asm/div64.h b/arch/alpha/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/alpha/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/alpha/include/asm/dma-mapping.h b/arch/alpha/include/asm/dma-mapping.h
index 0ee6a5c99b16..6ce7e2041685 100644
--- a/arch/alpha/include/asm/dma-mapping.h
+++ b/arch/alpha/include/asm/dma-mapping.h
@@ -4,7 +4,7 @@
extern const struct dma_map_ops alpha_pci_ops;
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+static inline const struct dma_map_ops *get_arch_dma_ops(void)
{
#ifdef CONFIG_ALPHA_JENSEN
return NULL;
diff --git a/arch/alpha/include/asm/dma.h b/arch/alpha/include/asm/dma.h
index 28610ea7786d..a04d76b96089 100644
--- a/arch/alpha/include/asm/dma.h
+++ b/arch/alpha/include/asm/dma.h
@@ -365,13 +365,4 @@ extern void free_dma(unsigned int dmanr); /* release it again */
#define KERNEL_HAVE_CHECK_DMA
extern int check_dma(unsigned int dmanr);
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-
#endif /* _ASM_DMA_H */
diff --git a/arch/alpha/include/asm/elf.h b/arch/alpha/include/asm/elf.h
index 8049997fa372..e6da23f1da83 100644
--- a/arch/alpha/include/asm/elf.h
+++ b/arch/alpha/include/asm/elf.h
@@ -120,12 +120,6 @@ extern int dump_elf_task(elf_greg_t *dest, struct task_struct *task);
#define ELF_CORE_COPY_TASK_REGS(TASK, DEST) \
dump_elf_task(*(DEST), TASK)
-/* Similar, but for the FP registers. */
-
-extern int dump_elf_task_fp(elf_fpreg_t *dest, struct task_struct *task);
-#define ELF_CORE_COPY_FPREGS(TASK, DEST) \
- dump_elf_task_fp(*(DEST), TASK)
-
/* This yields a mask that user programs can use to figure out what
instruction set this CPU supports. This is trivial on Alpha,
but not so on other machines. */
diff --git a/arch/alpha/include/asm/floppy.h b/arch/alpha/include/asm/floppy.h
index 588758685439..64b42d9591fc 100644
--- a/arch/alpha/include/asm/floppy.h
+++ b/arch/alpha/include/asm/floppy.h
@@ -20,7 +20,7 @@
#define fd_free_dma() free_dma(FLOPPY_DMA)
#define fd_clear_dma_ff() clear_dma_ff(FLOPPY_DMA)
#define fd_set_dma_mode(mode) set_dma_mode(FLOPPY_DMA,mode)
-#define fd_set_dma_addr(addr) set_dma_addr(FLOPPY_DMA,virt_to_bus(addr))
+#define fd_set_dma_addr(addr) set_dma_addr(FLOPPY_DMA,isa_virt_to_bus(addr))
#define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA,count)
#define fd_enable_irq() enable_irq(FLOPPY_IRQ)
#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
diff --git a/arch/alpha/include/asm/fpu.h b/arch/alpha/include/asm/fpu.h
index b9691405e56b..30b24135dd7a 100644
--- a/arch/alpha/include/asm/fpu.h
+++ b/arch/alpha/include/asm/fpu.h
@@ -15,21 +15,27 @@ rdfpcr(void)
{
unsigned long tmp, ret;
+ preempt_disable();
+ if (current_thread_info()->status & TS_SAVED_FP) {
+ ret = current_thread_info()->fp[31];
+ } else {
#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
- __asm__ __volatile__ (
- "ftoit $f0,%0\n\t"
- "mf_fpcr $f0\n\t"
- "ftoit $f0,%1\n\t"
- "itoft %0,$f0"
- : "=r"(tmp), "=r"(ret));
+ __asm__ __volatile__ (
+ "ftoit $f0,%0\n\t"
+ "mf_fpcr $f0\n\t"
+ "ftoit $f0,%1\n\t"
+ "itoft %0,$f0"
+ : "=r"(tmp), "=r"(ret));
#else
- __asm__ __volatile__ (
- "stt $f0,%0\n\t"
- "mf_fpcr $f0\n\t"
- "stt $f0,%1\n\t"
- "ldt $f0,%0"
- : "=m"(tmp), "=m"(ret));
+ __asm__ __volatile__ (
+ "stt $f0,%0\n\t"
+ "mf_fpcr $f0\n\t"
+ "stt $f0,%1\n\t"
+ "ldt $f0,%0"
+ : "=m"(tmp), "=m"(ret));
#endif
+ }
+ preempt_enable();
return ret;
}
@@ -39,21 +45,28 @@ wrfpcr(unsigned long val)
{
unsigned long tmp;
+ preempt_disable();
+ if (current_thread_info()->status & TS_SAVED_FP) {
+ current_thread_info()->status |= TS_RESTORE_FP;
+ current_thread_info()->fp[31] = val;
+ } else {
#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
- __asm__ __volatile__ (
- "ftoit $f0,%0\n\t"
- "itoft %1,$f0\n\t"
- "mt_fpcr $f0\n\t"
- "itoft %0,$f0"
- : "=&r"(tmp) : "r"(val));
+ __asm__ __volatile__ (
+ "ftoit $f0,%0\n\t"
+ "itoft %1,$f0\n\t"
+ "mt_fpcr $f0\n\t"
+ "itoft %0,$f0"
+ : "=&r"(tmp) : "r"(val));
#else
- __asm__ __volatile__ (
- "stt $f0,%0\n\t"
- "ldt $f0,%1\n\t"
- "mt_fpcr $f0\n\t"
- "ldt $f0,%0"
- : "=m"(tmp) : "m"(val));
+ __asm__ __volatile__ (
+ "stt $f0,%0\n\t"
+ "ldt $f0,%1\n\t"
+ "mt_fpcr $f0\n\t"
+ "ldt $f0,%0"
+ : "=m"(tmp) : "m"(val));
#endif
+ }
+ preempt_enable();
}
static inline unsigned long
diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h
index c9cb554fbe54..7aeaf7c30a6f 100644
--- a/arch/alpha/include/asm/io.h
+++ b/arch/alpha/include/asm/io.h
@@ -14,10 +14,6 @@
the implementation we have here matches that interface. */
#include <asm-generic/iomap.h>
-/* We don't use IO slowdowns on the Alpha, but.. */
-#define __SLOW_DOWN_IO do { } while (0)
-#define SLOW_DOWN_IO do { } while (0)
-
/*
* Virtual -> physical identity mapping starts at this offset
*/
@@ -90,6 +86,8 @@ static inline void * phys_to_virt(unsigned long address)
}
#endif
+#define virt_to_phys virt_to_phys
+#define phys_to_virt phys_to_virt
#define page_to_phys(page) page_to_pa(page)
/* Maximum PIO space address supported? */
@@ -106,15 +104,15 @@ static inline void * phys_to_virt(unsigned long address)
extern unsigned long __direct_map_base;
extern unsigned long __direct_map_size;
-static inline unsigned long __deprecated virt_to_bus(volatile void *address)
+static inline unsigned long __deprecated isa_virt_to_bus(volatile void *address)
{
unsigned long phys = virt_to_phys(address);
unsigned long bus = phys + __direct_map_base;
return phys <= __direct_map_size ? bus : 0;
}
-#define isa_virt_to_bus virt_to_bus
+#define isa_virt_to_bus isa_virt_to_bus
-static inline void * __deprecated bus_to_virt(unsigned long address)
+static inline void * __deprecated isa_bus_to_virt(unsigned long address)
{
void *virt;
@@ -125,7 +123,7 @@ static inline void * __deprecated bus_to_virt(unsigned long address)
virt = phys_to_virt(address);
return (long)address <= 0 ? NULL : virt;
}
-#define isa_bus_to_virt bus_to_virt
+#define isa_bus_to_virt isa_bus_to_virt
/*
* There are different chipsets to interface the Alpha CPUs to the world.
@@ -153,6 +151,7 @@ static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \
REMAP1(unsigned int, ioread8, const)
REMAP1(unsigned int, ioread16, const)
REMAP1(unsigned int, ioread32, const)
+REMAP1(u64, ioread64, const)
REMAP1(u8, readb, const volatile)
REMAP1(u16, readw, const volatile)
REMAP1(u32, readl, const volatile)
@@ -161,6 +160,7 @@ REMAP1(u64, readq, const volatile)
REMAP2(u8, iowrite8, /**/)
REMAP2(u16, iowrite16, /**/)
REMAP2(u32, iowrite32, /**/)
+REMAP2(u64, iowrite64, /**/)
REMAP2(u8, writeb, volatile)
REMAP2(u16, writew, volatile)
REMAP2(u32, writel, volatile)
@@ -242,6 +242,12 @@ extern u32 inl(unsigned long port);
extern void outb(u8 b, unsigned long port);
extern void outw(u16 b, unsigned long port);
extern void outl(u32 b, unsigned long port);
+#define inb inb
+#define inw inw
+#define inl inl
+#define outb outb
+#define outw outw
+#define outl outl
extern u8 readb(const volatile void __iomem *addr);
extern u16 readw(const volatile void __iomem *addr);
@@ -251,6 +257,14 @@ extern void writeb(u8 b, volatile void __iomem *addr);
extern void writew(u16 b, volatile void __iomem *addr);
extern void writel(u32 b, volatile void __iomem *addr);
extern void writeq(u64 b, volatile void __iomem *addr);
+#define readb readb
+#define readw readw
+#define readl readl
+#define readq readq
+#define writeb writeb
+#define writew writew
+#define writel writel
+#define writeq writeq
extern u8 __raw_readb(const volatile void __iomem *addr);
extern u16 __raw_readw(const volatile void __iomem *addr);
@@ -260,6 +274,14 @@ extern void __raw_writeb(u8 b, volatile void __iomem *addr);
extern void __raw_writew(u16 b, volatile void __iomem *addr);
extern void __raw_writel(u32 b, volatile void __iomem *addr);
extern void __raw_writeq(u64 b, volatile void __iomem *addr);
+#define __raw_readb __raw_readb
+#define __raw_readw __raw_readw
+#define __raw_readl __raw_readl
+#define __raw_readq __raw_readq
+#define __raw_writeb __raw_writeb
+#define __raw_writew __raw_writew
+#define __raw_writel __raw_writel
+#define __raw_writeq __raw_writeq
/*
* Mapping from port numbers to __iomem space is pretty easy.
@@ -277,6 +299,9 @@ extern inline void ioport_unmap(void __iomem *addr)
{
}
+#define ioport_map ioport_map
+#define ioport_unmap ioport_unmap
+
static inline void __iomem *ioremap(unsigned long port, unsigned long size)
{
return IO_CONCAT(__IO_PREFIX,ioremap) (port, size);
@@ -358,6 +383,11 @@ extern inline void outw(u16 b, unsigned long port)
}
#endif
+#define ioread8 ioread8
+#define ioread16 ioread16
+#define iowrite8 iowrite8
+#define iowrite16 iowrite16
+
#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
extern inline unsigned int ioread32(const void __iomem *addr)
{
@@ -368,12 +398,27 @@ extern inline unsigned int ioread32(const void __iomem *addr)
return ret;
}
+extern inline u64 ioread64(const void __iomem *addr)
+{
+ unsigned int ret;
+ mb();
+ ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr);
+ mb();
+ return ret;
+}
+
extern inline void iowrite32(u32 b, void __iomem *addr)
{
mb();
IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr);
}
+extern inline void iowrite64(u64 b, void __iomem *addr)
+{
+ mb();
+ IO_CONCAT(__IO_PREFIX, iowrite64)(b, addr);
+}
+
extern inline u32 inl(unsigned long port)
{
return ioread32(ioport_map(port, 4));
@@ -385,6 +430,11 @@ extern inline void outl(u32 b, unsigned long port)
}
#endif
+#define ioread32 ioread32
+#define ioread64 ioread64
+#define iowrite32 iowrite32
+#define iowrite64 iowrite64
+
#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1
extern inline u8 __raw_readb(const volatile void __iomem *addr)
{
@@ -505,6 +555,10 @@ extern u8 readb_relaxed(const volatile void __iomem *addr);
extern u16 readw_relaxed(const volatile void __iomem *addr);
extern u32 readl_relaxed(const volatile void __iomem *addr);
extern u64 readq_relaxed(const volatile void __iomem *addr);
+#define readb_relaxed readb_relaxed
+#define readw_relaxed readw_relaxed
+#define readl_relaxed readl_relaxed
+#define readq_relaxed readq_relaxed
#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
extern inline u8 readb_relaxed(const volatile void __iomem *addr)
@@ -557,6 +611,10 @@ static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len)
_memset_c_io(addr, 0x0001000100010001UL * c, len);
}
+#define memset_io memset_io
+#define memcpy_fromio memcpy_fromio
+#define memcpy_toio memcpy_toio
+
/*
* String versions of in/out ops:
*/
@@ -567,6 +625,13 @@ extern void outsb (unsigned long port, const void *src, unsigned long count);
extern void outsw (unsigned long port, const void *src, unsigned long count);
extern void outsl (unsigned long port, const void *src, unsigned long count);
+#define insb insb
+#define insw insw
+#define insl insl
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
+
/*
* The Alpha Jensen hardware for some rather strange reason puts
* the RTC clock at 0x170 instead of 0x70. Probably due to some
@@ -587,21 +652,29 @@ extern void outsl (unsigned long port, const void *src, unsigned long count);
#define RTC_ALWAYS_BCD 0
/*
- * Some mucking forons use if[n]def writeq to check if platform has it.
- * It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them
- * to play with; for now just use cpp anti-recursion logics and make sure
- * that damn thing is defined and expands to itself.
- */
-
-#define writeq writeq
-#define readq readq
-
-/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
+/*
+ * These get provided from <asm-generic/iomap.h> since alpha does not
+ * select GENERIC_IOMAP.
+ */
+#define ioread64 ioread64
+#define iowrite64 iowrite64
+#define ioread64be ioread64be
+#define iowrite64be iowrite64be
+#define ioread8_rep ioread8_rep
+#define ioread16_rep ioread16_rep
+#define ioread32_rep ioread32_rep
+#define iowrite8_rep iowrite8_rep
+#define iowrite16_rep iowrite16_rep
+#define iowrite32_rep iowrite32_rep
+#define pci_iounmap pci_iounmap
+
+#include <asm-generic/io.h>
+
#endif /* __KERNEL__ */
#endif /* __ALPHA_IO_H */
diff --git a/arch/alpha/include/asm/io_trivial.h b/arch/alpha/include/asm/io_trivial.h
index a1a29cbe02fa..00032093bcfc 100644
--- a/arch/alpha/include/asm/io_trivial.h
+++ b/arch/alpha/include/asm/io_trivial.h
@@ -6,13 +6,13 @@
/* This file may be included multiple times. */
#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
-__EXTERN_INLINE unsigned int
+__EXTERN_INLINE u8
IO_CONCAT(__IO_PREFIX,ioread8)(const void __iomem *a)
{
return __kernel_ldbu(*(const volatile u8 __force *)a);
}
-__EXTERN_INLINE unsigned int
+__EXTERN_INLINE u16
IO_CONCAT(__IO_PREFIX,ioread16)(const void __iomem *a)
{
return __kernel_ldwu(*(const volatile u16 __force *)a);
@@ -32,7 +32,7 @@ IO_CONCAT(__IO_PREFIX,iowrite16)(u16 b, void __iomem *a)
#endif
#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
-__EXTERN_INLINE unsigned int
+__EXTERN_INLINE u32
IO_CONCAT(__IO_PREFIX,ioread32)(const void __iomem *a)
{
return *(const volatile u32 __force *)a;
@@ -43,6 +43,18 @@ IO_CONCAT(__IO_PREFIX,iowrite32)(u32 b, void __iomem *a)
{
*(volatile u32 __force *)a = b;
}
+
+__EXTERN_INLINE u64
+IO_CONCAT(__IO_PREFIX,ioread64)(const void __iomem *a)
+{
+ return *(const volatile u64 __force *)a;
+}
+
+__EXTERN_INLINE void
+IO_CONCAT(__IO_PREFIX,iowrite64)(u64 b, void __iomem *a)
+{
+ *(volatile u64 __force *)a = b;
+}
#endif
#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1
diff --git a/arch/alpha/include/asm/irq_regs.h b/arch/alpha/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/alpha/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/alpha/include/asm/jensen.h b/arch/alpha/include/asm/jensen.h
index 1c4131453db2..66eb049eb421 100644
--- a/arch/alpha/include/asm/jensen.h
+++ b/arch/alpha/include/asm/jensen.h
@@ -98,6 +98,7 @@ __EXTERN_INLINE void jensen_set_hae(unsigned long addr)
}
#define vuip volatile unsigned int *
+#define vulp volatile unsigned long *
/*
* IO functions
@@ -183,6 +184,12 @@ __EXTERN_INLINE u32 jensen_inl(unsigned long addr)
return *(vuip) ((addr << 7) + EISA_IO + 0x60);
}
+__EXTERN_INLINE u64 jensen_inq(unsigned long addr)
+{
+ jensen_set_hae(0);
+ return *(vulp) ((addr << 7) + EISA_IO + 0x60);
+}
+
__EXTERN_INLINE void jensen_outw(u16 b, unsigned long addr)
{
jensen_set_hae(0);
@@ -197,6 +204,13 @@ __EXTERN_INLINE void jensen_outl(u32 b, unsigned long addr)
mb();
}
+__EXTERN_INLINE void jensen_outq(u64 b, unsigned long addr)
+{
+ jensen_set_hae(0);
+ *(vulp) ((addr << 7) + EISA_IO + 0x60) = b;
+ mb();
+}
+
/*
* Memory functions.
*/
@@ -305,7 +319,7 @@ __EXTERN_INLINE int jensen_is_mmio(const volatile void __iomem *addr)
that it doesn't make sense to merge them. */
#define IOPORT(OS, NS) \
-__EXTERN_INLINE unsigned int jensen_ioread##NS(const void __iomem *xaddr) \
+__EXTERN_INLINE u##NS jensen_ioread##NS(const void __iomem *xaddr) \
{ \
if (jensen_is_mmio(xaddr)) \
return jensen_read##OS(xaddr - 0x100000000ul); \
@@ -323,10 +337,12 @@ __EXTERN_INLINE void jensen_iowrite##NS(u##NS b, void __iomem *xaddr) \
IOPORT(b, 8)
IOPORT(w, 16)
IOPORT(l, 32)
+IOPORT(q, 64)
#undef IOPORT
#undef vuip
+#undef vulp
#undef __IO_PREFIX
#define __IO_PREFIX jensen
diff --git a/arch/alpha/include/asm/kdebug.h b/arch/alpha/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/alpha/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/alpha/include/asm/local.h b/arch/alpha/include/asm/local.h
index fab26a1c93d5..0fcaad642cc3 100644
--- a/arch/alpha/include/asm/local.h
+++ b/arch/alpha/include/asm/local.h
@@ -52,8 +52,16 @@ static __inline__ long local_sub_return(long i, local_t * l)
return result;
}
-#define local_cmpxchg(l, o, n) \
- (cmpxchg_local(&((l)->a.counter), (o), (n)))
+static __inline__ long local_cmpxchg(local_t *l, long old, long new)
+{
+ return cmpxchg_local(&l->a.counter, old, new);
+}
+
+static __inline__ bool local_try_cmpxchg(local_t *l, long *old, long new)
+{
+ return try_cmpxchg_local(&l->a.counter, (s64 *)old, new);
+}
+
#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
/**
diff --git a/arch/alpha/include/asm/machvec.h b/arch/alpha/include/asm/machvec.h
index e49fabce7b33..8623f995d34c 100644
--- a/arch/alpha/include/asm/machvec.h
+++ b/arch/alpha/include/asm/machvec.h
@@ -46,13 +46,15 @@ struct alpha_machine_vector
void (*mv_pci_tbi)(struct pci_controller *hose,
dma_addr_t start, dma_addr_t end);
- unsigned int (*mv_ioread8)(const void __iomem *);
- unsigned int (*mv_ioread16)(const void __iomem *);
- unsigned int (*mv_ioread32)(const void __iomem *);
+ u8 (*mv_ioread8)(const void __iomem *);
+ u16 (*mv_ioread16)(const void __iomem *);
+ u32 (*mv_ioread32)(const void __iomem *);
+ u64 (*mv_ioread64)(const void __iomem *);
void (*mv_iowrite8)(u8, void __iomem *);
void (*mv_iowrite16)(u16, void __iomem *);
void (*mv_iowrite32)(u32, void __iomem *);
+ void (*mv_iowrite64)(u64, void __iomem *);
u8 (*mv_readb)(const volatile void __iomem *);
u16 (*mv_readw)(const volatile void __iomem *);
diff --git a/arch/alpha/include/asm/page.h b/arch/alpha/include/asm/page.h
index 18f48a6f2ff6..4db1ebc0ed99 100644
--- a/arch/alpha/include/asm/page.h
+++ b/arch/alpha/include/asm/page.h
@@ -17,9 +17,8 @@
extern void clear_page(void *page);
#define clear_user_page(page, vaddr, pg) clear_page(page)
-#define alloc_zeroed_user_highpage_movable(vma, vaddr) \
- alloc_page_vma(GFP_HIGHUSER_MOVABLE | __GFP_ZERO, vma, vmaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE_MOVABLE
+#define vma_alloc_zeroed_movable_folio(vma, vaddr) \
+ vma_alloc_folio(GFP_HIGHUSER_MOVABLE | __GFP_ZERO, 0, vma, vaddr, false)
extern void copy_page(void * _to, void * _from);
#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
@@ -87,10 +86,6 @@ typedef struct page *pgtable_t;
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid((__pa(kaddr) >> PAGE_SHIFT))
-#ifdef CONFIG_FLATMEM
-#define pfn_valid(pfn) ((pfn) < max_mapnr)
-#endif /* CONFIG_FLATMEM */
-
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>
diff --git a/arch/alpha/include/asm/pci.h b/arch/alpha/include/asm/pci.h
index cf6bc1e64d66..6312656279d7 100644
--- a/arch/alpha/include/asm/pci.h
+++ b/arch/alpha/include/asm/pci.h
@@ -56,12 +56,6 @@ struct pci_controller {
/* IOMMU controls. */
-/* TODO: integrate with include/asm-generic/pci.h ? */
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
- return channel ? 15 : 14;
-}
-
#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h
index 170451fde043..ba43cb841d19 100644
--- a/arch/alpha/include/asm/pgtable.h
+++ b/arch/alpha/include/asm/pgtable.h
@@ -74,6 +74,9 @@ struct vm_area_struct;
#define _PAGE_DIRTY 0x20000
#define _PAGE_ACCESSED 0x40000
+/* We borrow bit 39 to store the exclusive marker in swap PTEs. */
+#define _PAGE_SWP_EXCLUSIVE 0x8000000000UL
+
/*
* NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly
* by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
@@ -116,23 +119,6 @@ struct vm_area_struct;
* arch/alpha/mm/fault.c)
*/
/* xwr */
-#define __P000 _PAGE_P(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
-#define __P001 _PAGE_P(_PAGE_FOE | _PAGE_FOW)
-#define __P010 _PAGE_P(_PAGE_FOE)
-#define __P011 _PAGE_P(_PAGE_FOE)
-#define __P100 _PAGE_P(_PAGE_FOW | _PAGE_FOR)
-#define __P101 _PAGE_P(_PAGE_FOW)
-#define __P110 _PAGE_P(0)
-#define __P111 _PAGE_P(0)
-
-#define __S000 _PAGE_S(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
-#define __S001 _PAGE_S(_PAGE_FOE | _PAGE_FOW)
-#define __S010 _PAGE_S(_PAGE_FOE)
-#define __S011 _PAGE_S(_PAGE_FOE)
-#define __S100 _PAGE_S(_PAGE_FOW | _PAGE_FOR)
-#define __S101 _PAGE_S(_PAGE_FOW)
-#define __S110 _PAGE_S(0)
-#define __S111 _PAGE_S(0)
/*
* pgprot_noncached() is only for infiniband pci support, and a real
@@ -318,19 +304,46 @@ extern inline void update_mmu_cache(struct vm_area_struct * vma,
}
/*
- * Non-present pages: high 24 bits are offset, next 8 bits type,
- * low 32 bits zero.
+ * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
+ * are !pte_none() && !pte_present().
+ *
+ * Format of swap PTEs:
+ *
+ * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
+ * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
+ * <------------------- offset ------------------> E <--- type -->
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * <--------------------------- zeroes -------------------------->
+ *
+ * E is the exclusive marker that is not stored in swap entries.
*/
extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
-{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
+{ pte_t pte; pte_val(pte) = ((type & 0x7f) << 32) | (offset << 40); return pte; }
-#define __swp_type(x) (((x).val >> 32) & 0xff)
+#define __swp_type(x) (((x).val >> 32) & 0x7f)
#define __swp_offset(x) ((x).val >> 40)
#define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-#define kern_addr_valid(addr) (1)
+static inline int pte_swp_exclusive(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
+}
+
+static inline pte_t pte_swp_mkexclusive(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
+ return pte;
+}
+
+static inline pte_t pte_swp_clear_exclusive(pte_t pte)
+{
+ pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
+ return pte;
+}
#define pte_ERROR(e) \
printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
diff --git a/arch/alpha/include/asm/processor.h b/arch/alpha/include/asm/processor.h
index 43e234c518b1..714abe494e5f 100644
--- a/arch/alpha/include/asm/processor.h
+++ b/arch/alpha/include/asm/processor.h
@@ -36,8 +36,6 @@ extern void start_thread(struct pt_regs *, unsigned long, unsigned long);
/* Free all resources held by a thread. */
struct task_struct;
-extern void release_thread(struct task_struct *);
-
unsigned long __get_wchan(struct task_struct *p);
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
diff --git a/arch/alpha/include/asm/ptrace.h b/arch/alpha/include/asm/ptrace.h
index df5f317ab3fc..3557ce64ed21 100644
--- a/arch/alpha/include/asm/ptrace.h
+++ b/arch/alpha/include/asm/ptrace.h
@@ -16,7 +16,6 @@
#define current_pt_regs() \
((struct pt_regs *) ((char *)current_thread_info() + 2*PAGE_SIZE) - 1)
-#define signal_pt_regs current_pt_regs
#define force_successful_syscall_return() (current_pt_regs()->r0 = 0)
diff --git a/arch/alpha/include/asm/termios.h b/arch/alpha/include/asm/termios.h
deleted file mode 100644
index b7c77bb1bfd2..000000000000
--- a/arch/alpha/include/asm/termios.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ALPHA_TERMIOS_H
-#define _ALPHA_TERMIOS_H
-
-#include <uapi/asm/termios.h>
-
-/* eof=^D eol=\0 eol2=\0 erase=del
- werase=^W kill=^U reprint=^R sxtc=\0
- intr=^C quit=^\ susp=^Z <OSF/1 VDSUSP>
- start=^Q stop=^S lnext=^V discard=^U
- vmin=\1 vtime=\0
-*/
-#define INIT_C_CC "\004\000\000\177\027\025\022\000\003\034\032\000\021\023\026\025\001\000"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-
-#define user_termio_to_kernel_termios(a_termios, u_termio) \
-({ \
- struct ktermios *k_termios = (a_termios); \
- struct termio k_termio; \
- int canon, ret; \
- \
- ret = copy_from_user(&k_termio, u_termio, sizeof(k_termio)); \
- if (!ret) { \
- /* Overwrite only the low bits. */ \
- *(unsigned short *)&k_termios->c_iflag = k_termio.c_iflag; \
- *(unsigned short *)&k_termios->c_oflag = k_termio.c_oflag; \
- *(unsigned short *)&k_termios->c_cflag = k_termio.c_cflag; \
- *(unsigned short *)&k_termios->c_lflag = k_termio.c_lflag; \
- canon = k_termio.c_lflag & ICANON; \
- \
- k_termios->c_cc[VINTR] = k_termio.c_cc[_VINTR]; \
- k_termios->c_cc[VQUIT] = k_termio.c_cc[_VQUIT]; \
- k_termios->c_cc[VERASE] = k_termio.c_cc[_VERASE]; \
- k_termios->c_cc[VKILL] = k_termio.c_cc[_VKILL]; \
- k_termios->c_cc[VEOL2] = k_termio.c_cc[_VEOL2]; \
- k_termios->c_cc[VSWTC] = k_termio.c_cc[_VSWTC]; \
- k_termios->c_cc[canon ? VEOF : VMIN] = k_termio.c_cc[_VEOF]; \
- k_termios->c_cc[canon ? VEOL : VTIME] = k_termio.c_cc[_VEOL]; \
- } \
- ret; \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- *
- * Note the "fun" _VMIN overloading.
- */
-#define kernel_termios_to_user_termio(u_termio, a_termios) \
-({ \
- struct ktermios *k_termios = (a_termios); \
- struct termio k_termio; \
- int canon; \
- \
- k_termio.c_iflag = k_termios->c_iflag; \
- k_termio.c_oflag = k_termios->c_oflag; \
- k_termio.c_cflag = k_termios->c_cflag; \
- canon = (k_termio.c_lflag = k_termios->c_lflag) & ICANON; \
- \
- k_termio.c_line = k_termios->c_line; \
- k_termio.c_cc[_VINTR] = k_termios->c_cc[VINTR]; \
- k_termio.c_cc[_VQUIT] = k_termios->c_cc[VQUIT]; \
- k_termio.c_cc[_VERASE] = k_termios->c_cc[VERASE]; \
- k_termio.c_cc[_VKILL] = k_termios->c_cc[VKILL]; \
- k_termio.c_cc[_VEOF] = k_termios->c_cc[canon ? VEOF : VMIN]; \
- k_termio.c_cc[_VEOL] = k_termios->c_cc[canon ? VEOL : VTIME]; \
- k_termio.c_cc[_VEOL2] = k_termios->c_cc[VEOL2]; \
- k_termio.c_cc[_VSWTC] = k_termios->c_cc[VSWTC]; \
- \
- copy_to_user(u_termio, &k_termio, sizeof(k_termio)); \
-})
-
-#define user_termios_to_kernel_termios(k, u) \
- copy_from_user(k, u, sizeof(struct termios2))
-
-#define kernel_termios_to_user_termios(u, k) \
- copy_to_user(u, k, sizeof(struct termios2))
-
-#define user_termios_to_kernel_termios_1(k, u) \
- copy_from_user(k, u, sizeof(struct termios))
-
-#define kernel_termios_to_user_termios_1(u, k) \
- copy_to_user(u, k, sizeof(struct termios))
-
-#endif /* _ALPHA_TERMIOS_H */
diff --git a/arch/alpha/include/asm/thread_info.h b/arch/alpha/include/asm/thread_info.h
index fdc485d7787a..4a4d00b37986 100644
--- a/arch/alpha/include/asm/thread_info.h
+++ b/arch/alpha/include/asm/thread_info.h
@@ -26,6 +26,7 @@ struct thread_info {
int bpt_nsaved;
unsigned long bpt_addr[2]; /* breakpoint handling */
unsigned int bpt_insn[2];
+ unsigned long fp[32];
};
/*
@@ -41,6 +42,8 @@ struct thread_info {
register struct thread_info *__current_thread_info __asm__("$8");
#define current_thread_info() __current_thread_info
+register unsigned long *current_stack_pointer __asm__ ("$30");
+
#endif /* __ASSEMBLY__ */
/* Thread information allocation. */
@@ -75,16 +78,15 @@ register struct thread_info *__current_thread_info __asm__("$8");
/* Work to do on interrupt/exception return. */
#define _TIF_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
- _TIF_NOTIFY_RESUME)
-
-/* Work to do on any return to userspace. */
-#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK \
- | _TIF_SYSCALL_TRACE)
+ _TIF_NOTIFY_RESUME | _TIF_NOTIFY_SIGNAL)
#define TS_UAC_NOPRINT 0x0001 /* ! Preserve the following three */
#define TS_UAC_NOFIX 0x0002 /* ! flags as they match */
#define TS_UAC_SIGBUS 0x0004 /* ! userspace part of 'osf_sysinfo' */
+#define TS_SAVED_FP 0x0008
+#define TS_RESTORE_FP 0x0010
+
#define SET_UNALIGN_CTL(task,value) ({ \
__u32 status = task_thread_info(task)->status & ~UAC_BITMASK; \
if (value & PR_UNALIGN_NOPRINT) \
@@ -108,5 +110,17 @@ register struct thread_info *__current_thread_info __asm__("$8");
put_user(res, (int __user *)(value)); \
})
+#ifndef __ASSEMBLY__
+extern void __save_fpu(void);
+
+static inline void save_fpu(void)
+{
+ if (!(current_thread_info()->status & TS_SAVED_FP)) {
+ current_thread_info()->status |= TS_SAVED_FP;
+ __save_fpu();
+ }
+}
+#endif
+
#endif /* __KERNEL__ */
#endif /* _ALPHA_THREAD_INFO_H */
diff --git a/arch/alpha/include/asm/timex.h b/arch/alpha/include/asm/timex.h
index b565cc6f408e..f89798da8a14 100644
--- a/arch/alpha/include/asm/timex.h
+++ b/arch/alpha/include/asm/timex.h
@@ -28,5 +28,6 @@ static inline cycles_t get_cycles (void)
__asm__ __volatile__ ("rpcc %0" : "=r"(ret));
return ret;
}
+#define get_cycles get_cycles
#endif
diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h
index 986f5da9b7d8..caabd92ea709 100644
--- a/arch/alpha/include/asm/unistd.h
+++ b/arch/alpha/include/asm/unistd.h
@@ -4,7 +4,7 @@
#include <uapi/asm/unistd.h>
-#define NR_SYSCALLS __NR_syscalls
+#define NR_syscalls __NR_syscalls
#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/alpha/include/uapi/asm/mman.h b/arch/alpha/include/uapi/asm/mman.h
index 4aa996423b0d..763929e814e9 100644
--- a/arch/alpha/include/uapi/asm/mman.h
+++ b/arch/alpha/include/uapi/asm/mman.h
@@ -76,6 +76,8 @@
#define MADV_DONTNEED_LOCKED 24 /* like DONTNEED, but drop locked pages too */
+#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
+
/* compatibility flags */
#define MAP_FILE 0
diff --git a/arch/alpha/include/uapi/asm/ptrace.h b/arch/alpha/include/uapi/asm/ptrace.h
index c29194181025..5ca45934fcbb 100644
--- a/arch/alpha/include/uapi/asm/ptrace.h
+++ b/arch/alpha/include/uapi/asm/ptrace.h
@@ -64,7 +64,9 @@ struct switch_stack {
unsigned long r14;
unsigned long r15;
unsigned long r26;
+#ifndef __KERNEL__
unsigned long fp[32]; /* fp[31] is fpcr */
+#endif
};
diff --git a/arch/alpha/include/uapi/asm/socket.h b/arch/alpha/include/uapi/asm/socket.h
index 7d81535893af..739891b94136 100644
--- a/arch/alpha/include/uapi/asm/socket.h
+++ b/arch/alpha/include/uapi/asm/socket.h
@@ -135,6 +135,8 @@
#define SO_TXREHASH 74
+#define SO_RCVMARK 75
+
#if !defined(__KERNEL__)
#if __BITS_PER_LONG == 64
diff --git a/arch/alpha/include/uapi/asm/termbits.h b/arch/alpha/include/uapi/asm/termbits.h
index 4575ba34a0ea..f1290b22072b 100644
--- a/arch/alpha/include/uapi/asm/termbits.h
+++ b/arch/alpha/include/uapi/asm/termbits.h
@@ -2,10 +2,8 @@
#ifndef _ALPHA_TERMBITS_H
#define _ALPHA_TERMBITS_H
-#include <linux/posix_types.h>
+#include <asm-generic/termbits-common.h>
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
typedef unsigned int tcflag_t;
/*
@@ -53,76 +51,58 @@ struct ktermios {
};
/* c_cc characters */
-#define VEOF 0
-#define VEOL 1
-#define VEOL2 2
-#define VERASE 3
-#define VWERASE 4
-#define VKILL 5
-#define VREPRINT 6
-#define VSWTC 7
-#define VINTR 8
-#define VQUIT 9
-#define VSUSP 10
-#define VSTART 12
-#define VSTOP 13
-#define VLNEXT 14
-#define VDISCARD 15
-#define VMIN 16
-#define VTIME 17
+#define VEOF 0
+#define VEOL 1
+#define VEOL2 2
+#define VERASE 3
+#define VWERASE 4
+#define VKILL 5
+#define VREPRINT 6
+#define VSWTC 7
+#define VINTR 8
+#define VQUIT 9
+#define VSUSP 10
+#define VSTART 12
+#define VSTOP 13
+#define VLNEXT 14
+#define VDISCARD 15
+#define VMIN 16
+#define VTIME 17
/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IXON 0001000
-#define IXOFF 0002000
-#define IXANY 0004000
-#define IUCLC 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
+#define IXON 0x0200
+#define IXOFF 0x0400
+#define IUCLC 0x1000
+#define IMAXBEL 0x2000
+#define IUTF8 0x4000
/* c_oflag bits */
-#define OPOST 0000001
-#define ONLCR 0000002
-#define OLCUC 0000004
-
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-
-#define OFILL 00000100
-#define OFDEL 00000200
-#define NLDLY 00001400
-#define NL0 00000000
-#define NL1 00000400
-#define NL2 00001000
-#define NL3 00001400
-#define TABDLY 00006000
-#define TAB0 00000000
-#define TAB1 00002000
-#define TAB2 00004000
-#define TAB3 00006000
-#define CRDLY 00030000
-#define CR0 00000000
-#define CR1 00010000
-#define CR2 00020000
-#define CR3 00030000
-#define FFDLY 00040000
-#define FF0 00000000
-#define FF1 00040000
-#define BSDLY 00100000
-#define BS0 00000000
-#define BS1 00100000
-#define VTDLY 00200000
-#define VT0 00000000
-#define VT1 00200000
+#define ONLCR 0x00002
+#define OLCUC 0x00004
+#define NLDLY 0x00300
+#define NL0 0x00000
+#define NL1 0x00100
+#define NL2 0x00200
+#define NL3 0x00300
+#define TABDLY 0x00c00
+#define TAB0 0x00000
+#define TAB1 0x00400
+#define TAB2 0x00800
+#define TAB3 0x00c00
+#define CRDLY 0x03000
+#define CR0 0x00000
+#define CR1 0x01000
+#define CR2 0x02000
+#define CR3 0x03000
+#define FFDLY 0x04000
+#define FF0 0x00000
+#define FF1 0x04000
+#define BSDLY 0x08000
+#define BS0 0x00000
+#define BS1 0x08000
+#define VTDLY 0x10000
+#define VT0 0x00000
+#define VT1 0x10000
/*
* Should be equivalent to TAB3, see description of TAB3 in
* POSIX.1-2008, Ch. 11.2.3 "Output Modes"
@@ -130,61 +110,36 @@ struct ktermios {
#define XTABS TAB3
/* c_cflag bit meaning */
-#define CBAUD 0000037
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CBAUDEX 0000000
-#define B57600 00020
-#define B115200 00021
-#define B230400 00022
-#define B460800 00023
-#define B500000 00024
-#define B576000 00025
-#define B921600 00026
-#define B1000000 00027
-#define B1152000 00030
-#define B1500000 00031
-#define B2000000 00032
-#define B2500000 00033
-#define B3000000 00034
-#define B3500000 00035
-#define B4000000 00036
-#define BOTHER 00037
-
-#define CSIZE 00001400
-#define CS5 00000000
-#define CS6 00000400
-#define CS7 00001000
-#define CS8 00001400
-
-#define CSTOPB 00002000
-#define CREAD 00004000
-#define PARENB 00010000
-#define PARODD 00020000
-#define HUPCL 00040000
-
-#define CLOCAL 00100000
-#define CMSPAR 010000000000 /* mark or space (stick) parity */
-#define CRTSCTS 020000000000 /* flow control */
-
-#define CIBAUD 07600000
-#define IBSHIFT 16
+#define CBAUD 0x0000001f
+#define CBAUDEX 0x00000000
+#define BOTHER 0x0000001f
+#define B57600 0x00000010
+#define B115200 0x00000011
+#define B230400 0x00000012
+#define B460800 0x00000013
+#define B500000 0x00000014
+#define B576000 0x00000015
+#define B921600 0x00000016
+#define B1000000 0x00000017
+#define B1152000 0x00000018
+#define B1500000 0x00000019
+#define B2000000 0x0000001a
+#define B2500000 0x0000001b
+#define B3000000 0x0000001c
+#define B3500000 0x0000001d
+#define B4000000 0x0000001e
+#define CSIZE 0x00000300
+#define CS5 0x00000000
+#define CS6 0x00000100
+#define CS7 0x00000200
+#define CS8 0x00000300
+#define CSTOPB 0x00000400
+#define CREAD 0x00000800
+#define PARENB 0x00001000
+#define PARODD 0x00002000
+#define HUPCL 0x00004000
+#define CLOCAL 0x00008000
+#define CIBAUD 0x001f0000
/* c_lflag bits */
#define ISIG 0x00000080
@@ -204,17 +159,6 @@ struct ktermios {
#define IEXTEN 0x00000400
#define EXTPROC 0x10000000
-/* Values for the ACTION argument to `tcflow'. */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* Values for the QUEUE_SELECTOR argument to `tcflush'. */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */
#define TCSANOW 0
#define TCSADRAIN 1
diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile
index 5a74581bf0ee..fb4efec7cbc7 100644
--- a/arch/alpha/kernel/Makefile
+++ b/arch/alpha/kernel/Makefile
@@ -3,13 +3,13 @@
# Makefile for the linux kernel.
#
-extra-y := head.o vmlinux.lds
+extra-y := vmlinux.lds
asflags-y := $(KBUILD_CFLAGS)
ccflags-y := -Wno-sign-compare
-obj-y := entry.o traps.o process.o osf_sys.o irq.o \
+obj-y := head.o entry.o traps.o process.o osf_sys.o irq.o \
irq_alpha.o signal.o setup.o ptrace.o time.o \
- systbls.o err_common.o io.o bugs.o
+ systbls.o err_common.o io.o bugs.o termios.o
obj-$(CONFIG_VGA_HOSE) += console.o
obj-$(CONFIG_SMP) += smp.o
@@ -47,10 +47,6 @@ else
# Misc support
obj-$(CONFIG_ALPHA_SRM) += srmcons.o
-ifdef CONFIG_BINFMT_AOUT
-obj-y += binfmt_loader.o
-endif
-
# Core logic support
obj-$(CONFIG_ALPHA_APECS) += core_apecs.o
obj-$(CONFIG_ALPHA_CIA) += core_cia.o
diff --git a/arch/alpha/kernel/asm-offsets.c b/arch/alpha/kernel/asm-offsets.c
index 2e125e5c1508..b121294bee26 100644
--- a/arch/alpha/kernel/asm-offsets.c
+++ b/arch/alpha/kernel/asm-offsets.c
@@ -17,6 +17,8 @@ void foo(void)
DEFINE(TI_TASK, offsetof(struct thread_info, task));
DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
+ DEFINE(TI_FP, offsetof(struct thread_info, fp));
+ DEFINE(TI_STATUS, offsetof(struct thread_info, status));
BLANK();
DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked));
diff --git a/arch/alpha/kernel/binfmt_loader.c b/arch/alpha/kernel/binfmt_loader.c
deleted file mode 100644
index e4be7a543ecf..000000000000
--- a/arch/alpha/kernel/binfmt_loader.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/mm_types.h>
-#include <linux/binfmts.h>
-#include <linux/a.out.h>
-
-static int load_binary(struct linux_binprm *bprm)
-{
- struct exec *eh = (struct exec *)bprm->buf;
- unsigned long loader;
- struct file *file;
- int retval;
-
- if (eh->fh.f_magic != 0x183 || (eh->fh.f_flags & 0x3000) != 0x3000)
- return -ENOEXEC;
-
- if (bprm->loader)
- return -ENOEXEC;
-
- loader = bprm->vma->vm_end - sizeof(void *);
-
- file = open_exec("/sbin/loader");
- retval = PTR_ERR(file);
- if (IS_ERR(file))
- return retval;
-
- /* Remember if the application is TASO. */
- bprm->taso = eh->ah.entry < 0x100000000UL;
-
- bprm->interpreter = file;
- bprm->loader = loader;
- return 0;
-}
-
-static struct linux_binfmt loader_format = {
- .load_binary = load_binary,
-};
-
-static int __init init_loader_binfmt(void)
-{
- insert_binfmt(&loader_format);
- return 0;
-}
-arch_initcall(init_loader_binfmt);
diff --git a/arch/alpha/kernel/core_cia.c b/arch/alpha/kernel/core_cia.c
index f489170201c3..12926e9538b8 100644
--- a/arch/alpha/kernel/core_cia.c
+++ b/arch/alpha/kernel/core_cia.c
@@ -527,7 +527,7 @@ verify_tb_operation(void)
if (use_tbia_try2) {
alpha_mv.mv_pci_tbi = cia_pci_tbi_try2;
- /* Tags 0-3 must be disabled if we use this workaraund. */
+ /* Tags 0-3 must be disabled if we use this workaround. */
wmb();
*(vip)CIA_IOC_TB_TAGn(0) = 2;
*(vip)CIA_IOC_TB_TAGn(1) = 2;
diff --git a/arch/alpha/kernel/core_marvel.c b/arch/alpha/kernel/core_marvel.c
index 1efca79ac83c..e9348aec4649 100644
--- a/arch/alpha/kernel/core_marvel.c
+++ b/arch/alpha/kernel/core_marvel.c
@@ -803,7 +803,7 @@ void __iomem *marvel_ioportmap (unsigned long addr)
return (void __iomem *)addr;
}
-unsigned int
+u8
marvel_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S
index e227f3a29a43..eb51f93a70c8 100644
--- a/arch/alpha/kernel/entry.S
+++ b/arch/alpha/kernel/entry.S
@@ -17,7 +17,7 @@
/* Stack offsets. */
#define SP_OFF 184
-#define SWITCH_STACK_SIZE 320
+#define SWITCH_STACK_SIZE 64
.macro CFI_START_OSF_FRAME func
.align 4
@@ -159,7 +159,6 @@
.cfi_rel_offset $13, 32
.cfi_rel_offset $14, 40
.cfi_rel_offset $15, 48
- /* We don't really care about the FP registers for debugging. */
.endm
.macro UNDO_SWITCH_STACK
@@ -454,7 +453,7 @@ entSys:
SAVE_ALL
lda $8, 0x3fff
bic $sp, $8, $8
- lda $4, NR_SYSCALLS($31)
+ lda $4, NR_syscalls($31)
stq $16, SP_OFF+24($sp)
lda $5, sys_call_table
lda $27, sys_ni_syscall
@@ -469,13 +468,16 @@ entSys:
#ifdef CONFIG_AUDITSYSCALL
lda $6, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
and $3, $6, $3
-#endif
bne $3, strace
+#else
+ blbs $3, strace /* check for SYSCALL_TRACE in disguise */
+#endif
beq $4, 1f
ldq $27, 0($5)
1: jsr $26, ($27), sys_ni_syscall
ldgp $gp, 0($26)
blt $0, $syscall_error /* the call failed */
+$ret_success:
stq $0, 0($sp)
stq $31, 72($sp) /* a3=0 => no error */
@@ -495,6 +497,10 @@ ret_to_user:
and $17, _TIF_WORK_MASK, $2
bne $2, work_pending
restore_all:
+ ldl $2, TI_STATUS($8)
+ and $2, TS_SAVED_FP | TS_RESTORE_FP, $3
+ bne $3, restore_fpu
+restore_other:
.cfi_remember_state
RESTORE_ALL
call_pal PAL_rti
@@ -503,7 +509,7 @@ ret_to_kernel:
.cfi_restore_state
lda $16, 7
call_pal PAL_swpipl
- br restore_all
+ br restore_other
.align 3
$syscall_error:
@@ -525,11 +531,6 @@ $syscall_error:
stq $1, 72($sp) /* a3 for return */
br ret_from_sys_call
-$ret_success:
- stq $0, 0($sp)
- stq $31, 72($sp) /* a3=0 => no error */
- br ret_from_sys_call
-
/*
* Do all cleanup when returning from all interrupts and system calls.
*
@@ -572,6 +573,14 @@ $work_notifysig:
.type strace, @function
strace:
/* set up signal stack, call syscall_trace */
+ // NB: if anyone adds preemption, this block will need to be protected
+ ldl $1, TI_STATUS($8)
+ and $1, TS_SAVED_FP, $3
+ or $1, TS_SAVED_FP, $2
+ bne $3, 1f
+ stl $2, TI_STATUS($8)
+ bsr $26, __save_fpu
+1:
DO_SWITCH_STACK
jsr $26, syscall_trace_enter /* returns the syscall number */
UNDO_SWITCH_STACK
@@ -585,7 +594,7 @@ strace:
ldq $21, 88($sp)
/* get the system call pointer.. */
- lda $1, NR_SYSCALLS($31)
+ lda $1, NR_syscalls($31)
lda $2, sys_call_table
lda $27, sys_ni_syscall
cmpult $0, $1, $1
@@ -598,8 +607,8 @@ ret_from_straced:
/* check return.. */
blt $0, $strace_error /* the call failed */
- stq $31, 72($sp) /* a3=0 => no error */
$strace_success:
+ stq $31, 72($sp) /* a3=0 => no error */
stq $0, 0($sp) /* save return value */
DO_SWITCH_STACK
@@ -651,40 +660,6 @@ do_switch_stack:
stq $14, 40($sp)
stq $15, 48($sp)
stq $26, 56($sp)
- stt $f0, 64($sp)
- stt $f1, 72($sp)
- stt $f2, 80($sp)
- stt $f3, 88($sp)
- stt $f4, 96($sp)
- stt $f5, 104($sp)
- stt $f6, 112($sp)
- stt $f7, 120($sp)
- stt $f8, 128($sp)
- stt $f9, 136($sp)
- stt $f10, 144($sp)
- stt $f11, 152($sp)
- stt $f12, 160($sp)
- stt $f13, 168($sp)
- stt $f14, 176($sp)
- stt $f15, 184($sp)
- stt $f16, 192($sp)
- stt $f17, 200($sp)
- stt $f18, 208($sp)
- stt $f19, 216($sp)
- stt $f20, 224($sp)
- stt $f21, 232($sp)
- stt $f22, 240($sp)
- stt $f23, 248($sp)
- stt $f24, 256($sp)
- stt $f25, 264($sp)
- stt $f26, 272($sp)
- stt $f27, 280($sp)
- mf_fpcr $f0 # get fpcr
- stt $f28, 288($sp)
- stt $f29, 296($sp)
- stt $f30, 304($sp)
- stt $f0, 312($sp) # save fpcr in slot of $f31
- ldt $f0, 64($sp) # dont let "do_switch_stack" change fp state.
ret $31, ($1), 1
.cfi_endproc
.size do_switch_stack, .-do_switch_stack
@@ -703,54 +678,71 @@ undo_switch_stack:
ldq $14, 40($sp)
ldq $15, 48($sp)
ldq $26, 56($sp)
- ldt $f30, 312($sp) # get saved fpcr
- ldt $f0, 64($sp)
- ldt $f1, 72($sp)
- ldt $f2, 80($sp)
- ldt $f3, 88($sp)
- mt_fpcr $f30 # install saved fpcr
- ldt $f4, 96($sp)
- ldt $f5, 104($sp)
- ldt $f6, 112($sp)
- ldt $f7, 120($sp)
- ldt $f8, 128($sp)
- ldt $f9, 136($sp)
- ldt $f10, 144($sp)
- ldt $f11, 152($sp)
- ldt $f12, 160($sp)
- ldt $f13, 168($sp)
- ldt $f14, 176($sp)
- ldt $f15, 184($sp)
- ldt $f16, 192($sp)
- ldt $f17, 200($sp)
- ldt $f18, 208($sp)
- ldt $f19, 216($sp)
- ldt $f20, 224($sp)
- ldt $f21, 232($sp)
- ldt $f22, 240($sp)
- ldt $f23, 248($sp)
- ldt $f24, 256($sp)
- ldt $f25, 264($sp)
- ldt $f26, 272($sp)
- ldt $f27, 280($sp)
- ldt $f28, 288($sp)
- ldt $f29, 296($sp)
- ldt $f30, 304($sp)
lda $sp, SWITCH_STACK_SIZE($sp)
ret $31, ($1), 1
.cfi_endproc
.size undo_switch_stack, .-undo_switch_stack
+
+#define FR(n) n * 8 + TI_FP($8)
+ .align 4
+ .globl __save_fpu
+ .type __save_fpu, @function
+__save_fpu:
+#define V(n) stt $f##n, FR(n)
+ V( 0); V( 1); V( 2); V( 3)
+ V( 4); V( 5); V( 6); V( 7)
+ V( 8); V( 9); V(10); V(11)
+ V(12); V(13); V(14); V(15)
+ V(16); V(17); V(18); V(19)
+ V(20); V(21); V(22); V(23)
+ V(24); V(25); V(26); V(27)
+ mf_fpcr $f0 # get fpcr
+ V(28); V(29); V(30)
+ stt $f0, FR(31) # save fpcr in slot of $f31
+ ldt $f0, FR(0) # don't let "__save_fpu" change fp state.
+ ret
+#undef V
+ .size __save_fpu, .-__save_fpu
+
+ .align 4
+restore_fpu:
+ and $3, TS_RESTORE_FP, $3
+ bic $2, TS_SAVED_FP | TS_RESTORE_FP, $2
+ beq $3, 1f
+#define V(n) ldt $f##n, FR(n)
+ ldt $f30, FR(31) # get saved fpcr
+ V( 0); V( 1); V( 2); V( 3)
+ mt_fpcr $f30 # install saved fpcr
+ V( 4); V( 5); V( 6); V( 7)
+ V( 8); V( 9); V(10); V(11)
+ V(12); V(13); V(14); V(15)
+ V(16); V(17); V(18); V(19)
+ V(20); V(21); V(22); V(23)
+ V(24); V(25); V(26); V(27)
+ V(28); V(29); V(30)
+1: stl $2, TI_STATUS($8)
+ br restore_other
+#undef V
+
/*
* The meat of the context switch code.
*/
-
.align 4
.globl alpha_switch_to
.type alpha_switch_to, @function
.cfi_startproc
alpha_switch_to:
DO_SWITCH_STACK
+ ldl $1, TI_STATUS($8)
+ and $1, TS_RESTORE_FP, $3
+ bne $3, 1f
+ or $1, TS_RESTORE_FP | TS_SAVED_FP, $2
+ and $1, TS_SAVED_FP, $3
+ stl $2, TI_STATUS($8)
+ bne $3, 1f
+ bsr $26, __save_fpu
+1:
call_pal PAL_swpctx
lda $8, 0x3fff
UNDO_SWITCH_STACK
@@ -768,7 +760,7 @@ alpha_switch_to:
.align 4
.ent ret_from_fork
ret_from_fork:
- lda $26, ret_from_sys_call
+ lda $26, ret_to_user
mov $17, $16
jmp $31, schedule_tail
.end ret_from_fork
@@ -801,6 +793,14 @@ ret_from_kernel_thread:
alpha_\name:
.prologue 0
bsr $1, do_switch_stack
+ // NB: if anyone adds preemption, this block will need to be protected
+ ldl $1, TI_STATUS($8)
+ and $1, TS_SAVED_FP, $3
+ or $1, TS_SAVED_FP, $2
+ bne $3, 1f
+ stl $2, TI_STATUS($8)
+ bsr $26, __save_fpu
+1:
jsr $26, sys_\name
ldq $26, 56($sp)
lda $sp, SWITCH_STACK_SIZE($sp)
diff --git a/arch/alpha/kernel/io.c b/arch/alpha/kernel/io.c
index 838586abb1e0..eda09778268f 100644
--- a/arch/alpha/kernel/io.c
+++ b/arch/alpha/kernel/io.c
@@ -41,6 +41,15 @@ unsigned int ioread32(const void __iomem *addr)
return ret;
}
+u64 ioread64(const void __iomem *addr)
+{
+ unsigned int ret;
+ mb();
+ ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr);
+ mb();
+ return ret;
+}
+
void iowrite8(u8 b, void __iomem *addr)
{
mb();
@@ -59,12 +68,20 @@ void iowrite32(u32 b, void __iomem *addr)
IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr);
}
+void iowrite64(u64 b, void __iomem *addr)
+{
+ mb();
+ IO_CONCAT(__IO_PREFIX,iowrite64)(b, addr);
+}
+
EXPORT_SYMBOL(ioread8);
EXPORT_SYMBOL(ioread16);
EXPORT_SYMBOL(ioread32);
+EXPORT_SYMBOL(ioread64);
EXPORT_SYMBOL(iowrite8);
EXPORT_SYMBOL(iowrite16);
EXPORT_SYMBOL(iowrite32);
+EXPORT_SYMBOL(iowrite64);
u8 inb(unsigned long port)
{
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c
index f6d2946edbd2..15f2effd6baf 100644
--- a/arch/alpha/kernel/irq.c
+++ b/arch/alpha/kernel/irq.c
@@ -60,7 +60,7 @@ int irq_select_affinity(unsigned int irq)
cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
last_cpu = cpu;
- cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu));
+ irq_data_update_affinity(data, cpumask_of(cpu));
chip->irq_set_affinity(data, cpumask_of(cpu), false);
return 0;
}
diff --git a/arch/alpha/kernel/machvec_impl.h b/arch/alpha/kernel/machvec_impl.h
index 393d5d6ca5d2..c2ebcb39e589 100644
--- a/arch/alpha/kernel/machvec_impl.h
+++ b/arch/alpha/kernel/machvec_impl.h
@@ -78,9 +78,11 @@
.mv_ioread8 = CAT(low,_ioread8), \
.mv_ioread16 = CAT(low,_ioread16), \
.mv_ioread32 = CAT(low,_ioread32), \
+ .mv_ioread64 = CAT(low,_ioread64), \
.mv_iowrite8 = CAT(low,_iowrite8), \
.mv_iowrite16 = CAT(low,_iowrite16), \
.mv_iowrite32 = CAT(low,_iowrite32), \
+ .mv_iowrite64 = CAT(low,_iowrite64), \
.mv_readb = CAT(low,_readb), \
.mv_readw = CAT(low,_readw), \
.mv_readl = CAT(low,_readl), \
diff --git a/arch/alpha/kernel/module.c b/arch/alpha/kernel/module.c
index 5b60c248de9e..cbefa5a77384 100644
--- a/arch/alpha/kernel/module.c
+++ b/arch/alpha/kernel/module.c
@@ -146,10 +146,8 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
base = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr;
symtab = (Elf64_Sym *)sechdrs[symindex].sh_addr;
- /* The small sections were sorted to the end of the segment.
- The following should definitely cover them. */
- gp = (u64)me->core_layout.base + me->core_layout.size - 0x8000;
got = sechdrs[me->arch.gotsecindex].sh_addr;
+ gp = got + 0x8000;
for (i = 0; i < n; i++) {
unsigned long r_sym = ELF64_R_SYM (rela[i].r_info);
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 8bbeebb73cf0..2a9a877a0508 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -36,6 +36,7 @@
#include <linux/types.h>
#include <linux/ipc.h>
#include <linux/namei.h>
+#include <linux/mount.h>
#include <linux/uio.h>
#include <linux/vfs.h>
#include <linux/rcupdate.h>
@@ -107,7 +108,7 @@ struct osf_dirent_callback {
int error;
};
-static int
+static bool
osf_filldir(struct dir_context *ctx, const char *name, int namlen,
loff_t offset, u64 ino, unsigned int d_type)
{
@@ -119,11 +120,11 @@ osf_filldir(struct dir_context *ctx, const char *name, int namlen,
buf->error = -EINVAL; /* only used if we fail */
if (reclen > buf->count)
- return -EINVAL;
+ return false;
d_ino = ino;
if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) {
buf->error = -EOVERFLOW;
- return -EOVERFLOW;
+ return false;
}
if (buf->basep) {
if (put_user(offset, buf->basep))
@@ -140,10 +141,10 @@ osf_filldir(struct dir_context *ctx, const char *name, int namlen,
dirent = (void __user *)dirent + reclen;
buf->dirent = dirent;
buf->count -= reclen;
- return 0;
+ return true;
Efault:
buf->error = -EFAULT;
- return -EFAULT;
+ return false;
}
SYSCALL_DEFINE4(osf_getdirentries, unsigned int, fd,
@@ -521,7 +522,7 @@ SYSCALL_DEFINE4(osf_mount, unsigned long, typenr, const char __user *, path,
break;
default:
retval = -EINVAL;
- printk("osf_mount(%ld, %x)\n", typenr, flag);
+ printk_ratelimited("osf_mount(%ld, %x)\n", typenr, flag);
}
return retval;
@@ -1277,48 +1278,6 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
return addr;
}
-#ifdef CONFIG_OSF4_COMPAT
-/* Clear top 32 bits of iov_len in the user's buffer for
- compatibility with old versions of OSF/1 where iov_len
- was defined as int. */
-static int
-osf_fix_iov_len(const struct iovec __user *iov, unsigned long count)
-{
- unsigned long i;
-
- for (i = 0 ; i < count ; i++) {
- int __user *iov_len_high = (int __user *)&iov[i].iov_len + 1;
-
- if (put_user(0, iov_len_high))
- return -EFAULT;
- }
- return 0;
-}
-#endif
-
-SYSCALL_DEFINE3(osf_readv, unsigned long, fd,
- const struct iovec __user *, vector, unsigned long, count)
-{
-#ifdef CONFIG_OSF4_COMPAT
- if (unlikely(personality(current->personality) == PER_OSF4))
- if (osf_fix_iov_len(vector, count))
- return -EFAULT;
-#endif
-
- return sys_readv(fd, vector, count);
-}
-
-SYSCALL_DEFINE3(osf_writev, unsigned long, fd,
- const struct iovec __user *, vector, unsigned long, count)
-{
-#ifdef CONFIG_OSF4_COMPAT
- if (unlikely(personality(current->personality) == PER_OSF4))
- if (osf_fix_iov_len(vector, count))
- return -EFAULT;
-#endif
- return sys_writev(fd, vector, count);
-}
-
SYSCALL_DEFINE2(osf_getpriority, int, which, int, who)
{
int prio = sys_getpriority(which, who);
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 64fbfb0763b2..4458eb7f44f0 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -288,11 +288,10 @@ pcibios_claim_one_bus(struct pci_bus *b)
struct pci_bus *child_bus;
list_for_each_entry(dev, &b->devices, bus_list) {
+ struct resource *r;
int i;
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- struct resource *r = &dev->resource[i];
-
+ pci_dev_for_each_resource(dev, r, i) {
if (r->parent || !r->start || !r->flags)
continue;
if (pci_has_flag(PCI_PROBE_ONLY) ||
diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
index e83a02ed5267..c81183935e97 100644
--- a/arch/alpha/kernel/pci_iommu.c
+++ b/arch/alpha/kernel/pci_iommu.c
@@ -127,10 +127,12 @@ again:
goto again;
}
- if (ptes[p+i])
- p = ALIGN(p + i + 1, mask + 1), i = 0;
- else
+ if (ptes[p+i]) {
+ p = ALIGN(p + i + 1, mask + 1);
+ i = 0;
+ } else {
i = i + 1;
+ }
}
if (i < n) {
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index efcf7321701b..ccdb508c1516 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -689,8 +689,6 @@ static int __hw_perf_event_init(struct perf_event *event)
*/
static int alpha_pmu_event_init(struct perf_event *event)
{
- int err;
-
/* does not support taken branch sampling */
if (has_branch_stack(event))
return -EOPNOTSUPP;
@@ -709,9 +707,7 @@ static int alpha_pmu_event_init(struct perf_event *event)
return -ENODEV;
/* Do the real initialisation work. */
- err = __hw_perf_event_init(event);
-
- return err;
+ return __hw_perf_event_init(event);
}
/*
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index 5f8527081da9..582d96548385 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -9,6 +9,7 @@
* This file handles the architecture-dependent parts of process handling.
*/
+#include <linux/cpu.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/sched.h>
@@ -57,12 +58,12 @@ EXPORT_SYMBOL(pm_power_off);
void arch_cpu_idle(void)
{
wtint(0);
- raw_local_irq_enable();
}
-void arch_cpu_idle_dead(void)
+void __noreturn arch_cpu_idle_dead(void)
{
wtint(INT_MAX);
+ BUG();
}
#endif /* ALPHA_WTINT */
@@ -74,7 +75,7 @@ struct halt_info {
static void
common_shutdown_1(void *generic_ptr)
{
- struct halt_info *how = (struct halt_info *)generic_ptr;
+ struct halt_info *how = generic_ptr;
struct percpu_struct *cpup;
unsigned long *pflags, flags;
int cpuid = smp_processor_id();
@@ -125,7 +126,7 @@ common_shutdown_1(void *generic_ptr)
/* Wait for the secondaries to halt. */
set_cpu_present(boot_cpuid, false);
set_cpu_possible(boot_cpuid, false);
- while (cpumask_weight(cpu_present_mask))
+ while (!cpumask_empty(cpu_present_mask))
barrier();
#endif
@@ -134,7 +135,7 @@ common_shutdown_1(void *generic_ptr)
#ifdef CONFIG_DUMMY_CONSOLE
/* If we've gotten here after SysRq-b, leave interrupt
context before taking over the console. */
- if (in_irq())
+ if (in_hardirq())
irq_exit();
/* This has the effect of resetting the VGA video origin. */
console_lock();
@@ -225,18 +226,14 @@ flush_thread(void)
current_thread_info()->pcb.unique = 0;
}
-void
-release_thread(struct task_struct *dead_task)
-{
-}
-
/*
* Copy architecture-specific thread state
*/
-int copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long kthread_arg, struct task_struct *p,
- unsigned long tls)
+int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
{
+ unsigned long clone_flags = args->flags;
+ unsigned long usp = args->stack;
+ unsigned long tls = args->tls;
extern void ret_from_fork(void);
extern void ret_from_kernel_thread(void);
@@ -248,15 +245,17 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
childstack = ((struct switch_stack *) childregs) - 1;
childti->pcb.ksp = (unsigned long) childstack;
childti->pcb.flags = 1; /* set FEN, clear everything else */
+ childti->status |= TS_SAVED_FP | TS_RESTORE_FP;
- if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) {
+ if (unlikely(args->fn)) {
/* kernel thread */
memset(childstack, 0,
sizeof(struct switch_stack) + sizeof(struct pt_regs));
childstack->r26 = (unsigned long) ret_from_kernel_thread;
- childstack->r9 = usp; /* function */
- childstack->r10 = kthread_arg;
+ childstack->r9 = (unsigned long) args->fn;
+ childstack->r10 = (unsigned long) args->fn_arg;
childregs->hae = alpha_mv.hae_cache;
+ memset(childti->fp, '\0', sizeof(childti->fp));
childti->pcb.usp = 0;
return 0;
}
@@ -337,14 +336,11 @@ dump_elf_task(elf_greg_t *dest, struct task_struct *task)
}
EXPORT_SYMBOL(dump_elf_task);
-int
-dump_elf_task_fp(elf_fpreg_t *dest, struct task_struct *task)
+int elf_core_copy_task_fpregs(struct task_struct *t, elf_fpregset_t *fpu)
{
- struct switch_stack *sw = (struct switch_stack *)task_pt_regs(task) - 1;
- memcpy(dest, sw->fp, 32 * 8);
+ memcpy(fpu, task_thread_info(t)->fp, 32 * 8);
return 1;
}
-EXPORT_SYMBOL(dump_elf_task_fp);
/*
* Return saved PC of a blocked thread. This assumes the frame
diff --git a/arch/alpha/kernel/ptrace.c b/arch/alpha/kernel/ptrace.c
index a1a239ea002d..fde4c68e7a0b 100644
--- a/arch/alpha/kernel/ptrace.c
+++ b/arch/alpha/kernel/ptrace.c
@@ -78,6 +78,8 @@ enum {
(PAGE_SIZE*2 - sizeof(struct pt_regs) - sizeof(struct switch_stack) \
+ offsetof(struct switch_stack, reg))
+#define FP_REG(reg) (offsetof(struct thread_info, reg))
+
static int regoff[] = {
PT_REG( r0), PT_REG( r1), PT_REG( r2), PT_REG( r3),
PT_REG( r4), PT_REG( r5), PT_REG( r6), PT_REG( r7),
@@ -87,14 +89,14 @@ static int regoff[] = {
PT_REG( r20), PT_REG( r21), PT_REG( r22), PT_REG( r23),
PT_REG( r24), PT_REG( r25), PT_REG( r26), PT_REG( r27),
PT_REG( r28), PT_REG( gp), -1, -1,
- SW_REG(fp[ 0]), SW_REG(fp[ 1]), SW_REG(fp[ 2]), SW_REG(fp[ 3]),
- SW_REG(fp[ 4]), SW_REG(fp[ 5]), SW_REG(fp[ 6]), SW_REG(fp[ 7]),
- SW_REG(fp[ 8]), SW_REG(fp[ 9]), SW_REG(fp[10]), SW_REG(fp[11]),
- SW_REG(fp[12]), SW_REG(fp[13]), SW_REG(fp[14]), SW_REG(fp[15]),
- SW_REG(fp[16]), SW_REG(fp[17]), SW_REG(fp[18]), SW_REG(fp[19]),
- SW_REG(fp[20]), SW_REG(fp[21]), SW_REG(fp[22]), SW_REG(fp[23]),
- SW_REG(fp[24]), SW_REG(fp[25]), SW_REG(fp[26]), SW_REG(fp[27]),
- SW_REG(fp[28]), SW_REG(fp[29]), SW_REG(fp[30]), SW_REG(fp[31]),
+ FP_REG(fp[ 0]), FP_REG(fp[ 1]), FP_REG(fp[ 2]), FP_REG(fp[ 3]),
+ FP_REG(fp[ 4]), FP_REG(fp[ 5]), FP_REG(fp[ 6]), FP_REG(fp[ 7]),
+ FP_REG(fp[ 8]), FP_REG(fp[ 9]), FP_REG(fp[10]), FP_REG(fp[11]),
+ FP_REG(fp[12]), FP_REG(fp[13]), FP_REG(fp[14]), FP_REG(fp[15]),
+ FP_REG(fp[16]), FP_REG(fp[17]), FP_REG(fp[18]), FP_REG(fp[19]),
+ FP_REG(fp[20]), FP_REG(fp[21]), FP_REG(fp[22]), FP_REG(fp[23]),
+ FP_REG(fp[24]), FP_REG(fp[25]), FP_REG(fp[26]), FP_REG(fp[27]),
+ FP_REG(fp[28]), FP_REG(fp[29]), FP_REG(fp[30]), FP_REG(fp[31]),
PT_REG( pc)
};
diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c
index b4fbbba30aa2..33bf3a627002 100644
--- a/arch/alpha/kernel/setup.c
+++ b/arch/alpha/kernel/setup.c
@@ -491,9 +491,9 @@ setup_arch(char **cmdline_p)
boot flags depending on the boot mode, we need some shorthand.
This should do for installation. */
if (strcmp(COMMAND_LINE, "INSTALL") == 0) {
- strlcpy(command_line, "root=/dev/fd0 load_ramdisk=1", sizeof command_line);
+ strscpy(command_line, "root=/dev/fd0 load_ramdisk=1", sizeof(command_line));
} else {
- strlcpy(command_line, COMMAND_LINE, sizeof command_line);
+ strscpy(command_line, COMMAND_LINE, sizeof(command_line));
}
strcpy(boot_command_line, command_line);
*cmdline_p = command_line;
diff --git a/arch/alpha/kernel/signal.c b/arch/alpha/kernel/signal.c
index 6f47f256fe80..e62d1d461b1f 100644
--- a/arch/alpha/kernel/signal.c
+++ b/arch/alpha/kernel/signal.c
@@ -150,9 +150,10 @@ restore_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs)
{
unsigned long usp;
struct switch_stack *sw = (struct switch_stack *)regs - 1;
- long i, err = __get_user(regs->pc, &sc->sc_pc);
+ long err = __get_user(regs->pc, &sc->sc_pc);
current->restart_block.fn = do_no_restart_syscall;
+ current_thread_info()->status |= TS_SAVED_FP | TS_RESTORE_FP;
sw->r26 = (unsigned long) ret_from_sys_call;
@@ -189,9 +190,9 @@ restore_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs)
err |= __get_user(usp, sc->sc_regs+30);
wrusp(usp);
- for (i = 0; i < 31; i++)
- err |= __get_user(sw->fp[i], sc->sc_fpregs+i);
- err |= __get_user(sw->fp[31], &sc->sc_fpcr);
+ err |= __copy_from_user(current_thread_info()->fp,
+ sc->sc_fpregs, 31 * 8);
+ err |= __get_user(current_thread_info()->fp[31], &sc->sc_fpcr);
return err;
}
@@ -272,7 +273,7 @@ setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
unsigned long mask, unsigned long sp)
{
struct switch_stack *sw = (struct switch_stack *)regs - 1;
- long i, err = 0;
+ long err = 0;
err |= __put_user(on_sig_stack((unsigned long)sc), &sc->sc_onstack);
err |= __put_user(mask, &sc->sc_mask);
@@ -312,10 +313,10 @@ setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
err |= __put_user(sp, sc->sc_regs+30);
err |= __put_user(0, sc->sc_regs+31);
- for (i = 0; i < 31; i++)
- err |= __put_user(sw->fp[i], sc->sc_fpregs+i);
+ err |= __copy_to_user(sc->sc_fpregs,
+ current_thread_info()->fp, 31 * 8);
err |= __put_user(0, sc->sc_fpregs+31);
- err |= __put_user(sw->fp[31], &sc->sc_fpcr);
+ err |= __put_user(current_thread_info()->fp[31], &sc->sc_fpcr);
err |= __put_user(regs->trap_a0, &sc->sc_traparg_a0);
err |= __put_user(regs->trap_a1, &sc->sc_traparg_a1);
@@ -528,6 +529,9 @@ do_work_pending(struct pt_regs *regs, unsigned long thread_flags,
} else {
local_irq_enable();
if (thread_flags & (_TIF_SIGPENDING|_TIF_NOTIFY_SIGNAL)) {
+ preempt_disable();
+ save_fpu();
+ preempt_enable();
do_signal(regs, r0, r19);
r0 = 0;
} else {
diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
index cb64e4797d2a..7439b2377df5 100644
--- a/arch/alpha/kernel/smp.c
+++ b/arch/alpha/kernel/smp.c
@@ -497,12 +497,6 @@ smp_cpus_done(unsigned int max_cpus)
((bogosum + 2500) / (5000/HZ)) % 100);
}
-int
-setup_profiling_timer(unsigned int multiplier)
-{
- return -EINVAL;
-}
-
static void
send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation)
{
@@ -568,7 +562,7 @@ handle_ipi(struct pt_regs *regs)
}
void
-smp_send_reschedule(int cpu)
+arch_smp_send_reschedule(int cpu)
{
#ifdef DEBUG_IPI_MSG
if (cpu == hard_smp_processor_id())
@@ -634,7 +628,7 @@ flush_tlb_all(void)
static void
ipi_flush_tlb_mm(void *x)
{
- struct mm_struct *mm = (struct mm_struct *) x;
+ struct mm_struct *mm = x;
if (mm == current->active_mm && !asn_locked())
flush_tlb_current(mm);
else
@@ -676,7 +670,7 @@ struct flush_tlb_page_struct {
static void
ipi_flush_tlb_page(void *x)
{
- struct flush_tlb_page_struct *data = (struct flush_tlb_page_struct *)x;
+ struct flush_tlb_page_struct *data = x;
struct mm_struct * mm = data->mm;
if (mm == current->active_mm && !asn_locked())
diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl
index 3515bc4f16a4..8ebacf37a8cf 100644
--- a/arch/alpha/kernel/syscalls/syscall.tbl
+++ b/arch/alpha/kernel/syscalls/syscall.tbl
@@ -125,8 +125,8 @@
116 common osf_gettimeofday sys_osf_gettimeofday
117 common osf_getrusage sys_osf_getrusage
118 common getsockopt sys_getsockopt
-120 common readv sys_osf_readv
-121 common writev sys_osf_writev
+120 common readv sys_readv
+121 common writev sys_writev
122 common osf_settimeofday sys_osf_settimeofday
123 common fchown sys_fchown
124 common fchmod sys_fchmod
diff --git a/arch/alpha/kernel/termios.c b/arch/alpha/kernel/termios.c
new file mode 100644
index 000000000000..a4c29a22edf7
--- /dev/null
+++ b/arch/alpha/kernel/termios.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/termios_internal.h>
+
+int user_termio_to_kernel_termios(struct ktermios *termios,
+ struct termio __user *termio)
+{
+ struct termio v;
+ bool canon;
+
+ if (copy_from_user(&v, termio, sizeof(struct termio)))
+ return -EFAULT;
+
+ termios->c_iflag = (0xffff0000 & termios->c_iflag) | v.c_iflag;
+ termios->c_oflag = (0xffff0000 & termios->c_oflag) | v.c_oflag;
+ termios->c_cflag = (0xffff0000 & termios->c_cflag) | v.c_cflag;
+ termios->c_lflag = (0xffff0000 & termios->c_lflag) | v.c_lflag;
+ termios->c_line = (0xffff0000 & termios->c_lflag) | v.c_line;
+
+ canon = v.c_lflag & ICANON;
+ termios->c_cc[VINTR] = v.c_cc[_VINTR];
+ termios->c_cc[VQUIT] = v.c_cc[_VQUIT];
+ termios->c_cc[VERASE] = v.c_cc[_VERASE];
+ termios->c_cc[VKILL] = v.c_cc[_VKILL];
+ termios->c_cc[VEOL2] = v.c_cc[_VEOL2];
+ termios->c_cc[VSWTC] = v.c_cc[_VSWTC];
+ termios->c_cc[canon ? VEOF : VMIN] = v.c_cc[_VEOF];
+ termios->c_cc[canon ? VEOL : VTIME] = v.c_cc[_VEOL];
+
+ return 0;
+}
+
+int kernel_termios_to_user_termio(struct termio __user *termio,
+ struct ktermios *termios)
+{
+ struct termio v;
+ bool canon;
+
+ memset(&v, 0, sizeof(struct termio));
+ v.c_iflag = termios->c_iflag;
+ v.c_oflag = termios->c_oflag;
+ v.c_cflag = termios->c_cflag;
+ v.c_lflag = termios->c_lflag;
+ v.c_line = termios->c_line;
+
+ canon = v.c_lflag & ICANON;
+ v.c_cc[_VINTR] = termios->c_cc[VINTR];
+ v.c_cc[_VQUIT] = termios->c_cc[VQUIT];
+ v.c_cc[_VERASE] = termios->c_cc[VERASE];
+ v.c_cc[_VKILL] = termios->c_cc[VKILL];
+ v.c_cc[_VEOF] = termios->c_cc[canon ? VEOF : VMIN];
+ v.c_cc[_VEOL] = termios->c_cc[canon ? VEOL : VTIME];
+ v.c_cc[_VEOL2] = termios->c_cc[VEOL2];
+ v.c_cc[_VSWTC] = termios->c_cc[VSWTC];
+
+ return copy_to_user(termio, &v, sizeof(struct termio));
+}
diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c
index 8a66fe544c69..d9a67b370e04 100644
--- a/arch/alpha/kernel/traps.c
+++ b/arch/alpha/kernel/traps.c
@@ -233,7 +233,21 @@ do_entIF(unsigned long type, struct pt_regs *regs)
{
int signo, code;
- if ((regs->ps & ~IPL_MAX) == 0) {
+ if (type == 3) { /* FEN fault */
+ /* Irritating users can call PAL_clrfen to disable the
+ FPU for the process. The kernel will then trap in
+ do_switch_stack and undo_switch_stack when we try
+ to save and restore the FP registers.
+
+ Given that GCC by default generates code that uses the
+ FP registers, PAL_clrfen is not useful except for DoS
+ attacks. So turn the bleeding FPU back on and be done
+ with it. */
+ current_thread_info()->pcb.flags |= 1;
+ __reload_thread(&current_thread_info()->pcb);
+ return;
+ }
+ if (!user_mode(regs)) {
if (type == 1) {
const unsigned int *data
= (const unsigned int *) regs->pc;
@@ -366,20 +380,6 @@ do_entIF(unsigned long type, struct pt_regs *regs)
}
break;
- case 3: /* FEN fault */
- /* Irritating users can call PAL_clrfen to disable the
- FPU for the process. The kernel will then trap in
- do_switch_stack and undo_switch_stack when we try
- to save and restore the FP registers.
-
- Given that GCC by default generates code that uses the
- FP registers, PAL_clrfen is not useful except for DoS
- attacks. So turn the bleeding FPU back on and be done
- with it. */
- current_thread_info()->pcb.flags |= 1;
- __reload_thread(&current_thread_info()->pcb);
- return;
-
case 5: /* illoc */
default: /* unexpected instruction-fault type */
;
diff --git a/arch/alpha/kernel/vmlinux.lds.S b/arch/alpha/kernel/vmlinux.lds.S
index 5b78d640725d..2efa7dfc798a 100644
--- a/arch/alpha/kernel/vmlinux.lds.S
+++ b/arch/alpha/kernel/vmlinux.lds.S
@@ -27,7 +27,6 @@ SECTIONS
HEAD_TEXT
TEXT_TEXT
SCHED_TEXT
- CPUIDLE_TEXT
LOCK_TEXT
*(.fixup)
*(.gnu.warning)
diff --git a/arch/alpha/lib/csum_partial_copy.c b/arch/alpha/lib/csum_partial_copy.c
index 1931a04af85a..4d180d96f09e 100644
--- a/arch/alpha/lib/csum_partial_copy.c
+++ b/arch/alpha/lib/csum_partial_copy.c
@@ -353,7 +353,6 @@ csum_and_copy_from_user(const void __user *src, void *dst, int len)
return 0;
return __csum_and_copy(src, dst, len);
}
-EXPORT_SYMBOL(csum_and_copy_from_user);
__wsum
csum_partial_copy_nocheck(const void *src, void *dst, int len)
diff --git a/arch/alpha/lib/fpreg.c b/arch/alpha/lib/fpreg.c
index 34fea465645b..7c08b225261c 100644
--- a/arch/alpha/lib/fpreg.c
+++ b/arch/alpha/lib/fpreg.c
@@ -7,6 +7,8 @@
#include <linux/compiler.h>
#include <linux/export.h>
+#include <linux/preempt.h>
+#include <asm/thread_info.h>
#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
#define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val));
@@ -19,7 +21,12 @@ alpha_read_fp_reg (unsigned long reg)
{
unsigned long val;
- switch (reg) {
+ if (unlikely(reg >= 32))
+ return 0;
+ preempt_disable();
+ if (current_thread_info()->status & TS_SAVED_FP)
+ val = current_thread_info()->fp[reg];
+ else switch (reg) {
case 0: STT( 0, val); break;
case 1: STT( 1, val); break;
case 2: STT( 2, val); break;
@@ -52,8 +59,8 @@ alpha_read_fp_reg (unsigned long reg)
case 29: STT(29, val); break;
case 30: STT(30, val); break;
case 31: STT(31, val); break;
- default: return 0;
}
+ preempt_enable();
return val;
}
EXPORT_SYMBOL(alpha_read_fp_reg);
@@ -67,7 +74,14 @@ EXPORT_SYMBOL(alpha_read_fp_reg);
void
alpha_write_fp_reg (unsigned long reg, unsigned long val)
{
- switch (reg) {
+ if (unlikely(reg >= 32))
+ return;
+
+ preempt_disable();
+ if (current_thread_info()->status & TS_SAVED_FP) {
+ current_thread_info()->status |= TS_RESTORE_FP;
+ current_thread_info()->fp[reg] = val;
+ } else switch (reg) {
case 0: LDT( 0, val); break;
case 1: LDT( 1, val); break;
case 2: LDT( 2, val); break;
@@ -101,6 +115,7 @@ alpha_write_fp_reg (unsigned long reg, unsigned long val)
case 30: LDT(30, val); break;
case 31: LDT(31, val); break;
}
+ preempt_enable();
}
EXPORT_SYMBOL(alpha_write_fp_reg);
@@ -115,7 +130,14 @@ alpha_read_fp_reg_s (unsigned long reg)
{
unsigned long val;
- switch (reg) {
+ if (unlikely(reg >= 32))
+ return 0;
+
+ preempt_disable();
+ if (current_thread_info()->status & TS_SAVED_FP) {
+ LDT(0, current_thread_info()->fp[reg]);
+ STS(0, val);
+ } else switch (reg) {
case 0: STS( 0, val); break;
case 1: STS( 1, val); break;
case 2: STS( 2, val); break;
@@ -148,8 +170,8 @@ alpha_read_fp_reg_s (unsigned long reg)
case 29: STS(29, val); break;
case 30: STS(30, val); break;
case 31: STS(31, val); break;
- default: return 0;
}
+ preempt_enable();
return val;
}
EXPORT_SYMBOL(alpha_read_fp_reg_s);
@@ -163,7 +185,15 @@ EXPORT_SYMBOL(alpha_read_fp_reg_s);
void
alpha_write_fp_reg_s (unsigned long reg, unsigned long val)
{
- switch (reg) {
+ if (unlikely(reg >= 32))
+ return;
+
+ preempt_disable();
+ if (current_thread_info()->status & TS_SAVED_FP) {
+ current_thread_info()->status |= TS_RESTORE_FP;
+ LDS(0, val);
+ STT(0, current_thread_info()->fp[reg]);
+ } else switch (reg) {
case 0: LDS( 0, val); break;
case 1: LDS( 1, val); break;
case 2: LDS( 2, val); break;
@@ -197,5 +227,6 @@ alpha_write_fp_reg_s (unsigned long reg, unsigned long val)
case 30: LDS(30, val); break;
case 31: LDS(31, val); break;
}
+ preempt_enable();
}
EXPORT_SYMBOL(alpha_write_fp_reg_s);
diff --git a/arch/alpha/lib/stacktrace.c b/arch/alpha/lib/stacktrace.c
index 62454a7810e2..2b1176dd5174 100644
--- a/arch/alpha/lib/stacktrace.c
+++ b/arch/alpha/lib/stacktrace.c
@@ -92,7 +92,7 @@ stacktrace(void)
{
instr * ret_pc;
instr * prologue = (instr *)stacktrace;
- register unsigned char * sp __asm__ ("$30");
+ unsigned char *sp = (unsigned char *)current_stack_pointer;
printk("\tstack trace:\n");
do {
diff --git a/arch/alpha/mm/fault.c b/arch/alpha/mm/fault.c
index ec20c1004abf..7b01ae4f3bc6 100644
--- a/arch/alpha/mm/fault.c
+++ b/arch/alpha/mm/fault.c
@@ -152,7 +152,14 @@ retry:
the fault. */
fault = handle_mm_fault(vma, address, flags, regs);
- if (fault_signal_pending(fault, regs))
+ if (fault_signal_pending(fault, regs)) {
+ if (!user_mode(regs))
+ goto no_context;
+ return;
+ }
+
+ /* The fault is fully completed (including releasing mmap lock) */
+ if (fault & VM_FAULT_COMPLETED)
return;
if (unlikely(fault & VM_FAULT_ERROR)) {
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 7511723b7669..a155180d7a83 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -280,3 +280,25 @@ mem_init(void)
high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
memblock_free_all();
}
+
+static const pgprot_t protection_map[16] = {
+ [VM_NONE] = _PAGE_P(_PAGE_FOE | _PAGE_FOW |
+ _PAGE_FOR),
+ [VM_READ] = _PAGE_P(_PAGE_FOE | _PAGE_FOW),
+ [VM_WRITE] = _PAGE_P(_PAGE_FOE),
+ [VM_WRITE | VM_READ] = _PAGE_P(_PAGE_FOE),
+ [VM_EXEC] = _PAGE_P(_PAGE_FOW | _PAGE_FOR),
+ [VM_EXEC | VM_READ] = _PAGE_P(_PAGE_FOW),
+ [VM_EXEC | VM_WRITE] = _PAGE_P(0),
+ [VM_EXEC | VM_WRITE | VM_READ] = _PAGE_P(0),
+ [VM_SHARED] = _PAGE_S(_PAGE_FOE | _PAGE_FOW |
+ _PAGE_FOR),
+ [VM_SHARED | VM_READ] = _PAGE_S(_PAGE_FOE | _PAGE_FOW),
+ [VM_SHARED | VM_WRITE] = _PAGE_S(_PAGE_FOE),
+ [VM_SHARED | VM_WRITE | VM_READ] = _PAGE_S(_PAGE_FOE),
+ [VM_SHARED | VM_EXEC] = _PAGE_S(_PAGE_FOW | _PAGE_FOR),
+ [VM_SHARED | VM_EXEC | VM_READ] = _PAGE_S(_PAGE_FOW),
+ [VM_SHARED | VM_EXEC | VM_WRITE] = _PAGE_S(0),
+ [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = _PAGE_S(0)
+};
+DECLARE_VM_GET_PAGE_PROT
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index e0a60a27e14d..ab6d701365bb 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -36,8 +36,10 @@ config ARC
select HAVE_KERNEL_LZMA
select HAVE_KPROBES
select HAVE_KRETPROBES
+ select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_PERF_EVENTS
+ select HAVE_SYSCALL_TRACEPOINTS
select IRQ_DOMAIN
select MODULES_USE_ELF_RELA
select OF
@@ -552,9 +554,9 @@ config ARC_BUILTIN_DTB_NAME
endmenu # "ARC Architecture Configuration"
-config FORCE_MAX_ZONEORDER
+config ARCH_FORCE_MAX_ORDER
int "Maximum zone order"
- default "12" if ARC_HUGEPAGE_16M
- default "11"
+ default "11" if ARC_HUGEPAGE_16M
+ default "10"
source "kernel/power/Kconfig"
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index efc54f3e35e0..329400a1c355 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -82,8 +82,6 @@ KBUILD_CFLAGS += $(cflags-y)
KBUILD_AFLAGS += $(KBUILD_CFLAGS)
KBUILD_LDFLAGS += $(ldflags-y)
-head-y := arch/arc/kernel/head.o
-
# w/o this dtb won't embed into kernel binary
core-y += arch/arc/boot/dts/
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index cd1edcf4f95e..3434c8131ecd 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -103,11 +103,11 @@
dma-coherent;
};
- ehci@40000 {
+ usb@40000 {
dma-coherent;
};
- ohci@60000 {
+ usb@60000 {
dma-coherent;
};
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index 70779386ca79..67556f4b7057 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -110,11 +110,11 @@
dma-coherent;
};
- ehci@40000 {
+ usb@40000 {
dma-coherent;
};
- ohci@60000 {
+ usb@60000 {
dma-coherent;
};
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 99d3e7175bf7..b64435385304 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -87,13 +87,13 @@
mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
};
- ehci@40000 {
+ usb@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;
};
- ohci@60000 {
+ usb@60000 {
compatible = "generic-ohci";
reg = < 0x60000 0x100 >;
interrupts = < 8 >;
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index dcaa44e408ac..6691f4255077 100644
--- a/arch/arc/boot/dts/hsdk.dts
+++ b/arch/arc/boot/dts/hsdk.dts
@@ -234,7 +234,7 @@
};
};
- ohci@60000 {
+ usb@60000 {
compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
reg = <0x60000 0x100>;
interrupts = <15>;
@@ -242,7 +242,7 @@
dma-coherent;
};
- ehci@40000 {
+ usb@40000 {
compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
reg = <0x40000 0x100>;
interrupts = <15>;
@@ -275,7 +275,7 @@
cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
<&creg_gpio 1 GPIO_ACTIVE_LOW>;
- spi-flash@0 {
+ flash@0 {
compatible = "sst26wf016b", "jedec,spi-nor";
reg = <0>;
#address-cells = <1>;
diff --git a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
index cbb179770293..90a412026e64 100644
--- a/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/vdk_axs10x_mb.dtsi
@@ -46,7 +46,7 @@
clock-names = "stmmaceth";
};
- ehci@40000 {
+ usb@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;
diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig
index 0016149f9583..81764160451f 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -9,7 +9,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -36,9 +35,6 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
@@ -100,7 +96,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
diff --git a/arch/arc/configs/axs103_defconfig b/arch/arc/configs/axs103_defconfig
index 5b031582a1cf..d5181275490e 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -9,7 +9,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -35,9 +34,6 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
@@ -98,7 +94,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig
index d4eec39e0112..2f336d99a8cf 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -9,7 +9,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -36,9 +35,6 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
@@ -101,7 +97,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
diff --git a/arch/arc/configs/haps_hs_defconfig b/arch/arc/configs/haps_hs_defconfig
index 7337cdf4ffdd..899b2fd5c71d 100644
--- a/arch/arc/configs/haps_hs_defconfig
+++ b/arch/arc/configs/haps_hs_defconfig
@@ -11,7 +11,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
@@ -60,6 +59,5 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/haps_hs_smp_defconfig b/arch/arc/configs/haps_hs_smp_defconfig
index bc927221afc0..0d32aac8069f 100644
--- a/arch/arc/configs/haps_hs_smp_defconfig
+++ b/arch/arc/configs/haps_hs_smp_defconfig
@@ -11,7 +11,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -60,6 +59,5 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/hsdk_defconfig b/arch/arc/configs/hsdk_defconfig
index aa000075a575..d18378d2c2a6 100644
--- a/arch/arc/configs/hsdk_defconfig
+++ b/arch/arc/configs/hsdk_defconfig
@@ -9,7 +9,6 @@ CONFIG_NAMESPACES=y
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_BLK_DEV_RAM=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -86,7 +85,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
diff --git a/arch/arc/configs/nsim_700_defconfig b/arch/arc/configs/nsim_700_defconfig
index 326f6cde7826..3e9829775992 100644
--- a/arch/arc/configs/nsim_700_defconfig
+++ b/arch/arc/configs/nsim_700_defconfig
@@ -11,7 +11,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
@@ -57,5 +56,4 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
-# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig
index bf39a0091679..502c87f351c8 100644
--- a/arch/arc/configs/nsimosci_defconfig
+++ b/arch/arc/configs/nsimosci_defconfig
@@ -10,7 +10,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
@@ -66,4 +65,3 @@ CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
-# CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arc/configs/nsimosci_hs_defconfig b/arch/arc/configs/nsimosci_hs_defconfig
index 7121bd71c543..f721cc3997d0 100644
--- a/arch/arc/configs/nsimosci_hs_defconfig
+++ b/arch/arc/configs/nsimosci_hs_defconfig
@@ -10,7 +10,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
@@ -64,4 +63,3 @@ CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
-# CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arc/configs/nsimosci_hs_smp_defconfig b/arch/arc/configs/nsimosci_hs_smp_defconfig
index f9863b294a70..1419fc946a08 100644
--- a/arch/arc/configs/nsimosci_hs_smp_defconfig
+++ b/arch/arc/configs/nsimosci_hs_smp_defconfig
@@ -8,7 +8,6 @@ CONFIG_IKCONFIG_PROC=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_KPROBES=y
@@ -27,9 +26,6 @@ CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
@@ -38,7 +34,6 @@ CONFIG_DEVTMPFS=y
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y
# CONFIG_NET_VENDOR_INTEL is not set
@@ -75,5 +70,5 @@ CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FTRACE=y
+# CONFIG_NET_VENDOR_CADENCE is not set
diff --git a/arch/arc/configs/tb10x_defconfig b/arch/arc/configs/tb10x_defconfig
index a12656ec0072..6f0d2be9d926 100644
--- a/arch/arc/configs/tb10x_defconfig
+++ b/arch/arc/configs/tb10x_defconfig
@@ -14,7 +14,6 @@ CONFIG_INITRAMFS_SOURCE="../tb10x-rootfs.cpio"
CONFIG_INITRAMFS_ROOT_UID=2100
CONFIG_INITRAMFS_ROOT_GID=501
# CONFIG_RD_GZIP is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
@@ -36,15 +35,11 @@ CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_NETDEVICES=y
-# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
@@ -91,16 +86,15 @@ CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_HEADERS_INSTALL=y
-CONFIG_HEADERS_CHECK=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
# CONFIG_CRYPTO_HW is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
diff --git a/arch/arc/configs/vdk_hs38_defconfig b/arch/arc/configs/vdk_hs38_defconfig
index d7c858df520c..d3ef189c75f8 100644
--- a/arch/arc/configs/vdk_hs38_defconfig
+++ b/arch/arc/configs/vdk_hs38_defconfig
@@ -4,7 +4,6 @@ CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -59,8 +58,6 @@ CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
-CONFIG_ARCPGU_RGB888=y
-CONFIG_ARCPGU_DISPTYPE=0
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
@@ -88,7 +85,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_SOFTLOCKUP_DETECTOR=y
diff --git a/arch/arc/configs/vdk_hs38_smp_defconfig b/arch/arc/configs/vdk_hs38_smp_defconfig
index 015c1d43889e..944b347025fd 100644
--- a/arch/arc/configs/vdk_hs38_smp_defconfig
+++ b/arch/arc/configs/vdk_hs38_smp_defconfig
@@ -4,7 +4,6 @@ CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -92,7 +91,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_SOFTLOCKUP_DETECTOR=y
diff --git a/arch/arc/include/asm/atomic-llsc.h b/arch/arc/include/asm/atomic-llsc.h
index 088d348781c1..1b0ffaeee16d 100644
--- a/arch/arc/include/asm/atomic-llsc.h
+++ b/arch/arc/include/asm/atomic-llsc.h
@@ -5,7 +5,7 @@
#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
-#define ATOMIC_OP(op, c_op, asm_op) \
+#define ATOMIC_OP(op, asm_op) \
static inline void arch_atomic_##op(int i, atomic_t *v) \
{ \
unsigned int val; \
@@ -21,7 +21,7 @@ static inline void arch_atomic_##op(int i, atomic_t *v) \
: "cc"); \
} \
-#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
+#define ATOMIC_OP_RETURN(op, asm_op) \
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
{ \
unsigned int val; \
@@ -42,7 +42,7 @@ static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
-#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
+#define ATOMIC_FETCH_OP(op, asm_op) \
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
{ \
unsigned int val, orig; \
@@ -69,23 +69,23 @@ static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
-#define ATOMIC_OPS(op, c_op, asm_op) \
- ATOMIC_OP(op, c_op, asm_op) \
- ATOMIC_OP_RETURN(op, c_op, asm_op) \
- ATOMIC_FETCH_OP(op, c_op, asm_op)
+#define ATOMIC_OPS(op, asm_op) \
+ ATOMIC_OP(op, asm_op) \
+ ATOMIC_OP_RETURN(op, asm_op) \
+ ATOMIC_FETCH_OP(op, asm_op)
-ATOMIC_OPS(add, +=, add)
-ATOMIC_OPS(sub, -=, sub)
+ATOMIC_OPS(add, add)
+ATOMIC_OPS(sub, sub)
#undef ATOMIC_OPS
-#define ATOMIC_OPS(op, c_op, asm_op) \
- ATOMIC_OP(op, c_op, asm_op) \
- ATOMIC_FETCH_OP(op, c_op, asm_op)
+#define ATOMIC_OPS(op, asm_op) \
+ ATOMIC_OP(op, asm_op) \
+ ATOMIC_FETCH_OP(op, asm_op)
-ATOMIC_OPS(and, &=, and)
-ATOMIC_OPS(andnot, &= ~, bic)
-ATOMIC_OPS(or, |=, or)
-ATOMIC_OPS(xor, ^=, xor)
+ATOMIC_OPS(and, and)
+ATOMIC_OPS(andnot, bic)
+ATOMIC_OPS(or, or)
+ATOMIC_OPS(xor, xor)
#define arch_atomic_andnot arch_atomic_andnot
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index bdb7e190a294..f5a936496f06 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -82,7 +82,7 @@ static inline __attribute__ ((const)) int fls(unsigned int x)
/*
* __fls: Similar to fls, but zero based (0-31)
*/
-static inline __attribute__ ((const)) int __fls(unsigned long x)
+static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)
{
if (!x)
return 0;
@@ -131,7 +131,7 @@ static inline __attribute__ ((const)) int fls(unsigned int x)
/*
* __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set
*/
-static inline __attribute__ ((const)) int __fls(unsigned long x)
+static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)
{
/* FLS insn has exactly same semantics as the API */
return __builtin_arc_fls(x);
diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h
index c5b544a5fe81..e138fde067de 100644
--- a/arch/arc/include/asm/cmpxchg.h
+++ b/arch/arc/include/asm/cmpxchg.h
@@ -85,7 +85,7 @@
*/
#ifdef CONFIG_ARC_HAS_LLSC
-#define __xchg(ptr, val) \
+#define __arch_xchg(ptr, val) \
({ \
__asm__ __volatile__( \
" ex %0, [%1] \n" /* set new value */ \
@@ -102,7 +102,7 @@
\
switch(sizeof(*(_p_))) { \
case 4: \
- _val_ = __xchg(_p_, _val_); \
+ _val_ = __arch_xchg(_p_, _val_); \
break; \
default: \
BUILD_BUG(); \
diff --git a/arch/arc/include/asm/dma.h b/arch/arc/include/asm/dma.h
index 5b744f4b10a7..02431027ed2f 100644
--- a/arch/arc/include/asm/dma.h
+++ b/arch/arc/include/asm/dma.h
@@ -7,10 +7,5 @@
#define ASM_ARC_DMA_H
#define MAX_DMA_ADDRESS 0xC0000000
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy 0
-#endif
#endif
diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h
index 5aab4f93ab8a..67ff06e15cea 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -21,7 +21,7 @@
* r25 contains the kernel current task ptr
* - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
* - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
- * address Write back load ld.ab instead of seperate ld/add instn
+ * address Write back load ld.ab instead of separate ld/add instn
*
* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
*/
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 8f777d6441a5..80347382a380 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -32,7 +32,7 @@ static inline void ioport_unmap(void __iomem *addr)
{
}
-extern void iounmap(const void __iomem *addr);
+extern void iounmap(const volatile void __iomem *addr);
/*
* io{read,write}{16,32}be() macros
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 9a62e1d87967..e43fe27ec54d 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -109,7 +109,6 @@ extern int pfn_valid(unsigned long pfn);
#else /* CONFIG_HIGHMEM */
#define ARCH_PFN_OFFSET virt_to_pfn(CONFIG_LINUX_RAM_BASE)
-#define pfn_valid(pfn) (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
#endif /* CONFIG_HIGHMEM */
diff --git a/arch/arc/include/asm/perf_event.h b/arch/arc/include/asm/perf_event.h
index 4c919c0f4b30..d5719a260864 100644
--- a/arch/arc/include/asm/perf_event.h
+++ b/arch/arc/include/asm/perf_event.h
@@ -63,4 +63,8 @@ struct arc_reg_cc_build {
#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8)
+#ifdef CONFIG_PERF_EVENTS
+#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
+#endif
+
#endif /* __ASM_PERF_EVENT_H */
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h b/arch/arc/include/asm/pgtable-bits-arcv2.h
index 183d23bc1e00..6e9f8ca6d6a1 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -26,6 +26,9 @@
#define _PAGE_GLOBAL (1 << 8) /* ASID agnostic (H) */
#define _PAGE_PRESENT (1 << 9) /* PTE/TLB Valid (H) */
+/* We borrow bit 5 to store the exclusive marker in swap PTEs. */
+#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
+
#ifdef CONFIG_ARC_MMU_V4
#define _PAGE_HW_SZ (1 << 10) /* Normal/super (H) */
#else
@@ -72,24 +75,6 @@
* This is to enable COW mechanism
*/
/* xwr */
-#define __P000 PAGE_U_NONE
-#define __P001 PAGE_U_R
-#define __P010 PAGE_U_R /* Pvt-W => !W */
-#define __P011 PAGE_U_R /* Pvt-W => !W */
-#define __P100 PAGE_U_X_R /* X => R */
-#define __P101 PAGE_U_X_R
-#define __P110 PAGE_U_X_R /* Pvt-W => !W and X => R */
-#define __P111 PAGE_U_X_R /* Pvt-W => !W */
-
-#define __S000 PAGE_U_NONE
-#define __S001 PAGE_U_R
-#define __S010 PAGE_U_W_R /* W => R */
-#define __S011 PAGE_U_W_R
-#define __S100 PAGE_U_X_R /* X => R */
-#define __S101 PAGE_U_X_R
-#define __S110 PAGE_U_X_W_R /* X => R */
-#define __S111 PAGE_U_X_W_R
-
#ifndef __ASSEMBLY__
#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
@@ -124,9 +109,18 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
pte_t *ptep);
-/* Encode swap {type,off} tuple into PTE
- * We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that
- * PAGE_PRESENT is zero in a PTE holding swap "identifier"
+/*
+ * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
+ * are !pte_none() && !pte_present().
+ *
+ * Format of swap PTEs:
+ *
+ * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * <-------------- offset -------------> <--- zero --> E < type ->
+ *
+ * E is the exclusive marker that is not stored in swap entries.
+ * The zero'ed bits include _PAGE_PRESENT.
*/
#define __swp_entry(type, off) ((swp_entry_t) \
{ ((type) & 0x1f) | ((off) << 13) })
@@ -138,7 +132,13 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-#define kern_addr_valid(addr) (1)
+static inline int pte_swp_exclusive(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
+}
+
+PTE_BIT_FUNC(swp_mkexclusive, |= (_PAGE_SWP_EXCLUSIVE));
+PTE_BIT_FUNC(swp_clear_exclusive, &= ~(_PAGE_SWP_EXCLUSIVE));
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#include <asm/hugepage.h>
diff --git a/arch/arc/include/asm/pgtable-levels.h b/arch/arc/include/asm/pgtable-levels.h
index 7848348719b2..ef68758b69f7 100644
--- a/arch/arc/include/asm/pgtable-levels.h
+++ b/arch/arc/include/asm/pgtable-levels.h
@@ -98,9 +98,6 @@
/*
* 1st level paging: pgd
*/
-#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
-#define pgd_offset(mm, addr) (((mm)->pgd) + pgd_index(addr))
-#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
#define pgd_ERROR(e) \
pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
@@ -164,7 +161,7 @@
#define pmd_pfn(pmd) ((pmd_val(pmd) & PAGE_MASK) >> PAGE_SHIFT)
#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
#define set_pmd(pmdp, pmd) (*(pmdp) = pmd)
-#define pmd_pgtable(pmd) ((pgtable_t) pmd_page_vaddr(pmd))
+#define pmd_pgtable(pmd) ((pgtable_t) pmd_page(pmd))
/*
* 4th level paging: pte
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 54db9d7bb562..fb844fce1ab6 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -43,9 +43,6 @@ struct task_struct;
#define task_pt_regs(p) \
((struct pt_regs *)(THREAD_SIZE + (void *)task_stack_page(p)) - 1)
-/* Free all resources held by a thread */
-#define release_thread(thread) do { } while (0)
-
/*
* A lot of busy-wait loops in SMP are based off of non-volatile data otherwise
* get optimised away by gcc
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index cca8d6583e31..5869a74c0db2 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -8,6 +8,7 @@
#define __ASM_ARC_PTRACE_H
#include <uapi/asm/ptrace.h>
+#include <linux/compiler.h>
#ifndef __ASSEMBLY__
@@ -54,6 +55,9 @@ struct pt_regs {
unsigned long user_r25;
};
+
+#define MAX_REG_OFFSET offsetof(struct pt_regs, user_r25)
+
#else
struct pt_regs {
@@ -102,6 +106,8 @@ struct pt_regs {
unsigned long status32;
};
+#define MAX_REG_OFFSET offsetof(struct pt_regs, status32)
+
#endif
/* Callee saved registers - need to be saved only when you are scheduled out */
@@ -154,6 +160,27 @@ static inline void instruction_pointer_set(struct pt_regs *regs,
{
instruction_pointer(regs) = val;
}
+
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+ return regs->sp;
+}
+
+extern int regs_query_register_offset(const char *name);
+extern const char *regs_query_register_name(unsigned int offset);
+extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
+extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+ unsigned int n);
+
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+ unsigned int offset)
+{
+ if (unlikely(offset > MAX_REG_OFFSET))
+ return 0;
+
+ return *(unsigned long *)((unsigned long)regs + offset);
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_PTRACE_H */
diff --git a/arch/arc/include/asm/syscall.h b/arch/arc/include/asm/syscall.h
index 94529e89dff0..9709256e31c8 100644
--- a/arch/arc/include/asm/syscall.h
+++ b/arch/arc/include/asm/syscall.h
@@ -12,6 +12,8 @@
#include <asm/unistd.h>
#include <asm/ptrace.h> /* in_syscall() */
+extern void *sys_call_table[];
+
static inline long
syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
{
diff --git a/arch/arc/include/asm/thread_info.h b/arch/arc/include/asm/thread_info.h
index 1e0b2e3914d5..6ba7fe417095 100644
--- a/arch/arc/include/asm/thread_info.h
+++ b/arch/arc/include/asm/thread_info.h
@@ -78,9 +78,9 @@ static inline __attribute_const__ struct thread_info *current_thread_info(void)
#define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */
#define TIF_NOTIFY_SIGNAL 5 /* signal notifications exist */
#define TIF_SYSCALL_TRACE 15 /* syscall trace active */
-
/* true if poll_idle() is polling TIF_NEED_RESCHED */
#define TIF_MEMDIE 16
+#define TIF_SYSCALL_TRACEPOINT 17 /* syscall tracepoint instrumentation */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
@@ -89,11 +89,14 @@ static inline __attribute_const__ struct thread_info *current_thread_info(void)
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
#define _TIF_NOTIFY_SIGNAL (1<<TIF_NOTIFY_SIGNAL)
#define _TIF_MEMDIE (1<<TIF_MEMDIE)
+#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
_TIF_NOTIFY_RESUME | _TIF_NOTIFY_SIGNAL)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT)
+
/*
* _TIF_ALLWORK_MASK includes SYSCALL_TRACE, but we don't need it.
* SYSCALL_TRACE is anyway separately/unconditionally tested right after a
diff --git a/arch/arc/include/uapi/asm/bpf_perf_event.h b/arch/arc/include/uapi/asm/bpf_perf_event.h
new file mode 100644
index 000000000000..6cb1c2823288
--- /dev/null
+++ b/arch/arc/include/uapi/asm/bpf_perf_event.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__
+#define _UAPI__ASM_BPF_PERF_EVENT_H__
+
+#include <asm/ptrace.h>
+
+typedef struct user_regs_struct bpf_user_pt_regs_t;
+
+#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index 8c4fc4b54c14..0723d888ac44 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -3,7 +3,7 @@
# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
#
-obj-y := arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o
+obj-y := head.o arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o
obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o
obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o
obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
@@ -31,4 +31,4 @@ else
obj-y += ctx_sw_asm.o
endif
-extra-y := vmlinux.lds head.o
+extra-y := vmlinux.lds
diff --git a/arch/arc/kernel/disasm.c b/arch/arc/kernel/disasm.c
index 03f8b1be0c3a..ccc7e8c39eb3 100644
--- a/arch/arc/kernel/disasm.c
+++ b/arch/arc/kernel/disasm.c
@@ -366,7 +366,7 @@ void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state,
case op_SP: /* LD_S|LDB_S b,[sp,u7], ST_S|STB_S b,[sp,u7] */
/* note: we are ignoring possibility of:
* ADD_S, SUB_S, PUSH_S, POP_S as these should not
- * cause unaliged exception anyway */
+ * cause unaligned exception anyway */
state->write = BITS(state->words[0], 6, 6);
state->zz = BITS(state->words[0], 5, 5);
if (state->zz)
@@ -434,14 +434,31 @@ long __kprobes get_reg(int reg, struct pt_regs *regs,
{
long *p;
+#if defined(CONFIG_ISA_ARCOMPACT)
if (reg <= 12) {
p = &regs->r0;
return p[-reg];
}
+#else /* CONFIG_ISA_ARCV2 */
+ if (reg <= 11) {
+ p = &regs->r0;
+ return p[reg];
+ }
+ if (reg == 12)
+ return regs->r12;
+ if (reg == 30)
+ return regs->r30;
+#ifdef CONFIG_ARC_HAS_ACCL_REGS
+ if (reg == 58)
+ return regs->r58;
+ if (reg == 59)
+ return regs->r59;
+#endif
+#endif
if (cregs && (reg <= 25)) {
p = &cregs->r13;
- return p[13-reg];
+ return p[13 - reg];
}
if (reg == 26)
@@ -461,6 +478,7 @@ void __kprobes set_reg(int reg, long val, struct pt_regs *regs,
{
long *p;
+#if defined(CONFIG_ISA_ARCOMPACT)
switch (reg) {
case 0 ... 12:
p = &regs->r0;
@@ -469,7 +487,7 @@ void __kprobes set_reg(int reg, long val, struct pt_regs *regs,
case 13 ... 25:
if (cregs) {
p = &cregs->r13;
- p[13-reg] = val;
+ p[13 - reg] = val;
}
break;
case 26:
@@ -487,6 +505,48 @@ void __kprobes set_reg(int reg, long val, struct pt_regs *regs,
default:
break;
}
+#else /* CONFIG_ISA_ARCV2 */
+ switch (reg) {
+ case 0 ... 11:
+ p = &regs->r0;
+ p[reg] = val;
+ break;
+ case 12:
+ regs->r12 = val;
+ break;
+ case 13 ... 25:
+ if (cregs) {
+ p = &cregs->r13;
+ p[13 - reg] = val;
+ }
+ break;
+ case 26:
+ regs->r26 = val;
+ break;
+ case 27:
+ regs->fp = val;
+ break;
+ case 28:
+ regs->sp = val;
+ break;
+ case 30:
+ regs->r30 = val;
+ break;
+ case 31:
+ regs->blink = val;
+ break;
+#ifdef CONFIG_ARC_HAS_ACCL_REGS
+ case 58:
+ regs->r58 = val;
+ break;
+ case 59:
+ regs->r59 = val;
+ break;
+#endif
+ default:
+ break;
+ }
+#endif
}
/*
@@ -503,7 +563,6 @@ int __kprobes disasm_next_pc(unsigned long pc, struct pt_regs *regs,
{
struct disasm_state instr;
- memset(&instr, 0, sizeof(struct disasm_state));
disasm_instr(pc, &instr, 0, regs, cregs);
*next_pc = pc + instr.instr_len;
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index dd77a0c8f740..54e91df678dd 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -29,8 +29,8 @@ ENTRY(sys_clone_wrapper)
DISCARD_CALLEE_SAVED_USER
GET_CURR_THR_INFO_FLAGS r10
- btst r10, TIF_SYSCALL_TRACE
- bnz tracesys_exit
+ and.f 0, r10, _TIF_SYSCALL_WORK
+ bnz tracesys_exit
b .Lret_from_system_call
END(sys_clone_wrapper)
@@ -41,8 +41,8 @@ ENTRY(sys_clone3_wrapper)
DISCARD_CALLEE_SAVED_USER
GET_CURR_THR_INFO_FLAGS r10
- btst r10, TIF_SYSCALL_TRACE
- bnz tracesys_exit
+ and.f 0, r10, _TIF_SYSCALL_WORK
+ bnz tracesys_exit
b .Lret_from_system_call
END(sys_clone3_wrapper)
@@ -196,6 +196,7 @@ tracesys_exit:
st r0, [sp, PT_r0] ; sys call return value in pt_regs
;POST Sys Call Ptrace Hook
+ mov r0, sp ; pt_regs needed
bl @syscall_trace_exit
b ret_from_exception ; NOT ret_from_system_call at is saves r0 which
; we'd done before calling post hook above
@@ -246,8 +247,8 @@ ENTRY(EV_Trap)
; If syscall tracing ongoing, invoke pre-post-hooks
GET_CURR_THR_INFO_FLAGS r10
- btst r10, TIF_SYSCALL_TRACE
- bnz tracesys ; this never comes back
+ and.f 0, r10, _TIF_SYSCALL_WORK
+ bnz tracesys ; this never comes back
;============ Normal syscall case
diff --git a/arch/arc/kernel/jump_label.c b/arch/arc/kernel/jump_label.c
index b8600dc325b5..70b74a5d047b 100644
--- a/arch/arc/kernel/jump_label.c
+++ b/arch/arc/kernel/jump_label.c
@@ -96,19 +96,6 @@ void arch_jump_label_transform(struct jump_entry *entry,
flush_icache_range(entry->code, entry->code + JUMP_LABEL_NOP_SIZE);
}
-void arch_jump_label_transform_static(struct jump_entry *entry,
- enum jump_label_type type)
-{
- /*
- * We use only one NOP type (1x, 4 byte) in arch_static_branch, so
- * there's no need to patch an identical NOP over the top of it here.
- * The generic code calls 'arch_jump_label_transform' if the NOP needs
- * to be replaced by a branch, so 'arch_jump_label_transform_static' is
- * never called with type other than JUMP_LABEL_NOP.
- */
- BUG_ON(type != JUMP_LABEL_NOP);
-}
-
#ifdef CONFIG_ARC_DBG_JUMP_LABEL
#define SELFTEST_MSG "ARC: instruction generation self-test: "
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 5f7f5aab361f..980b71da2f61 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -114,6 +114,8 @@ void arch_cpu_idle(void)
"sleep %0 \n"
:
:"I"(arg)); /* can't be "r" has to be embedded const */
+
+ raw_local_irq_disable();
}
#else /* ARC700 */
@@ -122,6 +124,7 @@ void arch_cpu_idle(void)
{
/* sleep, but enable both set E1/E2 (levels of interrupts) before committing */
__asm__ __volatile__("sleep 0x3 \n");
+ raw_local_irq_disable();
}
#endif
@@ -162,10 +165,11 @@ asmlinkage void ret_from_fork(void);
* | user_r25 |
* ------------------ <===== END of PAGE
*/
-int copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long kthread_arg, struct task_struct *p,
- unsigned long tls)
+int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
{
+ unsigned long clone_flags = args->flags;
+ unsigned long usp = args->stack;
+ unsigned long tls = args->tls;
struct pt_regs *c_regs; /* child's pt_regs */
unsigned long *childksp; /* to unwind out of __switch_to() */
struct callee_regs *c_callee; /* child's callee regs */
@@ -191,11 +195,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
childksp[0] = 0; /* fp */
childksp[1] = (unsigned long)ret_from_fork; /* blink */
- if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) {
+ if (unlikely(args->fn)) {
memset(c_regs, 0, sizeof(struct pt_regs));
- c_callee->r13 = kthread_arg;
- c_callee->r14 = usp; /* function */
+ c_callee->r13 = (unsigned long)args->fn_arg;
+ c_callee->r14 = (unsigned long)args->fn;
return 0;
}
diff --git a/arch/arc/kernel/ptrace.c b/arch/arc/kernel/ptrace.c
index 54b419ac8bda..2abdcd9b09e8 100644
--- a/arch/arc/kernel/ptrace.c
+++ b/arch/arc/kernel/ptrace.c
@@ -9,6 +9,92 @@
#include <linux/unistd.h>
#include <linux/elf.h>
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
+struct pt_regs_offset {
+ const char *name;
+ int offset;
+};
+
+#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+#ifdef CONFIG_ISA_ARCOMPACT
+static const struct pt_regs_offset regoffset_table[] = {
+ REG_OFFSET_NAME(bta),
+ REG_OFFSET_NAME(lp_start),
+ REG_OFFSET_NAME(lp_end),
+ REG_OFFSET_NAME(lp_count),
+ REG_OFFSET_NAME(status32),
+ REG_OFFSET_NAME(ret),
+ REG_OFFSET_NAME(blink),
+ REG_OFFSET_NAME(fp),
+ REG_OFFSET_NAME(r26),
+ REG_OFFSET_NAME(r12),
+ REG_OFFSET_NAME(r11),
+ REG_OFFSET_NAME(r10),
+ REG_OFFSET_NAME(r9),
+ REG_OFFSET_NAME(r8),
+ REG_OFFSET_NAME(r7),
+ REG_OFFSET_NAME(r6),
+ REG_OFFSET_NAME(r5),
+ REG_OFFSET_NAME(r4),
+ REG_OFFSET_NAME(r3),
+ REG_OFFSET_NAME(r2),
+ REG_OFFSET_NAME(r1),
+ REG_OFFSET_NAME(r0),
+ REG_OFFSET_NAME(sp),
+ REG_OFFSET_NAME(orig_r0),
+ REG_OFFSET_NAME(event),
+ REG_OFFSET_NAME(user_r25),
+ REG_OFFSET_END,
+};
+
+#else
+
+static const struct pt_regs_offset regoffset_table[] = {
+ REG_OFFSET_NAME(orig_r0),
+ REG_OFFSET_NAME(event),
+ REG_OFFSET_NAME(bta),
+ REG_OFFSET_NAME(user_r25),
+ REG_OFFSET_NAME(r26),
+ REG_OFFSET_NAME(fp),
+ REG_OFFSET_NAME(sp),
+ REG_OFFSET_NAME(r12),
+ REG_OFFSET_NAME(r30),
+#ifdef CONFIG_ARC_HAS_ACCL_REGS
+ REG_OFFSET_NAME(r58),
+ REG_OFFSET_NAME(r59),
+#endif
+#ifdef CONFIG_ARC_DSP_SAVE_RESTORE_REGS
+ REG_OFFSET_NAME(DSP_CTRL),
+#endif
+ REG_OFFSET_NAME(r0),
+ REG_OFFSET_NAME(r1),
+ REG_OFFSET_NAME(r2),
+ REG_OFFSET_NAME(r3),
+ REG_OFFSET_NAME(r4),
+ REG_OFFSET_NAME(r5),
+ REG_OFFSET_NAME(r6),
+ REG_OFFSET_NAME(r7),
+ REG_OFFSET_NAME(r8),
+ REG_OFFSET_NAME(r9),
+ REG_OFFSET_NAME(r10),
+ REG_OFFSET_NAME(r11),
+ REG_OFFSET_NAME(blink),
+ REG_OFFSET_NAME(lp_end),
+ REG_OFFSET_NAME(lp_start),
+ REG_OFFSET_NAME(lp_count),
+ REG_OFFSET_NAME(ei),
+ REG_OFFSET_NAME(ldi),
+ REG_OFFSET_NAME(jli),
+ REG_OFFSET_NAME(ret),
+ REG_OFFSET_NAME(status32),
+ REG_OFFSET_END,
+};
+#endif
+
static struct callee_regs *task_callee_regs(struct task_struct *tsk)
{
struct callee_regs *tmp = (struct callee_regs *)tsk->thread.callee_reg;
@@ -99,7 +185,7 @@ static int genregs_set(struct task_struct *target,
#define REG_IGNORE_ONE(LOC) \
if (!ret) \
- ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, \
+ user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, \
offsetof(struct user_regs_struct, LOC), \
offsetof(struct user_regs_struct, LOC) + 4);
@@ -257,13 +343,61 @@ long arch_ptrace(struct task_struct *child, long request,
asmlinkage int syscall_trace_entry(struct pt_regs *regs)
{
- if (ptrace_report_syscall_entry(regs))
- return ULONG_MAX;
+ if (test_thread_flag(TIF_SYSCALL_TRACE))
+ if (ptrace_report_syscall_entry(regs))
+ return ULONG_MAX;
+
+#ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
+ if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+ trace_sys_enter(regs, syscall_get_nr(current, regs));
+#endif
return regs->r8;
}
asmlinkage void syscall_trace_exit(struct pt_regs *regs)
{
- ptrace_report_syscall_exit(regs, 0);
+ if (test_thread_flag(TIF_SYSCALL_TRACE))
+ ptrace_report_syscall_exit(regs, 0);
+
+#ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
+ if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+ trace_sys_exit(regs, regs_return_value(regs));
+#endif
+}
+
+int regs_query_register_offset(const char *name)
+{
+ const struct pt_regs_offset *roff;
+
+ for (roff = regoffset_table; roff->name != NULL; roff++)
+ if (!strcmp(roff->name, name))
+ return roff->offset;
+ return -EINVAL;
+}
+
+const char *regs_query_register_name(unsigned int offset)
+{
+ const struct pt_regs_offset *roff;
+ for (roff = regoffset_table; roff->name != NULL; roff++)
+ if (roff->offset == offset)
+ return roff->name;
+ return NULL;
+}
+
+bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
+{
+ return (addr & ~(THREAD_SIZE - 1)) ==
+ (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1));
+}
+
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
+{
+ unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+
+ addr += n;
+ if (regs_within_kernel_stack(regs, (unsigned long)addr))
+ return *addr;
+ else
+ return 0;
}
diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
index f748483628f2..3c1590c27fae 100644
--- a/arch/arc/kernel/signal.c
+++ b/arch/arc/kernel/signal.c
@@ -319,7 +319,7 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
regs->ret = (unsigned long)ksig->ka.sa.sa_handler;
/*
- * handler returns using sigreturn stub provided already by userpsace
+ * handler returns using sigreturn stub provided already by userspace
* If not, nuke the process right away
*/
if(!(ksig->ka.sa.sa_flags & SA_RESTORER))
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 78e6d069b1c1..409cfa4675b4 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -35,7 +35,7 @@ EXPORT_SYMBOL_GPL(smp_atomic_ops_lock);
struct plat_smp_ops __weak plat_smp_ops;
-/* XXX: per cpu ? Only needed once in early seconday boot */
+/* XXX: per cpu ? Only needed once in early secondary boot */
struct task_struct *secondary_idle_tsk;
/* Called from start_kernel */
@@ -232,14 +232,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
return 0;
}
-/*
- * not supported here
- */
-int setup_profiling_timer(unsigned int multiplier)
-{
- return -EINVAL;
-}
-
/*****************************************************************************/
/* Inter Processor Interrupt Handling */
/*****************************************************************************/
@@ -274,7 +266,7 @@ static void ipi_send_msg_one(int cpu, enum ipi_msg_type msg)
* and read back old value
*/
do {
- new = old = READ_ONCE(*ipi_data_ptr);
+ new = old = *ipi_data_ptr;
new |= 1U << msg;
} while (cmpxchg(ipi_data_ptr, old, new) != old);
@@ -300,7 +292,7 @@ static void ipi_send_msg(const struct cpumask *callmap, enum ipi_msg_type msg)
ipi_send_msg_one(cpu, msg);
}
-void smp_send_reschedule(int cpu)
+void arch_smp_send_reschedule(int cpu)
{
ipi_send_msg_one(cpu, IPI_RESCHEDULE);
}
@@ -393,7 +385,7 @@ irqreturn_t do_IPI(int irq, void *dev_id)
* API called by platform code to hookup arch-common ISR to their IPI IRQ
*
* Note: If IPI is provided by platform (vs. say ARC MCIP), their intc setup/map
- * function needs to call call irq_set_percpu_devid() for IPI IRQ, otherwise
+ * function needs to call irq_set_percpu_devid() for IPI IRQ, otherwise
* request_percpu_irq() below will fail
*/
static DEFINE_PER_CPU(int, ipi_dev);
diff --git a/arch/arc/kernel/unaligned.c b/arch/arc/kernel/unaligned.c
index d63ebd81f1c6..99a9b92ed98d 100644
--- a/arch/arc/kernel/unaligned.c
+++ b/arch/arc/kernel/unaligned.c
@@ -237,7 +237,7 @@ int misaligned_fixup(unsigned long address, struct pt_regs *regs,
if (state.fault)
goto fault;
- /* clear any remanants of delay slot */
+ /* clear any remnants of delay slot */
if (delay_mode(regs)) {
regs->ret = regs->bta & ~1U;
regs->status32 &= ~STATUS_DE_MASK;
diff --git a/arch/arc/kernel/unwind.c b/arch/arc/kernel/unwind.c
index 200270a94558..9270d0a713c3 100644
--- a/arch/arc/kernel/unwind.c
+++ b/arch/arc/kernel/unwind.c
@@ -369,6 +369,8 @@ void *unwind_add_table(struct module *module, const void *table_start,
unsigned long table_size)
{
struct unwind_table *table;
+ struct module_memory *core_text;
+ struct module_memory *init_text;
if (table_size <= 0)
return NULL;
@@ -377,11 +379,11 @@ void *unwind_add_table(struct module *module, const void *table_start,
if (!table)
return NULL;
- init_unwind_table(table, module->name,
- module->core_layout.base, module->core_layout.size,
- module->init_layout.base, module->init_layout.size,
- table_start, table_size,
- NULL, 0);
+ core_text = &module->mem[MOD_TEXT];
+ init_text = &module->mem[MOD_INIT_TEXT];
+
+ init_unwind_table(table, module->name, core_text->base, core_text->size,
+ init_text->base, init_text->size, table_start, table_size, NULL, 0);
init_unwind_hdr(table, unw_hdr_alloc);
diff --git a/arch/arc/kernel/vmlinux.lds.S b/arch/arc/kernel/vmlinux.lds.S
index 529ae50f9fe2..549c3f407918 100644
--- a/arch/arc/kernel/vmlinux.lds.S
+++ b/arch/arc/kernel/vmlinux.lds.S
@@ -85,7 +85,6 @@ SECTIONS
_stext = .;
TEXT_TEXT
SCHED_TEXT
- CPUIDLE_TEXT
LOCK_TEXT
KPROBES_TEXT
IRQENTRY_TEXT
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 8aa1231865d1..55c6de138eae 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -401,7 +401,7 @@ static inline void __before_dc_op(const int op)
{
if (op == OP_FLUSH_N_INV) {
/* Dcache provides 2 cmd: FLUSH or INV
- * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
+ * INV in turn has sub-modes: DISCARD or FLUSH-BEFORE
* flush-n-inv is achieved by INV cmd but with IM=1
* So toggle INV sub-mode depending on op request and default
*/
@@ -750,7 +750,7 @@ static inline void arc_slc_enable(void)
* -In SMP, if hardware caches are coherent
*
* There's a corollary case, where kernel READs from a userspace mapped page.
- * If the U-mapping is not congruent to to K-mapping, former needs flushing.
+ * If the U-mapping is not congruent to K-mapping, former needs flushing.
*/
void flush_dcache_page(struct page *page)
{
@@ -910,7 +910,7 @@ EXPORT_SYMBOL(flush_icache_range);
* @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
* However in one instance, when called by kprobe (for a breakpt in
* builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
- * use a paddr to index the cache (despite VIPT). This is fine since since a
+ * use a paddr to index the cache (despite VIPT). This is fine since a
* builtin kernel page will not have any virtual mappings.
* kprobe on loadable module will be kernel vaddr.
*/
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index dad27e4d69ff..5ca59a482632 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -146,6 +146,10 @@ retry:
return;
}
+ /* The fault is fully completed (including releasing mmap lock) */
+ if (fault & VM_FAULT_COMPLETED)
+ return;
+
/*
* Fault retry nuances, mmap_lock already relinquished by core mm
*/
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index ce4e939a7f07..2b89b6c53801 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -74,11 +74,6 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
base, TO_MB(size), !in_use ? "Not used":"");
}
-bool arch_has_descending_max_zone_pfns(void)
-{
- return !IS_ENABLED(CONFIG_ARC_HAS_PAE40);
-}
-
/*
* First memory setup routine called from setup_arch()
* 1. setup swapper's mm @init_mm
diff --git a/arch/arc/mm/ioremap.c b/arch/arc/mm/ioremap.c
index 0ee75aca6e10..712c2311daef 100644
--- a/arch/arc/mm/ioremap.c
+++ b/arch/arc/mm/ioremap.c
@@ -94,7 +94,7 @@ void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
EXPORT_SYMBOL(ioremap_prot);
-void iounmap(const void __iomem *addr)
+void iounmap(const volatile void __iomem *addr)
{
/* weird double cast to handle phys_addr_t > 32 bits */
if (arc_uncached_addr_space((phys_addr_t)(u32)addr))
diff --git a/arch/arc/mm/mmap.c b/arch/arc/mm/mmap.c
index 722d26b94307..fce5fa2b4f52 100644
--- a/arch/arc/mm/mmap.c
+++ b/arch/arc/mm/mmap.c
@@ -74,3 +74,23 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
info.align_offset = pgoff << PAGE_SHIFT;
return vm_unmapped_area(&info);
}
+
+static const pgprot_t protection_map[16] = {
+ [VM_NONE] = PAGE_U_NONE,
+ [VM_READ] = PAGE_U_R,
+ [VM_WRITE] = PAGE_U_R,
+ [VM_WRITE | VM_READ] = PAGE_U_R,
+ [VM_EXEC] = PAGE_U_X_R,
+ [VM_EXEC | VM_READ] = PAGE_U_X_R,
+ [VM_EXEC | VM_WRITE] = PAGE_U_X_R,
+ [VM_EXEC | VM_WRITE | VM_READ] = PAGE_U_X_R,
+ [VM_SHARED] = PAGE_U_NONE,
+ [VM_SHARED | VM_READ] = PAGE_U_R,
+ [VM_SHARED | VM_WRITE] = PAGE_U_W_R,
+ [VM_SHARED | VM_WRITE | VM_READ] = PAGE_U_W_R,
+ [VM_SHARED | VM_EXEC] = PAGE_U_X_R,
+ [VM_SHARED | VM_EXEC | VM_READ] = PAGE_U_X_R,
+ [VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_U_X_W_R,
+ [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_U_X_W_R
+};
+DECLARE_VM_GET_PAGE_PROT
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 700655e31b04..0fb4b218f665 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -15,21 +15,20 @@ config ARM
select ARCH_HAS_MEMBARRIER_SYNC_CORE
select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
- select ARCH_HAS_PHYS_TO_DMA
select ARCH_HAS_SETUP_DMA_OPS
select ARCH_HAS_SET_MEMORY
+ select ARCH_STACKWALK
select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
select ARCH_HAS_STRICT_MODULE_RWX if MMU
- select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
- select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
+ select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
- select ARCH_HAVE_CUSTOM_GPIO_H
select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_KEEP_MEMBLOCK
+ select ARCH_HAS_UBSAN_SANITIZE_ALL
select ARCH_MIGHT_HAVE_PC_PARPORT
- select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
select ARCH_SUPPORTS_ATOMIC_RMW
@@ -43,6 +42,7 @@ config ARM
select ARCH_WANT_LD_ORPHAN_WARN
select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
select BUILDTIME_TABLE_SORT if MMU
+ select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
select CLONE_BACKWARDS
select CPU_PM if SUSPEND || CPU_IDLE
select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
@@ -69,12 +69,14 @@ config ARM
select GENERIC_SCHED_CLOCK
select GENERIC_SMP_IDLE_THREAD
select HARDIRQS_SW_RESEND
+ select HAS_IOPORT
select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
+ select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
select HAVE_ARCH_MMAP_RND_BITS if MMU
select HAVE_ARCH_PFN_VALID
select HAVE_ARCH_SECCOMP
@@ -84,7 +86,7 @@ config ARM
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
select HAVE_ARM_SMCCC if CPU_V7
select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
- select HAVE_CONTEXT_TRACKING
+ select HAVE_CONTEXT_TRACKING_USER
select HAVE_C_RECORDMCOUNT
select HAVE_BUILDTIME_MCOUNT_SORT
select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
@@ -95,6 +97,7 @@ config ARM
select HAVE_EXIT_THREAD
select HAVE_FAST_GUP if ARM_LPAE
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
+ select HAVE_FUNCTION_ERROR_INJECTION
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_TRACER if !XIP_KERNEL
select HAVE_GCC_PLUGINS
@@ -110,6 +113,7 @@ config ARM
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_NMI
select HAVE_OPTPROBES if !THUMB2_KERNEL
+ select HAVE_PCI if MMU
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
@@ -126,13 +130,17 @@ config ARM
select OF_EARLY_FLATTREE if OF
select OLD_SIGACTION
select OLD_SIGSUSPEND3
+ select PCI_DOMAINS_GENERIC if PCI
select PCI_SYSCALL if PCI
select PERF_USE_VMALLOC
select RTC_LIB
+ select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
select SYS_SUPPORTS_APM_EMULATION
select THREAD_INFO_IN_TASK
+ select TIMER_OF if OF
select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
+ select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
help
@@ -154,12 +162,8 @@ config ARM_HAS_GROUP_RELOCS
which is usually sufficient, but not for allyesconfig, so we disable
this feature when doing compile testing.
-config ARM_HAS_SG_CHAIN
- bool
-
config ARM_DMA_USE_IOMMU
bool
- select ARM_HAS_SG_CHAIN
select NEED_SG_DMA_LENGTH
if ARM_DMA_USE_IOMMU
@@ -245,7 +249,7 @@ config ARCH_MTD_XIP
config ARM_PATCH_PHYS_VIRT
bool "Patch physical to virtual translations at runtime" if EMBEDDED
default y
- depends on !XIP_KERNEL && MMU
+ depends on MMU
help
Patch phys-to-virt and virt-to-phys translation functions at
boot and module load time according to the position of the
@@ -274,12 +278,11 @@ config NEED_MACH_MEMORY_H
config PHYS_OFFSET
hex "Physical address of main memory" if MMU
- depends on !ARM_PATCH_PHYS_VIRT
+ depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
default DRAM_BASE if !MMU
default 0x00000000 if ARCH_FOOTBRIDGE
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
- default 0x30000000 if ARCH_S3C24XX
- default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
+ default 0xa0000000 if ARCH_PXA
default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
default 0
help
@@ -307,13 +310,8 @@ config MMU
config ARM_SINGLE_ARMV7M
def_bool !MMU
select ARM_NVIC
- select AUTO_ZRELADDR
- select TIMER_OF
- select COMMON_CLK
select CPU_V7M
select NO_IOPORT_MAP
- select SPARSE_IRQ
- select USE_OF
config ARCH_MMAP_RND_BITS_MIN
default 8
@@ -323,196 +321,39 @@ config ARCH_MMAP_RND_BITS_MAX
default 15 if PAGE_OFFSET=0x80000000
default 16
-#
-# The "ARM system type" choice list is ordered alphabetically by option
-# text. Please add new entries in the option alphabetic order.
-#
-choice
- prompt "ARM system type"
- depends on MMU
- default ARCH_MULTIPLATFORM
-
config ARCH_MULTIPLATFORM
- bool "Allow multiple platforms to be selected"
- select ARCH_FLATMEM_ENABLE
- select ARCH_SPARSEMEM_ENABLE
- select ARCH_SELECT_MEMORY_MODEL
- select ARM_HAS_SG_CHAIN
- select ARM_PATCH_PHYS_VIRT
- select AUTO_ZRELADDR
- select TIMER_OF
- select COMMON_CLK
- select HAVE_PCI
- select PCI_DOMAINS_GENERIC if PCI
- select SPARSE_IRQ
- select USE_OF
-
-config ARCH_EP93XX
- bool "EP93xx-based"
- select ARCH_SPARSEMEM_ENABLE
- select ARM_AMBA
- imply ARM_PATCH_PHYS_VIRT
- select ARM_VIC
- select AUTO_ZRELADDR
- select CLKSRC_MMIO
- select CPU_ARM920T
- select GPIOLIB
- select COMMON_CLK
- help
- This enables support for the Cirrus EP93xx series of CPUs.
-
-config ARCH_FOOTBRIDGE
- bool "FootBridge"
- select CPU_SA110
- select FOOTBRIDGE
- select NEED_MACH_MEMORY_H
- help
- Support for systems based on the DC21285 companion chip
- ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
-
-config ARCH_IOP32X
- bool "IOP32x-based"
- select CPU_XSCALE
- select GPIO_IOP
- select GPIOLIB
- select FORCE_PCI
- select PLAT_IOP
- help
- Support for Intel's 80219 and IOP32X (XScale) family of
- processors.
-
-config ARCH_IXP4XX
- bool "IXP4xx-based"
- select ARCH_SUPPORTS_BIG_ENDIAN
- select ARM_PATCH_PHYS_VIRT
- select CPU_XSCALE
- select GPIO_IXP4XX
- select GPIOLIB
- select HAVE_PCI
- select IXP4XX_IRQ
- select IXP4XX_TIMER
- select SPARSE_IRQ
- select USB_EHCI_BIG_ENDIAN_DESC
- select USB_EHCI_BIG_ENDIAN_MMIO
- help
- Support for Intel's IXP4XX (XScale) family of processors.
-
-config ARCH_DOVE
- bool "Marvell Dove"
- select CPU_PJ4
- select GPIOLIB
- select HAVE_PCI
- select MVEBU_MBUS
- select PINCTRL
- select PINCTRL_DOVE
- select PLAT_ORION_LEGACY
- select SPARSE_IRQ
- select PM_GENERIC_DOMAINS if PM
- help
- Support for the Marvell Dove SoC 88AP510
-
-config ARCH_PXA
- bool "PXA2xx/PXA3xx-based"
- select ARCH_MTD_XIP
- select ARM_CPU_SUSPEND if PM
- select AUTO_ZRELADDR
- select COMMON_CLK
- select CLKSRC_PXA
- select CLKSRC_MMIO
- select TIMER_OF
- select CPU_XSCALE if !CPU_XSC3
- select GPIO_PXA
- select GPIOLIB
- select IRQ_DOMAIN
- select PLAT_PXA
- select SPARSE_IRQ
- help
- Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
-
-config ARCH_RPC
- bool "RiscPC"
- depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
- select ARCH_ACORN
- select ARCH_MAY_HAVE_PC_FDC
- select ARCH_SPARSEMEM_ENABLE
- select ARM_HAS_SG_CHAIN
- select CPU_SA110
- select FIQ
- select HAVE_PATA_PLATFORM
- select ISA_DMA_API
- select LEGACY_TIMER_TICK
- select NEED_MACH_IO_H
- select NEED_MACH_MEMORY_H
- select NO_IOPORT_MAP
+ bool "Require kernel to be portable to multiple machines" if EXPERT
+ depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
+ default y
help
- On the Acorn Risc-PC, Linux can support the internal IDE disk and
- CD-ROM interface, serial and parallel port, and the floppy drive.
+ In general, all Arm machines can be supported in a single
+ kernel image, covering either Armv4/v5 or Armv6/v7.
-config ARCH_SA1100
- bool "SA1100-based"
- select ARCH_MTD_XIP
- select ARCH_SPARSEMEM_ENABLE
- select CLKSRC_MMIO
- select CLKSRC_PXA
- select TIMER_OF if OF
- select COMMON_CLK
- select CPU_FREQ
- select CPU_SA1100
- select GPIOLIB
- select IRQ_DOMAIN
- select ISA
- select NEED_MACH_MEMORY_H
- select SPARSE_IRQ
- help
- Support for StrongARM 11x0 based boards.
-
-config ARCH_S3C24XX
- bool "Samsung S3C24XX SoCs"
- select ATAGS
- select CLKSRC_SAMSUNG_PWM
- select GPIO_SAMSUNG
- select GPIOLIB
- select NEED_MACH_IO_H
- select S3C2410_WATCHDOG
- select SAMSUNG_ATAGS
- select USE_OF
- select WATCHDOG
- help
- Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
- and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
- (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
- Samsung SMDK2410 development board (and derivatives).
-
-config ARCH_OMAP1
- bool "TI OMAP1"
- select ARCH_OMAP
- select CLKSRC_MMIO
- select GENERIC_IRQ_CHIP
- select GPIOLIB
- select HAVE_LEGACY_CLK
- select IRQ_DOMAIN
- select NEED_MACH_IO_H if PCCARD
- select NEED_MACH_MEMORY_H
- select SPARSE_IRQ
- help
- Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
+ However, some configuration options require hardcoding machine
+ specific physical addresses or enable errata workarounds that may
+ break other machines.
-endchoice
+ Selecting N here allows using those options, including
+ DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
-menu "Multiple platform selection"
- depends on ARCH_MULTIPLATFORM
+menu "Platform selection"
+ depends on MMU
comment "CPU Core family selection"
config ARCH_MULTI_V4
- bool "ARMv4 based platforms (FA526)"
+ bool "ARMv4 based platforms (FA526, StrongARM)"
depends on !ARCH_MULTI_V6_V7
+ # https://github.com/llvm/llvm-project/issues/50764
+ depends on !LD_IS_LLD || LLD_VERSION >= 160000
select ARCH_MULTI_V4_V5
- select CPU_FA526
+ select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
config ARCH_MULTI_V4T
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
depends on !ARCH_MULTI_V6_V7
+ # https://github.com/llvm/llvm-project/issues/50764
+ depends on !LD_IS_LLD || LLD_VERSION >= 160000
select ARCH_MULTI_V4_V5
select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
@@ -561,7 +402,6 @@ config ARCH_VIRT
select ARM_GIC_V3_ITS if PCI
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
- select ARCH_SUPPORTS_BIG_ENDIAN
config ARCH_AIROHA
bool "Airoha SoC Support"
@@ -571,7 +411,6 @@ config ARCH_AIROHA
select ARM_GIC_V3
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
- select COMMON_CLK
help
Support for Airoha EN7523 SoCs
@@ -600,8 +439,6 @@ source "arch/arm/mach-berlin/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
-source "arch/arm/mach-cns3xxx/Kconfig"
-
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-digicolor/Kconfig"
@@ -620,11 +457,9 @@ source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-hisi/Kconfig"
-source "arch/arm/mach-imx/Kconfig"
-
-source "arch/arm/mach-integrator/Kconfig"
+source "arch/arm/mach-hpe/Kconfig"
-source "arch/arm/mach-iop32x/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
@@ -662,10 +497,7 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
-source "arch/arm/mach-oxnas/Kconfig"
-
source "arch/arm/mach-pxa/Kconfig"
-source "arch/arm/plat-pxa/Kconfig"
source "arch/arm/mach-qcom/Kconfig"
@@ -673,7 +505,7 @@ source "arch/arm/mach-rda/Kconfig"
source "arch/arm/mach-realtek/Kconfig"
-source "arch/arm/mach-realview/Kconfig"
+source "arch/arm/mach-rpc/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
@@ -693,6 +525,8 @@ source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
+source "arch/arm/mach-sunplus/Kconfig"
+
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
@@ -703,8 +537,6 @@ source "arch/arm/mach-ux500/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
-source "arch/arm/mach-vexpress/Kconfig"
-
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
@@ -737,13 +569,9 @@ config ARCH_MPS2
config ARCH_ACORN
bool
-config PLAT_IOP
- bool
-
config PLAT_ORION
bool
select CLKSRC_MMIO
- select COMMON_CLK
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
@@ -751,9 +579,6 @@ config PLAT_ORION_LEGACY
bool
select PLAT_ORION
-config PLAT_PXA
- bool
-
config PLAT_VERSATILE
bool
@@ -831,7 +656,9 @@ config ARM_ERRATA_458693
hazard might then cause a processor deadlock. The workaround enables
the L1 caching of the NEON accesses and disables the PLD instruction
in the ACTLR register. Note that setting specific bits in the ACTLR
- register may not be available in non-secure mode.
+ register may not be available in non-secure mode and thus is not
+ available on a multiplatform kernel. This should be applied by the
+ bootloader instead.
config ARM_ERRATA_460075
bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
@@ -844,7 +671,9 @@ config ARM_ERRATA_460075
and overwritten with stale memory contents from external memory. The
workaround disables the write-allocate mode for the L2 cache via the
ACTLR register. Note that setting specific bits in the ACTLR register
- may not be available in non-secure mode.
+ may not be available in non-secure mode and thus is not available on
+ a multiplatform kernel. This should be applied by the bootloader
+ instead.
config ARM_ERRATA_742230
bool "ARM errata: DMB operation may be faulty"
@@ -857,7 +686,10 @@ config ARM_ERRATA_742230
ordering of the two writes. This workaround sets a specific bit in
the diagnostic register of the Cortex-A9 which causes the DMB
instruction to behave as a DSB, ensuring the correct behaviour of
- the two writes.
+ the two writes. Note that setting specific bits in the diagnostics
+ register may not be available in non-secure mode and thus is not
+ available on a multiplatform kernel. This should be applied by the
+ bootloader instead.
config ARM_ERRATA_742231
bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
@@ -872,7 +704,10 @@ config ARM_ERRATA_742231
replaced from one of the CPUs at the same time as another CPU is
accessing it. This workaround sets specific bits in the diagnostic
register of the Cortex-A9 which reduces the linefill issuing
- capabilities of the processor.
+ capabilities of the processor. Note that setting specific bits in the
+ diagnostics register may not be available in non-secure mode and thus
+ is not available on a multiplatform kernel. This should be applied by
+ the bootloader instead.
config ARM_ERRATA_643719
bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
@@ -909,7 +744,9 @@ config ARM_ERRATA_743622
register of the Cortex-A9 which disables the Store Buffer
optimisation, preventing the defect from occurring. This has no
visible impact on the overall performance or power consumption of the
- processor.
+ processor. Note that setting specific bits in the diagnostics register
+ may not be available in non-secure mode and thus is not available on a
+ multiplatform kernel. This should be applied by the bootloader instead.
config ARM_ERRATA_751472
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
@@ -921,6 +758,10 @@ config ARM_ERRATA_751472
completion of a following broadcasted operation if the second
operation is received by a CPU before the ICIALLUIS has completed,
potentially leading to corrupted entries in the cache or TLB.
+ Note that setting specific bits in the diagnostics register may
+ not be available in non-secure mode and thus is not available on
+ a multiplatform kernel. This should be applied by the bootloader
+ instead.
config ARM_ERRATA_754322
bool "ARM errata: possible faulty MMU translations following an ASID switch"
@@ -970,6 +811,17 @@ config ARM_ERRATA_764369
relevant cache maintenance functions and sets a specific bit
in the diagnostic control register of the SCU.
+config ARM_ERRATA_764319
+ bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 764319 Cortex A-9 erratum.
+ CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
+ unexpected Undefined Instruction exception when the DBGSWENABLE
+ external pin is set to 0, even when the CP14 accesses are performed
+ from a privileged mode. This work around catches the exception in a
+ way the kernel does not stop execution.
+
config ARM_ERRATA_775420
bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
depends on CPU_V7
@@ -1086,21 +938,10 @@ config ISA
(MCA) or VESA. ISA is an older system, now being displaced by PCI;
newer boards don't support it. If you have ISA, say Y, otherwise N.
-# Select ISA DMA controller support
-config ISA_DMA
- bool
- select ISA_DMA_API
-
# Select ISA DMA interface
config ISA_DMA_API
bool
-config PCI_NANOENGINE
- bool "BSE nanoEngine PCI support"
- depends on SA1100_NANOENGINE
- help
- Enable PCI on the BSE nanoEngine board.
-
config ARM_ERRATA_814220
bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
depends on CPU_V7
@@ -1143,7 +984,7 @@ config SMP
uniprocessor machines. On a uniprocessor machine, the kernel
will run faster if you say N here.
- See also <file:Documentation/x86/i386/IO-APIC.rst>,
+ See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
<file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
<http://tldp.org/HOWTO/SMP-HOWTO.html>.
@@ -1151,7 +992,7 @@ config SMP
config SMP_ON_UP
bool "Allow booting SMP kernel on uniprocessor systems"
- depends on SMP && !XIP_KERNEL && MMU
+ depends on SMP && MMU
default y
help
SMP kernels contain instructions which fail on non-SMP processors.
@@ -1324,27 +1165,6 @@ config ARM_PSCI
0022A ("Power State Coordination Interface System Software on
ARM processors").
-# The GPIO number here must be sorted by descending number. In case of
-# a multiplatform kernel, we just want the highest value required by the
-# selected platforms.
-config ARCH_NR_GPIO
- int
- default 2048 if ARCH_INTEL_SOCFPGA
- default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
- ARCH_ZYNQ || ARCH_ASPEED
- default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
- SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
- default 416 if ARCH_SUNXI
- default 392 if ARCH_U8500
- default 352 if ARCH_VT8500
- default 288 if ARCH_ROCKCHIP
- default 264 if MACH_H4700
- default 0
- help
- Maximum number of GPIOs in the system.
-
- If unsure, leave the default value.
-
config HZ_FIXED
int
default 128 if SOC_AT91RM9200
@@ -1400,7 +1220,7 @@ config THUMB2_KERNEL
config ARM_PATCH_IDIV
bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
- depends on CPU_32v7 && !XIP_KERNEL
+ depends on CPU_32v7
default y
help
The ARM compiler inserts calls to __aeabi_idiv() and
@@ -1455,13 +1275,13 @@ config OABI_COMPAT
at all). If in doubt say N.
config ARCH_SELECT_MEMORY_MODEL
- bool
+ def_bool y
config ARCH_FLATMEM_ENABLE
- bool
+ def_bool !(ARCH_RPC || ARCH_SA1100)
config ARCH_SPARSEMEM_ENABLE
- bool
+ def_bool !ARCH_FOOTBRIDGE
select SPARSEMEM_STATIC if SPARSEMEM
config HIGHMEM
@@ -1516,6 +1336,7 @@ config HW_PERF_EVENTS
config ARM_MODULE_PLTS
bool "Use PLTs to allow module memory to spill over into vmalloc area"
depends on MODULES
+ select KASAN_VMALLOC if KASAN
default y
help
Allocate PLTs when loading modules so that jumps and calls whose
@@ -1530,21 +1351,20 @@ config ARM_MODULE_PLTS
Disabling this is usually safe for small single-platform
configurations. If unsure, say y.
-config FORCE_MAX_ZONEORDER
- int "Maximum zone order"
- default "12" if SOC_AM33XX
- default "9" if SA1111
- default "11"
+config ARCH_FORCE_MAX_ORDER
+ int "Order of maximal physically contiguous allocations"
+ default "11" if SOC_AM33XX
+ default "8" if SA1111
+ default "10"
help
- The kernel memory allocator divides physically contiguous memory
- blocks into "zones", where each zone is a power of two number of
- pages. This option selects the largest power of two that the kernel
- keeps in the memory allocator. If you need to allocate very large
- blocks of physically contiguous memory, then you may need to
- increase this value.
+ The kernel page allocator limits the size of maximal physically
+ contiguous allocations. The limit is called MAX_ORDER and it
+ defines the maximal power of two of number of pages that can be
+ allocated as a single contiguous block. This option allows
+ overriding the default setting when ability to allocate very
+ large blocks of physically contiguous memory is required.
- This config option is actually maximum order plus one. For example,
- a value of 11 means that the largest free memory block is 2^10 pages.
+ Don't change if unsure.
config ALIGNMENT_TRAP
def_bool CPU_CP15_MMU
@@ -1641,14 +1461,13 @@ config USE_OF
Include support for flattened device tree machine descriptions.
config ATAGS
- bool "Support for the traditional ATAGS boot data passing" if USE_OF
+ bool "Support for the traditional ATAGS boot data passing"
default y
help
This is the traditional way of passing data to the kernel at boot
time. If you are solely relying on the flattened device tree (or
the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
- to remove ATAGS support from your kernel binary. If unsure,
- leave this to y.
+ to remove ATAGS support from your kernel binary.
config DEPRECATED_PARAM_STRUCT
bool "Provide old way to pass kernel parameters"
@@ -1755,7 +1574,6 @@ config CMDLINE
choice
prompt "Kernel command line type" if CMDLINE != ""
default CMDLINE_FROM_BOOTLOADER
- depends on ATAGS
config CMDLINE_FROM_BOOTLOADER
bool "Use bootloader kernel arguments if available"
@@ -1782,6 +1600,7 @@ endchoice
config XIP_KERNEL
bool "Kernel Execute-In-Place from ROM"
depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
+ depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
help
Execute-In-Place allows the kernel to run from non-volatile storage
directly addressable by the CPU, such as NOR flash. This saves RAM
@@ -1856,7 +1675,8 @@ config CRASH_DUMP
For more details see Documentation/admin-guide/kdump/kdump.rst
config AUTO_ZRELADDR
- bool "Auto calculation of the decompressed kernel image address"
+ bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
+ default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
@@ -2005,8 +1825,4 @@ config ARCH_HIBERNATION_POSSIBLE
endmenu
-if CRYPTO
-source "arch/arm/crypto/Kconfig"
-endif
-
source "arch/arm/Kconfig.assembler"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index dbc111e1f4e2..b407b7b9b715 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -210,6 +210,26 @@ choice
Say Y here if you want kernel low-level debugging support
on the FLEXCOM3 port of SAMA7G5.
+ config DEBUG_AT91_LAN966_FLEXCOM
+ bool "Kernel low-level debugging on LAN966 FLEXCOM USART"
+ select DEBUG_AT91_UART
+ depends on SOC_LAN966
+ help
+ Say Y here if you want kernel low-level debugging support
+ on the FLEXCOM port of LAN966.
+
+ DEBUG_UART_PHYS | DEBUG_UART_VIRT
+
+ 0xe0040200 | 0xfd040200 | FLEXCOM0
+ 0xe0044200 | 0xfd044200 | FLEXCOM1
+ 0xe0060200 | 0xfd060200 | FLEXCOM2
+ 0xe0064200 | 0xfd064200 | FLEXCOM3
+ 0xe0070200 | 0xfd070200 | FLEXCOM4
+
+ By default, enabling FLEXCOM3 port. Based on requirement, use
+ DEBUG_UART_PHYS and DEBUG_UART_VIRT configurations from above
+ table.
+
config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART"
depends on ARCH_BCM2835 && ARCH_MULTI_V6
@@ -251,7 +271,7 @@ choice
config DEBUG_BCM63XX_UART
bool "Kernel low-level debugging on BCM63XX UART"
- depends on ARCH_BCM_63XX
+ depends on ARCH_BCMBCA
config DEBUG_BERLIN_UART
bool "Marvell Berlin SoC Debug UART"
@@ -287,14 +307,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to the second serial port on these devices.
- config DEBUG_CNS3XXX
- bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
- depends on ARCH_CNS3XXX
- select DEBUG_UART_8250
- help
- Say Y here if you want the debug print routines to direct
- their output to the CNS3xxx UART0.
-
config DEBUG_DAVINCI_DA8XX_UART1
bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
depends on ARCH_DAVINCI_DA8XX
@@ -311,14 +323,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART2 serial port on DaVinci DA8XX devices.
- config DEBUG_DAVINCI_DMx_UART0
- bool "Kernel low-level debugging on DaVinci DMx using UART0"
- depends on ARCH_DAVINCI_DMx
- select DEBUG_UART_8250
- help
- Say Y here if you want the debug print routines to direct
- their output to UART0 serial port on DaVinci DMx devices.
-
config DEBUG_DC21285_PORT
bool "Kernel low-level debugging messages via footbridge serial port"
depends on FOOTBRIDGE
@@ -748,30 +752,6 @@ choice
depends on ARCH_OMAP2PLUS
select DEBUG_UART_8250
- config DEBUG_OMAP7XXUART1
- bool "Kernel low-level debugging via OMAP730 UART1"
- depends on ARCH_OMAP730
- select DEBUG_UART_8250
- help
- Say Y here if you want kernel low-level debugging support
- on OMAP730 based platforms on the UART1.
-
- config DEBUG_OMAP7XXUART2
- bool "Kernel low-level debugging via OMAP730 UART2"
- depends on ARCH_OMAP730
- select DEBUG_UART_8250
- help
- Say Y here if you want kernel low-level debugging support
- on OMAP730 based platforms on the UART2.
-
- config DEBUG_OMAP7XXUART3
- bool "Kernel low-level debugging via OMAP730 UART3"
- depends on ARCH_OMAP730
- select DEBUG_UART_8250
- help
- Say Y here if you want kernel low-level debugging support
- on OMAP730 based platforms on the UART3.
-
config DEBUG_TI81XXUART1
bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)"
depends on ARCH_OMAP2PLUS
@@ -1026,7 +1006,6 @@ choice
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
- select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 0 for low-level debug"
@@ -1038,7 +1017,6 @@ choice
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
- select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 1 for low-level debug"
@@ -1050,7 +1028,6 @@ choice
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
- select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 2 for low-level debug"
@@ -1070,33 +1047,6 @@ choice
their output to UART 3. The port must have been initialised
by the boot-loader before use.
- config DEBUG_S3C2410_UART0
- depends on ARCH_S3C24XX
- select DEBUG_S3C2410_UART
- bool "Use S3C2410/S3C2412 UART 0 for low-level debug"
- help
- Say Y here if you want the debug print routines to direct
- their output to UART 0. The port must have been initialised
- by the boot-loader before use.
-
- config DEBUG_S3C2410_UART1
- depends on ARCH_S3C24XX
- select DEBUG_S3C2410_UART
- bool "Use S3C2410/S3C2412 UART 1 for low-level debug"
- help
- Say Y here if you want the debug print routines to direct
- their output to UART 1. The port must have been initialised
- by the boot-loader before use.
-
- config DEBUG_S3C2410_UART2
- depends on ARCH_S3C24XX
- select DEBUG_S3C2410_UART
- bool "Use S3C2410/S3C2412 UART 2 for low-level debug"
- help
- Say Y here if you want the debug print routines to direct
- their output to UART 2. The port must have been initialised
- by the boot-loader before use.
-
config DEBUG_SA1100
depends on ARCH_SA1100
bool "Use SA1100 UARTs for low-level debug"
@@ -1256,8 +1206,8 @@ choice
depends on MACH_STM32MP157
select DEBUG_STM32_UART
help
- Say Y here if you want kernel low-level debugging support
- on STM32MP1 based platforms, wich default UART is wired on
+ Say Y here if you want kernel low-level debugging support on
+ STM32MP1-based platforms, where the default UART is wired to
UART4, but another UART instance can be selected by modifying
CONFIG_DEBUG_UART_PHYS and CONFIG_DEBUG_UART_VIRT.
@@ -1459,13 +1409,6 @@ config DEBUG_AT91_UART
config DEBUG_EXYNOS_UART
bool
-config DEBUG_S3C2410_UART
- bool
- select DEBUG_S3C24XX_UART
-
-config DEBUG_S3C24XX_UART
- bool
-
config DEBUG_S3C64XX_UART
bool
@@ -1473,8 +1416,7 @@ config DEBUG_S5PV210_UART
bool
config DEBUG_S3C_UART
- depends on DEBUG_S3C2410_UART || DEBUG_S3C24XX_UART || \
- DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \
+ depends on DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \
DEBUG_EXYNOS_UART
int
default "0" if DEBUG_S3C_UART0
@@ -1575,7 +1517,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
- default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART
+ default "debug/s3c24xx.S" if DEBUG_S3C64XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sti.S" if DEBUG_STIH41X_ASC2
default "debug/sti.S" if DEBUG_STIH41X_SBC_ASC1
@@ -1598,11 +1540,10 @@ config DEBUG_UART_PL01X
# Compatibility options for 8250
config DEBUG_UART_8250
- def_bool ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC
+ def_bool ARCH_IXP4XX || ARCH_RPC
config DEBUG_UART_PHYS
hex "Physical base address of debug UART"
- default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
default 0x01c28000 if DEBUG_SUNXI_UART0
default 0x01c28400 if DEBUG_SUNXI_UART1
default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1
@@ -1659,13 +1600,6 @@ config DEBUG_UART_PHYS
default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
default 0x49020000 if DEBUG_OMAP3UART3
default 0x49042000 if DEBUG_OMAP3UART4
- default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
- DEBUG_S3C2410_UART0)
- default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
- DEBUG_S3C2410_UART1)
- default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
- DEBUG_S3C2410_UART2)
- default 0x78000000 if DEBUG_CNS3XXX
default 0x7c0003f8 if DEBUG_FOOTBRIDGE_COM1
default 0x7f005000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0
default 0x7f005400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1
@@ -1685,6 +1619,7 @@ config DEBUG_UART_PHYS
default 0xd4017000 if DEBUG_MMP_UART2
default 0xd4018000 if DEBUG_MMP_UART3
default 0xe0000000 if DEBUG_SPEAR13XX
+ default 0xe0064200 if DEBUG_AT91_LAN966_FLEXCOM
default 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3
default 0xe4007000 if DEBUG_HIP04_UART
default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0
@@ -1708,7 +1643,6 @@ config DEBUG_UART_PHYS
default 0xfcb00000 if DEBUG_HI3620_UART
default 0xfd883000 if DEBUG_ALPINE_UART0
default 0xfe531000 if DEBUG_STIH41X_SBC_ASC1
- default 0xfe800000 if ARCH_IOP32X
default 0xfed32000 if DEBUG_STIH41X_ASC2
default 0xff690000 if DEBUG_RK32_UART2
default 0xffc02000 if DEBUG_SOCFPGA_UART0
@@ -1717,9 +1651,9 @@ config DEBUG_UART_PHYS
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
default 0xfff36000 if DEBUG_HIGHBANK_UART
- default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
- default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
- default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
+ default 0xfffb0000 if DEBUG_OMAP1UART1
+ default 0xfffb0800 if DEBUG_OMAP1UART2
+ default 0xfffb9800 if DEBUG_OMAP1UART3
default 0xfffe8600 if DEBUG_BCM63XX_UART
default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU
default 0xfffff200 if DEBUG_AT91_RM9200_DBGU
@@ -1733,7 +1667,7 @@ config DEBUG_UART_PHYS
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RCAR_GEN2_SCIFA2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
- DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
+ DEBUG_RMOBILE_SCIFA4 || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_DIGICOLOR_UA0 || \
@@ -1770,15 +1704,9 @@ config DEBUG_UART_VIRT
default 0xf6200000 if DEBUG_PXA_UART1
default 0xf7000000 if DEBUG_SUN9I_UART0
default 0xf7000000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0
- default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
- DEBUG_S3C2410_UART0)
default 0xf7000400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1
default 0xf7000800 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART2
default 0xf7000c00 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART3
- default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
- DEBUG_S3C2410_UART1)
- default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
- DEBUG_S3C2410_UART2)
default 0xf7020000 if DEBUG_AT91_SAMA5D2_UART1
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8007000 if DEBUG_HIP04_UART
@@ -1797,7 +1725,6 @@ config DEBUG_UART_VIRT
DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2
default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
default 0xfa71e000 if DEBUG_QCOM_UARTDM
- default 0xfb002000 if DEBUG_CNS3XXX
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3
default 0xfb020000 if DEBUG_OMAP3UART3
@@ -1805,6 +1732,7 @@ config DEBUG_UART_VIRT
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfcfe8600 if DEBUG_BCM63XX_UART
default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX
+ default 0xfd064200 if DEBUG_AT91_LAN966_FLEXCOM
default 0xfd531000 if DEBUG_STIH41X_SBC_ASC1
default 0xfd883000 if DEBUG_ALPINE_UART0
default 0xfdd32000 if DEBUG_STIH41X_ASC2
@@ -1813,7 +1741,6 @@ config DEBUG_UART_VIRT
default 0xfe018000 if DEBUG_MMP_UART3
default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default 0xfe300000 if DEBUG_BCM_KONA_UART
- default 0xfe800000 if ARCH_IOP32X
default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
default 0xfeb24000 if DEBUG_RK3X_UART0
default 0xfeb26000 if DEBUG_RK3X_UART1
@@ -1824,7 +1751,6 @@ config DEBUG_UART_VIRT
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
- default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
@@ -1837,14 +1763,14 @@ config DEBUG_UART_VIRT
default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfef36000 if DEBUG_HIGHBANK_UART
- default 0xff0b0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
- default 0xff0b0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
- default 0xff0b9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
+ default 0xff0b0000 if DEBUG_OMAP1UART1
+ default 0xff0b0800 if DEBUG_OMAP1UART2
+ default 0xff0b9800 if DEBUG_OMAP1UART3
default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
- DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
+ DEBUG_QCOM_UARTDM || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_DIGICOLOR_UA0 || \
@@ -1855,9 +1781,8 @@ config DEBUG_UART_VIRT
config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
- default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \
- DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \
- DEBUG_OMAP7XXUART3
+ default 0 if DEBUG_FOOTBRIDGE_COM1 || DEBUG_BCM_5301X || \
+ DEBUG_BCM_HR2
default 3 if DEBUG_MSTARV7_PMUART
default 2
@@ -1868,9 +1793,9 @@ config DEBUG_UART_8250_WORD
default y if DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
- DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
- DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \
- DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
+ DEBUG_DAVINCI_DA8XX_UART1 || DEBUG_DAVINCI_DA8XX_UART2 || \
+ DEBUG_BCM_IPROC_UART3 || DEBUG_BCM_KONA_UART || \
+ DEBUG_RK32_UART2
config DEBUG_UART_8250_PALMCHIP
bool "8250 UART is Palmchip BK-310x"
@@ -1882,7 +1807,8 @@ config DEBUG_UART_8250_PALMCHIP
config DEBUG_UNCOMPRESS
bool "Enable decompressor debugging via DEBUG_LL output"
- depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG || ARM_SINGLE_ARMV7M
+ depends on !ARCH_MULTIPLATFORM
+ depends on !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
depends on DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
!DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
@@ -1899,9 +1825,8 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
- default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
- PLAT_SAMSUNG || ARM_SINGLE_ARMV7M
- default "mach/uncompress.h"
+ default "mach/uncompress.h" if ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100
+ default "debug/uncompress.h"
config EARLY_PRINTK
bool "Early printk"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7bcf59d0d315..547e5856eaa0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -22,6 +22,9 @@ GZFLAGS :=-9
# Never generate .eh_frame
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
+# Disable FDPIC ABI
+KBUILD_CFLAGS += $(call cc-option,-mno-fdpic)
+
# This should work on most of the modern platforms
KBUILD_DEFCONFIG := multi_v7_defconfig
@@ -57,47 +60,54 @@ endif
KBUILD_CFLAGS += $(call cc-option,-fno-ipa-sra)
# This selects which instruction set is used.
+arch-$(CONFIG_CPU_32v7M) :=-march=armv7-m
+arch-$(CONFIG_CPU_32v7) :=-march=armv7-a
+arch-$(CONFIG_CPU_32v6) :=-march=armv6
+# Only override the compiler option if ARMv6. The ARMv6K extensions are
+# always available in ARMv7
+ifeq ($(CONFIG_CPU_32v6),y)
+arch-$(CONFIG_CPU_32v6K) :=-march=armv6k
+endif
+arch-$(CONFIG_CPU_32v5) :=-march=armv5te
+arch-$(CONFIG_CPU_32v4T) :=-march=armv4t
+arch-$(CONFIG_CPU_32v4) :=-march=armv4
+arch-$(CONFIG_CPU_32v3) :=-march=armv3m
+
# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m
-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a
-arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6
+cpp-$(CONFIG_CPU_32v7M) :=-D__LINUX_ARM_ARCH__=7
+cpp-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7
+cpp-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7
ifeq ($(CONFIG_CPU_32v6),y)
-arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 -march=armv6k
+cpp-$(CONFIG_CPU_32v6K) :=-D__LINUX_ARM_ARCH__=6
endif
-arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 -march=armv5te
-arch-$(CONFIG_CPU_32v4T) =-D__LINUX_ARM_ARCH__=4 -march=armv4t
-arch-$(CONFIG_CPU_32v4) =-D__LINUX_ARM_ARCH__=4 -march=armv4
-arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3m
-
-# Evaluate arch cc-option calls now
-arch-y := $(arch-y)
+cpp-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5
+cpp-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4
+cpp-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4
+cpp-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3
# This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM7TDMI) =-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM740T) =-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM9TDMI) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM940T) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM946E) =-mtune=arm9e
-tune-$(CONFIG_CPU_ARM920T) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM922T) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM925T) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM926T) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_FA526) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_SA110) =-mtune=strongarm110
-tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
-tune-$(CONFIG_CPU_XSCALE) =-mtune=xscale
-tune-$(CONFIG_CPU_XSC3) =-mtune=xscale
-tune-$(CONFIG_CPU_FEROCEON) =-mtune=xscale
-tune-$(CONFIG_CPU_V6) =-mtune=arm1136j-s
-tune-$(CONFIG_CPU_V6K) =-mtune=arm1136j-s
-
-# Evaluate tune cc-option calls now
-tune-y := $(tune-y)
+tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM946E) :=-mtune=arm9e
+tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_FA526) :=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
+tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
+tune-$(CONFIG_CPU_XSCALE) :=-mtune=xscale
+tune-$(CONFIG_CPU_XSC3) :=-mtune=xscale
+tune-$(CONFIG_CPU_FEROCEON) :=-mtune=xscale
+tune-$(CONFIG_CPU_V6) :=-mtune=arm1136j-s
+tune-$(CONFIG_CPU_V6K) :=-mtune=arm1136j-s
ifeq ($(CONFIG_AEABI),y)
CFLAGS_ABI :=-mabi=aapcs-linux -mfpu=vfp
@@ -114,37 +124,34 @@ CFLAGS_ABI += -meabi gnu
endif
ifeq ($(CONFIG_CURRENT_POINTER_IN_TPIDRURO),y)
-CFLAGS_ABI += -mtp=cp15
+KBUILD_CFLAGS += -mtp=cp15
endif
# Accept old syntax despite ".syntax unified"
AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
ifeq ($(CONFIG_THUMB2_KERNEL),y)
-CFLAGS_ISA :=-mthumb -Wa,-mimplicit-it=always $(AFLAGS_NOWARN)
+CFLAGS_ISA :=-Wa,-mimplicit-it=always $(AFLAGS_NOWARN)
AFLAGS_ISA :=$(CFLAGS_ISA) -Wa$(comma)-mthumb
+CFLAGS_ISA +=-mthumb
else
CFLAGS_ISA :=$(call cc-option,-marm,) $(AFLAGS_NOWARN)
AFLAGS_ISA :=$(CFLAGS_ISA)
endif
# Need -Uarm for gcc < 3.x
+KBUILD_CPPFLAGS +=$(cpp-y)
KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
-KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
+KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) -Wa,$(arch-y) $(tune-y) -include asm/unified.h -msoft-float
CHECKFLAGS += -D__arm__
-#Default value
-head-y := arch/arm/kernel/head$(MMUEXT).o
-
# Text offset. This list is sorted numerically by address in order to
# provide a means to avoid/resolve conflicts in multi-arch kernels.
# Note: the 32kB below this value is reserved for use by the kernel
# during boot, and this offset is critical to the functioning of
# kexec-tools.
textofs-y := 0x00008000
-# We don't want the htc bootloader to corrupt kernel during resume
-textofs-$(CONFIG_PM_H1940) := 0x00108000
# RTD1195 has Boot ROM at start of address space
textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
@@ -169,7 +176,6 @@ machine-$(CONFIG_ARCH_AXXIA) += axxia
machine-$(CONFIG_ARCH_BCM) += bcm
machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
-machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
machine-$(CONFIG_ARCH_DOVE) += dove
@@ -179,15 +185,13 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
-machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
-machine-$(CONFIG_ARCH_IOP32X) += iop32x
+machine-$(CONFIG_ARCH_HPE) += hpe
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
-machine-$(CONFIG_ARCH_MPS2) += vexpress
machine-$(CONFIG_ARCH_MOXART) += moxart
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
@@ -199,15 +203,12 @@ machine-$(CONFIG_ARCH_MSTARV7) += mstar
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_NSPIRE) += nspire
-machine-$(CONFIG_ARCH_OXNAS) += oxnas
machine-$(CONFIG_ARCH_OMAP1) += omap1
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_QCOM) += qcom
-machine-$(CONFIG_ARCH_RDA) += rda
machine-$(CONFIG_ARCH_REALTEK) += realtek
-machine-$(CONFIG_ARCH_REALVIEW) += realview
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_RPC) += rpc
machine-$(CONFIG_PLAT_SAMSUNG) += s3c
@@ -217,51 +218,33 @@ machine-$(CONFIG_ARCH_RENESAS) += shmobile
machine-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti
machine-$(CONFIG_ARCH_STM32) += stm32
+machine-$(CONFIG_ARCH_SUNPLUS) += sunplus
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += ux500
-machine-$(CONFIG_ARCH_VERSATILE) += versatile
-machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_ZYNQ) += zynq
+machine-$(CONFIG_PLAT_VERSATILE) += versatile
machine-$(CONFIG_PLAT_SPEAR) += spear
-# Platform directory name. This list is sorted alphanumerically
-# by CONFIG_* macro name.
-plat-$(CONFIG_PLAT_ORION) += orion
-plat-$(CONFIG_PLAT_PXA) += pxa
-plat-$(CONFIG_PLAT_VERSATILE) += versatile
+# legacy platforms provide their own mach/*.h headers globally,
+# these three are mutually exclusive
+machdirs-$(CONFIG_ARCH_FOOTBRIDGE) += arch/arm/mach-footbridge
+machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
+machdirs-$(CONFIG_ARCH_SA1100) += arch/arm/mach-sa1100
+KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%/include,$(machdirs-y))
# The byte offset of the kernel image in RAM from the start of RAM.
TEXT_OFFSET := $(textofs-y)
-# The first directory contains additional information for the boot setup code
-ifneq ($(machine-y),)
-MACHINE := arch/arm/mach-$(word 1,$(machine-y))/
-else
-MACHINE :=
-endif
-ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
-MACHINE :=
-endif
-
-machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
-platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
-
-ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
-ifneq ($(CONFIG_ARM_SINGLE_ARMV7M),y)
-KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
-endif
-endif
-
export TEXT_OFFSET GZFLAGS MMUEXT
# If we have a machine-specific directory, then include it in the build.
-core-y += $(machdirs) $(platdirs)
-
+core-y += $(patsubst %,arch/arm/mach-%/,$(machine-y))
# For cleaning
-core- += $(patsubst %,arch/arm/mach-%/, $(machine-))
-core- += $(patsubst %,arch/arm/plat-%/, $(plat-))
+core- += $(patsubst %,arch/arm/mach-%/,$(machine-))
+
+core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/
libs-y := arch/arm/lib/ $(libs-y)
@@ -314,12 +297,12 @@ bootpImage uImage: zImage
zImage: Image
$(BOOT_TARGETS): vmlinux
- $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
+ $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
@$(kecho) ' Kernel: $(boot)/$@ is ready'
+$(INSTALL_TARGETS): KBUILD_IMAGE = $(boot)/$(patsubst %install,%Image,$@)
$(INSTALL_TARGETS):
- $(CONFIG_SHELL) $(srctree)/$(boot)/install.sh "$(KERNELRELEASE)" \
- $(boot)/$(patsubst %install,%Image,$@) System.map "$(INSTALL_PATH)"
+ $(call cmd,install)
PHONY += vdso_install
vdso_install:
@@ -328,8 +311,12 @@ ifeq ($(CONFIG_VDSO),y)
endif
# My testing targets (bypasses dependencies)
-bp:; $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/bootpImage
+bp:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/bootpImage
+include $(srctree)/scripts/Makefile.defconf
+PHONY += multi_v7_lpae_defconfig
+multi_v7_lpae_defconfig:
+ $(call merge_into_defconfig,multi_v7_defconfig,lpae)
define archhelp
echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
@@ -345,4 +332,6 @@ define archhelp
echo ' (distribution) /sbin/$(INSTALLKERNEL) or'
echo ' install to $$(INSTALL_PATH) and run lilo'
echo ' vdso_install - Install unstripped vdso.so to $$(INSTALL_MOD_PATH)/vdso'
+ echo
+ echo ' multi_v7_lpae_defconfig - multi_v7_defconfig with CONFIG_ARM_LPAE enabled'
endef
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 54a09f9464fb..abd6a2889fd0 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -10,22 +10,16 @@
#
# Copyright (C) 1995-2002 Russell King
#
-
OBJCOPYFLAGS :=-O binary -R .comment -S
-ifneq ($(MACHINE),)
-include $(MACHINE)/Makefile.boot
-endif
-
-# Note: the following conditions must always be true:
# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
-# PARAMS_PHYS must be within 4MB of ZRELADDR
-# INITRD_PHYS must be in RAM
-ZRELADDR := $(zreladdr-y)
-PARAMS_PHYS := $(params_phys-y)
-INITRD_PHYS := $(initrd_phys-y)
+ifdef CONFIG_PHYS_OFFSET
+add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
+ZRELADDR := $(call add_hex, $(CONFIG_PHYS_OFFSET), $(TEXT_OFFSET))
+endif
-export ZRELADDR INITRD_PHYS PARAMS_PHYS
+PHYS_OFFSET := $(CONFIG_PHYS_OFFSET)
+export ZRELADDR PARAMS_PHYS PHYS_OFFSET
targets := Image zImage xipImage bootpImage uImage
@@ -90,17 +84,10 @@ $(obj)/uImage: $(obj)/zImage FORCE
@$(check_for_multiple_loadaddr)
$(call if_changed,uimage)
-$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
+$(obj)/bootp/bootp: $(obj)/zImage FORCE
$(Q)$(MAKE) $(build)=$(obj)/bootp $@
$(obj)/bootpImage: $(obj)/bootp/bootp FORCE
$(call if_changed,objcopy)
-PHONY += initrd
-initrd:
- @test "$(INITRD_PHYS)" != "" || \
- (echo This machine does not support INITRD; exit -1)
- @test "$(INITRD)" != "" || \
- (echo You must specify INITRD; exit -1)
-
subdir- := bootp compressed dts
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index 981a8d03f064..a2934e6fd89a 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -5,9 +5,40 @@
# This file is included by the global makefile so that you can add your own
# architecture-specific flags and dependencies.
#
-
GCOV_PROFILE := n
+ifdef PHYS_OFFSET
+add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
+
+# If PHYS_OFFSET is set, INITRD_PHYS and PARAMS_PHYS can be derived,
+# otherwise they must be passed on the command line.
+#
+# Note: the following conditions must always be true:
+# PARAMS_PHYS must be within 4MB of ZRELADDR
+# INITRD_PHYS must be in RAM
+
+PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
+
+# guess an initrd location if possible
+initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000
+initrd_offset-$(CONFIG_ARCH_SA1100) += 0x00800000
+initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
+INITRD_OFFSET := $(initrd_offset-y)
+ifdef INITRD_OFFSET
+INITRD_PHYS := $(call add_hex, $(PHYS_OFFSET), $(INITRD_OFFSET))
+endif
+
+endif
+
+PHONY += initrd
+initrd:
+ @test "$(PARAMS_PHYS)" != "" || \
+ (echo bootpImage: You must specify PHYS_OFFSET of PARAMS_PHYS ; exit -1)
+ @test "$(INITRD_PHYS)" != "" || \
+ (echo bootpImage: You must specify INITRD_OFFSET or INITRD_PHYS ; exit -1)
+ @test "$(INITRD)" != "" || \
+ (echo bootpImage: You must specify INITRD; exit -1)
+
LDFLAGS_bootp := --no-undefined -X \
--defsym initrd_phys=$(INITRD_PHYS) \
--defsym params_phys=$(PARAMS_PHYS) -T
@@ -24,6 +55,6 @@ $(obj)/bootp: $(src)/bootp.lds $(addprefix $(obj)/,init.o kernel.o initrd.o) FOR
$(obj)/kernel.o: arch/arm/boot/zImage FORCE
-$(obj)/initrd.o: $(INITRD) FORCE
+$(obj)/initrd.o: initrd $(INITRD) FORCE
PHONY += $(INITRD)
diff --git a/arch/arm/boot/bootp/bootp.lds b/arch/arm/boot/bootp/bootp.lds
index fc54394f4340..160128186bf8 100644
--- a/arch/arm/boot/bootp/bootp.lds
+++ b/arch/arm/boot/bootp/bootp.lds
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* linux/arch/arm/boot/bootp/bootp.lds
*
* Copyright (C) 2000-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
OUTPUT_ARCH(arm)
ENTRY(_start)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 41bcbb460fac..726ecabcef09 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -27,6 +27,7 @@ KASAN_SANITIZE := n
# Prevents link failures: __sanitizer_cov_trace_pc() is not linked in.
KCOV_INSTRUMENT := n
+UBSAN_SANITIZE := n
#
# Architecture dependencies
@@ -106,7 +107,7 @@ ccflags-remove-$(CONFIG_FUNCTION_TRACER) += -pg
asflags-y := -DZIMAGE
# Supply kernel BSS size to the decompressor via a linker symbol.
-KBSS_SZ = $(shell echo $$(($$($(NM) $(obj)/../../../../vmlinux | \
+KBSS_SZ = $(shell echo $$(($$($(NM) vmlinux | \
sed -n -e 's/^\([^ ]*\) [ABD] __bss_start$$/-0x\1/p' \
-e 's/^\([^ ]*\) [ABD] __bss_stop$$/+0x\1/p') )) )
LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
@@ -123,7 +124,7 @@ LDFLAGS_vmlinux += --no-undefined
LDFLAGS_vmlinux += -X
# Report orphan sections
ifdef CONFIG_LD_ORPHAN_WARN
-LDFLAGS_vmlinux += --orphan-handling=warn
+LDFLAGS_vmlinux += --orphan-handling=$(CONFIG_LD_ORPHAN_WARN_LEVEL)
endif
# Next argument is a linker script
LDFLAGS_vmlinux += -T
@@ -163,4 +164,3 @@ $(obj)/piggy_data: $(obj)/../Image FORCE
$(obj)/piggy.o: $(obj)/piggy_data
CFLAGS_font.o := -Dstatic=
-AFLAGS_hyp-stub.o := -Wa,-march=armv7-a
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 74255e819831..0669851394f0 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -31,6 +31,7 @@
/* Not needed, but used in some headers pulled in by decompressors */
extern char * strstr(const char * s1, const char *s2);
extern size_t strlen(const char *s);
+extern int strcmp(const char *cs, const char *ct);
extern int memcmp(const void *cs, const void *ct, size_t count);
extern char * strchrnul(const char *, int);
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 95abdd850fe3..23eae1a65064 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -20,10 +20,6 @@ __SA1100_start:
#ifdef CONFIG_SA1100_COLLIE
mov r7, #MACH_TYPE_COLLIE
#endif
-#ifdef CONFIG_SA1100_SIMPAD
- @ UNTIL we've something like an open bootldr
- mov r7, #MACH_TYPE_SIMPAD @should be 87
-#endif
mrc p15, 0, r0, c1, c0, 0 @ read control reg
ands r0, r0, #0x0d
beq 99f
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index bf79f2f78d23..9f406e9c0ea6 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -67,11 +67,7 @@
#if defined(CONFIG_ARCH_SA1100)
.macro loadsp, rb, tmp1, tmp2
mov \rb, #0x80000000 @ physical base address
-#ifdef CONFIG_DEBUG_LL_SER3
- add \rb, \rb, #0x00050000 @ Ser3
-#else
add \rb, \rb, #0x00010000 @ Ser1
-#endif
.endm
#else
.macro loadsp, rb, tmp1, tmp2
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/boot/compressed/misc-ep93xx.h
index b3ec1db988db..65b4121d1490 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/boot/compressed/misc-ep93xx.h
@@ -1,55 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * arch/arm/mach-ep93xx/include/mach/uncompress.h
- *
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*/
-#include <mach/ep93xx-regs.h>
#include <asm/mach-types.h>
-static unsigned char __raw_readb(unsigned int ptr)
-{
- return *((volatile unsigned char *)ptr);
-}
-
-static unsigned int __raw_readl(unsigned int ptr)
+static inline unsigned int __raw_readl(unsigned int ptr)
{
return *((volatile unsigned int *)ptr);
}
-static void __raw_writeb(unsigned char value, unsigned int ptr)
+static inline void __raw_writeb(unsigned char value, unsigned int ptr)
{
*((volatile unsigned char *)ptr) = value;
}
-static void __raw_writel(unsigned int value, unsigned int ptr)
+static inline void __raw_writel(unsigned int value, unsigned int ptr)
{
*((volatile unsigned int *)ptr) = value;
}
-#define PHYS_UART_DATA (CONFIG_DEBUG_UART_PHYS + 0x00)
-#define PHYS_UART_FLAG (CONFIG_DEBUG_UART_PHYS + 0x18)
-#define UART_FLAG_TXFF 0x20
-
-static inline void putc(int c)
-{
- int i;
-
- for (i = 0; i < 10000; i++) {
- /* Transmit fifo not full? */
- if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
- break;
- }
-
- __raw_writeb(c, PHYS_UART_DATA);
-}
-
-static inline void flush(void)
-{
-}
-
-
/*
* Some bootloaders don't turn off DMA from the ethernet MAC before
* jumping to linux, which means that we might end up with bits of RX
@@ -59,7 +29,7 @@ static inline void flush(void)
#define PHYS_ETH_SELF_CTL 0x80010020
#define ETH_SELF_CTL_RESET 0x00000001
-static void ethernet_reset(void)
+static inline void ep93xx_ethernet_reset(void)
{
unsigned int v;
@@ -76,15 +46,30 @@ static void ethernet_reset(void)
#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000
#define TS72XX_WDT_FEED_VAL 0x05
-static void __maybe_unused ts72xx_watchdog_disable(void)
+static inline void __maybe_unused ts72xx_watchdog_disable(void)
{
__raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE);
__raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE);
}
-static void arch_decomp_setup(void)
+static inline void ep93xx_decomp_setup(void)
{
if (machine_is_ts72xx())
ts72xx_watchdog_disable();
- ethernet_reset();
+
+ if (machine_is_edb9301() ||
+ machine_is_edb9302() ||
+ machine_is_edb9302a() ||
+ machine_is_edb9302a() ||
+ machine_is_edb9307() ||
+ machine_is_edb9307a() ||
+ machine_is_edb9307a() ||
+ machine_is_edb9312() ||
+ machine_is_edb9315() ||
+ machine_is_edb9315a() ||
+ machine_is_edb9315a() ||
+ machine_is_ts72xx() ||
+ machine_is_bk3() ||
+ machine_is_vision_ep9307())
+ ep93xx_ethernet_reset();
}
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index c3c66ff2d696..abfed1aa2baa 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -23,6 +23,9 @@ unsigned int __machine_arch_type;
#include <linux/types.h>
#include <linux/linkage.h>
#include "misc.h"
+#ifdef CONFIG_ARCH_EP93XX
+#include "misc-ep93xx.h"
+#endif
static void putstr(const char *ptr);
@@ -143,6 +146,9 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
free_mem_end_ptr = free_mem_ptr_end_p;
__machine_arch_type = arch_id;
+#ifdef CONFIG_ARCH_EP93XX
+ ep93xx_decomp_setup();
+#endif
arch_decomp_setup();
putstr("Uncompressing Linux...");
diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S
index 1bcb68ac4b01..3fcb3e62dc56 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -23,6 +23,7 @@ SECTIONS
*(.ARM.extab*)
*(.note.*)
*(.rel.*)
+ *(.printk_index)
/*
* Discard any r/w data - this produces a link error if we have any,
* which is required for PIC decompression. Local data generates
@@ -57,6 +58,7 @@ SECTIONS
*(.rodata)
*(.rodata.*)
*(.data.rel.ro)
+ *(.data.rel.ro.*)
}
.piggydata : {
*(.piggydata)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c16f8a2b738..59829fc90315 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM9X60) += \
+ at91-sam9x60_curiosity.dtb \
at91-sam9x60ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2-2.dtb \
@@ -61,6 +62,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d2_icp.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
+ at91-sama5d3_eds.dtb \
at91-sama5d3_ksz9477_evb.dtb \
at91-sama5d3_xplained.dtb \
at91-dvk_som60.dtb \
@@ -79,6 +81,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-vinco.dtb
dtb-$(CONFIG_SOC_SAMA7G5) += \
at91-sama7g5ek.dtb
+dtb-$(CONFIG_SOC_SP7021) += \
+ sunplus-sp7021-demo-v3.dtb
dtb-$(CONFIG_ARCH_AXXIA) += \
axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += \
@@ -103,6 +107,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac56u.dtb \
bcm4708-asus-rt-ac68u.dtb \
bcm4708-buffalo-wzr-1750dhp.dtb \
+ bcm4708-buffalo-wzr-1166dhp.dtb \
+ bcm4708-buffalo-wzr-1166dhp2.dtb \
bcm4708-linksys-ea6300-v1.dtb \
bcm4708-linksys-ea6500-v2.dtb \
bcm4708-luxul-xap-1510.dtb \
@@ -124,6 +130,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-tplink-archer-c9-v1.dtb \
bcm47094-asus-rt-ac88u.dtb \
bcm47094-dlink-dir-885l.dtb \
+ bcm47094-dlink-dir-890l.dtb \
bcm47094-linksys-panamera.dtb \
bcm47094-luxul-abr-4500.dtb \
bcm47094-luxul-xap-1610.dtb \
@@ -133,6 +140,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm47094-luxul-xwr-3150-v1.dtb \
bcm47094-netgear-r8500.dtb \
bcm47094-phicomm-k3.dtb \
+ bcm53015-meraki-mr26.dtb \
+ bcm53016-dlink-dwl-8610ap.dtb \
bcm53016-meraki-mr32.dtb \
bcm94708.dtb \
bcm94709.dtb \
@@ -144,8 +153,6 @@ dtb-$(CONFIG_ARCH_BCM_53573) += \
bcm47189-luxul-xap-810.dtb \
bcm47189-tenda-ac9.dtb \
bcm947189acdbmr.dtb
-dtb-$(CONFIG_ARCH_BCM_63XX) += \
- bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
bcm911360_entphn.dtb \
bcm911360k.dtb \
@@ -179,6 +186,16 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2q-marvell-dmp.dtb
dtb-$(CONFIG_ARCH_BRCMSTB) += \
bcm7445-bcm97445svmb.dtb
+dtb-$(CONFIG_ARCH_BCMBCA) += \
+ bcm947622.dtb \
+ bcm963138.dtb \
+ bcm963138dvt.dtb \
+ bcm963148.dtb \
+ bcm963178.dtb \
+ bcm96756.dtb \
+ bcm96846.dtb \
+ bcm96855.dtb \
+ bcm96878.dtb
dtb-$(CONFIG_ARCH_CLPS711X) += \
ep7211-edb7211.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += \
@@ -230,6 +247,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5422-odroidxu3.dtb \
exynos5422-odroidxu3-lite.dtb \
exynos5422-odroidxu4.dtb \
+ exynos5422-samsung-k3g.dtb \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-dlink-dir-685.dtb \
@@ -255,6 +273,8 @@ dtb-$(CONFIG_ARCH_HISI) += \
hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
+dtb-$(CONFIG_ARCH_HPE_GXP) += \
+ hpe-bmc-dl360gen10.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorap.dtb \
integratorap-im-pd1.dtb \
@@ -339,6 +359,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-ns2mini.dtb \
kirkwood-nsa310.dtb \
kirkwood-nsa310a.dtb \
+ kirkwood-nsa310s.dtb \
kirkwood-nsa320.dtb \
kirkwood-nsa325.dtb \
kirkwood-openblocks_a6.dtb \
@@ -446,6 +467,7 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-ppd.dtb \
imx53-qsb.dtb \
imx53-qsrb.dtb \
+ imx53-sk-imx53.dtb \
imx53-smd.dtb \
imx53-tx53-x03x.dtb \
imx53-tx53-x13x.dtb \
@@ -458,8 +480,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-aristainetos_7.dtb \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
+ imx6dl-colibri-aster.dtb \
imx6dl-colibri-eval-v3.dtb \
- imx6dl-colibri-v1_1-eval-v3.dtb \
+ imx6dl-colibri-iris.dtb \
+ imx6dl-colibri-iris-v2.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
@@ -537,16 +561,20 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-wandboard-revd1.dtb \
imx6dl-yapp4-draco.dtb \
imx6dl-yapp4-hydra.dtb \
+ imx6dl-yapp4-lynx.dtb \
imx6dl-yapp4-orion.dtb \
+ imx6dl-yapp4-phoenix.dtb \
imx6dl-yapp4-ursa.dtb \
imx6q-apalis-eval.dtb \
imx6q-apalis-ixora.dtb \
imx6q-apalis-ixora-v1.1.dtb \
+ imx6q-apalis-ixora-v1.2.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
imx6q-b650v3.dtb \
imx6q-b850v3.dtb \
+ imx6q-bosch-acc.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-cubox-i-emmc-som-v15.dtb \
@@ -642,6 +670,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-wandboard-revb1.dtb \
imx6q-wandboard-revd1.dtb \
imx6q-yapp4-crux.dtb \
+ imx6q-yapp4-pegasus.dtb \
imx6q-zii-rdu2.dtb \
imx6qp-mba6b.dtb \
imx6qp-nitrogen6_max.dtb \
@@ -657,12 +686,15 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-vicutp.dtb \
imx6qp-wandboard-revd1.dtb \
imx6qp-yapp4-crux-plus.dtb \
+ imx6qp-yapp4-pegasus-plus.dtb \
imx6qp-zii-rdu2.dtb \
imx6s-dhcom-drc02.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
+ imx6sl-kobo-aura2.dtb \
imx6sl-tolino-shine2hd.dtb \
imx6sl-tolino-shine3.dtb \
+ imx6sl-tolino-vision.dtb \
imx6sl-tolino-vision5.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
@@ -687,9 +719,12 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
- imx6ul-kontron-n6310-s.dtb \
- imx6ul-kontron-n6310-s-43.dtb \
+ imx6ul-kontron-bl.dtb \
+ imx6ul-kontron-bl-43.dtb \
imx6ul-liteboard.dtb \
+ imx6ul-tqma6ul1-mba6ulx.dtb \
+ imx6ul-tqma6ul2-mba6ulx.dtb \
+ imx6ul-tqma6ul2l-mba6ulx.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-pico-dwarf.dtb \
imx6ul-pico-hobbit.dtb \
@@ -701,23 +736,48 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
+ imx6ull-colibri-aster.dtb \
+ imx6ull-colibri-emmc-aster.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
+ imx6ull-colibri-emmc-iris.dtb \
+ imx6ull-colibri-emmc-iris-v2.dtb \
imx6ull-colibri-eval-v3.dtb \
+ imx6ull-colibri-iris.dtb \
+ imx6ull-colibri-iris-v2.dtb \
+ imx6ull-colibri-wifi-aster.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-colibri-wifi-iris.dtb \
+ imx6ull-colibri-wifi-iris-v2.dtb \
+ imx6ull-dhcom-drc02.dtb \
+ imx6ull-dhcom-pdk2.dtb \
+ imx6ull-dhcom-picoitx.dtb \
imx6ull-jozacp.dtb \
+ imx6ull-kontron-bl.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-phytec-segin-lc-rdk-nand.dtb \
+ imx6ull-phytec-tauri-emmc.dtb \
+ imx6ull-phytec-tauri-nand.dtb \
+ imx6ull-tarragon-master.dtb \
+ imx6ull-tarragon-micro.dtb \
+ imx6ull-tarragon-slave.dtb \
+ imx6ull-tarragon-slavext.dtb \
+ imx6ull-tqma6ull2-mba6ulx.dtb \
+ imx6ull-tqma6ull2l-mba6ulx.dtb \
imx6ulz-14x14-evk.dtb \
imx6ulz-bsh-smm-m2.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-aster.dtb \
imx7d-colibri-emmc-aster.dtb \
+ imx7d-colibri-emmc-iris.dtb \
+ imx7d-colibri-emmc-iris-v2.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
+ imx7d-colibri-iris.dtb \
+ imx7d-colibri-iris-v2.dtb \
imx7d-flex-concentrator.dtb \
imx7d-flex-concentrator-mfg.dtb \
imx7d-mba7.dtb \
@@ -732,18 +792,28 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb.dtb \
imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \
+ imx7d-smegw01.dtb \
imx7d-zii-rmu2.dtb \
imx7d-zii-rpu2.dtb \
imx7s-colibri-aster.dtb \
imx7s-colibri-eval-v3.dtb \
+ imx7s-colibri-iris.dtb \
+ imx7s-colibri-iris-v2.dtb \
imx7s-mba7.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
+dtb-$(CONFIG_SOC_IMXRT) += \
+ imxrt1050-evk.dtb
dtb-$(CONFIG_SOC_LAN966) += \
- lan966x-pcb8291.dtb
+ lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
+ lan966x-kontron-kswitch-d10-mmt-8g.dtb \
+ lan966x-pcb8290.dtb \
+ lan966x-pcb8291.dtb \
+ lan966x-pcb8309.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
+ ls1021a-iot.dtb \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
ls1021a-tsn.dtb \
@@ -933,16 +1003,24 @@ dtb-$(CONFIG_SOC_OMAP5) += \
omap5-igep0050.dtb \
omap5-sbc-t54.dtb \
omap5-uevm.dtb
+am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo
+am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo
dtb-$(CONFIG_SOC_DRA7XX) += \
am57xx-beagle-x15.dtb \
am57xx-beagle-x15-revb1.dtb \
am57xx-beagle-x15-revc.dtb \
+ am57xx-evm.dtb \
+ am57xx-evm-reva3.dtb \
am5729-beagleboneai.dtb \
am57xx-cl-som-am57x.dtb \
am57xx-sbc-am57x.dtb \
am572x-idk.dtb \
+ am572x-idk-touchscreen.dtbo \
am571x-idk.dtb \
+ am571x-idk-touchscreen.dtbo \
am574x-idk.dtb \
+ am57xx-idk-lcd-osd101t2045.dtbo \
+ am57xx-idk-lcd-osd101t2587.dtbo \
dra7-evm.dtb \
dra72-evm.dtb \
dra72-evm-revc.dtb \
@@ -972,16 +1050,16 @@ dtb-$(CONFIG_ARCH_PXA) += \
pxa300-raumfeld-speaker-m.dtb \
pxa300-raumfeld-speaker-one.dtb \
pxa300-raumfeld-speaker-s.dtb
-dtb-$(CONFIG_ARCH_OXNAS) += \
- ox810se-wd-mbwe.dtb \
- ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8016-sbc.dtb \
+ qcom-apq8026-asus-sparrow.dtb \
+ qcom-apq8026-huawei-sturgeon.dtb \
qcom-apq8026-lg-lenok.dtb \
+ qcom-apq8026-samsung-matisse-wifi.dtb \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
- qcom-apq8064-sony-xperia-yuga.dtb \
+ qcom-apq8064-sony-xperia-lagan-yuga.dtb \
qcom-apq8064-asus-nexus7-flo.dtb \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
@@ -998,14 +1076,18 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq8064-rb3011.dtb \
qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \
+ qcom-msm8916-samsung-e5.dtb \
+ qcom-msm8916-samsung-e7.dtb \
+ qcom-msm8916-samsung-grandmax.dtb \
qcom-msm8916-samsung-serranove.dtb \
qcom-msm8960-cdp.dtb \
- qcom-msm8974-fairphone-fp2.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
- qcom-msm8974-samsung-klte.dtb \
- qcom-msm8974-sony-xperia-amami.dtb \
- qcom-msm8974-sony-xperia-castor.dtb \
- qcom-msm8974-sony-xperia-honami.dtb \
+ qcom-msm8974-sony-xperia-rhine-amami.dtb \
+ qcom-msm8974-sony-xperia-rhine-honami.dtb \
+ qcom-msm8974pro-fairphone-fp2.dtb \
+ qcom-msm8974pro-oneplus-bacon.dtb \
+ qcom-msm8974pro-samsung-klte.dtb \
+ qcom-msm8974pro-sony-xperia-shinano-castor.dtb \
qcom-mdm9615-wp8548-mangoh-green.dtb \
qcom-sdx55-mtp.dtb \
qcom-sdx55-t55.dtb \
@@ -1065,12 +1147,14 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
+ rv1126-edgeble-neu2-io.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
+ rk3128-evb.dtb \
rk3188-bqedison2qc.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
@@ -1101,8 +1185,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-speedy.dtb \
rk3288-veyron-tiger.dtb \
rk3288-vyasa.dtb
-dtb-$(CONFIG_ARCH_S3C24XX) += \
- s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += \
s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
@@ -1116,7 +1198,8 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
- socfpga_arria10_mercury_aa1.dtb \
+ socfpga_arria10_chameleonv3.dtb \
+ socfpga_arria10_mercury_pe1.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
@@ -1156,10 +1239,16 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32h743i-disco.dtb \
stm32h750i-art-pi.dtb \
stm32mp135f-dk.dtb \
+ stm32mp151a-prtt1a.dtb \
+ stm32mp151a-prtt1c.dtb \
+ stm32mp151a-prtt1s.dtb \
+ stm32mp151a-dhcor-testbench.dtb \
stm32mp153c-dhcom-drc02.dtb \
+ stm32mp153c-dhcor-drc-compact.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
+ stm32mp157a-dk1-scmi.dtb \
stm32mp157a-iot-box.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
@@ -1170,9 +1259,12 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
stm32mp157c-dk2.dtb \
+ stm32mp157c-dk2-scmi.dtb \
stm32mp157c-ed1.dtb \
+ stm32mp157c-ed1-scmi.dtb \
stm32mp157c-emsbc-argon.dtb \
stm32mp157c-ev1.dtb \
+ stm32mp157c-ev1-scmi.dtb \
stm32mp157c-lxa-mc1.dtb \
stm32mp157c-odyssey.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
@@ -1319,6 +1411,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-s3-pinecube.dtb \
+ sun8i-t113s-mangopi-mq-r-t113.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb \
@@ -1328,7 +1421,9 @@ dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_MACH_SUNIV) += \
- suniv-f1c100s-licheepi-nano.dtb
+ suniv-f1c100s-licheepi-nano.dtb \
+ suniv-f1c200s-lctech-pi.dtb \
+ suniv-f1c200s-popstick-v1.1.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-asus-tf101.dtb \
@@ -1382,6 +1477,7 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-ux500-samsung-janice.dtb \
ste-ux500-samsung-gavini.dtb \
ste-ux500-samsung-codina.dtb \
+ ste-ux500-samsung-codina-tmo.dtb \
ste-ux500-samsung-skomer.dtb \
ste-ux500-samsung-kyle.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
@@ -1390,6 +1486,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-pro4-ace.dtb \
uniphier-pro4-ref.dtb \
uniphier-pro4-sanji.dtb \
+ uniphier-pro5-epcore.dtb \
+ uniphier-pro5-proex.dtb \
uniphier-pxs2-gentil.dtb \
uniphier-pxs2-vodka.dtb \
uniphier-sld8-ref.dtb
@@ -1516,19 +1614,22 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb-a1.dtb \
aspeed-ast2600-evb.dtb \
+ aspeed-bmc-amd-daytonax.dtb \
aspeed-bmc-amd-ethanolx.dtb \
aspeed-bmc-ampere-mtjade.dtb \
- aspeed-bmc-arm-centriq2400-rep.dtb \
+ aspeed-bmc-ampere-mtmitchell.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-asrock-e3c246d4i.dtb \
aspeed-bmc-asrock-romed8hm3.dtb \
aspeed-bmc-bytedance-g220a.dtb \
+ aspeed-bmc-delta-ahe50dc.dtb \
aspeed-bmc-facebook-bletchley.dtb \
aspeed-bmc-facebook-cloudripper.dtb \
aspeed-bmc-facebook-cmm.dtb \
aspeed-bmc-facebook-elbert.dtb \
aspeed-bmc-facebook-fuji.dtb \
aspeed-bmc-facebook-galaxy100.dtb \
+ aspeed-bmc-facebook-greatlakes.dtb \
aspeed-bmc-facebook-minipack.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-facebook-wedge40.dtb \
@@ -1536,6 +1637,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-facebook-wedge400.dtb \
aspeed-bmc-facebook-yamp.dtb \
aspeed-bmc-facebook-yosemitev2.dtb \
+ aspeed-bmc-ibm-bonnell.dtb \
aspeed-bmc-ibm-everest.dtb \
aspeed-bmc-ibm-rainier.dtb \
aspeed-bmc-ibm-rainier-1s4u.dtb \
@@ -1547,7 +1649,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-lenovo-hr855xg2.dtb \
aspeed-bmc-microsoft-olympus.dtb \
aspeed-bmc-opp-lanyang.dtb \
- aspeed-bmc-opp-mihawk.dtb \
aspeed-bmc-opp-mowgli.dtb \
aspeed-bmc-opp-nicole.dtb \
aspeed-bmc-opp-palmetto.dtb \
@@ -1558,12 +1659,14 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
+ aspeed-bmc-qcom-dc-scm-v1.dtb \
aspeed-bmc-quanta-q71l.dtb \
aspeed-bmc-quanta-s6q.dtb \
aspeed-bmc-supermicro-x11spi.dtb \
aspeed-bmc-inventec-transformers.dtb \
aspeed-bmc-tyan-s7106.dtb \
aspeed-bmc-tyan-s8036.dtb \
+ aspeed-bmc-ufispace-ncplite.dtb \
aspeed-bmc-vegman-n110.dtb \
aspeed-bmc-vegman-rx20.dtb \
aspeed-bmc-vegman-sx20.dtb
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index 3b0675a1c460..ff68dfb4eb78 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -126,7 +126,7 @@
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
- uart0: uart@fd883000 {
+ uart0: serial@fd883000 {
compatible = "ns16550a";
reg = <0x0 0xfd883000 0x0 0x1000>;
clock-frequency = <375000000>;
@@ -135,7 +135,7 @@
reg-io-width = <4>;
};
- uart1: uart@fd884000 {
+ uart1: serial@fd884000 {
compatible = "ns16550a";
reg = <0x0 0xfd884000 0x0 0x1000>;
clock-frequency = <375000000>;
@@ -154,7 +154,7 @@
reg = <0x0 0xfbc00000 0x0 0x100000>;
interrupt-map-mask = <0xf800 0 0 7>;
/* Add legacy interrupts for SATA devices only */
- interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
+ interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
<0x4800 0 0 1 &gic 0 44 4>;
/* 32 bit non prefetchable memory space */
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index daf4cb398070..75992eec830f 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -81,3 +81,147 @@
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
+
+&gpio0 {
+ gpio-line-names =
+ "MDIO",
+ "MDC",
+ "NC",
+ "NC",
+ "I2C1_SDA",
+ "I2C1_SCL",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "UART1_CTSN",
+ "UART1_RTSN",
+ "UART1_RX",
+ "UART1_TX",
+ "onrisc:blue:wlan",
+ "onrisc:green:app",
+ "USB0_DRVVBUS",
+ "ETH2_INT",
+ "NC",
+ "RMII1_TXD1",
+ "MMC1_DAT0",
+ "MMC1_DAT1",
+ "NC",
+ "NC",
+ "MMC1_DAT2",
+ "MMC1_DAT3",
+ "RMII1_TXD0",
+ "NC",
+ "GPMC_WAIT0",
+ "GPMC_WP_N";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "GPMC_AD0",
+ "GPMC_AD1",
+ "GPMC_AD2",
+ "GPMC_AD3",
+ "GPMC_AD4",
+ "GPMC_AD5",
+ "GPMC_AD6",
+ "GPMC_AD7",
+ "NC",
+ "NC",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "NC",
+ "NC",
+ "NC",
+ "SD_CD",
+ "RGMII2_TCTL",
+ "RGMII2_RCTL",
+ "RGMII2_TD3",
+ "RGMII2_TD2",
+ "RGMII2_TD1",
+ "RGMII2_TD0",
+ "RGMII2_TCLK",
+ "RGMII2_RCLK",
+ "RGMII2_RD3",
+ "RGMII2_RD2",
+ "RGMII2_RD1",
+ "RGMII2_RD0",
+ "PMIC_INT1",
+ "GPMC_CSN0_Flash",
+ "MMC1_CLK",
+ "MMC1_CMD";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "GPMC_CSN3_BUS",
+ "GPMC_CLK",
+ "GPMC_ADVN_ALE",
+ "GPMC_OEN_RE_N",
+ "GPMC_WE_N",
+ "GPMC_BEN0_CLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SW2_0",
+ "SW2_1",
+ "RMII1_RXD1",
+ "RMII1_RXD0",
+ "UART1_DTR",
+ "UART1_DSR",
+ "UART1_DCD",
+ "UART1_RI",
+ "MMC0_DAT3",
+ "MMC0_DAT2",
+ "MMC0_DAT1",
+ "MMC0_DAT0",
+ "MMC0_CLK",
+ "MMC0_CMD";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "onrisc:red:power",
+ "RMII1_CRS_DV",
+ "RMII1_RXER",
+ "RMII1_TXEN",
+ "NC",
+ "NC",
+ "NC",
+ "WLAN_IRQ",
+ "WLAN_EN",
+ "SW2_2",
+ "SW2_3",
+ "NC",
+ "NC",
+ "NC",
+ "ModeA0",
+ "ModeA1",
+ "ModeA2",
+ "ModeA3",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index 2123bd589484..087e084506d2 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -91,6 +91,10 @@
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
+ gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
+ "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
+ "ModeA0", "ModeA1", "ModeA2", "ModeA3",
+ "ModeB0", "ModeB1", "ModeB2", "ModeB3";
};
};
@@ -123,3 +127,147 @@
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
};
+
+&gpio0 {
+ gpio-line-names =
+ "MDIO",
+ "MDC",
+ "UART2_RX",
+ "UART2_TX",
+ "I2C1_SDA",
+ "I2C1_SCL",
+ "WLAN_BTN",
+ "W_DISABLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "UART1_CTSN",
+ "UART1_RTSN",
+ "UART1_RX",
+ "UART1_TX",
+ "onrisc:blue:wlan",
+ "onrisc:green:app",
+ "USB0_DRVVBUS",
+ "ETH2_INT",
+ "TCA6416_INT",
+ "RMII1_TXD1",
+ "MMC1_DAT0",
+ "MMC1_DAT1",
+ "NC",
+ "NC",
+ "MMC1_DAT2",
+ "MMC1_DAT3",
+ "RMII1_TXD0",
+ "NC",
+ "GPMC_WAIT0",
+ "GPMC_WP_N";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "GPMC_AD0",
+ "GPMC_AD1",
+ "GPMC_AD2",
+ "GPMC_AD3",
+ "GPMC_AD4",
+ "GPMC_AD5",
+ "GPMC_AD6",
+ "GPMC_AD7",
+ "NC",
+ "NC",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "UART2_DTR",
+ "UART2_DSR",
+ "UART2_DCD",
+ "UART2_RI",
+ "RGMII2_TCTL",
+ "RGMII2_RCTL",
+ "RGMII2_TD3",
+ "RGMII2_TD2",
+ "RGMII2_TD1",
+ "RGMII2_TD0",
+ "RGMII2_TCLK",
+ "RGMII2_RCLK",
+ "RGMII2_RD3",
+ "RGMII2_RD2",
+ "RGMII2_RD1",
+ "RGMII2_RD0",
+ "PMIC_INT1",
+ "GPMC_CSN0_Flash",
+ "MMC1_CLK",
+ "MMC1_CMD";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "GPMC_CSN3_BUS",
+ "GPMC_CLK",
+ "GPMC_ADVN_ALE",
+ "GPMC_OEN_RE_N",
+ "GPMC_WE_N",
+ "GPMC_BEN0_CLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SD_CD",
+ "SD_WP",
+ "RMII1_RXD1",
+ "RMII1_RXD0",
+ "UART1_DTR",
+ "UART1_DSR",
+ "UART1_DCD",
+ "UART1_RI",
+ "MMC0_DAT3",
+ "MMC0_DAT2",
+ "MMC0_DAT1",
+ "MMC0_DAT0",
+ "MMC0_CLK",
+ "MMC0_CMD";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "onrisc:red:power",
+ "RMII1_CRS_DV",
+ "RMII1_RXER",
+ "RMII1_TXEN",
+ "3G_PWR_EN",
+ "UART2_CTSN",
+ "UART2_RTSN",
+ "WLAN_IRQ",
+ "WLAN_EN",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "USB1_DRVVBUS",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index 2f3872dbf4f4..faeb39aab60a 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -99,6 +99,10 @@
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
+ gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
+ "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
+ "ModeA0", "ModeA1", "ModeA2", "ModeA3",
+ "ModeB0", "ModeB1", "ModeB2", "ModeB3";
};
};
@@ -147,3 +151,147 @@
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
};
+
+&gpio0 {
+ gpio-line-names =
+ "MDIO",
+ "MDC",
+ "UART2_RX",
+ "UART2_TX",
+ "I2C1_SDA",
+ "I2C1_SCL",
+ "WLAN_BTN",
+ "W_DISABLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "UART1_CTSN",
+ "UART1_RTSN",
+ "UART1_RX",
+ "UART1_TX",
+ "onrisc:blue:wlan",
+ "onrisc:green:app",
+ "USB0_DRVVBUS",
+ "ETH2_INT",
+ "TCA6416_INT",
+ "RMII1_TXD1",
+ "MMC1_DAT0",
+ "MMC1_DAT1",
+ "NC",
+ "NC",
+ "MMC1_DAT2",
+ "MMC1_DAT3",
+ "RMII1_TXD0",
+ "NC",
+ "GPMC_WAIT0",
+ "GPMC_WP_N";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "GPMC_AD0",
+ "GPMC_AD1",
+ "GPMC_AD2",
+ "GPMC_AD3",
+ "GPMC_AD4",
+ "GPMC_AD5",
+ "GPMC_AD6",
+ "GPMC_AD7",
+ "DCAN1_TX",
+ "DCAN1_RX",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "UART2_DTR",
+ "UART2_DSR",
+ "UART2_DCD",
+ "UART2_RI",
+ "RGMII2_TCTL",
+ "RGMII2_RCTL",
+ "RGMII2_TD3",
+ "RGMII2_TD2",
+ "RGMII2_TD1",
+ "RGMII2_TD0",
+ "RGMII2_TCLK",
+ "RGMII2_RCLK",
+ "RGMII2_RD3",
+ "RGMII2_RD2",
+ "RGMII2_RD1",
+ "RGMII2_RD0",
+ "PMIC_INT1",
+ "GPMC_CSN0_Flash",
+ "MMC1_CLK",
+ "MMC1_CMD";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "GPMC_CSN3_BUS",
+ "GPMC_CLK",
+ "GPMC_ADVN_ALE",
+ "GPMC_OEN_RE_N",
+ "GPMC_WE_N",
+ "GPMC_BEN0_CLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SD_CD",
+ "SD_WP",
+ "RMII1_RXD1",
+ "RMII1_RXD0",
+ "UART1_DTR",
+ "UART1_DSR",
+ "UART1_DCD",
+ "UART1_RI",
+ "MMC0_DAT3",
+ "MMC0_DAT2",
+ "MMC0_DAT1",
+ "MMC0_DAT0",
+ "MMC0_CLK",
+ "MMC0_CMD";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "onrisc:red:power",
+ "RMII1_CRS_DV",
+ "RMII1_RXER",
+ "RMII1_TXEN",
+ "3G_PWR_EN",
+ "UART2_CTSN",
+ "UART2_RTSN",
+ "WLAN_IRQ",
+ "WLAN_EN",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "USB1_DRVVBUS",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
index 9a79f727baf6..025014657d12 100644
--- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
@@ -17,18 +17,18 @@
compatible = "gpio-leds";
- power {
+ led-power {
label = "onrisc:red:power";
linux,default-trigger = "default-on";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- wlan {
+ led-wlan {
label = "onrisc:blue:wlan";
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- app {
+ led-app {
label = "onrisc:green:app";
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index 366702630290..6161c8929a78 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -197,7 +197,7 @@
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
- ti,nand-xfer-type = "polled";
+ ti,nand-xfer-type = "prefetch-dma";
gpmc,device-nand = "true";
gpmc,device-width = <1>;
@@ -285,7 +285,7 @@
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
- regulator-max-microvolt = <1312500>;
+ regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 56ae5095a5b8..02e04a12a270 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -405,3 +405,7 @@
&pruss_tm {
status = "okay";
};
+
+&wkup_m3_ipc {
+ firmware-name = "am335x-bone-scale-data.bin";
+};
diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi
index 7cfddada9348..486f24deb875 100644
--- a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi
+++ b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi
@@ -85,8 +85,13 @@
audio-ports = < TDA998x_I2S 0x03>;
ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
port@0 {
- hdmi_0: endpoint@0 {
+ reg = <0>;
+
+ hdmi_0: endpoint {
remote-endpoint = <&lcdc_0>;
};
};
diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
index c72b09ab8da0..207d2b63e0eb 100644
--- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
@@ -19,7 +19,7 @@
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- startup-delay-us= <70000>;
+ startup-delay-us = <70000>;
/* WL_EN */
gpio = <&gpio3 9 0>;
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 9312197316f0..b956e2f60fe0 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -168,3 +168,7 @@
"NC",
"NC";
};
+
+&baseboard_eeprom {
+ vcc-supply = <&ldo4_reg>;
+};
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index 147c00de3795..34579e98636e 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -106,7 +106,7 @@
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- startup-delay-us= <70000>;
+ startup-delay-us = <70000>;
/* WL_EN */
gpio = <&gpio3 9 0>;
diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
index 215f279e476b..d388cffa1a4d 100644
--- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
@@ -18,7 +18,7 @@
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- startup-delay-us= <70000>;
+ startup-delay-us = <70000>;
/* WL_EN */
gpio = <&gpio0 26 0>;
diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts
index d9f003d886bf..993b13420699 100644
--- a/arch/arm/boot/dts/am335x-cm-t335.dts
+++ b/arch/arm/boot/dts/am335x-cm-t335.dts
@@ -325,7 +325,7 @@ status = "okay";
tlv320aic23: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
- #sound-dai-cells= <0>;
+ #sound-dai-cells = <0>;
status = "okay";
};
};
@@ -491,7 +491,7 @@ status = "okay";
tx-num-evt = <1>;
rx-num-evt = <1>;
- #sound-dai-cells= <0>;
+ #sound-dai-cells = <0>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 659e99eabe66..5beabaa5ff6a 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -92,20 +92,18 @@
0x0201006c>; /* DOWN */
};
- gpio_keys: volume_keys0 {
+ gpio_keys: volume-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- switch9 {
+ switch-9 {
label = "volume-up";
linux,code = <115>;
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
wakeup-source;
};
- switch10 {
+ switch-10 {
label = "volume-down";
linux,code = <114>;
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
@@ -128,7 +126,7 @@
backlight = <&backlight>;
port {
- panel_0: endpoint@0 {
+ panel_0: endpoint {
remote-endpoint = <&lcdc_0>;
};
};
@@ -546,7 +544,7 @@
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
- reg = <0x00000000 0x000020000>;
+ reg = <0x00000000 0x00020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
@@ -782,3 +780,7 @@
&pruss_tm {
status = "okay";
};
+
+&wkup_m3_ipc {
+ firmware-name = "am335x-evm-scale-data.bin";
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index a2db65538e51..5b3278c0c46a 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -191,7 +191,7 @@
backlight = <&lcd_bl>;
port {
- panel_0: endpoint@0 {
+ panel_0: endpoint {
remote-endpoint = <&lcdc_0>;
};
};
@@ -719,3 +719,7 @@
&pruss_tm {
status = "okay";
};
+
+&wkup_m3_ipc {
+ firmware-name = "am335x-evm-scale-data.bin";
+};
diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts
index 1918766c1f80..b357364e93f9 100644
--- a/arch/arm/boot/dts/am335x-guardian.dts
+++ b/arch/arm/boot/dts/am335x-guardian.dts
@@ -29,39 +29,42 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
+ guardian_buttons: gpio-keys {
pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pins>;
+ pinctrl-0 = <&guardian_button_pins>;
+ compatible = "gpio-keys";
+
+ select-button {
+ label = "guardian-select-button";
+ linux,code = <KEY_5>;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
- button21 {
+ power-button {
label = "guardian-power-button";
linux,code = <KEY_POWER>;
- gpios = <&gpio2 21 0>;
+ gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
- leds {
- compatible = "gpio-leds";
+ guardian_leds: gpio-leds {
pinctrl-names = "default";
- pinctrl-0 = <&leds_pins>;
+ pinctrl-0 = <&guardian_led_pins>;
+ compatible = "gpio-leds";
- led1 {
- label = "green:heartbeat";
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ life-led {
+ label = "guardian:life-led";
+ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
+ };
- led2 {
- label = "green:mmc0";
- gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
panel {
@@ -100,20 +103,37 @@
};
- pwm7: dmtimer-pwm {
+ guardian_beeper: pwm-7 {
compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
ti,timers = <&timer7>;
pinctrl-names = "default";
- pinctrl-0 = <&dmtimer7_pins>;
+ pinctrl-0 = <&guardian_beeper_pins>;
ti,clock-source = <0x01>;
};
- vmmcsd_fixed: regulator-3v3 {
+ vmmcsd_fixed: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ mt_keypad: mt_keypad@0 {
+ compatible = "gpio-mt-keypad";
+ debounce-delay-ms = <10>;
+ col-scan-delay-us = <2>;
+ keypad,num-lines = <5>;
+ linux,no-autorepeat;
+ gpio-activelow;
+ line-gpios = <
+ &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/
+ &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/
+ &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/
+ &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/
+ &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/
+ >;
+ };
};
&elm {
@@ -133,28 +153,29 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
+ gpmc,cs-rd-off-ns = <30>;
+ gpmc,cs-wr-off-ns = <30>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <30>;
+ gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-on-ns = <0>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
+ gpmc,we-off-ns = <15>;
+ gpmc,oe-on-ns = <1>;
+ gpmc,oe-off-ns = <15>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <30>;
+ gpmc,wr-cycle-ns = <30>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wr-access-ns = <40>;
+ gpmc,wr-access-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/*
@@ -198,18 +219,33 @@
};
partition@6 {
- label = "u-boot-env";
- reg = <0x300000 0x40000>;
+ label = "u-boot-2";
+ reg = <0x300000 0x100000>;
};
partition@7 {
- label = "u-boot-env.backup1";
- reg = <0x340000 0x40000>;
+ label = "u-boot-2.backup1";
+ reg = <0x400000 0x100000>;
};
partition@8 {
+ label = "u-boot-env";
+ reg = <0x500000 0x40000>;
+ };
+
+ partition@9 {
+ label = "u-boot-env.backup1";
+ reg = <0x540000 0x40000>;
+ };
+
+ partition@10 {
+ label = "splash-screen";
+ reg = <0x580000 0x40000>;
+ };
+
+ partition@11 {
label = "UBI";
- reg = <0x380000 0x1fc80000>;
+ reg = <0x5c0000 0x1fa40000>;
};
};
};
@@ -228,6 +264,11 @@
&lcdc {
blue-and-red-wiring = "crossed";
status = "okay";
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <0>;
+ };
+ };
};
&mmc1 {
@@ -242,7 +283,6 @@
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
- system-power-controller;
};
&spi0 {
@@ -255,14 +295,34 @@
#include "tps65217.dtsi"
&tps {
+ /*
+ * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
+ * mode") at poweroff. Most BeagleBone versions do not support RTC-only
+ * mode and risk hardware damage if this mode is entered.
+ *
+ * For details, see linux-omap mailing list May 2015 thread
+ * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
+ * In particular, messages:
+ * http://www.spinics.net/lists/linux-omap/msg118585.html
+ * http://www.spinics.net/lists/linux-omap/msg118615.html
+ *
+ * You can override this later with
+ * &tps { /delete-property/ ti,pmic-shutdown-controller; }
+ * if you want to use RTC-only mode and made sure you are not affected
+ * by the hardware problems. (Tip: double-check by performing a current
+ * measurement after shutdown: it should be less than 1 mA.)
+ */
ti,pmic-shutdown-controller;
interrupt-parent = <&intc>;
interrupts = <7>; /* NMI */
backlight {
isel = <1>; /* 1 - ISET1, 2 ISET2 */
- fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
- default-brightness = <100>;
+ fdim = <500>; /* TPS65217_BL_FDIM_500HZ */
+ default-brightness = <50>;
+ /* 1(on) - enable current sink, while initialization */
+ /* 0(off) - disable current sink, while initialization */
+ isink-en = <1>;
};
regulators {
@@ -272,6 +332,7 @@
};
dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1351500>;
@@ -280,6 +341,7 @@
};
dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
@@ -319,171 +381,364 @@
};
};
+&gpio0 {
+ gpio-line-names =
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "MirxWakeup",
+ "",
+ "";
+};
+
+&gpio3 {
+ ti,gpio-always-on;
+ ti,no-reset-on-init;
+ gpio-line-names =
+ "",
+ "MirxBtReset",
+ "",
+ "CcVolAdcEn",
+ "MirxBlePause",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AspEn",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "BatVolAdcEn",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
&usb0 {
dr_mode = "peripheral";
};
&usb1 {
dr_mode = "host";
+ /delete-property/dmas;
+ /delete-property/dma-names;
};
&am33xx_pinmux {
pinctrl-names = "default";
- pinctrl-0 = <&clkout2_pin &gpio_pins>;
+ pinctrl-0 = <&clkout2_pin &guardian_interface_pins>;
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
+ /* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
>;
};
- dmtimer7_pins: pinmux_dmtimer7_pins {
+ guardian_interface_pins: pinmux_interface_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
+ /* ADC_BATSENSE_EN */
+ /* (A14) MCASP0_AHCLKx.gpio3[21] */
+ AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* ADC_COINCELL_EN */
+ /* (J16) MII1_TX_EN.gpio3[3] */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* ASP_ENABLE */
+ /* (A13) MCASP0_ACLKx.gpio3[14] */
+ AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ /* (D16) uart1_rxd.uart1_rxd */
+ AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
+ /* (D15) uart1_txd.uart1_txd */
+ AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
+ /*SWITCH-OFF_3V6*/
+ /* (M18) gpio0[1] */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ /* MIRACULIX */
+ /* (H17) gmii1_crs.gpio3[1] */
+ AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* (H18) rmii1_refclk.gpio0[29] */
+ AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
+ /* (J18) gmii1_txd3.gpio0[16] */
+ AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 )
+ /* (J17) gmii1_rxdv.gpio3[4] */
+ AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 )
>;
};
- gpio_keys_pins: pinmux_gpio_keys_pins {
+ guardian_beeper_pins: pinmux_dmtimer7_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */
>;
};
- gpio_pins: pinmux_gpio_pins {
+ guardian_button_pins: pinmux_guardian_button_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
+ AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */
>;
};
+
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ led_bl_pins: gpio_led_bl_pins {
+ pinctrl-single,pins = <
+ /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
>;
};
lcd_disen_pins: pinmux_lcd_disen_pins {
pinctrl-single,pins = <
+ /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
lcd_pins_default: pinmux_lcd_pins_default {
pinctrl-single,pins = <
+ /* (U10) gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T10) gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T11) gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (U12) gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (T12) gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (R12) gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (V13) gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* (U13) gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+ /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+ /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
>;
};
lcd_pins_sleep: pinmux_lcd_pins_sleep {
pinctrl-single,pins = <
+ /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+ /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
>;
};
- leds_pins: pinmux_leds_pins {
+ guardian_led_pins: pinmux_guardian_led_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
- AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
+ /* SPI0_CLK - spi0_clk.spi */
AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ /* SPI0_MOSI - spi0_d0.spi0 */
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ /* SPI0_MISO - spi0_d1.spi0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
+ /* SPI0_CS0 - spi */
AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
+ /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
+ /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
>;
};
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ /* K18 uart2_rxd.mirx_txd */
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1)
+ /* L18 uart2_txd.mirx_rxd */
+ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)
+ >;
+ };
+
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
+ /* (U7) gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
+ /* (V7) gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
+ /* (R8) gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
+ /* (T8) gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
+ /* (U8) gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
+ /* (V8) gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
+ /* (R9) gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
+ /* (T9) gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
+ /* (T17) gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
+ /* (U17) gpmc_wpn.gpmc_wpn */
AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
+ /* (V6) gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
+ /* (R7) gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
+ /* (T7) gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
+ /* (U6) gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
+ /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
>;
};
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index cc14415a4eb9..3fddf80dcf71 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -168,7 +168,7 @@
/* MTD partition table */
partition@0 {
label = "SPL";
- reg = <0x00000000 0x000080000>;
+ reg = <0x00000000 0x00080000>;
};
partition@1 {
@@ -188,7 +188,7 @@
partition@4 {
label = "File System";
- reg = <0x00780000 0x007880000>;
+ reg = <0x00780000 0x07880000>;
};
};
};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
index 11e8f64b6606..49e280b42442 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
@@ -16,11 +16,11 @@
/* Power supply provides a fixed 3.3V @3A */
vmmcsd_fixed: vmmcsd-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
buttons: push_button {
@@ -166,10 +166,8 @@
&buttons {
pinctrl-names = "default";
pinctrl-0 = <&push_button_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- button@0 {
+ button-0 {
label = "push_button";
linux,code = <0x100>;
gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
@@ -182,7 +180,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- m25p80@0 {
+ flash@0 {
compatible = "mx25l6405d";
spi-max-frequency = <40000000>;
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
index a7269b90d795..7d00e8b20f18 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
@@ -21,11 +21,11 @@
/* Power supply provides a fixed 3.3V @3A */
vmmcsd_fixed: vmmcsd-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
buttons: push_button {
@@ -378,10 +378,8 @@
&buttons {
pinctrl-names = "default";
pinctrl-0 = <&push_button_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- button@0 {
+ button-0 {
label = "push_button";
linux,code = <0x100>;
gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
@@ -394,7 +392,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- m25p80@0 {
+ flash@0 {
compatible = "mx25l6405d";
spi-max-frequency = <40000000>;
diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi
index 245c35f41cdf..6eea18b29355 100644
--- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi
+++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi
@@ -27,6 +27,13 @@
reg = <0x80000000 0x10000000>;
};
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+
+ #clock-cells = <0>;
+ };
+
vdd_mod: vdd_mod_reg {
compatible = "regulator-fixed";
regulator-name = "vdd-mod";
@@ -124,9 +131,6 @@
gpmc,wr-data-mux-bus-ns = <0>;
ti,elm-id = <&elm>;
ti,nand-ecc-opt = "bch8";
-
- #address-cells = <1>;
- #size-cells = <1>;
};
};
@@ -149,6 +153,8 @@
};
&rtc {
+ clocks = <&clk32k>;
+ clock-names = "ext-clk";
system-power-controller;
};
diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts
index 1479fd95dec2..425ad9b81a68 100644
--- a/arch/arm/boot/dts/am335x-myirtech-myd.dts
+++ b/arch/arm/boot/dts/am335x-myirtech-myd.dts
@@ -161,8 +161,13 @@
#sound-dai-cells = <0>;
ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
port@0 {
- hdmi_0: endpoint@0 {
+ reg = <0>;
+
+ hdmi_0: endpoint {
remote-endpoint = <&lcdc_0>;
};
};
@@ -227,14 +232,20 @@
};
&nand0 {
- partition@0 {
- label = "MLO";
- reg = <0x00000 0x20000>;
- };
+ nand_parts: partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@20000 {
- label = "boot";
- reg = <0x20000 0x80000>;
+ partition@0 {
+ label = "MLO";
+ reg = <0x00000 0x20000>;
+ };
+
+ partition@80000 {
+ label = "boot";
+ reg = <0x80000 0x100000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
index b6f2567bd65a..c447aebd8d86 100644
--- a/arch/arm/boot/dts/am335x-nano.dts
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -120,8 +120,8 @@
uart3_pins: uart3_pins {
pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */
AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */
AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
>;
@@ -129,8 +129,8 @@
uart4_pins: uart4_pins {
pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */
AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */
>;
@@ -187,12 +187,22 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
+ rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ rs485-rts-active-high;
+ rs485-rx-during-tx;
+ rs485-rts-delay = <1 1>;
+ linux,rs485-enabled-at-boot-time;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
+ rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ rs485-rts-active-high;
+ rs485-rx-during-tx;
+ rs485-rts-delay = <1 1>;
+ linux,rs485-enabled-at-boot-time;
status = "okay";
};
@@ -220,6 +230,11 @@
reg = <0x24>;
};
+ temperature-sensor@48 {
+ compatible = "lm75";
+ reg = <0x48>;
+ };
+
eeprom@53 {
compatible = "microchip,24c02", "atmel,24c02";
reg = <0x53>;
@@ -403,8 +418,13 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
bus-width = <4>;
- cd-gpios = <&gpio3 8 0>;
- wp-gpios = <&gpio3 18 0>;
+ cd-debounce-delay-ms = <5>;
+ cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+};
+
+&usb0 {
+ dr_mode = "host";
};
#include "tps65217.dtsi"
diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts
index 57e756b0f192..2e049489ac06 100644
--- a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts
+++ b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts
@@ -85,3 +85,147 @@
status = "okay";
};
+
+&gpio0 {
+ gpio-line-names =
+ "MDIO",
+ "MDC",
+ "NC",
+ "NC",
+ "I2C1_SDA",
+ "I2C1_SCL",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "can_data",
+ "can_error",
+ "onrisc:blue:wlan",
+ "onrisc:green:app",
+ "USB0_DRVVBUS",
+ "ETH2_INT",
+ "NC",
+ "NC",
+ "MMC1_DAT0",
+ "MMC1_DAT1",
+ "NC",
+ "NC",
+ "MMC1_DAT2",
+ "MMC1_DAT3",
+ "NC",
+ "NC",
+ "GPMC_WAIT0",
+ "GPMC_WP_N";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "GPMC_AD0",
+ "GPMC_AD1",
+ "GPMC_AD2",
+ "GPMC_AD3",
+ "GPMC_AD4",
+ "GPMC_AD5",
+ "GPMC_AD6",
+ "GPMC_AD7",
+ "DCAN1_TX",
+ "DCAN1_RX",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "RGMII2_TCTL",
+ "RGMII2_RCTL",
+ "RGMII2_TD3",
+ "RGMII2_TD2",
+ "RGMII2_TD1",
+ "RGMII2_TD0",
+ "RGMII2_TCLK",
+ "RGMII2_RCLK",
+ "RGMII2_RD3",
+ "RGMII2_RD2",
+ "RGMII2_RD1",
+ "RGMII2_RD0",
+ "PMIC_INT1",
+ "GPMC_CSN0_Flash",
+ "MMC1_CLK",
+ "MMC1_CMD";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "GPMC_CSN3_BUS",
+ "GPMC_CLK",
+ "GPMC_ADVN_ALE",
+ "GPMC_OEN_RE_N",
+ "GPMC_WE_N",
+ "GPMC_BEN0_CLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SW2_0",
+ "SW2_1",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "MMC0_DAT3",
+ "MMC0_DAT2",
+ "MMC0_DAT1",
+ "MMC0_DAT0",
+ "MMC0_CLK",
+ "MMC0_CMD";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "onrisc:red:power",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "WLAN_IRQ",
+ "WLAN_EN",
+ "SW2_2",
+ "SW2_3",
+ "NC",
+ "NC",
+ "NC",
+ "ModeA0",
+ "ModeA1",
+ "ModeA2",
+ "ModeA3",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts
index c6cc1c6218a9..6ed886c3306b 100644
--- a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts
+++ b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts
@@ -93,3 +93,147 @@
ti,dual-emac-pvid = <2>;
phy-handle = <&phy1>;
};
+
+&gpio0 {
+ gpio-line-names =
+ "MDIO",
+ "MDC",
+ "UART2_RX",
+ "UART2_TX",
+ "I2C1_SDA",
+ "I2C1_SCL",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "UART1_CTSN",
+ "UART1_RTSN",
+ "UART1_RX",
+ "UART1_TX",
+ "onrisc:blue:wlan",
+ "onrisc:green:app",
+ "USB0_DRVVBUS",
+ "ETH2_INT",
+ "NC",
+ "NC",
+ "MMC1_DAT0",
+ "MMC1_DAT1",
+ "NC",
+ "NC",
+ "MMC1_DAT2",
+ "MMC1_DAT3",
+ "NC",
+ "NC",
+ "GPMC_WAIT0",
+ "GPMC_WP_N";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "GPMC_AD0",
+ "GPMC_AD1",
+ "GPMC_AD2",
+ "GPMC_AD3",
+ "GPMC_AD4",
+ "GPMC_AD5",
+ "GPMC_AD6",
+ "GPMC_AD7",
+ "NC",
+ "NC",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "UART2_DTR",
+ "UART2_DSR",
+ "UART2_DCD",
+ "UART2_RI",
+ "RGMII2_TCTL",
+ "RGMII2_RCTL",
+ "RGMII2_TD3",
+ "RGMII2_TD2",
+ "RGMII2_TD1",
+ "RGMII2_TD0",
+ "RGMII2_TCLK",
+ "RGMII2_RCLK",
+ "RGMII2_RD3",
+ "RGMII2_RD2",
+ "RGMII2_RD1",
+ "RGMII2_RD0",
+ "PMIC_INT1",
+ "GPMC_CSN0_Flash",
+ "MMC1_CLK",
+ "MMC1_CMD";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "GPMC_CSN3_BUS",
+ "GPMC_CLK",
+ "GPMC_ADVN_ALE",
+ "GPMC_OEN_RE_N",
+ "GPMC_WE_N",
+ "GPMC_BEN0_CLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SW2_0",
+ "SW2_1",
+ "NC",
+ "NC",
+ "UART1_DTR",
+ "UART1_DSR",
+ "UART1_DCD",
+ "UART1_RI",
+ "MMC0_DAT3",
+ "MMC0_DAT2",
+ "MMC0_DAT1",
+ "MMC0_DAT0",
+ "MMC0_CLK",
+ "MMC0_CMD";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "onrisc:red:power",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "UART2_CTSN",
+ "UART2_RTSN",
+ "WLAN_IRQ",
+ "WLAN_EN",
+ "SW2_2",
+ "SW2_3",
+ "NC",
+ "NC",
+ "NC",
+ "ModeA0",
+ "ModeA1",
+ "ModeA2",
+ "ModeA3",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts
index 96dffd3ffd85..ad3adc7679f9 100644
--- a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts
+++ b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts
@@ -71,6 +71,10 @@
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
+ gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
+ "GP_IN4", "GP_IN5", "GP_IN6", "GP_IN7",
+ "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
+ "GP_OUT4", "GP_OUT5", "GP_OUT6", "GP_OUT7";
};
};
@@ -86,6 +90,10 @@
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+ gpio-line-names = "CH1_M0", "CH1_M1", "CH1_M2", "CH1_M3",
+ "CH2_M0", "CH2_M1", "CH2_M2", "CH2_M3",
+ "CH3_M0", "CH3_M1", "CH3_M2", "CH3_M3",
+ "CH4_M0", "CH4_M1", "CH4_M2", "CH4_M3";
};
tca6416c: gpio@21 {
@@ -93,6 +101,10 @@
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
+ gpio-line-names = "CH5_M0", "CH5_M1", "CH5_M2", "CH5_M3",
+ "CH6_M0", "CH6_M1", "CH6_M2", "CH6_M3",
+ "CH7_M0", "CH7_M1", "CH7_M2", "CH7_M3",
+ "CH8_M0", "CH8_M1", "CH8_M2", "CH8_M3";
};
};
@@ -113,3 +125,147 @@
ti,dual-emac-pvid = <2>;
phy-handle = <&phy1>;
};
+
+&gpio0 {
+ gpio-line-names =
+ "MDIO",
+ "MDC",
+ "NC",
+ "NC",
+ "I2C1_SDA",
+ "I2C1_SCL",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "NC",
+ "NC",
+ "onrisc:blue:wlan",
+ "onrisc:green:app",
+ "USB0_DRVVBUS",
+ "ETH2_INT",
+ "NC",
+ "NC",
+ "MMC1_DAT0",
+ "MMC1_DAT1",
+ "NC",
+ "NC",
+ "MMC1_DAT2",
+ "MMC1_DAT3",
+ "NC",
+ "NC",
+ "GPMC_WAIT0",
+ "GPMC_WP_N";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "GPMC_AD0",
+ "GPMC_AD1",
+ "GPMC_AD2",
+ "GPMC_AD3",
+ "GPMC_AD4",
+ "GPMC_AD5",
+ "GPMC_AD6",
+ "GPMC_AD7",
+ "NC",
+ "NC",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "SW2_0_alt",
+ "SW2_1_alt",
+ "SW2_2_alt",
+ "SW2_3_alt",
+ "RGMII2_TCTL",
+ "RGMII2_RCTL",
+ "RGMII2_TD3",
+ "RGMII2_TD2",
+ "RGMII2_TD1",
+ "RGMII2_TD0",
+ "RGMII2_TCLK",
+ "RGMII2_RCLK",
+ "RGMII2_RD3",
+ "RGMII2_RD2",
+ "RGMII2_RD1",
+ "RGMII2_RD0",
+ "PMIC_INT1",
+ "GPMC_CSN0_Flash",
+ "MMC1_CLK",
+ "MMC1_CMD";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "GPMC_CSN3_BUS",
+ "GPMC_CLK",
+ "GPMC_ADVN_ALE",
+ "GPMC_OEN_RE_N",
+ "GPMC_WE_N",
+ "GPMC_BEN0_CLE",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SW2_0",
+ "SW2_1",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "MMC0_DAT3",
+ "MMC0_DAT2",
+ "MMC0_DAT1",
+ "MMC0_DAT0",
+ "MMC0_CLK",
+ "MMC0_CMD";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "onrisc:red:power",
+ "NC",
+ "NC",
+ "NC",
+ "3G_PWR_EN",
+ "NC",
+ "NC",
+ "WLAN_IRQ",
+ "WLAN_EN",
+ "SW2_2",
+ "SW2_3",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi
index 124026fa0d09..67c7fcc52ce6 100644
--- a/arch/arm/boot/dts/am335x-pcm-953.dtsi
+++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi
@@ -12,56 +12,52 @@
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx";
/* Power */
- regulators {
- vcc3v3: fixedregulator@1 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
+ vcc3v3: fixedregulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
- vcc1v8: fixedregulator@2 {
- compatible = "regulator-fixed";
- regulator-name = "vcc1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- };
+ vcc1v8: fixedregulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
};
/* User IO */
- user_leds: user_leds {
+ user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_leds_pins>;
user-led0 {
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "gpio";
default-state = "on";
};
user-led1 {
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "gpio";
default-state = "on";
};
};
- user_buttons: user_buttons {
+ user_buttons: user-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&user_buttons_pins>;
- button@0 {
+ button-0 {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
- button@1 {
+ button-1 {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
@@ -72,14 +68,14 @@
};
&am33xx_pinmux {
- user_buttons_pins: pinmux_user_buttons {
+ user_buttons_pins: pinmux-user-buttons {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */
AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */
>;
};
- user_leds_pins: pinmux_user_leds {
+ user_leds_pins: pinmux-user-leds {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */
@@ -89,7 +85,7 @@
/* CAN */
&am33xx_pinmux {
- dcan1_pins: pinmux_dcan1 {
+ dcan1_pins: pinmux-dcan1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */
AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */
@@ -146,7 +142,7 @@
pinctrl-names = "default";
pinctrl-0 = <&cb_gpio_pins>;
- cb_gpio_pins: pinmux_cb_gpio {
+ cb_gpio_pins: pinmux-cb-gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */
AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */
@@ -156,7 +152,7 @@
/* MMC */
&am33xx_pinmux {
- mmc1_pins: pinmux_mmc1_pins {
+ mmc1_pins: pinmux-mmc1-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
@@ -180,14 +176,14 @@
/* UARTs */
&am33xx_pinmux {
- uart0_pins: pinmux_uart0 {
+ uart0_pins: pinmux-uart0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
>;
};
- uart1_pins: pinmux_uart1 {
+ uart1_pins: pinmux-uart1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
@@ -196,14 +192,14 @@
>;
};
- uart2_pins: pinmux_uart2 {
+ uart2_pins: pinmux-uart2 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */
AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */
>;
};
- uart3_pins: pinmux_uart3 {
+ uart3_pins: pinmux-uart3 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */
AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */
diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts
index b5e88e627bc1..a4509e9e1056 100644
--- a/arch/arm/boot/dts/am335x-pepper.dts
+++ b/arch/arm/boot/dts/am335x-pepper.dts
@@ -555,11 +555,11 @@
};
&usb0 {
- dr_mode = "host";
+ dr_mode = "host";
};
&usb1 {
- dr_mode = "host";
+ dr_mode = "host";
};
&am33xx_pinmux {
@@ -596,24 +596,22 @@
&buttons {
pinctrl-names = "default";
pinctrl-0 = <&user_buttons_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- button0 {
+ button-0 {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
wakeup-source;
};
- button1 {
+ button-1 {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
wakeup-source;
};
- buttons2 {
+ button-2 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi
index f65cd1331315..034dc5181679 100644
--- a/arch/arm/boot/dts/am335x-phycore-som.dtsi
+++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi
@@ -14,6 +14,7 @@
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rtc;
+ rtc2 = &tps;
};
cpus {
@@ -48,7 +49,7 @@
/* EMMC */
&am33xx_pinmux {
- emmc_pins: pinmux_emmc_pins {
+ emmc_pins: pinmux-emmc-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
@@ -124,7 +125,7 @@
/* I2C Busses */
&am33xx_pinmux {
- i2c0_pins: pinmux_i2c0 {
+ i2c0_pins: pinmux-i2c0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
@@ -164,7 +165,7 @@
/* NAND memory */
&am33xx_pinmux {
- nandflash_pins: pinmux_nandflash {
+ nandflash_pins: pinmux-nandflash {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
@@ -202,7 +203,6 @@
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
- gpmc,device-nand = "true";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
@@ -316,7 +316,7 @@
/* SPI Busses */
&am33xx_pinmux {
- spi0_pins: pinmux_spi0 {
+ spi0_pins: pinmux-spi0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
@@ -331,7 +331,7 @@
pinctrl-0 = <&spi0_pins>;
status = "okay";
- serial_flash: m25p80@0 {
+ serial_flash: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <48000000>;
reg = <0x0>;
diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts
index 5e415d8ffdd8..0ba4883cd4ef 100644
--- a/arch/arm/boot/dts/am335x-pocketbeagle.dts
+++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts
@@ -23,28 +23,28 @@
compatible = "gpio-leds";
- usr0 {
+ led-usr0 {
label = "beaglebone:green:usr0";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
- usr1 {
+ led-usr1 {
label = "beaglebone:green:usr1";
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
- usr2 {
+ led-usr2 {
label = "beaglebone:green:usr2";
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "cpu0";
default-state = "off";
};
- usr3 {
+ led-usr3 {
label = "beaglebone:green:usr3";
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
default-state = "off";
diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/am335x-regor.dtsi
index 7b3966ee51b9..3894f14a914c 100644
--- a/arch/arm/boot/dts/am335x-regor.dtsi
+++ b/arch/arm/boot/dts/am335x-regor.dtsi
@@ -18,7 +18,7 @@
};
/* User IO */
- user_leds: user_leds {
+ user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_leds_pins>;
@@ -39,7 +39,7 @@
/* User Leds */
&am33xx_pinmux {
- user_leds_pins: pinmux_user_leds {
+ user_leds_pins: pinmux-user-leds {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */
AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */
@@ -49,7 +49,7 @@
/* CAN Busses */
&am33xx_pinmux {
- dcan1_pins: pinmux_dcan1 {
+ dcan1_pins: pinmux-dcan1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
@@ -65,7 +65,7 @@
/* Ethernet */
&am33xx_pinmux {
- ethernet1_pins: pinmux_ethernet1 {
+ ethernet1_pins: pinmux-ethernet1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
@@ -108,7 +108,7 @@
pinctrl-names = "default";
pinctrl-0 = <&user_gpios_pins>;
- user_gpios_pins: pinmux_user_gpios {
+ user_gpios_pins: pinmux-user-gpios {
pinctrl-single,pins = <
/* DIGIN 1-4 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */
@@ -126,7 +126,7 @@
/* MMC */
&am33xx_pinmux {
- mmc1_pins: pinmux_mmc1 {
+ mmc1_pins: pinmux-mmc1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
@@ -155,14 +155,14 @@
/* UARTs */
&am33xx_pinmux {
- uart0_pins: pinmux_uart0 {
+ uart0_pins: pinmux-uart0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
>;
};
- uart2_pins: pinmux_uart2 {
+ uart2_pins: pinmux-uart2 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */
AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */
@@ -184,7 +184,7 @@
/* RS485 - UART1 */
&am33xx_pinmux {
- uart1_rs485_pins: pinmux_uart1_rs485_pins {
+ uart1_rs485_pins: pinmux-uart1-rs485-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts
index 246a1a9b3e44..a2676d10c24a 100644
--- a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts
+++ b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts
@@ -23,7 +23,7 @@
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- startup-delay-us= <100000>;
+ startup-delay-us = <100000>;
};
};
diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts
index 6b9877560741..c497200f9cb0 100644
--- a/arch/arm/boot/dts/am335x-shc.dts
+++ b/arch/arm/boot/dts/am335x-shc.dts
@@ -36,10 +36,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- back_button {
+ back-button {
label = "Back Button";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_BACK>;
@@ -47,7 +47,7 @@
wakeup-source;
};
- front_button {
+ front-button {
label = "Front Button";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_FRONT>;
diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts
index 6516907ed579..73b5d1a024bd 100644
--- a/arch/arm/boot/dts/am335x-sl50.dts
+++ b/arch/arm/boot/dts/am335x-sl50.dts
@@ -588,7 +588,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- flash: n25q032@1 {
+ flash: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q032";
diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi
index f957fea8208e..6a103f17585b 100644
--- a/arch/arm/boot/dts/am335x-wega.dtsi
+++ b/arch/arm/boot/dts/am335x-wega.dtsi
@@ -8,8 +8,34 @@
model = "Phytec AM335x phyBOARD-WEGA";
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
- sound: sound_iface {
- compatible = "ti,da830-evm-audio";
+ sound: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "snd-wega";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound_iface_main>;
+ simple-audio-card,frame-master = <&sound_iface_main>;
+ simple-audio-card,mclk-fs = <32>;
+ simple-audio-card,widgets =
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "Speaker", "SPOP",
+ "Speaker", "SPOM",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp0>;
+ };
+
+ sound_iface_main: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3007>;
+ clocks = <&mcasp0_fck>;
+ };
+
};
vcc3v3: fixedregulator1 {
@@ -23,7 +49,7 @@
/* Audio */
&am33xx_pinmux {
- mcasp0_pins: pinmux_mcasp0 {
+ mcasp0_pins: pinmux-mcasp0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
@@ -36,6 +62,7 @@
&i2c0 {
tlv320aic3007: tlv320aic3007@18 {
+ #sound-dai-cells = <0>;
compatible = "ti,tlv320aic3007";
reg = <0x18>;
AVDD-supply = <&vcc3v3>;
@@ -47,6 +74,7 @@
};
&mcasp0 {
+ #sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcasp0_pins>;
op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
@@ -59,23 +87,10 @@
status = "okay";
};
-&sound {
- ti,model = "AM335x-Wega";
- ti,audio-codec = <&tlv320aic3007>;
- ti,mcasp-controller = <&mcasp0>;
- ti,audio-routing =
- "Line Out", "LLOUT",
- "Line Out", "RLOUT",
- "LINE1L", "Line In",
- "LINE1R", "Line In";
- clocks = <&mcasp0_fck>;
- clock-names = "mclk";
- status = "okay";
-};
/* CAN Busses */
&am33xx_pinmux {
- dcan1_pins: pinmux_dcan1 {
+ dcan1_pins: pinmux-dcan1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
@@ -91,7 +106,7 @@
/* Ethernet */
&am33xx_pinmux {
- ethernet1_pins: pinmux_ethernet1 {
+ ethernet1_pins: pinmux-ethernet1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
@@ -131,7 +146,7 @@
/* MMC */
&am33xx_pinmux {
- mmc1_pins: pinmux_mmc1 {
+ mmc1_pins: pinmux-mmc1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
@@ -161,14 +176,14 @@
/* UARTs */
&am33xx_pinmux {
- uart0_pins: pinmux_uart0 {
+ uart0_pins: pinmux-uart0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
>;
};
- uart1_pins: pinmux_uart1_pins {
+ uart1_pins: pinmux-uart1 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index b7b7106f2dee..d34483ae1778 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -5,251 +5,288 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&scm_clocks {
- sys_clkin_ck: sys_clkin_ck@40 {
+ sys_clkin_ck: clock-sys-clkin-22@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <22>;
reg = <0x0040>;
};
- adc_tsc_fck: adc_tsc_fck {
+ adc_tsc_fck: clock-adc-tsc-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "adc_tsc_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan0_fck: dcan0_fck {
+ dcan0_fck: clock-dcan0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan1_fck: dcan1_fck {
+ dcan1_fck: clock-dcan1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp0_fck: mcasp0_fck {
+ mcasp0_fck: clock-mcasp0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp1_fck: mcasp1_fck {
+ mcasp1_fck: clock-mcasp1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex0_fck: smartreflex0_fck {
+ smartreflex0_fck: clock-smartreflex0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex1_fck: smartreflex1_fck {
+ smartreflex1_fck: clock-smartreflex1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sha0_fck: sha0_fck {
+ sha0_fck: clock-sha0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sha0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- aes0_fck: aes0_fck {
+ aes0_fck: clock-aes0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "aes0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- rng_fck: rng_fck {
+ rng_fck: clock-rng-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "rng_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <0>;
- reg = <0x0664>;
- };
+ clock@664 {
+ compatible = "ti,clksel";
+ reg = <0x664>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <1>;
- reg = <0x0664>;
- };
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <0>;
+ };
- ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4ls_gclk>;
- ti,bit-shift = <2>;
- reg = <0x0664>;
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <1>;
+ };
+
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
+ clocks = <&l4ls_gclk>;
+ ti,bit-shift = <2>;
+ };
};
};
&prcm_clocks {
- clk_32768_ck: clk_32768_ck {
+ clk_32768_ck: clock-clk-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32768_ck";
clock-frequency = <32768>;
};
- clk_rc32k_ck: clk_rc32k_ck {
+ clk_rc32k_ck: clock-clk-rc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_rc32k_ck";
clock-frequency = <32000>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_24000000_ck: virt_24000000_ck {
+ virt_24000000_ck: clock-virt-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_24000000_ck";
clock-frequency = <24000000>;
};
- virt_25000000_ck: virt_25000000_ck {
+ virt_25000000_ck: clock-virt-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_25000000_ck";
clock-frequency = <25000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- tclkin_ck: tclkin_ck {
+ tclkin_ck: clock-tclkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tclkin_ck";
clock-frequency = <12000000>;
};
- dpll_core_ck: dpll_core_ck@490 {
+ dpll_core_ck: clock@490 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_m4_ck: dpll_core_m4_ck@480 {
+ dpll_core_m4_ck: clock-dpll-core-m4@480 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0480>;
ti,index-starts-at-one;
};
- dpll_core_m5_ck: dpll_core_m5_ck@484 {
+ dpll_core_m5_ck: clock-dpll-core-m5@484 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0484>;
ti,index-starts-at-one;
};
- dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
+ dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x04d8>;
ti,index-starts-at-one;
};
- dpll_mpu_ck: dpll_mpu_ck@488 {
+ dpll_mpu_ck: clock@488 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
reg = <0x04a8>;
ti,index-starts-at-one;
};
- dpll_ddr_ck: dpll_ddr_ck@494 {
+ dpll_ddr_ck: clock@494 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
reg = <0x04a0>;
ti,index-starts-at-one;
};
- dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+ dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_ddr_m2_div2_ck";
clocks = <&dpll_ddr_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- dpll_disp_ck: dpll_disp_ck@498 {
+ dpll_disp_ck: clock@498 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_disp_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
- dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
+ dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_disp_m2_ck";
clocks = <&dpll_disp_ck>;
ti,max-div = <31>;
reg = <0x04a4>;
@@ -257,418 +294,484 @@
ti,set-rate-parent;
};
- dpll_per_ck: dpll_per_ck@48c {
+ dpll_per_ck: clock@48c {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@4ac {
+ dpll_per_m2_ck: clock-dpll-per-m2@4ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x04ac>;
ti,index-starts-at-one;
};
- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- clk_24mhz: clk_24mhz {
+ clk_24mhz: clock-clk-24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clk_24mhz";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
- clkdiv32k_ck: clkdiv32k_ck {
+ clkdiv32k_ck: clock-clkdiv32k {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clkdiv32k_ck";
clocks = <&clk_24mhz>;
clock-mult = <1>;
clock-div = <732>;
};
- l3_gclk: l3_gclk {
+ l3_gclk: clock-l3-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- pruss_ocp_gclk: pruss_ocp_gclk@530 {
+ pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "pruss_ocp_gclk";
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
reg = <0x0530>;
};
- mmu_fck: mmu_fck@914 {
+ mmu_fck: clock-mmu-fck-1@914 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "mmu_fck";
clocks = <&dpll_core_m4_ck>;
ti,bit-shift = <1>;
reg = <0x0914>;
};
- timer1_fck: timer1_fck@528 {
+ timer1_fck: clock-timer1-fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer1_fck";
clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
- timer2_fck: timer2_fck@508 {
+ timer2_fck: clock-timer2-fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer2_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
- timer3_fck: timer3_fck@50c {
+ timer3_fck: clock-timer3-fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer3_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
- timer4_fck: timer4_fck@510 {
+ timer4_fck: clock-timer4-fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer4_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
- timer5_fck: timer5_fck@518 {
+ timer5_fck: clock-timer5-fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer5_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
- timer6_fck: timer6_fck@51c {
+ timer6_fck: clock-timer6-fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer6_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
- timer7_fck: timer7_fck@504 {
+ timer7_fck: clock-timer7-fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer7_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
- usbotg_fck: usbotg_fck@47c {
+ usbotg_fck: clock-usbotg-fck-8@47c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usbotg_fck";
clocks = <&dpll_per_ck>;
ti,bit-shift = <8>;
reg = <0x047c>;
};
- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_core_m4_div2_ck";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- ieee5000_fck: ieee5000_fck@e4 {
+ ieee5000_fck: clock-ieee5000-fck-1@e4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ieee5000_fck";
clocks = <&dpll_core_m4_div2_ck>;
ti,bit-shift = <1>;
reg = <0x00e4>;
};
- wdt1_fck: wdt1_fck@538 {
+ wdt1_fck: clock-wdt1-fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wdt1_fck";
clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
- l4_rtc_gclk: l4_rtc_gclk {
+ l4_rtc_gclk: clock-l4-rtc-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4_rtc_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- l4hs_gclk: l4hs_gclk {
+ l4hs_gclk: clock-l4hs-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4hs_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3s_gclk: l3s_gclk {
+ l3s_gclk: clock-l3s-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3s_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4fw_gclk: l4fw_gclk {
+ l4fw_gclk: clock-l4fw-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4fw_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4ls_gclk: l4ls_gclk {
+ l4ls_gclk: clock-l4ls-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4ls_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sysclk_div_ck: sysclk_div_ck {
+ sysclk_div_ck: clock-sysclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sysclk_div_ck";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_125mhz_gclk";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
+ cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "cpsw_cpts_rft_clk";
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
reg = <0x0520>;
};
- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
+ gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpio0_dbclk_mux_ck";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
- lcd_gclk: lcd_gclk@534 {
+ lcd_gclk: clock-lcd-gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "lcd_gclk";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x0534>;
ti,set-rate-parent;
};
- mmc_clk: mmc_clk {
+ mmc_clk: clock-mmc {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mmc_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
- ti,bit-shift = <1>;
- reg = <0x052c>;
- };
+ clock@52c {
+ compatible = "ti,clksel";
+ reg = <0x52c>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- gfx_fck_div_ck: gfx_fck_div_ck@52c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&gfx_fclk_clksel_ck>;
- reg = <0x052c>;
- ti,max-div = <2>;
- };
+ gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "gfx_fclk_clksel_ck";
+ clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+ ti,bit-shift = <1>;
+ };
- sysclkout_pre_ck: sysclkout_pre_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
- reg = <0x0700>;
+ gfx_fck_div_ck: clock-gfx-fck-div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "gfx_fck_div_ck";
+ clocks = <&gfx_fclk_clksel_ck>;
+ ti,max-div = <2>;
+ };
};
- clkout2_div_ck: clkout2_div_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sysclkout_pre_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <8>;
- reg = <0x0700>;
- };
+ clock@700 {
+ compatible = "ti,clksel";
+ reg = <0x700>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- clkout2_ck: clkout2_ck@700 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout2_div_ck>;
- ti,bit-shift = <7>;
- reg = <0x0700>;
+ sysclkout_pre_ck: clock-sysclkout-pre {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "sysclkout_pre_ck";
+ clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+ };
+
+ clkout2_div_ck: clock-clkout2-div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "clkout2_div_ck";
+ clocks = <&sysclkout_pre_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <8>;
+ };
+
+ clkout2_ck: clock-clkout2 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_ck";
+ clocks = <&clkout2_div_ck>;
+ ti,bit-shift = <7>;
+ };
};
};
&prcm {
- per_cm: per-cm@0 {
+ per_cm: clock@0 {
compatible = "ti,omap4-cm";
+ clock-output-names = "per_cm";
reg = <0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x400>;
- l4ls_clkctrl: l4ls-clkctrl@38 {
+ l4ls_clkctrl: clock@38 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4ls_clkctrl";
reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
#clock-cells = <2>;
};
- l3s_clkctrl: l3s-clkctrl@1c {
+ l3s_clkctrl: clock@1c {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_clkctrl";
reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
#clock-cells = <2>;
};
- l3_clkctrl: l3-clkctrl@24 {
+ l3_clkctrl: clock@24 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_clkctrl";
reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
#clock-cells = <2>;
};
- l4hs_clkctrl: l4hs-clkctrl@120 {
+ l4hs_clkctrl: clock@120 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4hs_clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
- pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
+ pruss_ocp_clkctrl: clock@e8 {
compatible = "ti,clkctrl";
+ clock-output-names = "pruss_ocp_clkctrl";
reg = <0xe8 0x4>;
#clock-cells = <2>;
};
- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
+ cpsw_125mhz_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "cpsw_125mhz_clkctrl";
reg = <0x0 0x18>;
#clock-cells = <2>;
};
- lcdc_clkctrl: lcdc-clkctrl@18 {
+ lcdc_clkctrl: clock@18 {
compatible = "ti,clkctrl";
+ clock-output-names = "lcdc_clkctrl";
reg = <0x18 0x4>;
#clock-cells = <2>;
};
- clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
+ clk_24mhz_clkctrl: clock@14c {
compatible = "ti,clkctrl";
+ clock-output-names = "clk_24mhz_clkctrl";
reg = <0x14c 0x4>;
#clock-cells = <2>;
};
};
- wkup_cm: wkup-cm@400 {
+ wkup_cm: clock@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkup_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
+ l4_wkup_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x0 0x10>, <0xb4 0x24>;
#clock-cells = <2>;
};
- l3_aon_clkctrl: l3-aon-clkctrl@14 {
+ l3_aon_clkctrl: clock@14 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_aon_clkctrl";
reg = <0x14 0x4>;
#clock-cells = <2>;
};
- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
+ l4_wkup_aon_clkctrl: clock@b0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_aon_clkctrl";
reg = <0xb0 0x4>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu-cm@600 {
+ mpu_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- mpu_clkctrl: mpu-clkctrl@0 {
+ mpu_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4-rtc-cm@800 {
+ l4_rtc_cm: clock@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_rtc_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
- l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
+ l4_rtc_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_rtc_clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx-l3-cm@900 {
+ gfx_l3_cm: clock@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gfx_l3_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
+ gfx_l3_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "gfx_l3_clkctrl";
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_cefuse_cm: l4-cefuse-cm@a00 {
+ l4_cefuse_cm: clock@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_cefuse_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
+ l4_cefuse_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_cefuse_clkctrl";
reg = <0x0 0x24>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index c9629cb5ccd1..7e50fe633d8a 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -263,6 +263,8 @@
compatible = "ti,am3359-tscadc";
reg = <0x0 0x1000>;
interrupts = <16>;
+ clocks = <&adc_tsc_fck>;
+ clock-names = "fck";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
@@ -1500,8 +1502,7 @@
mmc1: mmc@0 {
compatible = "ti,am335-sdhci";
ti,needs-special-reset;
- dmas = <&edma_xbar 24 0 0
- &edma_xbar 25 0 0>;
+ dmas = <&edma 24 0>, <&edma 25 0>;
dma-names = "tx", "rx";
interrupts = <64>;
reg = <0x0 0x1000>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f6ec85d58dd1..32d397b3950b 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for AM33XX SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
@@ -461,8 +458,11 @@
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <30>;
+ dma-channels = <30>;
#dma-requests = <256>;
+ dma-requests = <256>;
};
};
diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi
index 7d8f32bf70db..75ad42179aee 100644
--- a/arch/arm/boot/dts/am3517-evm-ui.dtsi
+++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi
@@ -70,61 +70,61 @@
compatible = "gpio-keys-polled";
poll-interval = <100>;
- record {
+ key-record {
label = "Record";
/* linux,code = <BTN_0>; */
gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
};
- play {
+ key-play {
label = "Play";
linux,code = <KEY_PLAY>;
gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
};
- Stop {
+ key-stop {
label = "Stop";
linux,code = <KEY_STOP>;
gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
};
- fwd {
+ key-fwd {
label = "FWD";
linux,code = <KEY_FASTFORWARD>;
gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
};
- rwd {
+ key-rwd {
label = "RWD";
linux,code = <KEY_REWIND>;
gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
};
- shift {
+ key-shift {
label = "Shift";
linux,code = <KEY_LEFTSHIFT>;
gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
};
- Mode {
+ key-mode {
label = "Mode";
linux,code = <BTN_MODE>;
gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
};
- Menu {
+ key-menu {
label = "Menu";
linux,code = <KEY_MENU>;
gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
};
- Up {
+ key-up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
};
- Down {
+ key-down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
@@ -137,14 +137,14 @@
tlv320aic23_1: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
- #sound-dai-cells= <0>;
+ #sound-dai-cells = <0>;
status = "okay";
};
tlv320aic23_2: codec@1b {
compatible = "ti,tlv320aic23";
reg = <0x1b>;
- #sound-dai-cells= <0>;
+ #sound-dai-cells = <0>;
status = "okay";
};
};
@@ -154,7 +154,7 @@
tlv320aic23_3: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
- #sound-dai-cells= <0>;
+ #sound-dai-cells = <0>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index 0d2fac98ce7d..11618aa501fc 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -26,66 +26,66 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
- vmmc_fixed: vmmc {
- compatible = "regulator-fixed";
- regulator-name = "vmmc_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+ vmmc_fixed: vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
gpio-keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
- user_pb {
+ button-user {
label = "User Push Button";
linux,code = <BTN_0>;
gpios = <&tca6416 5 GPIO_ACTIVE_LOW>;
};
- user_sw_1 {
+ switch-1 {
label = "User Switch 1";
linux,code = <BTN_1>;
gpios = <&tca6416 8 GPIO_ACTIVE_LOW>;
};
- user_sw_2 {
+ switch-2 {
label = "User Switch 2";
linux,code = <BTN_2>;
gpios = <&tca6416 9 GPIO_ACTIVE_LOW>;
};
- user_sw_3 {
+ switch-3 {
label = "User Switch 3";
linux,code = <BTN_3>;
gpios = <&tca6416 10 GPIO_ACTIVE_LOW>;
};
- user_sw_4 {
+ switch-4 {
label = "User Switch 4";
linux,code = <BTN_4>;
gpios = <&tca6416 11 GPIO_ACTIVE_LOW>;
};
- user_sw_5 {
+ switch-5 {
label = "User Switch 5";
linux,code = <BTN_5>;
gpios = <&tca6416 12 GPIO_ACTIVE_LOW>;
};
- user_sw_6 {
+ switch-6 {
label = "User Switch 6";
linux,code = <BTN_6>;
gpios = <&tca6416 13 GPIO_ACTIVE_LOW>;
};
- user_sw_7 {
+ switch-7 {
label = "User Switch 7";
linux,code = <BTN_7>;
gpios = <&tca6416 14 GPIO_ACTIVE_LOW>;
};
- user_sw_8 {
+ switch-8 {
label = "User Switch 8";
linux,code = <BTN_8>;
gpios = <&tca6416 15 GPIO_ACTIVE_LOW>;
@@ -150,7 +150,7 @@
enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */
};
- pwm11: dmtimer-pwm@11 {
+ pwm11: pwm-11 {
compatible = "ti,omap-dmtimer-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
@@ -161,6 +161,8 @@
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_rst_pins>;
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
#phy-cells = <0>;
@@ -168,11 +170,13 @@
};
&davinci_emac {
- status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ethernet_pins>;
+ status = "okay";
};
&davinci_mdio {
- status = "okay";
+ status = "okay";
};
&dss {
@@ -193,6 +197,8 @@
};
&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
/* User DIP swithes [1:8] / User LEDS [1:2] */
tca6416: gpio@21 {
@@ -205,6 +211,8 @@
};
&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
};
@@ -219,10 +227,12 @@
};
&mmc3 {
- status = "disabled";
+ status = "disabled";
};
&usbhshost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_pins>;
port1-mode = "ehci-phy";
};
@@ -231,8 +241,35 @@
};
&omap3_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb1_rst_pins>;
+
+ ethernet_pins: pinmux_ethernet_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */
+ OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */
+ OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */
+ OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */
+ OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */
+ OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */
+ OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */
+ OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */
+ OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */
+ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
+ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
+ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
@@ -300,8 +337,6 @@
};
&omap3_pmx_core2 {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb1_pins>;
hsusb1_pins: pinmux_hsusb1_pins {
pinctrl-single,pins = <
diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi
index 8b669e2eafec..f7b680f6c48a 100644
--- a/arch/arm/boot/dts/am3517-som.dtsi
+++ b/arch/arm/boot/dts/am3517-som.dtsi
@@ -69,6 +69,8 @@
};
&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
s35390a: s35390a@30 {
@@ -179,6 +181,13 @@
&omap3_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+ >;
+ };
+
wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index de33c4f89f33..823f63502e9f 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for am3517 SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "omap3.dtsi"
@@ -52,13 +49,35 @@
};
ocp@68000000 {
- am35x_otg_hs: am35x_otg_hs@5c040000 {
- compatible = "ti,omap3-musb";
- ti,hwmods = "am35x_otg_hs";
- status = "disabled";
- reg = <0x5c040000 0x1000>;
- interrupts = <71>;
- interrupt-names = "mc";
+ target-module@5c040000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5c040400 0x4>,
+ <0x5c040404 0x4>,
+ <0x5c040408 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&hsotgusb_ick_am35xx>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5c040000 0x1000>;
+
+ am35x_otg_hs: am35x_otg_hs@0 {
+ compatible = "ti,omap3-musb";
+ status = "disabled";
+ reg = <0 0x1000>;
+ interrupts = <71>;
+ interrupt-names = "mc";
+ };
};
davinci_emac: ethernet@5c000000 {
@@ -157,7 +176,7 @@
};
/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
-&usb_otg_hs {
+&usb_otg_target {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index 220d0a52797e..0ee7afaa0e8e 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -62,12 +62,27 @@
};
};
&cm_clocks {
- ipss_ick: ipss_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,am35xx-interface-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <4>;
+ clock@a10 {
+ compatible = "ti,clksel";
+ reg = <0xa10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ ipss_ick: clock-ipss-ick {
+ #clock-cells = <0>;
+ compatible = "ti,am35xx-interface-clock";
+ clock-output-names = "ipss_ick";
+ clocks = <&core_l3_ick>;
+ ti,bit-shift = <4>;
+ };
+
+ uart4_ick_am35xx: clock-uart4-ick-am35xx {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "uart4_ick_am35xx";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <23>;
+ };
};
rmii_ck: rmii_ck {
@@ -82,20 +97,19 @@
clock-frequency = <27000000>;
};
- uart4_ick_am35xx: uart4_ick_am35xx@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <23>;
- };
+ clock@a00 {
+ compatible = "ti,clksel";
+ reg = <0xa00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- uart4_fck_am35xx: uart4_fck_am35xx@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <23>;
+ uart4_fck_am35xx: clock-uart4-fck-am35xx {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "uart4_fck_am35xx";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <23>;
+ };
};
};
diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts
index 9423e9feaa10..791478e81c5a 100644
--- a/arch/arm/boot/dts/am3874-iceboard.dts
+++ b/arch/arm/boot/dts/am3874-iceboard.dts
@@ -106,7 +106,7 @@
* "i2c-mux-idle-disconnect" is important.
*/
- pca9548@70 {
+ i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
@@ -213,7 +213,7 @@
u48: pca9575@22 {
compatible = "nxp,pca9575";
- reg=<0x22>;
+ reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
@@ -232,7 +232,7 @@
u59: pca9575@23 {
compatible = "nxp,pca9575";
- reg=<0x23>;
+ reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
@@ -256,7 +256,7 @@
};
&i2c2 {
- pca9548@71 {
+ i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
@@ -434,7 +434,7 @@
};
&mcspi1 {
- s25fl256@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 61a1d88f9df6..8613355bbd5e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for AM4372 SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts
index 3e3354780db8..0861e868b75a 100644
--- a/arch/arm/boot/dts/am437x-cm-t43.dts
+++ b/arch/arm/boot/dts/am437x-cm-t43.dts
@@ -302,7 +302,7 @@
&edma 17 0>;
dma-names = "tx0", "rx0";
- flash: w25q64cvzpig@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 4416ddb559e4..46d5361fe876 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -1127,6 +1127,11 @@
cpu0-supply = <&dcdc2>;
};
+&wkup_m3_ipc {
+ ti,set-io-isolation;
+ firmware-name = "am43x-evm-scale-data.bin";
+};
+
&pruss1_mdio {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index 53f64e3ce735..e46cf2a9d075 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -98,14 +98,12 @@
vin-supply = <&v1_5dreg>;
};
- gpio_keys: gpio_keys {
+ gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins_default>;
- #address-cells = <1>;
- #size-cells = <0>;
- switch0 {
+ switch-0 {
label = "power-button";
linux,code = <KEY_POWER>;
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
@@ -437,7 +435,7 @@
pinctrl-1 = <&qspi_pins_sleep>;
spi-max-frequency = <48000000>;
- m25p80@0 {
+ flash@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
@@ -454,7 +452,7 @@
*/
partition@0 {
label = "QSPI.U_BOOT";
- reg = <0x00000000 0x000080000>;
+ reg = <0x00000000 0x00080000>;
};
partition@1 {
label = "QSPI.U_BOOT.backup";
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
index 8f2268c02778..415210b034ef 100644
--- a/arch/arm/boot/dts/am437x-l4.dtsi
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -2407,7 +2407,7 @@
adc {
#io-channel-cells = <1>;
- compatible ="ti,am4372-adc";
+ compatible = "ti,am4372-adc";
};
};
};
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 20a34d2d85df..511a02e13e2c 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -746,7 +746,7 @@
pinctrl-0 = <&qspi_pins>;
spi-max-frequency = <48000000>;
- m25p80@0 {
+ flash@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
@@ -763,7 +763,7 @@
*/
partition@0 {
label = "QSPI.U_BOOT";
- reg = <0x00000000 0x000080000>;
+ reg = <0x00000000 0x00080000>;
};
partition@1 {
label = "QSPI.U_BOOT.backup";
@@ -893,6 +893,10 @@
};
};
+&wkup_m3_ipc {
+ firmware-name = "am43x-evm-scale-data.bin";
+};
+
&pruss1_mdio {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 4f9a7251a107..9fc915a2582e 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -902,7 +902,7 @@
pinctrl-1 = <&qspi1_pins_sleep>;
spi-max-frequency = <48000000>;
- m25p80@0 {
+ flash@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
@@ -919,7 +919,7 @@
*/
partition@0 {
label = "QSPI.U_BOOT";
- reg = <0x00000000 0x000080000>;
+ reg = <0x00000000 0x00080000>;
};
partition@1 {
label = "QSPI.U_BOOT.backup";
@@ -1019,6 +1019,10 @@
cpu0-supply = <&dcdc2>;
};
+&wkup_m3_ipc {
+ firmware-name = "am43x-evm-scale-data.bin";
+};
+
&pruss1_mdio {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 66e892fa3398..9a5437b3d6a8 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -5,217 +5,246 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&scm_clocks {
- sys_clkin_ck: sys_clkin_ck@40 {
+ sys_clkin_ck: clock-sys-clkin-31@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
ti,bit-shift = <31>;
reg = <0x0040>;
};
- crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
+ crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "crystal_freq_sel_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <29>;
reg = <0x0040>;
};
- sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
+ sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sysboot_freq_sel_ck";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <22>;
reg = <0x0040>;
};
- adc_tsc_fck: adc_tsc_fck {
+ adc_tsc_fck: clock-adc-tsc-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "adc_tsc_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan0_fck: dcan0_fck {
+ dcan0_fck: clock-dcan0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dcan1_fck: dcan1_fck {
+ dcan1_fck: clock-dcan1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dcan1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp0_fck: mcasp0_fck {
+ mcasp0_fck: clock-mcasp0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- mcasp1_fck: mcasp1_fck {
+ mcasp1_fck: clock-mcasp1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex0_fck: smartreflex0_fck {
+ smartreflex0_fck: clock-smartreflex0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- smartreflex1_fck: smartreflex1_fck {
+ smartreflex1_fck: clock-smartreflex1-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex1_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- sha0_fck: sha0_fck {
+ sha0_fck: clock-sha0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sha0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- aes0_fck: aes0_fck {
+ aes0_fck: clock-aes0-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "aes0_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- rng_fck: rng_fck {
+ rng_fck: clock-rng-fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "rng_fck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
- ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
- ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
- ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
+ ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm3_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
- ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
+ ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm4_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
- ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
+ ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm5_tbclk";
clocks = <&l4ls_gclk>;
ti,bit-shift = <6>;
reg = <0x0664>;
};
};
&prcm_clocks {
- clk_32768_ck: clk_32768_ck {
+ clk_32768_ck: clock-clk-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32768_ck";
clock-frequency = <32768>;
};
- clk_rc32k_ck: clk_rc32k_ck {
+ clk_rc32k_ck: clock-clk-rc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_rc32k_ck";
clock-frequency = <32768>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_24000000_ck: virt_24000000_ck {
+ virt_24000000_ck: clock-virt-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_24000000_ck";
clock-frequency = <24000000>;
};
- virt_25000000_ck: virt_25000000_ck {
+ virt_25000000_ck: clock-virt-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_25000000_ck";
clock-frequency = <25000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- tclkin_ck: tclkin_ck {
+ tclkin_ck: clock-tclkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tclkin_ck";
clock-frequency = <26000000>;
};
- dpll_core_ck: dpll_core_ck@2d20 {
+ dpll_core_ck: clock@2d20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
+ dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -224,9 +253,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
+ dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -235,9 +265,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
+ dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -246,16 +277,18 @@
ti,invert-autoidle-bit;
};
- dpll_mpu_ck: dpll_mpu_ck@2d60 {
+ dpll_mpu_ck: clock@2d60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -264,24 +297,27 @@
ti,invert-autoidle-bit;
};
- mpu_periphclk: mpu_periphclk {
+ mpu_periphclk: clock-mpu-periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_periphclk";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- dpll_ddr_ck: dpll_ddr_ck@2da0 {
+ dpll_ddr_ck: clock@2da0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -290,16 +326,18 @@
ti,invert-autoidle-bit;
};
- dpll_disp_ck: dpll_disp_ck@2e20 {
+ dpll_disp_ck: clock@2e20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_disp_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
- dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
+ dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_disp_m2_ck";
clocks = <&dpll_disp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -309,16 +347,18 @@
ti,set-rate-parent;
};
- dpll_per_ck: dpll_per_ck@2de0 {
+ dpll_per_ck: clock@2de0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
+ dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -327,119 +367,135 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+ dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+ dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_ck";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- clk_24mhz: clk_24mhz {
+ clk_24mhz: clock-clk-24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clk_24mhz";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
- clkdiv32k_ck: clkdiv32k_ck {
+ clkdiv32k_ck: clock-clkdiv32k {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "clkdiv32k_ck";
clocks = <&clk_24mhz>;
clock-mult = <1>;
clock-div = <732>;
};
- clkdiv32k_ick: clkdiv32k_ick@2a38 {
+ clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkdiv32k_ick";
clocks = <&clkdiv32k_ck>;
ti,bit-shift = <8>;
reg = <0x2a38>;
};
- sysclk_div: sysclk_div {
+ sysclk_div: clock-sysclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sysclk_div";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- pruss_ocp_gclk: pruss_ocp_gclk@4248 {
+ pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "pruss_ocp_gclk";
clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
reg = <0x4248>;
};
- clk_32k_tpm_ck: clk_32k_tpm_ck {
+ clk_32k_tpm_ck: clock-clk-32k-tpm {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32k_tpm_ck";
clock-frequency = <32768>;
};
- timer1_fck: timer1_fck@4200 {
+ timer1_fck: clock-timer1-fck@4200 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer1_fck";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4200>;
};
- timer2_fck: timer2_fck@4204 {
+ timer2_fck: clock-timer2-fck@4204 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer2_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4204>;
};
- timer3_fck: timer3_fck@4208 {
+ timer3_fck: clock-timer3-fck@4208 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer3_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4208>;
};
- timer4_fck: timer4_fck@420c {
+ timer4_fck: clock-timer4-fck@420c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer4_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x420c>;
};
- timer5_fck: timer5_fck@4210 {
+ timer5_fck: clock-timer5-fck@4210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer5_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4210>;
};
- timer6_fck: timer6_fck@4214 {
+ timer6_fck: clock-timer6-fck@4214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer6_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4214>;
};
- timer7_fck: timer7_fck@4218 {
+ timer7_fck: clock-timer7-fck@4218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer7_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4218>;
};
- wdt1_fck: wdt1_fck@422c {
+ wdt1_fck: clock-wdt1-fck@422c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wdt1_fck";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
reg = <0x422c>;
};
@@ -451,125 +507,141 @@
reg = <0x424c>;
};
- l3_gclk: l3_gclk {
+ l3_gclk: clock-l3-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+ dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_core_m4_div2_ck";
clocks = <&sysclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- l4hs_gclk: l4hs_gclk {
+ l4hs_gclk: clock-l4hs-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4hs_gclk";
clocks = <&dpll_core_m4_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3s_gclk: l3s_gclk {
+ l3s_gclk: clock-l3s-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3s_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l4ls_gclk: l4ls_gclk {
+ l4ls_gclk: clock-l4ls-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4ls_gclk";
clocks = <&dpll_core_m4_div2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_125mhz_gclk";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
+ cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "cpsw_cpts_rft_clk";
clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
reg = <0x4238>;
};
- dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
+ dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_clksel_mac_clk";
clocks = <&dpll_core_m5_ck>;
reg = <0x4234>;
ti,bit-shift = <2>;
ti,dividers = <2>, <5>;
};
- clk_32k_mosc_ck: clk_32k_mosc_ck {
+ clk_32k_mosc_ck: clock-clk-32k-mosc {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "clk_32k_mosc_ck";
clock-frequency = <32768>;
};
- gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
+ gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpio0_dbclk_mux_ck";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
reg = <0x4240>;
};
- mmc_clk: mmc_clk {
+ mmc_clk: clock-mmc {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mmc_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
+ gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gfx_fclk_clksel_ck";
clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
reg = <0x423c>;
};
- gfx_fck_div_ck: gfx_fck_div_ck@423c {
+ gfx_fck_div_ck: clock-gfx-fck-div@423c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gfx_fck_div_ck";
clocks = <&gfx_fclk_clksel_ck>;
reg = <0x423c>;
ti,max-div = <2>;
};
- disp_clk: disp_clk@4244 {
+ disp_clk: clock-disp@4244 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "disp_clk";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x4244>;
ti,set-rate-parent;
};
- dpll_extdev_ck: dpll_extdev_ck@2e60 {
+ dpll_extdev_ck: clock@2e60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_extdev_ck";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
- dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
+ dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_extdev_m2_ck";
clocks = <&dpll_extdev_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -578,66 +650,75 @@
ti,invert-autoidle-bit;
};
- mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
+ mux_synctimer32k_ck: clock-mux-synctimer32k@4230 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mux_synctimer32k_ck";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
reg = <0x4230>;
};
- timer8_fck: timer8_fck@421c {
+ timer8_fck: clock-timer8-fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer8_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x421c>;
};
- timer9_fck: timer9_fck@4220 {
+ timer9_fck: clock-timer9-fck@4220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer9_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4220>;
};
- timer10_fck: timer10_fck@4224 {
+ timer10_fck: clock-timer10-fck@4224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer10_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4224>;
};
- timer11_fck: timer11_fck@4228 {
+ timer11_fck: clock-timer11-fck@4228 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "timer11_fck";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4228>;
};
- cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+ cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_50m_clkdiv";
clocks = <&dpll_core_m5_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+ cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_5m_clkdiv";
clocks = <&cpsw_50m_clkdiv>;
clock-mult = <1>;
clock-div = <10>;
};
- dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_ddr_x2_ck";
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
+ dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m4_ck";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -646,9 +727,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
+ dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
+ clock-output-names = "dpll_per_clkdcoldo";
clocks = <&dpll_per_ck>;
ti,clock-mult = <1>;
ti,clock-div = <1>;
@@ -657,91 +739,102 @@
ti,invert-autoidle-bit;
};
- dll_aging_clk_div: dll_aging_clk_div@4250 {
+ dll_aging_clk_div: clock-dll-aging-clk-div@4250 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dll_aging_clk_div";
clocks = <&sys_clkin_ck>;
reg = <0x4250>;
ti,dividers = <8>, <16>, <32>;
};
- div_core_25m_ck: div_core_25m_ck {
+ div_core_25m_ck: clock-div-core-25m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "div_core_25m_ck";
clocks = <&sysclk_div>;
clock-mult = <1>;
clock-div = <8>;
};
- func_12m_clk: func_12m_clk {
+ func_12m_clk: clock-func-12m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
- vtp_clk_div: vtp_clk_div {
+ vtp_clk_div: clock-vtp-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "vtp_clk_div";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
+ usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "usbphy_32khz_clkmux";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4260>;
};
- usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
+ usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy0_always_on_clk32k";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a40>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
+ usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy1_always_on_clk32k";
clocks = <&usbphy_32khz_clkmux>;
ti,bit-shift = <8>;
reg = <0x2a48>;
};
- clkout1_osc_div_ck: clkout1-osc-div-ck {
+ clkout1_osc_div_ck: clock-clkout1-osc-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_osc_div_ck";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
- clkout1_src2_mux_ck: clkout1-src2-mux-ck {
+ clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkout1_src2_mux_ck";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
- clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
+ clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_src2_pre_div_ck";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
- clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
+ clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "clkout1_src2_post_div_ck";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
@@ -749,18 +842,20 @@
reg = <0x4100>;
};
- clkout1_mux_ck: clkout1-mux-ck {
+ clkout1_mux_ck: clock-clkout1-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkout1_mux_ck";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
- clkout1_ck: clkout1-ck {
+ clkout1_ck: clock-clkout1-ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkout1_ck";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
@@ -768,120 +863,138 @@
};
&prcm {
- wkup_cm: wkup-cm@2800 {
+ wkup_cm: clock@2800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkup_cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
- l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
+ l3s_tsc_clkctrl: clock@120 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_tsc_clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
- l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
+ l4_wkup_aon_clkctrl: clock@228 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_aon_clkctrl";
reg = <0x228 0xc>;
#clock-cells = <2>;
};
- l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
+ l4_wkup_clkctrl: clock@220 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x220 0x4>, <0x328 0x44>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu-cm@8300 {
+ mpu_cm: clock@8300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
- mpu_clkctrl: mpu-clkctrl@20 {
+ mpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx-l3-cm@8400 {
+ gfx_l3_cm: clock@8400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gfx_l3_cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
- gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
+ gfx_l3_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gfx_l3_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4-rtc-cm@8500 {
+ l4_rtc_cm: clock@8500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_rtc_cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
- l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
+ l4_rtc_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_rtc_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- per_cm: per-cm@8800 {
+ per_cm: clock@8800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "per_cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
- l3_clkctrl: l3-clkctrl@20 {
+ l3_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_clkctrl";
reg = <0x20 0x3c>, <0x78 0x2c>;
#clock-cells = <2>;
};
- l3s_clkctrl: l3s-clkctrl@68 {
+ l3s_clkctrl: clock@68 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3s_clkctrl";
reg = <0x68 0xc>, <0x220 0x4c>;
#clock-cells = <2>;
};
- pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
+ pruss_ocp_clkctrl: clock@320 {
compatible = "ti,clkctrl";
+ clock-output-names = "pruss_ocp_clkctrl";
reg = <0x320 0x4>;
#clock-cells = <2>;
};
- l4ls_clkctrl: l4ls-clkctrl@420 {
+ l4ls_clkctrl: clock@420 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4ls_clkctrl";
reg = <0x420 0x1a4>;
#clock-cells = <2>;
};
- emif_clkctrl: emif-clkctrl@720 {
+ emif_clkctrl: clock@720 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x720 0x4>;
#clock-cells = <2>;
};
- dss_clkctrl: dss-clkctrl@a20 {
+ dss_clkctrl: clock@a20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0xa20 0x4>;
#clock-cells = <2>;
};
- cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
+ cpsw_125mhz_clkctrl: clock@b20 {
compatible = "ti,clkctrl";
+ clock-output-names = "cpsw_125mhz_clkctrl";
reg = <0xb20 0x4>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/am571x-idk-touchscreen.dtso b/arch/arm/boot/dts/am571x-idk-touchscreen.dtso
new file mode 100644
index 000000000000..c051ee6c1130
--- /dev/null
+++ b/arch/arm/boot/dts/am571x-idk-touchscreen.dtso
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen: edt-ft5506@38 {
+ compatible = "edt,edt-ft5506", "edt,edt-ft5x06";
+
+ reg = <0x38>;
+
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+
+ /* GPIO line is inverted before going to touch panel */
+ reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+
+ touchscreen-size-x = <1920>;
+ touchscreen-size-y = <1200>;
+
+ wakeup-source;
+ };
+};
diff --git a/arch/arm/boot/dts/am572x-idk-touchscreen.dtso b/arch/arm/boot/dts/am572x-idk-touchscreen.dtso
new file mode 100644
index 000000000000..573e932b1239
--- /dev/null
+++ b/arch/arm/boot/dts/am572x-idk-touchscreen.dtso
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen: edt-ft5506@38 {
+ compatible = "edt,edt-ft5506", "edt,edt-ft5x06";
+
+ reg = <0x38>;
+
+ interrupt-parent = <&gpio3>;
+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+
+ /* GPIO line is inverted before going to touch panel */
+ reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+
+ touchscreen-size-x = <1920>;
+ touchscreen-size-y = <1200>;
+
+ wakeup-source;
+ };
+};
diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi
index c260aa1a85bd..a1f029e9d1f3 100644
--- a/arch/arm/boot/dts/am5748.dtsi
+++ b/arch/arm/boot/dts/am5748.dtsi
@@ -25,6 +25,10 @@
status = "disabled";
};
+&usb4_tm {
+ status = "disabled";
+};
+
&atl_tm {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts
index 6dff3660bf09..47b9174d2353 100644
--- a/arch/arm/boot/dts/am574x-idk.dts
+++ b/arch/arm/boot/dts/am574x-idk.dts
@@ -18,7 +18,7 @@
&qspi {
spi-max-frequency = <96000000>;
- m25p80@0 {
+ flash@0 {
spi-max-frequency = <96000000>;
};
};
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index 2e94f32d9dfc..2fc9a5d5e0c0 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -491,7 +491,7 @@
spi-max-frequency = <48000000>;
- spi_flash: spi_flash@0 {
+ spi_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/am57xx-evm.dtso b/arch/arm/boot/dts/am57xx-evm.dtso
new file mode 100644
index 000000000000..12385a31061e
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-evm.dtso
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT overlay for AM57xx GP EVM boards
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+&{/} {
+ compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+ model = "TI AM5728 EVM";
+
+ aliases {
+ display0 = "/display";
+ display1 = "/connector"; // Fixme: &lcd0 and &hdmi0 could be
+ // resolved here correcly based on
+ // information in the base dtb symbol
+ // table with a fix in dtc
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user1 {
+ gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ label = "USER1";
+ linux,code = <BTN_1>;
+ };
+
+ button-user2 {
+ gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
+ label = "USER2";
+ linux,code = <BTN_2>;
+ };
+
+ button-user3 {
+ gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ label = "USER3";
+ linux,code = <BTN_3>;
+ };
+
+ button-user4 {
+ gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ label = "USER4";
+ linux,code = <BTN_4>;
+ };
+
+ button-user5 {
+ gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+ label = "USER5";
+ linux,code = <BTN_5>;
+ };
+ };
+
+ lcd0: display {
+ compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
+ backlight = <&lcd_bl>;
+ enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ label = "lcd";
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ };
+
+ lcd_bl: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 243 245 247 249 251 252 253 255>;
+ default-brightness-level = <8>;
+ pwms = <&ehrpwm1 0 50000 0>;
+ };
+};
+
+&ehrpwm1 {
+ status = "okay";
+};
+
+&epwmss1 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@5c {
+ compatible = "pixcir,pixcir_tangoc";
+ attb-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0x5c>;
+ reset-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ };
+};
+
+&uart8 {
+ status = "okay";
+};
+
+&dss {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpi_out: endpoint {
+ data-lines = <24>;
+ remote-endpoint = <&lcd_in>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 9fcb8944aa3e..7f092a8811e8 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -526,7 +526,7 @@
status = "okay";
spi-max-frequency = <76800000>;
- m25p80@0 {
+ flash@0 {
compatible = "s25fl256s1", "jedec,spi-nor";
spi-max-frequency = <76800000>;
reg = <0>;
@@ -542,7 +542,7 @@
*/
partition@0 {
label = "QSPI.SPL";
- reg = <0x00000000 0x000040000>;
+ reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "QSPI.u-boot";
diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso
new file mode 100644
index 000000000000..25d74e9f3c9e
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ aliases {
+ display0 = "/display";
+ display1 = "/connector";
+ };
+
+ lcd_bl: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ecap0 0 50000 1>;
+ brightness-levels = <0 51 53 56 62 75 101 152 255>;
+ default-brightness-level = <8>;
+ };
+};
+
+&dsi_bridge {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lcd: display {
+ compatible = "osddisplays,osd101t2045-53ts";
+ reg = <0>;
+
+ label = "lcd";
+
+ backlight = <&lcd_bl>;
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&dsi_bridge_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&lcd_in>;
+ };
+ };
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&ecap0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso
new file mode 100644
index 000000000000..8cea7ba32487
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/} {
+ aliases {
+ display0 = "/display";
+ display1 = "/connector";
+ };
+
+ lcd_bl: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ecap0 0 50000 1>;
+ brightness-levels = <0 51 53 56 62 75 101 152 255>;
+ default-brightness-level = <8>;
+ };
+};
+
+&dsi_bridge {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lcd: display {
+ compatible = "osddisplays,osd101t2587-53ts";
+ reg = <0>;
+
+ label = "lcd";
+
+ backlight = <&lcd_bl>;
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+&dsi_bridge_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&lcd_in>;
+ };
+ };
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&ecap0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 7da718abbd85..29936bfbeeb7 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -168,26 +168,24 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- keyswitch_in {
+ key-switch-in {
label = "keyswitch_in";
gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
linux,code = <28>;
wakeup-source;
};
- error_in {
+ key-error-in {
label = "error_in";
gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
linux,code = <29>;
wakeup-source;
};
- btn {
+ key-s {
label = "btn";
gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
linux,code = <31>;
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
index 2dfb32bf9d48..fbb2258b451f 100644
--- a/arch/arm/boot/dts/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -399,7 +399,7 @@
compatible = "arm,pl022", "arm,primecell";
reg = <0x1000d000 0x1000>;
clocks = <&sspclk>, <&pclk>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
};
wdog: watchdog@10010000 {
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index 06b8723b09eb..efed325af88d 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -410,7 +410,7 @@
interrupt-parent = <&intc_dc1176>;
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sspclk>, <&pclk>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
};
pb1176_serial0: serial@1010c000 {
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index 295aef448123..89103d54ecc1 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -555,7 +555,7 @@
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sspclk>, <&pclk>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
};
watchdog@1000f000 {
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index 6f61f968d689..ec1507c5147c 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -390,7 +390,7 @@
compatible = "arm,pl022", "arm,primecell";
reg = <0x1000d000 0x1000>;
clocks = <&sspclk>, <&pclk>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
};
wdog0: watchdog@1000f000 {
diff --git a/arch/arm/boot/dts/armada-370-c200-v2.dts b/arch/arm/boot/dts/armada-370-c200-v2.dts
index 1a4a09bdde63..84d40e1d70ef 100644
--- a/arch/arm/boot/dts/armada-370-c200-v2.dts
+++ b/arch/arm/boot/dts/armada-370-c200-v2.dts
@@ -75,25 +75,25 @@
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
- power {
+ button-power {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
};
- reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
- usb1 {
+ button-usb1 {
label = "USB1 Button";
linux,code = <BTN_0>;
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
- usb2 {
+ button-usb2 {
label = "USB2 Button";
linux,code = <BTN_1>;
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 77261a2fb949..a7dc4c04d10b 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -203,7 +203,7 @@
pinctrl-names = "default";
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
index 2008c6eaaa52..561195b749eb 100644
--- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
+++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
@@ -86,19 +86,19 @@
pinctrl-names = "default";
- sata-r-amber-pin {
+ led-sata-r-amber {
label = "dns327l:amber:sata-r";
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
- sata-l-amber-pin {
+ led-sata-l-amber {
label = "dns327l:amber:sata-l";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
- backup-led-pin {
+ led-backup {
label = "dns327l:white:usb";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index b0b640b7de40..079b37cf148a 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -85,11 +85,11 @@
};
clocks {
- g762_clk: g762-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <8192>;
- };
+ g762_clk: g762-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <8192>;
+ };
};
gpio-leds {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 85e2e9e27a9f..d752ac1d7b58 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -94,11 +94,11 @@
};
clocks {
- g762_clk: g762-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <8192>;
- };
+ g762_clk: g762-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <8192>;
+ };
};
gpio-leds {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index c910d157a686..b459a670f615 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -20,6 +20,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"
@@ -61,8 +62,8 @@
status = "okay";
phy-mode = "rgmii-id";
fixed-link {
- speed = <1000>;
- full-duplex;
+ speed = <1000>;
+ full-duplex;
};
};
@@ -84,8 +85,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
button {
label = "Software Button";
linux,code = <KEY_POWER>;
@@ -137,6 +136,17 @@
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
};
switch: switch@10 {
@@ -157,24 +167,24 @@
};
port@1 {
- reg = <1>;
- label = "lan1";
+ reg = <1>;
+ label = "lan1";
};
port@2 {
- reg = <2>;
- label = "lan2";
+ reg = <2>;
+ label = "lan2";
};
port@3 {
- reg = <3>;
- label = "lan3";
+ reg = <3>;
+ label = "lan3";
};
port@5 {
reg = <5>;
- label = "cpu";
ethernet = <&eth1>;
+ phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
index 3cf70c72c5ca..9cb69999b1db 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
@@ -72,11 +72,11 @@
};
gpio-leds {
- red-sata2 {
+ led-red-sata2 {
label = "dart:red:sata2";
gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
};
- red-sata3 {
+ led-red-sata3 {
label = "dart:red:sata3";
gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
index b52634ecf1d9..822f10734946 100644
--- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
@@ -108,22 +108,20 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- power {
+ button-power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- backup {
+ button-backup {
label = "Backup button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
@@ -134,21 +132,21 @@
gpio-leds {
compatible = "gpio-leds";
- white-power {
+ led-white-power {
label = "dart:white:power";
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
};
- red-power {
+ led-red-power {
label = "dart:red:power";
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
};
- red-sata0 {
+ led-red-sata0 {
label = "dart:red:sata0";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- red-sata1 {
+ led-red-sata1 {
label = "dart:red:sata1";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
index a624b2371fb6..124a8ba279e3 100644
--- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
@@ -83,22 +83,20 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- power {
+ button-power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
debounce-interval = <100>;
};
- reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- button {
+ button-usb {
label = "USB VBUS error";
linux,code = <KEY_UNKNOWN>;
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
@@ -109,7 +107,7 @@
gpio-leds {
compatible = "gpio-leds";
- red-sata0 {
+ led-red-sata0 {
label = "cumulus:red:sata0";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
@@ -159,7 +157,7 @@
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
/* MX25L8006E */
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
index 64f2ce254fb6..f0893cc06607 100644
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -91,9 +91,9 @@
};
ethernet@70000 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "sgmii";
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
};
sata@a0000 {
@@ -258,7 +258,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 46e6d3ed8f35..2013a5ccecd3 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -60,34 +60,54 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie2: pcie@2,0 {
device_type = "pci";
- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 0e679465cbb5..4c4092790a20 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -64,7 +64,7 @@
status = "disabled";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 7f2f24a29e6c..ddc49547d786 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -178,6 +178,8 @@
/* Network controller */
ethernet: ethernet@f0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "marvell,armada-375-pp2";
reg = <0xf0000 0xa000>, /* Packet Processor regs */
<0xc0000 0x3060>, /* LMS regs */
@@ -187,15 +189,17 @@
clock-names = "pp_clk", "gop_clk";
status = "disabled";
- eth0: eth0 {
+ eth0: ethernet-port@0 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <0>;
+ reg = <0>;
+ port-id = <0>; /* For backward compatibility. */
status = "disabled";
};
- eth1: eth1 {
+ eth1: ethernet-port@1 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <1>;
+ reg = <1>;
+ port-id = <1>; /* For backward compatibility. */
status = "disabled";
};
};
@@ -568,34 +572,54 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie1: pcie@2,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index cff1269f3fbf..e94f22b0e9b5 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -64,54 +64,84 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
/* x1 port */
pcie@2,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
/* x1 port */
pcie@3,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+ <0 0 0 2 &pcie3_intc 1>,
+ <0 0 0 3 &pcie3_intc 2>,
+ <0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie3_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
index 0a961116a1f9..f4c4b213ef4e 100644
--- a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
+++ b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
@@ -24,7 +24,7 @@
pinctrl-0 = <&front_button_pins>;
pinctrl-names = "default";
- factory_default {
+ key-factory-default {
label = "Factory Default";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
@@ -148,7 +148,7 @@
port@0 {
ethernet = <&eth0>;
- label = "cpu";
+ phy-mode = "rgmii";
reg = <0>;
fixed-link {
@@ -242,7 +242,7 @@
pinctrl-names = "default";
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/armada-385-atl-x530.dts
index ed3f41c7df71..241f5d7c80e9 100644
--- a/arch/arm/boot/dts/armada-385-atl-x530.dts
+++ b/arch/arm/boot/dts/armada-385-atl-x530.dts
@@ -168,7 +168,7 @@
pinctrl-0 = <&spi1_pins>;
status = "okay";
- spi-flash@1 {
+ flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts
index c9ac630e5874..1990f7d0cc79 100644
--- a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts
@@ -68,8 +68,13 @@
port@10 {
reg = <10>;
- label = "cpu";
+ phy-mode = "2500base-x";
+
ethernet = <&eth1>;
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts
index fa653b379490..b795ad573891 100644
--- a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts
@@ -48,8 +48,13 @@
port@5 {
reg = <5>;
- label = "cpu";
+ phy-mode = "2500base-x";
ethernet = <&eth1>;
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi
index 624bbcae68c0..d1452a04e904 100644
--- a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi
@@ -256,14 +256,14 @@
pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
pinctrl-names = "default";
- button_0 {
+ button-0 {
label = "Rear Button";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
- button_1 {
+ button-1 {
label = "Front Button";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,can-disable;
@@ -365,7 +365,7 @@
pinctrl-names = "default";
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "w25q32", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts
index 7881df3b28a0..389d9c75d546 100644
--- a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts
+++ b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts
@@ -126,7 +126,7 @@
pinctrl-0 = <&spi1_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
index 0e4613bb56ee..332f8fce77dc 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -192,7 +192,7 @@
pinctrl-0 = <&spi1_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
index a03050c97084..88b2921fed55 100644
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -62,11 +62,11 @@
};
&gpio_leds {
- power {
+ led-power {
label = "caiman:white:power";
};
- sata {
+ led-sata {
label = "caiman:white:sata";
};
};
diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
index e3e4877a6f49..88200f930d0d 100644
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -62,11 +62,11 @@
};
&gpio_leds {
- power {
+ led-power {
label = "cobra:white:power";
};
- sata {
+ led-sata {
label = "cobra:white:sata";
};
};
diff --git a/arch/arm/boot/dts/armada-385-linksys-rango.dts b/arch/arm/boot/dts/armada-385-linksys-rango.dts
index 3c4af57ec2b9..4ab45f294de2 100644
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -54,22 +54,22 @@
};
&gpio_leds {
- power {
+ led-power {
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
label = "rango:white:power";
};
- sata {
+ led-sata {
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
label = "rango:white:sata";
};
- wlan_2g {
+ led-wlan_2g {
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
label = "rango:white:wlan_2g";
};
- wlan_5g {
+ led-wlan_5g {
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
label = "rango:white:wlan_5g";
};
diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
index 3451cd3e5dff..f1b1f22413f1 100644
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -62,11 +62,11 @@
};
&gpio_leds {
- power {
+ led-power {
label = "shelby:white:power";
};
- sata {
+ led-sata {
label = "shelby:white:sata";
};
};
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index fb9c8a0b241c..fc8216fd9f60 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -53,13 +53,13 @@
pinctrl-0 = <&gpio_keys_pins>;
pinctrl-names = "default";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
@@ -71,12 +71,12 @@
pinctrl-0 = <&gpio_leds_pins>;
pinctrl-names = "default";
- power {
+ led-power {
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- sata {
+ led-sata {
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "disk-activity";
@@ -195,7 +195,7 @@
port@5 {
reg = <5>;
- label = "cpu";
+ phy-mode = "sgmii";
ethernet = <&eth2>;
fixed-link {
diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts
index d8769956cbfc..ea91ff964d94 100644
--- a/arch/arm/boot/dts/armada-385-synology-ds116.dts
+++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts
@@ -149,7 +149,7 @@
* sata0, and accesses to SATA disk 0 make it blink so it
* doesn't need to be declared here.
*/
- orange {
+ led-orange {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
label = "ds116:orange:disk";
default-state = "off";
@@ -223,7 +223,7 @@
pinctrl-0 = <&spi0_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "macronix,mx25l6405d", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
index f240018148f6..2d8d319bec83 100644
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -23,6 +23,12 @@
stdout-path = &uart0;
};
+ aliases {
+ ethernet0 = &eth0;
+ ethernet1 = &eth1;
+ ethernet2 = &eth2;
+ };
+
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1024 MB */
@@ -105,6 +111,33 @@
*/
status = "disabled";
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+ simple-audio-card,format = "i2s";
+
+ simple-audio-card,cpu {
+ sound-dai = <&audio_controller 1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+};
+
+&audio_controller {
+ /* Pin header U16, GPIO51 in SPDIFO mode */
+ pinctrl-0 = <&spdif_pins>;
+ pinctrl-names = "default";
+ spdif-mode;
+ status = "okay";
};
&bm {
@@ -166,6 +199,7 @@
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
+ label = "wan";
};
&i2c0 {
@@ -191,15 +225,13 @@
reg = <0x2b>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "okay";
/*
* LEDs are controlled by MCU (STM32F0) at
* address 0x2b.
*
- * The driver does not support HW control mode
- * for the LEDs yet. Disable the LEDs for now.
- *
- * Also LED functions are not stable yet:
+ * LED functions are not stable yet:
* - there are 3 LEDs connected via MCU to PCIe
* ports. One of these ports supports mSATA.
* There is no mSATA nor PCIe function.
@@ -210,7 +242,6 @@
* B. Again there is no such function defined.
* For now we use LED_FUNCTION_INDICATOR
*/
- status = "disabled";
multi-led@0 {
reg = <0x0>;
@@ -348,7 +379,11 @@
#size-cells = <0>;
reg = <5>;
- /* ATSHA204A at address 0x64 */
+ /* ATSHA204A-MAHDA-T crypto module */
+ crypto@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
};
i2c@6 {
@@ -393,7 +428,8 @@
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
- marvell,reg-init = <3 18 0 0x4985>;
+ marvell,reg-init = <3 18 0 0x4985>,
+ <3 16 0xfff0 0x0001>;
/* irq is connected to &pcawan pin 7 */
};
@@ -443,7 +479,6 @@
ports@5 {
reg = <5>;
- label = "cpu";
ethernet = <&eth1>;
phy-mode = "rgmii-id";
@@ -453,7 +488,16 @@
};
};
- /* port 6 is connected to eth0 */
+ ports@6 {
+ reg = <6>;
+ ethernet = <&eth0>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
};
};
};
@@ -474,7 +518,7 @@
marvell,function = "spi0";
};
- spi0cs1_pins: spi0cs1-pins {
+ spi0cs2_pins: spi0cs2-pins {
marvell,pins = "mpp26";
marvell,function = "spi0";
};
@@ -485,7 +529,7 @@
pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "spansion,s25fl164k", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
@@ -509,7 +553,7 @@
};
};
- /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
+ /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
};
&uart0 {
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 83392b92dae2..be8d607c59b2 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -93,7 +93,7 @@
/* x1 port */
pcie2: pcie@2,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -121,7 +121,7 @@
/* x1 port */
pcie3: pcie@3,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -152,7 +152,7 @@
*/
pcie4: pcie@4,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts
index 53b4bd35522a..f7daa3bc707e 100644
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
@@ -19,7 +19,7 @@
pinctrl-0 = <&rear_button_pins>;
pinctrl-names = "default";
- button_0 {
+ button-0 {
/* The rear SW3 button */
label = "Rear Button";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 4140a5303b48..95299167dcf5 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -35,7 +35,7 @@
pinctrl-0 = <&rear_button_pins>;
pinctrl-names = "default";
- button_0 {
+ button-0 {
/* The rear SW3 button */
label = "Rear Button";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index a2bec07bf4c5..45cc784659fd 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -36,6 +36,11 @@
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
+ audio_codec: audio-codec@4a {
+ #sound-dai-cells = <0>;
+ compatible = "cirrus,cs42l51";
+ reg = <0x4a>;
+ };
};
i2c@11100 {
@@ -57,7 +62,7 @@
};
usb@58000 {
- status = "ok";
+ status = "okay";
};
ethernet@70000 {
@@ -99,6 +104,12 @@
no-1-8-v;
};
+ audio-controller@e8000 {
+ pinctrl-0 = <&i2s_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
usb3@f0000 {
status = "okay";
};
@@ -128,12 +139,70 @@
};
};
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Armada 385 DB Audio";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Headphone", "Out Jack",
+ "Line", "In Jack";
+ simple-audio-card,routing =
+ "Out Jack", "HPL",
+ "Out Jack", "HPR",
+ "AIN1L", "In Jack",
+ "AIN1R", "In Jack";
+ status = "disabled";
+
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&audio_controller 0>;
+ };
+
+ codec {
+ sound-dai = <&audio_codec>;
+ };
+ };
+
+ simple-audio-card,dai-link@1 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&audio_controller 1>;
+ };
+
+ codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ simple-audio-card,dai-link@2 {
+ format = "i2s";
+ cpu {
+ sound-dai = <&audio_controller 1>;
+ };
+
+ codec {
+ sound-dai = <&spdif_in>;
+ };
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+
+ spdif_in: spdif-in {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dir";
+ };
};
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 9d873257ac45..e2ba50520b6b 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -395,7 +395,7 @@
pinctrl-0 = <&spi0_pins>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index 328a4d6afd2c..c0efafd45b33 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -97,7 +97,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 363ac4238859..2c64bc6e5a17 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -101,7 +101,7 @@
/* The microsom has an optional W25Q32 on board, connected to CS0 */
pinctrl-0 = <&spi1_pins>;
- w25q32: spi-flash@0 {
+ w25q32: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index df3c8d1d8f64..446861b6b17b 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -289,6 +289,18 @@
marvell,pins = "mpp44";
marvell,function = "sata3";
};
+
+ i2s_pins: i2s-pins {
+ marvell,pins = "mpp48", "mpp49",
+ "mpp50", "mpp51",
+ "mpp52", "mpp53";
+ marvell,function = "audio";
+ };
+
+ spdif_pins: spdif-pins {
+ marvell,pins = "mpp51";
+ marvell,function = "audio";
+ };
};
gpio0: gpio@18100 {
@@ -298,6 +310,7 @@
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
@@ -316,6 +329,7 @@
reg-names = "gpio", "pwm";
ngpios = <28>;
gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 28>;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
@@ -618,6 +632,18 @@
status = "disabled";
};
+ audio_controller: audio-controller@e8000 {
+ #sound-dai-cells = <1>;
+ compatible = "marvell,armada-380-audio";
+ reg = <0xe8000 0x4000>, <0x18410 0xc>,
+ <0x18204 0x4>;
+ reg-names = "i2s_regs", "pll_regs", "soc_ctrl";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gateclk 0>;
+ clock-names = "internal";
+ status = "disabled";
+ };
+
usb3_0: usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts
index 0e29474ae9a2..792d0a0184e8 100644
--- a/arch/arm/boot/dts/armada-390-db.dts
+++ b/arch/arm/boot/dts/armada-390-db.dts
@@ -81,7 +81,7 @@
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
- spi-flash@1 {
+ flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13",
diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
index fc28308e5bc5..ec6cdbeedde7 100644
--- a/arch/arm/boot/dts/armada-398-db.dts
+++ b/arch/arm/boot/dts/armada-398-db.dts
@@ -79,7 +79,7 @@
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index e0b7c2099831..9d1cac49c022 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -438,54 +438,84 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
/* x1 port */
pcie@2,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
/* x1 port */
pcie@3,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+ <0 0 0 2 &pcie3_intc 1>,
+ <0 0 0 3 &pcie3_intc 2>,
+ <0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie3_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
/*
@@ -494,20 +524,30 @@
*/
pcie@4,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie4_intc 0>,
+ <0 0 0 2 &pcie4_intc 1>,
+ <0 0 0 3 &pcie4_intc 2>,
+ <0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 7>;
status = "disabled";
+
+ pcie4_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index 38a052a0312d..7a7e2066c498 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -76,16 +76,26 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
@@ -286,6 +296,7 @@
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
+ interrupts = <93>, <38>;
};
&cpurst {
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index 606fd3476a59..5a74197be0ad 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -69,14 +69,12 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
- reset {
+ button-reset {
label = "Factory Reset Button";
linux,code = <KEY_SETUP>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -134,7 +132,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts
index a022c68dc943..c28e140b4afc 100644
--- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts
+++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts
@@ -15,7 +15,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi
index 32fb21b2bf6a..47b003a81bd4 100644
--- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi
+++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi
@@ -80,7 +80,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts
index 21f442afab1f..20ba5c823bb2 100644
--- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts
+++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts
@@ -15,7 +15,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi
index f3e1a25ca5f2..cab99d8e2911 100644
--- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi
+++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi
@@ -80,7 +80,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts
index e05aee6cdc04..2caa3980fdf6 100644
--- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts
+++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts
@@ -15,7 +15,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi
index c8b1355ce15e..7028482ce4b2 100644
--- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi
+++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi
@@ -80,7 +80,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
index 8a3aa616bbd0..02bef8dc4270 100644
--- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
+++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
@@ -93,7 +93,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 4ec0ae01b61d..d1b61dad0c46 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -89,7 +89,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 5d04dc68cf57..75318fd0fc11 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -235,7 +235,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index b4cca507cf13..d1d348b91c0a 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -220,7 +220,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 87dcb502f72d..0dad95ea26c2 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -164,7 +164,7 @@
};
};
- spi3 {
+ spi-3 {
compatible = "spi-gpio";
status = "okay";
gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 8480a16919a0..7a0614fd0c93 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -172,20 +172,18 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -197,7 +195,7 @@
pinctrl-0 = <&power_led_pin>;
pinctrl-names = "default";
- power {
+ led-power {
label = "mamba:white:power";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -255,7 +253,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "everspin,mr25h256";
@@ -304,7 +302,7 @@
port@5 {
reg = <5>;
- label = "cpu";
+ phy-mode = "rgmii-id";
ethernet = <&eth0>;
fixed-link {
speed = <1000>;
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 8558bf6bb54c..5ea9d509cd30 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -83,88 +83,138 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie2: pcie@2,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie3: pcie@3,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+ <0 0 0 2 &pcie3_intc 1>,
+ <0 0 0 3 &pcie3_intc 2>,
+ <0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
+
+ pcie3_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie4: pcie@4,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie4_intc 0>,
+ <0 0 0 2 &pcie4_intc 1>,
+ <0 0 0 3 &pcie4_intc 2>,
+ <0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
+
+ pcie4_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie5: pcie@5,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie5_intc 0>,
+ <0 0 0 2 &pcie5_intc 1>,
+ <0 0 0 3 &pcie5_intc 2>,
+ <0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
+
+ pcie5_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d85fe8ac327..6c6fbb9faf5a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -98,160 +98,250 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie2: pcie@2,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie3: pcie@3,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+ <0 0 0 2 &pcie3_intc 1>,
+ <0 0 0 3 &pcie3_intc 2>,
+ <0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
+
+ pcie3_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie4: pcie@4,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie4_intc 0>,
+ <0 0 0 2 &pcie4_intc 1>,
+ <0 0 0 3 &pcie4_intc 2>,
+ <0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
+
+ pcie4_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie5: pcie@5,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie5_intc 0>,
+ <0 0 0 2 &pcie5_intc 1>,
+ <0 0 0 3 &pcie5_intc 2>,
+ <0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
+
+ pcie5_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie6: pcie@6,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
+ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 63>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie6_intc 0>,
+ <0 0 0 2 &pcie6_intc 1>,
+ <0 0 0 3 &pcie6_intc 2>,
+ <0 0 0 4 &pcie6_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
+
+ pcie6_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie7: pcie@7,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
+ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 64>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie7_intc 0>,
+ <0 0 0 2 &pcie7_intc 1>,
+ <0 0 0 3 &pcie7_intc 2>,
+ <0 0 0 4 &pcie7_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
+
+ pcie7_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie8: pcie@8,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
+ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 65>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie8_intc 0>,
+ <0 0 0 2 &pcie8_intc 1>,
+ <0 0 0 3 &pcie8_intc 2>,
+ <0 0 0 4 &pcie8_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
+
+ pcie8_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie9: pcie@9,0 {
device_type = "pci";
- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 99>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie9_intc 0>,
+ <0 0 0 2 &pcie9_intc 1>,
+ <0 0 0 3 &pcie9_intc 2>,
+ <0 0 0 4 &pcie9_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
+
+ pcie9_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 230a3fd36b30..16185edf9aa5 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -119,16 +119,26 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie2: pcie@2,0 {
@@ -137,16 +147,26 @@
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie3: pcie@3,0 {
@@ -155,16 +175,26 @@
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+ <0 0 0 2 &pcie3_intc 1>,
+ <0 0 0 3 &pcie3_intc 2>,
+ <0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
+
+ pcie3_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie4: pcie@4,0 {
@@ -173,16 +203,26 @@
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie4_intc 0>,
+ <0 0 0 2 &pcie4_intc 1>,
+ <0 0 0 3 &pcie4_intc 2>,
+ <0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
+
+ pcie4_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie5: pcie@5,0 {
@@ -191,16 +231,26 @@
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie5_intc 0>,
+ <0 0 0 2 &pcie5_intc 1>,
+ <0 0 0 3 &pcie5_intc 2>,
+ <0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
+
+ pcie5_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie6: pcie@6,0 {
@@ -209,16 +259,26 @@
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 63>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie6_intc 0>,
+ <0 0 0 2 &pcie6_intc 1>,
+ <0 0 0 3 &pcie6_intc 2>,
+ <0 0 0 4 &pcie6_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
+
+ pcie6_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie7: pcie@7,0 {
@@ -227,16 +287,26 @@
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 64>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie7_intc 0>,
+ <0 0 0 2 &pcie7_intc 1>,
+ <0 0 0 3 &pcie7_intc 2>,
+ <0 0 0 4 &pcie7_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
+
+ pcie7_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie8: pcie@8,0 {
@@ -245,16 +315,26 @@
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 65>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie8_intc 0>,
+ <0 0 0 2 &pcie8_intc 1>,
+ <0 0 0 3 &pcie8_intc 2>,
+ <0 0 0 4 &pcie8_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
+
+ pcie8_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie9: pcie@9,0 {
@@ -263,16 +343,26 @@
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 99>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie9_intc 0>,
+ <0 0 0 2 &pcie9_intc 1>,
+ <0 0 0 3 &pcie9_intc 2>,
+ <0 0 0 4 &pcie9_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
+
+ pcie9_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie10: pcie@a,0 {
@@ -281,16 +371,26 @@
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 103>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie10_intc 0>,
+ <0 0 0 2 &pcie10_intc 1>,
+ <0 0 0 3 &pcie10_intc 2>,
+ <0 0 0 4 &pcie10_intc 3>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
+
+ pcie10_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 8ea73587db81..31933f81144e 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -121,11 +121,11 @@
};
clocks {
- g762_clk: g762-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ g762_clk: g762-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
gpio-leds {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 0efcc166dabf..1ecf72a61bca 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -97,12 +97,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- init {
+ button-init {
label = "Init Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
index 809e821d7399..5551bac1962c 100644
--- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -274,7 +274,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 6c19984d668e..4297482da62f 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -260,6 +260,7 @@
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
+ interrupts = <93>, <38>;
};
&cpurst {
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts
index d20d95359b28..042a9cc920c6 100644
--- a/arch/arm/boot/dts/artpec6-devboard.dts
+++ b/arch/arm/boot/dts/artpec6-devboard.dts
@@ -1,10 +1,5 @@
-/*
- * Axis ARTPEC-6 development board.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Axis ARTPEC-6 development board.
/dts-v1/;
#include "artpec6.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 1d24b394ea4c..a497dd135491 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -5,7 +5,7 @@
/ {
model = "AST2500 EVB";
- compatible = "aspeed,ast2500";
+ compatible = "aspeed,ast2500-evb", "aspeed,ast2500";
aliases {
serial4 = &uart5;
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
index dd7148060c4a..f34a2b1ec2f0 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
@@ -5,6 +5,7 @@
/ {
model = "AST2600 A1 EVB";
+ compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600-evb", "aspeed,ast2600";
/delete-node/regulator-vcc-sdhci0;
/delete-node/regulator-vcc-sdhci1;
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..de83c0eb1d6e 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -8,7 +8,7 @@
/ {
model = "AST2600 EVB";
- compatible = "aspeed,ast2600";
+ compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
aliases {
serial4 = &uart5;
@@ -23,6 +23,26 @@
reg = <0x80000000 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: video {
+ size = <0x04000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
vcc_sdhci0: regulator-vcc-sdhci0 {
compatible = "regulator-fixed";
regulator-name = "SDHCI0 Vcc";
@@ -103,7 +123,7 @@
&mac0 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
@@ -114,7 +134,7 @@
&mac1 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
phy-handle = <&ethphy1>;
pinctrl-names = "default";
@@ -162,6 +182,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+ spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
@@ -176,6 +197,7 @@
status = "okay";
m25p,fast-read;
label = "pnor";
+ spi-rx-bus-width = <4>;
spi-max-frequency = <100000000>;
};
};
@@ -187,11 +209,6 @@
&i2c0 {
status = "okay";
-
- temp@2e {
- compatible = "adi,adt7490";
- reg = <0x2e>;
- };
};
&i2c1 {
@@ -220,10 +237,26 @@
&i2c7 {
status = "okay";
+
+ temp@2e {
+ compatible = "adi,adt7490";
+ reg = <0x2e>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
};
&i2c8 {
status = "okay";
+
+ lm75@4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
};
&i2c9 {
@@ -300,3 +333,18 @@
vqmmc-supply = <&vccq_sdhci1>;
clk-phase-sd-hs = <7>, <200>;
};
+
+&vhub {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts b/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts
new file mode 100644
index 000000000000..64bb9bf92de2
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "AMD DaytonaX BMC";
+ compatible = "amd,daytonax-bmc", "aspeed,ast2500";
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: jpegbuffer {
+ size = <0x02000000>; /* 32M */
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ aliases {
+ serial0 = &uart1;
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-fault {
+ gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ led-identify {
+ gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>,
+ <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>,
+ <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>,
+ <&adc 15>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ #include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+};
+
+&uart1 {
+ //Host Console
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart5 {
+ //BMC Console
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+ aspeed,lpc-io-reg = <0x3f8>;
+ aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&adc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default
+ &pinctrl_adc8_default
+ &pinctrl_adc9_default
+ &pinctrl_adc10_default
+ &pinctrl_adc11_default
+ &pinctrl_adc12_default
+ &pinctrl_adc13_default
+ &pinctrl_adc14_default
+ &pinctrl_adc15_default>;
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names =
+ /*A0-A7*/ "","","led-fault","led-identify","","","","",
+ /*B0-B7*/ "","","","","","","","",
+ /*C0-C7*/ "id-button","","","","","","","",
+ /*D0-D7*/ "","","ASSERT_BMC_READY","","","","","",
+ /*E0-E7*/ "reset-button","reset-control","power-button","power-control","",
+ "power-good","power-ok","",
+ /*F0-F7*/ "","","","","","","BATTERY_DETECT","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "","","","","","","","",
+ /*AB0-AB7*/ "FM_BMC_READ_SPD_TEMP","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&kcs3 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca2>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>, <0x81>;
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default
+ &pinctrl_pwm7_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan@6 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan@7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan@8 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan@9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan@10 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan@11 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan@12 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan@13 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+
+ fan@14 {
+ reg = <0x07>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
+ };
+
+ fan@15 {
+ reg = <0x07>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
+ };
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&vhub {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
index 6406a0f080ee..6bded774c457 100644
--- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
@@ -5,6 +5,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "AMD EthanolX BMC";
@@ -58,10 +59,22 @@
flash@0 {
status = "okay";
m25p,fast-read;
+ label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bios";
+ spi-max-frequency = <100000000>;
+ };
+};
&mac0 {
status = "okay";
@@ -78,7 +91,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
- &pinctrl_rxd1_default>;
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ncts1_default>;
};
&uart5 {
@@ -160,7 +175,7 @@
&i2c3 {
status = "okay";
eeprom@50 {
- compatible = "atmel,24c256";
+ compatible = "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};
@@ -261,6 +276,12 @@
status = "okay";
};
+&vuart {
+ status = "okay";
+ aspeed,lpc-io-reg = <0x3f8>;
+ aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
index 1b2e7ad37566..0a51d2e32fab 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
@@ -97,101 +97,6 @@
};
};
- gpio-keys {
- compatible = "gpio-keys";
-
- shutdown_ack {
- label = "SHUTDOWN_ACK";
- gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(G, 2)>;
- };
-
- reboot_ack {
- label = "REBOOT_ACK";
- gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(J, 3)>;
- };
-
- S0_overtemp {
- label = "S0_OVERTEMP";
- gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(G, 3)>;
- };
-
- S0_hightemp {
- label = "S0_HIGHTEMP";
- gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(J, 0)>;
- };
-
- S0_cpu_fault {
- label = "S0_CPU_FAULT";
- gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
- linux,code = <ASPEED_GPIO(J, 1)>;
- };
-
- S0_scp_auth_fail {
- label = "S0_SCP_AUTH_FAIL";
- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(J, 2)>;
- };
-
- S1_scp_auth_fail {
- label = "S1_SCP_AUTH_FAIL";
- gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(Z, 5)>;
- };
-
- S1_overtemp {
- label = "S1_OVERTEMP";
- gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(Z, 6)>;
- };
-
- S1_hightemp {
- label = "S1_HIGHTEMP";
- gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(AB, 0)>;
- };
-
- S1_cpu_fault {
- label = "S1_CPU_FAULT";
- gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
- linux,code = <ASPEED_GPIO(Z, 1)>;
- };
-
- id_button {
- label = "ID_BUTTON";
- gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(Q, 5)>;
- };
-
- psu1_vin_good {
- label = "PSU1_VIN_GOOD";
- gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(H, 4)>;
- };
-
- psu2_vin_good {
- label = "PSU2_VIN_GOOD";
- gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(H, 5)>;
- };
-
- psu1_present {
- label = "PSU1_PRESENT";
- gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(I, 0)>;
- };
-
- psu2_present {
- label = "PSU2_PRESENT";
- gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(I, 1)>;
- };
-
- };
-
gpioA0mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
@@ -437,6 +342,10 @@
&i2c0 {
status = "okay";
+ ssif-bmc@10 {
+ compatible = "ssif-bmc";
+ reg = <0x10>;
+ };
};
&i2c1 {
@@ -445,6 +354,14 @@
&i2c2 {
status = "okay";
+ smpro@4f {
+ compatible = "ampere,smpro";
+ reg = <0x4f>;
+ };
+ smpro@4e {
+ compatible = "ampere,smpro";
+ reg = <0x4e>;
+ };
};
&i2c3 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts
new file mode 100644
index 000000000000..1e0e88465254
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2022, Ampere Computing LLC
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Ampere Mt.Mitchell BMC";
+ compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
+
+ chosen {
+ stdout-path = &uart5;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ video_engine_memory: video {
+ size = <0x04000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ vga_memory: region@bf000000 {
+ no-map;
+ compatible = "shared-dma-pool";
+ reg = <0xbf000000 0x01000000>; /* 16M */
+ };
+ };
+
+ voltage_mon_reg: voltage-mon-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ltc2497_reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ gpioI5mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
+ };
+
+ adc0mux: adc0mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 0>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc1mux: adc1mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 1>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc2mux: adc2mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 2>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc3mux: adc3mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 3>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc4mux: adc4mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 4>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc5mux: adc5mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 5>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc6mux: adc6mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 6>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc7mux: adc7mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc0 7>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc8mux: adc8mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 0>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc9mux: adc9mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 1>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc10mux: adc10mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 2>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc11mux: adc11mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 3>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc12mux: adc12mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 4>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc13mux: adc13mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 5>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc14mux: adc14mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 6>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ adc15mux: adc15mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc1 7>;
+ #io-channel-cells = <1>;
+ io-channel-names = "parent";
+ mux-controls = <&gpioI5mux>;
+ channels = "s0", "s1";
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0mux 0>, <&adc0mux 1>,
+ <&adc1mux 0>, <&adc1mux 1>,
+ <&adc2mux 0>, <&adc2mux 1>,
+ <&adc3mux 0>, <&adc3mux 1>,
+ <&adc4mux 0>, <&adc4mux 1>,
+ <&adc5mux 0>, <&adc5mux 1>,
+ <&adc6mux 0>, <&adc6mux 1>,
+ <&adc7mux 0>, <&adc7mux 1>,
+ <&adc8mux 0>, <&adc8mux 1>,
+ <&adc9mux 0>, <&adc9mux 1>,
+ <&adc10mux 0>, <&adc10mux 1>,
+ <&adc11mux 0>, <&adc11mux 1>,
+ <&adc12mux 0>, <&adc12mux 1>,
+ <&adc13mux 0>, <&adc13mux 1>,
+ <&adc14mux 0>, <&adc14mux 1>,
+ <&adc15mux 0>, <&adc15mux 1>,
+ <&adc_i2c 0>, <&adc_i2c 1>,
+ <&adc_i2c 2>, <&adc_i2c 3>,
+ <&adc_i2c 4>, <&adc_i2c 5>,
+ <&adc_i2c 6>, <&adc_i2c 7>,
+ <&adc_i2c 8>, <&adc_i2c 9>,
+ <&adc_i2c 10>, <&adc_i2c 11>,
+ <&adc_i2c 12>, <&adc_i2c 13>,
+ <&adc_i2c 14>, <&adc_i2c 15>;
+ };
+};
+
+&mdio0 {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1_default>;
+};
+
+&mac3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temperature-sensor@2e {
+ compatible = "adi,adt7490";
+ reg = <0x2e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ psu@58 {
+ compatible = "pmbus";
+ reg = <0x58>;
+ };
+
+ psu@59 {
+ compatible = "pmbus";
+ reg = <0x59>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ adc_i2c: adc@16 {
+ compatible = "lltc,ltc2497";
+ reg = <0x16>;
+ vref-supply = <&voltage_mon_reg>;
+ #io-channel-cells = <1>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9545";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ i2c4_bus70_chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ outlet_temp1: temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+ psu1_inlet_temp2: temperature-sensor@49 {
+ compatible = "ti,tmp75";
+ reg = <0x49>;
+ };
+ };
+
+ i2c4_bus70_chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ pcie_zone_temp1: temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+ psu0_inlet_temp2: temperature-sensor@49 {
+ compatible = "ti,tmp75";
+ reg = <0x49>;
+ };
+ };
+
+ i2c4_bus70_chn2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ pcie_zone_temp2: temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+ outlet_temp2: temperature-sensor@49 {
+ compatible = "ti,tmp75";
+ reg = <0x49>;
+ };
+ };
+
+ i2c4_bus70_chn3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ mb_inlet_temp1: temperature-sensor@7c {
+ compatible = "microchip,emc1413";
+ reg = <0x7c>;
+ };
+ mb_inlet_temp2: temperature-sensor@4c {
+ compatible = "microchip,emc1413";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ rtc@51 {
+ compatible = "nxp,pcf85063a";
+ reg = <0x51>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+
+ gpio@77 {
+ compatible = "nxp,pca9539";
+ reg = <0x77>;
+ gpio-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <2>;
+
+ bmc-ocp0-en-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "bmc-ocp0-en-n";
+ };
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+ ssif-bmc@10 {
+ compatible = "ssif-bmc";
+ reg = <0x10>;
+ };
+};
+
+&i2c14 {
+ status = "okay";
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ bmc_ast2600_cpu: temperature-sensor@35 {
+ compatible = "ti,tmp175";
+ reg = <0x35>;
+ };
+};
+
+&adc0 {
+ ref_voltage = <2500>;
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+};
+
+&adc1 {
+ ref_voltage = <2500>;
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc10_default &pinctrl_adc11_default
+ &pinctrl_adc12_default &pinctrl_adc13_default
+ &pinctrl_adc14_default &pinctrl_adc15_default>;
+};
+
+&vhub {
+ status = "okay";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&gpio0 {
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n",
+ /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","",
+ /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","",
+ "irq-n","","vrd-sel","spd-sel",
+ /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n",
+ "","bmc-ncsi-txen","","",
+ /*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","",
+ /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control",
+ "cpu-bios-recover","s0-heartbeat","hs-csout-prochot",
+ "s0-vr-hot-n","s1-vr-hot-n",
+ /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","",
+ /*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","",
+ /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0",
+ "s0-rtc-lock","","","",
+ /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb",
+ "jtag-dbgr-prsnt-n","s1-heartbeat","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","",
+ "led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","identify-button","led-identify",
+ "s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
+ "host0-reboot-ack-n","host0-ready","host0-shd-req-n",
+ "host0-shd-ack-n","s0-overtemp-n",
+ /*W0-W7*/ "","ocp-main-pwren","ocp-pgood","",
+ "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel",
+ /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok",
+ "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n",
+ "s1-overtemp-n","s1-spi-auth-fail-n",
+ /*Y0-Y7*/ "","","","","","","","host0-special-boot",
+ /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","","";
+
+ ocp-aux-pwren-hog {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "ocp-aux-pwren";
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/ "","","","","","","","",
+ /*18B0-18B7*/ "","","","","","","s0-soc-pgood","",
+ /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1",
+ "uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1",
+ /*18D0-18D7*/ "","","","","","","","",
+ /*18E0-18E3*/ "","","","";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
deleted file mode 100644
index 3395de96ee11..000000000000
--- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
+++ /dev/null
@@ -1,225 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/dts-v1/;
-
-#include "aspeed-g5.dtsi"
-#include <dt-bindings/gpio/aspeed-gpio.h>
-
-/ {
- model = "Qualcomm Centriq 2400 REP AST2520";
- compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500";
-
- chosen {
- stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlycon";
- };
-
- memory@80000000 {
- reg = <0x80000000 0x40000000>;
- };
-
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
- <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>;
- };
-
- iio-hwmon-battery {
- compatible = "iio-hwmon";
- io-channels = <&adc 7>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- uid_led {
- label = "UID_LED";
- gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
- };
-
- ras_error_led {
- label = "RAS_ERROR_LED";
- gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
- };
-
- system_fault {
- label = "System_fault";
- gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
-#include "openbmc-flash-layout.dtsi"
- };
-};
-
-&spi1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1_default>;
- flash@0 {
- status = "okay";
- };
-};
-
-&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2ck_default
- &pinctrl_spi2miso_default
- &pinctrl_spi2mosi_default
- &pinctrl_spi2cs0_default>;
-};
-
-&uart3 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
- current-speed = <115200>;
-};
-
-&uart5 {
- status = "okay";
-};
-
-&mac0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-
- tmp421@1e {
- compatible = "ti,tmp421";
- reg = <0x1e>;
- };
- tmp421@2a {
- compatible = "ti,tmp421";
- reg = <0x2a>;
- };
- tmp421@4e {
- compatible = "ti,tmp421";
- reg = <0x4e>;
- };
- tmp421@1c {
- compatible = "ti,tmp421";
- reg = <0x1c>;
- };
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&i2c4 {
- status = "okay";
-};
-
-&i2c5 {
- status = "okay";
-};
-
-&i2c6 {
- status = "okay";
-
- tmp421@1d {
- compatible = "ti,tmp421";
- reg = <0x1d>;
- };
- tmp421@1f {
- compatible = "ti,tmp421";
- reg = <0x1f>;
- };
- tmp421@4d {
- compatible = "ti,tmp421";
- reg = <0x4d>;
- };
- tmp421@4f {
- compatible = "ti,tmp421";
- reg = <0x4f>;
- };
- nvt210@4c {
- compatible = "nvt210";
- reg = <0x4c>;
- };
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- pagesize = <128>;
- };
-};
-
-&i2c7 {
- status = "okay";
-};
-
-&i2c8 {
- status = "okay";
-
- pca9641@70 {
- compatible = "nxp,pca9641";
- reg = <0x70>;
- i2c-arb {
- #address-cells = <1>;
- #size-cells = <0>;
- tmp421@1d {
- compatible = "tmp421";
- reg = <0x1d>;
- };
- adm1278@12 {
- compatible = "adi,adm1278";
- reg = <0x12>;
- Rsense = <500>;
- };
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- };
- ds1100@58 {
- compatible = "ds1100";
- reg = <0x58>;
- };
- };
- };
-};
-
-&i2c9 {
- status = "okay";
-};
-
-&vuart {
- status = "okay";
-};
-
-&gfx {
- status = "okay";
-};
-
-&pinctrl {
- aspeed,external-nodes = <&gfx &lhc>;
-};
-
-&gpio {
- pin_gpio_c7 {
- gpio-hog;
- gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
- output;
- line-name = "BIOS_SPI_MUX_S";
- };
-};
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
index 9b4cf5ebe6d5..c4b2efbfdf56 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
@@ -63,7 +63,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
- spi-max-frequency = <100000000>; /* 100 MHz */
+ spi-max-frequency = <50000000>; /* 50 MHz */
#include "openbmc-flash-layout.dtsi"
};
};
@@ -202,3 +202,7 @@
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
};
+
+&peci0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index e71ccfd1df63..4554abf0c7cd 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -31,7 +31,7 @@
};
system-fault {
- gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>;
+ gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
panic-indicator;
};
};
@@ -51,7 +51,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
- spi-max-frequency = <100000000>; /* 100 MHz */
+ spi-max-frequency = <50000000>; /* 50 MHz */
#include "openbmc-flash-layout-64.dtsi"
};
};
@@ -100,12 +100,14 @@
lm25066@40 {
compatible = "lm25066";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <1000>;
};
/* 12VSB PMIC */
lm25066@41 {
compatible = "lm25066";
reg = <0x41>;
+ shunt-resistor-micro-ohms = <10000>;
};
};
@@ -196,7 +198,7 @@
gpio-line-names =
/* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI",
"", "", "", "",
- /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "",
+ /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "",
/* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "",
/* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON",
"", "", "", "PSU_FAN_FAIL_N",
diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
index 0d1fb5ccfd36..f75cad41ae6f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
@@ -100,7 +100,7 @@
gpio-keys {
compatible = "gpio-keys";
- burn-in-signal {
+ event-burn-in-signal {
label = "burn-in";
gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(R, 5)>;
@@ -111,139 +111,139 @@
compatible = "gpio-keys-polled";
poll-interval = <1000>;
- rear-riser1-presence {
+ event-rear-riser1-presence {
label = "rear-riser1-presence";
gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
linux,code = <1>;
};
- alrt-pvddq-cpu0 {
+ event-alrt-pvddq-cpu0 {
label = "alrt-pvddq-cpu0";
gpios = <&pca0 8 GPIO_ACTIVE_LOW>;
linux,code = <2>;
};
- rear-riser0-presence {
+ event-rear-riser0-presence {
label = "rear-riser0-presence";
gpios = <&pca0 9 GPIO_ACTIVE_LOW>;
linux,code = <3>;
};
- fault-pvddq-cpu0 {
+ event-fault-pvddq-cpu0 {
label = "fault-pvddq-cpu0";
gpios = <&pca0 10 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
- alrt-pvddq-cpu1 {
+ event-alrt-pvddq-cpu1 {
label = "alrt-pvddq-cpu1";
gpios = <&pca0 11 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
- fault-pvddq-cpu1 {
+ event-fault-pvddq-cpu1 {
label = "alrt-pvddq-cpu1";
gpios = <&pca0 12 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
- fault-pvccin-cpu1 {
+ event-fault-pvccin-cpu1 {
label = "fault-pvccin-cpuq";
gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
- bmc-rom0-wp {
+ event-bmc-rom0-wp {
label = "bmc-rom0-wp";
gpios = <&pca1 0 GPIO_ACTIVE_LOW>;
linux,code = <8>;
};
- bmc-rom1-wp {
+ event-bmc-rom1-wp {
label = "bmc-rom1-wp";
gpios = <&pca1 1 GPIO_ACTIVE_LOW>;
linux,code = <9>;
};
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca1 2 GPIO_ACTIVE_LOW>;
linux,code = <10>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca1 3 GPIO_ACTIVE_LOW>;
linux,code = <11>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca1 4 GPIO_ACTIVE_LOW>;
linux,code = <12>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca1 5 GPIO_ACTIVE_LOW>;
linux,code = <13>;
};
- fan4-presence {
+ event-fan4-presence {
label = "fan4-presence";
gpios = <&pca1 6 GPIO_ACTIVE_LOW>;
linux,code = <14>;
};
- fan5-presence {
+ event-fan5-presence {
label = "fan5-presence";
gpios = <&pca1 7 GPIO_ACTIVE_LOW>;
linux,code = <15>;
};
- front-bp1-presence {
+ event-front-bp1-presence {
label = "front-bp1-presence";
gpios = <&pca1 8 GPIO_ACTIVE_LOW>;
linux,code = <16>;
};
- rear-bp-presence {
+ event-rear-bp-presence {
label = "rear-bp-presence";
gpios = <&pca1 9 GPIO_ACTIVE_LOW>;
linux,code = <17>;
};
- fault-pvccin-cpu0 {
+ event-fault-pvccin-cpu0 {
label = "fault-pvccin-cpu0";
gpios = <&pca1 10 GPIO_ACTIVE_LOW>;
linux,code = <18>;
};
- alrt-p1v05-pvcc {
+ event-alrt-p1v05-pvcc {
label = "alrt-p1v05-pvcc1";
gpios = <&pca1 11 GPIO_ACTIVE_LOW>;
linux,code = <19>;
};
- fault-p1v05-pvccio {
+ event-fault-p1v05-pvccio {
label = "alrt-p1v05-pvcc1";
gpios = <&pca1 12 GPIO_ACTIVE_LOW>;
linux,code = <20>;
};
- alrt-p1v8-pvccio {
+ event-alrt-p1v8-pvccio {
label = "alrt-p1v8-pvccio";
gpios = <&pca1 13 GPIO_ACTIVE_LOW>;
linux,code = <21>;
};
- fault-p1v8-pvccio {
+ event-fault-p1v8-pvccio {
label = "fault-p1v8-pvccio";
gpios = <&pca1 14 GPIO_ACTIVE_LOW>;
linux,code = <22>;
};
- front-bp0-presence {
+ event-front-bp0-presence {
label = "front-bp0-presence";
gpios = <&pca1 15 GPIO_ACTIVE_LOW>;
linux,code = <23>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts b/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts
new file mode 100644
index 000000000000..6600f7e9bf5e
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+#define EFUSE_OUTPUT(n) \
+ efuse##n { \
+ compatible = "regulator-output"; \
+ vout-supply = <&efuse##n>; \
+ }
+
+#define __stringify(x) #x
+
+#define EFUSE(hexaddr, num) \
+ efuse@##hexaddr { \
+ compatible = "lm25066"; \
+ reg = <0x##hexaddr>; \
+ shunt-resistor-micro-ohms = <675>; \
+ regulators { \
+ efuse##num: vout0 { \
+ regulator-name = __stringify(efuse##num##-reg); \
+ }; \
+ }; \
+ }
+
+/{
+ model = "Delta Power AHE-50DC";
+ compatible = "delta,ahe50dc-bmc", "aspeed,ast2400";
+
+ aliases {
+ serial4 = &uart5;
+
+ /*
+ * pca9541-arbitrated logical i2c buses are numbered as the
+ * corresponding physical bus plus 20
+ */
+ i2c20 = &i2carb0;
+ i2c21 = &i2carb1;
+ i2c22 = &i2carb2;
+ i2c23 = &i2carb3;
+ i2c24 = &i2carb4;
+ i2c26 = &i2carb6;
+ i2c27 = &i2carb7;
+ i2c28 = &i2carb8;
+ i2c32 = &i2carb12;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ bootargs = "console=ttyS2,115200n8 earlycon";
+ };
+
+ memory@40000000 {
+ reg = <0x40000000 0x10000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ panic {
+ gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "panic";
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>,
+ <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>;
+ };
+
+ EFUSE_OUTPUT(01);
+ EFUSE_OUTPUT(02);
+ EFUSE_OUTPUT(03);
+ EFUSE_OUTPUT(04);
+ EFUSE_OUTPUT(05);
+ EFUSE_OUTPUT(06);
+ EFUSE_OUTPUT(07);
+ EFUSE_OUTPUT(08);
+ EFUSE_OUTPUT(09);
+ EFUSE_OUTPUT(10);
+ EFUSE_OUTPUT(11);
+ EFUSE_OUTPUT(12);
+ EFUSE_OUTPUT(13);
+ EFUSE_OUTPUT(14);
+ EFUSE_OUTPUT(15);
+ EFUSE_OUTPUT(16);
+ EFUSE_OUTPUT(17);
+ EFUSE_OUTPUT(18);
+ EFUSE_OUTPUT(19);
+ EFUSE_OUTPUT(20);
+ EFUSE_OUTPUT(21);
+ EFUSE_OUTPUT(22);
+ EFUSE_OUTPUT(23);
+ EFUSE_OUTPUT(24);
+ EFUSE_OUTPUT(25);
+ EFUSE_OUTPUT(26);
+ EFUSE_OUTPUT(27);
+ EFUSE_OUTPUT(28);
+ EFUSE_OUTPUT(29);
+ EFUSE_OUTPUT(30);
+ EFUSE_OUTPUT(31);
+ EFUSE_OUTPUT(32);
+ EFUSE_OUTPUT(33);
+ EFUSE_OUTPUT(34);
+ EFUSE_OUTPUT(35);
+ EFUSE_OUTPUT(36);
+ EFUSE_OUTPUT(37);
+ EFUSE_OUTPUT(38);
+ EFUSE_OUTPUT(39);
+ EFUSE_OUTPUT(40);
+ EFUSE_OUTPUT(41);
+ EFUSE_OUTPUT(42);
+ EFUSE_OUTPUT(43);
+ EFUSE_OUTPUT(44);
+ EFUSE_OUTPUT(45);
+ EFUSE_OUTPUT(46);
+ EFUSE_OUTPUT(47);
+ EFUSE_OUTPUT(48);
+ EFUSE_OUTPUT(49);
+ EFUSE_OUTPUT(50);
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "flash0";
+ spi-max-frequency = <50000000>; // 50 MHz
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&mac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&i2c0 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@79 {
+ compatible = "nxp,pca9541";
+ reg = <0x79>;
+
+ i2carb0: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* lm25066 efuses @ 10-17, 40-47, 50-57 */
+ EFUSE(10, 03);
+ EFUSE(11, 04);
+ EFUSE(12, 01);
+ EFUSE(13, 02);
+ EFUSE(14, 13);
+ EFUSE(15, 14);
+ EFUSE(16, 15);
+ EFUSE(17, 16);
+ EFUSE(40, 12);
+ EFUSE(41, 11);
+ EFUSE(42, 10);
+ EFUSE(43, 09);
+ EFUSE(44, 08);
+ EFUSE(45, 07);
+ EFUSE(46, 05);
+ EFUSE(47, 06);
+ EFUSE(50, 17);
+ EFUSE(51, 18);
+ EFUSE(52, 20);
+ EFUSE(53, 19);
+ EFUSE(54, 22);
+ EFUSE(55, 21);
+ EFUSE(56, 24);
+ EFUSE(57, 23);
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@72 {
+ compatible = "nxp,pca9541";
+ reg = <0x72>;
+
+ i2carb1: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@73 {
+ compatible = "nxp,pca9541";
+ reg = <0x73>;
+
+ i2carb2: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@74 {
+ compatible = "nxp,pca9541";
+ reg = <0x74>;
+
+ i2carb3: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c4 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@7a {
+ compatible = "nxp,pca9541";
+ reg = <0x7a>;
+
+ i2carb4: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9534";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ /* lm25066 efuses @ 10-17, 40-47, 50-57, 59, 5a */
+ EFUSE(10, 27);
+ EFUSE(11, 28);
+ EFUSE(12, 25);
+ EFUSE(13, 26);
+ EFUSE(14, 37);
+ EFUSE(15, 38);
+ EFUSE(16, 39);
+ EFUSE(17, 40);
+ EFUSE(40, 36);
+ EFUSE(41, 35);
+ EFUSE(42, 34);
+ EFUSE(43, 33);
+ EFUSE(44, 32);
+ EFUSE(45, 31);
+ EFUSE(46, 29);
+ EFUSE(47, 30);
+ EFUSE(50, 41);
+ EFUSE(51, 42);
+ EFUSE(52, 44);
+ EFUSE(53, 43);
+ EFUSE(54, 46);
+ EFUSE(55, 45);
+ EFUSE(56, 48);
+ EFUSE(57, 47);
+ EFUSE(59, 49);
+ EFUSE(5a, 50);
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@75 {
+ compatible = "nxp,pca9541";
+ reg = <0x75>;
+
+ i2carb6: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@76 {
+ compatible = "nxp,pca9541";
+ reg = <0x76>;
+
+ i2carb7: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@7c {
+ compatible = "nxp,pca9541";
+ reg = <0x7c>;
+
+ i2carb8: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fancontrol@30 {
+ compatible = "delta,ahe50dc-fan";
+ reg = <0x30>;
+ };
+
+ /* Baseboard FRU eeprom */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+ };
+ };
+};
+
+&i2c12 {
+ status = "okay";
+ bus-frequency = <200000>;
+
+ pca9541@71 {
+ compatible = "nxp,pca9541";
+ reg = <0x71>;
+
+ i2carb12: i2c-arb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names =
+ /* A */ "", "", "", "", "", "", "", "",
+ /* B */ "", "", "", "", "", "", "", "",
+ /* C */ "RESET_PEER_N", "HEARTBEAT_OUT", "", "", "", "", "", "",
+ /* D */ "", "", "", "", "", "", "", "",
+ /* E */ "DOOM_N", "", "", "", "", "LED_PWR_BLUE", "", "",
+ /* F */ "", "", "", "", "", "", "", "",
+ /* G */ "", "", "", "", "", "", "", "",
+ /* H */ "", "", "", "", "", "", "", "",
+ /* I */ "", "", "", "", "", "", "", "",
+ /* J */ "", "", "BMC_ID", "", "", "", "", "",
+ /* K */ "", "", "", "", "", "", "", "",
+ /* L */ "", "", "", "", "", "", "", "",
+ /* M */ "", "", "", "", "", "", "", "",
+ /* N */ "", "", "", "", "", "", "", "",
+ /* O */ "", "", "", "", "", "", "", "",
+ /* P */ "LED_GREEN", "", "LED_RED", "", "", "", "", "",
+ /* Q */ "", "", "", "", "", "", "", "",
+ /* R */ "", "", "", "", "", "", "", "",
+ /* S */ "", "", "", "", "", "", "", "",
+ /* T */ "", "", "", "", "", "", "", "",
+ /* U */ "", "", "", "", "", "", "", "",
+ /* V */ "", "", "", "", "", "", "", "",
+ /* W */ "", "", "", "", "", "", "", "",
+ /* X */ "", "", "", "", "", "", "", "",
+ /* Y */ "HEARTBEAT_IN", "BOARDREV0", "BOARDREV1", "",
+ /* Z */ "", "", "", "", "", "", "", "",
+ /* AA */ "", "", "", "", "", "", "", "",
+ /* AB */ "", "", "", "";
+
+ /*
+ * I don't rightly know what this GPIO really *is*, but setting it to
+ * zero causes the fans to run at full speed, after which setting it
+ * back to one causes a power output glitch, so install a hog to keep
+ * it at one as a failsafe to ensure nothing accidentally touches it.
+ */
+ doom-guardrail {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(E, 0) GPIO_ACTIVE_LOW>;
+ output-low;
+ };
+};
+
+&adc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default
+ &pinctrl_adc8_default
+ &pinctrl_adc9_default>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
index eaf1bc261ee3..e899de681f47 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/leds/leds-pca955x.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/i2c/i2c.h>
/ {
model = "Facebook Bletchley BMC";
@@ -51,26 +52,6 @@
};
};
- spi2_gpio: spi2-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
- num-chipselects = <1>;
- cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- m25p,fast-read;
- label = "pnor";
- spi-max-frequency = <100000000>;
- };
- };
-
switchphy: ethernet-phy@0 {
// Fixed link
};
@@ -79,7 +60,7 @@
compatible = "gpio-leds";
sys_log_id {
default-state = "off";
- gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>;
+ gpios = <&front_leds 0 GPIO_ACTIVE_LOW>;
};
};
@@ -210,6 +191,95 @@
gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>;
};
};
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ presence-sled1 {
+ label = "presence-sled1";
+ gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 2)>;
+ };
+ presence-sled2 {
+ label = "presence-sled2";
+ gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 3)>;
+ };
+ presence-sled3 {
+ label = "presence-sled3";
+ gpios = <&gpio0 ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 4)>;
+ };
+ presence-sled4 {
+ label = "presence-sled4";
+ gpios = <&gpio0 ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 5)>;
+ };
+ presence-sled5 {
+ label = "presence-sled5";
+ gpios = <&gpio0 ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 6)>;
+ };
+ presence-sled6 {
+ label = "presence-sled6";
+ gpios = <&gpio0 ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 7)>;
+ };
+ };
+
+ vbus_sled1: vbus_sled1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_sled1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&sled1_ioexp 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vbus_sled2: vbus_sled2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_sled2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&sled2_ioexp 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vbus_sled3: vbus_sled3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_sled3";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&sled3_ioexp 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vbus_sled4: vbus_sled4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_sled4";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&sled4_ioexp 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vbus_sled5: vbus_sled5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_sled5";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&sled5_ioexp 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vbus_sled6: vbus_sled6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_sled6";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&sled6_ioexp 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&mac2 {
@@ -237,7 +307,20 @@
flash@1 {
status = "okay";
m25p,fast-read;
- label = "flash1";
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&spi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
spi-max-frequency = <50000000>;
};
};
@@ -260,6 +343,17 @@
reg = <0x4f>;
};
+ sled1_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED1_SWD_MUX", "SLED1_XRES_SWD_N",
+ "SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN";
+ };
+
sled1_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -297,19 +391,24 @@
compatible = "fcs,fusb302";
reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <ASPEED_GPIO(B, 0) IRQ_TYPE_LEVEL_LOW>;
+ vbus-supply = <&vbus_sled1>;
+
connector {
compatible = "usb-c-connector";
label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- data-role = "dual";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(3000, 12000, 3000)
- PDO_PPS_APDO(3000, 11000, 3000)>;
- op-sink-microwatt = <10000000>;
+ power-role = "source";
+ data-role = "host";
+ pd-disable;
+ typec-power-opmode = "default";
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c1 {
@@ -330,6 +429,17 @@
reg = <0x4f>;
};
+ sled2_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED2_SWD_MUX", "SLED2_XRES_SWD_N",
+ "SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN";
+ };
+
sled2_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -367,19 +477,24 @@
compatible = "fcs,fusb302";
reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <ASPEED_GPIO(B, 1) IRQ_TYPE_LEVEL_LOW>;
+ vbus-supply = <&vbus_sled2>;
+
connector {
compatible = "usb-c-connector";
label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- data-role = "dual";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(3000, 12000, 3000)
- PDO_PPS_APDO(3000, 11000, 3000)>;
- op-sink-microwatt = <10000000>;
+ power-role = "source";
+ data-role = "host";
+ pd-disable;
+ typec-power-opmode = "default";
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c2 {
@@ -400,6 +515,17 @@
reg = <0x4f>;
};
+ sled3_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED3_SWD_MUX", "SLED3_XRES_SWD_N",
+ "SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN";
+ };
+
sled3_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -437,19 +563,24 @@
compatible = "fcs,fusb302";
reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <ASPEED_GPIO(B, 7) IRQ_TYPE_LEVEL_LOW>;
+ vbus-supply = <&vbus_sled3>;
+
connector {
compatible = "usb-c-connector";
label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- data-role = "dual";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(3000, 12000, 3000)
- PDO_PPS_APDO(3000, 11000, 3000)>;
- op-sink-microwatt = <10000000>;
+ power-role = "source";
+ data-role = "host";
+ pd-disable;
+ typec-power-opmode = "default";
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c3 {
@@ -470,6 +601,17 @@
reg = <0x4f>;
};
+ sled4_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED4_SWD_MUX", "SLED4_XRES_SWD_N",
+ "SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN";
+ };
+
sled4_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -507,19 +649,24 @@
compatible = "fcs,fusb302";
reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <ASPEED_GPIO(S, 7) IRQ_TYPE_LEVEL_LOW>;
+ vbus-supply = <&vbus_sled4>;
+
connector {
compatible = "usb-c-connector";
label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- data-role = "dual";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(3000, 12000, 3000)
- PDO_PPS_APDO(3000, 11000, 3000)>;
- op-sink-microwatt = <10000000>;
+ power-role = "source";
+ data-role = "host";
+ pd-disable;
+ typec-power-opmode = "default";
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c4 {
@@ -540,6 +687,17 @@
reg = <0x4f>;
};
+ sled5_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED5_SWD_MUX", "SLED5_XRES_SWD_N",
+ "SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN";
+ };
+
sled5_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -577,19 +735,24 @@
compatible = "fcs,fusb302";
reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <ASPEED_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>;
+ vbus-supply = <&vbus_sled5>;
+
connector {
compatible = "usb-c-connector";
label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- data-role = "dual";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(3000, 12000, 3000)
- PDO_PPS_APDO(3000, 11000, 3000)>;
- op-sink-microwatt = <10000000>;
+ power-role = "source";
+ data-role = "host";
+ pd-disable;
+ typec-power-opmode = "default";
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c5 {
@@ -610,6 +773,17 @@
reg = <0x4f>;
};
+ sled6_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED6_SWD_MUX", "SLED6_XRES_SWD_N",
+ "SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN";
+ };
+
sled6_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -647,19 +821,24 @@
compatible = "fcs,fusb302";
reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <ASPEED_GPIO(I, 7) IRQ_TYPE_LEVEL_LOW>;
+ vbus-supply = <&vbus_sled6>;
+
connector {
compatible = "usb-c-connector";
label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- data-role = "dual";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(3000, 12000, 3000)
- PDO_PPS_APDO(3000, 11000, 3000)>;
- op-sink-microwatt = <10000000>;
+ power-role = "source";
+ data-role = "host";
+ pd-disable;
+ typec-power-opmode = "default";
};
};
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
};
&i2c6 {
@@ -703,11 +882,6 @@
reg = <0x4f>;
};
- hdc1080@40 {
- compatible = "ti,hdc1080";
- reg = <0x40>;
- };
-
front_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
@@ -732,6 +906,8 @@
compatible = "adi,adm1278";
reg = <0x11>;
shunt-resistor-micro-ohms = <300>;
+ adi,volt-curr-sample-average = <128>;
+ adi,power-sample-average = <128>;
};
tmp421@4c {
@@ -766,48 +942,70 @@
multi-master;
aspeed,hw-timeout-ms = <1000>;
status = "okay";
+
+ //USB Debug Connector
+ ipmb13@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
};
&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiov2_unbiased_default>;
+
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
- /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1",
- "SPI2_MUX2","SPI2_MUX3","","",
+ /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N",
+ "SEL_SPI2_MUX","SPI2_MUX1",
+ "SPI2_MUX2","SPI2_MUX3",
+ "","FUSB302_SLED3_INT_N",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
- /*F0-F7*/ "","","","","","","","",
- /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","",
+ /*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK",
+ "BMC_SLED3_STCK","BMC_SLED4_STCK",
+ "BMC_SLED5_STCK","BMC_SLED6_STCK",
+ "","",
+ /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL",
"PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","",
/*H0-H7*/ "presence-riser1","presence-riser2",
"presence-sled1","presence-sled2",
"presence-sled3","presence-sled4",
"presence-sled5","presence-sled6",
- /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2",
- "","BSM_FLASH_WP_STATUS","BMC_TPM_PRES","",
+ /*I0-I7*/ "REV_ID0","",
+ "REV_ID1","REV_ID2",
+ "","BSM_FLASH_WP_STATUS",
+ "BMC_TPM_PRES_N","FUSB302_SLED6_INT_N",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","BMC_RTC_INT","","",
- /*M0-M7*/ "ALERT_SLED1","ALERT_SLED2",
- "ALERT_SLED3","ALERT_SLED4",
- "ALERT_SLED5","ALERT_SLED6",
- "P12V_AUX_ALERT1","",
- /*N0-N7*/ "","","","","","","","",
+ /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N",
+ "ALERT_SLED3_N","ALERT_SLED4_N",
+ "ALERT_SLED5_N","ALERT_SLED6_N",
+ "","USB_DEBUG_PWR_BTN_N",
+ /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1",
+ "LED_POSTCODE_2","LED_POSTCODE_3",
+ "LED_POSTCODE_4","LED_POSTCODE_5",
+ "LED_POSTCODE_6","LED_POSTCODE_7",
/*O0-O7*/ "","","","",
"","BOARD_ID0","BOARD_ID1","BOARD_ID2",
/*P0-P7*/ "","","","","","","","BMC_HEARTBEAT",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","BAT_DETECT",
- "BMC_BT_WP0","BMC_BT_WP1","","",
+ "BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
- /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL","","PSU_PRSNT",
+ /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N",
+ "P12V_AUX_ALERT1_N","PSU_PRSNT",
"USB2_SEL0_A","USB2_SEL1_A",
"USB2_SEL0_B","USB2_SEL1_B",
- /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","",
+ /*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","",
/*X0-X7*/ "","","","","","","","",
- /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT","BSM_FLASH_LATCH","",
+ /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N",
+ "BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N",
"","","","",
/*Z0-Z7*/ "","","","","","","","";
};
@@ -834,7 +1032,46 @@
&pinctrl_adc14_default &pinctrl_adc15_default>;
};
+&mdio0 {
+ status = "okay";
+ /* TODO: Add Marvell 88E6191X */
+};
+
&mdio3 {
status = "okay";
/* TODO: Add Marvell 88X3310 */
};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emmc_controller {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl_gpiov2_unbiased_default: gpiov2 {
+ pins = "AD14";
+ bias-disable;
+ };
+};
+
+&wdt1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+ aspeed,reset-type = "soc";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+ aspeed,ext-pulse-duration = <256>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts
index 9c6271a17ae8..5cd060029ea9 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts
@@ -77,7 +77,7 @@
i2c55 = &imux55;
};
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
num-chipselects = <2>;
cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>,
<&gpio0 ASPEED_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts
index 27b43fe099f1..b5cd4c7800b0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts
@@ -44,7 +44,7 @@
stdout-path = &uart5;
};
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
num-chipselects = <1>;
cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
};
@@ -183,3 +183,21 @@
&i2c11 {
status = "okay";
};
+
+/*
+ * BMC's "mac3" controller is connected to BCM53134P's IMP_RGMII port
+ * directly (fixed link, no PHY in between).
+ * Note: BMC's "mdio0" controller is connected to BCM53134P's MDIO
+ * interface, and the MDIO channel will be enabled in dts later, when
+ * BCM53134 is added to "bcm53xx" DSA driver.
+ */
+&mac3 {
+ status = "okay";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii4_default>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts
index af58a73bbc49..6b319f34a9b9 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts
@@ -207,7 +207,7 @@
i2c143 = &imux143;
};
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
num-chipselects = <3>;
cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>,
<0>, /* device reg=<1> does not exist */
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
new file mode 100644
index 000000000000..7a53f54833a0
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2022 Facebook Inc.
+
+/dts-v1/;
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Facebook Greatlakes BMC";
+ compatible = "facebook,greatlakes-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 0>, <&adc1 2>, <&adc1 3>, <&adc1 4>,
+ <&adc1 5>, <&adc1 6>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&wdt1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+ aspeed,reset-type = "soc";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+ aspeed,ext-pulse-duration = <256>;
+};
+
+&mac3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+ no-hw-checksum;
+ use-ncsi;
+ mlx,multi-host;
+ ncsi-ctrl,start-redo-probe;
+ ncsi-ctrl,no-channel-monitor;
+ ncsi-package = <1>;
+ ncsi-channel = <1>;
+ ncsi-rexmit = <1>;
+ ncsi-timeout = <2>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64.dtsi"
+ };
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc2";
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ multi-master;
+ ipmb@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ multi-master;
+ ipmb@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ multi-master;
+ ipmb@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ multi-master;
+ ipmb@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+ mctp-controller;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ // NIC EEPROM
+ eeprom@50 {
+ compatible = "st,24c32";
+ reg = <0x50>;
+ };
+ mctp@10 {
+ compatible = "mctp-i2c-controller";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+ multi-master;
+ ipmb@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+ temperature-sensor@4f {
+ compatible = "lm75";
+ reg = <0x4f>;
+ };
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&adc0 {
+ ref_voltage = <2500>;
+ status = "okay";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+};
+
+&adc1 {
+ ref_voltage = <2500>;
+ status = "okay";
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default
+ &pinctrl_adc11_default &pinctrl_adc12_default
+ &pinctrl_adc13_default &pinctrl_adc14_default>;
+};
+
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>;
+
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "power-bmc-nic","presence-ocp-debug",
+ "power-bmc-slot1","power-bmc-slot2",
+ "power-bmc-slot3","power-bmc-slot4","","",
+ /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary",
+ "reset-cause-nic-secondary","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button",
+ "slot3-bmc-reset-button","slot4-bmc-reset-button",
+ "","","","presence-emmc",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","",
+ "presence-mb-slot1","presence-mb-slot2",
+ "presence-mb-slot3","presence-mb-slot4",
+ /*I0-I7*/ "","","","","","","bb-bmc-button","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","",
+ /*N0-N7*/ "","","","","bmc-ready","","","",
+ /*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable",
+ /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable",
+ "reset-cause-pcie-slot1","reset-cause-pcie-slot2",
+ "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","GND",
+ /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button",
+ "bmc-slot3-ac-button","bmc-slot4-ac-button",
+ "","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","reset-cause-emmc","","","","",
+ /*Z0-Z7*/ "","","","","","","","";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/ "","","","","","","","",
+ /*18B0-18B7*/ "","","","","","","","",
+ /*18C0-18C7*/ "","","","","","","","",
+ /*18D0-18D7*/ "","","","","","","","",
+ /*18E0-18E3*/ "","","","","","","","";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts
index a901c8be49b9..ed305948386f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts
@@ -67,7 +67,7 @@
* full-duplex SPI transactions are not supported by ASPEED SPI
* Controllers.
*/
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
status = "okay";
compatible = "spi-gpio";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts
index 8864e9c312a8..6bf2ff85a40e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts
@@ -207,11 +207,16 @@
&i2c12 {
status = "okay";
- //MEZZ_FRU
- eeprom@51 {
- compatible = "atmel,24c64";
- reg = <0x51>;
- pagesize = <32>;
+};
+
+&i2c13 {
+ status = "okay";
+ // Debug Card
+ multi-master;
+ ipmb13@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts
new file mode 100644
index 000000000000..81902cbe662c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts
@@ -0,0 +1,915 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2022 IBM Corp.
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Bonnell";
+ compatible = "ibm,bonnell-bmc", "aspeed,ast2600";
+
+ aliases {
+ i2c100 = &cfam0_i2c0;
+ i2c101 = &cfam0_i2c1;
+ i2c110 = &cfam0_i2c10;
+ i2c111 = &cfam0_i2c11;
+ i2c112 = &cfam0_i2c12;
+ i2c113 = &cfam0_i2c13;
+ i2c114 = &cfam0_i2c14;
+ i2c115 = &cfam0_i2c15;
+ i2c202 = &cfam1_i2c2;
+ i2c203 = &cfam1_i2c3;
+ i2c210 = &cfam1_i2c10;
+ i2c211 = &cfam1_i2c11;
+ i2c214 = &cfam1_i2c14;
+ i2c215 = &cfam1_i2c15;
+ i2c216 = &cfam1_i2c16;
+ i2c217 = &cfam1_i2c17;
+
+ serial4 = &uart5;
+ i2c16 = &i2c11mux0chn0;
+ i2c17 = &i2c11mux0chn1;
+ i2c18 = &i2c11mux0chn2;
+ i2c19 = &i2c11mux0chn3;
+
+ spi10 = &cfam0_spi0;
+ spi11 = &cfam0_spi1;
+ spi12 = &cfam0_spi2;
+ spi13 = &cfam0_spi3;
+ spi20 = &cfam1_spi0;
+ spi21 = &cfam1_spi1;
+ spi22 = &cfam1_spi2;
+ spi23 = &cfam1_spi3;
+
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8 earlycon";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ramoops@b3e00000 {
+ compatible = "ramoops";
+ reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
+ record-size = <0x8000>;
+ console-size = <0x8000>;
+ ftrace-size = <0x8000>;
+ pmsg-size = <0x8000>;
+ max-reason = <3>; /* KMSG_DUMP_EMERG */
+ };
+
+ /* LPC FW cycle bridge region requires natural alignment */
+ flash_memory: region@b4000000 {
+ no-map;
+ reg = <0xb4000000 0x04000000>; /* 64M */
+ };
+
+ /* VGA region is dictated by hardware strapping */
+ vga_memory: region@bf000000 {
+ no-map;
+ compatible = "shared-dma-pool";
+ reg = <0xbf000000 0x01000000>; /* 16M */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fan0 {
+ gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ fan1 {
+ gpios = <&gpio0 ASPEED_GPIO(G, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-enc-id0 {
+ gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-enc-fault0 {
+ gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&gpio0 ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&gpio0 ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc1 7>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc10_default &pinctrl_adc11_default
+ &pinctrl_adc12_default &pinctrl_adc13_default
+ &pinctrl_adc14_default &pinctrl_adc15_default>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gpio0 {
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "","","","","","","checkstop","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","","",
+ /*G0-G7*/ "fan0","fan1","","","","","","",
+ /*H0-H7*/ "","","rear-enc-id0","rear-enc-fault0","","","","",
+ /*I0-I7*/ "","","","","","","bmc-secure-boot","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","usb-power","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","",
+ /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","",
+ /*S0-S7*/ "presence-ps0","presence-ps1","","","power-ffs-sync-history","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","";
+
+ usb_power {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(O, 3) GPIO_ACTIVE_LOW>;
+ output-high;
+ };
+};
+
+&emmc_controller {
+ status = "okay";
+};
+
+&pinctrl_emmc_default {
+ bias-disable;
+};
+
+&emmc {
+ status = "okay";
+ clk-phase-mmc-hs200 = <180>, <180>;
+};
+
+&fsim0 {
+ status = "okay";
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam0_i2c0: i2c-bus@0 {
+ reg = <0>; /* OMI01 */
+ };
+
+ cfam0_i2c1: i2c-bus@1 {
+ reg = <1>; /* OMI23 */
+ };
+
+ cfam0_i2c10: i2c-bus@a {
+ reg = <10>; /* OP3A */
+ };
+
+ cfam0_i2c11: i2c-bus@b {
+ reg = <11>; /* OP3B */
+ };
+
+ cfam0_i2c12: i2c-bus@c {
+ reg = <12>; /* OP4A */
+ };
+
+ cfam0_i2c13: i2c-bus@d {
+ reg = <13>; /* OP4B */
+ };
+
+ cfam0_i2c14: i2c-bus@e {
+ reg = <14>; /* OP5A */
+ };
+
+ cfam0_i2c15: i2c-bus@f {
+ reg = <15>; /* OP5B */
+ };
+ };
+
+ fsi2spi@1c00 {
+ compatible = "ibm,fsi2spi";
+ reg = <0x1c00 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam0_spi0: spi@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam0_spi1: spi@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam0_spi2: spi@40 {
+ reg = <0x40>;
+ compatible = "ibm,fsi2spi-restricted";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam0_spi3: spi@60 {
+ reg = <0x60>;
+ compatible = "ibm,fsi2spi-restricted";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ0: occ {
+ compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
+ };
+ };
+
+ fsi_hub0: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&fsi_hub0 {
+ cfam@1,0 {
+ reg = <1 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <1>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam1_i2c2: i2c-bus@2 {
+ reg = <2>; /* OMI45 */
+ };
+
+ cfam1_i2c3: i2c-bus@3 {
+ reg = <3>; /* OMI67 */
+ };
+
+ cfam1_i2c10: i2c-bus@a {
+ reg = <10>; /* OP3A */
+ };
+
+ cfam1_i2c11: i2c-bus@b {
+ reg = <11>; /* OP3B */
+ };
+
+ cfam1_i2c14: i2c-bus@e {
+ reg = <14>; /* OP5A */
+ };
+
+ cfam1_i2c15: i2c-bus@f {
+ reg = <15>; /* OP5B */
+ };
+
+ cfam1_i2c16: i2c-bus@10 {
+ reg = <16>; /* OP6A */
+ };
+
+ cfam1_i2c17: i2c-bus@11 {
+ reg = <17>; /* OP6B */
+ };
+ };
+
+ fsi2spi@1c00 {
+ compatible = "ibm,fsi2spi";
+ reg = <0x1c00 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam1_spi0: spi@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam1_spi1: spi@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam1_spi2: spi@40 {
+ reg = <0x40>;
+ compatible = "ibm,fsi2spi-restricted";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam1_spi3: spi@60 {
+ reg = <0x60>;
+ compatible = "ibm,fsi2spi-restricted";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ1: occ {
+ compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
+ };
+ };
+
+ fsi_hub1: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+&ibt {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ tca9554@20 {
+ compatible = "ti,tca9554";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "",
+ "RUSSEL_FW_I2C_ENABLE_N",
+ "RUSSEL_OPPANEL_PRESENCE_N",
+ "BLYTH_OPPANEL_PRESENCE_N",
+ "CPU_TPM_CARD_PRESENT_N",
+ "",
+ "",
+ "DASD_BP_PRESENT_N";
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ power-supply@5a {
+ compatible = "acbel,fsg032";
+ reg = <0x5a>;
+ };
+
+ power-supply@5b {
+ compatible = "acbel,fsg032";
+ reg = <0x5b>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ multi-master;
+ status = "okay";
+
+ si7021-a20@40 {
+ compatible = "silabs,si7020";
+ reg = <0x40>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan0: fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ };
+
+ fan1: fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ };
+ };
+
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "front-sys-id0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "front-check-log0";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "front-enc-fault1";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "front-sys-pwron0";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ ibm-panel@62 {
+ compatible = "ibm,op-panel";
+ reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "",
+ "APSS_RESET_N",
+ "",
+ "N_MODE_CPU_N",
+ "",
+ "",
+ "P10_DCM_PRESENT",
+ "";
+ };
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ tca9554@20 {
+ compatible = "ti,tca9554";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "BOOT_RCVRY_TWI",
+ "BOOT_RCVRY_UART",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "PE_SWITCH_RSTB_N";
+ };
+
+ tmp435@4c {
+ compatible = "ti,tmp435";
+ reg = <0x4c>;
+ };
+
+ pca9849@75 {
+ compatible = "nxp,pca9849";
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ i2c-mux-idle-disconnect;
+
+ i2c11mux0chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c11mux0chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c11mux0chn2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c11mux0chn3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c12 {
+ status = "okay";
+
+ tpm@2e {
+ compatible = "nuvoton,npct75x";
+ reg = <0x2e>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&i2c13 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "nvme0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "nvme1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "nvme2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "nvme3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&vuart1 {
+ status = "okay";
+};
+
+&vuart2 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
+ <&syscon ASPEED_CLK_MAC3RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&xdma {
+ status = "okay";
+ memory-region = <&vga_memory>;
+};
+
+&kcs2 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca8 0xcac>;
+};
+
+&kcs3 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca2>;
+ aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
index 578f9e2fc7ed..c6f8f20914d1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
@@ -162,16 +162,14 @@
#size-cells = <1>;
ranges;
- /* LPC FW cycle bridge region requires natural alignment */
- flash_memory: region@b8000000 {
+ event_log: tcg_event_log@b3d00000 {
no-map;
- reg = <0xb8000000 0x04000000>; /* 64M */
+ reg = <0xb3d00000 0x100000>;
};
- /* 48MB region from the end of flash to start of vga memory */
- ramoops@bc000000 {
+ ramoops@b3e00000 {
compatible = "ramoops";
- reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */
+ reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x8000>;
@@ -179,6 +177,12 @@
max-reason = <3>; /* KMSG_DUMP_EMERG */
};
+ /* LPC FW cycle bridge region requires natural alignment */
+ flash_memory: region@b4000000 {
+ no-map;
+ reg = <0xb4000000 0x04000000>; /* 64M */
+ };
+
/* VGA region is dictated by hardware strapping */
vga_memory: region@bf000000 {
no-map;
@@ -189,29 +193,27 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca0 15 GPIO_ACTIVE_LOW>;
linux,code = <15>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
linux,code = <14>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
linux,code = <13>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca0 12 GPIO_ACTIVE_LOW>;
linux,code = <12>;
@@ -247,7 +249,7 @@
};
};
- iio-hwmon-battery {
+ iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 7>;
};
@@ -283,7 +285,7 @@
/*P0-P7*/ "","","","","led-pcieslot-power","","","",
/*Q0-Q7*/ "","","regulator-standby-faulted","","","","","",
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","",
- /*S0-S7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","power-ffs-sync-history","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","",
@@ -1890,6 +1892,7 @@
tpm@2e {
compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c";
reg = <0x2e>;
+ memory-region = <&event_log>;
};
};
@@ -2553,6 +2556,11 @@
fsi_occ0: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -2697,6 +2705,11 @@
fsi_occ1: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -2841,6 +2854,11 @@
fsi_occ2: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -2985,6 +3003,11 @@
fsi_occ3: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -3129,6 +3152,11 @@
fsi_occ4: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -3273,6 +3301,11 @@
fsi_occ5: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -3417,6 +3450,11 @@
fsi_occ6: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -3561,6 +3599,11 @@
fsi_occ7: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -3612,6 +3655,10 @@
status = "okay";
};
+&uart2 {
+ status = "okay";
+};
+
&vuart1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
index 528b49e2c0f8..7162e65b8115 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -95,14 +95,9 @@
#size-cells = <1>;
ranges;
- flash_memory: region@b8000000 {
- no-map;
- reg = <0xb8000000 0x04000000>; /* 64M */
- };
-
- ramoops@bc000000 {
+ ramoops@b3e00000 {
compatible = "ramoops";
- reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */
+ reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x8000>;
@@ -110,6 +105,13 @@
max-reason = <3>; /* KMSG_DUMP_EMERG */
};
+ /* LPC FW cycle bridge region requires natural alignment */
+ flash_memory: region@b4000000 {
+ no-map;
+ reg = <0xb4000000 0x04000000>; /* 64M */
+ };
+
+ /* VGA region is dictated by hardware strapping */
vga_memory: region@bf000000 {
no-map;
compatible = "shared-dma-pool";
@@ -179,48 +181,46 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca0 8 GPIO_ACTIVE_LOW>;
linux,code = <8>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca0 9 GPIO_ACTIVE_LOW>;
linux,code = <9>;
};
- fan4-presence {
+ event-fan4-presence {
label = "fan4-presence";
gpios = <&pca0 10 GPIO_ACTIVE_LOW>;
linux,code = <10>;
};
- fan5-presence {
+ event-fan5-presence {
label = "fan5-presence";
gpios = <&pca0 11 GPIO_ACTIVE_LOW>;
linux,code = <11>;
};
};
- iio-hwmon-battery {
+ iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 7>;
};
@@ -265,7 +265,7 @@
/*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","",
/*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","",
/*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3",
- "","","","",
+ "power-ffs-sync-history","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
@@ -444,6 +444,11 @@
fsi_occ0: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -588,6 +593,11 @@
fsi_occ1: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -732,6 +742,11 @@
fsi_occ2: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -876,6 +891,11 @@
fsi_occ3: occ {
compatible = "ibm,p10-occ";
+
+ occ-hwmon {
+ compatible = "ibm,p10-occ-hwmon";
+ ibm,no-poll-on-init;
+ };
};
};
@@ -997,32 +1017,6 @@
reg = <0x4a>;
};
- pca9551@60 {
- compatible = "nxp,pca9551";
- reg = <0x60>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- led@0 {
- label = "cablecard0-cxp-top";
- reg = <0>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
-
- led@1 {
- label = "cablecard0-cxp-bot";
- reg = <1>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
- };
-
pca9546@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -1040,6 +1034,32 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard0-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard0-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
i2c4mux0chn1: i2c@1 {
@@ -1079,58 +1099,6 @@
reg = <0x49>;
};
- pca9551@60 {
- compatible = "nxp,pca9551";
- reg = <0x60>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- led@0 {
- label = "cablecard3-cxp-top";
- reg = <0>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
-
- led@1 {
- label = "cablecard3-cxp-bot";
- reg = <1>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
- };
-
- pca9551@61 {
- compatible = "nxp,pca9551";
- reg = <0x61>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- led@0 {
- label = "cablecard4-cxp-top";
- reg = <0>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
-
- led@1 {
- label = "cablecard4-cxp-bot";
- reg = <1>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
- };
-
pca9546@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -1148,6 +1116,32 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard3-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard3-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
i2c5mux0chn1: i2c@1 {
@@ -1159,6 +1153,32 @@
compatible = "atmel,24c64";
reg = <0x51>;
};
+
+ pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard4-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard4-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
};
};
@@ -2011,32 +2031,6 @@
reg = <0x49>;
};
- pca9551@60 {
- compatible = "nxp,pca9551";
- reg = <0x60>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- led@0 {
- label = "cablecard10-cxp-top";
- reg = <0>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
-
- led@1 {
- label = "cablecard10-cxp-bot";
- reg = <1>;
- retain-state-shutdown;
- default-state = "keep";
- type = <PCA955X_TYPE_LED>;
- };
- };
-
pca9546@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -2054,6 +2048,32 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard10-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard10-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
i2c11mux0chn1: i2c@1 {
@@ -2332,6 +2352,10 @@
};
};
+&uart2 {
+ status = "okay";
+};
+
&vuart1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
index 60a39ea10ab1..208b0f094ed9 100644
--- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
@@ -73,19 +73,19 @@
gpio-keys {
compatible = "gpio-keys";
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(B, 3)>;
};
- ps0-presence {
+ event-ps0-presence {
label = "ps0-presence";
gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 0)>;
};
- ps1-presence {
+ event-ps1-presence {
label = "ps1-presence";
gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 1)>;
@@ -97,49 +97,49 @@
compatible = "gpio-keys-polled";
poll-interval = <1000>;
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca1 0 GPIO_ACTIVE_LOW>;
linux,code = <1>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca1 1 GPIO_ACTIVE_LOW>;
linux,code = <2>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca1 2 GPIO_ACTIVE_LOW>;
linux,code = <3>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca1 3 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
- fan4-presence {
+ event-fan4-presence {
label = "fan4-presence";
gpios = <&pca1 4 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
- fan5-presence {
+ event-fan5-presence {
label = "fan5-presence";
gpios = <&pca1 5 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
- fan6-presence {
+ event-fan6-presence {
label = "fan6-presence";
gpios = <&pca1 6 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
- fan7-presence {
+ event-fan7-presence {
label = "fan7-presence";
gpios = <&pca1 7 GPIO_ACTIVE_LOW>;
linux,code = <8>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
deleted file mode 100644
index a52a289cee85..000000000000
--- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
+++ /dev/null
@@ -1,1380 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/dts-v1/;
-#include "aspeed-g5.dtsi"
-#include <dt-bindings/gpio/aspeed-gpio.h>
-#include <dt-bindings/leds/leds-pca955x.h>
-
-/ {
- model = "Mihawk BMC";
- compatible = "ibm,mihawk-bmc", "aspeed,ast2500";
-
- aliases {
- i2c215 = &bus6_mux215;
- i2c216 = &bus6_mux216;
- i2c217 = &bus6_mux217;
- i2c218 = &bus6_mux218;
- i2c219 = &bus6_mux219;
- i2c220 = &bus6_mux220;
- i2c221 = &bus6_mux221;
- i2c222 = &bus6_mux222;
- i2c223 = &bus7_mux223;
- i2c224 = &bus7_mux224;
- i2c225 = &bus7_mux225;
- i2c226 = &bus7_mux226;
- i2c227 = &bus7_mux227;
- i2c228 = &bus7_mux228;
- i2c229 = &bus7_mux229;
- i2c230 = &bus7_mux230;
- i2c231 = &bus9_mux231;
- i2c232 = &bus9_mux232;
- i2c233 = &bus9_mux233;
- i2c234 = &bus9_mux234;
- i2c235 = &bus9_mux235;
- i2c236 = &bus9_mux236;
- i2c237 = &bus9_mux237;
- i2c238 = &bus9_mux238;
- i2c239 = &bus10_mux239;
- i2c240 = &bus10_mux240;
- i2c241 = &bus10_mux241;
- i2c242 = &bus10_mux242;
- i2c243 = &bus10_mux243;
- i2c244 = &bus10_mux244;
- i2c245 = &bus10_mux245;
- i2c246 = &bus10_mux246;
- i2c247 = &bus12_mux247;
- i2c248 = &bus12_mux248;
- i2c249 = &bus12_mux249;
- i2c250 = &bus12_mux250;
- i2c251 = &bus13_mux251;
- i2c252 = &bus13_mux252;
- i2c253 = &bus13_mux253;
- i2c254 = &bus13_mux254;
- i2c255 = &bus13_mux255;
- i2c256 = &bus13_mux256;
- i2c257 = &bus13_mux257;
- i2c258 = &bus13_mux258;
- };
-
- chosen {
- stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlycon";
- };
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- flash_memory: region@98000000 {
- no-map;
- reg = <0x98000000 0x04000000>; /* 64M */
- };
-
- gfx_memory: framebuffer {
- size = <0x01000000>;
- alignment = <0x01000000>;
- compatible = "shared-dma-pool";
- reusable;
- };
-
- video_engine_memory: jpegbuffer {
- size = <0x02000000>;
- alignment = <0x01000000>;
- compatible = "shared-dma-pool";
- reusable;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- air-water {
- label = "air-water";
- gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(F, 6)>;
- };
-
- checkstop {
- label = "checkstop";
- gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(J, 2)>;
- };
-
- ps0-presence {
- label = "ps0-presence";
- gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(Z, 2)>;
- };
-
- ps1-presence {
- label = "ps1-presence";
- gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(Z, 0)>;
- };
- id-button {
- label = "id-button";
- gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
- linux,code = <ASPEED_GPIO(F, 1)>;
- };
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <1000>;
-
- fan0-presence {
- label = "fan0-presence";
- gpios = <&pca9552 9 GPIO_ACTIVE_LOW>;
- linux,code = <9>;
- };
-
- fan1-presence {
- label = "fan1-presence";
- gpios = <&pca9552 10 GPIO_ACTIVE_LOW>;
- linux,code = <10>;
- };
-
- fan2-presence {
- label = "fan2-presence";
- gpios = <&pca9552 11 GPIO_ACTIVE_LOW>;
- linux,code = <11>;
- };
-
- fan3-presence {
- label = "fan3-presence";
- gpios = <&pca9552 12 GPIO_ACTIVE_LOW>;
- linux,code = <12>;
- };
-
- fan4-presence {
- label = "fan4-presence";
- gpios = <&pca9552 13 GPIO_ACTIVE_LOW>;
- linux,code = <13>;
- };
-
- fan5-presence {
- label = "fan5-presence";
- gpios = <&pca9552 14 GPIO_ACTIVE_LOW>;
- linux,code = <14>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- front-fault {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>;
- };
-
- power-button {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>;
- };
-
- front-id {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
- };
-
-
- fan0 {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&pca9552 0 GPIO_ACTIVE_LOW>;
- };
-
- fan1 {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&pca9552 1 GPIO_ACTIVE_LOW>;
- };
-
- fan2 {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&pca9552 2 GPIO_ACTIVE_LOW>;
- };
-
- fan3 {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&pca9552 3 GPIO_ACTIVE_LOW>;
- };
-
- fan4 {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&pca9552 4 GPIO_ACTIVE_LOW>;
- };
-
- fan5 {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&pca9552 5 GPIO_ACTIVE_LOW>;
- };
- };
-
- fsi: gpio-fsi {
- compatible = "fsi-master-gpio", "fsi-master";
- #address-cells = <2>;
- #size-cells = <0>;
- no-gpio-delays;
-
- clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>;
- data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>;
- mux-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>;
- enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
- trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
- };
- iio-hwmon-12v {
- compatible = "iio-hwmon";
- io-channels = <&adc 0>;
- };
-
- iio-hwmon-5v {
- compatible = "iio-hwmon";
- io-channels = <&adc 1>;
- };
-
- iio-hwmon-3v {
- compatible = "iio-hwmon";
- io-channels = <&adc 2>;
- };
-
- iio-hwmon-vdd0 {
- compatible = "iio-hwmon";
- io-channels = <&adc 3>;
- };
-
- iio-hwmon-vdd1 {
- compatible = "iio-hwmon";
- io-channels = <&adc 4>;
- };
-
- iio-hwmon-vcs0 {
- compatible = "iio-hwmon";
- io-channels = <&adc 5>;
- };
-
- iio-hwmon-vcs1 {
- compatible = "iio-hwmon";
- io-channels = <&adc 6>;
- };
-
- iio-hwmon-vdn0 {
- compatible = "iio-hwmon";
- io-channels = <&adc 7>;
- };
-
- iio-hwmon-vdn1 {
- compatible = "iio-hwmon";
- io-channels = <&adc 8>;
- };
-
- iio-hwmon-vio0 {
- compatible = "iio-hwmon";
- io-channels = <&adc 9>;
- };
-
- iio-hwmon-vio1 {
- compatible = "iio-hwmon";
- io-channels = <&adc 10>;
- };
-
- iio-hwmon-vddra {
- compatible = "iio-hwmon";
- io-channels = <&adc 11>;
- };
-
- iio-hwmon-battery {
- compatible = "iio-hwmon";
- io-channels = <&adc 12>;
- };
-
- iio-hwmon-vddrb {
- compatible = "iio-hwmon";
- io-channels = <&adc 13>;
- };
-
- iio-hwmon-vddrc {
- compatible = "iio-hwmon";
- io-channels = <&adc 14>;
- };
-
- iio-hwmon-vddrd {
- compatible = "iio-hwmon";
- io-channels = <&adc 15>;
- };
-};
-
-&pwm_tacho {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
- &pinctrl_pwm2_default &pinctrl_pwm3_default
- &pinctrl_pwm4_default &pinctrl_pwm5_default>;
-
- fan@0 {
- reg = <0x00>;
- aspeed,fan-tach-ch = /bits/ 8 <0x00>;
- };
-
- fan@1 {
- reg = <0x01>;
- aspeed,fan-tach-ch = /bits/ 8 <0x01>;
- };
-
- fan@2 {
- reg = <0x02>;
- aspeed,fan-tach-ch = /bits/ 8 <0x02>;
- };
-
- fan@3 {
- reg = <0x03>;
- aspeed,fan-tach-ch = /bits/ 8 <0x03>;
- };
-
- fan@4 {
- reg = <0x04>;
- aspeed,fan-tach-ch = /bits/ 8 <0x04>;
- };
-
- fan@5 {
- reg = <0x05>;
- aspeed,fan-tach-ch = /bits/ 8 <0x05>;
- };
-
- fan@6 {
- reg = <0x00>;
- aspeed,fan-tach-ch = /bits/ 8 <0x06>;
- };
-
- fan@7 {
- reg = <0x01>;
- aspeed,fan-tach-ch = /bits/ 8 <0x07>;
- };
-
- fan@8 {
- reg = <0x02>;
- aspeed,fan-tach-ch = /bits/ 8 <0x08>;
- };
-
- fan@9 {
- reg = <0x03>;
- aspeed,fan-tach-ch = /bits/ 8 <0x09>;
- };
-
- fan@10 {
- reg = <0x04>;
- aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
- };
-
- fan@11 {
- reg = <0x05>;
- aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
- };
-};
-
-&gpio {
- gpio-line-names =
- /*A0-A7*/ "","cfam-reset","","","","","","",
- /*B0-B7*/ "","","","","","","","",
- /*C0-C7*/ "","","","","","","","",
- /*D0-D7*/ "fsi-enable","","","","","","","",
- /*E0-E7*/ "","","","","","fsi-mux","fsi-clock","fsi-data",
- /*F0-F7*/ "","id-button","","","","","air-water","",
- /*G0-G7*/ "","","","","","","","",
- /*H0-H7*/ "","","","","","","","",
- /*I0-I7*/ "","","","","","","","",
- /*J0-J7*/ "","","checkstop","","","","","",
- /*K0-K7*/ "","","","","","","","",
- /*L0-L7*/ "","","","","","","","",
- /*M0-M7*/ "","","","","","","","",
- /*N0-N7*/ "","","","","","","","",
- /*O0-O7*/ "","","","","","","","",
- /*P0-P7*/ "","","","","","","","",
- /*Q0-Q7*/ "","","","","","","","",
- /*R0-R7*/ "","","fsi-trans","","","","","",
- /*S0-S7*/ "","","","","","","","",
- /*T0-T7*/ "","","","","","","","",
- /*U0-U7*/ "","","","","","","","",
- /*V0-V7*/ "","","","","","","","",
- /*W0-W7*/ "","","","","","","","",
- /*X0-X7*/ "","","","","","","","",
- /*Y0-Y7*/ "","","","","","","","",
- /*Z0-Z7*/ "presence-ps1","","presence-ps0","","","","","",
- /*AA0-AA7*/ "led-front-fault","power-button","led-front-id","","","","","",
- /*AB0-AB7*/ "","","","","","","","",
- /*AC0-AC7*/ "","","","","","","","";
-};
-
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- label = "bmc";
- m25p,fast-read;
- spi-max-frequency = <50000000>;
- partitions {
- #address-cells = < 1 >;
- #size-cells = < 1 >;
- compatible = "fixed-partitions";
- u-boot@0 {
- reg = < 0 0x60000 >;
- label = "u-boot";
- };
- u-boot-env@60000 {
- reg = < 0x60000 0x20000 >;
- label = "u-boot-env";
- };
- obmc-ubi@80000 {
- reg = < 0x80000 0x1F80000 >;
- label = "obmc-ubi";
- };
- };
- };
- flash@1 {
- status = "okay";
- label = "alt-bmc";
- m25p,fast-read;
- spi-max-frequency = <50000000>;
- partitions {
- #address-cells = < 1 >;
- #size-cells = < 1 >;
- compatible = "fixed-partitions";
- u-boot@0 {
- reg = < 0 0x60000 >;
- label = "alt-u-boot";
- };
- u-boot-env@60000 {
- reg = < 0x60000 0x20000 >;
- label = "alt-u-boot-env";
- };
- obmc-ubi@80000 {
- reg = < 0x80000 0x1F80000 >;
- label = "alt-obmc-ubi";
- };
- };
- };
-};
-
-&spi1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1_default>;
-
- flash@0 {
- status = "okay";
- label = "pnor";
- m25p,fast-read;
- spi-max-frequency = <100000000>;
- };
-};
-
-&lpc_ctrl {
- status = "okay";
- memory-region = <&flash_memory>;
- flash = <&spi1>;
-};
-
-&uart1 {
- /* Rear RS-232 connector */
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd1_default
- &pinctrl_rxd1_default
- &pinctrl_nrts1_default
- &pinctrl_ndtr1_default
- &pinctrl_ndsr1_default
- &pinctrl_ncts1_default
- &pinctrl_ndcd1_default
- &pinctrl_nri1_default>;
-};
-
-&uart2 {
- /* APSS */
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
-};
-
-&uart5 {
- status = "okay";
-};
-
-&mac0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rmii1_default>;
- clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
- <&syscon ASPEED_CLK_MAC1RCLK>;
- clock-names = "MACCLK", "RCLK";
- use-ncsi;
-};
-
-&mac1 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
-};
-
-&i2c0 {
- status = "disabled";
-};
-
-&i2c1 {
- status = "disabled";
-};
-
-&i2c2 {
- status = "okay";
-
- /* SAMTEC P0 */
- /* SAMTEC P1 */
-
-};
-
-&i2c3 {
- status = "okay";
-
- /* APSS */
- /* CPLD */
-
- /* PCA9516 (repeater) ->
- * CLK Buffer 9FGS9092
- * CLK Buffer 9DBL0651BKILFT
- * CLK Buffer 9DBL0651BKILFT
- * Power Supply 0
- * Power Supply 1
- * PCA 9552 LED
- */
-
- power-supply@58 {
- compatible = "ibm,cffps1";
- reg = <0x58>;
- };
-
- power-supply@5b {
- compatible = "ibm,cffps1";
- reg = <0x5b>;
- };
-
- pca9552: pca9552@60 {
- compatible = "nxp,pca9552";
- reg = <0x60>;
- #address-cells = <1>;
- #size-cells = <0>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio@0 {
- reg = <0>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@1 {
- reg = <1>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@2 {
- reg = <2>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@3 {
- reg = <3>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@4 {
- reg = <4>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@5 {
- reg = <5>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@6 {
- reg = <6>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@7 {
- reg = <7>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@8 {
- reg = <8>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@9 {
- reg = <9>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@10 {
- reg = <10>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@11 {
- reg = <11>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@12 {
- reg = <12>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@13 {
- reg = <13>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@14 {
- reg = <14>;
- type = <PCA955X_TYPE_GPIO>;
- };
- gpio@15 {
- reg = <15>;
- type = <PCA955X_TYPE_GPIO>;
- };
-
- };
-
-};
-
-&i2c4 {
- status = "okay";
-
- /* CP0 VDD & VCS : IR35221 */
- /* CP0 VDN : IR35221 */
- /* CP0 VIO : IR38064 */
- /* CP0 VDDR : PXM1330 */
-
- ir35221@70 {
- compatible = "infineon,ir35221";
- reg = <0x70>;
- };
-
- ir35221@72 {
- compatible = "infineon,ir35221";
- reg = <0x72>;
- };
-
-};
-
-&i2c5 {
- status = "okay";
-
- /* CP0 VDD & VCS : IR35221 */
- /* CP0 VDN : IR35221 */
- /* CP0 VIO : IR38064 */
- /* CP0 VDDR : PXM1330 */
-
- ir35221@70 {
- compatible = "infineon,ir35221";
- reg = <0x70>;
- };
-
- ir35221@72 {
- compatible = "infineon,ir35221";
- reg = <0x72>;
- };
-
-};
-
-&i2c6 {
- status = "okay";
-
- /* pca9548 -> NVMe1 to 8 */
-
- pca9548@70 {
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- bus7_mux223: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- bus7_mux224: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- bus7_mux225: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- bus7_mux226: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
-
- bus7_mux227: i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
- };
-
- bus7_mux228: i2c@5 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <5>;
- };
-
- bus7_mux229: i2c@6 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <6>;
- };
-
- bus7_mux230: i2c@7 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <7>;
- };
- };
-
-};
-
-&i2c7 {
- status = "okay";
-
- /* pca9548 -> NVMe9 to 16 */
-
- pca9548@70 {
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- bus6_mux215: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- bus6_mux216: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- bus6_mux217: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- bus6_mux218: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
-
- bus6_mux219: i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
- };
-
- bus6_mux220: i2c@5 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <5>;
- };
-
- bus6_mux221: i2c@6 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <6>;
- };
-
- bus6_mux222: i2c@7 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <7>;
- };
- };
-
-};
-
-&i2c8 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
-};
-
-&i2c9 {
- status = "okay";
-
- /* pca9545 Riser ->
- * PCIe x8 Slot3
- * PCIe x16 slot4
- * PCIe x8 slot5
- * I2C BMC RISER PCA9554
- * BMC SCL/SDA PCA9554
- * PCA9554
- */
-
- /* pca9545 ->
- * PCIe x16 Slot1
- * PCIe x8 slot2
- * PEX8748
- */
-
- pca9545riser@70 {
- compatible = "nxp,pca9545";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- i2c-mux-idle-disconnect;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- bus9_mux231: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus0-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus0";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus9_mux232: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus1-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus1";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus9_mux233: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- bus9_mux234: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
-
- pca9545@71 {
- compatible = "nxp,pca9545";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x71>;
-
- i2c-mux-idle-disconnect;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- bus9_mux235: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus2-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus2";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus9_mux236: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus3-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus3";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus9_mux237: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- bus9_mux238: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
-};
-
-&i2c10 {
- status = "okay";
-
- /* pca9545 Riser ->
- * PCIe x8 Slot8
- * PCIe x16 slot9
- * PCIe x8 slot10
- * I2C BMC RISER PCA9554
- * BMC SCL/SDA PCA9554
- * PCA9554
- */
-
- /* pca9545 ->
- * PCIe x16 Slot1
- * PCIe x8 slot2
- * PEX8748
- */
-
- pca9545riser@70 {
- compatible = "nxp,pca9545";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- i2c-mux-idle-disconnect;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- bus10_mux239: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus4-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus4";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus10_mux240: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus5-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus5";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus10_mux241: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- bus10_mux242: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
-
- pca9545@71 {
- compatible = "nxp,pca9545";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x71>;
-
- i2c-mux-idle-disconnect;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- bus10_mux243: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus6-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus6";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus10_mux244: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tca9554@39 {
- compatible = "ti,tca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
-
- smbus7-hog {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "smbus7";
- };
- };
-
- tmp431@4c {
- compatible = "ti,tmp401";
- reg = <0x4c>;
- };
- };
-
- bus10_mux245: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- bus10_mux246: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
-};
-
-&i2c11 {
- status = "okay";
-
- /* TPM */
- /* RTC RX8900CE */
- /* FPGA for power sequence */
- /* TMP275A */
- /* TMP275A */
- /* EMC1462 */
-
- tpm@57 {
- compatible = "infineon,slb9645tt";
- reg = <0x57>;
- };
-
- rtc@32 {
- compatible = "epson,rx8900";
- reg = <0x32>;
- };
-
- tmp275@48 {
- compatible = "ti,tmp275";
- reg = <0x48>;
- };
-
- tmp275@49 {
- compatible = "ti,tmp275";
- reg = <0x49>;
- };
-
- /* chip emc1462 use emc1403 driver */
- emc1403@4c {
- compatible = "smsc,emc1403";
- reg = <0x4c>;
- };
-
-};
-
-&i2c12 {
- status = "okay";
-
- /* pca9545 ->
- * SAS BP1
- * SAS BP2
- * NVMe BP
- * M.2 riser
- */
-
- pca9545@70 {
- compatible = "nxp,pca9545";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- bus12_mux247: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
- };
-
- bus12_mux248: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
- };
-
- bus12_mux249: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
- };
-
- bus12_mux250: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- tmp275@48 {
- compatible = "ti,tmp275";
- reg = <0x48>;
- };
- };
-
- };
-
-};
-
-&i2c13 {
- status = "okay";
-
- /* pca9548 ->
- * NVMe BP
- * NVMe HDD17 to 24
- */
-
- pca9548@70 {
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
- bus13_mux251: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- bus13_mux252: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- bus13_mux253: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- bus13_mux254: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
-
- bus13_mux255: i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
- };
-
- bus13_mux256: i2c@5 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <5>;
- };
-
- bus13_mux257: i2c@6 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <6>;
- };
-
- bus13_mux258: i2c@7 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <7>;
- };
- };
-};
-
-&vuart {
- status = "okay";
-};
-
-&gfx {
- status = "okay";
- memory-region = <&gfx_memory>;
-};
-
-&adc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc0_default
- &pinctrl_adc1_default
- &pinctrl_adc2_default
- &pinctrl_adc3_default
- &pinctrl_adc4_default
- &pinctrl_adc5_default
- &pinctrl_adc6_default
- &pinctrl_adc7_default
- &pinctrl_adc8_default
- &pinctrl_adc9_default
- &pinctrl_adc10_default
- &pinctrl_adc11_default
- &pinctrl_adc12_default
- &pinctrl_adc13_default
- &pinctrl_adc14_default
- &pinctrl_adc15_default>;
-};
-
-&wdt1 {
- aspeed,reset-type = "none";
- aspeed,external-signal;
- aspeed,ext-push-pull;
- aspeed,ext-active-high;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdtrst1_default>;
-};
-
-&wdt2 {
- aspeed,alt-boot;
-};
-
-&ibt {
- status = "okay";
-};
-
-&vhub {
- status = "okay";
-};
-
-&video {
- status = "okay";
- memory-region = <&video_engine_memory>;
-};
-
-#include "ibm-power9-dual.dtsi"
-
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
index 7d38d121ec6d..31ff19ef87a0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
@@ -46,31 +46,31 @@
gpio-keys {
compatible = "gpio-keys";
- air-water {
+ event-air-water {
label = "air-water";
gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 6)>;
};
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
- ps0-presence {
+ event-ps0-presence {
label = "ps0-presence";
gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 2)>;
};
- ps1-presence {
+ event-ps1-presence {
label = "ps1-presence";
gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 0)>;
};
- id-button {
+ button-id {
label = "id-button";
gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 1)>;
@@ -81,31 +81,31 @@
compatible = "gpio-keys-polled";
poll-interval = <1000>;
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca9552 9 GPIO_ACTIVE_LOW>;
linux,code = <9>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca9552 10 GPIO_ACTIVE_LOW>;
linux,code = <10>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca9552 11 GPIO_ACTIVE_LOW>;
linux,code = <11>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca9552 12 GPIO_ACTIVE_LOW>;
linux,code = <12>;
};
- fan4-presence {
+ event-fan4-presence {
label = "fan4-presence";
gpios = <&pca9552 13 GPIO_ACTIVE_LOW>;
linux,code = <13>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
index 3d4bdad27c2d..ac0d666ca10e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
@@ -96,7 +96,7 @@
gpio-keys {
compatible = "gpio-keys";
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index cd660c1ff3f5..45631b47a7b3 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -73,7 +73,7 @@
gpio-keys {
compatible = "gpio-keys";
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(P, 5)>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 084f54866f38..893e621ecab1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -87,7 +87,7 @@
gpio-keys {
compatible = "gpio-keys";
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
index 4816486c0c9e..bbf864f84d37 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
@@ -38,37 +38,37 @@
gpio-keys {
compatible = "gpio-keys";
- air-water {
+ event-air-water {
label = "air-water";
gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(B, 5)>;
};
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
- ps0-presence {
+ event-ps0-presence {
label = "ps0-presence";
gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(R, 7)>;
};
- ps1-presence {
+ event-ps1-presence {
label = "ps1-presence";
gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(N, 0)>;
};
- oppanel-presence {
+ event-oppanel-presence {
label = "oppanel-presence";
gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(A, 7)>;
};
- opencapi-riser-presence {
+ event-opencapi-riser-presence {
label = "opencapi-riser-presence";
gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(I, 0)>;
@@ -84,55 +84,55 @@
compatible = "gpio-keys-polled";
poll-interval = <1000>;
- scm0-presence {
+ event-scm0-presence {
label = "scm0-presence";
gpios = <&pca9552 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
- scm1-presence {
+ event-scm1-presence {
label = "scm1-presence";
gpios = <&pca9552 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
- cpu0vrm-presence {
+ event-cpu0vrm-presence {
label = "cpu0vrm-presence";
gpios = <&pca9552 12 GPIO_ACTIVE_LOW>;
linux,code = <12>;
};
- cpu1vrm-presence {
+ event-cpu1vrm-presence {
label = "cpu1vrm-presence";
gpios = <&pca9552 13 GPIO_ACTIVE_LOW>;
linux,code = <13>;
};
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca0 8 GPIO_ACTIVE_LOW>;
linux,code = <8>;
};
- fanboost-presence {
+ event-fanboost-presence {
label = "fanboost-presence";
gpios = <&pca0 9 GPIO_ACTIVE_LOW>;
linux,code = <9>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
index 72b7a6639ed9..3f6010ef2b86 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
@@ -50,13 +50,13 @@
gpio-keys {
compatible = "gpio-keys";
- ps0-presence {
+ event-ps0-presence {
label = "ps0-presence";
gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 3)>;
};
- ps1-presence {
+ event-ps1-presence {
label = "ps1-presence";
gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(E, 5)>;
@@ -65,29 +65,27 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 328ef472c479..8a7fb55ab489 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -63,13 +63,13 @@
gpio-keys {
compatible = "gpio-keys";
- button_checkstop {
+ event-checkstop {
label = "checkstop";
linux,code = <74>;
gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>;
};
- button_identify {
+ event-identify {
label = "identify";
linux,code = <152>;
gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 230f3584bcab..a20a532fc280 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -51,25 +51,25 @@
gpio-keys {
compatible = "gpio-keys";
- air-water {
+ event-air-water {
label = "air-water";
gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(B, 5)>;
};
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
- ps0-presence {
+ event-ps0-presence {
label = "ps0-presence";
gpios = <&gpio ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(P, 7)>;
};
- ps1-presence {
+ event-ps1-presence {
label = "ps1-presence";
gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(N, 0)>;
@@ -85,25 +85,25 @@
compatible = "gpio-keys-polled";
poll-interval = <1000>;
- fan0-presence {
+ event-fan0-presence {
label = "fan0-presence";
gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
- fan1-presence {
+ event-fan1-presence {
label = "fan1-presence";
gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
- fan2-presence {
+ event-fan2-presence {
label = "fan2-presence";
gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
- fan3-presence {
+ event-fan3-presence {
label = "fan3-presence";
gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
index 7ae4ea0d2931..0cb7b20ff3ab 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -58,13 +58,13 @@
gpio-keys {
compatible = "gpio-keys";
- checkstop {
+ event-checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 7)>;
};
- pcie-e2b-present{
+ event-pcie-e2b-present{
label = "pcie-e2b-present";
gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(E, 7)>;
diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
index 61bc74b423cf..a5e64ccc2b3a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
@@ -24,17 +24,17 @@
leds {
compatible = "gpio-leds";
postcode0 {
- label="BMC_UP";
+ label = "BMC_UP";
gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
default-state = "on";
};
postcode1 {
- label="BMC_HB";
+ label = "BMC_HB";
gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
postcode2 {
- label="FAULT";
+ label = "FAULT";
gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
};
// postcode3-7 are GPIOH3-H7
diff --git a/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
new file mode 100644
index 000000000000..259ef3f54c5c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+
+/ {
+ model = "Qualcomm DC-SCM V1 BMC";
+ compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&mdio3 {
+ status = "okay";
+
+ ethphy3: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mac2 {
+ status = "okay";
+
+ /* Bootloader sets up the MAC to insert delay */
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii3_default>;
+};
+
+&mac3 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+
+ use-ncsi;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <133000000>;
+#include "openbmc-flash-layout-64.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <133000000>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bios";
+ spi-max-frequency = <133000000>;
+ };
+};
+
+&gpio0 {
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
+ /*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3",
+ "SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
+ "SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "","","","","","","","",
+ /*AB0-AB7*/ "","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*A0-A7*/ "GPI_1_BMC_1V8","","","","","",
+ "SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
+ /*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
+ "SCMFPGA_SPARE_GPIO5_1V8","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
+ "","TPM2_PIRQ_N","TPM2_RST_N","",
+ /*E0-E7*/ "","","","","","","","";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts
index 69e1bd256271..46cbba6305b8 100644
--- a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts
@@ -65,19 +65,19 @@
compatible = "gpio-leds";
BMC_HEARTBEAT_N {
- label="BMC_HEARTBEAT_N";
+ label = "BMC_HEARTBEAT_N";
gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
BMC_LED_STATUS_AMBER_N {
- label="BMC_LED_STATUS_AMBER_N";
+ label = "BMC_LED_STATUS_AMBER_N";
gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>;
default-state = "off";
};
FM_ID_LED_N {
- label="FM_ID_LED_N";
+ label = "FM_ID_LED_N";
gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
default-state = "off";
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts
index 708ee78e4b83..f6c4549c0ac4 100644
--- a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts
@@ -364,6 +364,7 @@
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
+ aspeed,lpc-interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
diff --git a/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts b/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts
new file mode 100644
index 000000000000..7ab29129d1e4
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright (c) 2022 Ufispace Co., Ltd.
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Ufispace NCPLite BMC";
+ compatible = "ufispace,ncplite-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8 earlycon";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
+ <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ fan-status-int-l {
+ label = "fan-status-int-l";
+ gpios = <&gpio0 ASPEED_GPIO(M, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(M, 2)>;
+ };
+
+ allpwr-good {
+ label = "allpwr-good";
+ gpios = <&gpio0 ASPEED_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
+ linux,code = <ASPEED_GPIO(V, 4)>;
+ };
+
+ psu0-alert-n {
+ label = "psu0-alert-n";
+ gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(V, 1)>;
+ };
+
+ psu1-alert-n {
+ label = "psu1-alert-n";
+ gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(V, 2)>;
+ };
+
+ int-thermal-alert {
+ label = "int-thermal-alert";
+ gpios = <&gpio0 ASPEED_GPIO(P, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(P, 2)>;
+ };
+
+ cpu-caterr-l {
+ label = "cpu-caterr-l";
+ gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(N, 3)>;
+ };
+
+ cpu-thermtrip-l {
+ label = "cpu-thermtrip-l";
+ gpios = <&gpio0 ASPEED_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(V, 5)>;
+ };
+
+ psu0-presence-l {
+ label = "psu0-presence-l";
+ gpios = <&gpio0 ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 6)>;
+ };
+
+ psu1-presence-l {
+ label = "psu1-presence-l";
+ gpios = <&gpio0 ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 7)>;
+ };
+
+ psu0-power-ok {
+ label = "psu0-power-ok";
+ gpios = <&gpio0 ASPEED_GPIO(M, 4) GPIO_ACTIVE_HIGH>;
+ linux,code = <ASPEED_GPIO(M, 4)>;
+ };
+
+ psu1-power-ok {
+ label = "psu1-power-ok";
+ gpios = <&gpio0 ASPEED_GPIO(M, 5) GPIO_ACTIVE_HIGH>;
+ linux,code = <ASPEED_GPIO(M, 5)>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&fan_ioexp 2 GPIO_ACTIVE_LOW>;
+ linux,code = <2>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&fan_ioexp 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&fan_ioexp 10 GPIO_ACTIVE_LOW>;
+ linux,code = <10>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&fan_ioexp 14 GPIO_ACTIVE_LOW>;
+ linux,code = <14>;
+ };
+ };
+};
+
+&mac2 {
+ status = "okay";
+ use-ncsi;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
+ <&syscon ASPEED_CLK_MAC3RCLK>;
+ clock-names = "MACCLK", "RCLK";
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&kcs3 {
+ status = "okay";
+ aspeed,lpc-io-reg = <0xca2>;
+};
+
+&lpc_reset {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&wdt1 {
+ status = "okay";
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&peci0 {
+ status = "okay";
+};
+
+&udc {
+ status = "okay";
+};
+
+&adc0 {
+ vref = <2500>;
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+};
+
+&adc1 {
+ vref = <2500>;
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc10_default &pinctrl_adc11_default
+ &pinctrl_adc12_default &pinctrl_adc13_default
+ &pinctrl_adc14_default &pinctrl_adc15_default>;
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ lm75@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+
+ lm75@49 {
+ compatible = "national,lm75";
+ reg = <0x49>;
+ };
+
+ lm86@4c {
+ compatible = "national,lm86";
+ reg = <0x4c>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ lm75@4f {
+ cpmpatible = "national,lm75";
+ reg = <0x4f>;
+ };
+
+ fan_ioexp: pca9535@20 {
+ compatible = "nxp,pca9535";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","","presence-fan0","",
+ "","","presence-fan1","",
+ "","","presence-fan2","",
+ "","","presence-fan3","";
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ psu@58 {
+ compatible = "pmbus";
+ reg = <0x58>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <1>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ psu@58 {
+ compatible = "pmbus";
+ reg = <0x58>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <1>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+
+ lm75@4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "CPU_PWRGD","","","power-button","host0-ready","","presence-ps0","presence-ps1",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","reset-button","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "power-chassis-control0","power-chassis-control1","","","","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","power-chassis-good","","","";
+};
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index fa8b581c3d6c..530491ae5eb2 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -54,8 +54,7 @@
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0x94
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
@@ -65,34 +64,42 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@3 {
reg = < 3 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@4 {
reg = < 4 >;
compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
spi: spi@1e630000 {
- reg = < 0x1e630000 0x18
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
@@ -102,6 +109,7 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 4147b397c883..04f98d1dbb97 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -55,8 +55,7 @@
ranges;
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
@@ -67,25 +66,27 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x08000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
@@ -95,19 +96,20 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x38000000 0x08000000 >;
+ reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
@@ -117,12 +119,14 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -258,6 +262,14 @@
quality = <100>;
};
+ hace: crypto@1e6e3000 {
+ compatible = "aspeed,ast2500-hace";
+ reg = <0x1e6e3000 0x100>;
+ interrupts = <4>;
+ clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
+ resets = <&syscon ASPEED_RESET_HACE>;
+ };
+
gfx: display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
index e4775bbceecc..7cd4f075e325 100644
--- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
@@ -117,9 +117,9 @@
groups = "FWSPID";
};
- pinctrl_fwqspid_default: fwqspid_default {
- function = "FWSPID";
- groups = "FWQSPID";
+ pinctrl_fwqspi_default: fwqspi_default {
+ function = "FWQSPI";
+ groups = "FWQSPI";
};
pinctrl_fwspiwp_default: fwspiwp_default {
@@ -653,12 +653,12 @@
};
pinctrl_qspi1_default: qspi1_default {
- function = "QSPI1";
+ function = "SPI1";
groups = "QSPI1";
};
pinctrl_qspi2_default: qspi2_default {
- function = "QSPI2";
+ function = "SPI2";
groups = "QSPI2";
};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 3d5ce9da42c3..172dd748d807 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -36,6 +36,10 @@
serial4 = &uart5;
serial5 = &vuart1;
serial6 = &vuart2;
+ mdio0 = &mdio0;
+ mdio1 = &mdio1;
+ mdio2 = &mdio2;
+ mdio3 = &mdio3;
};
@@ -94,9 +98,13 @@
<0x40466000 0x2000>;
};
+ ahbc: bus@1e600000 {
+ compatible = "aspeed,ast2600-ahbc", "syscon";
+ reg = <0x1e600000 0x100>;
+ };
+
fmc: spi@1e620000 {
- reg = < 0x1e620000 0xc4
- 0x20000000 0x10000000 >;
+ reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
@@ -107,25 +115,27 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi1: spi@1e630000 {
- reg = < 0x1e630000 0xc4
- 0x30000000 0x10000000 >;
+ reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
@@ -135,19 +145,20 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi2: spi@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x50000000 0x10000000 >;
+ reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-spi";
@@ -157,18 +168,21 @@
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <2>;
status = "disabled";
};
};
@@ -181,6 +195,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio1_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mdio1: mdio@1e650008 {
@@ -191,6 +206,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio2_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mdio2: mdio@1e650010 {
@@ -201,6 +217,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio3_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mdio3: mdio@1e650018 {
@@ -211,6 +228,7 @@
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio4_default>;
+ resets = <&syscon ASPEED_RESET_MII>;
};
mac0: ftgmac@1e660000 {
@@ -298,12 +316,30 @@
status = "disabled";
};
+ udc: usb@1e6a2000 {
+ compatible = "aspeed,ast2600-udc";
+ reg = <0x1e6a2000 0x300>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2bd_default>;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ hace: crypto@1e6d0000 {
+ compatible = "aspeed,ast2600-hace";
+ reg = <0x1e6d0000 0x200>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
+ resets = <&syscon ASPEED_RESET_HACE>;
+ };
+
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1000>;
@@ -351,6 +387,17 @@
quality = <100>;
};
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2600-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
+ resets = <&syscon ASPEED_RESET_GRAPHICS>;
+ syscon = <&syscon>;
+ status = "disabled";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
xdma: xdma@1e6e7000 {
compatible = "aspeed,ast2600-xdma";
reg = <0x1e6e7000 0x100>;
@@ -389,6 +436,24 @@
reg = <0x1e6f2000 0x1000>;
};
+ acry: crypto@1e6fa000 {
+ compatible = "aspeed,ast2600-acry";
+ reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
+ aspeed,ahbc = <&ahbc>;
+ };
+
+ video: video@1e700000 {
+ compatible = "aspeed,ast2600-video-engine";
+ reg = <0x1e700000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
+ <&syscon ASPEED_CLK_GATE_ECLK>;
+ clock-names = "vclk", "eclk";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
gpio0: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
@@ -716,6 +781,62 @@
status = "disabled";
};
+ uart6: serial@1e790000 {
+ compatible = "ns16550a";
+ reg = <0x1e790000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6_default>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@1e790100 {
+ compatible = "ns16550a";
+ reg = <0x1e790100 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7_default>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@1e790200 {
+ compatible = "ns16550a";
+ reg = <0x1e790200 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8_default>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@1e790300 {
+ compatible = "ns16550a";
+ reg = <0x1e790300 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart9_default>;
+
+ status = "disabled";
+ };
+
i2c: bus@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -742,6 +863,15 @@
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
status = "disabled";
};
+
+ udma: dma-controller@1e79e000 {
+ compatible = "aspeed,ast2600-udma";
+ reg = <0x1e79e000 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <28>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi
index 051de5bec345..31590d3186a2 100644
--- a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi
+++ b/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi
@@ -25,7 +25,7 @@
* full-duplex SPI transactions are not supported by ASPEED SPI
* Controllers.
*/
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
status = "okay";
compatible = "spi-gpio";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
index c1c8650dafce..3542ad8a243e 100644
--- a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
+++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
@@ -44,7 +44,7 @@
status = "okay";
/* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */
- spi-flash@0 {
+ flash@0 {
compatible = "mxicy,mx25u4035", "jedec,spi-nor";
spi-max-frequency = <33000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
index 7edf057047f8..9dfd5de808d1 100644
--- a/arch/arm/boot/dts/at91-foxg20.dts
+++ b/arch/arm/boot/dts/at91-foxg20.dts
@@ -155,10 +155,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- btn {
+ button {
label = "Button";
gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts
index 5a81cab5fc3a..551300fd7746 100644
--- a/arch/arm/boot/dts/at91-gatwick.dts
+++ b/arch/arm/boot/dts/at91-gatwick.dts
@@ -13,7 +13,7 @@
model = "Laird Workgroup Bridge 50N - Project Gatwick";
compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -31,37 +31,37 @@
leds {
compatible = "gpio-leds";
- ethernet {
+ led-ethernet {
label = "gatwick:yellow:ethernet";
gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- wifi {
+ led-wifi {
label = "gatwick:green:wifi";
gpios = <&pioA 28 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- ble {
+ led-ble {
label = "gatwick:blue:ble";
gpios = <&pioA 22 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- lora {
+ led-lora {
label = "gatwick:orange:lora";
gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- blank {
+ led-blank {
label = "gatwick:green:blank";
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- user {
+ led-user {
label = "gatwick:yellow:user";
gpios = <&pioA 12 GPIO_ACTIVE_LOW>;
default-state = "off";
diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts
index 3b8812fcd854..307663b4eec2 100644
--- a/arch/arm/boot/dts/at91-kizbox.dts
+++ b/arch/arm/boot/dts/at91-kizbox.dts
@@ -28,19 +28,17 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- reset {
+ button-reset {
label = "PB_RST";
gpios = <&pioB 30 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
wakeup-source;
};
- user {
+ button-user {
label = "PB_USER";
gpios = <&pioB 31 GPIO_ACTIVE_HIGH>;
linux,code = <0x101>;
diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi
index c08834ddf07b..e5e21dff882f 100644
--- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi
+++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi
@@ -31,26 +31,24 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- prog {
+ button-prog {
label = "PB_PROG";
gpios = <&pioE 27 GPIO_ACTIVE_LOW>;
linux,code = <0x102>;
wakeup-source;
};
- reset {
+ button-reset {
label = "PB_RST";
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
linux,code = <0x100>;
wakeup-source;
};
- user {
+ button-user {
label = "PB_USER";
gpios = <&pioE 31 GPIO_ACTIVE_HIGH>;
linux,code = <0x101>;
diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts
index 2799b2a1f4d2..7075df6549e9 100644
--- a/arch/arm/boot/dts/at91-kizbox3-hs.dts
+++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts
@@ -55,7 +55,7 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default" , "default", "default",
"default", "default" ;
@@ -68,35 +68,35 @@
&pinctrl_pio_zbe_rst>;
pinctrl-4 = <&pinctrl_pio_input>;
- SW1 {
+ switch-1 {
label = "SW1";
gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>;
linux,code = <0x101>;
wakeup-source;
};
- SW2 {
+ switch-2 {
label = "SW2";
gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>;
linux,code = <0x102>;
wakeup-source;
};
- SW3 {
+ switch-3 {
label = "SW3";
gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
wakeup-source;
};
- SW7 {
+ switch-7 {
label = "SW7";
gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>;
linux,code = <0x107>;
wakeup-source;
};
- SW8 {
+ switch-8 {
label = "SW8";
gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>;
linux,code = <0x108>;
@@ -186,7 +186,7 @@
&pioA {
pinctrl_key_gpio_default: key_gpio_default {
- pinmux= <PIN_PA22__GPIO>,
+ pinmux = <PIN_PA22__GPIO>,
<PIN_PA24__GPIO>,
<PIN_PA26__GPIO>,
<PIN_PA29__GPIO>,
diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi
index 9c622892c692..42640fe6b6d0 100644
--- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi
+++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi
@@ -36,17 +36,15 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- prog {
+ key-prog {
label = "PB_PROG";
gpios = <&pioC 17 GPIO_ACTIVE_LOW>;
linux,code = <0x102>;
wakeup-source;
};
- reset {
+ key-reset {
label = "PB_RST";
gpios = <&pioC 16 GPIO_ACTIVE_LOW>;
linux,code = <0x100>;
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index 4f123477e631..f71377c9b757 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -18,7 +18,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "Wakeup";
linux,code = <10>;
wakeup-source;
diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/at91-q5xr5.dts
index 47a00062f01f..9cf60b6f695c 100644
--- a/arch/arm/boot/dts/at91-q5xr5.dts
+++ b/arch/arm/boot/dts/at91-q5xr5.dts
@@ -125,7 +125,7 @@
cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts
index 969d990767fc..9d26f9996348 100644
--- a/arch/arm/boot/dts/at91-qil_a9260.dts
+++ b/arch/arm/boot/dts/at91-qil_a9260.dts
@@ -198,10 +198,8 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- user_pb {
+ button-user {
label = "user_pb";
gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
linux,code = <28>;
diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts
index 1e2a28c2f365..2fb51b9aca2a 100644
--- a/arch/arm/boot/dts/at91-sam9_l9260.dts
+++ b/arch/arm/boot/dts/at91-sam9_l9260.dts
@@ -101,7 +101,7 @@
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
- nand-on-flash-bbt = <1>;
+ nand-on-flash-bbt;
status = "okay";
};
diff --git a/arch/arm/boot/dts/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/at91-sam9x60_curiosity.dts
new file mode 100644
index 000000000000..cb86a3a170ce
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60_curiosity.dts
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Curiosity board
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Durai Manickam KR <durai.manickamkr@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Microchip SAM9X60 Curiosity";
+ compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c6;
+ serial2 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@20000000 {
+ reg = <0x20000000 0x8000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+ button-user {
+ label = "PB_USER";
+ gpios = <&pioA 29 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PROG1>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-red {
+ label = "red";
+ gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-green {
+ label = "green";
+ gpios = <&pioD 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-blue {
+ label = "blue";
+ gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+
+ vdd_1v8: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "VDD_1V8";
+ };
+
+ vdd_1v15: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <1150000>;
+ regulator-min-microvolt = <1150000>;
+ regulator-name = "VDD_1V15";
+ };
+
+ vdd1_3v3: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VDD1_3V3";
+ };
+};
+
+&adc {
+ vddana-supply = <&vdd1_3v3>;
+ vref-supply = <&vdd1_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_rx_tx>;
+ status = "okay";
+};
+
+&dbgu {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_lsb>;
+ status = "okay";
+
+ nand_controller: nand-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "u-boot";
+ reg = <0x40000 0xc0000>;
+ };
+
+ ubootenvred@100000 {
+ label = "U-Boot Env Redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ ubootenv@140000 {
+ label = "U-Boot Env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c0: i2c@600 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+ };
+};
+
+&flx6 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c6: i2c@600 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx6_default>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "disabled";
+ };
+};
+
+&flx7 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart7: serial@200 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx7_default>;
+ status = "okay";
+ };
+};
+
+&macb0 {
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ status = "okay";
+
+ ethernet-phy@0 {
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ adc {
+ pinctrl_adc_default: adc-default {
+ atmel,pins = <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_adtrg_default: adtrg-default {
+ atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ can0 {
+ pinctrl_can0_rx_tx: can0-rx-tx {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0 */
+ AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX0 */
+ AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1-rx-tx {
+ atmel,pins =
+ <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1 */
+ AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX1 */
+ AT91_PIOB 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
+ };
+ };
+
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ ebi {
+ pinctrl_ebi_data_lsb: ebi-data-lsb {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_ebi_addr_nand: ebi-addr-nand {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
+ flexcom {
+ pinctrl_flx0_default: flx0-twi {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_flx6_default: flx6-twi {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_flx7_default: flx7-usart {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
+ AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+ };
+ };
+
+ gpio-keys {
+ pinctrl_key_gpio_default: pinctrl-key-gpio {
+ atmel,pins = <AT91_PIOA 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ leds {
+ pinctrl_gpio_leds: gpio-leds {
+ atmel,pins = <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ macb0 {
+ pinctrl_macb0_rmii: macb0-rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+ };
+
+ nand {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ pwm0 {
+ pinctrl_pwm0_0: pwm0-0 {
+ atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_1: pwm0-1 {
+ atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_2: pwm0-2 {
+ atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ sdmmc0 {
+ pinctrl_sdmmc0_default: sdmmc0 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA17 CK periph A with pullup */
+ AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD periph A with pullup */
+ AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA15 DAT0 periph A */
+ AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA18 DAT1 periph A with pullup */
+ AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA19 DAT2 periph A with pullup */
+ AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA20 DAT3 periph A with pullup */
+ };
+
+ pinctrl_sdmmc0_cd: sdmmc0-cd {
+ atmel,pins =
+ <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ sdmmc1 {
+ pinctrl_sdmmc1_default: sdmmc1 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
+ AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
+ AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
+ AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
+ AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
+ AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
+ };
+ };
+
+ usb0 {
+ pinctrl_usba_vbus: usba-vbus {
+ atmel,pins = <AT91_PIOA 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ usb1 {
+ pinctrl_usb_default: usb-default {
+ atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+}; /* pinctrl */
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>;
+ cd-gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ disable-wp;
+ status = "okay";
+};
+
+&shutdown_controller {
+ debounce-delay-us = <976>;
+ status = "okay";
+
+ input@0 {
+ reg = <0>;
+ };
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&usb0 {
+ atmel,vbus-gpio = <&pioA 27 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioD 18 GPIO_ACTIVE_HIGH
+ &pioD 15 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
index 7719ea3d4933..5cd593028aff 100644
--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -16,8 +16,8 @@
aliases {
i2c0 = &i2c0;
- i2c1 = &i2c1;
- serial1 = &uart1;
+ i2c1 = &i2c6;
+ serial1 = &uart5;
};
chosen {
@@ -34,58 +34,15 @@
};
};
- regulators: regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd_1v8: fixed-regulator-vdd_1v8@0 {
- compatible = "regulator-fixed";
- regulator-name = "VDD_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- status = "okay";
- };
-
- vdd_1v15: fixed-regulator-vdd_1v15@1 {
- compatible = "regulator-fixed";
- regulator-name = "VDD_1V15";
- regulator-min-microvolt = <1150000>;
- regulator-max-microvolt = <1150000>;
- regulator-always-on;
- status = "okay";
- };
-
- vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
- compatible = "regulator-fixed";
- regulator-name = "VDD1_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- status = "okay";
- };
-
- vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
- compatible = "regulator-fixed";
- regulator-name = "VDD2_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- status = "okay";
- };
- };
-
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- status = "okay";
- sw1 {
+ button-1 {
label = "SW1";
gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
- linux,code=<KEY_PROG1>;
+ linux,code = <KEY_PROG1>;
wakeup-source;
};
};
@@ -112,6 +69,38 @@
linux,default-trigger = "heartbeat";
};
};
+
+ vdd_1v8: fixed-regulator-vdd_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vdd_1v15: fixed-regulator-vdd_1v15 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V15";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ };
+
+ vdd1_3v3: fixed-regulator-vdd1_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD1_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd2_3v3: regulator-fixed-vdd2_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD2_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
&adc {
@@ -218,25 +207,20 @@
status = "okay";
i2c0: i2c@600 {
- compatible = "microchip,sam9x60-i2c";
- reg = <0x600 0x200>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
- atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
eeprom@53 {
- compatible = "atmel,24c32";
+ compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
- size = <128>;
status = "okay";
};
};
@@ -246,17 +230,10 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "disabled";
- spi0: spi@400 {
- compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
- clock-names = "spi_clk";
+ spi4: spi@400 {
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
- atmel,fifo-size = <16>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
};
@@ -265,23 +242,9 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
- uart1: serial@200 {
- compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
- dmas = <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(10))>,
- <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(11))>;
- dma-names = "tx", "rx";
- clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
- clock-names = "usart";
- pinctrl-0 = <&pinctrl_flx5_default>;
+ uart5: serial@200 {
pinctrl-names = "default";
- atmel,use-dma-rx;
- atmel,use-dma-tx;
+ pinctrl-0 = <&pinctrl_flx5_default>;
status = "okay";
};
};
@@ -290,16 +253,12 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
- i2c1: i2c@600 {
- compatible = "microchip,sam9x60-i2c";
- reg = <0x600 0x200>;
- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+ i2c6: i2c@600 {
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx6_default>;
- atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
@@ -450,7 +409,7 @@
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
- pinctrl_flx5_default: flx_uart {
+ pinctrl_flx5_default: flx5_uart {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
@@ -619,7 +578,8 @@
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <80000000>;
+ spi-max-frequency = <104000000>;
+ spi-cs-setup-ns = <7>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index a4623cc67cc1..95ecb7d040a8 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -15,7 +15,7 @@
compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
aliases {
- i2c0 = &i2c0;
+ i2c0 = &i2c0;
};
clocks {
@@ -43,7 +43,8 @@
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <80000000>;
+ spi-max-frequency = <104000000>;
+ spi-cs-setup-ns = <7>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
@@ -83,6 +84,8 @@
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
phy-mode = "rmii";
ethernet-phy@7 {
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index 08f0d4b995ff..52ddd0571f1c 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -21,8 +21,8 @@
serial0 = &uart1; /* DBGU */
serial1 = &uart4; /* mikro BUS 1 */
serial2 = &uart2; /* mikro BUS 2 */
- i2c1 = &i2c1;
- i2c2 = &i2c3;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
};
chosen {
@@ -478,13 +478,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- pb4 {
+ button {
label = "USER";
gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -498,17 +498,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay"; /* Conflict with pwm0. */
- red {
+ led-red {
label = "red";
gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-green {
label = "green";
gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
};
- blue {
+ led-blue {
label = "blue";
gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
index 21c86171e462..4617805c7748 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -76,8 +76,8 @@
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -95,8 +95,8 @@
vddio_ddr: VDD_DDR {
regulator-name = "VDD_DDR";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1850000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -118,8 +118,8 @@
vdd_core: VDD_CORE {
regulator-name = "VDD_CORE";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1850000>;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -160,8 +160,8 @@
LDO1 {
regulator-name = "LDO1";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-standby {
@@ -175,9 +175,8 @@
LDO2 {
regulator-name = "LDO2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
- regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
regulator-state-standby {
regulator-on-in-suspend;
@@ -194,6 +193,8 @@
&macb0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
phy-mode = "rmii";
ethernet-phy@0 {
@@ -214,12 +215,13 @@
pinctrl-0 = <&pinctrl_qspi1_default>;
status = "disabled";
- qspi1_flash: spi_flash@0 {
+ qspi1_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <80000000>;
+ spi-max-frequency = <104000000>;
+ spi-cs-setup-ns = <7>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
index c145c4e5ef58..e055b9e2fe34 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
@@ -19,21 +19,20 @@
serial1 = &uart6; /* BT */
serial2 = &uart5; /* mikro BUS 2 */
serial3 = &uart3; /* mikro BUS 1 */
- i2c1 = &i2c1;
+ i2c1 = &i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- status = "okay";
- sw4 {
+ button-1 {
label = "USER BUTTON";
gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -47,17 +46,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
- red {
+ led-red {
label = "red";
gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-green {
label = "green";
gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>;
};
- blue {
+ led-blue {
label = "blue";
gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -191,7 +190,7 @@
&qspi1 {
status = "okay";
- qspi1_flash: spi_flash@0 {
+ qspi1_flash: flash@0 {
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
index 806eb1d911d7..999adeca6f33 100644
--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -24,8 +24,8 @@
serial1 = &uart1; /* mikro BUS 3 */
serial3 = &uart3; /* mikro BUS 2 */
serial5 = &uart7; /* flx2 */
- i2c0 = &i2c0;
- i2c1 = &i2c1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
};
chosen {
@@ -42,14 +42,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- status = "okay";
- sw4 {
+ button-1 {
label = "USER_PB1";
gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -63,17 +62,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay"; /* conflict with pwm0 */
- red {
+ led-red {
label = "red";
gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-green {
label = "green";
gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
};
- blue {
+ led-blue {
label = "blue";
gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -197,8 +196,8 @@
regulators {
vdd_io_reg: VDD_IO {
regulator-name = "VDD_IO";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -216,8 +215,8 @@
VDD_DDR {
regulator-name = "VDD_DDR";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1850000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -235,8 +234,8 @@
VDD_CORE {
regulator-name = "VDD_CORE";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1850000>;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -258,7 +257,6 @@
regulator-max-microvolt = <1850000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
- regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
@@ -273,8 +271,8 @@
LDO1 {
regulator-name = "LDO1";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
regulator-always-on;
regulator-state-standby {
@@ -288,8 +286,8 @@
LDO2 {
regulator-name = "LDO2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-standby {
@@ -329,21 +327,21 @@
status = "okay";
eeprom@50 {
- compatible = "atmel,24c32";
+ compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
status = "okay";
};
eeprom@52 {
- compatible = "atmel,24c32";
+ compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
status = "disabled";
};
eeprom@53 {
- compatible = "atmel,24c32";
+ compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
status = "disabled";
@@ -671,7 +669,8 @@
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <80000000>;
+ spi-max-frequency = <104000000>;
+ spi-cs-setup-ns = <7>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index 8ed58af01391..bf1c9ca72a9f 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -20,9 +20,9 @@
aliases {
serial0 = &uart0; /* DBGU */
- i2c0 = &i2c0; /* mikroBUS 1 */
- i2c1 = &i2c1; /* XPRO EXT1 */
- i2c2 = &i2c2;
+ i2c0 = &i2c0; /* mikroBUS 1 */
+ i2c1 = &i2c1; /* XPRO EXT1 */
+ i2c2 = &i2c2;
};
chosen {
@@ -139,6 +139,8 @@
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
phy-mode = "rmii";
status = "okay";
@@ -394,13 +396,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- bp1 {
+ button-1 {
label = "PB_USER";
gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -414,17 +416,17 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
- red {
+ led-red {
label = "red";
gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-green {
label = "green";
gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
};
- blue {
+ led-blue {
label = "blue";
gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 9bf2ec0ba3e2..2d53c47d7cc8 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -137,7 +137,7 @@
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "atmel,at25df321a";
reg = <0>;
spi-max-frequency = <50000000>;
@@ -147,6 +147,8 @@
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
phy-mode = "rmii";
status = "okay";
@@ -205,10 +207,10 @@
regulator-state-mem {
regulator-on-in-suspend;
- regulator-suspend-min-microvolt=<1400000>;
- regulator-suspend-max-microvolt=<1400000>;
+ regulator-suspend-min-microvolt = <1400000>;
+ regulator-suspend-max-microvolt = <1400000>;
regulator-changeable-in-suspend;
- regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>;
+ regulator-mode = <ACT8945A_REGULATOR_MODE_LOWPOWER>;
};
};
@@ -703,13 +705,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- bp1 {
+ button {
label = "PB_USER";
gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -723,18 +725,18 @@
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay"; /* conflict with pwm0 */
- red {
+ led-red {
label = "red";
gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>;
};
- green {
+ led-green {
label = "green";
gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>;
};
- blue {
+ led-blue {
label = "blue";
gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/at91-sama5d3_eds.dts b/arch/arm/boot/dts/at91-sama5d3_eds.dts
new file mode 100644
index 000000000000..c287b03d768b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d3_eds.dts
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet
+ * Development System board.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Jerry Ray <jerry.ray@microchip.com>
+ */
+/dts-v1/;
+#include "sama5d36.dtsi"
+
+/ {
+ model = "SAMA5D3 Ethernet Development System";
+ compatible = "microchip,sama5d3-eds", "atmel,sama5d36",
+ "atmel,sama5d3", "atmel,sama5";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio>;
+
+ button-3 {
+ label = "PB_USER";
+ gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
+ linux,code = <0x104>;
+ wakeup-source;
+ };
+ };
+
+ memory@20000000 {
+ reg = <0x20000000 0x10000000>;
+ };
+
+ vcc_3v3_reg: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vcc_2v5_reg: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ vin-supply = <&vcc_3v3_reg>;
+ };
+
+ vcc_1v8_reg: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&vcc_3v3_reg>;
+ };
+
+ vcc_1v2_reg: regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vcc_mmc0_reg: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc0-card-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>;
+ gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&ebi {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenvred@100000 {
+ label = "bootloader env redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "bootloader env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&pinctrl_i2c0_pu>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-0 = <&pinctrl_i2c2_pu>;
+ status = "okay";
+};
+
+&main_xtal {
+ clock-frequency = <12000000>;
+};
+
+&mmc0 {
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3
+ &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
+ vmmc-supply = <&vcc_mmc0_reg>;
+ vqmmc-supply = <&vcc_3v3_reg>;
+ status = "okay";
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ board {
+ pinctrl_i2c0_pu: i2c0-pu {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_i2c2_pu: i2c2-pu {
+ atmel,pins =
+ <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_key_gpio: key-gpio-0 {
+ atmel,pins =
+ <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+
+ pinctrl_mmc0_cd: mmc0-cd {
+ atmel,pins =
+ <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+
+ /* Reserved for reset signal to the RGMII connector. */
+ pinctrl_rgmii_rstn: rgmii-rstn {
+ atmel,pins =
+ <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+
+ /* Reserved for an interrupt line from the RMII and RGMII connectors. */
+ pinctrl_spi_irqn: spi-irqn {
+ atmel,pins =
+ <AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+ };
+
+ pinctrl_spi0_cs: spi0-cs-default {
+ atmel,pins =
+ <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi1_cs: spi1-cs-default {
+ atmel,pins = <AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOC 28 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usba_vbus: usba-vbus {
+ atmel,pins =
+ <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+ };
+
+ pinctrl_usb_default: usb-default {
+ atmel,pins =
+ <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+
+ /* Reserved for VBUS fault interrupt. */
+ pinctrl_vbusfault_irqn: vbusfault-irqn {
+ atmel,pins =
+ <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+ };
+
+ pinctrl_vcc_mmc0_reg_gpio: vcc-mmc0-reg-gpio-default {
+ atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+};
+
+&slow_xtal {
+ clock-frequency = <32768>;
+};
+
+&spi0 {
+ pinctrl-names = "default", "cs";
+ pinctrl-1 = <&pinctrl_spi0_cs>;
+ cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default", "cs";
+ pinctrl-1 = <&pinctrl_spi1_cs>;
+ cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>;
+ status = "okay";
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&usb0 { /* USB Device port with VBUS detection. */
+ atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+};
+
+&usb1 { /* 3-port Host. First port is unused. */
+ atmel,vbus-gpio = <0
+ &pioE 3 GPIO_ACTIVE_HIGH
+ &pioE 4 GPIO_ACTIVE_HIGH
+ >;
+ num-ports = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts
index 443e8b022897..14af1fd6d247 100644
--- a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts
@@ -120,26 +120,31 @@
port@0 {
reg = <0>;
label = "lan1";
+ phy-mode = "internal";
};
port@1 {
reg = <1>;
label = "lan2";
+ phy-mode = "internal";
};
port@2 {
reg = <2>;
label = "lan3";
+ phy-mode = "internal";
};
port@3 {
reg = <3>;
label = "lan4";
+ phy-mode = "internal";
};
port@4 {
reg = <4>;
label = "lan5";
+ phy-mode = "internal";
};
port@5 {
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index d72c042f2850..820033727088 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -57,8 +57,8 @@
};
spi0: spi@f0004000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi0_cs>;
+ pinctrl-names = "default", "cs";
+ pinctrl-1 = <&pinctrl_spi0_cs>;
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay";
};
@@ -171,8 +171,8 @@
};
spi1: spi@f8008000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1_cs>;
+ pinctrl-names = "default", "cs";
+ pinctrl-1 = <&pinctrl_spi1_cs>;
cs-gpios = <&pioC 25 0>;
status = "okay";
};
@@ -372,13 +372,13 @@
regulator-always-on;
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
- bp3 {
+ button {
label = "PB_USER";
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -392,13 +392,13 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
status = "okay";
- d2 {
+ led-d2 {
label = "d2";
gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */
linux,default-trigger = "heartbeat";
};
- d3 {
+ led-d3 {
label = "d3"; /* Conflict with EBI CS0, USART2 CTS. */
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
index 710cb72bda5a..fd1086f52b40 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
@@ -49,7 +49,7 @@
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
index 4d7cee569ff2..8adf567f2f0f 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
@@ -115,19 +115,19 @@
compatible = "gpio-leds";
status = "okay";
- user1 {
+ led-user1 {
label = "user1";
gpios = <&pioD 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- user2 {
+ led-user2 {
label = "user2";
gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- user3 {
+ led-user3 {
label = "user3";
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
index d241c24f0d83..95d701d13fef 100644
--- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -81,8 +81,8 @@
};
spi1: spi@fc018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi0_cs>;
+ pinctrl-names = "default", "cs";
+ pinctrl-1 = <&pinctrl_spi1_cs>;
cs-gpios = <&pioB 21 0>;
status = "okay";
};
@@ -140,7 +140,7 @@
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
- pinctrl_spi0_cs: spi0_cs_default {
+ pinctrl_spi1_cs: spi1_cs_default {
atmel,pins =
<AT91_PIOB 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
@@ -242,13 +242,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
- pb_user1 {
+ button {
label = "pb_user1";
gpios = <&pioE 8 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_PROG1>;
@@ -262,13 +262,13 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
status = "okay";
- d8 {
+ led-d8 {
label = "d8";
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- d10 {
+ led-d10 {
label = "d10";
gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index fe432b6b7e95..20ac775059ca 100644
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -65,7 +65,7 @@
spi0: spi@f8010000 {
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
@@ -269,13 +269,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
- pb_user1 {
+ button {
label = "pb_user1";
gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
@@ -287,18 +287,18 @@
compatible = "gpio-leds";
status = "okay";
- d8 {
+ led-d8 {
label = "d8";
/* PE28, conflicts with usart4 rts pin */
gpios = <&pioE 28 GPIO_ACTIVE_LOW>;
};
- d9 {
+ led-d9 {
label = "d9";
gpios = <&pioE 9 GPIO_ACTIVE_HIGH>;
};
- d10 {
+ led-d10 {
label = "d10";
gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 08685a10eda1..aa5cc0e98bba 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -14,6 +14,7 @@
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/sound/microchip,pdmc.h>
/ {
model = "Microchip SAMA7G5-EK";
@@ -44,13 +45,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- bp1 {
+ button {
label = "PB_USER";
gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -243,8 +244,8 @@
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -263,8 +264,8 @@
vddioddr: VDD_DDR {
regulator-name = "VDD_DDR";
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1450000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -284,8 +285,8 @@
vddcore: VDD_CORE {
regulator-name = "VDD_CORE";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1850000>;
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -305,7 +306,7 @@
vddcpu: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1850000>;
+ regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-ramp-delay = <3125>;
@@ -325,8 +326,8 @@
vldo1: LDO1 {
regulator-name = "LDO1";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-standby {
@@ -456,7 +457,7 @@
&pinctrl_gmac1_mdio_default
&pinctrl_gmac1_phy_irq>;
phy-mode = "rmii";
- status = "okay";
+ status = "okay"; /* Conflict with pdmc0. */
ethernet-phy@0 {
reg = <0x0>;
@@ -470,6 +471,17 @@
pinctrl-0 = <&pinctrl_i2s0_default>;
};
+&pdmc0 {
+ #sound-dai-cells = <0>;
+ microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */
+ <MCHP_PDMC_DS1 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 2 */
+ <MCHP_PDMC_DS0 MCHP_PDMC_CLK_POSITIVE>, /* MIC 3 */
+ <MCHP_PDMC_DS1 MCHP_PDMC_CLK_POSITIVE>; /* MIC 4 */
+ status = "disabled"; /* Conflict with gmac1. */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pdmc0_default>;
+};
+
&pioA {
pinctrl_can0_default: can0_default {
@@ -495,7 +507,7 @@
pinctrl_flx3_default: flx3_default {
pinmux = <PIN_PD16__FLEXCOM3_IO0>,
<PIN_PD17__FLEXCOM3_IO1>;
- bias-disable;
+ bias-pull-up;
};
pinctrl_flx4_default: flx4_default {
@@ -639,6 +651,13 @@
bias-disable;
};
+ pinctrl_pdmc0_default: pdmc0_default {
+ pinmux = <PIN_PD23__PDMC0_DS0>,
+ <PIN_PD24__PDMC0_DS1>,
+ <PIN_PD22__PDMC0_CLK>;
+ bias_disable;
+ };
+
pinctrl_qspi: qspi {
pinmux = <PIN_PB12__QSPI0_IO0>,
<PIN_PB11__QSPI0_IO1>,
@@ -655,7 +674,7 @@
<PIN_PB21__QSPI0_INT>;
bias-disable;
slew-rate = <0>;
- atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
+ atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
};
pinctrl_sdmmc0_default: sdmmc0_default {
@@ -745,8 +764,9 @@
&sdmmc0 {
bus-width = <8>;
non-removable;
- no-1-8-v;
sdhci-caps-mask = <0x0 0x00200000>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vldo1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
@@ -756,6 +776,8 @@
bus-width = <4>;
no-1-8-v;
sdhci-caps-mask = <0x0 0x00200000>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay";
diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
index 7e5c598e7e68..b99a4fb44a36 100644
--- a/arch/arm/boot/dts/at91-tse850-3.dts
+++ b/arch/arm/boot/dts/at91-tse850-3.dts
@@ -106,35 +106,35 @@
leds {
compatible = "gpio-leds";
- ch1-red {
+ led-ch1-red {
label = "ch-1:red";
gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
};
- ch1-green {
+ led-ch1-green {
label = "ch-1:green";
gpios = <&pioA 22 GPIO_ACTIVE_LOW>;
};
- ch2-red {
+ led-ch2-red {
label = "ch-2:red";
gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
};
- ch2-green {
+ led-ch2-green {
label = "ch-2:green";
gpios = <&pioA 20 GPIO_ACTIVE_LOW>;
};
- data-red {
+ led-data-red {
label = "data:red";
gpios = <&pioA 19 GPIO_ACTIVE_LOW>;
};
- data-green {
+ led-data-green {
label = "data:green";
gpios = <&pioA 18 GPIO_ACTIVE_LOW>;
};
- alarm-red {
+ led-alarm-red {
label = "alarm:red";
gpios = <&pioA 17 GPIO_ACTIVE_LOW>;
};
- alarm-green {
+ led-alarm-green {
label = "alarm:green";
gpios = <&pioA 16 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts
index a51a3372afa1..ebeaa6ab500e 100644
--- a/arch/arm/boot/dts/at91-vinco.dts
+++ b/arch/arm/boot/dts/at91-vinco.dts
@@ -59,7 +59,7 @@
spi0: spi@f8010000 {
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "n25q32b", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts
index 54d130c92185..ef73f727f7bd 100644
--- a/arch/arm/boot/dts/at91-wb45n.dts
+++ b/arch/arm/boot/dts/at91-wb45n.dts
@@ -12,13 +12,10 @@
model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9";
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- irqbtn@18 {
- reg = <18>;
+ button {
label = "IRQBTN";
linux,code = <99>;
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts
index 89f0f717f7ed..ec2becf6133b 100644
--- a/arch/arm/boot/dts/at91-wb50n.dts
+++ b/arch/arm/boot/dts/at91-wb50n.dts
@@ -13,21 +13,17 @@
model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- btn0@10 {
- reg = <10>;
+ button-0 {
label = "BTNESC";
linux,code = <1>; /* ESC button */
gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
wakeup-source;
};
- irqbtn@31 {
- reg = <31>;
+ button-1 {
label = "IRQBTN";
linux,code = <99>; /* SysReq button */
gpios = <&pioE 31 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index d1181ead18e5..6f9004ebf424 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -596,6 +597,7 @@
dbgu: serial@fffff200 {
compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
reg = <0xfffff200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@@ -607,6 +609,7 @@
usart0: serial@fffc0000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffc0000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -620,6 +623,7 @@
usart1: serial@fffc4000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffc4000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -633,6 +637,7 @@
usart2: serial@fffc8000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffc8000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -646,6 +651,7 @@
usart3: serial@fffcc000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffcc000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -660,7 +666,7 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffb0000 0x4000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>;
clock-names = "pclk", "hclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index e1ef4e44e663..4624a6f076f8 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -73,7 +73,7 @@
spi0: spi@fffe0000 {
status = "okay";
cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
- mtd_dataflash@0 {
+ flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <15000000>;
reg = <0>;
@@ -94,7 +94,7 @@
status = "okay";
};
- nor_flash@10000000 {
+ flash@10000000 {
compatible = "cfi-flash";
reg = <0x10000000 0x800000>;
linux,mtd-name = "physmap-flash.0";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 7368347c9357..789fe356dbf6 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -123,7 +124,7 @@
clock-names = "slow_xtal", "main_xtal";
};
- rstc@fffffd00 {
+ reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
@@ -532,6 +533,7 @@
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@@ -543,6 +545,7 @@
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -556,6 +559,7 @@
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -569,6 +573,7 @@
usart2: serial@fffb8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -582,6 +587,7 @@
usart3: serial@fffd0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd0000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -595,6 +601,7 @@
uart0: serial@fffd4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd4000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -608,6 +615,7 @@
uart1: serial@fffd8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd8000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
index ce96345d28a3..bb72f050a4fe 100644
--- a/arch/arm/boot/dts/at91sam9260ek.dts
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -92,7 +92,7 @@
spi0: spi@fffc8000 {
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
- mtd_dataflash@1 {
+ flash@1 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <1>;
@@ -144,17 +144,17 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- btn3 {
+ button-3 {
label = "Button 3";
gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
wakeup-source;
};
- btn4 {
+ button-4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 7adc36ca8a46..ee0bd1aceb3f 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -179,6 +180,7 @@
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -192,6 +194,7 @@
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -205,6 +208,7 @@
usart2: serial@fffb8000{
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -301,6 +305,7 @@
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@@ -603,7 +608,7 @@
clock-names = "slow_xtal", "main_xtal";
};
- rstc@fffffd00 {
+ reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index beed819609e8..88869ca874d1 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -145,7 +145,7 @@
cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;
status = "okay";
- mtd_dataflash@0 {
+ flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
reg = <0>;
spi-max-frequency = <15000000>;
@@ -178,6 +178,10 @@
status = "okay";
};
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ };
+
watchdog@fffffd40 {
status = "okay";
};
@@ -207,31 +211,31 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- button_0 {
+ button-0 {
label = "button_0";
gpios = <&pioA 27 GPIO_ACTIVE_LOW>;
linux,code = <256>;
wakeup-source;
};
- button_1 {
+ button-1 {
label = "button_1";
gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
linux,code = <257>;
wakeup-source;
};
- button_2 {
+ button-2 {
label = "button_2";
gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
linux,code = <258>;
wakeup-source;
};
- button_3 {
+ button-3 {
label = "button_3";
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
linux,code = <259>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index fe45d96239c9..3ce9ea987312 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -151,7 +152,7 @@
clock-names = "t0_clk", "slow_clk";
};
- rstc@fffffd00 {
+ reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&slow_xtal>;
@@ -540,6 +541,7 @@
dbgu: serial@ffffee00 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xffffee00 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@@ -551,6 +553,7 @@
usart0: serial@fff8c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff8c000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -564,6 +567,7 @@
usart1: serial@fff90000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff90000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -577,6 +581,7 @@
usart2: serial@fff94000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff94000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 71f60576761a..ce8baff6a9f4 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -95,13 +95,17 @@
spi0: spi@fffa4000 {
status = "okay";
cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
- mtd_dataflash@0 {
+ flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ };
+
watchdog@fffffd40 {
status = "okay";
};
@@ -228,17 +232,17 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- left_click {
+ button-left-click {
label = "left_click";
gpios = <&pioC 5 GPIO_ACTIVE_LOW>;
linux,code = <272>;
wakeup-source;
};
- right_click {
+ button-right-click {
label = "right_click";
gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
linux,code = <273>;
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 87bb39060e8b..024af2db638e 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -39,6 +39,13 @@
};
+ usb1 {
+ pinctrl_usb1_vbus_gpio: usb1_vbus_gpio {
+ atmel,pins =
+ <AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PC5 GPIO */
+ };
+ };
+
mmc0_slot1 {
pinctrl_board_mmc0_slot1: mmc0_slot1-board {
atmel,pins =
@@ -84,6 +91,8 @@
};
usb1: gadget@fffa4000 {
+ pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
+ pinctrl-names = "default";
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@@ -110,7 +119,7 @@
spi0: spi@fffc8000 {
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
- mtd_dataflash@1 {
+ flash@1 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <1>;
@@ -214,25 +223,37 @@
24c512@50 {
compatible = "atmel,24c512";
reg = <0x50>;
+ vcc-supply = <&reg_3v3>;
};
wm8731: wm8731@1b {
compatible = "wm8731";
reg = <0x1b>;
+
+ /* PCK0 at 12MHz */
+ clocks = <&pmc PMC_TYPE_SYSTEM 8>;
+ clock-names = "mclk";
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
+ assigned-clock-rates = <12000000>;
+
+ HPVDD-supply = <&vcc_dac>;
+ AVDD-supply = <&vcc_dac>;
+ DCVDD-supply = <&reg_3v3>;
+ DBVDD-supply = <&reg_3v3>;
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- btn3 {
+ button-3 {
label = "Button 3";
gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
wakeup-source;
};
- btn4 {
+ button-4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -254,4 +275,35 @@
atmel,ssc-controller = <&ssc0>;
atmel,audio-codec = <&wm8731>;
};
+
+ reg_5v: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_3v3: fixedregulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ vin-supply = <&reg_5v>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_1v: fixedregulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1V";
+ vin-supply = <&reg_5v>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ vcc_dac: fixedregulator3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_DAC";
+ vin-supply = <&reg_3v3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts
index 7da70aeeb528..92f2c05c873f 100644
--- a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts
+++ b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts
@@ -23,7 +23,7 @@
gpio-keys {
compatible = "gpio-keys";
- user_btn1 {
+ button {
label = "USER_BTN1";
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 2ab730fd6472..95f5d76234db 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -137,7 +138,7 @@
clock-names = "slow_clk", "main_xtal";
};
- rstc@fffffd00 {
+ reset-controller@fffffd00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
@@ -675,6 +676,7 @@
dbgu: serial@ffffee00 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
reg = <0xffffee00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
@@ -687,6 +689,7 @@
usart0: serial@fff8c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff8c000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -700,6 +703,7 @@
usart1: serial@fff90000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff90000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -713,6 +717,7 @@
usart2: serial@fff94000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff94000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -726,6 +731,7 @@
usart3: serial@fff98000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff98000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index b6256a20fbc7..7f45e81ca165 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -167,7 +167,7 @@
spi0: spi@fffa4000{
status = "okay";
cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
- mtd_dataflash@0 {
+ flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <13000000>;
reg = <0>;
@@ -343,48 +343,48 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- left_click {
+ button-left-click {
label = "left_click";
gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
linux,code = <272>;
wakeup-source;
};
- right_click {
+ button-right-click {
label = "right_click";
gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
linux,code = <273>;
wakeup-source;
};
- left {
+ button-left {
label = "Joystick Left";
gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
linux,code = <105>;
};
- right {
+ button-right {
label = "Joystick Right";
gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
linux,code = <106>;
};
- up {
+ button-up {
label = "Joystick Up";
gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
linux,code = <103>;
};
- down {
+ button-down {
label = "Joystick Down";
gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
linux,code = <108>;
};
- enter {
+ button-enter {
label = "Joystick Press";
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
linux,code = <28>;
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 0785389f5507..83114d26f10d 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -126,7 +127,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
};
- rstc@fffffe00 {
+ reset-controller@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
@@ -593,6 +594,7 @@
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@@ -618,6 +620,7 @@
usart0: serial@f801c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x4000>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
@@ -629,6 +632,7 @@
usart1: serial@f8020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x4000>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
@@ -640,6 +644,7 @@
usart2: serial@f8024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8024000 0x4000>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
@@ -651,6 +656,7 @@
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x4000>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 2bc4e6e0a923..4c644d4c6be7 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -119,7 +119,7 @@
spi0: spi@f0000000 {
status = "okay";
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
- m25p80@0 {
+ flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
@@ -226,10 +226,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- enter {
+ button-enter {
label = "Enter";
gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
linux,code = <28>;
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 730d1182c73e..364a2ff0a763 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -175,6 +176,7 @@
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -188,6 +190,7 @@
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -201,6 +204,7 @@
usart2: serial@fffb8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -214,6 +218,7 @@
usart3: serial@fffbc000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffbc000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -322,6 +327,7 @@
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@@ -766,7 +772,7 @@
clock-names = "slow_clk", "main_xtal";
};
- rstc@fffffd00 {
+ reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index 62981b39c815..a57351270551 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -180,7 +180,7 @@
spi0: spi@fffcc000 {
status = "okay";
cs-gpios = <&pioA 28 0>, <0>, <0>, <0>;
- mtd_dataflash@0 {
+ flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <15000000>;
reg = <0>;
@@ -212,6 +212,10 @@
status = "okay";
};
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ };
+
rtc@fffffe00 {
status = "okay";
};
@@ -244,17 +248,17 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- right_click {
+ button-right-click {
label = "right_click";
gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
linux,code = <273>;
wakeup-source;
};
- left_click {
+ button-left-click {
label = "left_click";
gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
linux,code = <272>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 395e883644cd..0c26c925761b 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -134,7 +135,7 @@
clock-names = "slow_clk", "main_xtal";
};
- reset_controller: rstc@fffffe00 {
+ reset_controller: reset-controller@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
@@ -674,6 +675,7 @@
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@@ -688,6 +690,7 @@
usart0: serial@f801c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
@@ -702,6 +705,7 @@
usart1: serial@f8020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
@@ -716,6 +720,7 @@
usart2: serial@f8024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8024000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
@@ -775,6 +780,7 @@
uart0: serial@f8040000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8040000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
@@ -786,6 +792,7 @@
uart1: serial@f8044000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8044000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 098d3fef5c37..a47c765e1b20 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
aliases {
@@ -44,6 +45,7 @@
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 6d1264de6060..5f4eaa618ab4 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -125,7 +125,7 @@
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
status = "disabled"; /* conflicts with mmc1 */
- m25p80@0 {
+ flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi
index 3bcf4e0a3c85..f13ef80b6637 100644
--- a/arch/arm/boot/dts/axm5516-cpus.dtsi
+++ b/arch/arm/boot/dts/axm5516-cpus.dtsi
@@ -73,7 +73,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x00>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -81,7 +81,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x01>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -89,7 +89,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x02>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -97,7 +97,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x03>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -105,7 +105,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x100>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -113,7 +113,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x101>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -121,7 +121,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x102>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -129,7 +129,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x103>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -137,7 +137,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x200>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -145,7 +145,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x201>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -153,7 +153,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x202>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -161,7 +161,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x203>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -169,7 +169,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x300>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -177,7 +177,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x301>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -185,7 +185,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x302>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
@@ -193,7 +193,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x303>;
- clock-frequency= <1400000000>;
+ clock-frequency = <1400000000>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
};
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index 7676a65059a4..5277890cfad2 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -108,7 +108,7 @@
#size-cells = <2>;
ranges;
- serial0: uart@2010080000 {
+ serial0: serial@2010080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10080000 0 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
@@ -117,7 +117,7 @@
status = "disabled";
};
- serial1: uart@2010081000 {
+ serial1: serial@2010081000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10081000 0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -126,7 +126,7 @@
status = "disabled";
};
- serial2: uart@2010082000 {
+ serial2: serial@2010082000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10082000 0 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
@@ -135,7 +135,7 @@
status = "disabled";
};
- serial3: uart@2010083000 {
+ serial3: serial@2010083000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10083000 0 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi
index a020c12b2884..f79650afd0a7 100644
--- a/arch/arm/boot/dts/axp22x.dtsi
+++ b/arch/arm/boot/dts/axp22x.dtsi
@@ -67,6 +67,12 @@
status = "disabled";
};
+ axp_gpio: gpio {
+ compatible = "x-powers,axp221-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/axp809.dtsi
index ab8e5f2d9246..d134d4c00bd8 100644
--- a/arch/arm/boot/dts/axp809.dtsi
+++ b/arch/arm/boot/dts/axp809.dtsi
@@ -50,4 +50,11 @@
compatible = "x-powers,axp809";
interrupt-controller;
#interrupt-cells = <1>;
+
+ axp_gpio: gpio {
+ compatible = "x-powers,axp809-gpio",
+ "x-powers,axp221-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index b93387b0c1c3..ebaf1c3ce8db 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -62,16 +62,6 @@
compatible = "x-powers,axp813-gpio";
gpio-controller;
#gpio-cells = <2>;
-
- gpio0_ldo: gpio0-ldo-pin {
- pins = "GPIO0";
- function = "ldo";
- };
-
- gpio1_ldo: gpio1-ldo-pin {
- pins = "GPIO1";
- function = "ldo";
- };
};
battery_power_supply: battery-power {
@@ -144,15 +134,11 @@
};
reg_ldo_io0: ldo-io0 {
- pinctrl-names = "default";
- pinctrl-0 = <&gpio0_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
reg_ldo_io1: ldo-io1 {
- pinctrl-names = "default";
- pinctrl-0 = <&gpio1_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index ad65be871938..f9f79ed82518 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -397,8 +397,8 @@
#size-cells = <0>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi_0>;
- clocks = <&axi81_clk>;
- clock-names = "apb_pclk";
+ clocks = <&axi81_clk>, <&axi81_clk>;
+ clock-names = "sspclk", "apb_pclk";
status = "disabled";
};
@@ -409,8 +409,8 @@
#size-cells = <0>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi_1>;
- clocks = <&axi81_clk>;
- clock-names = "apb_pclk";
+ clocks = <&axi81_clk>, <&axi81_clk>;
+ clock-names = "sspclk", "apb_pclk";
status = "disabled";
};
@@ -421,8 +421,8 @@
#size-cells = <0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi_2>;
- clocks = <&axi81_clk>;
- clock-names = "apb_pclk";
+ clocks = <&axi81_clk>, <&axi81_clk>;
+ clock-names = "sspclk", "apb_pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 6197e7d80e3b..ba75784d66a9 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012-2013 Broadcom Corporation
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -60,7 +50,7 @@
reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
};
- uart@3e000000 {
+ serial@3e000000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e000000 0x1000>;
@@ -70,7 +60,7 @@
reg-io-width = <4>;
};
- uart@3e001000 {
+ serial@3e001000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e001000 0x1000>;
@@ -80,7 +70,7 @@
reg-io-width = <4>;
};
- uart@3e002000 {
+ serial@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x1000>;
@@ -90,7 +80,7 @@
reg-io-width = <4>;
};
- uart@3e003000 {
+ serial@3e003000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e003000 0x1000>;
diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts
index be468f4adc37..cd03fa0c2aae 100644
--- a/arch/arm/boot/dts/bcm21664-garnet.dts
+++ b/arch/arm/boot/dts/bcm21664-garnet.dts
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
/dts-v1/;
@@ -26,7 +16,7 @@
reg = <0x80000000 0x40000000>; /* 1 GB */
};
- uart@3e000000 {
+ serial@3e000000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index cc58f2b926b9..ed4de031e48e 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -60,7 +50,7 @@
reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
};
- uart@3e000000 {
+ serial@3e000000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e000000 0x118>;
@@ -70,7 +60,7 @@
reg-io-width = <4>;
};
- uart@3e001000 {
+ serial@3e001000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e001000 0x118>;
@@ -80,7 +70,7 @@
reg-io-width = <4>;
};
- uart@3e002000 {
+ serial@3e002000 {
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x118>;
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
index 4432412044de..d5f8823230db 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
@@ -14,20 +15,7 @@
stdout-path = "serial1:115200n8";
};
- leds {
- led-act {
- gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
- };
-
- led-pwr {
- label = "PWR";
- gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
- };
-
- sd_io_1v8_reg: sd_io_1v8_reg {
+ sd_io_1v8_reg: regulator-sd-io-1v8 {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
regulator-min-microvolt = <1800000>;
@@ -41,7 +29,7 @@
status = "okay";
};
- sd_vcc_reg: sd_vcc_reg {
+ sd_vcc_reg: regulator-sd-vcc {
compatible = "regulator-fixed";
regulator-name = "vcc-sd";
regulator-min-microvolt = <3300000>;
@@ -156,6 +144,19 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ led_pwr: led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+};
+
&pixelvalve0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts
index f4d2fc20397c..1ab8184302db 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts
@@ -11,14 +11,6 @@
stdout-path = "serial1:115200n8";
};
- leds {
- /delete-node/ led-act;
-
- led-pwr {
- gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
- };
- };
-
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>;
@@ -28,18 +20,26 @@
&expgpio {
gpio-line-names = "BT_ON",
"WL_ON",
- "",
+ "PWR_LED_OFF",
"GLOBAL_RESET",
"VDD_SD_IO_SEL",
- "CAM_GPIO",
+ "GLOBAL_SHUTDOWN",
"SD_PWR_ON",
- "SD_OC_N";
+ "SHUTDOWN_REQUEST";
};
&genet_mdio {
clock-frequency = <1950000>;
};
+&led_pwr {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ /delete-node/ led_act;
+};
+
&pm {
/delete-property/ system-power-controller;
};
diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts
index 19600b629be5..d7ba02f586d3 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts
@@ -1,23 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711-rpi-cm4.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
model = "Raspberry Pi Compute Module 4 IO Board";
-
- leds {
- led-act {
- gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
- };
-
- led-pwr {
- label = "PWR";
- gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
- };
};
&ddc0 {
@@ -113,6 +101,19 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+};
+
&pixelvalve0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi b/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi
index a2954d466a73..48e63ab7848c 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi
+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi
@@ -12,7 +12,7 @@
stdout-path = "serial1:115200n8";
};
- sd_io_1v8_reg: sd_io_1v8_reg {
+ sd_io_1v8_reg: regulator-sd-io-1v8 {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
regulator-min-microvolt = <1800000>;
@@ -26,7 +26,7 @@
status = "okay";
};
- sd_vcc_reg: sd_vcc_reg {
+ sd_vcc_reg: regulator-sd-vcc {
compatible = "regulator-fixed";
regulator-name = "vcc-sd";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi
index ca266c5d9f9b..98817a6675b9 100644
--- a/arch/arm/boot/dts/bcm2711-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi
@@ -69,6 +69,10 @@
};
};
+&v3d {
+ clocks = <&firmware_clocks 5>;
+};
+
&vchiq {
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 89af57482bc8..097e9f252235 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -48,7 +48,7 @@
* This node is the provider for the enable-method for
* bringing up secondary cores.
*/
- local_intc: local_intc@40000000 {
+ local_intc: interrupt-controller@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
};
@@ -107,12 +107,13 @@
};
pm: watchdog@7e100000 {
- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x7e100000 0x114>,
<0x7e00a000 0x24>,
<0x7ec11000 0x20>;
+ reg-names = "pm", "asb", "rpivid_asb";
clocks = <&clocks BCM2835_CLOCK_V3D>,
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
<&clocks BCM2835_CLOCK_H264>,
@@ -535,6 +536,7 @@
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
@@ -601,6 +603,17 @@
#size-cells = <0x0>;
};
};
+
+ v3d: gpu@7ec00000 {
+ compatible = "brcm,2711-v3d";
+ reg = <0x0 0x7ec00000 0x4000>,
+ <0x0 0x7ec04000 0x4000>;
+ reg-names = "hub", "core0";
+
+ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
+ resets = <&pm BCM2835_RESET_V3D>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
@@ -635,21 +648,21 @@
gpio-ranges = <&gpio 0 0 58>;
- gpclk0_gpio49: gpclk0_gpio49 {
+ gpclk0_gpio49: gpclk0-gpio49 {
pin-gpclk {
pins = "gpio49";
function = "alt1";
bias-disable;
};
};
- gpclk1_gpio50: gpclk1_gpio50 {
+ gpclk1_gpio50: gpclk1-gpio50 {
pin-gpclk {
pins = "gpio50";
function = "alt1";
bias-disable;
};
};
- gpclk2_gpio51: gpclk2_gpio51 {
+ gpclk2_gpio51: gpclk2-gpio51 {
pin-gpclk {
pins = "gpio51";
function = "alt1";
@@ -657,7 +670,7 @@
};
};
- i2c0_gpio46: i2c0_gpio46 {
+ i2c0_gpio46: i2c0-gpio46 {
pin-sda {
function = "alt0";
pins = "gpio46";
@@ -669,7 +682,7 @@
bias-disable;
};
};
- i2c1_gpio46: i2c1_gpio46 {
+ i2c1_gpio46: i2c1-gpio46 {
pin-sda {
function = "alt1";
pins = "gpio46";
@@ -681,7 +694,7 @@
bias-disable;
};
};
- i2c3_gpio2: i2c3_gpio2 {
+ i2c3_gpio2: i2c3-gpio2 {
pin-sda {
function = "alt5";
pins = "gpio2";
@@ -693,7 +706,7 @@
bias-disable;
};
};
- i2c3_gpio4: i2c3_gpio4 {
+ i2c3_gpio4: i2c3-gpio4 {
pin-sda {
function = "alt5";
pins = "gpio4";
@@ -705,7 +718,7 @@
bias-disable;
};
};
- i2c4_gpio6: i2c4_gpio6 {
+ i2c4_gpio6: i2c4-gpio6 {
pin-sda {
function = "alt5";
pins = "gpio6";
@@ -717,7 +730,7 @@
bias-disable;
};
};
- i2c4_gpio8: i2c4_gpio8 {
+ i2c4_gpio8: i2c4-gpio8 {
pin-sda {
function = "alt5";
pins = "gpio8";
@@ -729,7 +742,7 @@
bias-disable;
};
};
- i2c5_gpio10: i2c5_gpio10 {
+ i2c5_gpio10: i2c5-gpio10 {
pin-sda {
function = "alt5";
pins = "gpio10";
@@ -741,7 +754,7 @@
bias-disable;
};
};
- i2c5_gpio12: i2c5_gpio12 {
+ i2c5_gpio12: i2c5-gpio12 {
pin-sda {
function = "alt5";
pins = "gpio12";
@@ -753,7 +766,7 @@
bias-disable;
};
};
- i2c6_gpio0: i2c6_gpio0 {
+ i2c6_gpio0: i2c6-gpio0 {
pin-sda {
function = "alt5";
pins = "gpio0";
@@ -765,7 +778,7 @@
bias-disable;
};
};
- i2c6_gpio22: i2c6_gpio22 {
+ i2c6_gpio22: i2c6-gpio22 {
pin-sda {
function = "alt5";
pins = "gpio22";
@@ -777,7 +790,7 @@
bias-disable;
};
};
- i2c_slave_gpio8: i2c_slave_gpio8 {
+ i2c_slave_gpio8: i2c-slave-gpio8 {
pins-i2c-slave {
pins = "gpio8",
"gpio9",
@@ -787,7 +800,7 @@
};
};
- jtag_gpio48: jtag_gpio48 {
+ jtag_gpio48: jtag-gpio48 {
pins-jtag {
pins = "gpio48",
"gpio49",
@@ -799,7 +812,7 @@
};
};
- mii_gpio28: mii_gpio28 {
+ mii_gpio28: mii-gpio28 {
pins-mii {
pins = "gpio28",
"gpio29",
@@ -808,7 +821,7 @@
function = "alt4";
};
};
- mii_gpio36: mii_gpio36 {
+ mii_gpio36: mii-gpio36 {
pins-mii {
pins = "gpio36",
"gpio37",
@@ -818,7 +831,7 @@
};
};
- pcm_gpio50: pcm_gpio50 {
+ pcm_gpio50: pcm-gpio50 {
pins-pcm {
pins = "gpio50",
"gpio51",
@@ -828,63 +841,63 @@
};
};
- pwm0_0_gpio12: pwm0_0_gpio12 {
+ pwm0_0_gpio12: pwm0-0-gpio12 {
pin-pwm {
pins = "gpio12";
function = "alt0";
bias-disable;
};
};
- pwm0_0_gpio18: pwm0_0_gpio18 {
+ pwm0_0_gpio18: pwm0-0-gpio18 {
pin-pwm {
pins = "gpio18";
function = "alt5";
bias-disable;
};
};
- pwm1_0_gpio40: pwm1_0_gpio40 {
+ pwm1_0_gpio40: pwm1-0-gpio40 {
pin-pwm {
pins = "gpio40";
function = "alt0";
bias-disable;
};
};
- pwm0_1_gpio13: pwm0_1_gpio13 {
+ pwm0_1_gpio13: pwm0-1-gpio13 {
pin-pwm {
pins = "gpio13";
function = "alt0";
bias-disable;
};
};
- pwm0_1_gpio19: pwm0_1_gpio19 {
+ pwm0_1_gpio19: pwm0-1-gpio19 {
pin-pwm {
pins = "gpio19";
function = "alt5";
bias-disable;
};
};
- pwm1_1_gpio41: pwm1_1_gpio41 {
+ pwm1_1_gpio41: pwm1-1-gpio41 {
pin-pwm {
pins = "gpio41";
function = "alt0";
bias-disable;
};
};
- pwm0_1_gpio45: pwm0_1_gpio45 {
+ pwm0_1_gpio45: pwm0-1-gpio45 {
pin-pwm {
pins = "gpio45";
function = "alt0";
bias-disable;
};
};
- pwm0_0_gpio52: pwm0_0_gpio52 {
+ pwm0_0_gpio52: pwm0-0-gpio52 {
pin-pwm {
pins = "gpio52";
function = "alt1";
bias-disable;
};
};
- pwm0_1_gpio53: pwm0_1_gpio53 {
+ pwm0_1_gpio53: pwm0-1-gpio53 {
pin-pwm {
pins = "gpio53";
function = "alt1";
@@ -892,7 +905,7 @@
};
};
- rgmii_gpio35: rgmii_gpio35 {
+ rgmii_gpio35: rgmii-gpio35 {
pin-start-stop {
pins = "gpio35";
function = "alt4";
@@ -902,26 +915,26 @@
function = "alt4";
};
};
- rgmii_irq_gpio34: rgmii_irq_gpio34 {
+ rgmii_irq_gpio34: rgmii-irq-gpio34 {
pin-irq {
pins = "gpio34";
function = "alt5";
};
};
- rgmii_irq_gpio39: rgmii_irq_gpio39 {
+ rgmii_irq_gpio39: rgmii-irq-gpio39 {
pin-irq {
pins = "gpio39";
function = "alt4";
};
};
- rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
+ rgmii_mdio_gpio28: rgmii-mdio-gpio28 {
pins-mdio {
pins = "gpio28",
"gpio29";
function = "alt5";
};
};
- rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
+ rgmii_mdio_gpio37: rgmii-mdio-gpio37 {
pins-mdio {
pins = "gpio37",
"gpio38";
@@ -929,7 +942,7 @@
};
};
- spi0_gpio46: spi0_gpio46 {
+ spi0_gpio46: spi0-gpio46 {
pins-spi {
pins = "gpio46",
"gpio47",
@@ -938,7 +951,7 @@
function = "alt2";
};
};
- spi2_gpio46: spi2_gpio46 {
+ spi2_gpio46: spi2-gpio46 {
pins-spi {
pins = "gpio46",
"gpio47",
@@ -948,7 +961,7 @@
function = "alt5";
};
};
- spi3_gpio0: spi3_gpio0 {
+ spi3_gpio0: spi3-gpio0 {
pins-spi {
pins = "gpio0",
"gpio1",
@@ -957,7 +970,7 @@
function = "alt3";
};
};
- spi4_gpio4: spi4_gpio4 {
+ spi4_gpio4: spi4-gpio4 {
pins-spi {
pins = "gpio4",
"gpio5",
@@ -966,7 +979,7 @@
function = "alt3";
};
};
- spi5_gpio12: spi5_gpio12 {
+ spi5_gpio12: spi5-gpio12 {
pins-spi {
pins = "gpio12",
"gpio13",
@@ -975,7 +988,7 @@
function = "alt3";
};
};
- spi6_gpio18: spi6_gpio18 {
+ spi6_gpio18: spi6-gpio18 {
pins-spi {
pins = "gpio18",
"gpio19",
@@ -985,7 +998,7 @@
};
};
- uart2_gpio0: uart2_gpio0 {
+ uart2_gpio0: uart2-gpio0 {
pin-tx {
pins = "gpio0";
function = "alt4";
@@ -997,7 +1010,7 @@
bias-pull-up;
};
};
- uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
+ uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 {
pin-cts {
pins = "gpio2";
function = "alt4";
@@ -1009,7 +1022,7 @@
bias-disable;
};
};
- uart3_gpio4: uart3_gpio4 {
+ uart3_gpio4: uart3-gpio4 {
pin-tx {
pins = "gpio4";
function = "alt4";
@@ -1021,7 +1034,7 @@
bias-pull-up;
};
};
- uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
+ uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 {
pin-cts {
pins = "gpio6";
function = "alt4";
@@ -1033,7 +1046,7 @@
bias-disable;
};
};
- uart4_gpio8: uart4_gpio8 {
+ uart4_gpio8: uart4-gpio8 {
pin-tx {
pins = "gpio8";
function = "alt4";
@@ -1045,7 +1058,7 @@
bias-pull-up;
};
};
- uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
+ uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 {
pin-cts {
pins = "gpio10";
function = "alt4";
@@ -1057,7 +1070,7 @@
bias-disable;
};
};
- uart5_gpio12: uart5_gpio12 {
+ uart5_gpio12: uart5-gpio12 {
pin-tx {
pins = "gpio12";
function = "alt4";
@@ -1069,7 +1082,7 @@
bias-pull-up;
};
};
- uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
+ uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 {
pin-cts {
pins = "gpio14";
function = "alt4";
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index ead6e9804dbf..60c8ab8a2855 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013 Broadcom Corporation
/dts-v1/;
@@ -26,27 +16,27 @@
reg = <0x80000000 0x40000000>; /* 1 GB */
};
- uart@3e000000 {
+ serial@3e000000 {
status = "okay";
};
i2c@3e016000 {
- status="okay";
+ status = "okay";
clock-frequency = <400000>;
};
i2c@3e017000 {
- status="okay";
+ status = "okay";
clock-frequency = <400000>;
};
i2c@3e018000 {
- status="okay";
+ status = "okay";
clock-frequency = <400000>;
};
i2c@3500d000 {
- status="okay";
+ status = "okay";
clock-frequency = <100000>;
pmu: pmu@8 {
diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi
index c25e797b9060..bb7e8f7facaf 100644
--- a/arch/arm/boot/dts/bcm2835-common.dtsi
+++ b/arch/arm/boot/dts/bcm2835-common.dtsi
@@ -62,6 +62,7 @@
#reset-cells = <1>;
reg = <0x7e100000 0x114>,
<0x7e00a000 0x24>;
+ reg-names = "pm", "asb";
clocks = <&clocks BCM2835_CLOCK_V3D>,
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
<&clocks BCM2835_CLOCK_H264>,
@@ -151,41 +152,41 @@
};
&gpio {
- i2c_slave_gpio18: i2c_slave_gpio18 {
+ i2c_slave_gpio18: i2c-slave-gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
- jtag_gpio4: jtag_gpio4 {
+ jtag_gpio4: jtag-gpio4 {
brcm,pins = <4 5 6 12 13>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- pwm0_gpio12: pwm0_gpio12 {
+ pwm0_gpio12: pwm0-gpio12 {
brcm,pins = <12>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- pwm0_gpio18: pwm0_gpio18 {
+ pwm0_gpio18: pwm0-gpio18 {
brcm,pins = <18>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- pwm0_gpio40: pwm0_gpio40 {
+ pwm0_gpio40: pwm0-gpio40 {
brcm,pins = <40>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- pwm1_gpio13: pwm1_gpio13 {
+ pwm1_gpio13: pwm1-gpio13 {
brcm,pins = <13>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- pwm1_gpio19: pwm1_gpio19 {
+ pwm1_gpio19: pwm1-gpio19 {
brcm,pins = <19>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- pwm1_gpio41: pwm1_gpio41 {
+ pwm1_gpio41: pwm1-gpio41 {
brcm,pins = <41>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- pwm1_gpio45: pwm1_gpio45 {
+ pwm1_gpio45: pwm1-gpio45 {
brcm,pins = <45>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index 40b9405f1a8e..02ce817868ba 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
@@ -12,19 +14,6 @@
device_type = "memory";
reg = <0 0x10000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
- };
-
- led-pwr {
- label = "PWR";
- gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
- };
};
&gpio {
@@ -32,7 +21,6 @@
* This is based on the unreleased schematic for the Model A+.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -67,21 +55,21 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
- "NC", /* GPIO31 */
+ "", /* GPIO30 */
+ "", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
@@ -108,6 +96,19 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ led-pwr {
+ label = "PWR";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 11edb581dbaf..3fdf60eb11dc 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
@@ -12,12 +14,6 @@
device_type = "memory";
reg = <0 0x10000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
- };
- };
};
&gpio {
@@ -26,7 +22,6 @@
* RPI00021 sheet 02
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -42,41 +37,41 @@
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
- "NC", /* GPIO12 */
- "NC", /* GPIO13 */
+ "", /* GPIO12 */
+ "", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
- "NC", /* GPIO19 */
- "NC", /* GPIO20 */
+ "", /* GPIO19 */
+ "", /* GPIO20 */
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
- "NC", /* GPIO26 */
+ "", /* GPIO26 */
"CAM_GPIO0",
/* Binary number representing build/revision */
"CONFIG0",
"CONFIG1",
"CONFIG2",
"CONFIG3",
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO32 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
"PWM0_OUT",
- "NC", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO41 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
@@ -103,6 +98,10 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index 1b435c64bd9c..9956fd06a4b6 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
@@ -13,19 +15,6 @@
device_type = "memory";
reg = <0 0x20000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
- };
-
- led-pwr {
- label = "PWR";
- gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
- };
};
&gpio {
@@ -34,7 +23,6 @@
* RPI-BPLUS sheet 1
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -69,21 +57,21 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
+ "", /* GPIO30 */
"LAN_RUN", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
"PWR_LOW_N", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
"USB_LIMIT", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO39 */
"PWM0_OUT", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "ETHCLK", /* GPIO44 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "ETH_CLK", /* GPIO44 */
"PWM1_OUT", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED",
@@ -110,6 +98,19 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ led-pwr {
+ label = "PWR";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index a23c25c00eea..4e1770afb145 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-smsc9512.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
@@ -13,12 +15,6 @@
device_type = "memory";
reg = <0 0x10000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
- };
- };
};
&gpio {
@@ -27,7 +23,6 @@
* RPI00022 sheet 02
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -43,40 +38,40 @@
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
- "NC", /* GPIO12 */
- "NC", /* GPIO13 */
+ "", /* GPIO12 */
+ "", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
- "NC", /* GPIO19 */
- "NC", /* GPIO20 */
+ "", /* GPIO19 */
+ "", /* GPIO20 */
"CAM_GPIO",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
- "NC", /* GPIO26 */
+ "", /* GPIO26 */
"GPIO27",
"GPIO28",
"GPIO29",
"GPIO30",
"GPIO31",
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO32 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
"PWM0_OUT",
- "NC", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO41 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
@@ -103,6 +98,10 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 1b63d6b19750..eec1d0892d33 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-smsc9512.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
@@ -13,12 +15,6 @@
device_type = "memory";
reg = <0 0x10000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
- };
- };
};
&gpio {
@@ -27,7 +23,6 @@
* RPI00021 sheet 02
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -43,41 +38,40 @@
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
- "NC", /* GPIO12 */
- "NC", /* GPIO13 */
+ "", /* GPIO12 */
+ "", /* GPIO13 */
/* Serial port */
"TXD0",
"RXD0",
"STATUS_LED_N",
"GPIO17",
"GPIO18",
- "NC", /* GPIO19 */
- "NC", /* GPIO20 */
- "GPIO21",
+ "", /* GPIO19 */
+ "", /* GPIO20 */
+ "CAM_GPIO0",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
- "NC", /* GPIO26 */
- "CAM_GPIO0",
- /* Binary number representing build/revision */
- "CONFIG0",
- "CONFIG1",
- "CONFIG2",
- "CONFIG3",
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ "", /* GPIO26 */
+ "GPIO27",
+ "GPIO28",
+ "GPIO29",
+ "GPIO30",
+ "GPIO31",
+ "", /* GPIO32 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
"PWM0_OUT",
- "NC", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
+ "", /* GPIO41 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
"PWM1_OUT",
"HDMI_HPD_P",
"SD_CARD_DET",
@@ -98,6 +92,10 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts
index a75c882e6575..87958a96c3e0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts
@@ -13,7 +13,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
index e4e6b6abbfc1..750cd76948e3 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
@@ -2,6 +2,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
/ {
leds {
@@ -32,6 +34,10 @@
};
};
+&led_act {
+ gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+};
+
&sdhost {
non-removable;
vmmc-supply = <&reg_3v3>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi
index 8a55b6cded59..4e7b4a592da7 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi
@@ -7,6 +7,23 @@
#include <dt-bindings/power/raspberrypi-power.h>
+&firmware {
+ firmware_clocks: clocks {
+ compatible = "raspberrypi,firmware-clocks";
+ #clock-cells = <1>;
+ };
+};
+
+&hdmi {
+ clocks = <&firmware_clocks 9>,
+ <&firmware_clocks 13>;
+ clock-names = "pixel", "hdmi";
+};
+
&v3d {
power-domains = <&power RPI_POWER_DOMAIN_V3D>;
};
+
+&vec {
+ clocks = <&firmware_clocks 15>;
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
index 243236bc1e00..dbf825985ec0 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
@@ -22,12 +24,6 @@
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
-
- leds {
- led-act {
- gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
- };
- };
};
&bt {
@@ -39,7 +35,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -74,19 +69,21 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
- "NC", /* GPIO31 */
- "NC", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
"CAM_GPIO1", /* GPIO40 */
"WL_ON", /* GPIO41 */
- "NC", /* GPIO42 */
+ "", /* GPIO42 */
"WIFI_CLK", /* GPIO43 */
"CAM_GPIO0", /* GPIO44 */
"BT_ON", /* GPIO45 */
@@ -109,6 +106,10 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+};
+
&sdhci {
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 6f9b3a908f28..f80e65a825fd 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
/ {
@@ -16,12 +18,6 @@
device_type = "memory";
reg = <0 0x20000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
- };
- };
};
&gpio {
@@ -29,7 +25,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -64,22 +59,22 @@
"GPIO27",
"SDA0",
"SCL0",
- "NC", /* GPIO30 */
- "NC", /* GPIO31 */
+ "", /* GPIO30 */
+ "", /* GPIO31 */
"CAM_GPIO1", /* GPIO32 */
- "NC", /* GPIO33 */
- "NC", /* GPIO34 */
- "NC", /* GPIO35 */
- "NC", /* GPIO36 */
- "NC", /* GPIO37 */
- "NC", /* GPIO38 */
- "NC", /* GPIO39 */
- "NC", /* GPIO40 */
+ "", /* GPIO33 */
+ "", /* GPIO34 */
+ "", /* GPIO35 */
+ "", /* GPIO36 */
+ "", /* GPIO37 */
+ "", /* GPIO38 */
+ "", /* GPIO39 */
+ "", /* GPIO40 */
"CAM_GPIO0", /* GPIO41 */
- "NC", /* GPIO42 */
- "NC", /* GPIO43 */
- "NC", /* GPIO44 */
- "NC", /* GPIO45 */
+ "", /* GPIO42 */
+ "", /* GPIO43 */
+ "", /* GPIO44 */
+ "", /* GPIO45 */
"HDMI_HPD_N",
"STATUS_LED_N",
/* Used by SD Card */
@@ -105,6 +100,10 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
+};
+
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 87ddcad76083..ee9ee9d1fe65 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -1,16 +1,6 @@
#include <dt-bindings/power/raspberrypi-power.h>
/ {
- leds {
- compatible = "gpio-leds";
-
- led-act {
- label = "ACT";
- default-state = "keep";
- linux,default-trigger = "heartbeat";
- };
- };
-
soc {
firmware: firmware {
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 1c90e5a44283..15cb331febbb 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
#include "bcm2835-common.dtsi"
-#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2835";
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index d8af8eeac7b6..6068ec390081 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "bcm2836.dtsi"
#include "bcm2836-rpi.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
@@ -13,19 +14,6 @@
device_type = "memory";
reg = <0 0x40000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
- };
-
- led-pwr {
- label = "PWR";
- gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
- };
};
&gpio {
@@ -34,7 +22,6 @@
* the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -83,7 +70,7 @@
"CAM_GPIO0",
"SMPS_SCL",
"SMPS_SDA",
- "ETHCLK",
+ "ETH_CLK",
"PWM1_OUT",
"HDMI_HPD_N",
"STATUS_LED",
@@ -110,6 +97,19 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ led-pwr {
+ label = "PWR";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
diff --git a/arch/arm/boot/dts/bcm2836-rpi.dtsi b/arch/arm/boot/dts/bcm2836-rpi.dtsi
index c4c858b984c6..48b03b55ff56 100644
--- a/arch/arm/boot/dts/bcm2836-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2836-rpi.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm2835-rpi.dtsi"
+#include "bcm2835-rpi-common.dtsi"
&vchiq {
compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq";
diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi
index 534dacfc4dd5..783fe624ba68 100644
--- a/arch/arm/boot/dts/bcm2836.dtsi
+++ b/arch/arm/boot/dts/bcm2836.dtsi
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
#include "bcm2835-common.dtsi"
-#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2836";
@@ -11,7 +10,7 @@
<0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
- local_intc: local_intc@40000000 {
+ local_intc: interrupt-controller@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
@@ -113,6 +112,7 @@
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
index d73daf5bff1d..3548306dfbcb 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
@@ -18,19 +19,6 @@
device_type = "memory";
reg = <0 0x20000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
- };
-
- led-pwr {
- label = "PWR";
- gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
- };
};
&firmware {
@@ -55,7 +43,6 @@
* This is mostly based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -125,6 +112,19 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
index e12938baaf12..2f1800cbc522 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
@@ -3,6 +3,7 @@
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-lan7515.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
@@ -19,19 +20,6 @@
device_type = "memory";
reg = <0 0x40000000>;
};
-
- leds {
- led-act {
- gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
- };
-
- led-pwr {
- label = "PWR";
- gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
- };
};
&bt {
@@ -45,7 +33,7 @@
#gpio-cells = <2>;
gpio-line-names = "BT_ON",
"WL_ON",
- "STATUS_LED_R",
+ "PWR_LED_R",
"LAN_RUN",
"",
"CAM_GPIO0",
@@ -61,7 +49,6 @@
* the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -110,7 +97,7 @@
"SD1_DATA3",
"PWM0_OUT",
"PWM1_OUT",
- "ETHCLK",
+ "ETH_CLK",
"WIFI_CLK",
"SDA0",
"SCL0",
@@ -131,6 +118,19 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+};
+
+&leds {
+ led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index 42b5383b55d8..61270340075c 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
@@ -19,12 +20,6 @@
device_type = "memory";
reg = <0 0x40000000>;
};
-
- leds {
- led-act {
- gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
- };
- };
};
&bt {
@@ -54,7 +49,6 @@
* the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -103,7 +97,7 @@
"SD1_DATA3",
"PWM0_OUT",
"PWM1_OUT",
- "ETHCLK",
+ "ETH_CLK",
"WIFI_CLK",
"SDA0",
"SCL0",
@@ -130,6 +124,10 @@
status = "okay";
};
+&led_act {
+ gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
+};
+
/* uart0 communicates with the BT module */
&uart0 {
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts
index 588d9411ceb6..cf84e69fced8 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts
@@ -13,7 +13,6 @@
* This is based on the official GPU firmware DT blob.
*
* Legend:
- * "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
@@ -63,8 +62,8 @@
"GPIO43",
"GPIO44",
"GPIO45",
- "GPIO46",
- "GPIO47",
+ "SMPS_SCL",
+ "SMPS_SDA",
/* Used by eMMC */
"SD_CLK_R",
"SD_CMD_R",
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
index 828a20561b96..1e4e4946b6b6 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
@@ -9,14 +9,6 @@
reg = <0 0x40000000>;
};
- leds {
- /*
- * Since there is no upstream GPIO driver yet,
- * remove the incomplete node.
- */
- /delete-node/ led-act;
- };
-
reg_3v3: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "3V3";
@@ -41,12 +33,12 @@
#gpio-cells = <2>;
gpio-line-names = "HDMI_HPD_N",
"EMMC_EN_N",
- "NC",
- "NC",
- "NC",
- "NC",
- "NC",
- "NC";
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts
index 4a768562985e..b9cc4594398b 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
+#include "bcm283x-rpi-led-deprecated.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
@@ -22,12 +23,6 @@
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
-
- leds {
- led-act {
- gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
- };
- };
};
&bt {
@@ -109,6 +104,10 @@
status = "okay";
};
+&led_act {
+ gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+};
+
&sdhci {
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
};
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 5dbdebc46259..84c08b46519d 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -1,6 +1,5 @@
#include "bcm283x.dtsi"
#include "bcm2835-common.dtsi"
-#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2837";
@@ -115,6 +114,7 @@
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
diff --git a/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi b/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi
new file mode 100644
index 000000000000..f83e56de1a72
--- /dev/null
+++ b/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ /*
+ * This file provides the now deprecated ACT LED to the
+ * Raspberry Pi boards. Please don't include this file
+ * for new boards!
+ */
+ leds: leds {
+ compatible = "gpio-leds";
+
+ led_act: led-act {
+ label = "ACT";
+ default-state = "keep";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi
index 967e081cb9c2..882b13807075 100644
--- a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi
+++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi
@@ -12,7 +12,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
index dc7ae776db5f..4273b90b53cc 100644
--- a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
+++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
@@ -11,7 +11,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index c113661a6668..c9c52a19ef3b 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -50,9 +50,9 @@
trips {
cpu-crit {
- temperature = <90000>;
- hysteresis = <0>;
- type = "critical";
+ temperature = <90000>;
+ hysteresis = <0>;
+ type = "critical";
};
};
@@ -135,17 +135,17 @@
* groups only make sense to switch to a
* particular function together.
*/
- dpi_gpio0: dpi_gpio0 {
+ dpi_gpio0: dpi-gpio0 {
brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- emmc_gpio22: emmc_gpio22 {
+ emmc_gpio22: emmc-gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
- emmc_gpio34: emmc_gpio34 {
+ emmc_gpio34: emmc-gpio34 {
brcm,pins = <34 35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT3>;
brcm,pull = <BCM2835_PUD_OFF
@@ -155,95 +155,95 @@
BCM2835_PUD_UP
BCM2835_PUD_UP>;
};
- emmc_gpio48: emmc_gpio48 {
+ emmc_gpio48: emmc-gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
- gpclk0_gpio4: gpclk0_gpio4 {
+ gpclk0_gpio4: gpclk0-gpio4 {
brcm,pins = <4>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- gpclk1_gpio5: gpclk1_gpio5 {
+ gpclk1_gpio5: gpclk1-gpio5 {
brcm,pins = <5>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- gpclk1_gpio42: gpclk1_gpio42 {
+ gpclk1_gpio42: gpclk1-gpio42 {
brcm,pins = <42>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- gpclk1_gpio44: gpclk1_gpio44 {
+ gpclk1_gpio44: gpclk1-gpio44 {
brcm,pins = <44>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- gpclk2_gpio6: gpclk2_gpio6 {
+ gpclk2_gpio6: gpclk2-gpio6 {
brcm,pins = <6>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- gpclk2_gpio43: gpclk2_gpio43 {
+ gpclk2_gpio43: gpclk2-gpio43 {
brcm,pins = <43>;
brcm,function = <BCM2835_FSEL_ALT0>;
brcm,pull = <BCM2835_PUD_OFF>;
};
- i2c0_gpio0: i2c0_gpio0 {
+ i2c0_gpio0: i2c0-gpio0 {
brcm,pins = <0 1>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- i2c0_gpio28: i2c0_gpio28 {
+ i2c0_gpio28: i2c0-gpio28 {
brcm,pins = <28 29>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- i2c0_gpio44: i2c0_gpio44 {
+ i2c0_gpio44: i2c0-gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT1>;
};
- i2c1_gpio2: i2c1_gpio2 {
+ i2c1_gpio2: i2c1-gpio2 {
brcm,pins = <2 3>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- i2c1_gpio44: i2c1_gpio44 {
+ i2c1_gpio44: i2c1-gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- jtag_gpio22: jtag_gpio22 {
+ jtag_gpio22: jtag-gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
- pcm_gpio18: pcm_gpio18 {
+ pcm_gpio18: pcm-gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- pcm_gpio28: pcm_gpio28 {
+ pcm_gpio28: pcm-gpio28 {
brcm,pins = <28 29 30 31>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- sdhost_gpio48: sdhost_gpio48 {
+ sdhost_gpio48: sdhost-gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- spi0_gpio7: spi0_gpio7 {
+ spi0_gpio7: spi0-gpio7 {
brcm,pins = <7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- spi0_gpio35: spi0_gpio35 {
+ spi0_gpio35: spi0-gpio35 {
brcm,pins = <35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
- spi1_gpio16: spi1_gpio16 {
+ spi1_gpio16: spi1-gpio16 {
brcm,pins = <16 17 18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
- spi2_gpio40: spi2_gpio40 {
+ spi2_gpio40: spi2-gpio40 {
brcm,pins = <40 41 42 43 44 45>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
- uart0_gpio14: uart0_gpio14 {
+ uart0_gpio14: uart0-gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
@@ -252,50 +252,50 @@
* people often run uart0 on the two pins
* without flow control.
*/
- uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
+ uart0_ctsrts_gpio16: uart0-ctsrts-gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
- uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
+ uart0_ctsrts_gpio30: uart0-ctsrts-gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT3>;
brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
};
- uart0_gpio32: uart0_gpio32 {
+ uart0_gpio32: uart0-gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>;
brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
};
- uart0_gpio36: uart0_gpio36 {
+ uart0_gpio36: uart0-gpio36 {
brcm,pins = <36 37>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
+ uart0_ctsrts_gpio38: uart0-ctsrts-gpio38 {
brcm,pins = <38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- uart1_gpio14: uart1_gpio14 {
+ uart1_gpio14: uart1-gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
+ uart1_ctsrts_gpio16: uart1-ctsrts-gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- uart1_gpio32: uart1_gpio32 {
+ uart1_gpio32: uart1-gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
+ uart1_ctsrts_gpio30: uart1-ctsrts-gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- uart1_gpio40: uart1_gpio40 {
+ uart1_gpio40: uart1-gpio40 {
brcm,pins = <40 41>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
- uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
+ uart1_ctsrts_gpio42: uart1-ctsrts-gpio42 {
brcm,pins = <42 43>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
@@ -352,8 +352,6 @@
clocks = <&clocks BCM2835_CLOCK_VPU>,
<&clocks BCM2835_CLOCK_DPI>;
clock-names = "core", "pixel";
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
index 8ed403767540..c80ac16ad949 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
@@ -28,40 +28,39 @@
leds {
compatible = "gpio-leds";
- usb3 {
+ led-usb3 {
label = "bcm53xx:blue:usb3";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
};
- wan {
+ led-wan {
label = "bcm53xx:blue:wan";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
};
- lan {
+ led-lan {
label = "bcm53xx:blue:lan";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
};
- power {
+ led-power {
label = "bcm53xx:blue:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- all {
+ led-all {
label = "bcm53xx:blue:all";
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
};
-
- usb2 {
+ led-usb2 {
label = "bcm53xx:blue:usb2";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
@@ -70,19 +69,19 @@
gpio-keys {
compatible = "gpio-keys";
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
index 667b118ba4ee..3fe17bd7b86d 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
@@ -28,24 +28,24 @@
leds {
compatible = "gpio-leds";
- usb2 {
+ led-usb2 {
label = "bcm53xx:blue:usb2";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
};
- power {
+ led-power {
label = "bcm53xx:blue:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- logo {
+ led-logo {
label = "bcm53xx:white:logo";
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:blue:usb3";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
@@ -54,25 +54,25 @@
gpio-keys {
compatible = "gpio-keys";
- brightness {
+ button-brightness {
label = "Backlight";
linux,code = <KEY_BRIGHTNESS_ZERO>;
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
new file mode 100644
index 000000000000..e583b9cbf07c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
+ */
+
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ spi {
+ compatible = "spi-gpio";
+ num-chipselects = <1>;
+ gpio-sck = <&chipcommon 7 0>;
+ gpio-mosi = <&chipcommon 4 0>;
+ cs-gpios = <&chipcommon 6 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hc595: gpio_spi@0 {
+ compatible = "fairchild,74hc595";
+ reg = <0>;
+ registers-number = <1>;
+ spi-max-frequency = <100000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-usb {
+ /* label = "bcm53xx:blue:usb"; */
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>,
+ <&xhci_port1>, <&ohci_port2>,
+ <&ehci_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ led-power0 {
+ /* label = "bcm53xx:red:power"; */
+ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-power1 {
+ /* label = "bcm53xx:white:power"; */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-router0 {
+ /* label = "bcm53xx:blue:router"; */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-router1 {
+ /* label = "bcm53xx:amber:router"; */
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ /* label = "bcm53xx:blue:wan"; */
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-wireless0 {
+ /* label = "bcm53xx:blue:wireless"; */
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wireless1 {
+ /* label = "bcm53xx:amber:wireless"; */
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+
+ button-aoss {
+ label = "AOSS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+ };
+
+ /* Commit mode set by switch? */
+ button-mode {
+ label = "Mode";
+ linux,code = <KEY_SETUP>;
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ };
+
+ /* Switch: AP mode */
+ button-sw-ap {
+ label = "AP";
+ linux,code = <BTN_0>;
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ };
+
+ button-eject {
+ label = "USB eject";
+ linux,code = <KEY_EJECTCD>;
+ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&usb2 {
+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+};
+
+&spi_nor {
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts
new file mode 100644
index 000000000000..8e506269fa1a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindigs for Buffalo WZR-1166DHP
+ *
+ * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi"
+
+/ {
+ compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708";
+ model = "Buffalo WZR-1166DHP";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
+ };
+
+};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts
new file mode 100644
index 000000000000..596129027074
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindigs for Buffalo WZR-1166DHP2
+ *
+ * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi"
+
+/ {
+ compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708";
+ model = "Buffalo WZR-1166DHP2";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
+ };
+
+};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index ff31ce45831a..43c698a0a7c3 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -49,7 +49,7 @@
leds {
compatible = "gpio-leds";
- usb {
+ led-usb {
label = "bcm53xx:blue:usb";
gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -58,40 +58,40 @@
linux,default-trigger = "usbport";
};
- power0 {
+ led-power0 {
label = "bcm53xx:red:power";
gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
};
- power1 {
+ led-power1 {
label = "bcm53xx:white:power";
gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- router0 {
+ led-router0 {
label = "bcm53xx:blue:router";
gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- router1 {
+ led-router1 {
label = "bcm53xx:amber:router";
gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
};
- wan {
+ led-wan {
label = "bcm53xx:blue:wan";
gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- wireless0 {
+ led-wireless0 {
label = "bcm53xx:blue:wireless";
gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
};
- wireless1 {
+ led-wireless1 {
label = "bcm53xx:amber:wireless";
gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
};
@@ -100,33 +100,33 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
- aoss {
+ button-aoss {
label = "AOSS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
};
/* Commit mode set by switch? */
- mode {
+ button-mode {
label = "Mode";
linux,code = <KEY_SETUP>;
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
/* Switch: AP mode */
- sw_ap {
+ button-sw-ap {
label = "AP";
linux,code = <BTN_0>;
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
- eject {
+ button-eject {
label = "USB eject";
linux,code = <KEY_EJECTCD>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
index 5bac1e15775a..0ed25bf71f0d 100644
--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
@@ -29,13 +29,13 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
index cd797b4202ad..f1412ba83def 100644
--- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
@@ -25,13 +25,13 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
index 5b4a481be4f4..6de7fe204b0c 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
@@ -23,19 +23,19 @@
leds {
compatible = "gpio-leds";
- 5ghz {
+ led-5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
@@ -45,7 +45,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
index c81944cd6d0b..f5b75ba93512 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -42,7 +42,7 @@
leds {
compatible = "gpio-leds";
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
@@ -52,7 +52,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 43a5d675dd67..89155caf50be 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -29,24 +29,24 @@
leds {
compatible = "gpio-leds";
- logo {
+ led-logo {
label = "bcm53xx:white:logo";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- power0 {
+ led-power0 {
label = "bcm53xx:green:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- power1 {
+ led-power1 {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- usb {
+ led-usb {
label = "bcm53xx:blue:usb";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -54,7 +54,7 @@
linux,default-trigger = "usbport";
};
- wireless {
+ led-wireless {
label = "bcm53xx:blue:wireless";
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
@@ -63,19 +63,19 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
index 4c60eda296d9..57d00a0b4765 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -28,29 +28,29 @@
leds {
compatible = "gpio-leds";
- logo {
+ led-logo {
label = "bcm53xx:white:logo";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- power0 {
+ led-power0 {
label = "bcm53xx:green:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
};
- power1 {
+ led-power1 {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- usb {
+ led-usb {
label = "bcm53xx:blue:usb";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
};
- wireless {
+ led-wireless {
label = "bcm53xx:blue:wireless";
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
@@ -59,19 +59,19 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
index 9ca6d1b2590d..26cdeb5cc337 100644
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
@@ -28,64 +28,64 @@
leds {
compatible = "gpio-leds";
- power-white {
+ led-power-white {
label = "bcm53xx:white:power";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- power-amber {
+ led-power-amber {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
};
- usb2 {
+ led-usb2 {
label = "bcm53xx:white:usb2";
gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port2>, <&ehci_port2>;
linux,default-trigger = "usbport";
};
- usb3-white {
+ led-usb3-white {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
trigger-sources = <&xhci_port1>;
linux,default-trigger = "usbport";
};
- usb3-green {
+ led-usb3-green {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
linux,default-trigger = "usbport";
};
- wps {
+ led-wps {
label = "bcm53xx:white:wps";
gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
};
- status-red {
+ led-status-red {
label = "bcm53xx:red:status";
gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
};
- status-green {
+ led-status-green {
label = "bcm53xx:green:status";
gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
- status-blue {
+ led-status-blue {
label = "bcm53xx:blue:status";
gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
};
- wan-white {
+ led-wan-white {
label = "bcm53xx:white:wan";
gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
};
- wan-red {
+ led-wan-red {
label = "bcm53xx:red:wan";
gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
};
@@ -94,19 +94,19 @@
gpio-keys {
compatible = "gpio-keys";
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
index 0e273c598732..3854db0118a9 100644
--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -28,30 +28,30 @@
leds {
compatible = "gpio-leds";
- power {
+ led-power {
label = "bcm53xx:blue:power";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- usb2 {
+ led-usb2 {
label = "bcm53xx:blue:usb2";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- wan {
+ led-wan {
label = "bcm53xx:blue:wan";
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- lan {
+ led-lan {
label = "bcm53xx:blue:lan";
gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:blue:usb3";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
@@ -60,13 +60,13 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
index d00495a8b6fc..407319cb5c0d 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -49,40 +49,40 @@
leds {
compatible = "gpio-leds";
- power0 {
+ led-power0 {
label = "bcm53xx:green:power";
gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- power1 {
+ led-power1 {
label = "bcm53xx:red:power";
gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
};
- router0 {
+ led-router0 {
label = "bcm53xx:green:router";
gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- router1 {
+ led-router1 {
label = "bcm53xx:amber:router";
gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
};
- wan {
+ led-wan {
label = "bcm53xx:green:wan";
gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- wireless0 {
+ led-wireless0 {
label = "bcm53xx:green:wireless";
gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
};
- wireless1 {
+ led-wireless1 {
label = "bcm53xx:amber:wireless";
gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
};
@@ -91,26 +91,26 @@
gpio-keys {
compatible = "gpio-keys";
- aoss {
+ button-aoss {
label = "AOSS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
/* Switch device mode? */
- mode {
+ button-mode {
label = "Mode";
linux,code = <KEY_SETUP>;
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
- eject {
+ button-eject {
label = "USB eject";
linux,code = <KEY_EJECTCD>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index 8b1a05a0f1a1..f8622ecce6a2 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -49,45 +49,45 @@
leds {
compatible = "gpio-leds";
- usb {
+ led-usb {
label = "bcm53xx:green:usb";
gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
};
- power0 {
+ led-power0 {
label = "bcm53xx:green:power";
gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- power1 {
+ led-power1 {
label = "bcm53xx:red:power";
gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
};
- router0 {
+ led-router0 {
label = "bcm53xx:green:router";
gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- router1 {
+ led-router1 {
label = "bcm53xx:amber:router";
gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
};
- wan {
+ led-wan {
label = "bcm53xx:green:wan";
gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- wireless0 {
+ led-wireless0 {
label = "bcm53xx:green:wireless";
gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
};
- wireless1 {
+ led-wireless1 {
label = "bcm53xx:amber:wireless";
gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
};
@@ -96,7 +96,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
index 68aaf0af3945..76c9b30b868d 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
@@ -23,19 +23,19 @@
leds {
compatible = "gpio-leds";
- 5ghz {
+ led-5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
@@ -45,7 +45,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
index 9316a36434f7..6ef0c0788e62 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
@@ -29,62 +29,62 @@
leds {
compatible = "gpio-leds";
- power {
+ led-power {
label = "bcm53xx:green:power";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- lan3 {
+ led-lan3 {
label = "bcm53xx:green:lan3";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- lan4 {
+ led-lan4 {
label = "bcm53xx:green:lan4";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- wan {
+ led-wan {
label = "bcm53xx:green:wan";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- lan2 {
+ led-lan2 {
label = "bcm53xx:green:lan2";
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- usb {
+ led-usb {
label = "bcm53xx:green:usb";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port2>, <&ehci_port2>;
linux,default-trigger = "usbport";
};
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:green:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:green:5ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
- lan1 {
+ led-lan1 {
label = "bcm53xx:green:lan1";
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
@@ -94,7 +94,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
index 12e34a0439b4..b6a5886698b2 100644
--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
@@ -23,50 +23,50 @@
leds {
compatible = "gpio-leds";
- 2ghz {
+ led-2ghz {
label = "bcm53xx:green:2ghz";
gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
- lan {
+ led-lan {
label = "bcm53xx:green:lan";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
};
- usb2-port1 {
+ led-usb2-port1 {
label = "bcm53xx:green:usb2-port1";
gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
linux,default-trigger = "usbport";
};
- power {
+ led-power {
label = "bcm53xx:green:power";
gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- wan-green {
+ led-wan-green {
label = "bcm53xx:green:wan";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
- wps {
+ led-wps {
label = "bcm53xx:green:wps";
gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
};
- wan-amber {
+ led-wan-amber {
label = "bcm53xx:amber:wan";
gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:green:5ghz";
gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
};
- usb2-port2 {
+ led-usb2-port2 {
label = "bcm53xx:green:usb2-port2";
gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port2>, <&ehci_port2>;
@@ -77,13 +77,13 @@
gpio-keys {
compatible = "gpio-keys";
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
@@ -95,30 +95,15 @@
status = "okay";
partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- boot@0 {
- label = "boot";
- reg = <0x000000 0x040000>;
- read-only;
- };
+ compatible = "tplink,safeloader-partitions";
+ partitions-table-offset = <0xe50000>;
- os-image@100000 {
- label = "os-image";
- reg = <0x040000 0x200000>;
+ partition-os-image {
compatible = "brcm,trx";
};
- rootfs@240000 {
- label = "rootfs";
- reg = <0x240000 0xc00000>;
- };
-
- nvram@ff0000 {
- label = "nvram";
- reg = <0xff0000 0x010000>;
+ partition-file-system {
+ linux,rootfs;
};
};
};
diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
index 7546c8d07bcd..4f44cb4df704 100644
--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
@@ -28,18 +28,18 @@
leds {
compatible = "gpio-leds";
- wps {
+ led-wps {
label = "bcm53xx:blue:wps";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
};
- power {
+ led-power {
label = "bcm53xx:blue:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- wan {
+ led-wan {
label = "bcm53xx:red:wan";
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
};
@@ -47,16 +47,14 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
index beae9eab9cb8..b7cd2faa30ce 100644
--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
@@ -28,48 +28,48 @@
leds {
compatible = "gpio-leds";
- usb {
+ led-usb {
label = "bcm53xx:green:usb";
gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
};
- power-amber {
+ led-power-amber {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
- power-white {
+ led-power-white {
label = "bcm53xx:white:power";
gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- router-amber {
+ led-router-amber {
label = "bcm53xx:amber:router";
gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
};
- router-white {
+ led-router-white {
label = "bcm53xx:white:router";
gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
};
- wan-amber {
+ led-wan-amber {
label = "bcm53xx:amber:wan";
gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
- wan-white {
+ led-wan-white {
label = "bcm53xx:white:wan";
gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
};
- wireless-amber {
+ led-wireless-amber {
label = "bcm53xx:amber:wireless";
gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
};
- wireless-white {
+ led-wireless-white {
label = "bcm53xx:white:wireless";
gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
};
@@ -77,42 +77,40 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- power {
+ button-power {
label = "Power";
linux,code = <KEY_POWER>;
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
};
- aoss {
+ button-aoss {
label = "AOSS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
};
/* Commit mode set by switch? */
- mode {
+ button-mode {
label = "Mode";
linux,code = <KEY_SETUP>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
};
/* Switch: AP mode */
- sw_ap {
+ button-sw-ap {
label = "AP";
linux,code = <BTN_0>;
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
};
- eject {
+ button-eject {
label = "USB eject";
linux,code = <KEY_EJECTCD>;
gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
index 7879f7d7d9c3..99253fd7adb3 100644
--- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
@@ -29,16 +29,14 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
index 56d309dbc6b0..24ba8f8f9bf3 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
@@ -28,43 +28,43 @@
leds {
compatible = "gpio-leds";
- power-white {
+ led-power-white {
label = "bcm53xx:white:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- power-amber {
+ led-power-amber {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:white:5ghz";
gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:white:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
- wps {
+ led-wps {
label = "bcm53xx:white:wps";
gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
};
- wireless {
+ led-wireless {
label = "bcm53xx:white:wireless";
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
};
- usb2 {
+ led-usb2 {
label = "bcm53xx:white:usb2";
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
};
@@ -72,22 +72,20 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
index 89f992af61d1..14303ab521ea 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
@@ -39,59 +39,59 @@
leds {
compatible = "gpio-leds";
- power-white {
+ led-power-white {
label = "bcm53xx:white:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- power-amber {
+ led-power-amber {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- wan-white {
+ led-wan-white {
label = "bcm53xx:white:wan";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- wan-amber {
+ led-wan-amber {
label = "bcm53xx:amber:wan";
gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
- 5ghz-1 {
+ led-5ghz-1 {
label = "bcm53xx:white:5ghz-1";
gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:white:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
- wireless {
+ led-wireless {
label = "bcm53xx:white:wireless";
gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
};
- wps {
+ led-wps {
label = "bcm53xx:white:wps";
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
};
- 5ghz-2 {
+ led-5ghz-2 {
label = "bcm53xx:white:5ghz-2";
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
};
- usb2 {
+ led-usb2 {
label = "bcm53xx:white:usb2";
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
};
@@ -99,28 +99,26 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
};
- brightness {
+ button-brightness {
label = "Backlight";
linux,code = <KEY_BRIGHTNESS_ZERO>;
gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
index c2a266a439d0..5a8b2b1567e6 100644
--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
@@ -23,27 +23,27 @@
leds {
compatible = "gpio-leds";
- lan {
+ led-lan {
label = "bcm53xx:blue:lan";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
};
- wps {
+ led-wps {
label = "bcm53xx:blue:wps";
gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:blue:usb3";
gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -51,24 +51,24 @@
linux,default-trigger = "usbport";
};
- usb2 {
+ led-usb2 {
label = "bcm53xx:blue:usb2";
gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port2>, <&ehci_port2>;
linux,default-trigger = "usbport";
};
- wan-blue {
+ led-wan-blue {
label = "bcm53xx:blue:wan";
gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
};
- wan-amber {
+ led-wan-amber {
label = "bcm53xx:amber:wan";
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
};
- power {
+ led-power {
label = "bcm53xx:blue:power";
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
@@ -77,16 +77,14 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
@@ -106,30 +104,15 @@
status = "okay";
partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- boot@0 {
- label = "boot";
- reg = <0x000000 0x040000>;
- read-only;
- };
+ compatible = "tplink,safeloader-partitions";
+ partitions-table-offset = <0xe50000>;
- os-image@100000 {
- label = "os-image";
- reg = <0x040000 0x200000>;
+ partition-os-image {
compatible = "brcm,trx";
};
- rootfs@240000 {
- label = "rootfs";
- reg = <0x240000 0xc00000>;
- };
-
- nvram@ff0000 {
- label = "nvram";
- reg = <0xff0000 0x010000>;
+ partition-file-system {
+ linux,rootfs;
};
};
};
diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
index 82f9629f0abb..a50ff686b557 100644
--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>
+ * Copyright (C) 2021-2022 Arınç ÜNAL <arinc.unal@arinc9.com>
*/
/dts-v1/;
@@ -25,42 +25,45 @@
nvram@1c080000 {
compatible = "brcm,nvram";
reg = <0x1c080000 0x00180000>;
+
+ et1macaddr: et1macaddr {
+ };
};
leds {
compatible = "gpio-leds";
- power {
+ led-power {
label = "white:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- wan-red {
+ led-wan-red {
label = "red:wan";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
- lan {
+ led-lan {
label = "white:lan";
gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
};
- usb2 {
+ led-usb2 {
label = "white:usb2";
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port2>;
linux,default-trigger = "usbport";
};
- usb3 {
+ led-usb3 {
label = "white:usb3";
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port1>, <&xhci_port1>;
linux,default-trigger = "usbport";
};
- wps {
+ led-wps {
label = "white:wps";
gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
};
@@ -69,25 +72,25 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
- wifi {
+ button-wifi {
label = "Wi-Fi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
};
- led {
+ button-led {
label = "Backlight";
linux,code = <KEY_BRIGHTNESS_ZERO>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
@@ -177,9 +180,6 @@
dsa,member = <0 0>;
ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
port@0 {
reg = <0>;
label = "lan4";
@@ -208,6 +208,7 @@
sw0_p5: port@5 {
reg = <5>;
label = "extsw";
+ phy-mode = "rgmii";
fixed-link {
speed = <1000>;
@@ -231,7 +232,6 @@
reg = <8>;
ethernet = <&gmac2>;
label = "cpu";
- status = "disabled";
fixed-link {
speed = <1000>;
@@ -241,6 +241,15 @@
};
};
+&gmac0 {
+ status = "disabled";
+};
+
+&gmac1 {
+ nvmem-cells = <&et1macaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
&usb2 {
vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index 60bfd52ee677..555fbe41dd8f 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -43,28 +43,28 @@
leds {
compatible = "gpio-leds";
- power-white {
+ led-power-white {
label = "bcm53xx:white:power";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- wan-white {
+ led-wan-white {
label = "bcm53xx:white:wan";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
};
- power-amber {
+ led-power-amber {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
};
- wan-amber {
+ led-wan-amber {
label = "bcm53xx:amber:wan";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- usb3-white {
+ led-usb3-white {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -72,12 +72,12 @@
linux,default-trigger = "usbport";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:white:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:white:5ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
@@ -86,20 +86,20 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
/* Switch: router / extender */
- extender {
+ button-extender {
label = "Extender";
linux,code = <BTN_0>;
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts
new file mode 100644
index 000000000000..d945a20b06e0
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device tree for D-Link DIR-890L
+ * D-Link calls this board "WRGAC36"
+ * this router has the same looks and form factor as D-Link DIR-885L.
+ *
+ * Some differences from DIR-885L include a separate USB2 port, separate LEDs
+ * for USB2 and USB3, a separate VCC supply for the USB2 slot and no
+ * router/extender switch is mounted (there is an empty mount point on the
+ * PCB) so this device is a pure router. Also the LAN ports are in the right
+ * order.
+ *
+ * Based on the device tree for DIR-885L
+ * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
+ * Copyright (C) 2022 Linus Walleij
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch1.dtsi"
+
+/ {
+ compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708";
+ model = "D-Link DIR-890L";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
+ };
+
+ leds {
+ /*
+ * LED information is derived from the boot log which
+ * conveniently lists all the LEDs.
+ */
+ compatible = "gpio-leds";
+
+ led-power-white {
+ label = "bcm53xx:white:power";
+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-wan-white {
+ label = "bcm53xx:white:wan";
+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+ };
+
+ led-power-amber {
+ label = "bcm53xx:amber:power";
+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+ };
+
+ led-wan-amber {
+ label = "bcm53xx:amber:wan";
+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+ };
+
+ led-usb3-white {
+ label = "bcm53xx:white:usb3";
+ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&xhci_port1>;
+ linux,default-trigger = "usbport";
+ };
+
+ led-usb2-white {
+ label = "bcm53xx:white:usb2";
+ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
+ linux,default-trigger = "usbport";
+ };
+
+ led-2ghz {
+ label = "bcm53xx:white:2ghz";
+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+ };
+
+ led-5ghz {
+ label = "bcm53xx:white:5ghz";
+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+ };
+
+ /* Called "factory reset" in the vendor dmesg */
+ button-restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ /*
+ * The flash memory is memory mapped at 0x1e000000-0x1fffffff
+ * 64KB blocks; total size 2MB, same that can be
+ * found attached to the spi_nor SPI controller.
+ */
+ nvram@1e1f0000 {
+ compatible = "brcm,nvram";
+ reg = <0x1e1f0000 0x00010000>;
+
+ et0macaddr: et0macaddr {
+ };
+ };
+};
+
+&gmac2 {
+ /*
+ * The NVRAM curiously does not contain a MAC address
+ * for et2 so since that is the only ethernet interface
+ * actually in use on the platform, we use this et0 MAC
+ * address for et2.
+ */
+ nvmem-cells = <&et0macaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&spi_nor {
+ status = "okay";
+};
+
+&nandcs {
+ /* Spansion S34ML01G2, 128MB with 128KB erase blocks */
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * This is called "nflash" in the vendor kernel with
+ * "upgrade" and "rootfs" (probably using OpenWrt
+ * splitpart). We call it "firmware" like standard tools
+ * assume. The CFE loader contains incorrect information
+ * about TRX partitions, ignore this, there are no TRX
+ * partitions: this device uses SEAMA.
+ */
+ firmware@0 {
+ label = "firmware";
+ reg = <0x00000000 0x08000000>;
+ };
+ };
+};
+
+&usb2 {
+ vcc-gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+ vcc-gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ ethernet = <&gmac2>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 9bef6b9bfa8d..d9a16a820e7f 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -30,19 +30,19 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
@@ -52,19 +52,19 @@
leds {
compatible = "gpio-leds";
- wps {
+ led-wps {
label = "bcm53xx:white:wps";
gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>;
};
- usb2 {
+ led-usb2 {
label = "bcm53xx:green:usb2";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port2>, <&ehci_port2>;
linux,default-trigger = "usbport";
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -72,58 +72,58 @@
linux,default-trigger = "usbport";
};
- power {
+ led-power {
label = "bcm53xx:white:power";
gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
- wifi-disabled {
+ led-wifi-disabled {
label = "bcm53xx:amber:wifi-disabled";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
};
- wifi-enabled {
+ led-wifi-enabled {
label = "bcm53xx:white:wifi-enabled";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
- bluebar1 {
+ led-bluebar1 {
label = "bcm53xx:white:bluebar1";
gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
};
- bluebar2 {
+ led-bluebar2 {
label = "bcm53xx:white:bluebar2";
gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
};
- bluebar3 {
+ led-bluebar3 {
label = "bcm53xx:white:bluebar3";
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
};
- bluebar4 {
+ led-bluebar4 {
label = "bcm53xx:white:bluebar4";
gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
};
- bluebar5 {
+ led-bluebar5 {
label = "bcm53xx:white:bluebar5";
gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>;
};
- bluebar6 {
+ led-bluebar6 {
label = "bcm53xx:white:bluebar6";
gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>;
};
- bluebar7 {
+ led-bluebar7 {
label = "bcm53xx:white:bluebar7";
gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>;
};
- bluebar8 {
+ led-bluebar8 {
label = "bcm53xx:white:bluebar8";
gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
index b51a0ee7e584..41a0722fa64a 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
@@ -30,13 +30,13 @@
leds {
compatible = "gpio-leds";
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
index 6fa101f0a90d..c56c7e366848 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
@@ -23,18 +23,18 @@
leds {
compatible = "gpio-leds";
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
@@ -43,7 +43,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
index b959a9504eea..1b5c91a524ac 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
@@ -30,13 +30,13 @@
leds {
compatible = "gpio-leds";
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
index b0d8a688141d..739063b77b1f 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
@@ -25,7 +25,7 @@
leds {
compatible = "gpio-leds";
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
@@ -34,10 +34,8 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
index cbe8c8e4a301..7afc68d5d2c2 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
@@ -30,38 +30,38 @@
leds {
compatible = "gpio-leds";
- power {
+ led-power {
label = "bcm53xx:green:power";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- lan3 {
+ led-lan3 {
label = "bcm53xx:green:lan3";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
};
- lan4 {
+ led-lan4 {
label = "bcm53xx:green:lan4";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
};
- wan {
+ led-wan {
label = "bcm53xx:green:wan";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- lan1 {
+ led-lan1 {
label = "bcm53xx:green:lan1";
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
- lan2 {
+ led-lan2 {
label = "bcm53xx:green:lan2";
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -69,18 +69,18 @@
linux,default-trigger = "usbport";
};
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:green:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:green:5ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
@@ -89,7 +89,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
index 9efcb2424228..60a2c441d5bd 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
@@ -33,13 +33,13 @@
leds {
compatible = "gpio-leds";
- power {
+ led-power {
label = "bcm53xx:green:power";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
@@ -47,18 +47,18 @@
linux,default-trigger = "usbport";
};
- status {
+ led-status {
label = "bcm53xx:green:status";
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:green:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:green:5ghz";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
@@ -67,7 +67,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
index 42097a4c2659..76d562610654 100644
--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
@@ -25,38 +25,38 @@
leds {
compatible = "gpio-leds";
- power0 {
+ led-power0 {
label = "bcm53xx:white:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
- power1 {
+ led-power1 {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- 5ghz-1 {
+ led-5ghz-1 {
label = "bcm53xx:white:5ghz-1";
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
- 5ghz-2 {
+ led-5ghz-2 {
label = "bcm53xx:white:5ghz-2";
gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:white:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
};
- usb2 {
+ led-usb2 {
label = "bcm53xx:white:usb2";
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
};
- usb3 {
+ led-usb3 {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
};
@@ -65,25 +65,25 @@
gpio-keys {
compatible = "gpio-keys";
- brightness {
+ button-brightness {
label = "Backlight";
linux,code = <KEY_BRIGHTNESS_ZERO>;
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
};
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
index a2566ad4619c..3bf6e24978ac 100644
--- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
@@ -22,7 +22,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
index 57ca1cfaecd8..0734aa249b8e 100644
--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
@@ -23,13 +23,13 @@
leds {
compatible = "gpio-leds";
- wlan {
+ led-wlan {
label = "bcm53xx:blue:wlan";
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
- system {
+ led-system {
label = "bcm53xx:green:system";
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
@@ -39,7 +39,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
index 2e1a7e382cb7..e6fb6cbe6963 100644
--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
@@ -20,26 +20,26 @@
reg = <0x00000000 0x08000000>;
};
- leds {
+ leds-0 {
compatible = "gpio-leds";
- 5ghz {
+ led-5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-off";
};
- system {
+ led-system {
label = "bcm53xx:green:system";
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
};
};
- pcie0_leds {
+ leds-1 {
compatible = "gpio-leds";
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-off";
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
index 07eb3a8287d6..dab2e5f63a72 100644
--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
@@ -20,37 +20,37 @@
reg = <0x00000000 0x08000000>;
};
- leds {
+ leds-0 {
compatible = "gpio-leds";
- usb {
+ led-usb {
label = "bcm53xx:blue:usb";
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
linux,default-trigger = "usbport";
};
- wps {
+ led-wps {
label = "bcm53xx:blue:wps";
gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
};
- system {
+ led-system {
label = "bcm53xx:blue:system";
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
};
};
- pcie0_leds {
+ leds-1 {
compatible = "gpio-leds";
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>;
};
@@ -59,19 +59,19 @@
gpio-keys {
compatible = "gpio-keys";
- rfkill {
+ button-rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi
new file mode 100644
index 000000000000..cd25ed2757b7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47622.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm47622", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>, <&CA7_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
new file mode 100644
index 000000000000..14f58033efeb
--- /dev/null
+++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Meraki MR26 / Codename: Venom
+ *
+ * Copyright (C) 2022 Christian Lamparter <chunkeey@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708";
+ model = "Meraki MR26";
+
+ memory@0 {
+ reg = <0x00000000 0x08000000>;
+ device_type = "memory";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+ panic-indicator;
+ };
+ led-1 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ key-restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ clock-frequency = <50000000>;
+ /delete-property/ clocks;
+};
+
+&uart1 {
+ status = "disabled";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "disabled";
+};
+&gmac2 {
+ status = "disabled";
+};
+&gmac3 {
+ status = "disabled";
+};
+
+&nandcs {
+ nand-ecc-algo = "hw";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x200000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "u-boot-env";
+ reg = <0x200000 0x200000>;
+ /* empty */
+ };
+
+ partition@400000 {
+ label = "u-boot-backup";
+ reg = <0x400000 0x200000>;
+ /* empty */
+ };
+
+ partition@600000 {
+ label = "u-boot-env-backup";
+ reg = <0x600000 0x200000>;
+ /* empty */
+ };
+
+ partition@800000 {
+ label = "ubi";
+ reg = <0x800000 0x7780000>;
+ };
+ };
+};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "poe";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_i2c>;
+
+ clock-frequency = <100000>;
+
+ ina219@40 {
+ compatible = "ti,ina219"; /* PoE power */
+ reg = <0x40>;
+ shunt-resistor = <60000>; /* = 60 mOhms */
+ };
+
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ pagesize = <32>;
+ read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* it's empty */
+ };
+};
+
+&thermal {
+ status = "disabled";
+ /* does not work, reads 418 degree Celsius */
+};
diff --git a/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts
new file mode 100644
index 000000000000..c1f54391746f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "bcm4709.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "D-Link DWL-8610AP";
+ compatible = "dlink,dwl-8610ap", "brcm,bcm53016", "brcm,bcm4708";
+
+ memory@0 {
+ device_type = "memory";
+ /* 512 MB RAM in 2 x Macronix D9PSH chips */
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-power {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-diag {
+ /* Actually "diag" unclear what this means */
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-wlan-2g {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
+ };
+
+ led-wlan-5g {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ button-reset {
+ debounce-interval = <100>;
+ wakeup-source;
+ linux,code = <KEY_RESTART>;
+ label = "reset";
+ /* This GPIO is actually stored in NVRAM, but it's not gonna change */
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ /*
+ * Flash memory at 0x1e000000-0x1fffffff
+ * Macronix 32 64KB blocks; total size 2MB, same that can be
+ * found attached to the spi_nor SPI controller.
+ */
+ nvram@1e080000 {
+ compatible = "brcm,nvram";
+ reg = <0x1e080000 0x00020000>;
+
+ et0macaddr: et0macaddr {
+ };
+
+ et1macaddr: et1macaddr {
+ };
+ };
+};
+
+&gmac0 {
+ nvmem-cells = <&et0macaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+ nvmem-cells = <&et1macaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&spi_nor {
+ /* Serial SPI NOR Flash MX 25L1606E */
+ status = "okay";
+};
+
+&nandcs {
+ /*
+ * Spansion S34ML01G100TFI00 128 MB NAND Flash memory
+ *
+ * This ECC is a bit unorthodox but it is what the stock firmware
+ * is using, so to be able to mount the original partitions
+ * this is necessary.
+ */
+ nand-ecc-strength = <5>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* This is named nflash1.trx in CFE */
+ trx@0 {
+ label = "firmware";
+ reg = <0x00000000 0x02800000>;
+ compatible = "brcm,trx";
+ };
+
+ /* This is named nflash1.trx2 in CFE */
+ trx2@2800000 {
+ label = "firmware2";
+ reg = <0x02800000 0x02800000>;
+ compatible = "brcm,trx";
+ };
+
+ /* This is named nflash1.rwfs in CFE */
+ free@5000000 {
+ label = "free";
+ reg = <0x05000000 0x03000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
index 66c64a6ec414..46c2c93b01d8 100644
--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
@@ -13,7 +13,7 @@
#include <dt-bindings/leds/common.h>
/ {
- compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708";
+ compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708";
model = "Meraki MR32";
chosen {
@@ -47,10 +47,8 @@
keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
@@ -60,7 +58,7 @@
pwm-leds {
compatible = "pwm-leds";
- red {
+ led-0 {
/* SYS-LED 1 - Tricolor */
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RED>;
@@ -68,7 +66,7 @@
max-brightness = <255>;
};
- green {
+ led-1 {
/* SYS-LED 1 - Tricolor */
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
@@ -76,7 +74,7 @@
max-brightness = <255>;
};
- blue {
+ led-2 {
/* SYS-LED 1 - Tricolor */
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_BLUE>;
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 603c700c706f..5fc1b847f4aa 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -455,7 +455,7 @@
reg = <0x180 0x4>;
};
- pinctrl: pin-controller@1c0 {
+ pinctrl: pinctrl@1c0 {
compatible = "brcm,bcm4708-pinmux";
reg = <0x1c0 0x24>;
reg-names = "cru_gpio_control";
@@ -568,9 +568,9 @@
trips {
cpu-crit {
- temperature = <125000>;
- hysteresis = <0>;
- type = "critical";
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
};
};
diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts
index 2e7fda9b998c..975f854f652f 100644
--- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts
+++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts
@@ -34,7 +34,7 @@
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "m25p80";
reg = <0>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index cca49a2e2d62..93281c47c9ba 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -9,8 +9,8 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "brcm,bcm63138";
- model = "Broadcom BCM63138 DSL SoC";
+ compatible = "brcm,bcm63138", "brcm,bcmbca";
+ model = "Broadcom BCM963138 Reference Board";
interrupt-parent = <&gic>;
aliases {
@@ -66,6 +66,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
};
/* ARM bus */
@@ -203,6 +209,18 @@
status = "disabled";
};
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
nand_controller: nand-controller@2000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi
new file mode 100644
index 000000000000..ba7f265db121
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63148.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm63148", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ B15_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b15";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B15_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b15";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B15_0>, <&B15_1>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@80030000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x80030000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xfffe8000 0x8000>;
+
+ uart0: serial@600 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x600 0x20>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi
new file mode 100644
index 000000000000..d8268a1e889b
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63178.dtsi
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm63178", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi
new file mode 100644
index 000000000000..49ecc1f0c18c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6756.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6756", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>, <&CA7_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
+ reg = <0x1000 0x600>, <0x2610 0x4>;
+ reg-names = "hsspi", "spim-ctrl";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi
new file mode 100644
index 000000000000..fbc7d3a5dc5f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6846.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6846", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x1b>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi
new file mode 100644
index 000000000000..5e0fe26530f1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6855.dtsi
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6855", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1";
+ reg = <0x1000 0x600>, <0x2610 0x4>;
+ reg-names = "hsspi", "spim-ctrl";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi
new file mode 100644
index 000000000000..96529d3d4dc2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6878.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6878", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&hsspi_pll &hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
index a76c74b44bba..363009e747b3 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -47,10 +47,10 @@
stdout-path = "serial0:115200n8";
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- hook {
+ button-hook {
label = "HOOK";
linux,code = <KEY_O>;
gpios = <&gpio_asiu 48 0>;
diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts
index b0b8c774a37f..3709baa2376f 100644
--- a/arch/arm/boot/dts/bcm947189acdbmr.dts
+++ b/arch/arm/boot/dts/bcm947189acdbmr.dts
@@ -25,17 +25,17 @@
leds {
compatible = "gpio-leds";
- wps {
+ led-wps {
label = "bcm53xx:blue:wps";
gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
};
- 5ghz {
+ led-5ghz {
label = "bcm53xx:blue:5ghz";
gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
};
- 2ghz {
+ led-2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
};
@@ -44,13 +44,13 @@
gpio-keys {
compatible = "gpio-keys";
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
};
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts
new file mode 100644
index 000000000000..93b8ce22678d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm947622.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm47622.dtsi"
+
+/ {
+ model = "Broadcom BCM947622 Reference Board";
+ compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts
index 52feca0fb906..4fe3b3653376 100644
--- a/arch/arm/boot/dts/bcm953012er.dts
+++ b/arch/arm/boot/dts/bcm953012er.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar Enterprise Router (BCM953012ER)";
- compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
+ compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708";
memory@0 {
device_type = "memory";
@@ -47,13 +47,13 @@
gpio-keys {
compatible = "gpio-keys";
- wps {
+ button-wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
};
- restart {
+ button-restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts
index 9140be7ec053..b070b69466bd 100644
--- a/arch/arm/boot/dts/bcm953012hr.dts
+++ b/arch/arm/boot/dts/bcm953012hr.dts
@@ -37,7 +37,7 @@
/ {
model = "NorthStar HR (BCM953012HR)";
- compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708";
+ compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708";
aliases {
ethernet0 = &gmac0;
diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts
index de40bd59a5fa..f1e6bcaa1edd 100644
--- a/arch/arm/boot/dts/bcm953012k.dts
+++ b/arch/arm/boot/dts/bcm953012k.dts
@@ -36,7 +36,7 @@
/ {
model = "NorthStar SVK (BCM953012K)";
- compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708";
+ compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708";
aliases {
serial0 = &uart0;
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index 60376b62cd5f..15f023656df0 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -136,7 +136,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index 8eeb319f5b54..9b9c225a1fb3 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -136,7 +136,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index dc86d5a91292..ca9311452739 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -152,7 +152,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index c457e53d886e..9db3c851451a 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -140,7 +140,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index c06871915a1c..32786e7c4e12 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -144,7 +144,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
index 58b7d9fc7574..c54451dde6dd 100644
--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
@@ -13,7 +13,7 @@
autorepeat;
poll-interval = <20>;
- reset {
+ button-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
index 576cfc52567b..1830844c8404 100644
--- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
@@ -14,7 +14,7 @@
autorepeat;
poll-interval = <20>;
- reset {
+ button-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index b22fc6624ae4..74263d98de73 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -151,7 +151,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 0183f8965a74..69ebc7a913a7 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -155,7 +155,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/bcm963138.dts
new file mode 100644
index 000000000000..1b405c249213
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963138.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63138.dtsi"
+
+/ {
+ model = "Broadcom BCM963138 Reference Board";
+ compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = &serial0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
index df5c8ab90627..b5af61853a07 100644
--- a/arch/arm/boot/dts/bcm963138dvt.dts
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -8,7 +8,7 @@
#include "bcm63138.dtsi"
/ {
- compatible = "brcm,BCM963138DVT", "brcm,bcm63138";
+ compatible = "brcm,BCM963138DVT", "brcm,bcm63138", "brcm,bcmbca";
model = "Broadcom BCM963138DVT";
chosen {
@@ -50,3 +50,7 @@
&sata_phy {
status = "okay";
};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts
new file mode 100644
index 000000000000..1f5d6d783f09
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963148.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63148.dtsi"
+
+/ {
+ model = "Broadcom BCM963148 Reference Board";
+ compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts
new file mode 100644
index 000000000000..d036e99dd8d1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963178.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63178.dtsi"
+
+/ {
+ model = "Broadcom BCM963178 Reference Board";
+ compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts
new file mode 100644
index 000000000000..8b104f3fb14a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96756.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6756.dtsi"
+
+/ {
+ model = "Broadcom BCM96756 Reference Board";
+ compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts
new file mode 100644
index 000000000000..55852c229608
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96846.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6846.dtsi"
+
+/ {
+ model = "Broadcom BCM96846 Reference Board";
+ compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/bcm96855.dts
new file mode 100644
index 000000000000..2ad880af2104
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96855.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6855.dtsi"
+
+/ {
+ model = "Broadcom BCM96855 Reference Board";
+ compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts
new file mode 100644
index 000000000000..b7af8ade7a9d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96878.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6878.dtsi"
+
+/ {
+ model = "Broadcom BCM96878 Reference Board";
+ compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&hsspi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index 007e34715956..e96bc3f2d5cf 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -140,7 +140,7 @@
&qspi {
status = "okay";
bspi-sel = <0>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 598a46f96a82..6edaefa617a5 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -581,7 +581,7 @@
status = "disabled";
};
- uart0: uart@9000 {
+ uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
interrupts = <8>;
@@ -592,7 +592,7 @@
status = "disabled";
};
- uart1: uart@a000 {
+ uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
interrupts = <9>;
diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi
index d2e8f36f8c60..227675fbe820 100644
--- a/arch/arm/boot/dts/cx92755.dtsi
+++ b/arch/arm/boot/dts/cx92755.dtsi
@@ -107,7 +107,7 @@
reg = <0xf00003a0 0x10>;
};
- uart0: uart@f0000740 {
+ uart0: serial@f0000740 {
compatible = "cnxt,cx92755-usart";
reg = <0xf0000740 0x20>;
clocks = <&main_clk>;
@@ -115,7 +115,7 @@
status = "disabled";
};
- uart1: uart@f0000760 {
+ uart1: serial@f0000760 {
compatible = "cnxt,cx92755-usart";
reg = <0xf0000760 0x20>;
clocks = <&main_clk>;
@@ -123,7 +123,7 @@
status = "disabled";
};
- uart2: uart@f0000780 {
+ uart2: serial@f0000780 {
compatible = "cnxt,cx92755-usart";
reg = <0xf0000780 0x20>;
clocks = <&main_clk>;
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 87c517d65f62..0ca849885d1f 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -52,15 +52,15 @@
enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz = <16>;
- bpp = <16>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order = <0>;
- fifo-th = <0>;
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <16>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
};
display-timings {
@@ -278,7 +278,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -415,7 +415,7 @@
&aemif {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
- status = "ok";
+ status = "okay";
cs3 {
#address-cells = <2>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index c3942b4e82ad..e46e4d22db39 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -419,7 +419,7 @@
edma0: edma@0 {
compatible = "ti,edma3-tpcc";
/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
- reg = <0x0 0x8000>;
+ reg = <0x0 0x8000>;
reg-names = "edma3_cc";
interrupts = <11 12>;
interrupt-names = "edma3_ccint", "edma3_ccerrint";
@@ -430,14 +430,14 @@
};
edma0_tptc0: tptc@8000 {
compatible = "ti,edma3-tptc";
- reg = <0x8000 0x400>;
+ reg = <0x8000 0x400>;
interrupts = <13>;
interrupt-names = "edm3_tcerrint";
power-domains = <&psc0 1>;
};
edma0_tptc1: tptc@8400 {
compatible = "ti,edma3-tptc";
- reg = <0x8400 0x400>;
+ reg = <0x8400 0x400>;
interrupts = <32>;
interrupt-names = "edm3_tcerrint";
power-domains = <&psc0 2>;
@@ -445,7 +445,7 @@
edma1: edma@230000 {
compatible = "ti,edma3-tpcc";
/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
- reg = <0x230000 0x8000>;
+ reg = <0x230000 0x8000>;
reg-names = "edma3_cc";
interrupts = <93 94>;
interrupt-names = "edma3_ccint", "edma3_ccerrint";
@@ -456,7 +456,7 @@
};
edma1_tptc0: tptc@238000 {
compatible = "ti,edma3-tptc";
- reg = <0x238000 0x400>;
+ reg = <0x238000 0x400>;
interrupts = <95>;
interrupt-names = "edm3_tcerrint";
power-domains = <&psc1 21>;
@@ -672,14 +672,16 @@
cppi41dma: dma-controller@201000 {
compatible = "ti,da830-cppi41";
- reg = <0x201000 0x1000
+ reg = <0x201000 0x1000
0x202000 0x1000
0x204000 0x4000>;
reg-names = "controller",
"scheduler", "queuemgr";
interrupts = <58>;
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <4>;
+ dma-channels = <4>;
power-domains = <&psc1 1>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts
index 8ef48c00f98d..fe3f9a970b18 100644
--- a/arch/arm/boot/dts/dm8148-evm.dts
+++ b/arch/arm/boot/dts/dm8148-evm.dts
@@ -51,7 +51,7 @@
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name= "micron,mt29f2g16aadwp";
+ linux,mtd-name = "micron,mt29f2g16aadwp";
#address-cells = <1>;
#size-cells = <1>;
ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index 7702e048e110..a8cd724ce4bc 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm814.h>
@@ -167,8 +163,11 @@
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <30>;
+ dma-channels = <30>;
#dma-requests = <256>;
+ dma-requests = <256>;
};
};
@@ -334,7 +333,7 @@
};
};
- uart1: uart@20000 {
+ uart1: serial@20000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
reg = <0x20000 0x2000>;
@@ -344,7 +343,7 @@
dma-names = "tx", "rx";
};
- uart2: uart@22000 {
+ uart2: serial@22000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
reg = <0x22000 0x2000>;
@@ -354,7 +353,7 @@
dma-names = "tx", "rx";
};
- uart3: uart@24000 {
+ uart3: serial@24000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
reg = <0x24000 0x2000>;
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 5126e2d72ed7..244a957f9ba3 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -119,7 +119,7 @@
nand@0,0 {
compatible = "ti,omap2-nand";
- linux,mtd-name= "micron,mt29f2g16aadwp";
+ linux,mtd-name = "micron,mt29f2g16aadwp";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
@@ -177,7 +177,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mcspi1_pins>;
- m25p80@0 {
+ flash@0 {
compatible = "w25x32";
spi-max-frequency = <48000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index a9e7274806f4..b68686f0643b 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm816.h>
@@ -526,7 +522,7 @@
ti,timer-pwm;
};
- uart1: uart@48020000 {
+ uart1: serial@48020000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
reg = <0x48020000 0x2000>;
@@ -536,7 +532,7 @@
dma-names = "tx", "rx";
};
- uart2: uart@48022000 {
+ uart2: serial@48022000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
reg = <0x48022000 0x2000>;
@@ -546,7 +542,7 @@
dma-names = "tx", "rx";
};
- uart3: uart@48024000 {
+ uart3: serial@48024000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
reg = <0x48024000 0x2000>;
@@ -655,8 +651,11 @@
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
+ /* For backwards compatibility: */
#dma-channels = <30>;
+ dma-channels = <30>;
#dma-requests = <256>;
+ dma-requests = <256>;
};
};
diff --git a/arch/arm/boot/dts/dove-cm-a510.dtsi b/arch/arm/boot/dts/dove-cm-a510.dtsi
index 9b9dfbe07be4..1082fdfbfe60 100644
--- a/arch/arm/boot/dts/dove-cm-a510.dtsi
+++ b/arch/arm/boot/dts/dove-cm-a510.dtsi
@@ -101,7 +101,7 @@
pinctrl-0 = <&pmx_nand_gpo>;
pinctrl-names = "default";
- system {
+ led-system {
label = "cm-a510:system:green";
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
default-state = "keep";
@@ -124,9 +124,17 @@
};
/* Optional RTL8211D GbE PHY on SMI address 0x03 */
-&ethphy {
- reg = <3>;
- status = "disabled";
+&mdio {
+ ethphy: ethernet-phy@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+};
+
+&eth {
+ ethernet-port@0 {
+ phy-handle = <&ethphy>;
+ };
};
&i2c0 {
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 3e1584e787ae..dbba0c8cdab1 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -21,7 +21,7 @@
pinctrl-0 = <&pmx_gpio_18>;
pinctrl-names = "default";
- power {
+ led-power {
label = "Power";
gpios = <&gpio0 18 1>;
default-state = "keep";
@@ -72,11 +72,18 @@
&uart0 { status = "okay"; };
&sata0 { status = "okay"; };
&mdio { status = "okay"; };
-&eth { status = "okay"; };
+&eth {
+ status = "okay";
+ ethernet-port@0 {
+ phy-handle = <&ethphy>;
+ };
+};
-&ethphy {
- compatible = "marvell,88e1310";
- reg = <1>;
+&mdio {
+ ethphy: ethernet-phy@1 {
+ compatible = "marvell,88e1310";
+ reg = <1>;
+ };
};
&gpu {
@@ -127,7 +134,7 @@
status = "okay";
/* spi0.0: 4M Flash Winbond W25Q32BV */
- spi-flash@0 {
+ flash@0 {
compatible = "st,w25q32";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts
index 273f12ca2512..79ee2b32409d 100644
--- a/arch/arm/boot/dts/dove-d2plug.dts
+++ b/arch/arm/boot/dts/dove-d2plug.dts
@@ -21,17 +21,17 @@
pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
pinctrl-names = "default";
- wlan-ap {
+ led-wlan-ap {
label = "wlan-ap";
gpios = <&gpio0 0 1>;
};
- wlan-act {
+ led-wlan-act {
label = "wlan-act";
gpios = <&gpio0 1 1>;
};
- bluetooth-act {
+ led-bluetooth-act {
label = "bt-act";
gpios = <&gpio0 2 1>;
};
@@ -62,7 +62,7 @@
status = "okay";
/* spi0.0: 4M Flash Macronix MX25L3205D */
- spi-flash@0 {
+ flash@0 {
compatible = "st,m25l3205d";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts
index 826026c28f90..5aa5d4a7d51d 100644
--- a/arch/arm/boot/dts/dove-d3plug.dts
+++ b/arch/arm/boot/dts/dove-d3plug.dts
@@ -21,17 +21,17 @@
pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
pinctrl-names = "default";
- wlan-act {
+ led-wlan-act {
label = "wlan-act";
gpios = <&gpio0 0 1>;
};
- wlan-ap {
+ led-wlan-ap {
label = "wlan-ap";
gpios = <&gpio0 1 1>;
};
- status {
+ led-status {
label = "status";
gpios = <&gpio0 2 1>;
};
@@ -79,7 +79,7 @@
status = "okay";
/* spi0.0: 2M Flash Macronix MX25L1605D */
- spi-flash@0 {
+ flash@0 {
compatible = "st,m25l1605d";
spi-max-frequency = <86000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
index 1754a62e014e..c1912dc6bfc3 100644
--- a/arch/arm/boot/dts/dove-dove-db.dts
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -27,7 +27,7 @@
status = "okay";
/* spi0.0: 4M Flash ST-M25P32-VMF6P */
- spi-flash@0 {
+ flash@0 {
compatible = "st,m25p32";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 89e0bdaf3a85..062c86361640 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -122,14 +122,24 @@
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 16>;
+ interrupt-names = "intx", "error";
+ interrupts = <16>, <15>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie1: pcie@2 {
device_type = "pci";
status = "disabled";
- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+ assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
clocks = <&gate_clk 5>;
marvell,pcie-port = <1>;
@@ -141,8 +151,18 @@
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 18>;
+ interrupt-names = "intx", "error";
+ interrupts = <18>, <17>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
@@ -362,7 +382,6 @@
interrupts = <29>;
/* overwrite MAC address in bootloader */
local-mac-address = [00 00 00 00 00 00];
- phy-handle = <&ethphy>;
};
};
@@ -374,10 +393,6 @@
interrupts = <30>;
clocks = <&gate_clk 2>;
status = "disabled";
-
- ethphy: ethernet-phy {
- /* set phy address in board file */
- };
};
sdio0: sdio-host@92000 {
@@ -407,7 +422,7 @@
clocks = <&gate_clk 3>;
clock-names = "sata";
#phy-cells = <0>;
- status = "ok";
+ status = "okay";
};
audio0: audio-controller@b0000 {
diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts
index c16e183822be..577114c4c20a 100644
--- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts
+++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts
@@ -51,7 +51,7 @@
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name= "micron,mt29f2g16aadwp";
+ linux,mtd-name = "micron,mt29f2g16aadwp";
#address-cells = <1>;
#size-cells = <1>;
ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/dra62x.dtsi
index cc4878aaa8ea..cfefa670515c 100644
--- a/arch/arm/boot/dts/dra62x.dtsi
+++ b/arch/arm/boot/dts/dra62x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include "dm814x.dtsi"
diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
index e75569383dd8..747ff0db90c7 100644
--- a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
+++ b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for DRA7x SoC DSPEVE thermal
*
* Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi
index 0f71a9f37a72..4cdffd6db740 100644
--- a/arch/arm/boot/dts/dra7-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra7-evm-common.dtsi
@@ -135,7 +135,7 @@
status = "okay";
spi-max-frequency = <76800000>;
- m25p80@0 {
+ flash@0 {
compatible = "s25fl256s1";
spi-max-frequency = <76800000>;
reg = <0>;
@@ -151,7 +151,7 @@
*/
partition@0 {
label = "QSPI.SPL";
- reg = <0x00000000 0x000010000>;
+ reg = <0x00000000 0x00010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 87deb6a76eff..8cbcf55a5a33 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -483,7 +483,7 @@
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
- reg = <0x00000000 0x000020000>;
+ reg = <0x00000000 0x00020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi
index a7077321613f..0a31313065df 100644
--- a/arch/arm/boot/dts/dra7-iva-thermal.dtsi
+++ b/arch/arm/boot/dts/dra7-iva-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for DRA7x SoC IVA thermal
*
* Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 0a11bacffc1f..5733e3a4ea8e 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -4188,11 +4188,11 @@
reg = <0x1d0010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
+ <SYSC_IDLE_NO>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
+ power-domains = <&prm_vpe>;
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index f12825268188..c79ba671ec2b 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -356,7 +356,7 @@
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
- reg = <0x00000000 0x000020000>;
+ reg = <0x00000000 0x00020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
@@ -474,7 +474,7 @@
status = "okay";
spi-max-frequency = <76800000>;
- m25p80@0 {
+ flash@0 {
compatible = "s25fl256s1";
spi-max-frequency = <76800000>;
reg = <0>;
@@ -490,7 +490,7 @@
*/
partition@0 {
label = "QSPI.SPL";
- reg = <0x00000000 0x000010000>;
+ reg = <0x00000000 0x00010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
index a9dce919d443..34eea3c048bd 100644
--- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
+++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
*
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/*
diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
index e86da7a970b6..b9d040135c5f 100644
--- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
+++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
*
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
/*
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index e2b7fcb061cf..57868ac60d29 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -511,7 +511,7 @@
&qspi {
spi-max-frequency = <96000000>;
- m25p80@0 {
+ flash@0 {
spi-max-frequency = <96000000>;
};
};
diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
index bc4ae91cba16..931db7932c11 100644
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -90,8 +90,8 @@
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
reg = <0x03fc>;
- ti,bit-shift=<20>;
- ti,latch-bit=<26>;
+ ti,bit-shift = <20>;
+ ti,latch-bit = <26>;
assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
assigned-clock-rates = <80000000>;
};
@@ -102,7 +102,7 @@
clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
reg = <0x3fc>;
ti,bit-shift = <29>;
- ti,latch-bit=<26>;
+ ti,latch-bit = <26>;
assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
};
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 2365554eef3c..04a7a6d1d529 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -5,210 +5,244 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&cm_core_aon_clocks {
- atl_clkin0_ck: atl_clkin0_ck {
+ atl_clkin0_ck: clock-atl-clkin0 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin0_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin1_ck: atl_clkin1_ck {
+ atl_clkin1_ck: clock-atl-clkin1 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin1_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin2_ck: atl_clkin2_ck {
+ atl_clkin2_ck: clock-atl-clkin2 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin2_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- atl_clkin3_ck: atl_clkin3_ck {
+ atl_clkin3_ck: clock-atl-clkin3 {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
+ clock-output-names = "atl_clkin3_ck";
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
- hdmi_clkin_ck: hdmi_clkin_ck {
+ hdmi_clkin_ck: clock-hdmi-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "hdmi_clkin_ck";
clock-frequency = <0>;
};
- mlb_clkin_ck: mlb_clkin_ck {
+ mlb_clkin_ck: clock-mlb-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "mlb_clkin_ck";
clock-frequency = <0>;
};
- mlbp_clkin_ck: mlbp_clkin_ck {
+ mlbp_clkin_ck: clock-mlbp-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "mlbp_clkin_ck";
clock-frequency = <0>;
};
- pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ pciesref_acs_clk_ck: clock-pciesref-acs {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pciesref_acs_clk_ck";
clock-frequency = <100000000>;
};
- ref_clkin0_ck: ref_clkin0_ck {
+ ref_clkin0_ck: clock-ref-clkin0 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin0_ck";
clock-frequency = <0>;
};
- ref_clkin1_ck: ref_clkin1_ck {
+ ref_clkin1_ck: clock-ref-clkin1 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin1_ck";
clock-frequency = <0>;
};
- ref_clkin2_ck: ref_clkin2_ck {
+ ref_clkin2_ck: clock-ref-clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin2_ck";
clock-frequency = <0>;
};
- ref_clkin3_ck: ref_clkin3_ck {
+ ref_clkin3_ck: clock-ref-clkin3 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "ref_clkin3_ck";
clock-frequency = <0>;
};
- rmii_clk_ck: rmii_clk_ck {
+ rmii_clk_ck: clock-rmii {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "rmii_clk_ck";
clock-frequency = <0>;
};
- sdvenc_clkin_ck: sdvenc_clkin_ck {
+ sdvenc_clkin_ck: clock-sdvenc-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sdvenc_clkin_ck";
clock-frequency = <0>;
};
- secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ secure_32k_clk_src_ck: clock-secure-32k-clk-src {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
- sys_clk32_crystal_ck: sys_clk32_crystal_ck {
+ sys_clk32_crystal_ck: clock-sys-clk32-crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_clk32_crystal_ck";
clock-frequency = <32768>;
};
- sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+ sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "sys_clk32_pseudo_ck";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <610>;
};
- virt_12000000_ck: virt_12000000_ck {
+ virt_12000000_ck: clock-virt-12000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
- virt_13000000_ck: virt_13000000_ck {
+ virt_13000000_ck: clock-virt-13000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
- virt_16800000_ck: virt_16800000_ck {
+ virt_16800000_ck: clock-virt-16800000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
- virt_19200000_ck: virt_19200000_ck {
+ virt_19200000_ck: clock-virt-19200000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
- virt_20000000_ck: virt_20000000_ck {
+ virt_20000000_ck: clock-virt-20000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_20000000_ck";
clock-frequency = <20000000>;
};
- virt_26000000_ck: virt_26000000_ck {
+ virt_26000000_ck: clock-virt-26000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
- virt_27000000_ck: virt_27000000_ck {
+ virt_27000000_ck: clock-virt-27000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
- virt_38400000_ck: virt_38400000_ck {
+ virt_38400000_ck: clock-virt-38400000 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
- sys_clkin2: sys_clkin2 {
+ sys_clkin2: clock-sys-clkin2 {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_clkin2";
clock-frequency = <22579200>;
};
- usb_otg_clkin_ck: usb_otg_clkin_ck {
+ usb_otg_clkin_ck: clock-usb-otg-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "usb_otg_clkin_ck";
clock-frequency = <0>;
};
- video1_clkin_ck: video1_clkin_ck {
+ video1_clkin_ck: clock-video1-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video1_clkin_ck";
clock-frequency = <0>;
};
- video1_m2_clkin_ck: video1_m2_clkin_ck {
+ video1_m2_clkin_ck: clock-video1-m2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video1_m2_clkin_ck";
clock-frequency = <0>;
};
- video2_clkin_ck: video2_clkin_ck {
+ video2_clkin_ck: clock-video2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video2_clkin_ck";
clock-frequency = <0>;
};
- video2_m2_clkin_ck: video2_m2_clkin_ck {
+ video2_m2_clkin_ck: clock-video2-m2-clkin {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "video2_m2_clkin_ck";
clock-frequency = <0>;
};
- dpll_abe_ck: dpll_abe_ck@1e0 {
+ dpll_abe_ck: clock@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
- dpll_abe_x2_ck: dpll_abe_x2_ck {
+ dpll_abe_x2_ck: clock-dpll-abe-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
};
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
+ dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -217,18 +251,20 @@
ti,invert-autoidle-bit;
};
- abe_clk: abe_clk@108 {
+ abe_clk: clock-abe@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
ti,index-power-of-two;
};
- dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
+ dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2_ck";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -237,9 +273,10 @@
ti,invert-autoidle-bit;
};
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
+ dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -248,30 +285,34 @@
ti,invert-autoidle-bit;
};
- dpll_core_byp_mux: dpll_core_byp_mux@12c {
+ dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_core_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
};
- dpll_core_ck: dpll_core_ck@120 {
+ dpll_core_ck: clock@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
- dpll_core_x2_ck: dpll_core_x2_ck {
+ dpll_core_x2_ck: clock-dpll-core-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
- dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
+ dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h12x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -280,24 +321,27 @@
ti,invert-autoidle-bit;
};
- mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_mpu_ck: dpll_mpu_ck@160 {
+ dpll_mpu_ck: clock@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
+ dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -306,42 +350,47 @@
ti,invert-autoidle-bit;
};
- mpu_dclk_div: mpu_dclk_div {
+ mpu_dclk_div: clock-mpu-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dclk_div";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dsp_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
+ dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_dsp_byp_mux";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0240>;
};
- dpll_dsp_ck: dpll_dsp_ck@234 {
+ dpll_dsp_ck: clock@234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_dsp_ck";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
assigned-clocks = <&dpll_dsp_ck>;
assigned-clock-rates = <600000000>;
};
- dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
+ dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_dsp_m2_ck";
clocks = <&dpll_dsp_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -352,34 +401,38 @@
assigned-clock-rates = <600000000>;
};
- iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
+ dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_iva_byp_mux";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
};
- dpll_iva_ck: dpll_iva_ck@1a0 {
+ dpll_iva_ck: clock@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
assigned-clock-rates = <1165000000>;
};
- dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
+ dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m2_ck";
clocks = <&dpll_iva_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -390,34 +443,38 @@
assigned-clock-rates = <388333334>;
};
- iva_dclk: iva_dclk {
+ iva_dclk: clock-iva-dclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dclk";
clocks = <&dpll_iva_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
+ dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gpu_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02e4>;
};
- dpll_gpu_ck: dpll_gpu_ck@2d8 {
+ dpll_gpu_ck: clock@2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_gpu_ck";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
assigned-clocks = <&dpll_gpu_ck>;
assigned-clock-rates = <1277000000>;
};
- dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
+ dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gpu_m2_ck";
clocks = <&dpll_gpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -428,9 +485,10 @@
assigned-clock-rates = <425666667>;
};
- dpll_core_m2_ck: dpll_core_m2_ck@130 {
+ dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -439,32 +497,36 @@
ti,invert-autoidle-bit;
};
- core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "core_dpll_out_dclk_div";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
+ dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_ddr_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x021c>;
};
- dpll_ddr_ck: dpll_ddr_ck@210 {
+ dpll_ddr_ck: clock@210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_ddr_ck";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
+ dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
clocks = <&dpll_ddr_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -473,24 +535,27 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
+ dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gmac_byp_mux";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};
- dpll_gmac_ck: dpll_gmac_ck@2a8 {
+ dpll_gmac_ck: clock@2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_gmac_ck";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
- dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
+ dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_m2_ck";
clocks = <&dpll_gmac_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -499,72 +564,81 @@
ti,invert-autoidle-bit;
};
- video2_dclk_div: video2_dclk_div {
+ video2_dclk_div: clock-video2-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_dclk_div";
clocks = <&video2_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video1_dclk_div: video1_dclk_div {
+ video1_dclk_div: clock-video1-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_dclk_div";
clocks = <&video1_m2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- hdmi_dclk_div: hdmi_dclk_div {
+ hdmi_dclk_div: clock-hdmi-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_dclk_div";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
};
- eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "eve_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
+ dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_eve_byp_mux";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x0290>;
};
- dpll_eve_ck: dpll_eve_ck@284 {
+ dpll_eve_ck: clock@284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_eve_ck";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
- dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
+ dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_eve_m2_ck";
clocks = <&dpll_eve_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -573,17 +647,19 @@
ti,invert-autoidle-bit;
};
- eve_dclk_div: eve_dclk_div {
+ eve_dclk_div: clock-eve-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "eve_dclk_div";
clocks = <&dpll_eve_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
+ dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h13x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -592,9 +668,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
+ dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h14x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -603,9 +680,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
+ dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h22x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -614,9 +692,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
+ dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h23x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -625,9 +704,10 @@
ti,invert-autoidle-bit;
};
- dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
+ dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h24x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -636,15 +716,17 @@
ti,invert-autoidle-bit;
};
- dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_ddr_x2_ck";
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
+ dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_h11x2_ck";
clocks = <&dpll_ddr_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -653,15 +735,17 @@
ti,invert-autoidle-bit;
};
- dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_dsp_x2_ck";
clocks = <&dpll_dsp_ck>;
};
- dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
+ dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_dsp_m3x2_ck";
clocks = <&dpll_dsp_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -672,15 +756,17 @@
assigned-clock-rates = <400000000>;
};
- dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_gmac_x2_ck";
clocks = <&dpll_gmac_ck>;
};
- dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
+ dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h11x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -689,9 +775,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
+ dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h12x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -700,9 +787,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
+ dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_h13x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -711,9 +799,10 @@
ti,invert-autoidle-bit;
};
- dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
+ dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_gmac_m3x2_ck";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -722,33 +811,37 @@
ti,invert-autoidle-bit;
};
- gmii_m_clk_div: gmii_m_clk_div {
+ gmii_m_clk_div: clock-gmii-m-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gmii_m_clk_div";
clocks = <&dpll_gmac_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- hdmi_clk2_div: hdmi_clk2_div {
+ hdmi_clk2_div: clock-hdmi-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_clk2_div";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- hdmi_div_clk: hdmi_div_clk {
+ hdmi_div_clk: clock-hdmi-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "hdmi_div_clk";
clocks = <&hdmi_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- l3_iclk_div: l3_iclk_div@100 {
+ l3_iclk_div: clock-l3-iclk-div-4@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_iclk_div";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x0100>;
@@ -756,374 +849,420 @@
ti,index-power-of-two;
};
- l4_root_clk_div: l4_root_clk_div {
+ l4_root_clk_div: clock-l4-root-clk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l4_root_clk_div";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- video1_clk2_div: video1_clk2_div {
+ video1_clk2_div: clock-video1-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_clk2_div";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video1_div_clk: video1_div_clk {
+ video1_div_clk: clock-video1-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video1_div_clk";
clocks = <&video1_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video2_clk2_div: video2_clk2_div {
+ video2_clk2_div: clock-video2-clk2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_clk2_div";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- video2_div_clk: video2_div_clk {
+ video2_div_clk: clock-video2-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "video2_div_clk";
clocks = <&video2_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dummy_ck: dummy_ck {
+ dummy_ck: clock-dummy {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
&prm_clocks {
- sys_clkin1: sys_clkin1@110 {
+ sys_clkin1: clock-sys-clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin1";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
- abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
+ abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_sys_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
+ abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
- abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
+ abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_clk_mux";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
- abe_24m_fclk: abe_24m_fclk@11c {
+ abe_24m_fclk: clock-abe-24m@11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x011c>;
ti,dividers = <8>, <16>;
};
- aess_fclk: aess_fclk@178 {
+ aess_fclk: clock-aess@178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "aess_fclk";
clocks = <&abe_clk>;
reg = <0x0178>;
ti,max-div = <2>;
};
- abe_giclk_div: abe_giclk_div@174 {
+ abe_giclk_div: clock-abe-giclk-div@174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_giclk_div";
clocks = <&aess_fclk>;
reg = <0x0174>;
ti,max-div = <2>;
};
- abe_lp_clk_div: abe_lp_clk_div@1d8 {
+ abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_lp_clk_div";
clocks = <&dpll_abe_m2x2_ck>;
reg = <0x01d8>;
ti,dividers = <16>, <32>;
};
- abe_sys_clk_div: abe_sys_clk_div@120 {
+ abe_sys_clk_div: clock-abe-sys-clk-div@120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_sys_clk_div";
clocks = <&sys_clkin1>;
reg = <0x0120>;
ti,max-div = <2>;
};
- adc_gfclk_mux: adc_gfclk_mux@1dc {
+ adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "adc_gfclk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
- sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
+ sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sys_clk1_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c8>;
ti,index-power-of-two;
};
- sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
+ sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sys_clk2_dclk_div";
clocks = <&sys_clkin2>;
ti,max-div = <64>;
reg = <0x01cc>;
ti,index-power-of-two;
};
- per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
+ per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_x1_dclk_div";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x01bc>;
ti,index-power-of-two;
};
- dsp_gclk_div: dsp_gclk_div@18c {
+ dsp_gclk_div: clock-dsp-gclk-div@18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dsp_gclk_div";
clocks = <&dpll_dsp_m2_ck>;
ti,max-div = <64>;
reg = <0x018c>;
ti,index-power-of-two;
};
- gpu_dclk: gpu_dclk@1a0 {
+ gpu_dclk: clock-gpu-dclk@1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gpu_dclk";
clocks = <&dpll_gpu_m2_ck>;
ti,max-div = <64>;
reg = <0x01a0>;
ti,index-power-of-two;
};
- emif_phy_dclk_div: emif_phy_dclk_div@190 {
+ emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "emif_phy_dclk_div";
clocks = <&dpll_ddr_m2_ck>;
ti,max-div = <64>;
reg = <0x0190>;
ti,index-power-of-two;
};
- gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
+ gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "gmac_250m_dclk_div";
clocks = <&dpll_gmac_m2_ck>;
ti,max-div = <64>;
reg = <0x019c>;
ti,index-power-of-two;
};
- gmac_main_clk: gmac_main_clk {
+ gmac_main_clk: clock-gmac-main {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gmac_main_clk";
clocks = <&gmac_250m_dclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
- l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
+ l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_480m_dclk_div";
clocks = <&dpll_usb_m2_ck>;
ti,max-div = <64>;
reg = <0x01ac>;
ti,index-power-of-two;
};
- usb_otg_dclk_div: usb_otg_dclk_div@184 {
+ usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "usb_otg_dclk_div";
clocks = <&usb_otg_clkin_ck>;
ti,max-div = <64>;
reg = <0x0184>;
ti,index-power-of-two;
};
- sata_dclk_div: sata_dclk_div@1c0 {
+ sata_dclk_div: clock-sata-dclk-div@1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "sata_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x01c0>;
ti,index-power-of-two;
};
- pcie2_dclk_div: pcie2_dclk_div@1b8 {
+ pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "pcie2_dclk_div";
clocks = <&dpll_pcie_ref_m2_ck>;
ti,max-div = <64>;
reg = <0x01b8>;
ti,index-power-of-two;
};
- pcie_dclk_div: pcie_dclk_div@1b4 {
+ pcie_dclk_div: clock-pcie-dclk-div@1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "pcie_dclk_div";
clocks = <&apll_pcie_m2_ck>;
ti,max-div = <64>;
reg = <0x01b4>;
ti,index-power-of-two;
};
- emu_dclk_div: emu_dclk_div@194 {
+ emu_dclk_div: clock-emu-dclk-div@194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "emu_dclk_div";
clocks = <&sys_clkin1>;
ti,max-div = <64>;
reg = <0x0194>;
ti,index-power-of-two;
};
- secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
+ secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "secure_32k_dclk_div";
clocks = <&secure_32k_clk_src_ck>;
ti,max-div = <64>;
reg = <0x01c4>;
ti,index-power-of-two;
};
- clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
+ clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux0_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
- clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
+ clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux1_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
- clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
+ clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "clkoutmux2_clk_mux";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0160>;
};
- custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "custefuse_sys_gfclk_div";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <2>;
};
- eve_clk: eve_clk@180 {
+ eve_clk: clock-eve@180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "eve_clk";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
- hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
+ hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "hdmi_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
- mlb_clk: mlb_clk@134 {
+ mlb_clk: clock-mlb@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "mlb_clk";
clocks = <&mlb_clkin_ck>;
ti,max-div = <64>;
reg = <0x0134>;
ti,index-power-of-two;
};
- mlbp_clk: mlbp_clk@130 {
+ mlbp_clk: clock-mlbp@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "mlbp_clk";
clocks = <&mlbp_clkin_ck>;
ti,max-div = <64>;
reg = <0x0130>;
ti,index-power-of-two;
};
- per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
+ per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_x1_gfclk2_div";
clocks = <&dpll_abe_m2_ck>;
ti,max-div = <64>;
reg = <0x0138>;
ti,index-power-of-two;
};
- timer_sys_clk_div: timer_sys_clk_div@144 {
+ timer_sys_clk_div: clock-timer-sys-clk-div@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "timer_sys_clk_div";
clocks = <&sys_clkin1>;
reg = <0x0144>;
ti,max-div = <2>;
};
- video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
+ video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "video1_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
- video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
+ video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "video2_dpll_clk_mux";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
- wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
+ wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wkupaon_iclk_mux";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
};
&cm_core_clocks {
- dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
+ dpll_pcie_ref_ck: clock@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_pcie_ref_ck";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
- dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
+ dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_pcie_ref_m2ldo_ck";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1132,23 +1271,26 @@
ti,invert-autoidle-bit;
};
- apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
compatible = "ti,mux-clock";
+ clock-output-names = "apll_pcie_in_clk_mux";
clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
};
- apll_pcie_ck: apll_pcie_ck@21c {
+ apll_pcie_ck: clock@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
+ clock-output-names = "apll_pcie_ck";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
};
- optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
compatible = "ti,divider-clock";
+ clock-output-names = "optfclk_pciephy_div";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
@@ -1157,48 +1299,54 @@
ti,max-div = <2>;
};
- apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_clkvcoldo";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_clkvcoldo_div";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- apll_pcie_m2_ck: apll_pcie_m2_ck {
+ apll_pcie_m2_ck: clock-apll-pcie-m2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "apll_pcie_m2_ck";
clocks = <&apll_pcie_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_per_byp_mux: dpll_per_byp_mux@14c {
+ dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_per_byp_mux";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
};
- dpll_per_ck: dpll_per_ck@140 {
+ dpll_per_ck: clock@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: dpll_per_m2_ck@150 {
+ dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1207,32 +1355,36 @@
ti,invert-autoidle-bit;
};
- func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_aon_dclk_div";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
+ dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_usb_byp_mux";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
};
- dpll_usb_ck: dpll_usb_ck@180 {
+ dpll_usb_ck: clock@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
- dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
+ dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -1241,9 +1393,10 @@
ti,invert-autoidle-bit;
};
- dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
+ dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_pcie_ref_m2_ck";
clocks = <&dpll_pcie_ref_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -1252,15 +1405,17 @@
ti,invert-autoidle-bit;
};
- dpll_per_x2_ck: dpll_per_x2_ck {
+ dpll_per_x2_ck: clock-dpll-per-x2 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
};
- dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
+ dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h11x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1269,9 +1424,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
+ dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h12x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1280,9 +1436,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
+ dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h13x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1291,9 +1448,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
+ dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h14x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
@@ -1302,9 +1460,10 @@
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
+ dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -1313,105 +1472,118 @@
ti,invert-autoidle-bit;
};
- dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
};
- func_128m_clk: func_128m_clk {
+ func_128m_clk: clock-func-128m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_128m_clk";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- func_12m_fclk: func_12m_fclk {
+ func_12m_fclk: clock-func-12m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
- func_24m_clk: func_24m_clk {
+ func_24m_clk: clock-func-24m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- func_48m_fclk: func_48m_fclk {
+ func_48m_fclk: clock-func-48m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
- func_96m_fclk: func_96m_fclk {
+ func_96m_fclk: clock-func-96m-fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
- l3init_60m_fclk: l3init_60m_fclk@104 {
+ l3init_60m_fclk: clock-l3init-60m@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
};
- clkout2_clk: clkout2_clk@6b0 {
+ clkout2_clk: clock-clkout2-8@6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_clk";
clocks = <&clkoutmux2_clk_mux>;
ti,bit-shift = <8>;
reg = <0x06b0>;
};
- l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
+ l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "l3init_960m_gfclk";
clocks = <&dpll_usb_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x06c0>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
+ usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy1_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
};
- usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
+ usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy2_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0688>;
};
- usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
+ usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy3_always_on_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0698>;
};
- gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
+ gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_core_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
@@ -1419,9 +1591,10 @@
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
+ gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_hyd_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
@@ -1429,34 +1602,38 @@
assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
- l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
+ l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3instr_ts_gclk_div";
clocks = <&wkupaon_iclk_mux>;
ti,bit-shift = <24>;
reg = <0x0e50>;
ti,dividers = <8>, <16>, <32>;
};
- vip1_gclk_mux: vip1_gclk_mux@1020 {
+ vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip1_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1020>;
};
- vip2_gclk_mux: vip2_gclk_mux@1028 {
+ vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip2_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1028>;
};
- vip3_gclk_mux: vip3_gclk_mux@1030 {
+ vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "vip3_gclk_mux";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
ti,bit-shift = <24>;
reg = <0x1030>;
@@ -1464,48 +1641,54 @@
};
&cm_core_clockdomains {
- coreaon_clkdm: coreaon_clkdm {
+ coreaon_clkdm: clock-coreaon-clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "coreaon_clkdm";
clocks = <&dpll_usb_ck>;
};
};
&scm_conf_clocks {
- dss_deshdcp_clk: dss_deshdcp_clk@558 {
+ dss_deshdcp_clk: clock-dss-deshdcp-0@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "dss_deshdcp_clk";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
+ ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <20>;
reg = <0x0558>;
};
- ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
+ ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <21>;
reg = <0x0558>;
};
- ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
+ ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
clocks = <&l4_root_clk_div>;
ti,bit-shift = <22>;
reg = <0x0558>;
};
- sys_32k_ck: sys_32k_ck {
+ sys_32k_ck: clock-sys-32k {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_32k_ck";
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
ti,bit-shift = <8>;
reg = <0x6c4>;
@@ -1513,97 +1696,110 @@
};
&cm_core_aon {
- mpu_cm: mpu-cm@300 {
+ mpu_cm: clock@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x300 0x100>;
- mpu_clkctrl: mpu-clkctrl@20 {
+ mpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- dsp1_cm: dsp1-cm@400 {
+ dsp1_cm: clock@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp1_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- dsp1_clkctrl: dsp1-clkctrl@20 {
+ dsp1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- ipu_cm: ipu-cm@500 {
+ ipu_cm: clock@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
- ipu1_clkctrl: ipu1-clkctrl@20 {
+ ipu1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
- ipu_clkctrl: ipu-clkctrl@50 {
+ ipu_clkctrl: clock@50 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu_clkctrl";
reg = <0x50 0x34>;
#clock-cells = <2>;
};
};
- dsp2_cm: dsp2-cm@600 {
+ dsp2_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp2_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- dsp2_clkctrl: dsp2-clkctrl@20 {
+ dsp2_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- rtc_cm: rtc-cm@700 {
+ rtc_cm: clock@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "rtc_cm";
reg = <0x700 0x60>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x60>;
- rtc_clkctrl: rtc-clkctrl@20 {
+ rtc_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "rtc_clkctrl";
reg = <0x20 0x28>;
#clock-cells = <2>;
};
};
- vpe_cm: vpe-cm@760 {
+ vpe_cm: clock@760 {
compatible = "ti,omap4-cm";
+ clock-output-names = "vpe_cm";
reg = <0x760 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x760 0xc>;
- vpe_clkctrl: vpe-clkctrl@0 {
+ vpe_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "vpe_clkctrl";
reg = <0x0 0xc>;
#clock-cells = <2>;
};
@@ -1612,212 +1808,242 @@
};
&cm_core {
- coreaon_cm: coreaon-cm@600 {
+ coreaon_cm: clock@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "coreaon_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- coreaon_clkctrl: coreaon-clkctrl@20 {
+ coreaon_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "coreaon_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
};
- l3main1_cm: l3main1-cm@700 {
+ l3main1_cm: clock@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
- l3main1_clkctrl: l3main1-clkctrl@20 {
+ l3main1_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main1_clkctrl";
reg = <0x20 0x74>;
#clock-cells = <2>;
};
};
- ipu2_cm: ipu2-cm@900 {
+ ipu2_cm: clock@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu2_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- ipu2_clkctrl: ipu2-clkctrl@20 {
+ ipu2_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- dma_cm: dma-cm@a00 {
+ dma_cm: clock@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
- dma_clkctrl: dma-clkctrl@20 {
+ dma_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- emif_cm: emif-cm@b00 {
+ emif_cm: clock@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xb00 0x100>;
- emif_clkctrl: emif-clkctrl@20 {
+ emif_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- atl_cm: atl-cm@c00 {
+ atl_cm: clock@c00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "atl_cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xc00 0x100>;
- atl_clkctrl: atl-clkctrl@0 {
+ atl_clkctrl: clock@0 {
compatible = "ti,clkctrl";
+ clock-output-names = "atl_clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- l4cfg_cm: l4cfg-cm@d00 {
+ l4cfg_cm: clock@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd00 0x100>;
- l4cfg_clkctrl: l4cfg-clkctrl@20 {
+ l4cfg_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4cfg_clkctrl";
reg = <0x20 0x84>;
#clock-cells = <2>;
};
};
- l3instr_cm: l3instr-cm@e00 {
+ l3instr_cm: clock@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe00 0x100>;
- l3instr_clkctrl: l3instr-clkctrl@20 {
+ l3instr_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3instr_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- iva_cm: iva-cm@f00 {
+ iva_cm: clock@f00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "iva_cm";
reg = <0xf00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf00 0x100>;
- iva_clkctrl: iva-clkctrl@20 {
+ iva_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "iva_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- cam_cm: cam-cm@1000 {
+ cam_cm: clock@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "cam_cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x100>;
- cam_clkctrl: cam-clkctrl@20 {
+ cam_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "cam_clkctrl";
reg = <0x20 0x2c>;
#clock-cells = <2>;
};
};
- dss_cm: dss-cm@1100 {
+ dss_cm: clock@1100 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dss_cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1100 0x100>;
- dss_clkctrl: dss-clkctrl@20 {
+ dss_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
};
- gpu_cm: gpu-cm@1200 {
+ gpu_cm: clock@1200 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gpu_cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1200 0x100>;
- gpu_clkctrl: gpu-clkctrl@20 {
+ gpu_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
- l3init_cm: l3init-cm@1300 {
+ l3init_cm: clock@1300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3init_cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1300 0x100>;
- l3init_clkctrl: l3init-clkctrl@20 {
+ l3init_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3init_clkctrl";
reg = <0x20 0x6c>, <0xe0 0x14>;
#clock-cells = <2>;
};
- pcie_clkctrl: pcie-clkctrl@b0 {
+ pcie_clkctrl: clock@b0 {
compatible = "ti,clkctrl";
+ clock-output-names = "pcie_clkctrl";
reg = <0xb0 0xc>;
#clock-cells = <2>;
};
- gmac_clkctrl: gmac-clkctrl@d0 {
+ gmac_clkctrl: clock@d0 {
compatible = "ti,clkctrl";
+ clock-output-names = "gmac_clkctrl";
reg = <0xd0 0x4>;
#clock-cells = <2>;
};
};
- l4per_cm: l4per-cm@1700 {
+ l4per_cm: clock@1700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4per_cm";
reg = <0x1700 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1700 0x300>;
- l4per_clkctrl: l4per-clkctrl@28 {
+ l4per_clkctrl: clock@28 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per_clkctrl";
reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
#clock-cells = <2>;
@@ -1825,20 +2051,23 @@
assigned-clock-parents = <&abe_24m_fclk>;
};
- l4sec_clkctrl: l4sec-clkctrl@1a0 {
+ l4sec_clkctrl: clock@1a0 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4sec_clkctrl";
reg = <0x1a0 0x2c>;
#clock-cells = <2>;
};
- l4per2_clkctrl: l4per2-clkctrl@c {
+ l4per2_clkctrl: clock@c {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per2_clkctrl";
reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
#clock-cells = <2>;
};
- l4per3_clkctrl: l4per3-clkctrl@14 {
+ l4per3_clkctrl: clock@14 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4per3_clkctrl";
reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
#clock-cells = <2>;
};
@@ -1847,15 +2076,17 @@
};
&prm {
- wkupaon_cm: wkupaon-cm@1800 {
+ wkupaon_cm: clock@1800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkupaon_cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1800 0x100>;
- wkupaon_clkctrl: wkupaon-clkctrl@20 {
+ wkupaon_clkctrl: clock@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "wkupaon_clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi
index 1a49f15f2df2..dd03e3860f97 100644
--- a/arch/arm/boot/dts/e60k02.dtsi
+++ b/arch/arm/boot/dts/e60k02.dtsi
@@ -22,14 +22,14 @@
gpio_keys: gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- cover {
+ key-cover {
label = "Cover";
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
@@ -104,7 +104,16 @@
clock-frequency = <100000>;
status = "okay";
- /* TODO: CYTTSP5 touch controller at 0x24 */
+ touchscreen@24 {
+ compatible = "cypress,tt21000";
+ reg = <0x24>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cyttsp5_gpio>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&ldo5_reg>;
+ };
/* TODO: TPS65185 PMIC for E Ink at 0x68 */
@@ -302,6 +311,7 @@
&usbotg1 {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
disable-over-current;
srp-disable;
hnp-disable;
diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/e70k02.dtsi
index 156de653f2cd..4e1bf080eaca 100644
--- a/arch/arm/boot/dts/e70k02.dtsi
+++ b/arch/arm/boot/dts/e70k02.dtsi
@@ -26,14 +26,14 @@
gpio_keys: gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- cover {
+ key-cover {
label = "Cover";
gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
@@ -41,13 +41,13 @@
wakeup-source;
};
- pageup {
+ key-pageup {
label = "PageUp";
gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PAGEUP>;
};
- pagedown {
+ key-pagedown {
label = "PageDown";
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PAGEDOWN>;
@@ -122,7 +122,16 @@
clock-frequency = <100000>;
status = "okay";
- /* TODO: CYTTSP5 touch controller at 0x24 */
+ touchscreen@24 {
+ compatible = "cypress,tt21000";
+ reg = <0x24>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cyttsp5_gpio>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&ldo5_reg>;
+ };
/* TODO: SY7636 PMIC for E Ink at 0x62 */
@@ -312,6 +321,7 @@
&usbotg1 {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
disable-over-current;
srp-disable;
hnp-disable;
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index 57a028a69373..ce5221c6b358 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -9,11 +9,11 @@
};
psci {
- compatible = "arm,psci";
- method = "smc";
- cpu_suspend = <0x84000002>;
- cpu_off = <0x84000004>;
- cpu_on = <0x84000006>;
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000002>;
+ cpu_off = <0x84000004>;
+ cpu_on = <0x84000006>;
};
soc {
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
index a8d8bb0419a0..f23a25cce119 100644
--- a/arch/arm/boot/dts/en7523-evb.dts
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -33,3 +33,11 @@
&gpio1 {
status = "okay";
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 36597f587f46..7f839331a777 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/en7523-clk.h>
/ {
interrupt-parent = <&gic>;
@@ -83,6 +84,13 @@
};
};
+ scu: system-controller@1fa20000 {
+ compatible = "airoha,en7523-scu";
+ reg = <0x1fa20000 0x400>,
+ <0x1fb00000 0x1000>;
+ #clock-cells = <1>;
+ };
+
gic: interrupt-controller@9000000 {
compatible = "arm,gic-v3";
interrupt-controller;
@@ -135,4 +143,62 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ pcie0: pcie@1fa91000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa91000 0x1000>;
+ reg-names = "port0";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck0";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1fa92000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa92000 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck1";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/exynos-pinctrl.h b/arch/arm/boot/dts/exynos-pinctrl.h
new file mode 100644
index 000000000000..e3a6df95281c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos-pinctrl.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung Exynos DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
+#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
+
+#define EXYNOS_PIN_PULL_NONE 0
+#define EXYNOS_PIN_PULL_DOWN 1
+#define EXYNOS_PIN_PULL_UP 3
+
+/* Pin function in power down mode */
+#define EXYNOS_PIN_PDN_OUT0 0
+#define EXYNOS_PIN_PDN_OUT1 1
+#define EXYNOS_PIN_PDN_INPUT 2
+#define EXYNOS_PIN_PDN_PREV 3
+
+/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
+#define EXYNOS4_PIN_DRV_LV1 0
+#define EXYNOS4_PIN_DRV_LV2 2
+#define EXYNOS4_PIN_DRV_LV3 1
+#define EXYNOS4_PIN_DRV_LV4 3
+
+/* Drive strengths for Exynos5260 */
+#define EXYNOS5260_PIN_DRV_LV1 0
+#define EXYNOS5260_PIN_DRV_LV2 1
+#define EXYNOS5260_PIN_DRV_LV4 2
+#define EXYNOS5260_PIN_DRV_LV6 3
+
+/*
+ * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
+ * GPIO_HSI block)
+ */
+#define EXYNOS5420_PIN_DRV_LV1 0
+#define EXYNOS5420_PIN_DRV_LV2 1
+#define EXYNOS5420_PIN_DRV_LV3 2
+#define EXYNOS5420_PIN_DRV_LV4 3
+
+#define EXYNOS_PIN_FUNC_INPUT 0
+#define EXYNOS_PIN_FUNC_OUTPUT 1
+#define EXYNOS_PIN_FUNC_2 2
+#define EXYNOS_PIN_FUNC_3 3
+#define EXYNOS_PIN_FUNC_4 4
+#define EXYNOS_PIN_FUNC_5 5
+#define EXYNOS_PIN_FUNC_6 6
+#define EXYNOS_PIN_FUNC_EINT 0xf
+#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
index ecf416690a15..bc9a78f6d4b7 100644
--- a/arch/arm/boot/dts/exynos-syscon-restart.dtsi
+++ b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
@@ -7,7 +7,7 @@
poweroff: syscon-poweroff {
compatible = "syscon-poweroff";
regmap = <&pmu_system_controller>;
- offset = <0x330C>; /* PS_HOLD_CONTROL */
+ offset = <0x330c>; /* PS_HOLD_CONTROL */
mask = <0x5200>; /* reset value */
};
diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
index a1e22f630638..660cc7fac4db 100644
--- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts
+++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts
@@ -16,6 +16,10 @@
model = "Samsung ARTIK5 evaluation board";
compatible = "samsung,artik5-eval", "samsung,artik5",
"samsung,exynos3250", "samsung,exynos3";
+
+ aliases {
+ mmc0 = &mshc_2;
+ };
};
&mshc_2 {
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 7b429622a288..3fdd922e635c 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -17,6 +17,11 @@
/ {
compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
+ aliases {
+ mmc0 = &mshc_0;
+ mmc1 = &mshc_1;
+ };
+
chosen {
stdout-path = &serial_2;
};
@@ -321,6 +326,7 @@
vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>;
max-frequency = <100000000>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
@@ -357,7 +363,7 @@
&pinctrl_1 {
bten: bten-pins {
- samsung,pins ="gpx1-7";
+ samsung,pins = "gpx1-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index 02a9dc479d34..2de877d4ccc5 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -22,6 +22,7 @@
aliases {
i2c7 = &i2c_max77836;
+ mmc0 = &mshc_0;
};
memory@40000000 {
@@ -31,7 +32,7 @@
firmware@205f000 {
compatible = "samsung,secure-firmware";
- reg = <0x0205F000 0x1000>;
+ reg = <0x0205f000 0x1000>;
};
gpio-keys {
@@ -438,12 +439,12 @@
broken-cd;
non-removable;
cap-mmc-highspeed;
- desc-num = <4>;
mmc-hs200-1_8v;
card-detect-delay = <200>;
vmmc-supply = <&vemmc_reg>;
clock-frequency = <100000000>;
max-frequency = <100000000>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index cc30d154ec94..011ba2eff29e 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -9,7 +9,7 @@
* tree nodes are listed in this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
#define PIN_IN(_pin, _pull, _drv) \
pin- ## _pin { \
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 6d2c7bb19184..88fb3e68ff02 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -23,6 +23,8 @@
aliases {
i2c7 = &i2c_max77836;
+ mmc0 = &mshc_0;
+ mmc1 = &mshc_1;
};
chosen {
@@ -36,7 +38,7 @@
firmware@205f000 {
compatible = "samsung,secure-firmware";
- reg = <0x0205F000 0x1000>;
+ reg = <0x0205f000 0x1000>;
};
gpio-keys {
@@ -250,7 +252,7 @@
i80-if-timings {
cs-setup = <0>;
wr-setup = <0>;
- wr-act = <1>;
+ wr-active = <1>;
wr-hold = <0>;
};
};
@@ -619,12 +621,12 @@
broken-cd;
non-removable;
cap-mmc-highspeed;
- desc-num = <4>;
mmc-hs200-1_8v;
card-detect-delay = <200>;
vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>;
max-frequency = <100000000>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index ae644315855d..bd37f1b587f0 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -28,9 +28,6 @@
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
- mshc0 = &mshc_0;
- mshc1 = &mshc_1;
- mshc2 = &mshc_2;
spi0 = &spi_0;
spi1 = &spi_1;
i2c0 = &i2c_0;
@@ -46,6 +43,157 @@
serial2 = &serial_2;
};
+ bus_dmc: bus-dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+
+ bus_dmc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <825000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <875000>;
+ };
+ };
+ };
+
+ bus_fsys: bus-fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_isp: bus-isp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_isp_opp_table>;
+ status = "disabled";
+
+ bus_isp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp-80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+ };
+
+ bus_lcd0: bus-lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus: bus-leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mcuisp: bus-mcuisp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_mcuisp_opp_table>;
+ status = "disabled";
+
+ bus_mcuisp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp-80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+ };
+ };
+
+ bus_mfc: bus-mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peril: bus-peril {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_peril_opp_table>;
+ status = "disabled";
+
+ bus_peril_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp-80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ };
+ };
+
+ bus_rightbus: bus-rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -129,6 +277,31 @@
clock-output-names = "xtcxo";
};
+ bus_leftbus_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1000000>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -170,7 +343,7 @@
};
pmu_system_controller: system-controller@10020000 {
- compatible = "samsung,exynos3250-pmu", "syscon";
+ compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon";
reg = <0x10020000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
@@ -178,45 +351,44 @@
clock-names = "clkout8";
clocks = <&cmu CLK_FIN_PLL>;
#clock-cells = <1>;
- };
- mipi_phy: video-phy {
- compatible = "samsung,s5pv210-mipi-video-phy";
- #phy-cells = <1>;
- syscon = <&pmu_system_controller>;
+ mipi_phy: mipi-phy {
+ compatible = "samsung,s5pv210-mipi-video-phy";
+ #phy-cells = <1>;
+ };
};
pd_cam: power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C00 0x20>;
+ reg = <0x10023c00 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
pd_mfc: power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C40 0x20>;
+ reg = <0x10023c40 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
pd_g3d: power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C60 0x20>;
+ reg = <0x10023c60 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
pd_lcd0: power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C80 0x20>;
+ reg = <0x10023c80 0x20>;
#power-domain-cells = <0>;
label = "LCD0";
};
pd_isp: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023CA0 0x20>;
+ reg = <0x10023ca0 0x20>;
#power-domain-cells = <0>;
label = "ISP";
};
@@ -233,7 +405,7 @@
cmu_dmc: clock-controller@105c0000 {
compatible = "samsung,exynos3250-cmu-dmc";
- reg = <0x105C0000 0x2000>;
+ reg = <0x105c0000 0x2000>;
#clock-cells = <1>;
};
@@ -248,7 +420,7 @@
tmu: tmu@100c0000 {
compatible = "samsung,exynos3250-tmu";
- reg = <0x100C0000 0x100>;
+ reg = <0x100c0000 0x100>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
@@ -269,7 +441,8 @@
};
timer@10050000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos3250-mct",
+ "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
@@ -341,7 +514,7 @@
dsi_0: dsi@11c80000 {
compatible = "samsung,exynos3250-mipi-dsi";
- reg = <0x11C80000 0x10000>;
+ reg = <0x11c80000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
samsung,phy-type = <0>;
power-domains = <&pd_lcd0>;
@@ -364,7 +537,7 @@
#iommu-cells = <0>;
};
- hsotg: hsotg@12480000 {
+ hsotg: usb@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
@@ -375,7 +548,7 @@
status = "disabled";
};
- mshc_0: mshc@12510000 {
+ mshc_0: mmc@12510000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12510000 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
@@ -387,7 +560,7 @@
status = "disabled";
};
- mshc_1: mshc@12520000 {
+ mshc_1: mmc@12520000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12520000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -399,7 +572,7 @@
status = "disabled";
};
- mshc_2: mshc@12530000 {
+ mshc_2: mmc@12530000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12530000 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
@@ -411,9 +584,9 @@
status = "disabled";
};
- exynos_usbphy: exynos-usbphy@125b0000 {
+ exynos_usbphy: usb-phy@125b0000 {
compatible = "samsung,exynos3250-usb2-phy";
- reg = <0x125B0000 0x100>;
+ reg = <0x125b0000 0x100>;
samsung,pmureg-phandle = <&pmu_system_controller>;
clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
clock-names = "phy", "ref";
@@ -428,8 +601,6 @@
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@12690000 {
@@ -439,13 +610,11 @@
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
adc: adc@126c0000 {
compatible = "samsung,exynos3250-adc";
- reg = <0x126C0000 0x100>;
+ reg = <0x126c0000 0x100>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc", "sclk";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
@@ -488,7 +657,7 @@
};
mfc: codec@13400000 {
- compatible = "samsung,mfc-v7";
+ compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7";
reg = <0x13400000 0x10000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mfc", "sclk_mfc";
@@ -596,7 +765,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138A0000 0x100>;
+ reg = <0x138a0000 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C4>;
clock-names = "i2c";
@@ -609,7 +778,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138B0000 0x100>;
+ reg = <0x138b0000 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C5>;
clock-names = "i2c";
@@ -622,7 +791,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138C0000 0x100>;
+ reg = <0x138c0000 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C6>;
clock-names = "i2c";
@@ -635,7 +804,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138D0000 0x100>;
+ reg = <0x138d0000 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C7>;
clock-names = "i2c";
@@ -691,7 +860,7 @@
pwm: pwm@139d0000 {
compatible = "samsung,exynos4210-pwm";
- reg = <0x139D0000 0x1000>;
+ reg = <0x139d0000 0x1000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
@@ -774,182 +943,6 @@
clock-names = "ppmu";
status = "disabled";
};
-
- bus_dmc: bus-dmc {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu_dmc CLK_DIV_DMC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_dmc_opp_table>;
- status = "disabled";
- };
-
- bus_dmc_opp_table: opp-table1 {
- compatible = "operating-points-v2";
-
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- opp-microvolt = <800000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <800000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <800000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <825000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <875000>;
- };
- };
-
- bus_leftbus: bus-leftbus {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_DIV_GDL>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_rightbus: bus-rightbus {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_DIV_GDR>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_lcd0: bus-lcd0 {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_DIV_ACLK_160>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_fsys: bus-fsys {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_DIV_ACLK_200>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_mcuisp: bus-mcuisp {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
- clock-names = "bus";
- operating-points-v2 = <&bus_mcuisp_opp_table>;
- status = "disabled";
- };
-
- bus_isp: bus-isp {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_DIV_ACLK_266>;
- clock-names = "bus";
- operating-points-v2 = <&bus_isp_opp_table>;
- status = "disabled";
- };
-
- bus_peril: bus-peril {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_DIV_ACLK_100>;
- clock-names = "bus";
- operating-points-v2 = <&bus_peril_opp_table>;
- status = "disabled";
- };
-
- bus_mfc: bus-mfc {
- compatible = "samsung,exynos-bus";
- clocks = <&cmu CLK_SCLK_MFC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_leftbus_opp_table: opp-table2 {
- compatible = "operating-points-v2";
-
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- opp-microvolt = <900000>;
- };
- opp-80000000 {
- opp-hz = /bits/ 64 <80000000>;
- opp-microvolt = <900000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <1000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <1000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <1000000>;
- };
- };
-
- bus_mcuisp_opp_table: opp-table3 {
- compatible = "operating-points-v2";
-
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- };
- opp-80000000 {
- opp-hz = /bits/ 64 <80000000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- };
- };
-
- bus_isp_opp_table: opp-table4 {
- compatible = "operating-points-v2";
-
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- };
- opp-80000000 {
- opp-hz = /bits/ 64 <80000000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- };
- };
-
- bus_peril_opp_table: opp-table5 {
- compatible = "operating-points-v2";
-
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- };
- opp-80000000 {
- opp-hz = /bits/ 64 <80000000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- };
};
};
diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
index 021d9fc1b492..27a1a8952665 100644
--- a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
@@ -10,7 +10,7 @@
/ {
thermal-zones {
cpu_thermal: cpu-thermal {
- thermal-sensors = <&tmu 0>;
+ thermal-sensors = <&tmu>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e81b3ee4e0f7..8dd6976ab0a7 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -65,7 +65,7 @@
clock_audss: clock-controller@3810000 {
compatible = "samsung,exynos4210-audss-clock";
- reg = <0x03810000 0x0C>;
+ reg = <0x03810000 0x0c>;
#clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
<&clock CLK_SCLK_AUDIO0>,
@@ -105,36 +105,30 @@
reg = <0x12570000 0x14>;
};
- mipi_phy: video-phy {
- compatible = "samsung,s5pv210-mipi-video-phy";
- #phy-cells = <1>;
- syscon = <&pmu_system_controller>;
- };
-
pd_mfc: power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C40 0x20>;
+ reg = <0x10023c40 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
pd_g3d: power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C60 0x20>;
+ reg = <0x10023c60 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
pd_lcd0: power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C80 0x20>;
+ reg = <0x10023c80 0x20>;
#power-domain-cells = <0>;
label = "LCD0";
};
pd_tv: power-domain@10023c20 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C20 0x20>;
+ reg = <0x10023c20 0x20>;
#power-domain-cells = <0>;
power-domains = <&pd_lcd0>;
label = "TV";
@@ -142,21 +136,21 @@
pd_cam: power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023C00 0x20>;
+ reg = <0x10023c00 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
pd_gps: power-domain@10023ce0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023CE0 0x20>;
+ reg = <0x10023ce0 0x20>;
#power-domain-cells = <0>;
label = "GPS";
};
pd_gps_alive: power-domain@10023d00 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023D00 0x20>;
+ reg = <0x10023d00 0x20>;
#power-domain-cells = <0>;
label = "GPS alive";
};
@@ -181,16 +175,21 @@
};
pmu_system_controller: system-controller@10020000 {
- compatible = "samsung,exynos4210-pmu", "syscon";
+ compatible = "samsung,exynos4210-pmu", "simple-mfd", "syscon";
reg = <0x10020000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
+
+ mipi_phy: mipi-phy {
+ compatible = "samsung,s5pv210-mipi-video-phy";
+ #phy-cells = <1>;
+ };
};
dsi_0: dsi@11c80000 {
compatible = "samsung,exynos4210-mipi-dsi";
- reg = <0x11C80000 0x10000>;
+ reg = <0x11c80000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
@@ -309,14 +308,14 @@
keypad: keypad@100a0000 {
compatible = "samsung,s5pv210-keypad";
- reg = <0x100A0000 0x100>;
+ reg = <0x100a0000 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
};
- sdhci_0: sdhci@12510000 {
+ sdhci_0: mmc@12510000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@@ -325,7 +324,7 @@
status = "disabled";
};
- sdhci_1: sdhci@12520000 {
+ sdhci_1: mmc@12520000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@@ -334,7 +333,7 @@
status = "disabled";
};
- sdhci_2: sdhci@12530000 {
+ sdhci_2: mmc@12530000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -343,7 +342,7 @@
status = "disabled";
};
- sdhci_3: sdhci@12540000 {
+ sdhci_3: mmc@12540000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -352,9 +351,9 @@
status = "disabled";
};
- exynos_usbphy: exynos-usbphy@125b0000 {
+ exynos_usbphy: usb-phy@125b0000 {
compatible = "samsung,exynos4210-usb2-phy";
- reg = <0x125B0000 0x100>;
+ reg = <0x125b0000 0x100>;
samsung,pmureg-phandle = <&pmu_system_controller>;
clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
clock-names = "phy", "ref";
@@ -362,7 +361,7 @@
status = "disabled";
};
- hsotg: hsotg@12480000 {
+ hsotg: usb@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -373,7 +372,7 @@
status = "disabled";
};
- ehci: ehci@12580000 {
+ ehci: usb@12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -384,7 +383,7 @@
phy-names = "host", "hsic0", "hsic1";
};
- ohci: ohci@12590000 {
+ ohci: usb@12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -546,7 +545,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138A0000 0x100>;
+ reg = <0x138a0000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C4>;
clock-names = "i2c";
@@ -559,7 +558,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138B0000 0x100>;
+ reg = <0x138b0000 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C5>;
clock-names = "i2c";
@@ -572,7 +571,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138C0000 0x100>;
+ reg = <0x138c0000 0x100>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C6>;
clock-names = "i2c";
@@ -585,7 +584,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- reg = <0x138D0000 0x100>;
+ reg = <0x138d0000 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C7>;
clock-names = "i2c";
@@ -598,14 +597,14 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-hdmiphy-i2c";
- reg = <0x138E0000 0x100>;
+ reg = <0x138e0000 0x100>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c";
status = "disabled";
- hdmi_i2c_phy: hdmiphy@38 {
- compatible = "exynos4210-hdmiphy";
+ hdmi_i2c_phy: hdmi-phy@38 {
+ compatible = "samsung,exynos4210-hdmiphy";
reg = <0x38>;
};
};
@@ -657,7 +656,7 @@
pwm: pwm@139d0000 {
compatible = "samsung,exynos4210-pwm";
- reg = <0x139D0000 0x1000>;
+ reg = <0x139d0000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
@@ -676,8 +675,6 @@
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@12690000 {
@@ -687,8 +684,6 @@
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
mdma1: dma-controller@12850000 {
@@ -698,8 +693,6 @@
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
fimd: fimd@11c00000 {
@@ -718,7 +711,7 @@
tmu: tmu@100c0000 {
interrupt-parent = <&combiner>;
- reg = <0x100C0000 0x100>;
+ reg = <0x100c0000 0x100>;
interrupts = <2 4>;
status = "disabled";
#thermal-sensor-cells = <0>;
@@ -745,7 +738,7 @@
hdmi: hdmi@12d00000 {
compatible = "samsung,exynos4210-hdmi";
- reg = <0x12D00000 0x70000>;
+ reg = <0x12d00000 0x70000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "mout_hdmi";
@@ -762,7 +755,7 @@
hdmicec: cec@100b0000 {
compatible = "samsung,s5p-cec";
- reg = <0x100B0000 0x200>;
+ reg = <0x100b0000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
@@ -776,7 +769,7 @@
mixer: mixer@12c10000 {
compatible = "samsung,exynos4210-mixer";
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
+ reg = <0x12c10000 0x2100>, <0x12c00000 0x300>;
power-domains = <&pd_tv>;
iommus = <&sysmmu_tv>;
status = "disabled";
@@ -908,7 +901,7 @@
sysmmu_tv: sysmmu@12e20000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x12E20000 0x1000>;
+ reg = <0x12e20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 4>;
clock-names = "sysmmu", "master";
@@ -919,7 +912,7 @@
sysmmu_fimc0: sysmmu@11a20000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11A20000 0x1000>;
+ reg = <0x11a20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 2>;
clock-names = "sysmmu", "master";
@@ -930,7 +923,7 @@
sysmmu_fimc1: sysmmu@11a30000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11A30000 0x1000>;
+ reg = <0x11a30000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 3>;
clock-names = "sysmmu", "master";
@@ -941,7 +934,7 @@
sysmmu_fimc2: sysmmu@11a40000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11A40000 0x1000>;
+ reg = <0x11a40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 4>;
clock-names = "sysmmu", "master";
@@ -952,7 +945,7 @@
sysmmu_fimc3: sysmmu@11a50000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11A50000 0x1000>;
+ reg = <0x11a50000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 5>;
clock-names = "sysmmu", "master";
@@ -963,7 +956,7 @@
sysmmu_jpeg: sysmmu@11a60000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11A60000 0x1000>;
+ reg = <0x11a60000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 6>;
clock-names = "sysmmu", "master";
@@ -974,7 +967,7 @@
sysmmu_rotator: sysmmu@12a30000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x12A30000 0x1000>;
+ reg = <0x12a30000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 0>;
clock-names = "sysmmu", "master";
@@ -985,7 +978,7 @@
sysmmu_fimd0: sysmmu@11e20000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11E20000 0x1000>;
+ reg = <0x11e20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 2>;
clock-names = "sysmmu", "master";
diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts
index 3c0a18b30837..37cd4dde53e4 100644
--- a/arch/arm/boot/dts/exynos4210-i9100.dts
+++ b/arch/arm/boot/dts/exynos4210-i9100.dts
@@ -25,6 +25,12 @@
reg = <0x40000000 0x40000000>;
};
+ aliases {
+ mmc0 = &sdhci_0;
+ mmc1 = &sdhci_2;
+ mmc2 = &sdhci_3;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
@@ -89,21 +95,21 @@
gpio-keys {
compatible = "gpio-keys";
- vol-down {
+ key-vol-down {
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
label = "volume down";
debounce-interval = <10>;
};
- vol-up {
+ key-vol-up {
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
debounce-interval = <10>;
};
- power {
+ key-power {
gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "power";
@@ -111,7 +117,7 @@
wakeup-source;
};
- ok {
+ key-ok {
gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_OK>;
label = "ok";
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index a08ce2f37ea2..f1927ca15e08 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,6 +15,7 @@
#include "exynos4210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include "exynos-mfc-reserved-memory.dtsi"
/ {
@@ -29,6 +30,11 @@
0x70000000 0x10000000>;
};
+ aliases {
+ mmc0 = &sdhci_0;
+ mmc1 = &sdhci_2;
+ };
+
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
stdout-path = "serial2:115200n8";
@@ -46,35 +52,35 @@
gpio-keys {
compatible = "gpio-keys";
- up {
+ key-up {
label = "Up";
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
wakeup-source;
};
- down {
+ key-down {
label = "Down";
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
wakeup-source;
};
- back {
+ key-back {
label = "Back";
gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
wakeup-source;
};
- home {
+ key-home {
label = "Home";
gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
- menu {
+ key-menu {
label = "Menu";
gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
@@ -84,8 +90,9 @@
leds {
compatible = "gpio-leds";
- status {
+ led-status {
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
+ function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
};
};
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 6373009bb727..76f44ae0de46 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -11,7 +11,7 @@
* tree nodes are listed in this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
&pinctrl_0 {
gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index a5dfd7fd49b3..b566f878ed84 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -25,6 +25,10 @@
reg = <0x40000000 0x80000000>;
};
+ aliases {
+ mmc0 = &sdhci_2;
+ };
+
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
stdout-path = "serial1:115200n8";
@@ -203,7 +207,7 @@
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "w25x80";
+ compatible = "winbond,w25x80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 01f44d95f671..ff6ee4b2c31b 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -26,6 +26,12 @@
0x70000000 0x10000000>;
};
+ aliases {
+ mmc0 = &sdhci_0;
+ mmc1 = &sdhci_2;
+ mmc2 = &sdhci_3;
+ };
+
chosen {
bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
stdout-path = "serial2:115200n8";
@@ -180,7 +186,7 @@
vdd3-supply = <&vcclcd_reg>;
vci-supply = <&vlcd_reg>;
reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>;
- power-on-delay= <50>;
+ power-on-delay = <50>;
reset-delay = <100>;
init-delay = <100>;
flip-horizontal;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 138d606d58a5..8fe0d5d2be2d 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -24,6 +24,12 @@
0x50000000 0x10000000>;
};
+ aliases {
+ mmc0 = &sdhci_0;
+ mmc1 = &sdhci_2;
+ mmc2 = &sdhci_3;
+ };
+
chosen {
bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
stdout-path = "serial2:115200n8";
@@ -516,7 +522,7 @@
};
&mct {
- compatible = "none";
+ status = "disabled";
};
&mdma1 {
@@ -666,8 +672,6 @@
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
power-domains = <&pd_lcd0>;
};
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2c25cc37934e..0e27c3375e2e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -28,6 +28,151 @@
pinctrl2 = &pinctrl_2;
};
+ bus_acp: bus-acp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_acp_opp_table>;
+ status = "disabled";
+
+ bus_acp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ };
+ };
+
+ bus_display: bus-display {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_display_opp_table>;
+ status = "disabled";
+
+ bus_display_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ };
+ };
+
+ bus_dmc: bus-dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+
+ bus_dmc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1150000>;
+ opp-suspend;
+ };
+ };
+ };
+
+ bus_fsys: bus-fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_fsys_opp_table>;
+ status = "disabled";
+
+ bus_fsys_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ };
+ };
+
+ bus_lcd0: bus-lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK200>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus: bus-leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus-mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus-peri {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_peri_opp_table>;
+ status = "disabled";
+
+ bus_peri_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ };
+ };
+
+ bus_rightbus: bus-rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,6 +227,22 @@
};
};
+ bus_leftbus_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-suspend;
+ };
+ };
+
soc: soc {
sysram: sram@2020000 {
compatible = "mmio-sram";
@@ -103,7 +264,7 @@
pd_lcd1: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023CA0 0x20>;
+ reg = <0x10023ca0 0x20>;
#power-domain-cells = <0>;
label = "LCD1";
};
@@ -195,7 +356,7 @@
sysmmu_g2d: sysmmu@12a20000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x12A20000 0x1000>;
+ reg = <0x12a20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 7>;
clock-names = "sysmmu", "master";
@@ -214,167 +375,6 @@
power-domains = <&pd_lcd1>;
#iommu-cells = <0>;
};
-
- bus_dmc: bus-dmc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_DMC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_dmc_opp_table>;
- status = "disabled";
- };
-
- bus_acp: bus-acp {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_ACP>;
- clock-names = "bus";
- operating-points-v2 = <&bus_acp_opp_table>;
- status = "disabled";
- };
-
- bus_peri: bus-peri {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK100>;
- clock-names = "bus";
- operating-points-v2 = <&bus_peri_opp_table>;
- status = "disabled";
- };
-
- bus_fsys: bus-fsys {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK133>;
- clock-names = "bus";
- operating-points-v2 = <&bus_fsys_opp_table>;
- status = "disabled";
- };
-
- bus_display: bus-display {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK160>;
- clock-names = "bus";
- operating-points-v2 = <&bus_display_opp_table>;
- status = "disabled";
- };
-
- bus_lcd0: bus-lcd0 {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK200>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_leftbus: bus-leftbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDL>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_rightbus: bus-rightbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDR>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_mfc: bus-mfc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_SCLK_MFC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_dmc_opp_table: opp-table1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <1025000>;
- };
- opp-267000000 {
- opp-hz = /bits/ 64 <267000000>;
- opp-microvolt = <1050000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <1150000>;
- opp-suspend;
- };
- };
-
- bus_acp_opp_table: opp-table2 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- };
- };
-
- bus_peri_opp_table: opp-table3 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-5000000 {
- opp-hz = /bits/ 64 <5000000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- };
-
- bus_fsys_opp_table: opp-table4 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-10000000 {
- opp-hz = /bits/ 64 <10000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- };
- };
-
- bus_display_opp_table: opp-table5 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- };
-
- bus_leftbus_opp_table: opp-table6 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-suspend;
- };
- };
};
};
@@ -393,7 +393,6 @@
&cpu_thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
- thermal-sensors = <&tmu 0>;
};
&gic {
diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
index 03dffc690b79..94122e9c6625 100644
--- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
+++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
@@ -7,6 +7,7 @@
*/
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include "exynos4412-midas.dtsi"
/ {
@@ -25,8 +26,9 @@
pinctrl-1 = <&camera_flash_host>;
pinctrl-2 = <&camera_flash_isp>;
- flash-led {
- label = "flash";
+ led {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <520833>;
flash-max-microamp = <1012500>;
flash-max-timeout-us = <1940000>;
@@ -107,7 +109,7 @@
vdd3-supply = <&lcd_vdd3_reg>;
vci-supply = <&ldo25_reg>;
reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>;
- power-on-delay= <50>;
+ power-on-delay = <50>;
reset-delay = <100>;
init-delay = <100>;
flip-horizontal;
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
index a9406280b979..ded232b04e0d 100644
--- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -11,6 +11,7 @@
*/
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos4412-itop-scp-core.dtsi"
@@ -19,6 +20,10 @@
model = "TOPEET iTop 4412 Elite board based on Exynos4412";
compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4";
+ aliases {
+ mmc1 = &sdhci_2;
+ };
+
chosen {
bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait";
stdout-path = "serial2:115200n8";
@@ -28,7 +33,8 @@
compatible = "gpio-leds";
led2 {
- label = "red:system";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
@@ -36,6 +42,7 @@
led3 {
label = "red:user";
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
@@ -44,31 +51,31 @@
gpio-keys {
compatible = "gpio-keys";
- home {
+ key-home {
label = "GPIO Key Home";
linux,code = <KEY_HOME>;
gpios = <&gpx1 1 GPIO_ACTIVE_LOW>;
};
- back {
+ key-back {
label = "GPIO Key Back";
linux,code = <KEY_BACK>;
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
};
- sleep {
+ key-sleep {
label = "GPIO Key Sleep";
linux,code = <KEY_POWER>;
gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
};
- vol-up {
+ key-vol-up {
label = "GPIO Key Vol+";
linux,code = <KEY_UP>;
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
};
- vol-down {
+ key-vol-down {
label = "GPIO Key Vol-";
linux,code = <KEY_DOWN>;
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
@@ -179,7 +186,7 @@
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&pmu_system_controller 0>;
- clock-names = "MCLK1";
+ clock-names = "mclk";
wlf,shared-lrclk;
#sound-dai-cells = <0>;
};
@@ -211,7 +218,7 @@
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
pinctrl-names = "default";
- cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpx0 7 GPIO_ACTIVE_LOW>;
cap-sd-highspeed;
vmmc-supply = <&ldo23_reg>;
vqmmc-supply = <&ldo17_reg>;
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
index a67cb61e3cbb..7bc6968af9c3 100644
--- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
@@ -23,9 +23,13 @@
reg = <0x40000000 0x40000000>;
};
+ aliases {
+ mmc0 = &mshc_0;
+ };
+
firmware@203f000 {
compatible = "samsung,secure-firmware";
- reg = <0x0203F000 0x1000>;
+ reg = <0x0203f000 0x1000>;
};
fixed-rate-clocks {
@@ -476,6 +480,7 @@
vmmc-supply = <&buck9_reg>;
broken-cd;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
index 23f50c9be527..e6b949c1a00f 100644
--- a/arch/arm/boot/dts/exynos4412-midas.dtsi
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -12,11 +12,12 @@
/dts-v1/;
#include "exynos4412.dtsi"
#include "exynos4412-ppmu-common.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/maxim,max77686.h>
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
/ {
compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
@@ -24,6 +25,9 @@
aliases {
i2c11 = &i2c_max77693;
i2c12 = &i2c_max77693_fuel;
+ mmc0 = &mshc_0;
+ mmc2 = &sdhci_2;
+ mmc3 = &sdhci_3;
};
chosen {
@@ -32,7 +36,7 @@
firmware@204f000 {
compatible = "samsung,secure-firmware";
- reg = <0x0204F000 0x1000>;
+ reg = <0x0204f000 0x1000>;
};
fixed-rate-clocks {
@@ -272,9 +276,16 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x39>;
- port {
- mhl_to_hdmi: endpoint {
- remote-endpoint = <&hdmi_to_mhl>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mhl_to_hdmi: endpoint {
+ remote-endpoint = <&hdmi_to_mhl>;
+ };
};
};
};
@@ -489,8 +500,7 @@
pinctrl-0 = <&fimc_is_uart>;
pinctrl-names = "default";
status = "okay";
-
- };
+};
&fimc_lite_0 {
status = "okay";
@@ -584,8 +594,7 @@
/* CAM_B_CLKOUT */
clocks = <&camera 1>;
clock-names = "extclk";
- samsung,camclk-out = <1>;
- gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpm1 6 GPIO_ACTIVE_LOW>;
port {
is_s5k6a3_ep: endpoint {
@@ -645,8 +654,8 @@
CPVDD-supply = <&vbatt_reg>;
SPKVDD1-supply = <&vbatt_reg>;
SPKVDD2-supply = <&vbatt_reg>;
- wlf,ldo1ena = <&gpj0 4 0>;
- wlf,ldo2ena = <&gpj0 4 0>;
+ wlf,ldo1ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>;
+ wlf,ldo2ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>;
};
};
@@ -971,6 +980,7 @@
samsung,dw-mshc-ciu-div = <0>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
+ mmc-ddr-1_8v;
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
pinctrl-names = "default";
status = "okay";
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index e7669b9e9edb..45ef7b7ba7e0 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -13,13 +13,18 @@
#include "exynos-mfc-reserved-memory.dtsi"
/ {
+ aliases {
+ mmc0 = &mshc_0;
+ mmc2 = &sdhci_2;
+ };
+
chosen {
stdout-path = &serial_1;
};
firmware@204f000 {
compatible = "samsung,secure-firmware";
- reg = <0x0204F000 0x1000>;
+ reg = <0x0204f000 0x1000>;
};
gpio_keys: gpio-keys {
@@ -533,6 +538,7 @@
broken-cd;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index efaf7533e84f..42812da1f882 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -9,6 +9,7 @@
*/
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include "exynos4412-odroid-common.dtsi"
#include "exynos4412-prime.dtsi"
@@ -22,7 +23,7 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x7FF00000>;
+ reg = <0x40000000 0x7ff00000>;
};
vbus_otg_reg: regulator-1 {
@@ -37,7 +38,8 @@
leds {
compatible = "gpio-leds";
led1 {
- label = "led1:heart";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpc1 0 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
@@ -119,8 +121,8 @@
phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
phy-names = "hsic0", "hsic1";
- ethernet: usbether@2 {
- compatible = "usb0424,9730";
+ ethernet: ethernet@2 {
+ compatible = "usb424,9730";
reg = <2>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index a9fada51eb50..d5316cf2fbb6 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -9,6 +9,7 @@
*/
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include "exynos4412-odroid-common.dtsi"
/ {
@@ -21,19 +22,21 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x3FF00000>;
+ reg = <0x40000000 0x3ff00000>;
};
leds {
compatible = "gpio-leds";
led1 {
- label = "led1:heart";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpc1 0 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2:mmc0";
+ function = LED_FUNCTION_DISK_ACTIVITY;
gpios = <&gpc1 2 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "mmc0";
@@ -70,19 +73,19 @@
phy-names = "hsic0";
hub@2 {
- compatible = "usb0424,3503";
+ compatible = "usb424,3503";
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
hub@1 {
- compatible = "usb0424,9514";
+ compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
- compatible = "usb0424,ec00";
+ ethernet: ethernet@1 {
+ compatible = "usb424,ec00";
reg = <1>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts
index f4b68c75c962..7be4cbdc4413 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx2.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts
@@ -17,6 +17,6 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x7FF00000>;
+ reg = <0x40000000 0x7ff00000>;
};
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 6db09dba07ff..23b151645d66 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -25,13 +25,18 @@
reg = <0x40000000 0x40000000>;
};
+ aliases {
+ mmc0 = &mshc_0;
+ mmc1 = &sdhci_2;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
firmware@203f000 {
compatible = "samsung,secure-firmware";
- reg = <0x0203F000 0x1000>;
+ reg = <0x0203f000 0x1000>;
};
mmc_reg: regulator-0 {
@@ -95,7 +100,7 @@
};
&ehci {
- samsung,vbus-gpio = <&gpx3 5 1>;
+ samsung,vbus-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
status = "okay";
phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>;
phy-names = "hsic0", "hsic1";
@@ -498,6 +503,7 @@
broken-cd;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi
index 97f131b1014b..0b89d5682f85 100644
--- a/arch/arm/boot/dts/exynos4412-p4note.dtsi
+++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi
@@ -15,8 +15,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/samsung.h>
#include <dt-bindings/power/summit,smb347-charger.h>
+#include "exynos-pinctrl.h"
/ {
compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4";
@@ -26,13 +26,19 @@
reg = <0x40000000 0x80000000>;
};
+ aliases {
+ mmc0 = &mshc_0;
+ mmc2 = &sdhci_2;
+ mmc3 = &sdhci_3;
+ };
+
chosen {
stdout-path = &serial_2;
};
firmware@204f000 {
compatible = "samsung,secure-firmware";
- reg = <0x0204F000 0x1000>;
+ reg = <0x0204f000 0x1000>;
};
fixed-rate-clocks {
@@ -106,6 +112,16 @@
regulator-always-on;
};
+ panel_vdd: voltage-regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD_ENABLE";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable>;
+ gpios = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
wlan_pwrseq: sdhci3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>;
@@ -122,8 +138,6 @@
precharge-current-microamp = <250000>;
charge-term-current-microamp = <250000>;
constant-charge-voltage-max-microvolt = <4200000>;
-
- power-supplies = <&power_supply>;
};
i2c-gpio-1 {
@@ -180,17 +194,15 @@
pinctrl-names = "default";
interrupt-parent = <&gpx0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- irq-trigger = <0x1>;
st,adc-freq = <3>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,sample-time = <3>;
- stmpe_adc {
+ adc {
compatible = "st,stmpe-adc";
#io-channel-cells = <1>;
- st,norequest-mask = <0x2F>;
+ st,norequest-mask = <0x2f>;
};
};
};
@@ -216,6 +228,33 @@
monitored-battery = <&battery_cell>;
};
};
+
+ panel {
+ compatible = "samsung,ltl101al01";
+ pinctrl-0 = <&lvds_nshdn>;
+ pinctrl-names = "default";
+ power-supply = <&panel_vdd>;
+ enable-gpios = <&gpm0 5 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight>;
+
+ port {
+ lcd_ep: endpoint {
+ remote-endpoint = <&fimd_ep>;
+ };
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-0 = <&led_bl_reset>;
+ pinctrl-names = "default";
+ enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>;
+ power-supply = <&panel_vdd>;
+ pwms = <&pwm 1 78770 0>;
+ brightness-levels = <0 48 128 255>;
+ num-interpolated-steps = <8>;
+ default-brightness-level = <12>;
+ };
};
&adc {
@@ -295,22 +334,19 @@
};
&fimd {
- pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
+ pinctrl-0 = <&lcd_clk &lcd_data24>;
pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
- display-timings {
- timing0 {
- clock-frequency = <66666666>;
- hactive = <1280>;
- vactive = <800>;
- hfront-porch = <18>;
- hback-porch = <36>;
- hsync-len = <16>;
- vback-porch = <16>;
- vfront-porch = <4>;
- vsync-len = <3>;
- hsync-active = <1>;
+ samsung,invert-vclk;
+
+ port@3 {
+ reg = <3>;
+
+ fimd_ep: endpoint {
+ remote-endpoint = <&lcd_ep>;
};
};
};
@@ -663,6 +699,7 @@
samsung,dw-mshc-ciu-div = <0>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
+ mmc-ddr-1_8v;
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
pinctrl-names = "default";
bus-width = <4>;
@@ -687,6 +724,12 @@
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
+ lcd_enable: lcd-enable-pins {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
sleep0: sleep-state {
PIN_SLP(gpa0-0, INPUT, NONE);
PIN_SLP(gpa0-1, OUT0, NONE);
@@ -809,12 +852,24 @@
/* 0 = CP, 1 = AP (serial output) */
};
+ led_bl_reset: led-bl-reset-pins {
+ samsung,pins = "gpm0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
tsp_rst: tsp-rst-pins {
samsung,pins = "gpm0-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
+ lvds_nshdn: lvds-nshdn-pins {
+ samsung,pins = "gpm0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
tsp_irq: tsp-irq-pins {
samsung,pins = "gpm2-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
@@ -1100,6 +1155,13 @@
assigned-clock-parents = <&clock CLK_XUSBXTI>;
};
+&pwm {
+ pinctrl-0 = <&pwm1_out>;
+ pinctrl-names = "default";
+ samsung,pwm-outputs = <1>;
+ status = "okay";
+};
+
&rtc {
clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
clock-names = "rtc", "rtc_src";
diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
index 88b8afd55664..8ab31c3daa48 100644
--- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
@@ -9,10 +9,10 @@
* tree nodes are listed in this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
#define PIN_SLP(_pin, _mode, _pull) \
- _pin { \
+ pin- ## _pin { \
samsung,pins = #_pin; \
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index a40ff394977c..715dfcba1417 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -22,6 +22,10 @@
reg = <0x40000000 0x40000000>;
};
+ aliases {
+ mmc0 = &sdhci_2;
+ };
+
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc";
stdout-path = "serial1:115200n8";
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 017b26108bb0..5a2dcdc5c28b 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -11,11 +11,16 @@
/dts-v1/;
#include "exynos4412.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "FriendlyARM TINY4412 board based on Exynos4412";
compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
+ aliases {
+ mmc0 = &sdhci_2;
+ };
+
chosen {
stdout-path = &serial_0;
};
@@ -30,6 +35,7 @@
led1 {
label = "led1";
+ function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpm4 0 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
@@ -49,6 +55,7 @@
led4 {
label = "led4";
+ function = LED_FUNCTION_DISK_ACTIVITY;
gpios = <&gpm4 3 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "mmc0";
@@ -76,6 +83,7 @@
panel {
compatible = "innolux,at070tn92";
+ power-supply = <&vddq_lcd>;
port {
panel_input: endpoint {
@@ -83,6 +91,13 @@
};
};
};
+
+ vddq_lcd: regulator-vddq-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "vddq-lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
};
&cpu_thermal {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index aa0b61b59970..82a36fb5ee8b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -28,7 +28,134 @@
pinctrl3 = &pinctrl_3;
fimc-lite0 = &fimc_lite_0;
fimc-lite1 = &fimc_lite_1;
- mshc0 = &mshc_0;
+ };
+
+ bus_acp: bus-acp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_acp_opp_table>;
+ status = "disabled";
+
+ bus_acp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ };
+ };
+ };
+
+ bus_c2c: bus-c2c {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_C2C>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc: bus-dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ samsung,data-clock-ratio = <4>;
+ #interconnect-cells = <0>;
+ status = "disabled";
+ };
+
+ bus_display: bus-display {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_display_opp_table>;
+ interconnects = <&bus_leftbus &bus_dmc>;
+ #interconnect-cells = <0>;
+ status = "disabled";
+
+ bus_display_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ };
+ };
+
+ bus_fsys: bus-fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK133>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_fsys_opp_table>;
+ status = "disabled";
+
+ bus_fsys_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ };
+ };
+ };
+
+ bus_leftbus: bus-leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ interconnects = <&bus_dmc>;
+ #interconnect-cells = <0>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus-mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peri: bus-peri {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK100>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_peri_opp_table>;
+ status = "disabled";
+
+ bus_peri_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ };
+ };
+
+ bus_rightbus: bus-rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
};
cpus {
@@ -55,7 +182,7 @@
cpu0: cpu@a00 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- reg = <0xA00>;
+ reg = <0xa00>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
@@ -65,7 +192,7 @@
cpu1: cpu@a01 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- reg = <0xA01>;
+ reg = <0xa01>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
@@ -75,7 +202,7 @@
cpu2: cpu@a02 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- reg = <0xA02>;
+ reg = <0xa02>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
@@ -85,7 +212,7 @@
cpu3: cpu@a03 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- reg = <0xA03>;
+ reg = <0xa03>;
clocks = <&clock CLK_ARM_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
@@ -93,7 +220,7 @@
};
};
- cpu0_opp_table: opp-table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -171,6 +298,53 @@
};
};
+ bus_dmc_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ opp-suspend;
+ };
+ };
+
+ bus_leftbus_opp_table: opp-table-2 {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <925000>;
+ };
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1000000>;
+ opp-suspend;
+ };
+ };
soc: soc {
@@ -201,7 +375,7 @@
pinctrl_3: pinctrl@106e0000 {
compatible = "samsung,exynos4x12-pinctrl";
- reg = <0x106E0000 0x1000>;
+ reg = <0x106e0000 0x1000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -225,7 +399,7 @@
pd_isp: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x10023CA0 0x20>;
+ reg = <0x10023ca0 0x20>;
#power-domain-cells = <0>;
label = "ISP";
};
@@ -285,7 +459,7 @@
adc: adc@126c0000 {
compatible = "samsung,exynos4212-adc";
- reg = <0x126C0000 0x100>;
+ reg = <0x126c0000 0x100>;
interrupt-parent = <&combiner>;
interrupts = <10 3>;
clocks = <&clock CLK_TSADC>;
@@ -318,7 +492,7 @@
sysmmu_g2d: sysmmu@10a40000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x10A40000 0x1000>;
+ reg = <0x10a40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 7>;
clock-names = "sysmmu", "master";
@@ -350,7 +524,7 @@
sysmmu_fimc_fd: sysmmu@122a0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x122A0000 0x1000>;
+ reg = <0x122a0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <16 4>;
power-domains = <&pd_isp>;
@@ -361,7 +535,7 @@
sysmmu_fimc_mcuctl: sysmmu@122b0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x122B0000 0x1000>;
+ reg = <0x122b0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <16 5>;
power-domains = <&pd_isp>;
@@ -372,7 +546,7 @@
sysmmu_fimc_lite0: sysmmu@123b0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x123B0000 0x1000>;
+ reg = <0x123b0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <16 0>;
power-domains = <&pd_isp>;
@@ -384,7 +558,7 @@
sysmmu_fimc_lite1: sysmmu@123c0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x123C0000 0x1000>;
+ reg = <0x123c0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <16 1>;
power-domains = <&pd_isp>;
@@ -393,182 +567,6 @@
<&isp_clock CLK_ISP_FIMC_LITE1>;
#iommu-cells = <0>;
};
-
- bus_dmc: bus-dmc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_DMC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_dmc_opp_table>;
- samsung,data-clock-ratio = <4>;
- #interconnect-cells = <0>;
- status = "disabled";
- };
-
- bus_acp: bus-acp {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_ACP>;
- clock-names = "bus";
- operating-points-v2 = <&bus_acp_opp_table>;
- status = "disabled";
- };
-
- bus_c2c: bus-c2c {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_C2C>;
- clock-names = "bus";
- operating-points-v2 = <&bus_dmc_opp_table>;
- status = "disabled";
- };
-
- bus_dmc_opp_table: opp-table1 {
- compatible = "operating-points-v2";
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <900000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <900000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- opp-microvolt = <900000>;
- };
- opp-267000000 {
- opp-hz = /bits/ 64 <267000000>;
- opp-microvolt = <950000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <1050000>;
- opp-suspend;
- };
- };
-
- bus_acp_opp_table: opp-table2 {
- compatible = "operating-points-v2";
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- opp-267000000 {
- opp-hz = /bits/ 64 <267000000>;
- };
- };
-
- bus_leftbus: bus-leftbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDL>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- interconnects = <&bus_dmc>;
- #interconnect-cells = <0>;
- status = "disabled";
- };
-
- bus_rightbus: bus-rightbus {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DIV_GDR>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_display: bus-display {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK160>;
- clock-names = "bus";
- operating-points-v2 = <&bus_display_opp_table>;
- interconnects = <&bus_leftbus &bus_dmc>;
- #interconnect-cells = <0>;
- status = "disabled";
- };
-
- bus_fsys: bus-fsys {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK133>;
- clock-names = "bus";
- operating-points-v2 = <&bus_fsys_opp_table>;
- status = "disabled";
- };
-
- bus_peri: bus-peri {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_ACLK100>;
- clock-names = "bus";
- operating-points-v2 = <&bus_peri_opp_table>;
- status = "disabled";
- };
-
- bus_mfc: bus-mfc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_SCLK_MFC>;
- clock-names = "bus";
- operating-points-v2 = <&bus_leftbus_opp_table>;
- status = "disabled";
- };
-
- bus_leftbus_opp_table: opp-table3 {
- compatible = "operating-points-v2";
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <900000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- opp-microvolt = <925000>;
- };
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- opp-microvolt = <950000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <1000000>;
- opp-suspend;
- };
- };
-
- bus_display_opp_table: opp-table4 {
- compatible = "operating-points-v2";
-
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- };
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- };
- };
-
- bus_fsys_opp_table: opp-table5 {
- compatible = "operating-points-v2";
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp-134000000 {
- opp-hz = /bits/ 64 <134000000>;
- };
- };
-
- bus_peri_opp_table: opp-table6 {
- compatible = "operating-points-v2";
-
- opp-50000000 {
- opp-hz = /bits/ 64 <50000000>;
- };
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
- };
};
};
@@ -615,7 +613,7 @@
fimc_lite_1: fimc-lite@123a0000 {
compatible = "samsung,exynos4212-fimc-lite";
- reg = <0x123A0000 0x1000>;
+ reg = <0x123a0000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
@@ -799,7 +797,7 @@
};
&pmu_system_controller {
- compatible = "samsung,exynos4412-pmu", "syscon";
+ compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon";
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
@@ -812,7 +810,7 @@
compatible = "samsung,exynos4412-tmu";
interrupt-parent = <&combiner>;
interrupts = <2 4>;
- reg = <0x100C0000 0x100>;
+ reg = <0x100c0000 0x100>;
clocks = <&clock CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
status = "disabled";
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 9ce9fb3fc190..48e43b6b3213 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -89,7 +89,7 @@
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x10481000 0x1000>,
+ reg = <0x10481000 0x1000>,
<0x10482000 0x2000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
@@ -104,31 +104,31 @@
serial_0: serial@12c00000 {
compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
+ reg = <0x12c00000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
};
serial_1: serial@12c10000 {
compatible = "samsung,exynos4210-uart";
- reg = <0x12C10000 0x100>;
+ reg = <0x12c10000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
serial_2: serial@12c20000 {
compatible = "samsung,exynos4210-uart";
- reg = <0x12C20000 0x100>;
+ reg = <0x12c20000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
};
serial_3: serial@12c30000 {
compatible = "samsung,exynos4210-uart";
- reg = <0x12C30000 0x100>;
+ reg = <0x12c30000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
i2c_0: i2c@12c60000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12C60000 0x100>;
+ reg = <0x12c60000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -138,7 +138,7 @@
i2c_1: i2c@12c70000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12C70000 0x100>;
+ reg = <0x12c70000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -148,7 +148,7 @@
i2c_2: i2c@12c80000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12C80000 0x100>;
+ reg = <0x12c80000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -158,7 +158,7 @@
i2c_3: i2c@12c90000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12C90000 0x100>;
+ reg = <0x12c90000 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -168,7 +168,7 @@
pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
- reg = <0x12DD0000 0x100>;
+ reg = <0x12dd0000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
@@ -180,7 +180,7 @@
rtc: rtc@101e0000 {
compatible = "samsung,s3c6410-rtc";
- reg = <0x101E0000 0x100>;
+ reg = <0x101e0000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -198,7 +198,7 @@
dp: dp-controller@145b0000 {
compatible = "samsung,exynos5-dp";
- reg = <0x145B0000 0x1000>;
+ reg = <0x145b0000 0x1000>;
interrupts = <10 3>;
interrupt-parent = <&combiner>;
status = "disabled";
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index f7795f2d0f0e..d586189966da 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -23,6 +23,11 @@
reg = <0x40000000 0x80000000>;
};
+ aliases {
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_2;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
@@ -30,42 +35,42 @@
gpio-keys {
compatible = "gpio-keys";
- menu {
+ key-menu {
label = "SW-TACT2";
gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
wakeup-source;
};
- home {
+ key-home {
label = "SW-TACT3";
gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
- up {
+ key-up {
label = "SW-TACT4";
gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
wakeup-source;
};
- down {
+ key-down {
label = "SW-TACT5";
gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
wakeup-source;
};
- back {
+ key-back {
label = "SW-TACT6";
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
wakeup-source;
};
- wakeup {
+ key-wakeup {
label = "SW-TACT7";
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -73,6 +78,19 @@
};
};
+ /*
+ * For unknown reasons HDMI-DDC does not work with Exynos I2C
+ * controllers. Lets use software I2C over GPIO pins as a workaround.
+ */
+ i2c_ddc: i2c-10 {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_gpio_bus>;
+ sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ };
+
panel: panel {
compatible = "boe,hv070wsa-100";
power-supply = <&vcc_3v3_reg>;
@@ -179,12 +197,15 @@
vddio-supply = <&vcc_1v8_reg>;
vddlvds-supply = <&vcc_3v3_reg>;
reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
- #address-cells = <1>;
- #size-cells = <0>;
- port@1 {
- reg = <1>;
- bridge_out_ep: endpoint {
- remote-endpoint = <&panel_ep>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@1 {
+ reg = <1>;
+ bridge_out_ep: endpoint {
+ remote-endpoint = <&panel_ep>;
+ };
};
};
};
@@ -524,8 +545,8 @@
SPKVDD1-supply = <&main_dc_reg>;
SPKVDD2-supply = <&main_dc_reg>;
- wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>;
- wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>;
+ wlf,ldo1ena-gpios = <&gpb0 0 GPIO_ACTIVE_HIGH>;
+ wlf,ldo2ena-gpios = <&gpb0 1 GPIO_ACTIVE_HIGH>;
};
};
@@ -573,6 +594,7 @@
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-ddr-1_8v;
};
&mmc_2 {
@@ -615,24 +637,6 @@
status = "okay";
};
-&soc {
- /*
- * For unknown reasons HDMI-DDC does not work with Exynos I2C
- * controllers. Lets use software I2C over GPIO pins as a workaround.
- */
- i2c_ddc: i2c-10 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_gpio_bus>;
- status = "okay";
- compatible = "i2c-gpio";
- sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
&usbdrd {
vdd10-supply = <&ldo15_reg>;
vdd33-supply = <&ldo12_reg>;
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 918947a3897e..48732edadff1 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -9,7 +9,7 @@
* tree nodes are listed in this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
&pinctrl_0 {
gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 21fbbf3d8684..bb623726ef1e 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -17,6 +17,8 @@
compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
aliases {
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_2;
};
memory@40000000 {
@@ -129,7 +131,7 @@
samsung,i2c-max-bus-freq = <20000>;
eeprom@50 {
- compatible = "samsung,s524ad0xd1";
+ compatible = "samsung,s524ad0xd1", "atmel,24c128";
reg = <0x50>;
};
@@ -289,7 +291,7 @@
samsung,i2c-max-bus-freq = <20000>;
eeprom@51 {
- compatible = "samsung,s524ad0xd1";
+ compatible = "samsung,s524ad0xd1", "atmel,24c128";
reg = <0x51>;
};
@@ -350,6 +352,7 @@
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-ddr-1_8v;
};
&mmc_2 {
@@ -391,7 +394,7 @@
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "w25x80";
+ compatible = "winbond,w25x80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index c15ecfc4077d..59b2cc35c37b 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -15,6 +15,9 @@
/ {
aliases {
i2c104 = &i2c_104;
+ mmc0 = &mmc_0; /* eMMC */
+ mmc1 = &mmc_2; /* SD */
+ mmc2 = &mmc_3; /* WiFi */
};
memory@40000000 {
@@ -32,7 +35,7 @@
pinctrl-names = "default";
pinctrl-0 = <&power_key_irq &lid_irq>;
- power {
+ power-key {
label = "Power";
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -549,6 +552,7 @@
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-ddr-1_8v;
};
/* uSD card */
diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts
index 0a47597d6f0d..3d32c3476e84 100644
--- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts
+++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts
@@ -27,7 +27,7 @@
};
codec {
- sound-dai = <&max98090 0>, <&hdmi>;
+ sound-dai = <&max98090>, <&hdmi>;
};
};
};
@@ -42,7 +42,7 @@
pinctrl-0 = <&max98090_irq>;
clocks = <&pmu_system_controller 0>;
clock-names = "mclk";
- #sound-dai-cells = <1>;
+ #sound-dai-cells = <0>;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index 24609bb20158..c12bb17631b7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -23,6 +23,11 @@
reg = <0x40000000 0x80000000>;
};
+ aliases {
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_1;
+ };
+
chosen {
bootargs = "console=tty1";
stdout-path = "serial3:115200n8";
@@ -33,7 +38,7 @@
pinctrl-names = "default";
pinctrl-0 = <&power_key_irq>, <&lid_irq>;
- power {
+ power-key {
label = "Power";
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -431,6 +436,7 @@
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-ddr-1_8v;
};
/*
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 5baaa7eb71a4..1a4c6c028d03 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -30,10 +30,6 @@
gsc1 = &gsc_1;
gsc2 = &gsc_2;
gsc3 = &gsc_3;
- mshc0 = &mmc_0;
- mshc1 = &mmc_1;
- mshc2 = &mmc_2;
- mshc3 = &mmc_3;
i2c4 = &i2c_4;
i2c5 = &i2c_5;
i2c6 = &i2c_6;
@@ -81,7 +77,7 @@
};
};
- cpu0_opp_table: opp-table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -216,14 +212,14 @@
pd_disp1: power-domain@100440a0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x100440A0 0x20>;
+ reg = <0x100440a0 0x20>;
#power-domain-cells = <0>;
label = "DISP1";
};
pd_mau: power-domain@100440c0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x100440C0 0x20>;
+ reg = <0x100440c0 0x20>;
#power-domain-cells = <0>;
label = "MAU";
};
@@ -236,7 +232,7 @@
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5250-audss-clock";
- reg = <0x03810000 0x0C>;
+ reg = <0x03810000 0x0c>;
#clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
@@ -245,8 +241,9 @@
};
timer@101c0000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x101C0000 0x800>;
+ compatible = "samsung,exynos5250-mct",
+ "samsung,exynos4210-mct";
+ reg = <0x101c0000 0x800>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupts-extended = <&combiner 23 3>,
@@ -289,7 +286,7 @@
};
pmu_system_controller: system-controller@10040000 {
- compatible = "samsung,exynos5250-pmu", "syscon";
+ compatible = "samsung,exynos5250-pmu", "simple-mfd", "syscon";
reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
@@ -297,11 +294,21 @@
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
+
+ dp_phy: dp-phy {
+ compatible = "samsung,exynos5250-dp-video-phy";
+ #phy-cells = <0>;
+ };
+
+ mipi_phy: mipi-phy {
+ compatible = "samsung,s5pv210-mipi-video-phy";
+ #phy-cells = <1>;
+ };
};
watchdog@101d0000 {
compatible = "samsung,exynos5250-wdt";
- reg = <0x101D0000 0x100>;
+ reg = <0x101d0000 0x100>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
@@ -321,7 +328,7 @@
rotator: rotator@11c00000 {
compatible = "samsung,exynos5250-rotator";
- reg = <0x11C00000 0x64>;
+ reg = <0x11c00000 0x64>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
@@ -386,10 +393,10 @@
sata: sata@122f0000 {
compatible = "snps,dwc-ahci";
- reg = <0x122F0000 0x1ff>;
+ reg = <0x122f0000 0x1ff>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
- clock-names = "sata", "sclk_sata";
+ clock-names = "sata", "pclk";
phys = <&sata_phy>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
@@ -409,7 +416,7 @@
/* i2c_0-3 are defined in exynos5.dtsi */
i2c_4: i2c@12ca0000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12CA0000 0x100>;
+ reg = <0x12ca0000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -422,7 +429,7 @@
i2c_5: i2c@12cb0000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12CB0000 0x100>;
+ reg = <0x12cb0000 0x100>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -435,7 +442,7 @@
i2c_6: i2c@12cc0000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12CC0000 0x100>;
+ reg = <0x12cc0000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -448,7 +455,7 @@
i2c_7: i2c@12cd0000 {
compatible = "samsung,s3c2440-i2c";
- reg = <0x12CD0000 0x100>;
+ reg = <0x12cd0000 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -461,7 +468,7 @@
i2c_8: i2c@12ce0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
- reg = <0x12CE0000 0x1000>;
+ reg = <0x12ce0000 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -469,7 +476,7 @@
clock-names = "i2c";
status = "disabled";
- hdmiphy: hdmiphy@38 {
+ hdmiphy: hdmi-phy@38 {
compatible = "samsung,exynos4212-hdmiphy";
reg = <0x38>;
};
@@ -477,7 +484,7 @@
i2c_9: i2c@121d0000 {
compatible = "samsung,exynos5-sata-phy-i2c";
- reg = <0x121D0000 0x100>;
+ reg = <0x121d0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SATA_PHYI2C>;
@@ -607,7 +614,7 @@
i2s1: i2s@12d60000 {
compatible = "samsung,s3c6410-i2s";
status = "disabled";
- reg = <0x12D60000 0x100>;
+ reg = <0x12d60000 0x100>;
dmas = <&pdma1 12>,
<&pdma1 11>;
dma-names = "tx", "rx";
@@ -622,7 +629,7 @@
i2s2: i2s@12d70000 {
compatible = "samsung,s3c6410-i2s";
status = "disabled";
- reg = <0x12D70000 0x100>;
+ reg = <0x12d70000 0x100>;
dmas = <&pdma0 12>,
<&pdma0 11>;
dma-names = "tx", "rx";
@@ -634,17 +641,17 @@
#sound-dai-cells = <1>;
};
- usbdrd: usb3 {
+ usbdrd: usb@12000000 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&clock CLK_USB3>;
clock-names = "usbdrd30";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x12000000 0x10000>;
- usbdrd_dwc3: usb@12000000 {
+ usbdrd_dwc3: usb@0 {
compatible = "snps,dwc3";
- reg = <0x12000000 0x10000>;
+ reg = <0x0 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
@@ -694,24 +701,20 @@
pdma0: dma-controller@121a0000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x121A0000 0x1000>;
+ reg = <0x121a0000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@121b0000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x121B0000 0x1000>;
+ reg = <0x121b0000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
mdma0: dma-controller@10800000 {
@@ -721,19 +724,15 @@
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
mdma1: dma-controller@11c10000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x11C10000 0x1000>;
+ reg = <0x11c10000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
gsc_0: gsc@13e00000 {
@@ -794,7 +793,7 @@
hdmicec: cec@101b0000 {
compatible = "samsung,s5p-cec";
- reg = <0x101B0000 0x200>;
+ reg = <0x101b0000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
@@ -817,19 +816,6 @@
status = "disabled";
};
- dp_phy: video-phy {
- compatible = "samsung,exynos5250-dp-video-phy";
- samsung,pmu-syscon = <&pmu_system_controller>;
- #phy-cells = <0>;
- };
-
- mipi_phy: video-phy@10040710 {
- compatible = "samsung,s5pv210-mipi-video-phy";
- reg = <0x10040710 0x100>;
- #phy-cells = <1>;
- syscon = <&pmu_system_controller>;
- };
-
dsi_0: dsi@14500000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x14500000 0x10000>;
@@ -846,7 +832,7 @@
adc: adc@12d10000 {
compatible = "samsung,exynos-adc-v1";
- reg = <0x12D10000 0x100>;
+ reg = <0x12d10000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ADC>;
clock-names = "adc";
@@ -857,7 +843,7 @@
sysmmu_g2d: sysmmu@10a60000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x10A60000 0x1000>;
+ reg = <0x10a60000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <24 5>;
clock-names = "sysmmu", "master";
@@ -889,7 +875,7 @@
sysmmu_rotator: sysmmu@11d40000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11D40000 0x1000>;
+ reg = <0x11d40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 0>;
clock-names = "sysmmu", "master";
@@ -899,7 +885,7 @@
sysmmu_jpeg: sysmmu@11f20000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11F20000 0x1000>;
+ reg = <0x11f20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 2>;
power-domains = <&pd_gsc>;
@@ -930,7 +916,7 @@
sysmmu_fimc_fd: sysmmu@132a0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x132A0000 0x1000>;
+ reg = <0x132a0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 0>;
clock-names = "sysmmu";
@@ -960,7 +946,7 @@
sysmmu_fimc_mcuctl: sysmmu@132b0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x132B0000 0x1000>;
+ reg = <0x132b0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 4>;
clock-names = "sysmmu";
@@ -970,7 +956,7 @@
sysmmu_fimc_odc: sysmmu@132c0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x132C0000 0x1000>;
+ reg = <0x132c0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <11 0>;
clock-names = "sysmmu";
@@ -980,7 +966,7 @@
sysmmu_fimc_dis0: sysmmu@132d0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x132D0000 0x1000>;
+ reg = <0x132d0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <10 4>;
clock-names = "sysmmu";
@@ -990,7 +976,7 @@
sysmmu_fimc_dis1: sysmmu@132e0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x132E0000 0x1000>;
+ reg = <0x132e0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <9 4>;
clock-names = "sysmmu";
@@ -1000,7 +986,7 @@
sysmmu_fimc_3dnr: sysmmu@132f0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x132F0000 0x1000>;
+ reg = <0x132f0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 6>;
clock-names = "sysmmu";
@@ -1010,7 +996,7 @@
sysmmu_fimc_lite0: sysmmu@13c40000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13C40000 0x1000>;
+ reg = <0x13c40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <3 4>;
power-domains = <&pd_gsc>;
@@ -1021,7 +1007,7 @@
sysmmu_fimc_lite1: sysmmu@13c50000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13C50000 0x1000>;
+ reg = <0x13c50000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <24 1>;
power-domains = <&pd_gsc>;
@@ -1032,7 +1018,7 @@
sysmmu_gsc0: sysmmu@13e80000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13E80000 0x1000>;
+ reg = <0x13e80000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 0>;
power-domains = <&pd_gsc>;
@@ -1043,7 +1029,7 @@
sysmmu_gsc1: sysmmu@13e90000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13E90000 0x1000>;
+ reg = <0x13e90000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 2>;
power-domains = <&pd_gsc>;
@@ -1054,7 +1040,7 @@
sysmmu_gsc2: sysmmu@13ea0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13EA0000 0x1000>;
+ reg = <0x13ea0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 4>;
power-domains = <&pd_gsc>;
@@ -1065,7 +1051,7 @@
sysmmu_gsc3: sysmmu@13eb0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13EB0000 0x1000>;
+ reg = <0x13eb0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 6>;
power-domains = <&pd_gsc>;
@@ -1115,7 +1101,7 @@
&cpu_thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
- thermal-sensors = <&tmu 0>;
+ thermal-sensors = <&tmu>;
cooling-maps {
map0 {
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
index 150607f8103d..43e4a541f479 100644
--- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -9,7 +9,7 @@
* tree nodes are listed in this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
&pinctrl_0 {
gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 3c3b751d4360..d072a7398866 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -18,6 +18,11 @@
reg = <0x20000000 0x80000000>;
};
+ aliases {
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_2;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
@@ -87,8 +92,9 @@
status = "okay";
broken-cd;
cap-mmc-highspeed;
- supports-hs200-mode; /* 200 MHz */
+ mmc-hs200-1_8v;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 56271e7c4587..a97449b4640c 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -177,7 +177,7 @@
clock_g2d: clock-controller@10a00000 {
compatible = "samsung,exynos5260-clock-g2d";
- reg = <0x10A00000 0x10000>;
+ reg = <0x10a00000 0x10000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_top TOP_DOUT_ACLK_G2D_333>;
@@ -187,7 +187,7 @@
clock_mif: clock-controller@10ce0000 {
compatible = "samsung,exynos5260-clock-mif";
- reg = <0x10CE0000 0x10000>;
+ reg = <0x10ce0000 0x10000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
@@ -213,7 +213,7 @@
clock_fsys: clock-controller@122e0000 {
compatible = "samsung,exynos5260-clock-fsys";
- reg = <0x122E0000 0x10000>;
+ reg = <0x122e0000 0x10000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&fin_pll>,
@@ -233,7 +233,7 @@
clock_aud: clock-controller@128c0000 {
compatible = "samsung,exynos5260-clock-aud";
- reg = <0x128C0000 0x10000>;
+ reg = <0x128c0000 0x10000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_top TOP_FOUT_AUD_PLL>,
@@ -247,7 +247,7 @@
clock_isp: clock-controller@133c0000 {
compatible = "samsung,exynos5260-clock-isp";
- reg = <0x133C0000 0x10000>;
+ reg = <0x133c0000 0x10000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_top TOP_DOUT_ACLK_ISP1_266>,
@@ -261,7 +261,7 @@
clock_gscl: clock-controller@13f00000 {
compatible = "samsung,exynos5260-clock-gscl";
- reg = <0x13F00000 0x10000>;
+ reg = <0x13f00000 0x10000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_top TOP_DOUT_ACLK_GSCL_400>,
@@ -333,8 +333,9 @@
};
mct: timer@100b0000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x100B0000 0x1000>;
+ compatible = "samsung,exynos5260-mct",
+ "samsung,exynos4210-mct";
+ reg = <0x100b0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -355,8 +356,8 @@
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x10F00000 0x1000>;
- ranges = <0x0 0x10F00000 0x6000>;
+ reg = <0x10f00000 0x1000>;
+ ranges = <0x0 0x10f00000 0x6000>;
cci_control0: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
@@ -391,18 +392,18 @@
pinctrl_2: pinctrl@128b0000 {
compatible = "samsung,exynos5260-pinctrl";
- reg = <0x128B0000 0x1000>;
+ reg = <0x128b0000 0x1000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@10d50000 {
compatible = "samsung,exynos5260-pmu", "syscon";
- reg = <0x10D50000 0x10000>;
+ reg = <0x10d50000 0x10000>;
};
uart0: serial@12c00000 {
compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
+ reg = <0x12c00000 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
@@ -411,7 +412,7 @@
uart1: serial@12c10000 {
compatible = "samsung,exynos4210-uart";
- reg = <0x12C10000 0x100>;
+ reg = <0x12c10000 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
@@ -420,7 +421,7 @@
uart2: serial@12c20000 {
compatible = "samsung,exynos4210-uart";
- reg = <0x12C20000 0x100>;
+ reg = <0x12c20000 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
@@ -498,7 +499,7 @@
hsi2c_0: i2c@12da0000 {
compatible = "samsung,exynos5260-hsi2c";
- reg = <0x12DA0000 0x1000>;
+ reg = <0x12da0000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -511,7 +512,7 @@
hsi2c_1: i2c@12db0000 {
compatible = "samsung,exynos5260-hsi2c";
- reg = <0x12DB0000 0x1000>;
+ reg = <0x12db0000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -524,7 +525,7 @@
hsi2c_2: i2c@12dc0000 {
compatible = "samsung,exynos5260-hsi2c";
- reg = <0x12DC0000 0x1000>;
+ reg = <0x12dc0000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -537,7 +538,7 @@
hsi2c_3: i2c@12dd0000 {
compatible = "samsung,exynos5260-hsi2c";
- reg = <0x12DD0000 0x1000>;
+ reg = <0x12dd0000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index e54a3391854d..882fc77c4bc4 100644
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -21,6 +21,8 @@
aliases {
ethernet = &ethernet;
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_2;
};
memory@40000000 {
@@ -120,7 +122,6 @@
};
&cpu0_thermal {
- thermal-sensors = <&tmu_cpu0 0>;
polling-delay-passive = <0>;
polling-delay = <0>;
@@ -164,8 +165,7 @@
};
&hsi2c_4 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <400000>;
+ clock-frequency = <400000>;
status = "okay";
usb3503: usb-hub@8 {
@@ -515,6 +515,7 @@
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&ldo20_reg>;
vqmmc-supply = <&ldo11_reg>;
@@ -655,8 +656,8 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@2 {
- compatible = "usb0424,9730";
+ ethernet: ethernet@2 {
+ compatible = "usb424,9730";
reg = <2>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
index 6c7814b4372e..f7b923382892 100644
--- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
@@ -6,7 +6,7 @@
* https://www.hardkernel.com
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
&pinctrl_0 {
gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index b8f953c41c73..bb29b76f6f6a 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -18,6 +18,11 @@
reg = <0x40000000 0x80000000>;
};
+ aliases {
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_2;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
@@ -61,6 +66,7 @@
cap-mmc-highspeed;
broken-cd;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 4d797a9abba4..350b8afa0a3a 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -81,7 +81,7 @@
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5410-audss-clock";
- reg = <0x03810000 0x0C>;
+ reg = <0x03810000 0x0c>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
clock-names = "pll_ref", "pll_in";
@@ -196,8 +196,6 @@
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@121b0000 {
@@ -207,8 +205,6 @@
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
audi2s0: i2s@3830000 {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 946b791faf85..809ddda02e53 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -23,6 +23,11 @@
reg = <0x20000000 0x80000000>;
};
+ aliases {
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_2;
+ };
+
chosen {
stdout-path = "serial3:115200n8";
};
@@ -42,7 +47,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "SW-TACT1";
gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -778,6 +783,7 @@
status = "okay";
non-removable;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi
index d19bc3d266fa..f525b2f5e4e0 100644
--- a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi
+++ b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi
@@ -28,6 +28,11 @@
* for more details.
*/
+ aliases {
+ mmc0 = &mmc_0;
+ mmc2 = &mmc_2;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
@@ -51,7 +56,6 @@
gpio-keys {
compatible = "gpio-keys";
- pinctrl-names = "default";
key-power {
debounce-interval = <10>;
@@ -605,6 +609,7 @@
bus-width = <8>;
cap-mmc-highspeed;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index d6434ec86022..7a48f2b32819 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -31,6 +31,9 @@
aliases {
/* Assign 20 so we don't get confused w/ builtin ones */
i2c20 = &i2c_tunnel;
+ mmc0 = &mmc_0; /* eMMC */
+ mmc1 = &mmc_2; /* uSD */
+ mmc2 = &mmc_1; /* WiFi */
};
backlight: backlight {
@@ -60,7 +63,7 @@
pinctrl-names = "default";
pinctrl-0 = <&power_key_irq &lid_irq>;
- power {
+ power-key {
label = "Power";
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -722,6 +725,7 @@
/* eMMC flash */
&mmc_0 {
status = "okay";
+ mmc-ddr-1_8v;
mmc-hs200-1_8v;
cap-mmc-highspeed;
non-removable;
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index 546ba274f4e5..14cf9c4ca0ed 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -9,7 +9,7 @@
* tree nodes are listed in this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
&pinctrl_0 {
gpy7: gpy7-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 4d7b6d9008a7..e299344e427a 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -21,6 +21,11 @@
reg = <0x20000000 0x80000000>;
};
+ aliases {
+ mmc0 = &mmc_0;
+ mmc1 = &mmc_2;
+ };
+
chosen {
bootargs = "init=/linuxrc";
stdout-path = "serial2:115200n8";
@@ -355,6 +360,7 @@
status = "okay";
broken-cd;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 21b608705049..dd291f1199f2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,9 +19,6 @@
compatible = "samsung,exynos5420", "samsung,exynos5";
aliases {
- mshc0 = &mmc_0;
- mshc1 = &mmc_1;
- mshc2 = &mmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -37,12 +34,123 @@
spi2 = &spi_2;
};
+ bus_disp1: bus-disp1 {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_disp1_fimd: bus-disp1-fimd {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_fsys: bus-fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_fsys2: bus-fsys2 {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_fsys_apb: bus-fsys-apb {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_g2d: bus-g2d {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK333_G2D>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_g2d_acp: bus-g2d-acp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK266_G2D>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+ bus_gen: bus-gen {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK266>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_gscl_scaler: bus-gscl-scaler {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_jpeg: bus-jpeg {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_jpeg_apb: bus-jpeg-apb {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK166>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_mfc: bus-mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK333>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_mscl: bus-mscl {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_noc: bus-noc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK100_NOC>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_peri: bus-peri {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK66>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
+ bus_wcore: bus-wcore {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
+ clock-names = "bus";
+ status = "disabled";
+ };
+
/*
* The 'cpus' node is not present here but instead it is provided
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
*/
- cluster_a15_opp_table: opp-table0 {
+ cluster_a15_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -108,7 +216,7 @@
};
};
- cluster_a7_opp_table: opp-table1 {
+ cluster_a7_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@@ -182,7 +290,7 @@
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5420-audss-clock";
- reg = <0x03810000 0x0C>;
+ reg = <0x03810000 0x0c>;
#clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
@@ -262,37 +370,37 @@
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
- reg = <0x10CA1000 0x200>;
+ reg = <0x10ca1000 0x200>;
status = "disabled";
};
nocp_mem0_1: nocp@10ca1400 {
compatible = "samsung,exynos5420-nocp";
- reg = <0x10CA1400 0x200>;
+ reg = <0x10ca1400 0x200>;
status = "disabled";
};
nocp_mem1_0: nocp@10ca1800 {
compatible = "samsung,exynos5420-nocp";
- reg = <0x10CA1800 0x200>;
+ reg = <0x10ca1800 0x200>;
status = "disabled";
};
nocp_mem1_1: nocp@10ca1c00 {
compatible = "samsung,exynos5420-nocp";
- reg = <0x10CA1C00 0x200>;
+ reg = <0x10ca1c00 0x200>;
status = "disabled";
};
nocp_g3d_0: nocp@11a51000 {
compatible = "samsung,exynos5420-nocp";
- reg = <0x11A51000 0x200>;
+ reg = <0x11a51000 0x200>;
status = "disabled";
};
nocp_g3d_1: nocp@11a51400 {
compatible = "samsung,exynos5420-nocp";
- reg = <0x11A51400 0x200>;
+ reg = <0x11a51400 0x200>;
status = "disabled";
};
@@ -374,14 +482,14 @@
disp_pd: power-domain@100440c0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x100440C0 0x20>;
+ reg = <0x100440c0 0x20>;
#power-domain-cells = <0>;
label = "DISP";
};
mau_pd: power-domain@100440e0 {
compatible = "samsung,exynos4210-pd";
- reg = <0x100440E0 0x20>;
+ reg = <0x100440e0 0x20>;
#power-domain-cells = <0>;
label = "MAU";
};
@@ -437,31 +545,25 @@
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <6>;
- #dma-requests = <16>;
power-domains = <&mau_pd>;
};
pdma0: dma-controller@121a0000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x121A0000 0x1000>;
+ reg = <0x121a0000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
pdma1: dma-controller@121b0000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x121B0000 0x1000>;
+ reg = <0x121b0000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
mdma0: dma-controller@10800000 {
@@ -471,19 +573,15 @@
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
mdma1: dma-controller@11c10000 {
compatible = "arm,pl330", "arm,primecell";
- reg = <0x11C10000 0x1000>;
+ reg = <0x11c10000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in
@@ -517,7 +615,7 @@
i2s1: i2s@12d60000 {
compatible = "samsung,exynos5420-i2s";
- reg = <0x12D60000 0x100>;
+ reg = <0x12d60000 0x100>;
dmas = <&pdma1 12>,
<&pdma1 11>;
dma-names = "tx", "rx";
@@ -533,7 +631,7 @@
i2s2: i2s@12d70000 {
compatible = "samsung,exynos5420-i2s";
- reg = <0x12D70000 0x100>;
+ reg = <0x12d70000 0x100>;
dmas = <&pdma0 12>,
<&pdma0 11>;
dma-names = "tx", "rx";
@@ -595,19 +693,7 @@
status = "disabled";
};
- dp_phy: dp-video-phy {
- compatible = "samsung,exynos5420-dp-video-phy";
- samsung,pmu-syscon = <&pmu_system_controller>;
- #phy-cells = <0>;
- };
-
- mipi_phy: mipi-video-phy {
- compatible = "samsung,s5pv210-mipi-video-phy";
- syscon = <&pmu_system_controller>;
- #phy-cells = <1>;
- };
-
- dsi@14500000 {
+ dsi: dsi@14500000 {
compatible = "samsung,exynos5410-mipi-dsi";
reg = <0x14500000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -622,7 +708,7 @@
hsi2c_8: i2c@12e00000 {
compatible = "samsung,exynos5250-hsi2c";
- reg = <0x12E00000 0x1000>;
+ reg = <0x12e00000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -635,7 +721,7 @@
hsi2c_9: i2c@12e10000 {
compatible = "samsung,exynos5250-hsi2c";
- reg = <0x12E10000 0x1000>;
+ reg = <0x12e10000 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -648,7 +734,7 @@
hsi2c_10: i2c@12e20000 {
compatible = "samsung,exynos5250-hsi2c";
- reg = <0x12E20000 0x1000>;
+ reg = <0x12e20000 0x1000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -675,13 +761,13 @@
#sound-dai-cells = <0>;
};
- hdmiphy: hdmiphy@145d0000 {
- reg = <0x145D0000 0x20>;
+ hdmiphy: hdmi-phy@145d0000 {
+ reg = <0x145d0000 0x20>;
};
hdmicec: cec@101b0000 {
compatible = "samsung,s5p-cec";
- reg = <0x101B0000 0x200>;
+ reg = <0x101b0000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
@@ -706,7 +792,7 @@
rotator: rotator@11c00000 {
compatible = "samsung,exynos5250-rotator";
- reg = <0x11C00000 0x64>;
+ reg = <0x11c00000 0x64>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
@@ -815,7 +901,7 @@
jpeg_0: jpeg@11f50000 {
compatible = "samsung,exynos5420-jpeg";
- reg = <0x11F50000 0x1000>;
+ reg = <0x11f50000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG>;
@@ -824,7 +910,7 @@
jpeg_1: jpeg@11f60000 {
compatible = "samsung,exynos5420-jpeg";
- reg = <0x11F60000 0x1000>;
+ reg = <0x11f60000 0x1000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG2>;
@@ -832,7 +918,7 @@
};
pmu_system_controller: system-controller@10040000 {
- compatible = "samsung,exynos5420-pmu", "syscon";
+ compatible = "samsung,exynos5420-pmu", "simple-mfd", "syscon";
reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
@@ -840,6 +926,16 @@
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
+
+ dp_phy: dp-phy {
+ compatible = "samsung,exynos5420-dp-video-phy";
+ #phy-cells = <0>;
+ };
+
+ mipi_phy: mipi-phy {
+ compatible = "samsung,exynos5420-mipi-video-phy";
+ #phy-cells = <1>;
+ };
};
tmu_cpu0: tmu@10060000 {
@@ -889,7 +985,7 @@
sysmmu_g2dr: sysmmu@10a60000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x10A60000 0x1000>;
+ reg = <0x10a60000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <24 5>;
clock-names = "sysmmu", "master";
@@ -899,7 +995,7 @@
sysmmu_g2dw: sysmmu@10a70000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x10A70000 0x1000>;
+ reg = <0x10a70000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 2>;
clock-names = "sysmmu", "master";
@@ -920,7 +1016,7 @@
sysmmu_gscl0: sysmmu@13e80000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13E80000 0x1000>;
+ reg = <0x13e80000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 0>;
clock-names = "sysmmu", "master";
@@ -931,7 +1027,7 @@
sysmmu_gscl1: sysmmu@13e90000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x13E90000 0x1000>;
+ reg = <0x13e90000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 2>;
clock-names = "sysmmu", "master";
@@ -963,7 +1059,7 @@
sysmmu_scaler2r: sysmmu@128a0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x128A0000 0x1000>;
+ reg = <0x128a0000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
@@ -973,7 +1069,7 @@
sysmmu_scaler0w: sysmmu@128c0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x128C0000 0x1000>;
+ reg = <0x128c0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <27 2>;
clock-names = "sysmmu", "master";
@@ -984,7 +1080,7 @@
sysmmu_scaler1w: sysmmu@128d0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x128D0000 0x1000>;
+ reg = <0x128d0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 6>;
clock-names = "sysmmu", "master";
@@ -995,7 +1091,7 @@
sysmmu_scaler2w: sysmmu@128e0000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x128E0000 0x1000>;
+ reg = <0x128e0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <19 6>;
clock-names = "sysmmu", "master";
@@ -1006,7 +1102,7 @@
sysmmu_rotator: sysmmu@11d40000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11D40000 0x1000>;
+ reg = <0x11d40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 0>;
clock-names = "sysmmu", "master";
@@ -1016,7 +1112,7 @@
sysmmu_jpeg0: sysmmu@11f10000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11F10000 0x1000>;
+ reg = <0x11f10000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 2>;
clock-names = "sysmmu", "master";
@@ -1026,7 +1122,7 @@
sysmmu_jpeg1: sysmmu@11f20000 {
compatible = "samsung,exynos-sysmmu";
- reg = <0x11F20000 0x1000>;
+ reg = <0x11f20000 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
@@ -1076,118 +1172,6 @@
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};
-
- bus_wcore: bus-wcore {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_noc: bus-noc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK100_NOC>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_fsys_apb: bus-fsys-apb {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_fsys: bus-fsys {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_fsys2: bus-fsys2 {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_mfc: bus-mfc {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK333>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_gen: bus-gen {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK266>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_peri: bus-peri {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK66>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_g2d: bus-g2d {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK333_G2D>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_g2d_acp: bus-g2d-acp {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK266_G2D>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_jpeg: bus-jpeg {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_jpeg_apb: bus-jpeg-apb {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK166>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_disp1_fimd: bus-disp1-fimd {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_disp1: bus-disp1 {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_gscl_scaler: bus-gscl-scaler {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
- clock-names = "bus";
- status = "disabled";
- };
-
- bus_mscl: bus-mscl {
- compatible = "samsung,exynos-bus";
- clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
- clock-names = "bus";
- status = "disabled";
- };
};
thermal-zones {
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2f65dcf6ba73..2f5b8602e020 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -16,7 +16,11 @@
/ {
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x7EA00000>;
+ reg = <0x40000000 0x7ea00000>;
+ };
+
+ aliases {
+ mmc2 = &mmc_2;
};
chosen {
@@ -35,7 +39,7 @@
};
};
- bus_wcore_opp_table: opp-table2 {
+ bus_wcore_opp_table: opp-table-2 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
@@ -61,7 +65,7 @@
};
};
- bus_noc_opp_table: opp-table3 {
+ bus_noc_opp_table: opp-table-3 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@@ -79,7 +83,7 @@
};
};
- bus_fsys_apb_opp_table: opp-table4 {
+ bus_fsys_apb_opp_table: opp-table-4 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@@ -91,7 +95,7 @@
};
};
- bus_fsys2_opp_table: opp-table5 {
+ bus_fsys2_opp_table: opp-table-5 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@@ -106,7 +110,7 @@
};
};
- bus_mfc_opp_table: opp-table6 {
+ bus_mfc_opp_table: opp-table-6 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@@ -127,7 +131,7 @@
};
};
- bus_gen_opp_table: opp-table7 {
+ bus_gen_opp_table: opp-table-7 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
@@ -145,7 +149,7 @@
};
};
- bus_peri_opp_table: opp-table8 {
+ bus_peri_opp_table: opp-table-8 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@@ -154,7 +158,7 @@
};
};
- bus_g2d_opp_table: opp-table9 {
+ bus_g2d_opp_table: opp-table-9 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@@ -175,7 +179,7 @@
};
};
- bus_g2d_acp_opp_table: opp-table10 {
+ bus_g2d_acp_opp_table: opp-table-10 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
@@ -193,7 +197,7 @@
};
};
- bus_jpeg_opp_table: opp-table11 {
+ bus_jpeg_opp_table: opp-table-11 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@@ -211,7 +215,7 @@
};
};
- bus_jpeg_apb_opp_table: opp-table12 {
+ bus_jpeg_apb_opp_table: opp-table-12 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@@ -229,7 +233,7 @@
};
};
- bus_disp1_fimd_opp_table: opp-table13 {
+ bus_disp1_fimd_opp_table: opp-table-13 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@@ -241,7 +245,7 @@
};
};
- bus_disp1_opp_table: opp-table14 {
+ bus_disp1_opp_table: opp-table-14 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@@ -256,7 +260,7 @@
};
};
- bus_gscl_opp_table: opp-table15 {
+ bus_gscl_opp_table: opp-table-15 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@@ -271,7 +275,7 @@
};
};
- bus_mscl_opp_table: opp-table16 {
+ bus_mscl_opp_table: opp-table-16 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@@ -292,7 +296,7 @@
};
};
- dmc_opp_table: opp-table17 {
+ dmc_opp_table: opp-table-17 {
compatible = "operating-points-v2";
opp00 {
@@ -333,8 +337,6 @@
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
- #address-cells = <1>;
- #size-cells = <0>;
tRFC-min-tck = <17>;
tRRD-min-tck = <2>;
@@ -358,10 +360,9 @@
tCKESR-min-tck = <2>;
tMRD-min-tck = <5>;
- timings_samsung_K3QF2F20DB_800mhz: timings@800000000 {
+ timings_samsung_K3QF2F20DB_800mhz: timings {
compatible = "jedec,lpddr3-timings";
- /* workaround: 'reg' shows max-freq */
- reg = <800000000>;
+ max-freq = <800000000>;
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
index d91f7fa2cf80..5e4280393706 100644
--- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
@@ -8,6 +8,7 @@
*/
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include "exynos5422-odroid-core.dtsi"
/ {
@@ -19,7 +20,8 @@
compatible = "pwm-leds";
led-1 {
- label = "blue:heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
max-brightness = <255>;
@@ -29,7 +31,7 @@
thermal-zones {
cpu0_thermal: cpu0-thermal {
- thermal-sensors = <&tmu_cpu0 0>;
+ thermal-sensors = <&tmu_cpu0>;
trips {
cpu0_alert0: cpu-alert-0 {
temperature = <70000>; /* millicelsius */
@@ -84,7 +86,7 @@
};
};
cpu1_thermal: cpu1-thermal {
- thermal-sensors = <&tmu_cpu1 0>;
+ thermal-sensors = <&tmu_cpu1>;
trips {
cpu1_alert0: cpu-alert-0 {
temperature = <70000>;
@@ -128,7 +130,7 @@
};
};
cpu2_thermal: cpu2-thermal {
- thermal-sensors = <&tmu_cpu2 0>;
+ thermal-sensors = <&tmu_cpu2>;
trips {
cpu2_alert0: cpu-alert-0 {
temperature = <70000>;
@@ -172,7 +174,7 @@
};
};
cpu3_thermal: cpu3-thermal {
- thermal-sensors = <&tmu_cpu3 0>;
+ thermal-sensors = <&tmu_cpu3>;
trips {
cpu3_alert0: cpu-alert-0 {
temperature = <70000>;
@@ -216,7 +218,7 @@
};
};
gpu_thermal: gpu-thermal {
- thermal-sensors = <&tmu_gpu 0>;
+ thermal-sensors = <&tmu_gpu>;
trips {
gpu_alert0: gpu-alert-0 {
temperature = <70000>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index a6961ff24030..b4a851aa8881 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -13,6 +13,10 @@
#include "exynos5422-odroid-core.dtsi"
/ {
+ aliases {
+ mmc0 = &mmc_0;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -50,7 +54,7 @@
thermal-zones {
cpu0_thermal: cpu0-thermal {
- thermal-sensors = <&tmu_cpu0 0>;
+ thermal-sensors = <&tmu_cpu0>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@@ -139,7 +143,7 @@
};
};
cpu1_thermal: cpu1-thermal {
- thermal-sensors = <&tmu_cpu1 0>;
+ thermal-sensors = <&tmu_cpu1>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@@ -212,7 +216,7 @@
};
};
cpu2_thermal: cpu2-thermal {
- thermal-sensors = <&tmu_cpu2 0>;
+ thermal-sensors = <&tmu_cpu2>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@@ -285,7 +289,7 @@
};
};
cpu3_thermal: cpu3-thermal {
- thermal-sensors = <&tmu_cpu3 0>;
+ thermal-sensors = <&tmu_cpu3>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@@ -358,7 +362,7 @@
};
};
gpu_thermal: gpu-thermal {
- thermal-sensors = <&tmu_gpu 0>;
+ thermal-sensors = <&tmu_gpu>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@@ -472,6 +476,7 @@
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
bus-width = <8>;
cap-mmc-highspeed;
+ mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
max-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 62c5928aa994..e3154a1cae23 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -113,13 +113,13 @@
#size-cells = <0>;
hub@1 {
- compatible = "usb0424,9514";
+ compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
- compatible = "usb0424,ec00";
+ ethernet: ethernet@1 {
+ compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index cecaeb69e623..a378d4937ff7 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -80,13 +80,13 @@
#size-cells = <0>;
hub@1 {
- compatible = "usb0424,9514";
+ compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
- compatible = "usb0424,ec00";
+ ethernet: ethernet@1 {
+ compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 1c24f9b35973..f5fb617f46bd 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -9,6 +9,7 @@
*/
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5422-odroidxu3-common.dtsi"
@@ -21,7 +22,8 @@
compatible = "pwm-leds";
led-1 {
- label = "blue:heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
max-brightness = <255>;
diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts
new file mode 100644
index 000000000000..c35261a338ff
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts
@@ -0,0 +1,679 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Galaxy S5 (SM-G900H) device-tree source
+ *
+ * Copyright (c) 2023 Markuss Broks
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "exynos5800.dtsi"
+#include "exynos5422-cpus.dtsi"
+
+/ {
+ model = "Samsung Galaxy S5 (SM-G900H)";
+ compatible = "samsung,k3g", "samsung,exynos5800", \
+ "samsung,exynos5";
+
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &mmc_0;
+ };
+
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x80000000>; /* 2 GiB */
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5420-oscclk";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ firmware@2073000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x02073000 0x1000>;
+ };
+
+ tsp_vdd: regulator-tsp-vdd-en {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_vdd_en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpy3 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&buck4_reg>;
+};
+
+&hsi2c_7 {
+ status = "okay";
+
+ pmic@66 {
+ compatible = "samsung,s2mps11-pmic";
+ reg = <0x66>;
+
+ interrupt-parent = <&gpx0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&s2mps11_irq>;
+
+ s2mps11_osc: clocks {
+ compatible = "samsung,s2mps11-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps11_ap",
+ "s2mps11_cp", "s2mps11_bt";
+ };
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "VDD_MIF";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "VDD_ARM";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "VDD_INT";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "VDD_G3D";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VDD_MEM";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "VDD_KFC";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "VIN_LLDO";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "VIN_MLDO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
+ regulator-always-on;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "VIN_HLDO";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-always-on;
+ };
+
+ buck10_reg: BUCK10 {
+ regulator-name = "VDD_CAM_ISP";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3550000>;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "VDD_APIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VDD_APIO_MMC01";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDD_ADC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDD_HRM_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VDD_MIPI";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VDD_MIPI_PLL_ABB1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD_VTF";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "VDD_UOTG";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDDQ_PRE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD_HSIC_1V0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD_HSIC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDD_APIO_MMC2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD_MOTOR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD_CAM1_2V8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo17_reg: LDO17 {
+ /* Unused */
+ regulator-name = "VDD_LDO17";
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-name = "VDD_CODEC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VDD_VMMC";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDD_CAM1_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VDD_CAM_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDD_CAM0_S_CORE";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "VDD_MIFS";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VDD_MHL_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "VDD_LCD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "VDD_CAM0_AF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "VDD_G3DS";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "VDD_LCD_3V0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo29_reg: LDO29 {
+ /* Unused */
+ regulator-name = "VDD_LDO29";
+ };
+
+ ldo30_reg: LDO30 {
+ regulator-name = "VDD_TOUCH";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo31_reg: LDO31 {
+ regulator-name = "VDD_COMP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo32_reg: LDO32 {
+ regulator-name = "VDD_TOUCH_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo33_reg: LDO33 {
+ regulator-name = "VDD_MHL_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo34_reg: LDO34 {
+ regulator-name = "VDD_HRM_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo35_reg: LDO35 {
+ regulator-name = "VDD_SIL";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo36_reg: LDO36 {
+ /* Unused */
+ regulator-name = "VDD_LDO36";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3950000>;
+ };
+
+ ldo37_reg: LDO37 {
+ /* Unused */
+ regulator-name = "VDD_LDO37";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3950000>;
+ };
+
+ ldo38_reg: LDO38 {
+ regulator-name = "VDD_KEY_LED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c_0 {
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&gpx1>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ vio-supply = <&ldo32_reg>;
+ vdd-supply = <&tsp_vdd>;
+ syna,startup-delay-ms = <100>;
+
+ pinctrl-0 = <&touch_irq>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+/* eMMC flash */
+&mmc_0 {
+ status = "okay";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ cap-mmc-highspeed;
+ non-removable;
+ clock-frequency = <400000000>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ samsung,dw-mshc-hs400-timing = <0 2>;
+ samsung,read-strobe-delay = <90>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>;
+ bus-width = <8>;
+};
+
+&pinctrl_0 {
+ s2mps11_irq: s2mps11-irq-pins {
+ samsung,pins = "gpx0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ touch_irq: touch-irq-pins {
+ samsung,pins = "gpx1-6";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&timer {
+ arm,cpu-registers-not-fw-configured;
+};
+
+&tmu_cpu0 {
+ vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu1 {
+ vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu2 {
+ vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu3 {
+ vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_gpu {
+ vtmu-supply = <&ldo10_reg>;
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "peripheral";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "peripheral";
+};
+
+&usbdrd3_0 {
+ vdd33-supply = <&ldo9_reg>;
+ vdd10-supply = <&ldo11_reg>;
+};
+
+&usbdrd3_1 {
+ vdd33-supply = <&ldo9_reg>;
+ vdd10-supply = <&ldo11_reg>;
+};
diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
index 982752e1df24..8c0e1716c0b3 100644
--- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
+++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
@@ -9,6 +9,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
led-controller-1 {
@@ -16,6 +17,8 @@
led-1 {
label = "green:mmc0";
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ color = <LED_COLOR_ID_GREEN>;
pwms = <&pwm 1 2000000 0>;
pwm-names = "pwm1";
/*
@@ -27,7 +30,8 @@
};
led-2 {
- label = "blue:heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
max-brightness = <255>;
@@ -40,6 +44,8 @@
led-3 {
label = "red:microSD";
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc1";
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 2ddb7a5f12b3..5c799886c275 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -74,7 +74,8 @@
};
mct: timer@101c0000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos5420-mct",
+ "samsung,exynos4210-mct";
reg = <0x101c0000 0xb00>;
interrupts-extended = <&combiner 23 3>,
<&combiner 23 4>,
@@ -141,15 +142,15 @@
status = "disabled";
};
- usbdrd3_0: usb3-0 {
+ usbdrd3_0: usb@12000000 {
compatible = "samsung,exynos5250-dwusb3";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x12000000 0x10000>;
- usbdrd_dwc3_0: usb@12000000 {
+ usbdrd_dwc3_0: usb@0 {
compatible = "snps,dwc3";
- reg = <0x12000000 0x10000>;
+ reg = <0x0 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
@@ -163,15 +164,15 @@
#phy-cells = <1>;
};
- usbdrd3_1: usb3-1 {
+ usbdrd3_1: usb@12400000 {
compatible = "samsung,exynos5250-dwusb3";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x12400000 0x10000>;
- usbdrd_dwc3_1: usb@12400000 {
+ usbdrd_dwc3_1: usb@0 {
compatible = "snps,dwc3";
- reg = <0x12400000 0x10000>;
+ reg = <0x0 0x10000>;
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis_u3_susphy_quirk;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 4ee76281979c..1f544f12da6c 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -29,6 +29,9 @@
aliases {
/* Assign 20 so we don't get confused w/ builtin ones */
i2c20 = &i2c_tunnel;
+ mmc0 = &mmc_0; /* eMMC */
+ mmc1 = &mmc_2; /* SD */
+ mmc2 = &mmc_1; /* WiFi */
};
backlight: backlight {
@@ -59,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <&power_key_irq &lid_irq>;
- power {
+ power-key {
label = "Power";
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -703,6 +706,7 @@
/* eMMC flash */
&mmc_0 {
status = "okay";
+ mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 526729dad53f..8328ddb3b02f 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -148,6 +148,10 @@
};
};
+&dsi {
+ compatible = "samsung,exynos5422-mipi-dsi";
+};
+
&mfc {
compatible = "samsung,mfc-v8";
};
diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
index eba1c94ed7f7..138c47e1ac1b 100644
--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
@@ -80,6 +80,15 @@
#cooling-cells = <2>;
};
+ /*
+ * This is the type B USB connector on the device,
+ * a GPIO-controlled USB VBUS detect
+ */
+ usb1_phy: phy {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ #phy-cells = <0>;
+ vbus-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+ };
/* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
i2c {
@@ -164,6 +173,8 @@
compatible = "cortina,gemini-flash", "jedec-flash";
status = "okay";
reg = <0x30000000 0x00080000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
/*
* This "RedBoot" is the Storlink derivative.
@@ -300,5 +311,13 @@
ide@63000000 {
status = "okay";
};
+
+ usb@69000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ usb-phy = <&usb1_phy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_default_pins>;
+ };
};
};
diff --git a/arch/arm/boot/dts/gemini-ns2502.dts b/arch/arm/boot/dts/gemini-ns2502.dts
index 704abd212df5..e6eeb35e8819 100644
--- a/arch/arm/boot/dts/gemini-ns2502.dts
+++ b/arch/arm/boot/dts/gemini-ns2502.dts
@@ -39,10 +39,6 @@
phy0: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
- /* We lack the knowledge of necessary GPIO to achieve
- * Gigabit
- */
- max-speed = <100>;
};
};
};
@@ -50,7 +46,7 @@
&ethernet {
status = "okay";
ethernet-port@0 {
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};
};
@@ -65,30 +61,9 @@
pinctrl-1 = <&pflash_disabled_pins>;
partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "RedBoot";
- reg = <0x00000000 0x00020000>;
- };
- partition@20000 {
- label = "kernel";
- reg = <0x00020000 0x00700000>;
- };
- partition@720000 {
- label = "VCTL";
- reg = <0x00720000 0x00020000>;
- };
- partition@740000 {
- label = "CurConf";
- reg = <0x00740000 0x000a0000>;
- };
- partition@7e0000 {
- label = "FIS";
- reg = <0x007e0000 0x00010000>;
- };
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x7e0000 */
+ fis-index-block = <0x3f>;
};
};
diff --git a/arch/arm/boot/dts/gemini-ssi1328.dts b/arch/arm/boot/dts/gemini-ssi1328.dts
index 2b3e7db84fed..42e85f07cf76 100644
--- a/arch/arm/boot/dts/gemini-ssi1328.dts
+++ b/arch/arm/boot/dts/gemini-ssi1328.dts
@@ -40,10 +40,6 @@
phy0: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
- /* We lack the knowledge of necessary GPIO to achieve
- * Gigabit
- */
- max-speed = <100>;
};
/* WAN ICPlus IP101A */
phy1: ethernet-phy@2 {
diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts
index de3c4416b0fb..3c88c59ab481 100644
--- a/arch/arm/boot/dts/gemini-wbd111.dts
+++ b/arch/arm/boot/dts/gemini-wbd111.dts
@@ -87,33 +87,10 @@
/* 8MB of flash */
reg = <0x30000000 0x00800000>;
- partition@0 {
- label = "RedBoot";
- reg = <0x00000000 0x00020000>;
- read-only;
- };
- partition@20000 {
- label = "kernel";
- reg = <0x00020000 0x00100000>;
- };
- partition@120000 {
- label = "rootfs";
- reg = <0x00120000 0x006a0000>;
- };
- partition@7c0000 {
- label = "VCTL";
- reg = <0x007c0000 0x00010000>;
- read-only;
- };
- partition@7d0000 {
- label = "cfg";
- reg = <0x007d0000 0x00010000>;
- read-only;
- };
- partition@7e0000 {
- label = "FIS";
- reg = <0x007e0000 0x00010000>;
- read-only;
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x7e0000 */
+ fis-index-block = <0x3f>;
};
};
diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts
index e5ceaadbcc1a..ff72bbc4db3e 100644
--- a/arch/arm/boot/dts/gemini-wbd222.dts
+++ b/arch/arm/boot/dts/gemini-wbd222.dts
@@ -91,33 +91,10 @@
/* 8MB of flash */
reg = <0x30000000 0x00800000>;
- partition@0 {
- label = "RedBoot";
- reg = <0x00000000 0x00020000>;
- read-only;
- };
- partition@20000 {
- label = "kernel";
- reg = <0x00020000 0x00100000>;
- };
- partition@120000 {
- label = "rootfs";
- reg = <0x00120000 0x006a0000>;
- };
- partition@7c0000 {
- label = "VCTL";
- reg = <0x007c0000 0x00010000>;
- read-only;
- };
- partition@7d0000 {
- label = "cfg";
- reg = <0x007d0000 0x00010000>;
- read-only;
- };
- partition@7e0000 {
- label = "FIS";
- reg = <0x007e0000 0x00010000>;
- read-only;
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x7e0000 */
+ fis-index-block = <0x3f>;
};
};
diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi
index e836bd0818d4..befe322bd7de 100644
--- a/arch/arm/boot/dts/gemini.dtsi
+++ b/arch/arm/boot/dts/gemini.dtsi
@@ -22,8 +22,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pflash_default_pins>;
bank-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
status = "disabled";
};
@@ -441,7 +439,7 @@
};
usb0: usb@68000000 {
- compatible = "cortina,gemini-usb", "faraday,fotg210";
+ compatible = "cortina,gemini-usb", "faraday,fotg200";
reg = <0x68000000 0x1000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_USB0>;
@@ -457,12 +455,14 @@
*/
pinctrl-names = "default";
pinctrl-0 = <&usb_default_pins>;
+ /* Default to host mode */
+ dr_mode = "host";
syscon = <&syscon>;
status = "disabled";
};
usb1: usb@69000000 {
- compatible = "cortina,gemini-usb", "faraday,fotg210";
+ compatible = "cortina,gemini-usb", "faraday,fotg200";
reg = <0x69000000 0x1000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_USB1>;
diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts
index ce356c469e1e..d7f5daecc9dc 100644
--- a/arch/arm/boot/dts/hi3620-hi4511.dts
+++ b/arch/arm/boot/dts/hi3620-hi4511.dts
@@ -24,42 +24,42 @@
amba-bus {
dual_timer0: dual_timer@800000 {
- status = "ok";
+ status = "okay";
};
uart0: serial@b00000 { /* console */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
- status = "ok";
+ status = "okay";
};
uart1: serial@b01000 { /* modem */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
- status = "ok";
+ status = "okay";
};
uart2: serial@b02000 { /* audience */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
- status = "ok";
+ status = "okay";
};
uart3: serial@b03000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
- status = "ok";
+ status = "okay";
};
uart4: serial@b04000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
- status = "ok";
+ status = "okay";
};
pmx0: pinmux@803000 {
diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
index f5691dbc26d2..0210064bf6a5 100644
--- a/arch/arm/boot/dts/hip04-d01.dts
+++ b/arch/arm/boot/dts/hip04-d01.dts
@@ -23,7 +23,7 @@
soc {
uart0: serial@4007000 {
- status = "ok";
+ status = "okay";
};
};
};
diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
new file mode 100644
index 000000000000..3a7382ce40ef
--- /dev/null
+++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE DL360Gen10
+ */
+
+/include/ "hpe-gxp.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
+ model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";
+
+ aliases {
+ serial0 = &uartc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x20000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi
new file mode 100644
index 000000000000..cf735b3c4f35
--- /dev/null
+++ b/arch/arm/boot/dts/hpe-gxp.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GXP
+ */
+
+/dts-v1/;
+/ {
+ model = "Hewlett Packard Enterprise GXP BMC";
+ compatible = "hpe,gxp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L2>;
+ };
+ };
+
+ clocks {
+ pll: clock-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1600000000>;
+ };
+
+ iopclk: clock-1 {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&pll>;
+ };
+ };
+
+ axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+
+ L2: cache-controller@b0040000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xb0040000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ ahb@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc0000000 0x30000000>;
+ dma-ranges;
+
+ vic0: interrupt-controller@eff0000 {
+ compatible = "arm,pl192-vic";
+ reg = <0xeff0000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ vic1: interrupt-controller@80f00000 {
+ compatible = "arm,pl192-vic";
+ reg = <0x80f00000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uarta: serial@e0 {
+ compatible = "ns16550a";
+ reg = <0xe0 0x8>;
+ interrupts = <17>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartb: serial@e8 {
+ compatible = "ns16550a";
+ reg = <0xe8 0x8>;
+ interrupts = <18>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartc: serial@f0 {
+ compatible = "ns16550a";
+ reg = <0xf0 0x8>;
+ interrupts = <19>;
+ interrupt-parent = <&vic0>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ usb0: usb@efe0000 {
+ compatible = "hpe,gxp-ehci", "generic-ehci";
+ reg = <0xefe0000 0x100>;
+ interrupts = <7>;
+ interrupt-parent = <&vic0>;
+ };
+
+ st: timer@80 {
+ compatible = "hpe,gxp-timer";
+ reg = <0x80 0x16>;
+ interrupts = <0>;
+ interrupt-parent = <&vic0>;
+ clocks = <&iopclk>;
+ clock-names = "iop";
+ };
+
+ usb1: usb@efe0100 {
+ compatible = "hpe,gxp-ohci", "generic-ohci";
+ reg = <0xefe0100 0x110>;
+ interrupts = <6>;
+ interrupt-parent = <&vic0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/imx23-pinfunc.h
index 5c0f32ca3a93..468c079f3c2b 100644
--- a/arch/arm/boot/dts/imx23-pinfunc.h
+++ b/arch/arm/boot/dts/imx23-pinfunc.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX23 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
index a6213c590f94..b1d8210f3ecc 100644
--- a/arch/arm/boot/dts/imx23-xfi3.dts
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -158,19 +158,19 @@
default-brightness-level = <6>;
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_pins_a>;
- voldown {
+ key-voldown {
label = "volume-down";
linux,code = <114>;
gpios = <&gpio2 7 0>;
debounce-interval = <20>;
};
- volup {
+ key-volup {
label = "volume-up";
linux,code = <115>;
gpios = <&gpio2 8 0>;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 7f4c602454a5..d19508c8f9ed 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -64,8 +64,6 @@
reg = <0x80004000 0x2000>;
interrupts = <0 14 20 0
13 13 13 13>;
- interrupt-names = "empty", "ssp0", "ssp1", "empty",
- "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <8>;
clocks = <&clks 15>;
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 3f38c2e60a74..c7207ea437c4 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -13,12 +13,12 @@
model = "Eukrea MBIMXSD25";
compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
- bp1 {
+ button {
label = "BP1";
gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index fa8044c21cb8..5f90d72b840b 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -68,7 +68,7 @@
};
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -515,7 +515,7 @@
#interrupt-cells = <2>;
};
- sdma: sdma@53fd4000 {
+ sdma: dma-controller@53fd4000 {
compatible = "fsl,imx25-sdma";
reg = <0x53fd4000 0x4000>;
clocks = <&clks 112>, <&clks 68>;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index fd525c3b16fa..e140307be2e7 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -74,14 +74,14 @@
};
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&aitc>;
ranges;
- aipi@10000000 { /* AIPI1 */
+ aipi1: aipi@10000000 { /* AIPI1 */
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -96,7 +96,7 @@
<&clks IMX27_CLK_DMA_AHB_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <1>;
- #dma-channels = <16>;
+ dma-channels = <16>;
};
wdog: watchdog@10002000 {
@@ -453,7 +453,7 @@
};
};
- aipi@10020000 { /* AIPI2 */
+ aipi2: aipi@10020000 { /* AIPI2 */
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 14a92fe59770..98672932e41b 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -14,67 +14,59 @@
device_type = "memory";
reg = <0x40000000 0x08000000>;
};
+};
- apb@80000000 {
- apbh@80000000 {
- nand-controller@8000c000 {
- pinctrl-names = "default";
- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x300000>;
- };
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
- partition@300000 {
- label = "env";
- reg = <0x300000 0x80000>;
- };
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+ status = "okay";
- partition@380000 {
- label = "env2";
- reg = <0x380000 0x80000>;
- };
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x300000>;
+ };
- partition@400000 {
- label = "dtb";
- reg = <0x400000 0x80000>;
- };
+ partition@300000 {
+ label = "env";
+ reg = <0x300000 0x80000>;
+ };
- partition@480000 {
- label = "splash";
- reg = <0x480000 0x80000>;
- };
+ partition@380000 {
+ label = "env2";
+ reg = <0x380000 0x80000>;
+ };
- partition@500000 {
- label = "kernel";
- reg = <0x500000 0x800000>;
- };
+ partition@400000 {
+ label = "dtb";
+ reg = <0x400000 0x80000>;
+ };
- partition@d00000 {
- label = "rootfs";
- reg = <0xd00000 0xf300000>;
- };
- };
- };
+ partition@480000 {
+ label = "splash";
+ reg = <0x480000 0x80000>;
+ };
- apbx@80040000 {
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
- };
+ partition@500000 {
+ label = "kernel";
+ reg = <0x500000 0x800000>;
};
- ahb@80080000 {
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
+ partition@d00000 {
+ label = "rootfs";
+ reg = <0xd00000 0xf300000>;
};
};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 1b253b47006c..4704b6141836 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -10,166 +10,6 @@
model = "Armadeus Systems APF28Dev docking/development board";
compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28";
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <4>;
- status = "okay";
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-spi";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_apf28dev>;
-
- hog_pins_apf28dev: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D16__GPIO_1_16
- MX28_PAD_LCD_D17__GPIO_1_17
- MX28_PAD_LCD_D18__GPIO_1_18
- MX28_PAD_LCD_D19__GPIO_1_19
- MX28_PAD_LCD_D20__GPIO_1_20
- MX28_PAD_LCD_D21__GPIO_1_21
- MX28_PAD_LCD_D22__GPIO_1_22
- MX28_PAD_GPMI_CE1N__GPIO_0_17
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_apf28dev: lcdif-apf28dev@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- usb0_otg_apf28dev: otg-apf28dev@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D23__GPIO_1_23
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_16bit_pins_a
- &lcdif_pins_apf28dev>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <16>;
- bus-width = <16>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33000033>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <96>;
- hfront-porch = <96>;
- vback-porch = <20>;
- vfront-porch = <21>;
- hsync-len = <64>;
- vsync-len = <4>;
- hsync-active = <1>;
- vsync-active = <1>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
- };
-
- can0: can@80032000 {
- pinctrl-names = "default";
- pinctrl-0 = <&can0_pins_a>;
- xceiver-supply = <&reg_can0_vcc>;
- status = "okay";
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- fsl,lradc-touchscreen-wires = <4>;
- status = "okay";
- };
-
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
- };
-
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>;
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_pins_a>;
- uart-has-rtscts;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
-
- usbphy1: usbphy@8007e000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_otg_apf28dev
- &usb0_id_pins_b>;
- vbus-supply = <&reg_usb0_vbus>;
- status = "okay";
- };
-
- usb1: usb@80090000 {
- status = "okay";
- };
-
- mac1: ethernet@800f4000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac1_pins_a>;
- phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
- };
-
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -223,3 +63,155 @@
};
};
};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ xceiver-supply = <&reg_can0_vcc>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_16bit_pins_a
+ &lcdif_pins_apf28dev>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <16>;
+ bus-width = <16>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <33000033>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <96>;
+ hfront-porch = <96>;
+ vback-porch = <20>;
+ vfront-porch = <21>;
+ hsync-len = <64>;
+ vsync-len = <4>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&lradc {
+ fsl,lradc-touchscreen-wires = <4>;
+ status = "okay";
+};
+
+&mac1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac1_pins_a>;
+ phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_apf28dev>;
+
+ hog_pins_apf28dev: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D16__GPIO_1_16
+ MX28_PAD_LCD_D17__GPIO_1_17
+ MX28_PAD_LCD_D18__GPIO_1_18
+ MX28_PAD_LCD_D19__GPIO_1_19
+ MX28_PAD_LCD_D20__GPIO_1_20
+ MX28_PAD_LCD_D21__GPIO_1_21
+ MX28_PAD_LCD_D22__GPIO_1_22
+ MX28_PAD_GPMI_CE1N__GPIO_0_17
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_apf28dev: lcdif-apf28dev@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ usb0_otg_apf28dev: otg-apf28dev@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D23__GPIO_1_23
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>;
+ status = "okay";
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_cd_cfg &mmc0_sck_cfg>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_otg_apf28dev
+ &usb0_id_pins_b>;
+ vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index b86be320496b..f9bf40d96568 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -11,200 +11,6 @@
reg = <0x40000000 0x04000000>;
};
- apb@80000000 {
- apbh@80000000 {
- nand-controller@8000c000 {
- pinctrl-names = "default";
- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
- status = "okay";
- };
-
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
- bus-width = <4>;
- status = "okay";
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
- bus-width = <4>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_CE1N__GPIO_0_17
- MX28_PAD_GPMI_RDY1__GPIO_0_21
- MX28_PAD_SSP2_MISO__GPIO_2_18
- MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */
- MX28_PAD_PWM3__GPIO_3_28
- MX28_PAD_LCD_RESET__GPIO_3_30
- MX28_PAD_JTAG_RTCK__GPIO_4_20
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_apx4: lcdif-apx4@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP0_DATA4__SSP2_D0
- MX28_PAD_SSP0_DATA5__SSP2_D3
- MX28_PAD_SSP0_DATA6__SSP2_CMD
- MX28_PAD_SSP0_DATA7__SSP2_SCK
- MX28_PAD_SSP2_SS1__SSP2_D1
- MX28_PAD_SSP2_SS2__SSP2_D2
- >;
- fsl,drive-strength = <MXS_DRIVE_8mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP0_DATA7__SSP2_SCK
- >;
- fsl,drive-strength = <MXS_DRIVE_12mA>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_24bit_pins_a
- &lcdif_pins_apx4>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <30000000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <88>;
- hfront-porch = <40>;
- vback-porch = <32>;
- vfront-porch = <13>;
- hsync-len = <48>;
- vsync-len = <3>;
- hsync-active = <1>;
- vsync-active = <1>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
- };
- };
-
- apbx@80040000 {
- saif0: saif@80042000 {
- pinctrl-names = "default";
- pinctrl-0 = <&saif0_pins_a>;
- status = "okay";
- };
-
- saif1: saif@80046000 {
- pinctrl-names = "default";
- pinctrl-0 = <&saif1_pins_a>;
- fsl,saif-master = <&saif0>;
- status = "okay";
- };
-
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- #sound-dai-cells = <0>;
- VDDA-supply = <&reg_3p3v>;
- VDDIO-supply = <&reg_3p3v>;
- clocks = <&saif0>;
- };
-
- pcf8563: rtc@51 {
- compatible = "phg,pcf8563";
- reg = <0x51>;
- };
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_pins_a>;
- status = "okay";
- };
-
- auart1: serial@8006c000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart1_2pins_a>;
- status = "okay";
- };
-
- auart2: serial@8006e000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart2_2pins_a>;
- status = "okay";
- };
-
- usbphy1: usbphy@8007e000 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_a>;
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb1: usb@80090000 {
- status = "okay";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- status = "okay";
- };
- };
-
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -238,3 +44,189 @@
};
};
};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_pins_a>;
+ status = "okay";
+};
+
+&auart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart1_2pins_a>;
+ status = "okay";
+};
+
+&auart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart2_2pins_a>;
+ status = "okay";
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_apx4>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <30000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ vback-porch = <32>;
+ vfront-porch = <13>;
+ hsync-len = <48>;
+ vsync-len = <3>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_3p3v>;
+ clocks = <&saif0>;
+ };
+
+ pcf8563: rtc@51 {
+ compatible = "phg,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_CE1N__GPIO_0_17
+ MX28_PAD_GPMI_RDY1__GPIO_0_21
+ MX28_PAD_SSP2_MISO__GPIO_2_18
+ MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */
+ MX28_PAD_PWM3__GPIO_3_28
+ MX28_PAD_LCD_RESET__GPIO_3_30
+ MX28_PAD_JTAG_RTCK__GPIO_4_20
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_apx4: lcdif-apx4@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA4__SSP2_D0
+ MX28_PAD_SSP0_DATA5__SSP2_D3
+ MX28_PAD_SSP0_DATA6__SSP2_CMD
+ MX28_PAD_SSP0_DATA7__SSP2_SCK
+ MX28_PAD_SSP2_SS1__SSP2_D1
+ MX28_PAD_SSP2_SS2__SSP2_D2
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA7__SSP2_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ status = "okay";
+};
+
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ status = "okay";
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usbphy1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 85aa1cc3ff66..d004b1cbb4ae 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -16,107 +16,6 @@
reg = <0x40000000 0x08000000>;
};
- apb@80000000 {
- apbh@80000000 {
- pinctrl@80018000 {
- ssd1306_cfa10036: ssd1306-10036@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP0_DATA7__GPIO_2_7
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins_cfa10036: leds-10036@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_AUART1_RX__GPIO_3_4
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- usb0_otg_cfa10036: otg-10036@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_RDY0__USB0_ID
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- 0x31c3 /*
- MX28_PAD_PWM3__GPIO_3_28 */
- >;
- fsl,drive-strength = <0>;
- fsl,voltage = <1>;
- fsl,pull-up = <0>;
- };
-
- };
-
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- vmmc-supply = <&reg_vddio_sd0>;
- bus-width = <4>;
- status = "okay";
- };
- };
-
- apbx@80040000 {
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_b>;
- status = "okay";
- };
-
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_b>;
- clock-frequency = <400000>;
- status = "okay";
-
- ssd1306: oled@3c {
- compatible = "solomon,ssd1306fb-i2c";
- pinctrl-names = "default";
- pinctrl-0 = <&ssd1306_cfa10036>;
- reg = <0x3c>;
- reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- solomon,height = <32>;
- solomon,width = <128>;
- solomon,page-offset = <0>;
- solomon,com-lrremap;
- solomon,com-invdir;
- solomon,com-offset = <32>;
- };
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_otg_cfa10036>;
- dr_mode = "peripheral";
- phy_type = "utmi";
- status = "okay";
- };
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -138,3 +37,95 @@
gpio = <&gpio3 28 0>;
};
};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_b>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_b>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ ssd1306: oled@3c {
+ compatible = "solomon,ssd1306fb-i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ssd1306_cfa10036>;
+ reg = <0x3c>;
+ reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ solomon,height = <32>;
+ solomon,width = <128>;
+ solomon,page-offset = <0>;
+ solomon,com-lrremap;
+ solomon,com-invdir;
+ solomon,com-offset = <32>;
+ };
+};
+
+&pinctrl {
+ ssd1306_cfa10036: ssd1306-10036@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA7__GPIO_2_7
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ led_pins_cfa10036: leds-10036@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_RX__GPIO_3_4
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ usb0_otg_cfa10036: otg-10036@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY0__USB0_ID
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x31c3 /*
+ MX28_PAD_PWM3__GPIO_3_28 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_cd_cfg &mmc0_sck_cfg>;
+ vmmc-supply = <&reg_vddio_sd0>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_otg_cfa10036>;
+ dr_mode = "peripheral";
+ phy_type = "utmi";
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index a92b05ef390f..94d6614c1983 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -78,226 +78,6 @@
};
};
- apb@80000000 {
- apbh@80000000 {
- pinctrl@80018000 {
- usb_pins_cfa10049: usb-10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D07__GPIO_0_7
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- i2cmux_pins_cfa10049: i2cmux-10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D22__GPIO_1_22
- MX28_PAD_LCD_D23__GPIO_1_23
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_pins_cfa10049: mac0-10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP2_SS2__GPIO_2_21
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- pca_pins_cfa10049: pca-10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP2_SS0__GPIO_2_19
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- rotary_pins_cfa10049: rotary-10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_I2C0_SCL__GPIO_3_24
- MX28_PAD_I2C0_SDA__GPIO_3_25
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- rotary_btn_pins_cfa10049: rotary-btn-10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SAIF1_SDATA0__GPIO_3_26
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- spi2_pins_cfa10049: spi2-cfa10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP2_SCK__GPIO_2_16
- MX28_PAD_SSP2_MOSI__GPIO_2_17
- MX28_PAD_SSP2_MISO__GPIO_2_18
- MX28_PAD_AUART1_TX__GPIO_3_5
- >;
- fsl,drive-strength = <MXS_DRIVE_8mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- spi3_pins_cfa10049: spi3-cfa10049@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_RDN__GPIO_0_24
- MX28_PAD_GPMI_RESETN__GPIO_0_28
- MX28_PAD_GPMI_CE1N__GPIO_0_17
- MX28_PAD_GPMI_ALE__GPIO_0_26
- MX28_PAD_GPMI_CLE__GPIO_0_27
- >;
- fsl,drive-strength = <MXS_DRIVE_8mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- lcdif_18bit_pins_cfa10049: lcdif-18bit@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D00__LCD_D0
- MX28_PAD_LCD_D01__LCD_D1
- MX28_PAD_LCD_D02__LCD_D2
- MX28_PAD_LCD_D03__LCD_D3
- MX28_PAD_LCD_D04__LCD_D4
- MX28_PAD_LCD_D05__LCD_D5
- MX28_PAD_LCD_D06__LCD_D6
- MX28_PAD_LCD_D07__LCD_D7
- MX28_PAD_LCD_D08__LCD_D8
- MX28_PAD_LCD_D09__LCD_D9
- MX28_PAD_LCD_D10__LCD_D10
- MX28_PAD_LCD_D11__LCD_D11
- MX28_PAD_LCD_D12__LCD_D12
- MX28_PAD_LCD_D13__LCD_D13
- MX28_PAD_LCD_D14__LCD_D14
- MX28_PAD_LCD_D15__LCD_D15
- MX28_PAD_LCD_D16__LCD_D16
- MX28_PAD_LCD_D17__LCD_D17
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_cfa10049: lcdif-evk@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RESET__GPIO_3_30
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- w1_gpio_pins: w1-gpio@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D21__GPIO_1_21
- >;
- fsl,drive-strength = <MXS_DRIVE_8mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>; /* 0 will enable the keeper */
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_18bit_pins_cfa10049
- &lcdif_pins_cfa10049
- &lcdif_pins_cfa10049_pullup>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <18>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <9216000>;
- hactive = <320>;
- vactive = <480>;
- hback-porch = <2>;
- hfront-porch = <2>;
- vback-porch = <2>;
- vfront-porch = <2>;
- hsync-len = <15>;
- vsync-len = <15>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
- };
- };
-
- apbx@80040000 {
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pins_b>;
- status = "okay";
- };
-
- i2c1: i2c@8005a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
- };
-
- usbphy1: usbphy@8007e000 {
- status = "okay";
- };
-
- lradc@80050000 {
- status = "okay";
- fsl,lradc-touchscreen-wires = <4>;
- };
- };
- };
-
- ahb@80080000 {
- usb1: usb@80090000 {
- vbus-supply = <&reg_usb1_vbus>;
- pinctrl-0 = <&usb1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
- };
- };
-
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -315,19 +95,7 @@
};
};
- ahb@80080000 {
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a
- &mac0_pins_cfa10049>;
- phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <100>;
- status = "okay";
- };
- };
-
- spi2 {
+ spi-2 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_cfa10049>;
@@ -351,7 +119,7 @@
};
};
- spi3 {
+ spi-3 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins_cfa10049>;
@@ -388,12 +156,12 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&rotary_btn_pins_cfa10049>;
- rotary_button {
+ rotary-button {
label = "rotary_button";
gpios = <&gpio3 26 1>;
debounce-interval = <10>;
@@ -426,3 +194,225 @@
gpios = <&gpio1 21 0>;
};
};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_18bit_pins_cfa10049
+ &lcdif_pins_cfa10049
+ &lcdif_pins_cfa10049_pullup>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <9216000>;
+ hactive = <320>;
+ vactive = <480>;
+ hback-porch = <2>;
+ hfront-porch = <2>;
+ vback-porch = <2>;
+ vfront-porch = <2>;
+ hsync-len = <15>;
+ vsync-len = <15>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
+&lradc {
+ fsl,lradc-touchscreen-wires = <4>;
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a
+ &mac0_pins_cfa10049>;
+ phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb_pins_cfa10049: usb-10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D07__GPIO_0_7
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ i2cmux_pins_cfa10049: i2cmux-10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D22__GPIO_1_22
+ MX28_PAD_LCD_D23__GPIO_1_23
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mac0_pins_cfa10049: mac0-10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SS2__GPIO_2_21
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ pca_pins_cfa10049: pca-10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SS0__GPIO_2_19
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ rotary_pins_cfa10049: rotary-10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_I2C0_SCL__GPIO_3_24
+ MX28_PAD_I2C0_SDA__GPIO_3_25
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ rotary_btn_pins_cfa10049: rotary-btn-10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF1_SDATA0__GPIO_3_26
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ spi2_pins_cfa10049: spi2-cfa10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__GPIO_2_16
+ MX28_PAD_SSP2_MOSI__GPIO_2_17
+ MX28_PAD_SSP2_MISO__GPIO_2_18
+ MX28_PAD_AUART1_TX__GPIO_3_5
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ spi3_pins_cfa10049: spi3-cfa10049@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDN__GPIO_0_24
+ MX28_PAD_GPMI_RESETN__GPIO_0_28
+ MX28_PAD_GPMI_CE1N__GPIO_0_17
+ MX28_PAD_GPMI_ALE__GPIO_0_26
+ MX28_PAD_GPMI_CLE__GPIO_0_27
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ lcdif_18bit_pins_cfa10049: lcdif-18bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D00__LCD_D0
+ MX28_PAD_LCD_D01__LCD_D1
+ MX28_PAD_LCD_D02__LCD_D2
+ MX28_PAD_LCD_D03__LCD_D3
+ MX28_PAD_LCD_D04__LCD_D4
+ MX28_PAD_LCD_D05__LCD_D5
+ MX28_PAD_LCD_D06__LCD_D6
+ MX28_PAD_LCD_D07__LCD_D7
+ MX28_PAD_LCD_D08__LCD_D8
+ MX28_PAD_LCD_D09__LCD_D9
+ MX28_PAD_LCD_D10__LCD_D10
+ MX28_PAD_LCD_D11__LCD_D11
+ MX28_PAD_LCD_D12__LCD_D12
+ MX28_PAD_LCD_D13__LCD_D13
+ MX28_PAD_LCD_D14__LCD_D14
+ MX28_PAD_LCD_D15__LCD_D15
+ MX28_PAD_LCD_D16__LCD_D16
+ MX28_PAD_LCD_D17__LCD_D17
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_cfa10049: lcdif-evk@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RESET__GPIO_3_30
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ w1_gpio_pins: w1-gpio@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D21__GPIO_1_21
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>; /* 0 will enable the keeper */
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pins_b>;
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <&reg_usb1_vbus>;
+ pinctrl-0 = <&usb1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
index d05c370dfc17..42ba7da48beb 100644
--- a/arch/arm/boot/dts/imx28-cfa10055.dts
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -14,122 +14,7 @@
model = "Crystalfontz CFA-10055 Board";
compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
- apb@80000000 {
- apbh@80000000 {
- pinctrl@80018000 {
- spi2_pins_cfa10055: spi2-cfa10055@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP2_SCK__GPIO_2_16
- MX28_PAD_SSP2_MOSI__GPIO_2_17
- MX28_PAD_SSP2_MISO__GPIO_2_18
- MX28_PAD_AUART1_TX__GPIO_3_5
- >;
- fsl,drive-strength = <MXS_DRIVE_8mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D00__LCD_D0
- MX28_PAD_LCD_D01__LCD_D1
- MX28_PAD_LCD_D02__LCD_D2
- MX28_PAD_LCD_D03__LCD_D3
- MX28_PAD_LCD_D04__LCD_D4
- MX28_PAD_LCD_D05__LCD_D5
- MX28_PAD_LCD_D06__LCD_D6
- MX28_PAD_LCD_D07__LCD_D7
- MX28_PAD_LCD_D08__LCD_D8
- MX28_PAD_LCD_D09__LCD_D9
- MX28_PAD_LCD_D10__LCD_D10
- MX28_PAD_LCD_D11__LCD_D11
- MX28_PAD_LCD_D12__LCD_D12
- MX28_PAD_LCD_D13__LCD_D13
- MX28_PAD_LCD_D14__LCD_D14
- MX28_PAD_LCD_D15__LCD_D15
- MX28_PAD_LCD_D16__LCD_D16
- MX28_PAD_LCD_D17__LCD_D17
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_cfa10055: lcdif-evk@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RESET__GPIO_3_30
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_18bit_pins_cfa10055
- &lcdif_pins_cfa10055
- &lcdif_pins_cfa10055_pullup>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <18>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <9216000>;
- hactive = <320>;
- vactive = <480>;
- hback-porch = <2>;
- hfront-porch = <2>;
- vback-porch = <2>;
- vfront-porch = <2>;
- hsync-len = <15>;
- vsync-len = <15>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- fsl,lradc-touchscreen-wires = <4>;
- status = "okay";
- };
-
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pins_b>;
- status = "okay";
- };
- };
- };
-
- spi2 {
+ spi-2 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_cfa10055>;
@@ -159,3 +44,112 @@
default-brightness-level = <6>;
};
};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_18bit_pins_cfa10055
+ &lcdif_pins_cfa10055
+ &lcdif_pins_cfa10055_pullup>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <9216000>;
+ hactive = <320>;
+ vactive = <480>;
+ hback-porch = <2>;
+ hfront-porch = <2>;
+ vback-porch = <2>;
+ vfront-porch = <2>;
+ hsync-len = <15>;
+ vsync-len = <15>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
+&lradc {
+ fsl,lradc-touchscreen-wires = <4>;
+ status = "okay";
+};
+
+&pinctrl {
+ spi2_pins_cfa10055: spi2-cfa10055@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__GPIO_2_16
+ MX28_PAD_SSP2_MOSI__GPIO_2_17
+ MX28_PAD_SSP2_MISO__GPIO_2_18
+ MX28_PAD_AUART1_TX__GPIO_3_5
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D00__LCD_D0
+ MX28_PAD_LCD_D01__LCD_D1
+ MX28_PAD_LCD_D02__LCD_D2
+ MX28_PAD_LCD_D03__LCD_D3
+ MX28_PAD_LCD_D04__LCD_D4
+ MX28_PAD_LCD_D05__LCD_D5
+ MX28_PAD_LCD_D06__LCD_D6
+ MX28_PAD_LCD_D07__LCD_D7
+ MX28_PAD_LCD_D08__LCD_D8
+ MX28_PAD_LCD_D09__LCD_D9
+ MX28_PAD_LCD_D10__LCD_D10
+ MX28_PAD_LCD_D11__LCD_D11
+ MX28_PAD_LCD_D12__LCD_D12
+ MX28_PAD_LCD_D13__LCD_D13
+ MX28_PAD_LCD_D14__LCD_D14
+ MX28_PAD_LCD_D15__LCD_D15
+ MX28_PAD_LCD_D16__LCD_D16
+ MX28_PAD_LCD_D17__LCD_D17
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_cfa10055: lcdif-evk@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RESET__GPIO_3_30
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pins_b>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts
index c1060bd5f17f..0e15bdfd7281 100644
--- a/arch/arm/boot/dts/imx28-cfa10056.dts
+++ b/arch/arm/boot/dts/imx28-cfa10056.dts
@@ -13,82 +13,7 @@
model = "Crystalfontz CFA-10056 Board";
compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
- apb@80000000 {
- apbh@80000000 {
- pinctrl@80018000 {
- spi2_pins_cfa10056: spi2-cfa10056@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP2_SCK__GPIO_2_16
- MX28_PAD_SSP2_MOSI__GPIO_2_17
- MX28_PAD_SSP2_MISO__GPIO_2_18
- MX28_PAD_AUART1_TX__GPIO_3_5
- >;
- fsl,drive-strength = <MXS_DRIVE_8mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
-
- lcdif_pins_cfa10056: lcdif-10056@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RESET__GPIO_3_30
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_ENABLE>;
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_24bit_pins_a
- &lcdif_pins_cfa10056
- &lcdif_pins_cfa10056_pullup >;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <32000000>;
- hactive = <480>;
- vactive = <800>;
- hback-porch = <2>;
- hfront-porch = <2>;
- vback-porch = <2>;
- vfront-porch = <2>;
- hsync-len = <5>;
- vsync-len = <5>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
- };
- };
- };
-
- spi2 {
+ spi-2 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_cfa10056>;
@@ -111,3 +36,74 @@
};
};
};
+
+&pinctrl {
+ spi2_pins_cfa10056: spi2-cfa10056@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__GPIO_2_16
+ MX28_PAD_SSP2_MOSI__GPIO_2_17
+ MX28_PAD_SSP2_MISO__GPIO_2_18
+ MX28_PAD_AUART1_TX__GPIO_3_5
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ lcdif_pins_cfa10056: lcdif-10056@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RESET__GPIO_3_30
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_cfa10056
+ &lcdif_pins_cfa10056_pullup >;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <32000000>;
+ hactive = <480>;
+ vactive = <800>;
+ hback-porch = <2>;
+ hfront-porch = <2>;
+ vback-porch = <2>;
+ vfront-porch = <2>;
+ hsync-len = <5>;
+ vsync-len = <5>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index 2f7e479dbc74..27602c01f162 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -14,126 +14,6 @@
model = "Crystalfontz CFA-10057 Board";
compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28";
- apb@80000000 {
- apbh@80000000 {
- pinctrl@80018000 {
- usb_pins_cfa10057: usb-10057@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D07__GPIO_0_7
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D00__LCD_D0
- MX28_PAD_LCD_D01__LCD_D1
- MX28_PAD_LCD_D02__LCD_D2
- MX28_PAD_LCD_D03__LCD_D3
- MX28_PAD_LCD_D04__LCD_D4
- MX28_PAD_LCD_D05__LCD_D5
- MX28_PAD_LCD_D06__LCD_D6
- MX28_PAD_LCD_D07__LCD_D7
- MX28_PAD_LCD_D08__LCD_D8
- MX28_PAD_LCD_D09__LCD_D9
- MX28_PAD_LCD_D10__LCD_D10
- MX28_PAD_LCD_D11__LCD_D11
- MX28_PAD_LCD_D12__LCD_D12
- MX28_PAD_LCD_D13__LCD_D13
- MX28_PAD_LCD_D14__LCD_D14
- MX28_PAD_LCD_D15__LCD_D15
- MX28_PAD_LCD_D16__LCD_D16
- MX28_PAD_LCD_D17__LCD_D17
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_cfa10057: lcdif-evk@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_18bit_pins_cfa10057
- &lcdif_pins_cfa10057>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <18>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <30000000>;
- hactive = <480>;
- vactive = <800>;
- hfront-porch = <12>;
- hback-porch = <2>;
- vfront-porch = <5>;
- vback-porch = <3>;
- hsync-len = <2>;
- vsync-len = <2>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- fsl,lradc-touchscreen-wires = <4>;
- status = "okay";
- };
-
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm4_pins_a>;
- status = "okay";
- };
-
- i2c1: i2c@8005a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
- };
-
- usbphy1: usbphy@8007e000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb1: usb@80090000 {
- vbus-supply = <&reg_usb1_vbus>;
- pinctrl-0 = <&usb1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
- };
- };
-
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -151,17 +31,6 @@
};
};
- ahb@80080000 {
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <100>;
- status = "okay";
- };
- };
-
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 4 5000000>;
@@ -169,3 +38,124 @@
default-brightness-level = <7>;
};
};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_18bit_pins_cfa10057
+ &lcdif_pins_cfa10057>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <30000000>;
+ hactive = <480>;
+ vactive = <800>;
+ hfront-porch = <12>;
+ hback-porch = <2>;
+ vfront-porch = <5>;
+ vback-porch = <3>;
+ hsync-len = <2>;
+ vsync-len = <2>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
+&lradc {
+ fsl,lradc-touchscreen-wires = <4>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb_pins_cfa10057: usb-10057@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D07__GPIO_0_7
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D00__LCD_D0
+ MX28_PAD_LCD_D01__LCD_D1
+ MX28_PAD_LCD_D02__LCD_D2
+ MX28_PAD_LCD_D03__LCD_D3
+ MX28_PAD_LCD_D04__LCD_D4
+ MX28_PAD_LCD_D05__LCD_D5
+ MX28_PAD_LCD_D06__LCD_D6
+ MX28_PAD_LCD_D07__LCD_D7
+ MX28_PAD_LCD_D08__LCD_D8
+ MX28_PAD_LCD_D09__LCD_D9
+ MX28_PAD_LCD_D10__LCD_D10
+ MX28_PAD_LCD_D11__LCD_D11
+ MX28_PAD_LCD_D12__LCD_D12
+ MX28_PAD_LCD_D13__LCD_D13
+ MX28_PAD_LCD_D14__LCD_D14
+ MX28_PAD_LCD_D15__LCD_D15
+ MX28_PAD_LCD_D16__LCD_D16
+ MX28_PAD_LCD_D17__LCD_D17
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_cfa10057: lcdif-evk@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4_pins_a>;
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <&reg_usb1_vbus>;
+ pinctrl-0 = <&usb1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 4465fd86785a..931c4d089b26 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -14,93 +14,6 @@
model = "Crystalfontz CFA-10058 Board";
compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28";
- apb@80000000 {
- apbh@80000000 {
- pinctrl@80018000 {
- usb_pins_cfa10058: usb-10058@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D07__GPIO_0_7
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_cfa10058: lcdif-10058@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_24bit_pins_a
- &lcdif_pins_cfa10058>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <30000000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <40>;
- hfront-porch = <40>;
- vback-porch = <13>;
- vfront-porch = <29>;
- hsync-len = <8>;
- vsync-len = <8>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- fsl,lradc-touchscreen-wires = <4>;
- status = "okay";
- };
-
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pins_b>;
- status = "okay";
- };
-
- usbphy1: usbphy@8007e000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb1: usb@80090000 {
- vbus-supply = <&reg_usb1_vbus>;
- pinctrl-0 = <&usb1_pins_a>;
- pinctrl-names = "default";
- status = "okay";
- };
- };
-
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -118,17 +31,6 @@
};
};
- ahb@80080000 {
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <100>;
- status = "okay";
- };
- };
-
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 3 5000000>;
@@ -136,3 +38,91 @@
default-brightness-level = <6>;
};
};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_cfa10058>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <30000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <40>;
+ hfront-porch = <40>;
+ vback-porch = <13>;
+ vfront-porch = <29>;
+ hsync-len = <8>;
+ vsync-len = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
+&lradc {
+ fsl,lradc-touchscreen-wires = <4>;
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb_pins_cfa10058: usb-10058@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D07__GPIO_0_7
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_cfa10058: lcdif-10058@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pins_b>;
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <&reg_usb1_vbus>;
+ pinctrl-0 = <&usb1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
index d451fa018d83..b73020ff1053 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -5,172 +5,13 @@
*/
/dts-v1/;
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "imx28.dtsi"
+#include "imx28-duckbill-2.dts"
/ {
model = "I2SE Duckbill 2 485";
compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x08000000>;
- };
-
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <8>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- non-removable;
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_4bit_pins_b
- &mmc2_cd_cfg &mmc2_sck_cfg_b>;
- bus-width = <4>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_reset_pin: mac0-phy-reset@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_int_pin: mac0-phy-int@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins: leds@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SAIF0_MCLK__GPIO_3_20
- MX28_PAD_SAIF0_LRCLK__GPIO_3_21
- MX28_PAD_I2C0_SCL__GPIO_3_24
- MX28_PAD_I2C0_SDA__GPIO_3_25
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_2pins_a>;
- status = "okay";
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- status = "okay";
- dr_mode = "peripheral";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
- phy-supply = <&reg_3p3v>;
- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <25>;
- phy-handle = <&ethphy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_phy_int_pin>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
- max-speed = <100>;
- };
- };
- };
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- status-red {
- label = "duckbill:red:status";
- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- };
-
- status-green {
- label = "duckbill:green:status";
- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
rs485-red {
label = "duckbill:red:rs485";
gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
@@ -182,3 +23,16 @@
};
};
};
+
+&i2c0 {
+ status = "disabled";
+};
+
+&led_pins {
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF0_MCLK__GPIO_3_20
+ MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+ MX28_PAD_I2C0_SCL__GPIO_3_24
+ MX28_PAD_I2C0_SDA__GPIO_3_25
+ >;
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
index bacb846f99e3..473d99b9b42f 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -5,184 +5,14 @@
*/
/dts-v1/;
-#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "imx28.dtsi"
+#include "imx28-duckbill-2.dts"
/ {
model = "I2SE Duckbill 2 EnOcean";
compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x08000000>;
- };
-
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <8>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- non-removable;
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_4bit_pins_b
- &mmc2_cd_cfg &mmc2_sck_cfg_b>;
- bus-width = <4>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_reset_pin: mac0-phy-reset@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_int_pin: mac0-phy-int@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins: leds@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SAIF0_MCLK__GPIO_3_20
- MX28_PAD_SAIF0_LRCLK__GPIO_3_21
- MX28_PAD_AUART0_CTS__GPIO_3_2
- MX28_PAD_I2C0_SCL__GPIO_3_24
- MX28_PAD_I2C0_SDA__GPIO_3_25
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- enocean_button: enocean-button@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_AUART0_RTS__GPIO_3_3
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_2pins_a>;
- status = "okay";
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- status = "okay";
- dr_mode = "peripheral";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
- phy-supply = <&reg_3p3v>;
- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <25>;
- phy-handle = <&ethphy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_phy_int_pin>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
- max-speed = <100>;
- };
- };
- };
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- status-red {
- label = "duckbill:red:status";
- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- };
-
- status-green {
- label = "duckbill:green:status";
- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
enocean-blue {
label = "duckbill:blue:enocean";
gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
@@ -204,10 +34,36 @@
pinctrl-names = "default";
pinctrl-0 = <&enocean_button>;
- enocean {
+ key-enocean {
label = "EnOcean";
linux,code = <KEY_NEW>;
gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
};
};
};
+
+&i2c0 {
+ status = "disabled";
+};
+
+&led_pins {
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF0_MCLK__GPIO_3_20
+ MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+ MX28_PAD_AUART0_CTS__GPIO_3_2
+ MX28_PAD_I2C0_SCL__GPIO_3_24
+ MX28_PAD_I2C0_SDA__GPIO_3_25
+ >;
+};
+
+&pinctrl {
+ enocean_button: enocean-button@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RTS__GPIO_3_3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
index 0e8be5975709..859d97a5a775 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -5,9 +5,7 @@
*/
/dts-v1/;
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "imx28.dtsi"
+#include "imx28-duckbill-2.dts"
/ {
model = "I2SE Duckbill 2 SPI";
@@ -16,179 +14,50 @@
aliases {
ethernet1 = &qca7000;
};
+};
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x08000000>;
- };
-
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <8>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- non-removable;
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-spi";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
-
- qca7000: ethernet@0 {
- reg = <0>;
- compatible = "qca,qca7000";
- pinctrl-names = "default";
- pinctrl-0 = <&qca7000_pins>;
- interrupt-parent = <&gpio3>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
- spi-cpha;
- spi-cpol;
- spi-max-frequency = <8000000>;
- };
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_reset_pin: mac0-phy-reset@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_int_pin: mac0-phy-int@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins: led@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SAIF0_MCLK__GPIO_3_20
- MX28_PAD_SAIF0_LRCLK__GPIO_3_21
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- qca7000_pins: qca7000@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */
- MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */
- MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */
- MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */
- MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */
- MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- status = "okay";
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- status = "okay";
- dr_mode = "peripheral";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
- phy-supply = <&reg_3p3v>;
- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <25>;
- phy-handle = <&ethphy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
+&auart0 {
+ status = "disabled";
+};
- ethphy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_phy_int_pin>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
- max-speed = <100>;
- };
- };
- };
- };
+&i2c0 {
+ status = "disabled";
+};
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
+&pinctrl {
+ qca7000_pins: qca7000@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */
+ MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */
+ MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */
+ MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */
+ MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */
+ MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
};
+};
- leds {
- compatible = "gpio-leds";
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ /delete-property/ bus-width;
+ /delete-property/ vmmc-supply;
+ status = "okay";
+
+ qca7000: ethernet@0 {
+ reg = <0>;
+ compatible = "qca,qca7000";
pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- status-red {
- label = "duckbill:red:status";
- gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- };
-
- status-green {
- label = "duckbill:green:status";
- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
+ pinctrl-0 = <&qca7000_pins>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <8000000>;
};
};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
index 23fd3036404d..4e28212e9626 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -18,138 +18,6 @@
reg = <0x40000000 0x08000000>;
};
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <8>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- non-removable;
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_4bit_pins_b
- &mmc2_cd_cfg &mmc2_sck_cfg_b>;
- bus-width = <4>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_reset_pin: mac0-phy-reset@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_int_pin: mac0-phy-int@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins: leds@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SAIF0_MCLK__GPIO_3_20
- MX28_PAD_SAIF0_LRCLK__GPIO_3_21
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- status = "okay";
- };
-
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_2pins_a>;
- status = "okay";
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- status = "okay";
- dr_mode = "peripheral";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
- phy-supply = <&reg_3p3v>;
- phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <25>;
- phy-handle = <&ethphy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_phy_int_pin>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
- max-speed = <100>;
- };
- };
- };
- };
-
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
@@ -176,3 +44,127 @@
};
};
};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
+ phy-supply = <&reg_3p3v>;
+ phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <25>;
+ phy-handle = <&ethphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_phy_int_pin>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ max-speed = <100>;
+ };
+ };
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mac0_phy_reset_pin: mac0-phy-reset@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mac0_phy_int_pin: mac0-phy-int@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ led_pins: leds@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF0_MCLK__GPIO_3_20
+ MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a
+ &mmc0_cd_cfg &mmc0_sck_cfg>;
+ bus-width = <8>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+ non-removable;
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pins_b
+ &mmc2_cd_cfg &mmc2_sck_cfg_b>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usbphy0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index c666afb12445..13ffd533fdea 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -17,108 +17,6 @@
reg = <0x40000000 0x08000000>;
};
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <4>;
- vmmc-supply = <&reg_3p3v>;
- status = "okay";
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-spi";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- mac0_phy_reset_pin: mac0-phy-reset@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins: leds@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_AUART1_RX__GPIO_3_4
- MX28_PAD_AUART1_TX__GPIO_3_5
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
- };
-
- apbx@80040000 {
- lradc@80050000 {
- status = "okay";
- };
-
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_2pins_a>;
- status = "okay";
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- status = "okay";
- dr_mode = "peripheral";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
- phy-supply = <&reg_3p3v>;
- phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <25>;
- status = "okay";
- };
- };
-
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
@@ -145,3 +43,97 @@
};
};
};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
+ phy-supply = <&reg_3p3v>;
+ phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <25>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mac0_phy_reset_pin: mac0-phy-reset@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ led_pins: leds@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_RX__GPIO_3_4
+ MX28_PAD_AUART1_TX__GPIO_3_5
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_cd_cfg &mmc0_sck_cfg>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
index 3280fddaaf0d..b285a946e2c2 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -19,12 +19,12 @@
default-brightness-level = <10>;
};
- button-sw3 {
+ gpio-keys-0 {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>;
- sw3 {
+ switch-sw3 {
label = "SW3";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
@@ -32,12 +32,12 @@
};
};
- button-sw4 {
+ gpio-keys-1 {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>;
- sw4 {
+ switch-sw4 {
label = "SW4";
gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 7e2b0f198dfa..783abb82b2a8 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -95,266 +95,258 @@
};
};
- apb@80000000 {
- apbh@80000000 {
- nand-controller@8000c000 {
- pinctrl-names = "default";
- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
- &gpmi_pins_evk>;
- status = "okay";
- };
+ sound {
+ compatible = "fsl,imx28-evk-sgtl5000",
+ "fsl,mxs-audio-sgtl5000";
+ model = "imx28-evk-sgtl5000";
+ saif-controllers = <&saif0 &saif1>;
+ audio-codec = <&sgtl5000>;
+ };
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a
- &mmc0_cd_cfg &mmc0_sck_cfg>;
- bus-width = <8>;
- wp-gpios = <&gpio2 12 0>;
- vmmc-supply = <&reg_vddio_sd0>;
- status = "okay";
- };
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pin_gpio3_5>;
- ssp1: spi@80012000 {
- compatible = "fsl,imx28-mmc";
- bus-width = <8>;
- wp-gpios = <&gpio0 28 0>;
- };
+ user {
+ label = "Heartbeat";
+ gpios = <&gpio3 5 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
- ssp2: spi@80014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx28-spi";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
-
- flash: m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "sst,sst25vf016b", "jedec,spi-nor";
- spi-max-frequency = <40000000>;
- reg = <0>;
- };
- };
+ backlight_display: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 2 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
+};
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP1_CMD__GPIO_2_13
- MX28_PAD_SSP1_DATA3__GPIO_2_15
- MX28_PAD_ENET0_RX_CLK__GPIO_4_13
- MX28_PAD_SSP1_SCK__GPIO_2_12
- MX28_PAD_PWM3__GPIO_3_28
- MX28_PAD_LCD_RESET__GPIO_3_30
- MX28_PAD_AUART2_RX__GPIO_3_8
- MX28_PAD_AUART2_TX__GPIO_3_9
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pin_gpio3_5: led_gpio3_5@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_AUART1_TX__GPIO_3_5
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- gpmi_pins_evk: gpmi-nand-evk@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_CE1N__GPMI_CE1N
- MX28_PAD_GPMI_RDY1__GPMI_READY1
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_evk: lcdif-evk@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_RD_E__LCD_VSYNC
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC
- MX28_PAD_LCD_RS__LCD_DOTCLK
- MX28_PAD_LCD_CS__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+};
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_24bit_pins_a
- &lcdif_pins_evk>;
- status = "okay";
-
- port {
- display_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
+&auart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart3_pins_a>;
+ status = "okay";
+};
- can0: can@80032000 {
- pinctrl-names = "default";
- pinctrl-0 = <&can0_pins_a>;
- xceiver-supply = <&reg_can_3v3>;
- status = "okay";
- };
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ xceiver-supply = <&reg_can_3v3>;
+ status = "okay";
+};
- can1: can@80034000 {
- pinctrl-names = "default";
- pinctrl-0 = <&can1_pins_a>;
- xceiver-supply = <&reg_can_3v3>;
- status = "okay";
- };
- };
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins_a>;
+ xceiver-supply = <&reg_can_3v3>;
+ status = "okay";
+};
- apbx@80040000 {
- saif0: saif@80042000 {
- pinctrl-names = "default";
- pinctrl-0 = <&saif0_pins_a>;
- status = "okay";
- };
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
- saif1: saif@80046000 {
- pinctrl-names = "default";
- pinctrl-0 = <&saif1_pins_a>;
- fsl,saif-master = <&saif0>;
- status = "okay";
- };
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
+ &gpmi_pins_evk>;
+ status = "okay";
+};
- lradc@80050000 {
- status = "okay";
- fsl,lradc-touchscreen-wires = <4>;
- fsl,ave-ctrl = <4>;
- fsl,ave-delay = <2>;
- fsl,settling = <10>;
- };
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_evk>;
+ status = "okay";
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- #sound-dai-cells = <0>;
- VDDA-supply = <&reg_3p3v>;
- VDDIO-supply = <&reg_3p3v>;
- clocks = <&saif0>;
- };
-
- at24@51 {
- compatible = "atmel,24c32";
- pagesize = <32>;
- reg = <0x51>;
- };
- };
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pins_a>;
- status = "okay";
- };
+&lradc {
+ fsl,lradc-touchscreen-wires = <4>;
+ fsl,ave-ctrl = <4>;
+ fsl,ave-delay = <2>;
+ fsl,settling = <10>;
+ status = "okay";
+};
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_3p3v>;
+ clocks = <&saif0>;
+ };
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_pins_a>;
- uart-has-rtscts;
- status = "okay";
- };
+ at24@51 {
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x51>;
+ };
+};
- auart3: serial@80070000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart3_pins_a>;
- status = "okay";
- };
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-supply = <&reg_fec_3v3>;
+ phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+ status = "okay";
+};
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
+&mac1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac1_pins_a>;
+ status = "okay";
+};
- usbphy1: usbphy@8007e000 {
- status = "okay";
- };
- };
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP1_CMD__GPIO_2_13
+ MX28_PAD_SSP1_DATA3__GPIO_2_15
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13
+ MX28_PAD_SSP1_SCK__GPIO_2_12
+ MX28_PAD_PWM3__GPIO_3_28
+ MX28_PAD_LCD_RESET__GPIO_3_30
+ MX28_PAD_AUART2_RX__GPIO_3_8
+ MX28_PAD_AUART2_TX__GPIO_3_9
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
};
- ahb@80080000 {
- usb0: usb@80080000 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_pins_a>;
- vbus-supply = <&reg_usb0_vbus>;
- status = "okay";
- };
-
- usb1: usb@80090000 {
- vbus-supply = <&reg_usb1_vbus>;
- status = "okay";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-supply = <&reg_fec_3v3>;
- phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <100>;
- status = "okay";
- };
+ led_pin_gpio3_5: led_gpio3_5@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_TX__GPIO_3_5
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
- mac1: ethernet@800f4000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac1_pins_a>;
- status = "okay";
- };
+ gpmi_pins_evk: gpmi-nand-evk@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_CE1N__GPMI_CE1N
+ MX28_PAD_GPMI_RDY1__GPMI_READY1
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
};
- sound {
- compatible = "fsl,imx28-evk-sgtl5000",
- "fsl,mxs-audio-sgtl5000";
- model = "imx28-evk-sgtl5000";
- saif-controllers = <&saif0 &saif1>;
- audio-codec = <&sgtl5000>;
+ lcdif_pins_evk: lcdif-evk@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
};
+};
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pin_gpio3_5>;
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pins_a>;
+ status = "okay";
+};
- user {
- label = "Heartbeat";
- gpios = <&gpio3 5 0>;
- linux,default-trigger = "heartbeat";
- };
- };
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ status = "okay";
+};
- backlight_display: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm 2 5000000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ status = "okay";
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a
+ &mmc0_cd_cfg &mmc0_sck_cfg>;
+ bus-width = <8>;
+ wp-gpios = <&gpio2 12 0>;
+ vmmc-supply = <&reg_vddio_sd0>;
+ status = "okay";
+};
+
+&ssp1 {
+ compatible = "fsl,imx28-mmc";
+ bus-width = <8>;
+ wp-gpios = <&gpio0 28 0>;
+};
+
+&ssp2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ flash: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25vf016b", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
};
};
+
+&usb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_pins_a>;
+ vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
index 2bdb4c093545..c08b14ad7cd5 100644
--- a/arch/arm/boot/dts/imx28-m28.dtsi
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -14,31 +14,6 @@
reg = <0x40000000 0x08000000>;
};
- apb@80000000 {
- apbh@80000000 {
- nand-controller@8000c000 {
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
- status = "okay";
- };
- };
-
- apbx@80040000 {
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-
- rtc: rtc@68 {
- compatible = "st,m41t62";
- reg = <0x68>;
- };
- };
- };
- };
-
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -54,3 +29,22 @@
};
};
};
+
+&gpmi {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "st,m41t62";
+ reg = <0x68>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 865ac3d573c7..6b01de9efd02 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -15,187 +15,6 @@
reg = <0x40000000 0x08000000>;
};
- apb@80000000 {
- apbh@80000000 {
- nand-controller@8000c000 {
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
- status = "okay";
-
- partition@0 {
- label = "gpmi-nfc-0-boot";
- reg = <0x00000000 0x01400000>;
- read-only;
- };
-
- partition@1 {
- label = "gpmi-nfc-general-use";
- reg = <0x01400000 0x0ec00000>;
- };
- };
-
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a
- &mmc0_cd_cfg
- &mmc0_sck_cfg>;
- bus-width = <4>;
- vmmc-supply = <&reg_vddio_sd0>;
- status = "okay";
- };
-
- ssp2: spi@80014000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_4bit_pins_a
- &mmc2_cd_cfg
- &mmc2_sck_cfg_a>;
- bus-width = <4>;
- vmmc-supply = <&reg_vddio_sd1>;
- status = "okay";
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP2_SS0__GPIO_2_19
- MX28_PAD_PWM4__GPIO_3_29
- MX28_PAD_AUART2_RX__GPIO_3_8
- MX28_PAD_ENET0_RX_CLK__GPIO_4_13
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_m28: lcdif-m28@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_VSYNC__LCD_VSYNC
- MX28_PAD_LCD_HSYNC__LCD_HSYNC
- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
- MX28_PAD_LCD_RESET__LCD_RESET
- MX28_PAD_LCD_CS__LCD_ENABLE
- MX28_PAD_AUART1_TX__GPIO_3_5
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- led_pins_gpio: leds-m28@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_SSP3_MISO__GPIO_2_26
- MX28_PAD_SSP3_SCK__GPIO_2_24
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
-
- ocotp@8002c000 {
- status = "okay";
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_24bit_pins_a
- &lcdif_pins_m28>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <6410256>;
- hactive = <320>;
- vactive = <240>;
- hback-porch = <38>;
- hfront-porch = <20>;
- vback-porch = <15>;
- vfront-porch = <5>;
- hsync-len = <30>;
- vsync-len = <3>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
- };
- };
-
- apbx@80040000 {
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_b>;
- status = "okay";
- };
-
- usbphy1: usbphy@8007e000 {
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_2pins_a>;
- status = "okay";
- };
-
- auart3: serial@80070000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart3_2pins_b>;
- status = "okay";
- };
-
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pins_a>;
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb1: usb@80090000 {
- vbus-supply = <&reg_usb1_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_a>;
- disable-over-current;
- status = "okay";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <100>;
- status = "okay";
- };
-
- mac1: ethernet@800f4000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac1_pins_a>;
- status = "okay";
- };
- };
-
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 3 5000000>;
@@ -264,3 +83,176 @@
};
};
};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_2pins_a>;
+ status = "okay";
+};
+
+&auart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart3_2pins_b>;
+ status = "okay";
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_b>;
+ status = "okay";
+};
+
+&gpmi {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+ status = "okay";
+
+ partition@0 {
+ label = "gpmi-nfc-0-boot";
+ reg = <0x00000000 0x01400000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "gpmi-nfc-general-use";
+ reg = <0x01400000 0x0ec00000>;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_m28>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <6410256>;
+ hactive = <320>;
+ vactive = <240>;
+ hback-porch = <38>;
+ hfront-porch = <20>;
+ vback-porch = <15>;
+ vfront-porch = <5>;
+ hsync-len = <30>;
+ vsync-len = <3>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+ status = "okay";
+};
+
+&mac1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac1_pins_a>;
+ status = "okay";
+};
+
+&ocotp {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SS0__GPIO_2_19
+ MX28_PAD_PWM4__GPIO_3_29
+ MX28_PAD_AUART2_RX__GPIO_3_8
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_m28: lcdif-m28@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_VSYNC__LCD_VSYNC
+ MX28_PAD_LCD_HSYNC__LCD_HSYNC
+ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
+ MX28_PAD_LCD_RESET__LCD_RESET
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ MX28_PAD_AUART1_TX__GPIO_3_5
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ led_pins_gpio: leds-m28@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP3_MISO__GPIO_2_26
+ MX28_PAD_SSP3_SCK__GPIO_2_24
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pins_a>;
+ status = "okay";
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_cd_cfg
+ &mmc0_sck_cfg>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_vddio_sd0>;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pins_a
+ &mmc2_cd_cfg
+ &mmc2_sck_cfg_a>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_vddio_sd1>;
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <&reg_usb1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_a>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index f3bddc5ada4b..e350d57a4cec 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -11,220 +11,6 @@
model = "Aries/DENX M28EVK";
compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28";
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a
- &mmc0_cd_cfg
- &mmc0_sck_cfg>;
- bus-width = <8>;
- wp-gpios = <&gpio3 10 0>;
- vmmc-supply = <&reg_vddio_sd0>;
- status = "okay";
- };
-
- ssp2: spi@80014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx28-spi";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
-
- flash: m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p80", "jedec,spi-nor";
- spi-max-frequency = <40000000>;
- reg = <0>;
- };
- };
-
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_PWM3__GPIO_3_28
- MX28_PAD_AUART2_CTS__GPIO_3_10
- MX28_PAD_AUART2_RTS__GPIO_3_11
- MX28_PAD_AUART3_RX__GPIO_3_12
- MX28_PAD_AUART3_TX__GPIO_3_13
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- lcdif_pins_m28: lcdif-m28@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
- MX28_PAD_LCD_ENABLE__LCD_ENABLE
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
- };
-
- lcdif@80030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcdif_24bit_pins_a
- &lcdif_pins_m28>;
- display = <&display0>;
- status = "okay";
-
- display0: display0 {
- bits-per-pixel = <16>;
- bus-width = <18>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33260000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <0>;
- hfront-porch = <256>;
- vback-porch = <0>;
- vfront-porch = <45>;
- hsync-len = <1>;
- vsync-len = <1>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
- };
- };
- };
-
- can0: can@80032000 {
- pinctrl-names = "default";
- pinctrl-0 = <&can0_pins_a>;
- status = "okay";
- };
-
- can1: can@80034000 {
- pinctrl-names = "default";
- pinctrl-0 = <&can1_pins_a>;
- status = "okay";
- };
- };
-
- apbx@80040000 {
- saif0: saif@80042000 {
- pinctrl-names = "default";
- pinctrl-0 = <&saif0_pins_a>;
- status = "okay";
- };
-
- saif1: saif@80046000 {
- pinctrl-names = "default";
- pinctrl-0 = <&saif1_pins_a>;
- fsl,saif-master = <&saif0>;
- status = "okay";
- };
-
- i2c0: i2c@80058000 {
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- #sound-dai-cells = <0>;
- VDDA-supply = <&reg_3p3v>;
- VDDIO-supply = <&reg_3p3v>;
- clocks = <&saif0>;
- };
-
- eeprom: eeprom@51 {
- compatible = "atmel,24c128";
- reg = <0x51>;
- pagesize = <32>;
- };
- };
-
- lradc@80050000 {
- status = "okay";
- fsl,lradc-touchscreen-wires = <4>;
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
-
- usbphy1: usbphy@8007e000 {
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_pins_a>;
- status = "okay";
- };
-
- auart1: serial@8006c000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart1_pins_a>;
- status = "okay";
- };
-
- auart2: serial@8006e000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart2_2pins_b>;
- status = "okay";
- };
-
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm4_pins_a>;
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- vbus-supply = <&reg_usb0_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_a>;
- status = "okay";
- };
-
- usb1: usb@80090000 {
- vbus-supply = <&reg_usb1_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_a>;
- status = "okay";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- clocks = <&clks 57>, <&clks 57>;
- clock-names = "ipg", "ahb";
- status = "okay";
- };
-
- mac1: ethernet@800f4000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac1_pins_a>;
- status = "okay";
- };
- };
-
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 4 5000000>;
@@ -269,3 +55,209 @@
audio-codec = <&sgtl5000>;
};
};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_pins_a>;
+ status = "okay";
+};
+
+&auart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart1_pins_a>;
+ status = "okay";
+};
+
+&auart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart2_2pins_b>;
+ status = "okay";
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_3p3v>;
+ clocks = <&saif0>;
+ };
+
+ eeprom: eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_m28>;
+ display = <&display0>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <16>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <0>;
+ hfront-porch = <256>;
+ vback-porch = <0>;
+ vfront-porch = <45>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
+&lradc {
+ status = "okay";
+ fsl,lradc-touchscreen-wires = <4>;
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins_a>;
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ clocks = <&clks 57>, <&clks 57>;
+ clock-names = "ipg", "ahb";
+ status = "okay";
+};
+
+&mac1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac1_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM3__GPIO_3_28
+ MX28_PAD_AUART2_CTS__GPIO_3_10
+ MX28_PAD_AUART2_RTS__GPIO_3_11
+ MX28_PAD_AUART3_RX__GPIO_3_12
+ MX28_PAD_AUART3_TX__GPIO_3_13
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_pins_m28: lcdif-m28@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
+ MX28_PAD_LCD_ENABLE__LCD_ENABLE
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm4_pins_a>;
+ status = "okay";
+};
+
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ status = "okay";
+};
+
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ status = "okay";
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a
+ &mmc0_cd_cfg
+ &mmc0_sck_cfg>;
+ bus-width = <8>;
+ wp-gpios = <&gpio3 10 0>;
+ vmmc-supply = <&reg_vddio_sd0>;
+ status = "okay";
+};
+
+&ssp2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ vbus-supply = <&reg_usb0_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_a>;
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <&reg_usb1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_a>;
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/imx28-pinfunc.h
index e11f69ba0fe4..d427e6c2fa78 100644
--- a/arch/arm/boot/dts/imx28-pinfunc.h
+++ b/arch/arm/boot/dts/imx28-pinfunc.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX28 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX28_PINCTRL_H__
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 43be7a6a769b..5d74a68c56ff 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -15,111 +15,6 @@
reg = <0x40000000 0x08000000>;
};
- apb@80000000 {
- apbh@80000000 {
- pinctrl@80018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&hog_pins_a>;
-
- hog_pins_a: hog-gpios@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_GPMI_D00__GPIO_0_0
- MX28_PAD_GPMI_D03__GPIO_0_3
- MX28_PAD_GPMI_D06__GPIO_0_6
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- };
-
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a>;
- bus-width = <4>;
- status = "okay";
- };
-
- ssp2: spi@80014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx28-spi";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
-
- flash: m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "everspin,mr25h256", "mr25h256";
- spi-max-frequency = <40000000>;
- reg = <0>;
- };
- };
- };
-
- apbx@80040000 {
- i2c0: i2c@80058000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-
- eeprom: eeprom@52 {
- compatible = "atmel,24c64";
- reg = <0x52>;
- pagesize = <32>;
- };
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
-
- usbphy0: usbphy@8007c000 {
- status = "okay";
- };
-
- auart0: serial@8006a000 {
- pinctrl-names = "default";
- pinctrl-0 = <&auart0_pins_a>;
- status = "okay";
- };
- };
- };
-
- ahb@80080000 {
- usb0: usb@80080000 {
- vbus-supply = <&reg_usb0_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_b>;
- status = "okay";
- };
-
- mac0: ethernet@800f0000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- status = "okay";
- };
-
- mac1: ethernet@800f4000 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&mac1_pins_a>;
- status = "okay";
- };
- };
-
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -164,3 +59,99 @@
};
};
+
+&auart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_pins_a>;
+ status = "okay";
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+
+ eeprom: eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
+
+&mac0 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ status = "okay";
+};
+
+&mac1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac1_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog-gpios@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D00__GPIO_0_0
+ MX28_PAD_GPMI_D03__GPIO_0_3
+ MX28_PAD_GPMI_D06__GPIO_0_6
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ssp2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "everspin,mr25h256", "mr25h256";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ vbus-supply = <&reg_usb0_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_b>;
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
index 097ec35c62d8..ae6ed5c41be3 100644
--- a/arch/arm/boot/dts/imx28-ts4600.dts
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -18,50 +18,6 @@
reg = <0x40000000 0x10000000>; /* 256MB */
};
- apb@80000000 {
- apbh@80000000 {
- ssp0: spi@80010000 {
- compatible = "fsl,imx28-mmc";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a
- &mmc0_sck_cfg
- &en_sd_pwr>;
- broken-cd = <1>;
- bus-width = <4>;
- vmmc-supply = <&reg_vddio_sd0>;
- status = "okay";
- };
-
- pinctrl@80018000 {
-
- en_sd_pwr: en-sd-pwr@0 {
- reg = <0>;
- fsl,pinmux-ids = <
- MX28_PAD_PWM3__GPIO_3_28
- >;
- fsl,drive-strength = <MXS_DRIVE_4mA>;
- fsl,voltage = <MXS_VOLTAGE_HIGH>;
- fsl,pull-up = <MXS_PULL_DISABLE>;
- };
-
- };
- };
-
- apbx@80040000 {
- pwm: pwm@80064000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pins_a>;
- status = "okay";
- };
-
- duart: serial@80074000 {
- pinctrl-names = "default";
- pinctrl-0 = <&duart_pins_a>;
- status = "okay";
- };
- };
- };
-
reg_vddio_sd0: regulator-vddio-sd0 {
compatible = "regulator-fixed";
regulator-name = "vddio-sd0";
@@ -72,3 +28,39 @@
};
};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&pinctrl {
+ en_sd_pwr: en-sd-pwr@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM3__GPIO_3_28
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pins_a>;
+ status = "okay";
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_sck_cfg
+ &en_sd_pwr>;
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <&reg_vddio_sd0>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 6d7b044fec5b..ffe58c7093e1 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2012 Shawn Guo <shawn.guo@linaro.org>
* Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -221,7 +185,7 @@
linux,no-autorepeat;
};
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 130b4145af82..a8d3c3113e0f 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -85,10 +85,6 @@
88 88 88 88
88 88 88 88
87 86 0 0>;
- interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
- "gpmi0", "gmpi1", "gpmi2", "gmpi3",
- "gpmi4", "gmpi5", "gpmi6", "gmpi7",
- "hsadc", "lcdif", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 25>;
@@ -1001,10 +997,6 @@
80 81 68 69
70 71 72 73
74 75 76 77>;
- interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
- "saif0", "saif1", "i2c0", "i2c1",
- "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
- "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 26>;
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index 2adb923c0b27..95c05f17a6d5 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -48,7 +48,7 @@
reg = <0x68000000 0x100000>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -63,7 +63,7 @@
ranges = <0 0x1fffc000 0x4000>;
};
- bus@43f00000 { /* AIPS1 */
+ aips1: bus@43f00000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -297,7 +297,7 @@
#interrupt-cells = <2>;
};
- sdma: sdma@53fd4000 {
+ sdma: dma-controller@53fd4000 {
compatible = "fsl,imx31-sdma";
reg = <0x53fd4000 0x4000>;
interrupts = <34>;
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
index b1c11170ac25..7f4f812b0811 100644
--- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -13,12 +13,12 @@
model = "Eukrea CPUIMX35";
compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35";
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bp1>;
- bp1 {
+ button {
label = "BP1";
gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 8e41c8b7bd70..d650f54c3fc6 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -284,7 +284,7 @@
#interrupt-cells = <2>;
};
- sdma: sdma@53fd4000 {
+ sdma: dma-controller@53fd4000 {
compatible = "fsl,imx35-sdma";
reg = <0x53fd4000 0x4000>;
clocks = <&clks 9>, <&clks 65>;
diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts
index 82ce8c43be86..467db6b4ed7f 100644
--- a/arch/arm/boot/dts/imx50-kobo-aura.dts
+++ b/arch/arm/boot/dts/imx50-kobo-aura.dts
@@ -26,7 +26,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
- on {
+ led-on {
label = "kobo_aura:orange:on";
gpios = <&gpio6 24 GPIO_ACTIVE_LOW>;
panic-indicator;
@@ -38,20 +38,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
- hallsensor {
+ event-hallsensor {
label = "Hallsensor";
gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESERVED>;
linux,input-type = <EV_SW>;
};
- frontlight {
+ event-frontlight {
label = "Frontlight";
gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DISPLAYTOGGLE>;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index be0de0fd31f9..3d9a9f37f672 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -94,14 +94,14 @@
status = "okay";
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
- bus@50000000 { /* AIPS1 */
+ aips1: bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -385,7 +385,7 @@
};
};
- bus@60000000 { /* AIPS2 */
+ aips2: bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -421,7 +421,7 @@
status = "disabled";
};
- sdma: sdma@63fb0000 {
+ sdma: dma-controller@63fb0000 {
compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index c66f274ba4e9..b61d55ca1467 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -63,7 +63,7 @@
leds {
compatible = "gpio-leds";
- user {
+ led-user {
label = "Heartbeat";
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 552196d8a60a..a1f9c6a72275 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -154,7 +154,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
index aab8d6f137c3..10cae7c3a879 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
@@ -13,6 +13,13 @@
chosen {
stdout-path = &uart1;
};
+
+ usbphy1: usbphy1 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
+ };
};
&esdhc1 {
@@ -63,6 +70,7 @@
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
+ fsl,usbphy = <&usbphy1>;
dr_mode = "host";
phy_type = "ulpi";
disable-over-current;
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index 7d4970417dce..f0809a16a2ce 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -34,22 +34,22 @@
regulators {
sw1_reg: sw1 {
- regulator-min-microvolt = <1000000>;
+ regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
+ regulator-min-microvolt = <1175000>;
+ regulator-max-microvolt = <1275000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
@@ -102,18 +102,6 @@
regulator-always-on;
};
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3150000>;
- regulator-always-on;
- };
-
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -124,8 +112,6 @@
regulator-always-on;
};
- gpo1_reg: gpo1 { };
-
gpo2_reg: gpo2 { };
gpo3_reg: gpo3 { };
@@ -198,6 +184,7 @@
&usbotg {
phy_type = "utmi_wide";
disable-over-current;
+ vbus-supply = <&swbst_reg>;
/* Device role is not known, keep status disabled */
};
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index 85654d6baf28..f7408722d68a 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -174,7 +174,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_interrupt_fpga>;
interrupt-parent = <&gpio2>;
- interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index ec8ca3ac2c1c..e537e06e11d7 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -137,7 +137,7 @@
};
};
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
@@ -556,7 +556,7 @@
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-rdu1";
current-speed = <38400>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
index aa91e5dde4b8..21dd3f7abd48 100644
--- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
+++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
@@ -311,7 +311,7 @@
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-mezz";
current-speed = <57600>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
index 875b10a7d674..9f857eb44bf7 100644
--- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
+++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
@@ -319,7 +319,7 @@
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-esb";
current-speed = <57600>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 56c8d87864c3..ba92a3ea6872 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -114,7 +114,7 @@
ports = <&ipu_di0>, <&ipu_di1>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -124,6 +124,9 @@
iram: sram@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 0x20000>;
+ ranges = <0 0x1ffe0000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
gpu: gpu@30000000 {
@@ -171,7 +174,7 @@
};
};
- bus@70000000 { /* AIPS1 */
+ aips1: bus@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -215,6 +218,8 @@
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -426,6 +431,8 @@
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -436,6 +443,8 @@
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -454,7 +463,7 @@
};
};
- bus@80000000 { /* AIPS2 */
+ aips2: bus@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -498,7 +507,7 @@
status = "disabled";
};
- sdma: sdma@83fb0000 {
+ sdma: dma-controller@83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 6208fbb2e741..23a7492e2929 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -61,34 +61,34 @@
gpio-keys {
compatible = "gpio-keys";
- home {
+ key-home {
label = "Home";
gpios = <&gpio5 10 0>;
linux,code = <KEY_HOME>;
wakeup-source;
};
- back {
+ key-back {
label = "Back";
gpios = <&gpio5 11 0>;
linux,code = <KEY_BACK>;
wakeup-source;
};
- program {
+ key-program {
label = "Program";
gpios = <&gpio5 12 0>;
linux,code = <KEY_PROGRAM >;
wakeup-source;
};
- volume-up {
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio5 13 0>;
linux,code = <KEY_VOLUMEUP>;
};
- volume-down {
+ key-volume-down {
label = "Volume Down";
gpios = <&gpio4 0 0>;
linux,code = <KEY_VOLUMEDOWN>;
diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts
index cfb18849a92b..055d23a9aee7 100644
--- a/arch/arm/boot/dts/imx53-cx9020.dts
+++ b/arch/arm/boot/dts/imx53-cx9020.dts
@@ -86,27 +86,27 @@
leds {
compatible = "gpio-leds";
- pwr-r {
+ led-pwr-r {
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- pwr-g {
+ led-pwr-g {
gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- pwr-b {
+ led-pwr-b {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
- sd1-b {
+ led-sd1-b {
linux,default-trigger = "mmc0";
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
};
- sd2-b {
+ led-sd2-b {
linux,default-trigger = "mmc1";
gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index a1a6228d1aa6..2bd2432d317f 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -52,13 +52,13 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio>;
- user1 {
+ led-user1 {
label = "user1";
gpios = <&gpio2 8 0>;
linux,default-trigger = "heartbeat";
};
- user2 {
+ led-user2 {
label = "user2";
gpios = <&gpio2 9 0>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts
index d5c68d1ea707..4d77b6077fc1 100644
--- a/arch/arm/boot/dts/imx53-m53menlo.dts
+++ b/arch/arm/boot/dts/imx53-m53menlo.dts
@@ -34,19 +34,19 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- user1 {
+ led-user1 {
label = "TestLed601";
gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
- user2 {
+ led-user2 {
label = "TestLed602";
gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- eth {
+ led-eth {
label = "EthLedYe";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "netdev";
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index 37d0cffea99c..70c4a4852256 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -488,7 +488,7 @@
scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
status = "okay";
- i2c-switch@70 {
+ i2c-mux@70 {
compatible = "nxp,pca9547";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index fe4244044a0f..50fef8dd3675 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -45,20 +45,20 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
- volume-up {
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
- volume-down {
+ key-volume-down {
label = "Volume Down";
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
@@ -71,7 +71,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio7_7>;
- user {
+ led-user {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/imx53-sk-imx53.dts b/arch/arm/boot/dts/imx53-sk-imx53.dts
new file mode 100644
index 000000000000..103e73176e47
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-sk-imx53.dts
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2023 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx53.dtsi"
+
+/ {
+ model = "StarterKit SK-iMX53 Board";
+ compatible = "starterkit,sk-imx53", "fsl,imx53";
+
+ aliases {
+ /*
+ * iMX RTC is not battery powered on this board.
+ * Use the i2c RTC as rtc0.
+ */
+ rtc0 = &rtc;
+ rtc1 = &srtc;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@70000000 {
+ device_type = "memory";
+ /* v2 had only 256 MB, v3 has 512 MB */
+ reg = <0x70000000 0x20000000>;
+ };
+
+ reg_usb1_vbus: regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg_vbus: regulator-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ status = "okay";
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&esdhc1 {
+ cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ fsl,wp-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+ mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ tlv320aic23: codec@1a {
+ compatible = "ti,tlv320aic23";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_codec>;
+ #sound-dai-cells = <0>;
+ };
+
+ rtc: rtc@68 {
+ compatible = "dallas,ds1338";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x1e4
+ MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x1e4
+ MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x1e4
+ MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x1e4
+ >;
+ };
+
+ pinctrl_can1: can1grp {
+ fsl,pins = <
+ MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x1e4
+ MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x1e4
+ >;
+ };
+
+ pinctrl_codec: codecgrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D16__ECSPI1_SCLK 0x1e4
+ MX53_PAD_EIM_D17__ECSPI1_MISO 0x1e4
+ MX53_PAD_EIM_D18__ECSPI1_MOSI 0x1e4
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x1e4
+ MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x1e4
+ MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x1e4
+ >;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ MX53_PAD_EIM_DA14__GPIO3_14 0x1f0
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x1e4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4
+ MX53_PAD_GPIO_1__GPIO1_1 0x1c4
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
+ MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0x400001e4
+ MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4
+ MX53_PAD_EIM_EB2__GPIO2_30 0x1e4
+ >;
+ };
+
+ pinctrl_nand: nandgrp {
+ fsl,pins = <
+ MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
+ MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
+ MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
+ MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
+ MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
+ MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
+ MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
+ MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x4
+ MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x4
+ MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x4
+ MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
+ MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
+ MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
+ MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
+ MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
+ MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
+ MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
+ MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX53_PAD_GPIO_9__PWM1_PWMO 0x5
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D24__UART3_TXD_MUX 0x1e4
+ MX53_PAD_EIM_D25__UART3_RXD_MUX 0x1e4
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
+ MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
+ >;
+ };
+};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ nand-bus-width = <8>;
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot";
+ reg = <0x00100000 0x00100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "u-boot-env";
+ reg = <0x00200000 0x00100000>;
+ read-only;
+ };
+
+ partition@1000000 {
+ label = "kernel-safe";
+ reg = <0x01000000 0x00a00000>;
+ read-only;
+ };
+
+ partition@1a00000 {
+ label = "kernel";
+ reg = <0x01a00000 0x005e0000>;
+ };
+
+ partition@2000000 {
+ label = "ubifs";
+ reg = <0x02000000 0x0e000000>;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb1_vbus>;
+ phy_type = "utmi";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg {
+ dr_mode = "peripheral";
+ disable-over-current;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 9be44e807188..f8d17967a67e 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -19,13 +19,13 @@
gpio-keys {
compatible = "gpio-keys";
- volume-up {
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio2 14 0>;
linux,code = <KEY_VOLUMEUP>;
};
- volume-down {
+ key-volume-down {
label = "Volume Down";
gpios = <&gpio2 15 0>;
linux,code = <KEY_VOLUMEDOWN>;
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index 8712e9851465..a439a47fb65a 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -81,7 +81,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_key>;
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
linux,code = <116>; /* KEY_POWER */
@@ -94,7 +94,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_stk5led>;
- user {
+ led-user {
label = "Heartbeat";
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts
index f34993a490ee..acc44010d510 100644
--- a/arch/arm/boot/dts/imx53-usbarmory.dts
+++ b/arch/arm/boot/dts/imx53-usbarmory.dts
@@ -67,7 +67,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- user {
+ led-user {
label = "LED";
gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 67487f3caee1..17dc13719639 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -132,7 +132,7 @@
status = "okay";
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -222,7 +222,7 @@
clock-names = "core_clk", "mem_iface_clk";
};
- bus@50000000 { /* AIPS1 */
+ aips1: bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -655,7 +655,7 @@
};
};
- bus@60000000 { /* AIPS2 */
+ aips2: bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -710,7 +710,7 @@
status = "disabled";
};
- sdma: sdma@63fb0000 {
+ sdma: dma-controller@63fb0000 {
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
@@ -850,6 +850,9 @@
ocram: sram@f8000000 {
compatible = "mmio-sram";
reg = <0xf8000000 0x20000>;
+ ranges = <0 0xf8000000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX5_CLK_OCRAM>;
};
};
diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
index d9de9b4f0c52..d477a937b47a 100644
--- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
+++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
@@ -6,7 +6,7 @@
keyboard {
compatible = "gpio-keys";
- btn0 {
+ button-0 {
gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
label = "btn0";
linux,code = <KEY_WAKEUP>;
@@ -14,7 +14,7 @@
wakeup-source;
};
- btn1 {
+ button-1 {
gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
label = "btn1";
linux,code = <KEY_WAKEUP>;
@@ -22,7 +22,7 @@
wakeup-source;
};
- btn2 {
+ button-2 {
gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
label = "btn2";
linux,code = <KEY_WAKEUP>;
@@ -30,7 +30,7 @@
wakeup-source;
};
- btn3 {
+ button-3 {
gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
label = "btn3";
linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts
index e8325fd680d9..e6a4e2770640 100644
--- a/arch/arm/boot/dts/imx6dl-alti6p.dts
+++ b/arch/arm/boot/dts/imx6dl-alti6p.dts
@@ -22,6 +22,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
i2c2-mux {
@@ -191,6 +192,13 @@
status = "okay";
};
+&clks {
+ clocks = <&clock_ksz8081>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clock_ksz8081>;
+};
+
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -208,10 +216,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clock_ksz8081>;
- clock-names = "ipg", "ahb", "ptp";
status = "okay";
mdio {
diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
index ec5b66453156..37697fac9dea 100644
--- a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
+++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi
@@ -188,7 +188,7 @@
rotary-encoder-key {
compatible = "gpio-keys";
- rotary-encoder-press {
+ rotary-encoder-event {
label = "rotary-encoder press";
gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_ENTER>;
@@ -211,17 +211,17 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>;
- alarm1 {
+ led-alarm1 {
label = "alarm:red";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
- alarm2 {
+ led-alarm2 {
label = "alarm:yellow";
gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
};
- alarm3 {
+ led-alarm3 {
label = "alarm:blue";
gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts
new file mode 100644
index 000000000000..82a0d1a28d12
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Aster Board";
+ compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ cs-gpios = <
+ &gpio5 2 GPIO_ACTIVE_HIGH
+ &gpio5 4 GPIO_ACTIVE_HIGH
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>;
+ status = "okay";
+};
+
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
+&i2c3 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_csi_gpio_1
+ &pinctrl_gpio_2
+ &pinctrl_gpio_aster
+ &pinctrl_usbh_oc_1
+ &pinctrl_usbc_id_1
+ &pinctrl_weim_gpio_5
+ >;
+
+ pinctrl_gpio_aster: gpioaster {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ >;
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg {
+ disable-over-current;
+ status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 7da74e6f46d9..f50a26dd34c0 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
@@ -17,12 +17,6 @@
compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
"fsl,imx6dl";
- /* Will be filled by the bootloader */
- memory@10000000 {
- device_type = "memory";
- reg = <0x10000000 0>;
- };
-
aliases {
i2c0 = &i2c2;
i2c1 = &i2c3;
@@ -44,67 +38,6 @@
clock-frequency = <16000000>;
clock-output-names = "clk16m";
};
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- wakeup {
- label = "Wake-Up";
- gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- lcd_display: disp0 {
- compatible = "fsl,imx-parallel-display";
- #address-cells = <1>;
- #size-cells = <0>;
- interface-pix-fmt = "bgr666";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_lcdif>;
- status = "okay";
-
- port@0 {
- reg = <0>;
-
- lcd_display_in: endpoint {
- remote-endpoint = <&ipu1_di0_disp0>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
-
- panel: panel {
- /*
- * edt,et057090dhu: EDT 5.7" LCD TFT
- * edt,et070080dh6: EDT 7.0" LCD TFT
- */
- compatible = "edt,et057090dhu";
- backlight = <&backlight>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-};
-
-&backlight {
- brightness-levels = <0 127 191 223 239 247 251 255>;
- default-brightness-level = <1>;
- status = "okay";
};
/* Colibri SSP */
@@ -113,40 +46,21 @@
mcp251x0: mcp251x@0 {
compatible = "microchip,mcp2515";
- reg = <0>;
clocks = <&clk16m>;
interrupt-parent = <&gpio3>;
interrupts = <27 0x2>;
+ reg = <0>;
spi-max-frequency = <10000000>;
status = "okay";
};
};
-&hdmi {
- status = "okay";
-};
-
/*
* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
&i2c3 {
status = "okay";
- /*
- * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
- */
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcap_1>;
- reg = <0x4a>;
- interrupt-parent = <&gpio1>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */
- status = "disabled";
- };
-
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
@@ -162,24 +76,6 @@
&pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
>;
-
- pinctrl_pcap_1: pcap1grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
- >;
- };
-
- pinctrl_mxt_ts: mxttsgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
- >;
- };
-};
-
-&ipu1_di0_disp0 {
- remote-endpoint = <&lcd_display_in>;
};
&pwm1 {
@@ -215,11 +111,12 @@
};
&usbh1 {
- vbus-supply = <&reg_usb_host_vbus>;
+ disable-over-current;
status = "okay";
};
&usbotg {
+ disable-over-current;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts
new file mode 100644
index 000000000000..3a6d3889760d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6dl-colibri-iris.dts"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board";
+ compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
+ regulator-name = "3v3_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>;
+
+ pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ >;
+ };
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ cap-power-off-card;
+ /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */
+ /* /delete-property/ no-1-8-v; */
+ vmmc-supply = <&reg_3v3_vmmc>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts
new file mode 100644
index 000000000000..4303c88bb2a9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Iris Board";
+ compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c3;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* Colibri SSP */
+&ecspi4 {
+ status = "okay";
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>;
+
+ /*
+ * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one
+ * wants to turn the transceiver off, that property has to be deleted
+ * and the gpio handled in userspace.
+ * The same applies to uart-b-c-on-x14-enable where the UART_B and
+ * UART_C transceiver is turned on.
+ */
+ uart-a-on-x13-enable-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
+ output-high;
+ };
+
+ uart-b-c-on-x14-enable-hog {
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
+ output-high;
+ };
+};
+
+/*
+ * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
+&i2c3 {
+ status = "okay";
+
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_gpio_iris
+ &pinctrl_usbh_oc_1
+ &pinctrl_usbc_id_1
+ >;
+
+ pinctrl_gpio_iris: gpioirisgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1_forceoff: uart1forceoffgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart23_forceoff: uart23forceoffgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg {
+ disable-over-current;
+ status = "okay";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts
deleted file mode 100644
index 223275f028f1..000000000000
--- a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright 2020 Toradex
- */
-
-/dts-v1/;
-
-#include "imx6dl-colibri-eval-v3.dts"
-#include "imx6qdl-colibri-v1_1-uhs.dtsi"
-
-/ {
- model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3";
- compatible = "toradex,colibri_imx6dl-v1_1-eval-v3",
- "toradex,colibri_imx6dl-v1_1",
- "toradex,colibri_imx6dl-eval-v3",
- "toradex,colibri_imx6dl",
- "fsl,imx6dl";
-};
-
-/* Colibri MMC */
-&usdhc1 {
- status = "okay";
- /*
- * Please make sure your carrier board does not pull-up any of
- * the MMC/SD signals to 3.3 volt before attempting to activate
- * UHS-I support.
- * To let signaling voltage be changed to 1.8V, please
- * delete no-1-8-v property (example below):
- * /delete-property/no-1-8-v;
- */
-};
diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
index b4a9523e325b..33825b5a8f26 100644
--- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -28,6 +28,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
@@ -64,6 +65,13 @@
status = "okay";
};
+&clks {
+ clocks = <&rmii_clk>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&rmii_clk>;
+};
+
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
@@ -297,7 +305,6 @@
phy-mode = "rmii";
phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
- clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
status = "okay";
mdio {
diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts
index 6b6e6fcdea9c..fa823988312d 100644
--- a/arch/arm/boot/dts/imx6dl-lanmcu.dts
+++ b/arch/arm/boot/dts/imx6dl-lanmcu.dts
@@ -21,6 +21,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
backlight: backlight {
@@ -109,14 +110,17 @@
status = "okay";
};
+&clks {
+ clocks = <&clock_ksz8081>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clock_ksz8081>;
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clock_ksz8081>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rgmii_phy>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts
index bf72a67a9c76..e98046eea7a4 100644
--- a/arch/arm/boot/dts/imx6dl-plybas.dts
+++ b/arch/arm/boot/dts/imx6dl-plybas.dts
@@ -75,6 +75,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_5v0: regulator-5v0 {
@@ -99,6 +100,13 @@
status = "okay";
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -116,10 +124,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rgmii_phy>;
status = "okay";
@@ -214,7 +218,7 @@
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- fsl,uart-has-rtscts;
+ uart-has-rtscts;
linux,rs485-enabled-at-boot-time;
rs485-rts-delay = <0 20>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts
index c4ce23d8ac9f..e3c10483f33b 100644
--- a/arch/arm/boot/dts/imx6dl-plym2m.dts
+++ b/arch/arm/boot/dts/imx6dl-plym2m.dts
@@ -84,6 +84,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_3v3: regulator-3v3 {
@@ -173,6 +174,13 @@
status = "okay";
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -196,7 +204,7 @@
compatible = "ti,tsc2046e-adc";
reg = <0>;
pinctrl-0 = <&pinctrl_tsc2046>;
- pinctrl-names ="default";
+ pinctrl-names = "default";
spi-max-frequency = <1000000>;
interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
#io-channel-cells = <1>;
@@ -254,10 +262,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rgmii_phy>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/imx6dl-prtmvt.dts
index a35a1c66e770..5f4fa796ca18 100644
--- a/arch/arm/boot/dts/imx6dl-prtmvt.dts
+++ b/arch/arm/boot/dts/imx6dl-prtmvt.dts
@@ -51,98 +51,98 @@
pinctrl-0 = <&pinctrl_gpiokeys>;
autorepeat;
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- f1 {
+ key-f1 {
label = "GPIO Key F1";
linux,code = <KEY_F1>;
gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>;
};
- f2 {
+ key-f2 {
label = "GPIO Key F2";
linux,code = <KEY_F2>;
gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>;
};
- f3 {
+ key-f3 {
label = "GPIO Key F3";
linux,code = <KEY_F3>;
gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>;
};
- f4 {
+ key-f4 {
label = "GPIO Key F4";
linux,code = <KEY_F4>;
gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>;
};
- f5 {
+ key-f5 {
label = "GPIO Key F5";
linux,code = <KEY_F5>;
gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>;
};
- cycle {
+ key-cycle {
label = "GPIO Key CYCLE";
linux,code = <KEY_CYCLEWINDOWS>;
gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>;
};
- esc {
+ key-esc {
label = "GPIO Key ESC";
linux,code = <KEY_ESC>;
gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>;
};
- up {
+ key-up {
label = "GPIO Key UP";
linux,code = <KEY_UP>;
gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>;
};
- down {
+ key-down {
label = "GPIO Key DOWN";
linux,code = <KEY_DOWN>;
gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>;
};
- ok {
+ key-ok {
label = "GPIO Key OK";
linux,code = <KEY_OK>;
gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>;
};
- f6 {
+ key-f6 {
label = "GPIO Key F6";
linux,code = <KEY_F6>;
gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>;
};
- f7 {
+ key-f7 {
label = "GPIO Key F7";
linux,code = <KEY_F7>;
gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>;
};
- f8 {
+ key-f8 {
label = "GPIO Key F8";
linux,code = <KEY_F8>;
gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>;
};
- f9 {
+ key-f9 {
label = "GPIO Key F9";
linux,code = <KEY_F9>;
gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>;
};
- f10 {
+ key-f10 {
label = "GPIO Key F10";
linux,code = <KEY_F10>;
gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>;
@@ -193,6 +193,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_1v8: regulator-1v8 {
@@ -293,8 +294,10 @@
};
&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>;
};
&ecspi1 {
@@ -314,10 +317,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rmii_phy>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts
index b86deebef7b7..a1eb53851794 100644
--- a/arch/arm/boot/dts/imx6dl-prtvt7.dts
+++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts
@@ -62,91 +62,91 @@
compatible = "gpio-keys";
autorepeat;
- esc {
+ key-esc {
label = "GPIO Key ESC";
linux,code = <KEY_ESC>;
gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>;
};
- up {
+ key-up {
label = "GPIO Key UP";
linux,code = <KEY_UP>;
gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>;
};
- down {
+ key-down {
label = "GPIO Key DOWN";
linux,code = <KEY_DOWN>;
gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>;
};
- enter {
+ key-enter {
label = "GPIO Key Enter";
linux,code = <KEY_ENTER>;
gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>;
};
- cycle {
+ key-cycle {
label = "GPIO Key CYCLE";
linux,code = <KEY_CYCLEWINDOWS>;
gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>;
};
- f1 {
+ key-f1 {
label = "GPIO Key F1";
linux,code = <KEY_F1>;
gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>;
};
- f2 {
+ key-f2 {
label = "GPIO Key F2";
linux,code = <KEY_F2>;
gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>;
};
- f3 {
+ key-f3 {
label = "GPIO Key F3";
linux,code = <KEY_F3>;
gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>;
};
- f4 {
+ key-f4 {
label = "GPIO Key F4";
linux,code = <KEY_F4>;
gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>;
};
- f5 {
+ key-f5 {
label = "GPIO Key F5";
linux,code = <KEY_F5>;
gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>;
};
- f6 {
+ key-f6 {
label = "GPIO Key F6";
linux,code = <KEY_F6>;
gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>;
};
- f7 {
+ key-f7 {
label = "GPIO Key F7";
linux,code = <KEY_F7>;
gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>;
};
- f8 {
+ key-f8 {
label = "GPIO Key F8";
linux,code = <KEY_F8>;
gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>;
};
- f9 {
+ key-f9 {
label = "GPIO Key F9";
linux,code = <KEY_F9>;
gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>;
};
- f10 {
+ key-f10 {
label = "GPIO Key F10";
linux,code = <KEY_F10>;
gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>;
@@ -344,7 +344,7 @@
compatible = "ti,tsc2046e-adc";
reg = <0>;
pinctrl-0 = <&pinctrl_tsc>;
- pinctrl-names ="default";
+ pinctrl-names = "default";
spi-max-frequency = <1000000>;
interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
#io-channel-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts
index 0f1616bfa9a8..b72f8ea1e6f6 100644
--- a/arch/arm/boot/dts/imx6dl-rex-basic.dts
+++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts
@@ -19,7 +19,7 @@
};
&ecspi3 {
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index e7d9bfbfd0e4..24c7f535f63b 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -25,14 +25,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
default-state = "off";
@@ -90,6 +90,7 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-handle = <&rgmii_phy>;
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts
index 227c952543d4..23274be08e61 100644
--- a/arch/arm/boot/dts/imx6dl-victgo.dts
+++ b/arch/arm/boot/dts/imx6dl-victgo.dts
@@ -5,60 +5,27 @@
*/
/dts-v1/;
-#include <dt-bindings/display/sdtv-standards.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/media/tvp5150.h>
-#include <dt-bindings/sound/fsl-imx-audmux.h>
#include "imx6dl.dtsi"
+#include "imx6qdl-vicut1.dtsi"
/ {
model = "Kverneland TGO";
compatible = "kvg,victgo", "fsl,imx6dl";
- chosen {
- stdout-path = &uart4;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_backlight>;
- pwms = <&pwm1 0 5000000 0>;
- brightness-levels = <0 16 64 255>;
- num-interpolated-steps = <16>;
- default-brightness-level = <1>;
- power-supply = <&reg_3v3>;
- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
- };
-
- connector {
- compatible = "composite-video-connector";
- label = "Composite0";
- sdtv-standards = <SDTV_STD_PAL_B>;
-
- port {
- comp0_out: endpoint {
- remote-endpoint = <&tvp5150_comp0_in>;
- };
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
autorepeat;
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- enter {
+ key-enter {
label = "Rotary Key";
gpios = <&gpio2 05 GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
@@ -71,36 +38,9 @@
io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>;
};
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
-
- led-0 {
- label = "debug0";
- function = LED_FUNCTION_HEARTBEAT;
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- label = "debug1";
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "disk-activity";
- };
-
- led-2 {
- label = "power_led";
- function = LED_FUNCTION_POWER;
- gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
panel {
- compatible = "kyo,tcg121xglp";
- backlight = <&backlight>;
+ compatible = "lg,lb070wv8";
+ backlight = <&backlight_lcd>;
power-supply = <&reg_3v3>;
port {
@@ -114,38 +54,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- };
-
- reg_1v8: regulator-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_h1_vbus: regulator-h1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "h1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_otg_vbus: regulator-otg-vbus {
- compatible = "regulator-fixed";
- regulator-name = "otg-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ clock-output-names = "enet_ref_pad";
};
rotary-encoder {
@@ -160,33 +69,6 @@
wakeup-source;
};
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "prti6q-sgtl5000";
- simple-audio-card,format = "i2s";
- simple-audio-card,widgets =
- "Microphone", "Microphone Jack",
- "Line", "Line In Jack",
- "Headphone", "Headphone Jack",
- "Speaker", "External Speaker";
- simple-audio-card,routing =
- "MIC_IN", "Microphone Jack",
- "LINE_IN", "Line In Jack",
- "Headphone Jack", "HP_OUT",
- "External Speaker", "LINE_OUT";
-
- simple-audio-card,cpu {
- sound-dai = <&ssi1>;
- system-clock-frequency = <0>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&codec>;
- bitclock-master;
- frame-master;
- };
- };
-
thermal-zones {
chassis-thermal {
polling-delay = <20000>;
@@ -213,7 +95,6 @@
<&adc_ts 5>;
io-channel-names = "y", "z1", "z2", "x";
touchscreen-min-pressure = <64687>;
- touchscreen-inverted-x;
touchscreen-inverted-y;
touchscreen-x-plate-ohms = <300>;
touchscreen-y-plate-ohms = <800>;
@@ -254,59 +135,11 @@
};
};
-&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "okay";
-
- mux-ssi1 {
- fsl,audmux-port = <0>;
- fsl,port-config = <
- IMX_AUDMUX_V2_PTCR_SYN 0
- IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
- IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
- IMX_AUDMUX_V2_PTCR_TFSDIR 0
- IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
- >;
- };
-
- mux-pins3 {
- fsl,audmux-port = <2>;
- fsl,port-config = <
- IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
- 0 IMX_AUDMUX_V2_PDCR_TXRXEN
- >;
- };
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can2>;
- status = "okay";
-};
-
&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
-};
-
-&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
- };
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
};
&ecspi2 {
@@ -319,7 +152,7 @@
compatible = "ti,tsc2046e-adc";
reg = <0>;
pinctrl-0 = <&pinctrl_touchscreen>;
- pinctrl-names ="default";
+ pinctrl-names = "default";
spi-max-frequency = <1000000>;
interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
#io-channel-cells = <1>;
@@ -357,10 +190,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rmii_phy>;
status = "okay";
@@ -385,36 +214,19 @@
"CAM2_MIRROR", "", "", "SMBALERT",
"DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
"SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
- "SD1_DATA3", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
- "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH",
- "POWER_LED", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
- "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ",
- "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
- "YACO_RESET";
+ "SD1_DATA3", "ETH_MDIO", "",
+ "", "", "", "", "", "", "", "ETH_MDC";
};
&gpio4 {
gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX",
- "", "", "DIP1_FB", "", "VCAM_EN", "", "", "",
- "CPU_LIGHT_ON", "", "ETH_RESET", "CPU_CONTACT_IN", "BL_EN",
- "BL_PWM", "ETH_INTRP", "ISB_LED";
+ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
+ "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
+ "CAN2_SR", "CAN2_TX", "CAN2_RX",
+ "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL",
+ "HITCH_IN_OUT",
+ "LIGHT_ON", "", "ETH_RESET", "CONTACT_IN", "BL_EN",
+ "BL_PWM", "ETH_INT", "ISB_LED";
};
&gpio5 {
@@ -422,51 +234,22 @@
"", "", "", "", "", "", "", "",
"TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO",
"ECSPI2_SS0", "ECSPI2_SCLK", "", "",
- "", "", "", "", "", "", "", "",
+ "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
+ "I2S_BITCLK", "I2S_DOUT",
"I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
"YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
};
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- codec: audio-codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0xa>;
- #sound-dai-cells = <0>;
- clocks = <&clks 201>;
- VDDA-supply = <&reg_3v3>;
- VDDIO-supply = <&reg_3v3>;
- VDDD-supply = <&reg_1v8>;
- };
-
- video-decoder@5c {
- compatible = "ti,tvp5150";
- reg = <0x5c>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tvp5150_comp0_in: endpoint {
- remote-endpoint = <&comp0_out>;
- };
- };
-
- /* Output port 2 is video output pad */
- port@2 {
- reg = <2>;
-
- tvp5151_to_ipu1_csi0_mux: endpoint {
- remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
- };
- };
- };
+&gpio6 {
+ gpio-line-names =
+ "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
+ "ITU656_D6", "ITU656_D7", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+&i2c1 {
keypad@70 {
compatible = "holtek,ht16k33";
pinctrl-names = "default";
@@ -490,225 +273,9 @@
MATRIX_KEY(6, 1, KEY_F1)
>;
};
-
- /* additional i2c devices are added automatically by the boot loader */
-};
-
-&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- adc@49 {
- compatible = "ti,ads1015";
- reg = <0x49>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@4 {
- reg = <4>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
-
- channel@5 {
- reg = <5>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
-
- channel@6 {
- reg = <6>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
-
- channel@7 {
- reg = <7>;
- ti,gain = <3>;
- ti,datarate = <3>;
- };
- };
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-
- tsens0: temperature-sensor@70 {
- compatible = "ti,tmp103";
- reg = <0x70>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&ipu1_csi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_csi0>;
- status = "okay";
-};
-
-&ipu1_csi0_mux_from_parallel_sensor {
- remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
-};
-
-&ldb {
- status = "okay";
-
- lvds-channel@0 {
- status = "okay";
-
- port@4 {
- reg = <4>;
-
- lvds0_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "okay";
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&ssi1 {
- #sound-dai-cells = <0>;
- fsl,mode = "ac97-slave";
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- status = "okay";
-};
-
-&usbh1 {
- vbus-supply = <&reg_h1_vbus>;
- pinctrl-names = "default";
- phy_type = "utmi";
- dr_mode = "host";
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <&reg_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- phy_type = "utmi";
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- disable-wp;
- cap-sd-highspeed;
- no-mmc;
- no-sdio;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- bus-width = <8>;
- no-1-8-v;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
};
&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_audmux: audmuxgrp {
- fsl,pins = <
- /* SGTL5000 sys_mclk */
- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
- >;
- };
-
- pinctrl_backlight: backlightgrp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
- >;
- };
-
- pinctrl_can1: can1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
- /* CAN1_SR */
- MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
- /* CAN1_TERM */
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088
- >;
- };
-
- pinctrl_can2: can2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
- /* CAN2_SR */
- MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- /* CS */
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
- >;
- };
-
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
@@ -747,113 +314,12 @@
>;
};
- pinctrl_hog: hoggrp {
- fsl,pins = <
- /* ITU656_nRESET */
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
- /* CAM1_MIRROR */
- MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0
- /* CAM2_MIRROR */
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
- /* CAM_nDETECT */
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
- /* ISB_IN1 */
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
- /* ISB_nIN2 */
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
- /* WARN_LIGHT */
- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0
- /* ON2_FB */
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0
- /* YACO_nIRQ */
- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
- /* YACO_BOOT0 */
- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0
- /* YACO_nRESET */
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
- /* FORCE_ON1 */
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
- /* AUDIO_nRESET */
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
- /* ITU656_nPDN */
- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
-
- /* HW revision detect */
- /* REV_ID0 */
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
- /* REV_ID1 is shared with PWM3 */
- /* REV_ID2 */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
- /* REV_ID3 */
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
- /* REV_ID4 */
- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
-
- /* New in HW revision 1 */
- /* ON1_FB */
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
- /* DIP1_FB */
- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_ipu1_csi0: ipu1csi0grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
- >;
- };
-
pinctrl_keypad: keypadgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
- pinctrl_leds: ledsgrp {
- fsl,pins = <
- /* DEBUG0 */
- MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0
- /* DEBUG1 */
- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
- /* POWER_LED */
- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
- >;
- };
-
- pinctrl_pwm1: pwm1grp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
- >;
- };
-
pinctrl_rotary_ch: rotarychgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@@ -867,77 +333,4 @@
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
>;
};
-
- /* YaCO AUX Uart */
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
- >;
- };
-
- /* YaCO Touchscreen UART */
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
- /* power enable, high active */
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
- MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
- MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
- >;
- };
};
diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/imx6dl-vicut1.dts
index 174fd913bf96..5035d303447d 100644
--- a/arch/arm/boot/dts/imx6dl-vicut1.dts
+++ b/arch/arm/boot/dts/imx6dl-vicut1.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-vicut1.dtsi"
+#include "imx6qdl-vicut1-12inch.dtsi"
/ {
model = "Kverneland UT1 Board";
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
index 674af39c884a..3be38a3c4bb1 100644
--- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
+++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
@@ -55,6 +55,7 @@
panel: panel {
compatible = "dataimage,scf0700c48ggu18";
power-supply = <&sw2_reg>;
+ backlight = <&backlight>;
status = "disabled";
port {
@@ -97,7 +98,6 @@
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
- status = "okay";
};
};
@@ -105,8 +105,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <20>;
phy-supply = <&sw2_reg>;
status = "okay";
@@ -130,6 +128,7 @@
switch@10 {
compatible = "qca,qca8334";
reg = <10>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
switch_ports: ports {
#address-cells = <1>;
@@ -269,11 +268,11 @@
compatible = "ti,lp5562";
reg = <0x30>;
clock-mode = /bits/ 8 <1>;
- status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
- chan@0 {
+ led@0 {
chan-name = "R";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
@@ -281,7 +280,7 @@
color = <LED_COLOR_ID_RED>;
};
- chan@1 {
+ led@1 {
chan-name = "G";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
@@ -289,7 +288,7 @@
color = <LED_COLOR_ID_GREEN>;
};
- chan@2 {
+ led@2 {
chan-name = "B";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
@@ -302,7 +301,6 @@
compatible = "atmel,24c128";
reg = <0x57>;
pagesize = <64>;
- status = "okay";
};
touchscreen: touchscreen@5c {
@@ -312,7 +310,7 @@
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
- reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
status = "disabled";
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts b/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts
new file mode 100644
index 000000000000..5c2cd517589b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2021 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6dl-yapp43-common.dtsi"
+
+/ {
+ model = "Y Soft IOTA Lynx i.MX6DualLite board";
+ compatible = "ysoft,imx6dl-yapp4-lynx", "fsl,imx6dl";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+};
+
+&backlight {
+ status = "okay";
+};
+
+&lcd_display {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+};
+
+&panel {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&reg_usb_h1_vbus {
+ status = "okay";
+};
+
+&touchscreen {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts b/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts
new file mode 100644
index 000000000000..e0292f11d03e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2021 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6dl-yapp43-common.dtsi"
+
+/ {
+ model = "Y Soft IOTA Phoenix i.MX6DualLite board";
+ compatible = "ysoft,imx6dl-yapp4-phoenix", "fsl,imx6dl";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+};
+
+&aliases {
+ /delete-property/ ethernet1;
+};
+
+&gpio_keys {
+ status = "okay";
+};
+
+&reg_usb_h1_vbus {
+ status = "okay";
+};
+
+&switch_ports {
+ /delete-node/ port@2;
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi
new file mode 100644
index 000000000000..52a0f6ee426f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2021 Y Soft Corporation, a.s.
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ aliases: aliases {
+ ethernet1 = &eth1;
+ ethernet2 = &eth2;
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc4;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 32 64 128 255>;
+ default-brightness-level = <32>;
+ num-interpolated-steps = <8>;
+ power-supply = <&sw2_reg>;
+ status = "disabled";
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+ status = "disabled";
+
+ button {
+ label = "Factory RESET";
+ linux,code = <BTN_0>;
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ lcd_display: display {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel: panel {
+ compatible = "dataimage,scf0700c48ggu18";
+ power-supply = <&sw2_reg>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1_vbus>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_vbus>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&sw2_reg>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "marvell,mv88e6085";
+ reg = <0>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+
+ switch_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: port@0 {
+ reg = <0>;
+ label = "cpu";
+ phy-mode = "rgmii-id";
+ ethernet = <&fec>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ eth2: port@1 {
+ reg = <1>;
+ label = "eth2";
+ phy-handle = <&phy_port1>;
+ };
+
+ eth1: port@2 {
+ reg = <2>;
+ label = "eth1";
+ phy-handle = <&phy_port2>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port1: switchphy@11 {
+ reg = <0x11>;
+ };
+
+ phy_port2: switchphy@12 {
+ reg = <0x12>;
+ };
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@8 {
+ compatible = "fsl,pfuze200";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x8>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vsnvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ leds: led-controller@30 {
+ compatible = "ti,lp5562";
+ reg = <0x30>;
+ clock-mode = /bits/ 8 <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ led@0 {
+ chan-name = "R";
+ led-cur = /bits/ 8 <0x20>;
+ max-cur = /bits/ 8 <0x60>;
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@1 {
+ chan-name = "G";
+ led-cur = /bits/ 8 <0x20>;
+ max-cur = /bits/ 8 <0x60>;
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@2 {
+ chan-name = "B";
+ led-cur = /bits/ 8 <0x20>;
+ max-cur = /bits/ 8 <0x60>;
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c128";
+ reg = <0x57>;
+ pagesize = <64>;
+ };
+
+ touchscreen: touchscreen@5c {
+ compatible = "pixcir,pixcir_tangoc";
+ reg = <0x5c>;
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ status = "disabled";
+ };
+
+ rtc: rtc@68 {
+ compatible = "dallas,ds1341";
+ reg = <0x68>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "disabled";
+
+ oled_1309: oled@3c {
+ compatible = "solomon,ssd1309fb-i2c";
+ reg = <0x3c>;
+ solomon,height = <64>;
+ solomon,width = <128>;
+ solomon,page-offset = <0>;
+ solomon,segment-no-remap;
+ solomon,prechargep2 = <15>;
+ reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
+ vbat-supply = <&sw2_reg>;
+ status = "disabled";
+ };
+
+ oled_1305: oled@3d {
+ compatible = "solomon,ssd1305fb-i2c";
+ reg = <0x3d>;
+ solomon,height = <64>;
+ solomon,width = <128>;
+ solomon,page-offset = <0>;
+ solomon,col-offset = <4>;
+ solomon,prechargep2 = <15>;
+ reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
+ vbat-supply = <&sw2_reg>;
+ status = "disabled";
+ };
+
+ gpio_oled: gpio@41 {
+ compatible = "nxp,pca9536";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x41>;
+ vcc-supply = <&sw2_reg>;
+ status = "disabled";
+ };
+
+ touchkeys: keys@5a {
+ compatible = "fsl,mpr121-touchkey";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchkeys>;
+ reg = <0x5a>;
+ vdd-supply = <&sw2_reg>;
+ autorepeat;
+ linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>,
+ <KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>,
+ <KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>;
+ poll-interval = <50>;
+ status = "disabled";
+ };
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
+ >;
+ };
+
+ pinctrl_ipu1: ipu1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098
+ >;
+ };
+
+ pinctrl_touchkeys: touchkeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b098
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098
+ MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
+ >;
+ };
+
+ pinctrl_usbh1_vbus: usbh1-vbus {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098
+ MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098
+ >;
+ };
+
+ pinctrl_usbotg_vbus: usbotg-vbus {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
+ >;
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "disabled";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ vbus-supply = <&reg_usb_h1_vbus>;
+ over-current-active-low;
+ status = "disabled";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ vbus-supply = <&reg_usb_otg_vbus>;
+ over-current-active-low;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+ status = "okay";
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <109>;
+ status = "disabled";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ vmmc-supply = <&sw2_reg>;
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&wdog2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index fdd81fdc3f35..dc919e09a505 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -80,10 +80,13 @@
};
};
- soc {
+ soc: soc {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
+ ranges = <0 0x00900000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index a0683b4aeca1..3fc079dfd61e 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
@@ -30,89 +30,26 @@
stdout-path = "serial0:115200n8";
};
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- wakeup {
- label = "Wake-Up";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- lcd_display: disp0 {
- compatible = "fsl,imx-parallel-display";
- #address-cells = <1>;
- #size-cells = <0>;
- interface-pix-fmt = "rgb24";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_lcdif>;
- status = "okay";
-
- port@0 {
- reg = <0>;
-
- lcd_display_in: endpoint {
- remote-endpoint = <&ipu1_di1_disp1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
-
- panel: panel {
- /*
- * edt,et057090dhu: EDT 5.7" LCD TFT
- * edt,et070080dh6: EDT 7.0" LCD TFT
- */
- compatible = "edt,et057090dhu";
- backlight = <&backlight>;
- power-supply = <&reg_3v3_sw>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
reg_pcie_switch: regulator-pcie-switch {
compatible = "regulator-fixed";
- regulator-name = "pcie_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ enable-active-high;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "pcie_switch";
startup-delay-us = <100000>;
- enable-active-high;
status = "okay";
};
reg_3v3_sw: regulator-3v3-sw {
compatible = "regulator-fixed";
- regulator-name = "3.3V_SW";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V_SW";
};
};
-&backlight {
- brightness-levels = <0 127 191 223 239 247 251 255>;
- default-brightness-level = <1>;
- power-supply = <&reg_3v3_sw>;
- status = "okay";
-};
-
&can1 {
xceiver-supply = <&reg_3v3_sw>;
status = "okay";
@@ -123,27 +60,10 @@
status = "okay";
};
-&hdmi {
- status = "okay";
-};
-
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
status = "okay";
- /*
- * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
- */
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- reg = <0x4a>;
- interrupt-parent = <&gpio6>;
- interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
- reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */
- status = "disabled";
- };
-
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;
@@ -164,14 +84,6 @@
status = "okay";
};
-&ipu1_di1_disp1 {
- remote-endpoint = <&lcd_display_in>;
-};
-
-&ldb {
- status = "okay";
-};
-
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
@@ -198,11 +110,11 @@
status = "okay";
};
-&reg_usb_otg_vbus {
+&reg_usb_host_vbus {
status = "okay";
};
-&reg_usb_host_vbus {
+&reg_usb_otg_vbus {
status = "okay";
};
@@ -235,39 +147,26 @@
};
&usbh1 {
+ disable-over-current;
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
+ disable-over-current;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
/* MMC1 */
&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
- cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* SD1 */
&usdhc2 {
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
status = "okay";
};
-
-&iomuxc {
- /*
- * Mux the Apalis GPIOs
- */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
- &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
- &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
- &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
- >;
-};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index 86e84781cf5d..44637d606e61 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -1,274 +1,37 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "imx6q.dtsi"
-#include "imx6qdl-apalis.dtsi"
+#include "imx6q-apalis-ixora-v1.2.dts"
/ {
model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1";
- compatible = "toradex,apalis_imx6q-ixora-v1.1",
- "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
+ compatible = "toradex,apalis_imx6q-ixora-v1.1", "toradex,apalis_imx6q",
"fsl,imx6q";
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c3;
- i2c2 = &i2c2;
- rtc0 = &rtc_i2c;
- rtc1 = &snvs_rtc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- wakeup {
- label = "Wake-Up";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- lcd_display: disp0 {
- compatible = "fsl,imx-parallel-display";
- #address-cells = <1>;
- #size-cells = <0>;
- interface-pix-fmt = "rgb24";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_lcdif>;
- status = "okay";
-
- port@0 {
- reg = <0>;
-
- lcd_display_in: endpoint {
- remote-endpoint = <&ipu1_di1_disp1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
- panel: panel {
- /*
- * edt,et057090dhu: EDT 5.7" LCD TFT
- * edt,et070080dh6: EDT 7.0" LCD TFT
- */
- compatible = "edt,et057090dhu";
- backlight = <&backlight>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds_ixora>;
-
- led4-green {
- label = "LED_4_GREEN";
- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- };
-
- led4-red {
- label = "LED_4_RED";
- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
-
- led5-green {
- label = "LED_5_GREEN";
- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- };
-
- led5-red {
- label = "LED_5_RED";
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- };
- };
};
-&backlight {
- brightness-levels = <0 127 191 223 239 247 251 255>;
- default-brightness-level = <1>;
- status = "okay";
-};
+/delete-node/ &eeprom;
+/delete-node/ &reg_3v3_vmmc;
+/delete-node/ &reg_can1_supply;
+/delete-node/ &reg_can2_supply;
&can1 {
- status = "okay";
+ /delete-property/ xceiver-supply;
};
&can2 {
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
-&i2c1 {
- status = "okay";
-
- /*
- * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
- */
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- reg = <0x4a>;
- interrupt-parent = <&gpio6>;
- interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
- reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */
- status = "disabled";
- };
-
- /* M41T0M6 real time clock on carrier board */
- rtc_i2c: rtc@68 {
- compatible = "st,m41t0";
- reg = <0x68>;
- };
-};
-
-/*
- * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
- * board)
- */
-&i2c3 {
- status = "okay";
-};
-
-&ipu1_di1_disp1 {
- remote-endpoint = <&lcd_display_in>;
-};
-
-&ldb {
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reset_moci>;
- /* active-high meaning opposite of regular PERST# active-low polarity */
- reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- reset-gpio-active-high;
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pwm3 {
- status = "okay";
-};
-
-&pwm4 {
- status = "okay";
-};
-
-&reg_usb_otg_vbus {
- status = "okay";
-};
-
-&reg_usb_host_vbus {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&sound_spdif {
- status = "okay";
-};
-
-&spdif {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-};
-
-&uart5 {
- status = "okay";
-};
-
-&usbh1 {
- vbus-supply = <&reg_usb_host_vbus>;
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <&reg_usb_otg_vbus>;
- status = "okay";
+ /delete-property/ xceiver-supply;
};
/* MMC1 */
&usdhc1 {
+ /delete-property/ cap-power-off-card;
+ /delete-property/ pinctrl-1;
+ /delete-property/ vmmc-supply;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
- cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- status = "okay";
-};
-
-&iomuxc {
- /*
- * Mux the Apalis GPIOs
- */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
- &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
- &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
- &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
- >;
-
- pinctrl_leds_ixora: ledsixoragrp {
- fsl,pins = <
- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- >;
- };
};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
new file mode 100644
index 000000000000..717decda0ceb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2014-2022 Toradex
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.2";
+ compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q",
+ "fsl,imx6q";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ i2c2 = &i2c2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds_ixora>;
+
+ led4-green {
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ label = "LED_4_GREEN";
+ };
+
+ led4-red {
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ label = "LED_4_RED";
+ };
+
+ led5-green {
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ label = "LED_5_GREEN";
+ };
+
+ led5-red {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ label = "LED_5_RED";
+ };
+ };
+
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3v3_vmmc";
+ startup-delay-us = <100>;
+ };
+
+ reg_can1_supply: regulator-can1-supply {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can1_power>;
+ regulator-name = "can1_supply";
+ };
+
+ reg_can2_supply: regulator-can2-supply {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can2_power>;
+ regulator-name = "can2_supply";
+ };
+};
+
+&can1 {
+ xceiver-supply = <&reg_can1_supply>;
+ status = "okay";
+};
+
+&can2 {
+ xceiver-supply = <&reg_can2_supply>;
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart24_forceoff>;
+
+ /*
+ * uart-2-4-on-x21-enable-hog enables the UART transceiver for Apalis
+ * UART2 and UART3. If one wants to disable the transceiver force
+ * the GPIO to output-low, if one wants to control the transceiver
+ * from user space delete the hog node.
+ */
+ uart-2-4-on-x21-enable-hog {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>; /* MXM3 180 */
+ output-high;
+ };
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_moci>;
+ /* active-high meaning opposite of regular PERST# active-low polarity */
+ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ reset-gpio-active-high;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&reg_usb_otg_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sound_spdif {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ disable-over-current;
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ disable-over-current;
+ vbus-supply = <&reg_usb_otg_vbus>;
+ status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>;
+ bus-width = <4>;
+ cap-power-off-card;
+ vmmc-supply = <&reg_3v3_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_enable_can1_power: enablecan1powergrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ >;
+ };
+
+ pinctrl_enable_can2_power: enablecan2powergrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart24_forceoff: uart24forceoffgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_leds_ixora: ledsixoragrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_mmc_cd_sleep: mmccdslpgrp {
+ fsl,pins = <
+ /* MMC1 CD */
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0
+ >;
+ };
+
+ pinctrl_usdhc1_4bit_sleep: usdhc1-4bitslpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 62e72773e53b..f338be435277 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
@@ -30,95 +30,33 @@
stdout-path = "serial0:115200n8";
};
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- wakeup {
- label = "Wake-Up";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- lcd_display: disp0 {
- compatible = "fsl,imx-parallel-display";
- #address-cells = <1>;
- #size-cells = <0>;
- interface-pix-fmt = "rgb24";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_lcdif>;
- status = "okay";
-
- port@0 {
- reg = <0>;
-
- lcd_display_in: endpoint {
- remote-endpoint = <&ipu1_di1_disp1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
-
- panel: panel {
- /*
- * edt,et057090dhu: EDT 5.7" LCD TFT
- * edt,et070080dh6: EDT 7.0" LCD TFT
- */
- compatible = "edt,et057090dhu";
- backlight = <&backlight>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
leds {
compatible = "gpio-leds";
-
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_ixora>;
led4-green {
- label = "LED_4_GREEN";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ label = "LED_4_GREEN";
};
led4-red {
- label = "LED_4_RED";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ label = "LED_4_RED";
};
led5-green {
- label = "LED_5_GREEN";
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ label = "LED_5_GREEN";
};
led5-red {
- label = "LED_5_RED";
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ label = "LED_5_RED";
};
};
};
-&backlight {
- brightness-levels = <0 127 191 223 239 247 251 255>;
- default-brightness-level = <1>;
- status = "okay";
-};
-
&can1 {
status = "okay";
};
@@ -127,27 +65,10 @@
status = "okay";
};
-&hdmi {
- status = "okay";
-};
-
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
status = "okay";
- /*
- * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
- */
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- reg = <0x4a>;
- interrupt-parent = <&gpio6>;
- interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
- reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */
- status = "disabled";
- };
-
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -168,14 +89,6 @@
status = "okay";
};
-&ipu1_di1_disp1 {
- remote-endpoint = <&lcd_display_in>;
-};
-
-&ldb {
- status = "okay";
-};
-
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
@@ -201,11 +114,11 @@
status = "okay";
};
-&reg_usb_otg_vbus {
+&reg_usb_host_vbus {
status = "okay";
};
-&reg_usb_host_vbus {
+&reg_usb_otg_vbus {
status = "okay";
};
@@ -238,32 +151,26 @@
};
&usbh1 {
+ disable-over-current;
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
+ disable-over-current;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
/* SD1 */
&usdhc2 {
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
- /* Mux the Apalis GPIOs */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
- &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
- &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
- &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
- >;
-
pinctrl_leds_ixora: ledsixoragrp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 0b40f52268b3..75586299d9ca 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -178,6 +178,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index 6330d75f8f39..f266f1b7e0cf 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -142,7 +142,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: n25q032@0 {
+ flash: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6q-bosch-acc.dts
new file mode 100644
index 000000000000..8263bfef9bf8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-bosch-acc.dts
@@ -0,0 +1,779 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support for the i.MX6-based Bosch ACC board.
+ *
+ * Copyright (C) 2016 Garz & Fricke GmbH
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de>
+ * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
+ * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "imx6q.dtsi"
+
+/ {
+ model = "Bosch ACC";
+ compatible = "bosch,imx6q-acc", "fsl,imx6q";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc4;
+ mmc1 = &usdhc2;
+ serial0 = &uart2;
+ serial1 = &uart1;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ backlight_lvds: backlight-lvds {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 200000>;
+ brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
+ num-interpolated-steps = <10>;
+ default-brightness-level = <60>;
+ power-supply = <&reg_lcd>;
+ };
+
+ panel {
+ compatible = "dataimage,fg1001l0dsswmg01";
+ backlight = <&backlight_lvds>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ refclk: refclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "12mhz_refclk";
+ assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
+ <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_CKO2_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
+ <&clks IMX6QDL_CLK_CKO2_PODF>,
+ <&clks IMX6QDL_CLK_OSC>;
+ assigned-clock-rates = <0>, <12000000>, <0>;
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1225000
+ 852000 1225000
+ 792000 1150000
+ 396000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 1200000 1225000
+ 996000 1175000
+ 852000 1175000
+ 792000 1150000
+ 396000 1150000
+ >;
+ };
+
+ cpu1: cpu@1 {
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1225000
+ 852000 1225000
+ 792000 1150000
+ 396000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 1200000 1225000
+ 996000 1175000
+ 852000 1175000
+ 792000 1150000
+ 396000 1150000
+ >;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led_red: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = <&pwm2 0 500000>;
+ };
+
+ led_white: led-1 {
+ color = <LED_COLOR_ID_WHITE>;
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = <&pwm3 0 500000>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_gpio_led>;
+
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_5p0: regulator-5p0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5p0";
+ };
+
+ reg_vin: regulator-vin {
+ compatible = "regulator-fixed";
+ regulator-name = "VIN";
+ regulator-min-microvolt = <4500000>;
+ regulator-max-microvolt = <4500000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_usb_h2_vbus: regulator-usb-h2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_5p0> ;
+ regulator-always-on;
+ };
+
+ reg_vsnvs: regulator-vsnvs {
+ compatible = "regulator-fixed";
+ regulator-name = "VSNVS_3V0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD0 POWER";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_enable>;
+ gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ reg_dac: regulator-dac {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_dac";
+ regulator-min-microvolt = <20000>;
+ regulator-max-microvolt = <20000>;
+ vin-supply = <&reg_5p0> ;
+ regulator-boot-on;
+ };
+
+ reg_sw4: regulator-sw4 {
+ compatible = "regulator-fixed";
+ regulator-name = "SW4_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+
+ reg_sys: regulator-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "SYS_4V2";
+ regulator-min-microvolt = <4200000>;
+ regulator-max-microvolt = <4200000>;
+ regulator-always-on;
+ vin-supply = <&reg_5p0>;
+ };
+};
+
+&reg_arm {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_soc {
+ vin-supply = <&sw1c_reg>;
+};
+
+&reg_vdd1p1 {
+ vin-supply = <&reg_vsnvs>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&reg_vsnvs>;
+};
+
+&reg_vdd3p0 {
+ vin-supply = <&reg_vsnvs>;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_out";
+ phy-mode = "rmii";
+ phy-supply = <&reg_sw4>;
+ phy-handle = <&ethphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ smsc,disable-energy-detect;
+ };
+ };
+};
+
+&gpu_vg {
+ status = "disabled";
+};
+
+&gpu_2d {
+ status = "disabled";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1c_reg: sw1c {
+ regulator-name = "VDD_SOC (sw1abc)";
+ regulator-min-microvolt = <1275000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-name = "VDD_ARM (sw2)";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR_1V5a";
+ regulator-boot-on;
+ regulator-always-on;
+
+ };
+
+ sw3b_reg: sw3b {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR_1V5b";
+ regulator-boot-on;
+ regulator-always-on;
+
+ };
+
+ sw4_reg: sw4 {
+ regulator-name = "AUX 3V15 (sw4)";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ status = "disabled";
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ lm75: sensor@49 {
+ compatible = "national,lm75b";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm75>;
+ reg = <0x49>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ rtc: rtc@51 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ eeprom_ext: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ usb3503: usb@8 {
+ compatible = "smsc,usb3503";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3503>;
+ reg = <0x08>;
+ connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */
+ intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */
+ initial-mode = <1>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
+ refclk-frequency = <12000000>;
+ };
+
+ exc3000: touchscreen@2a {
+ compatible = "eeti,exc3000";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctouch>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ };
+
+ vcnl4035: light-sensor@60 {
+ compatible = "vishay,vcnl4035";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_proximity>;
+ reg = <0x60>;
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbh2 {
+ pinctrl-names = "idle", "active";
+ pinctrl-0 = <&pinctrl_usbh2_idle>;
+ pinctrl-1 = <&pinctrl_usbh2_active>;
+ vbus-supply = <&reg_usb_h2_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ vbus-supply = <&reg_usb_otg_vbus>;
+ disable-over-current;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbphynop1 {
+ clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+ clock-names = "main_clk";
+ vcc-supply = <&reg_usb_h1_vbus>;
+};
+
+&usbphynop2 {
+ vcc-supply = <&reg_usb_h2_vbus>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ voltage-ranges = <3300 3300>;
+ vmmc-supply = <&reg_sw4>;
+ fsl,wp-controller;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ voltage-ranges = <3300 3300>;
+ vmmc-supply = <&reg_sw4>;
+ fsl,wp-controller;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog1>;
+ fsl,ext-reset-output;
+ timeout-sec = <10>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
+ };
+
+ pinctrl_reset_gpio_led: reset-gpio-led-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_lcd_enable: lcdenablegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */
+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */
+ >;
+ };
+
+ pinctrl_lm75: lm75grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_proximity: proximitygrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0
+ >;
+ };
+
+ pinctrl_rtc: rtc-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */
+ >;
+ };
+
+ pinctrl_ctouch: ctouch-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh2_idle: usbh2-idle-grp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018
+ >;
+ };
+
+ pinctrl_usbh2_active: usbh2-active-grp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
+ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018
+ >;
+ };
+
+ pinctrl_usb3503: usb3503-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */
+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069
+ MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059
+ >;
+ };
+
+ pinctrl_wdog1: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index 10922375c51e..ead83091e193 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -160,7 +160,7 @@
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
- m25_eeprom: m25p80@0 {
+ m25_eeprom: flash@0 {
compatible = "atmel,at25";
spi-max-frequency = <10000000>;
size = <0x8000>;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index bfb530f29d9d..1ad41c944b4b 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -260,7 +260,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index c713ac03b3b9..9591848cbd37 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -102,7 +102,7 @@
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "m25p80", "jedec,spi-nor";
spi-max-frequency = <40000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts
index 48fb47e715f6..137db38f0d27 100644
--- a/arch/arm/boot/dts/imx6q-dms-ba16.dts
+++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts
@@ -47,7 +47,7 @@
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
- m25_eeprom: m25p80@0 {
+ m25_eeprom: flash@0 {
compatible = "atmel,at25256B", "atmel,at25";
spi-max-frequency = <20000000>;
size = <0x8000>;
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index c63f371ede8b..78d941fef5df 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -146,6 +146,7 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
index ccc2487d47ca..2fda68f9d3f6 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2013 Philipp Zabel
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013 Philipp Zabel
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 4cde45d5c90c..522a51042965 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -34,20 +34,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */
default-state = "off";
@@ -137,7 +137,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,w25q256", "jedec,spi-nor";
spi-max-frequency = <30000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts
index b8feadbff967..6406ade14f57 100644
--- a/arch/arm/boot/dts/imx6q-h100.dts
+++ b/arch/arm/boot/dts/imx6q-h100.dts
@@ -76,19 +76,19 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_h100_leds>;
- led0: power {
+ led0: led-power {
label = "power";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- led1: stream {
+ led1: led-stream {
label = "stream";
gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- led2: rec {
+ led2: led-rec {
label = "rec";
gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/imx6q-kp.dtsi
index 1ade0bff681d..5e0ed5560040 100644
--- a/arch/arm/boot/dts/imx6q-kp.dtsi
+++ b/arch/arm/boot/dts/imx6q-kp.dtsi
@@ -66,14 +66,14 @@
leds {
compatible = "gpio-leds";
- green {
+ led-green {
label = "led1";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "off";
};
- red {
+ led-red {
label = "led0";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index 05ee28388229..2c9961333b0a 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -73,14 +73,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- user1 {
+ led-user1 {
label = "imx6:green:user1";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
- user2 {
+ led-user2 {
label = "imx6:green:user2";
gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
default-state = "off";
@@ -100,7 +100,7 @@
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts
index 55692c73943d..f08b37010291 100644
--- a/arch/arm/boot/dts/imx6q-mccmon6.dts
+++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
@@ -100,8 +100,10 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,err006687-workaround-present;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 225cf6b7a7a4..ee8c0bd3ecfd 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -86,7 +86,7 @@
linux,code = <KEY_POWER>;
};
- lid {
+ lid-event {
label = "Lid";
gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
linux,input-type = <5>; /* EV_SW */
@@ -99,7 +99,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_novena>;
- heartbeat {
+ led-heartbeat {
label = "novena:white:panel";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts
index 7a33e54cc0f1..bad8d831e64e 100644
--- a/arch/arm/boot/dts/imx6q-pistachio.dts
+++ b/arch/arm/boot/dts/imx6q-pistachio.dts
@@ -100,7 +100,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wakeup-source;
diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/imx6q-prti6q.dts
index b4605edfd2ab..d8fa83effd63 100644
--- a/arch/arm/boot/dts/imx6q-prti6q.dts
+++ b/arch/arm/boot/dts/imx6q-prti6q.dts
@@ -364,8 +364,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
- ref-clock-frequency = "38400000";
- tcxo-clock-frequency = "19200000";
+ ref-clock-frequency = <38400000>;
+ tcxo-clock-frequency = <19200000>;
};
};
diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/imx6q-prtwd2.dts
index 349959d38020..54a57a4548e2 100644
--- a/arch/arm/boot/dts/imx6q-prtwd2.dts
+++ b/arch/arm/boot/dts/imx6q-prtwd2.dts
@@ -22,6 +22,13 @@
reg = <0x80000000 0x20000000>;
};
+ clk50m_phy: phy-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
+ };
+
usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -49,13 +56,17 @@
status = "okay";
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>;
- clock-names = "ipg", "ahb";
status = "okay";
fixed-link {
diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts
index 1767e1a3cd53..271f4b2d9b9f 100644
--- a/arch/arm/boot/dts/imx6q-rex-pro.dts
+++ b/arch/arm/boot/dts/imx6q-rex-pro.dts
@@ -19,7 +19,7 @@
};
&ecspi3 {
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf032b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index dc51262e7b2f..7c6a2f234ccb 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -1,43 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts
index 7f1f19b74bfa..a3f247c722b4 100644
--- a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts
+++ b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts
@@ -125,3 +125,9 @@
>;
};
};
+
+&reg_tft_vcom {
+ regulator-min-microvolt = <3160000>;
+ regulator-max-microvolt = <3160000>;
+ voltage-table = <3160000 73>;
+};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index 8daef65d5bb3..2f576e2ce73f 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -49,7 +49,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- blue {
+ led-blue {
label = "blue_status_led";
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
index d16ff2083d62..ad59b23ef27a 100644
--- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -89,7 +89,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- power {
+ key-power {
label = "Power Button";
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
index 63550351340d..2290c1237634 100644
--- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
+++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
@@ -28,7 +28,7 @@
compatible = "gpio-keys";
autorepeat;
- back {
+ key-back {
gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
label = "Key Back";
@@ -37,7 +37,7 @@
wakeup-source;
};
- home {
+ key-home {
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
label = "Key Home";
@@ -46,7 +46,7 @@
wakeup-source;
};
- menu {
+ key-menu {
gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
label = "Key Menu";
diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts
index 0a4e251be162..dd91aff3f9e2 100644
--- a/arch/arm/boot/dts/imx6q-vicut1.dts
+++ b/arch/arm/boot/dts/imx6q-vicut1.dts
@@ -6,12 +6,9 @@
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-vicut1.dtsi"
+#include "imx6qdl-vicut1-12inch.dtsi"
/ {
model = "Kverneland UT1Q Board";
compatible = "kvg,vicut1q", "fsl,imx6q";
};
-
-&sata {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/imx6q-yapp4-crux.dts
index 15f4824a5142..bddf3822ebf7 100644
--- a/arch/arm/boot/dts/imx6q-yapp4-crux.dts
+++ b/arch/arm/boot/dts/imx6q-yapp4-crux.dts
@@ -33,6 +33,10 @@
status = "okay";
};
+&reg_pu {
+ regulator-always-on;
+};
+
&reg_usb_h1_vbus {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts b/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts
new file mode 100644
index 000000000000..ec6651ba4ba2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2021 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6dl-yapp43-common.dtsi"
+
+/ {
+ model = "Y Soft IOTA Pegasus i.MX6Quad board";
+ compatible = "ysoft,imx6q-yapp4-pegasus", "fsl,imx6q";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0xf0000000>;
+ };
+};
+
+&gpio_oled {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+};
+
+&oled_1305 {
+ status = "okay";
+};
+
+&oled_1309 {
+ status = "okay";
+};
+
+&reg_pu {
+ regulator-always-on;
+};
+
+&reg_usb_h1_vbus {
+ status = "okay";
+};
+
+&touchkeys {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 9caba4529c71..df86049a695b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -159,14 +159,17 @@
};
};
- soc {
+ soc: soc {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
+ ranges = <0 0x00900000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- bus@2000000 { /* AIPS1 */
+ aips1: bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index ed2739e39085..4cc965277c52 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -1,11 +1,12 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "Toradex Apalis iMX6Q/D Module";
@@ -19,88 +20,182 @@
backlight: backlight {
compatible = "pwm-backlight";
+ brightness-levels = <0 45 63 88 119 158 203 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
- pwms = <&pwm4 0 5000000>;
- enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ power-supply = <&reg_module_3v3>;
+ pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>;
+ status = "disabled";
+ };
+
+ clk_ov5640_osc: clk-ov5640-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-wakeup {
+ debounce-interval = <10>;
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ lcd_display: disp0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di1_disp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel_dpi: panel-dpi {
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+
+ status = "disabled";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ panel_lvds: panel-lvds {
+ compatible = "panel-lvds";
+ backlight = <&backlight>;
status = "disabled";
+
+ port {
+ lvds_panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
};
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
- regulator-name = "+V3.3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3";
};
reg_module_3v3_audio: regulator-module-3v3-audio {
compatible = "regulator-fixed";
- regulator-name = "+V3.3_AUDIO";
- regulator-min-microvolt = <3300000>;
+ regulator-always-on;
regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_AUDIO";
+ };
+
+ reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd {
+ compatible = "regulator-fixed";
regulator-always-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "DOVDD/DVDD_1.8V";
+ /* Note: The CSI module uses on-board 3.3V_SW supply */
+ vin-supply = <&reg_module_3v3>;
+ };
+
+ reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-name = "AVDD/AFVDD_2.8V";
+ /* Note: The CSI module uses on-board 3.3V_SW supply */
+ vin-supply = <&reg_module_3v3>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
- regulator-name = "usb_otg_vbus";
- regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_otg_vbus";
status = "disabled";
};
/* on module USB hub */
reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
- regulator-name = "usb_host_vbus_hub";
- regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_host_vbus_hub";
startup-delay-us = <2000>;
- enable-active-high;
status = "okay";
};
reg_usb_host_vbus: regulator-usb-host-vbus {
compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
- regulator-name = "usb_host_vbus";
- regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_host_vbus";
vin-supply = <&reg_usb_host_vbus_hub>;
status = "disabled";
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
- model = "imx6q-apalis-sgtl5000";
- ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
- mux-int-port = <1>;
+ model = "imx6q-apalis-sgtl5000";
mux-ext-port = <4>;
+ mux-int-port = <1>;
+ ssi-controller = <&ssi1>;
};
sound_spdif: sound-spdif {
compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
spdif-out;
+ model = "imx-spdif";
status = "disabled";
};
};
@@ -125,6 +220,10 @@
status = "disabled";
};
+&clks {
+ fsl,pmic-stby-poweroff;
+};
+
/* Apalis SPI1 */
&ecspi1 {
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
@@ -141,6 +240,214 @@
status = "disabled";
};
+&gpio1 {
+ gpio-line-names = "MXM3_84",
+ "MXM3_4",
+ "MXM3_15/GPIO7",
+ "MXM3_96",
+ "MXM3_37",
+ "",
+ "MXM3_17/GPIO8",
+ "MXM3_14",
+ "MXM3_12",
+ "MXM3_2",
+ "MXM3_184",
+ "MXM3_180",
+ "MXM3_178",
+ "MXM3_176",
+ "MXM3_188",
+ "MXM3_186",
+ "MXM3_160",
+ "MXM3_162",
+ "MXM3_150",
+ "MXM3_144",
+ "MXM3_154",
+ "MXM3_146",
+ "",
+ "",
+ "MXM3_72";
+};
+
+&gpio2 {
+ gpio-line-names = "MXM3_148",
+ "MXM3_152",
+ "MXM3_156",
+ "MXM3_158",
+ "MXM3_1/GPIO1",
+ "MXM3_3/GPIO2",
+ "MXM3_5/GPIO3",
+ "MXM3_7/GPIO4",
+ "MXM3_95",
+ "MXM3_6",
+ "MXM3_8",
+ "MXM3_123",
+ "MXM3_126",
+ "MXM3_128",
+ "MXM3_130",
+ "MXM3_132",
+ "MXM3_253",
+ "MXM3_251",
+ "MXM3_283",
+ "MXM3_281",
+ "MXM3_279",
+ "MXM3_277",
+ "MXM3_243",
+ "MXM3_235",
+ "MXM3_231",
+ "MXM3_229",
+ "MXM3_233",
+ "MXM3_198",
+ "MXM3_275",
+ "MXM3_273",
+ "MXM3_207",
+ "MXM3_122";
+};
+
+&gpio3 {
+ gpio-line-names = "MXM3_271",
+ "MXM3_269",
+ "MXM3_301",
+ "MXM3_299",
+ "MXM3_297",
+ "MXM3_295",
+ "MXM3_293",
+ "MXM3_291",
+ "MXM3_289",
+ "MXM3_287",
+ "MXM3_249",
+ "MXM3_247",
+ "MXM3_245",
+ "MXM3_286",
+ "MXM3_239",
+ "MXM3_35",
+ "MXM3_205",
+ "MXM3_203",
+ "MXM3_201",
+ "MXM3_116",
+ "MXM3_114",
+ "MXM3_262",
+ "MXM3_274",
+ "MXM3_124",
+ "MXM3_110",
+ "MXM3_120",
+ "MXM3_263",
+ "MXM3_265",
+ "",
+ "MXM3_135",
+ "MXM3_261",
+ "MXM3_259";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "MXM3_194",
+ "MXM3_136",
+ "MXM3_134",
+ "MXM3_140",
+ "MXM3_138",
+ "",
+ "MXM3_220",
+ "",
+ "",
+ "MXM3_18",
+ "MXM3_16",
+ "",
+ "",
+ "MXM3_214",
+ "MXM3_216",
+ "MXM3_164";
+};
+
+&gpio5 {
+ gpio-line-names = "MXM3_159",
+ "",
+ "",
+ "",
+ "MXM3_257",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "MXM3_200",
+ "MXM3_196",
+ "MXM3_204",
+ "MXM3_202",
+ "",
+ "",
+ "",
+ "",
+ "MXM3_191",
+ "MXM3_197",
+ "MXM3_77",
+ "MXM3_195",
+ "MXM3_221",
+ "MXM3_225",
+ "MXM3_223",
+ "MXM3_227",
+ "MXM3_209",
+ "MXM3_211",
+ "MXM3_118",
+ "MXM3_112",
+ "MXM3_187",
+ "MXM3_185";
+};
+
+&gpio6 {
+ gpio-line-names = "MXM3_183",
+ "MXM3_181",
+ "MXM3_179",
+ "MXM3_177",
+ "MXM3_175",
+ "MXM3_173",
+ "MXM3_255",
+ "MXM3_83",
+ "MXM3_91",
+ "MXM3_13/GPIO6",
+ "MXM3_11/GPIO5",
+ "MXM3_79",
+ "",
+ "",
+ "MXM3_190",
+ "MXM3_193",
+ "MXM3_89";
+};
+
+&gpio7 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "MXM3_99",
+ "MXM3_85",
+ "MXM3_217",
+ "MXM3_215";
+};
+
+&gpr {
+ ipu1_csi0_mux {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ port@1 {
+ reg = <1>;
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ remote-endpoint = <&adv7280_to_ipu1_csi0_mux>;
+ };
+ };
+ };
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
@@ -177,6 +484,16 @@
scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
+
+ atmel_mxt_ts: touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ /* These GPIOs are muxed with the iomuxc node */
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */
+ reg = <0x4a>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */
+ status = "disabled";
+ };
};
/*
@@ -192,101 +509,105 @@
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
- pmic: pfuze100@8 {
+ pmic: pmic@8 {
compatible = "fsl,pfuze100";
+ fsl,pmic-stby-poweroff;
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1875000>;
+ regulator-min-microvolt = <300000>;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1875000>;
+ regulator-min-microvolt = <300000>;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <400000>;
};
swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5150000>;
+ regulator-min-microvolt = <5000000>;
};
snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <1000000>;
};
vref_reg: vrefddr {
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
};
vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1550000>;
+ regulator-min-microvolt = <800000>;
};
vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1550000>;
+ regulator-min-microvolt = <800000>;
};
vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
};
vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
};
};
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
- reg = <0x0a>;
+ #sound-dai-cells = <0>;
clocks = <&clks IMX6QDL_CLK_CKO>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
+ reg = <0x0a>;
VDDA-supply = <&reg_module_3v3_audio>;
VDDIO-supply = <&reg_module_3v3>;
VDDD-supply = <&vgen4_reg>;
@@ -295,15 +616,15 @@
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touch_int>;
- reg = <0x41>;
+ blocks = <0x5>;
+ id = <0>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio4>;
interrupt-controller;
- id = <0>;
- blocks = <0x5>;
+ interrupt-parent = <&gpio4>;
irq-trigger = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_int>;
+ reg = <0x41>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 12-bit ADC */
@@ -313,7 +634,7 @@
/* ADC conversion time: 80 clocks */
st,sample-time = <4>;
- stmpe_touchscreen: stmpe-touchscreen {
+ stmpe_ts: stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
st,ave-ctrl = <3>;
@@ -328,13 +649,14 @@
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
+ status = "disabled";
};
- stmpe_adc: stmpe-adc {
+ stmpe_adc: stmpe_adc {
compatible = "st,stmpe-adc";
+ #io-channel-cells = <1>;
/* forbid to use ADC channels 3-0 (touch) */
st,norequest-mask = <0x0F>;
- #io-channel-cells = <1>;
};
};
};
@@ -351,6 +673,90 @@
scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
+
+ adv_7280: adv7280@21 {
+ compatible = "adi,adv7280";
+ adv,force-bt656-4;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+ reg = <0x21>;
+ status = "disabled";
+
+ port {
+ adv7280_to_ipu1_csi0_mux: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ };
+ };
+ };
+
+ ov5640_csi_cam: ov5640_mipi@3c {
+ compatible = "ovti,ov5640";
+ AVDD-supply = <&reg_ov5640_2v8_a_vdd>;
+ DOVDD-supply = <&reg_ov5640_1v8_d_o_vdd>;
+ DVDD-supply = <&reg_ov5640_1v8_d_o_vdd>;
+ clock-names = "xclk";
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cam_mclk>;
+ /* These GPIOs are muxed with the iomuxc node */
+ powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ reg = <0x3c>;
+ reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
+ port {
+ ov5640_to_mipi_csi2: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&mipi_csi_from_ov5640>;
+ };
+ };
+ };
+};
+
+&ipu1_di1_disp1 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+ lvds-channel@0 {
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+
+ port@4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ };
+ };
+ };
+};
+
+&mipi_csi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi_from_ov5640: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&ov5640_to_mipi_csi2>;
+ };
+ };
};
&pwm1 {
@@ -372,7 +778,6 @@
};
&pwm4 {
- #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "disabled";
@@ -389,72 +794,72 @@
};
&uart1 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
- fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
&uart2 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_dte>;
- fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
&uart4 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_dte>;
- fsl,dte-mode;
status = "disabled";
};
&uart5 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5_dte>;
- fsl,dte-mode;
status = "disabled";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
- disable-over-current;
status = "disabled";
};
/* MMC1 */
&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
- vqmmc-supply = <&reg_module_3v3>;
bus-width = <8>;
+ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
disable-wp;
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
+ vqmmc-supply = <&reg_module_3v3>;
status = "disabled";
};
/* SD1 */
&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- vqmmc-supply = <&reg_module_3v3>;
bus-width = <4>;
disable-wp;
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ vqmmc-supply = <&reg_module_3v3>;
status = "disabled";
};
/* eMMC */
&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- vqmmc-supply = <&reg_module_3v3>;
bus-width = <8>;
no-1-8-v;
non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vqmmc-supply = <&reg_module_3v3>;
status = "okay";
};
@@ -463,49 +868,57 @@
};
&iomuxc {
- pinctrl_apalis_gpio1: gpio2io04grp {
+ /* Mux the Apalis GPIOs */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
+ >;
+
+ pinctrl_apalis_gpio1: apalisgpio1grp {
fsl,pins = <
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
>;
};
- pinctrl_apalis_gpio2: gpio2io05grp {
+ pinctrl_apalis_gpio2: apalisgpio2grp {
fsl,pins = <
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
>;
};
- pinctrl_apalis_gpio3: gpio2io06grp {
+ pinctrl_apalis_gpio3: apalisgpio3grp {
fsl,pins = <
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
>;
};
- pinctrl_apalis_gpio4: gpio2io07grp {
+ pinctrl_apalis_gpio4: apalisgpio4grp {
fsl,pins = <
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
>;
};
- pinctrl_apalis_gpio5: gpio6io10grp {
+ pinctrl_apalis_gpio5: apalisgpio5grp {
fsl,pins = <
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
>;
};
- pinctrl_apalis_gpio6: gpio6io09grp {
+ pinctrl_apalis_gpio6: apalisgpio6grp {
fsl,pins = <
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
>;
};
- pinctrl_apalis_gpio7: gpio1io02grp {
+ pinctrl_apalis_gpio7: apalisgpio7grp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
>;
};
- pinctrl_apalis_gpio8: gpio1io06grp {
+ pinctrl_apalis_gpio8: apalisgpio8grp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
>;
@@ -517,8 +930,6 @@
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
- /* SGTL5000 sys_mclk */
- MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
>;
};
@@ -600,7 +1011,7 @@
>;
};
- pinctrl_gpio_bl_on: gpioblon {
+ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
>;
@@ -745,7 +1156,7 @@
>;
};
- pinctrl_mmc_cd: gpiommccdgrp {
+ pinctrl_mmc_cd: mmccdgrp {
fsl,pins = <
/* MMC1 CD */
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
@@ -776,41 +1187,47 @@
>;
};
- pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+ pinctrl_regulator_usbh_pwr: regusbhpwrgrp {
fsl,pins = <
/* USBH_EN */
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
>;
};
- pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
+ pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp {
fsl,pins = <
/* USBH_HUB_EN */
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
>;
};
- pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
+ pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp {
fsl,pins = <
/* USBO1 power en */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
>;
};
- pinctrl_reset_moci: gpioresetmocigrp {
+ pinctrl_reset_moci: resetmocigrp {
fsl,pins = <
/* RESET_MOCI control */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
>;
};
- pinctrl_sd_cd: gpiosdcdgrp {
+ pinctrl_sd_cd: sdcdgrp {
fsl,pins = <
/* SD1 CD */
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
>;
};
+ pinctrl_sgtl5000: sgtl5000grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
@@ -818,13 +1235,22 @@
>;
};
- pinctrl_touch_int: gpiotouchintgrp {
+ pinctrl_touch_int: touchintgrp {
fsl,pins = <
/* STMPE811 interrupt */
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
>;
};
+ /* Additional DTR, DSR, DCD */
+ pinctrl_uart1_ctrl: uart1ctrlgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+ MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+ >;
+ };
+
pinctrl_uart1_dce: uart1dcegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
@@ -842,15 +1268,6 @@
>;
};
- /* Additional DTR, DSR, DCD */
- pinctrl_uart1_ctrl: uart1ctrlgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
- MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
- MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
- >;
- };
-
pinctrl_uart2_dce: uart2dcegrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
@@ -904,7 +1321,7 @@
>;
};
- pinctrl_usdhc1_4bit: usdhc1grp_4bit {
+ pinctrl_usdhc1_4bit: usdhc1-4bitgrp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
@@ -915,7 +1332,7 @@
>;
};
- pinctrl_usdhc1_8bit: usdhc1grp_8bit {
+ pinctrl_usdhc1_8bit: usdhc1-8bitgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index e21f6ac864e5..baa197c90060 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -96,7 +96,7 @@
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
index 563bf9d44fe0..6b64b2fc3995 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
@@ -131,7 +131,7 @@
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
- flash: m25p80@1 {
+ flash: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor";
@@ -154,112 +154,112 @@
regulators {
bcore1 {
regulator-name = "bcore1";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
bcore2 {
regulator-name = "bcore2";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
bpro {
regulator-name = "bpro";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
bperi {
regulator-name = "bperi";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
bmem {
regulator-name = "bmem";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo2 {
regulator-name = "ldo2";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1800000>;
};
ldo3 {
regulator-name = "ldo3";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo4 {
regulator-name = "ldo4";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo5 {
regulator-name = "ldo5";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo6 {
regulator-name = "ldo6";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo7 {
regulator-name = "ldo7";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo8 {
regulator-name = "ldo8";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo9 {
regulator-name = "ldo9";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo10 {
regulator-name = "ldo10";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
ldo11 {
regulator-name = "ldo11";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
};
bio {
regulator-name = "bio";
- regulator-always-on = <1>;
+ regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi
deleted file mode 100644
index 7672fbfc29be..000000000000
--- a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright 2020 Toradex
- */
-
-&iomuxc {
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
- >;
- };
-};
-
-/* Colibri MMC */
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
- vmmc-supply = <&reg_module_3v3>;
- vqmmc-supply = <&vgen3_reg>;
- wakeup-source;
- keep-power-in-suspend;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
-};
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 4e2a309c93fa..570995707504 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "Toradex Colibri iMX6DL/S Module";
@@ -13,11 +14,84 @@
backlight: backlight {
compatible = "pwm-backlight";
+ brightness-levels = <0 45 63 88 119 158 203 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
- pwms = <&pwm3 0 5000000>;
- enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
+ power-supply = <&reg_module_3v3>;
+ pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>;
+ status = "disabled";
+ };
+
+ extcon_usbc_det: usbc-det {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbc_det>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-wakeup {
+ debounce-interval = <10>;
+ gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ lcd_display: disp0 {
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "bgr666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ /* Will be filled by the bootloader */
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0>;
+ };
+
+ panel_dpi: panel-dpi {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
status = "disabled";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
};
reg_module_3v3: regulator-module-3v3 {
@@ -38,36 +112,36 @@
reg_usb_host_vbus: regulator-usb-host-vbus {
compatible = "regulator-fixed";
+ gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
- regulator-name = "usb_host_vbus";
- regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_host_vbus";
status = "disabled";
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
- model = "imx6dl-colibri-sgtl5000";
- ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HP_OUT",
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias";
+ model = "imx6dl-colibri-sgtl5000";
mux-int-port = <1>;
mux-ext-port = <5>;
+ ssi-controller = <&ssi1>;
};
/* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
sound_spdif: sound-spdif {
compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
spdif-out;
+ model = "imx-spdif";
status = "disabled";
};
};
@@ -92,6 +166,10 @@
status = "disabled";
};
+&clks {
+ fsl,pmic-stby-poweroff;
+};
+
/* Colibri SSP */
&ecspi4 {
cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
@@ -101,10 +179,10 @@
};
&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
status = "okay";
mdio {
@@ -118,6 +196,224 @@
};
};
+&gpio1 {
+ gpio-line-names = "",
+ "SODIMM_67",
+ "SODIMM_180",
+ "SODIMM_196",
+ "SODIMM_174",
+ "SODIMM_176",
+ "SODIMM_194",
+ "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_28",
+ "SODIMM_93",
+ "SODIMM_69",
+ "SODIMM_99",
+ "SODIMM_130",
+ "SODIMM_106",
+ "SODIMM_98",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_190",
+ "SODIMM_51",
+ "SODIMM_47",
+ "SODIMM_53",
+ "",
+ "SODIMM_22";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_132",
+ "SODIMM_134",
+ "SODIMM_135",
+ "SODIMM_133",
+ "SODIMM_102",
+ "SODIMM_43",
+ "SODIMM_127",
+ "SODIMM_37",
+ "SODIMM_104",
+ "SODIMM_59",
+ "SODIMM_30",
+ "SODIMM_100",
+ "SODIMM_38",
+ "SODIMM_34",
+ "SODIMM_32",
+ "SODIMM_36",
+ "SODIMM_59",
+ "SODIMM_67",
+ "SODIMM_97",
+ "SODIMM_79",
+ "SODIMM_103",
+ "SODIMM_101",
+ "SODIMM_45",
+ "SODIMM_105",
+ "SODIMM_107",
+ "SODIMM_91",
+ "SODIMM_89",
+ "SODIMM_150",
+ "SODIMM_126",
+ "SODIMM_128",
+ "",
+ "SODIMM_94";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_111",
+ "SODIMM_113",
+ "SODIMM_115",
+ "SODIMM_117",
+ "SODIMM_119",
+ "SODIMM_121",
+ "SODIMM_123",
+ "SODIMM_125",
+ "SODIMM_110",
+ "SODIMM_112",
+ "SODIMM_114",
+ "SODIMM_116",
+ "SODIMM_118",
+ "SODIMM_120",
+ "SODIMM_122",
+ "SODIMM_124",
+ "",
+ "SODIMM_96",
+ "SODIMM_77",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_88",
+ "SODIMM_90",
+ "SODIMM_31",
+ "SODIMM_23",
+ "SODIMM_29",
+ "SODIMM_71",
+ "SODIMM_73",
+ "SODIMM_92",
+ "SODIMM_81",
+ "SODIMM_131",
+ "SODIMM_129";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_168",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_184",
+ "SODIMM_186",
+ "HDMI_15",
+ "HDMI_16",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "SODIMM_24",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_95",
+ "",
+ "SODIMM_86",
+ "",
+ "SODIMM_65",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_136",
+ "SODIMM_138",
+ "SODIMM_140",
+ "SODIMM_142",
+ "SODIMM_144",
+ "SODIMM_146",
+ "SODIMM_172",
+ "SODIMM_170",
+ "SODIMM_149",
+ "SODIMM_151",
+ "SODIMM_153",
+ "SODIMM_155",
+ "SODIMM_157",
+ "SODIMM_159",
+ "SODIMM_161",
+ "SODIMM_163",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_165",
+ "SODIMM_167";
+};
+
+&gpio6 {
+ gpio-line-names = "SODIMM_169",
+ "SODIMM_171",
+ "SODIMM_173",
+ "SODIMM_175",
+ "SODIMM_177",
+ "SODIMM_179",
+ "SODIMM_85",
+ "SODIMM_166",
+ "SODIMM_160",
+ "SODIMM_162",
+ "SODIMM_158",
+ "SODIMM_164",
+ "",
+ "",
+ "SODIMM_156",
+ "SODIMM_75",
+ "SODIMM_154",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_152";
+};
+
+&gpio7 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_19",
+ "SODIMM_21",
+ "",
+ "SODIMM_137";
+};
+
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_ddc>;
@@ -132,65 +428,66 @@
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-0 = <&pinctrl_i2c2_gpio>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
- pmic: pfuze100@8 {
+ pmic: pmic@8 {
compatible = "fsl,pfuze100";
+ fsl,pmic-stby-poweroff;
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1875000>;
+ regulator-min-microvolt = <300000>;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1875000>;
+ regulator-min-microvolt = <300000>;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <400000>;
};
swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5150000>;
+ regulator-min-microvolt = <5000000>;
};
snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <1000000>;
};
vref_reg: vrefddr {
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
};
/* vgen1: unused */
vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1550000>;
+ regulator-min-microvolt = <800000>;
};
/*
@@ -198,57 +495,60 @@
* the i.MX 6 NVCC_SD1.
*/
vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
};
vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
};
};
};
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
- reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
+ lrclk-strength = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgtl5000>;
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <&reg_module_3v3_audio>;
VDDIO-supply = <&reg_module_3v3>;
VDDD-supply = <&vgen4_reg>;
- lrclk-strength = <3>;
};
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touch_int>;
- reg = <0x41>;
+ blocks = <0x5>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio6>;
interrupt-controller;
id = <0>;
- blocks = <0x5>;
irq-trigger = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_int>;
+ reg = <0x41>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 12-bit ADC */
@@ -258,7 +558,7 @@
/* ADC converstion time: 80 clocks */
st,sample-time = <4>;
- stmpe_touchscreen {
+ stmpe_ts: stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
st,ave-ctrl = <3>;
@@ -273,9 +573,10 @@
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
+ status = "disabled";
};
- stmpe_adc {
+ stmpe_adc: stmpe_adc {
compatible = "st,stmpe-adc";
/* forbid to use ADC channels 3-0 (touch) */
st,norequest-mask = <0x0F>;
@@ -294,6 +595,21 @@
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
+
+ atmel_mxt_ts: touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ interrupt-parent = <&gpio2>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_atmel_conn>;
+ reg = <0x4a>;
+ reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */
+ status = "disabled";
+ };
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
};
/* Colibri PWM<B> */
@@ -312,7 +628,6 @@
/* Colibri PWM<A> */
&pwm3 {
- #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
@@ -338,56 +653,66 @@
/* Colibri UART_A */
&uart1 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
- fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
/* Colibri UART_B */
&uart2 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_dte>;
- fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
/* Colibri UART_C */
&uart3 {
+ fsl,dte-mode;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_dte>;
- fsl,dte-mode;
status = "disabled";
};
+/* Colibri USBH */
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+};
+
+/* Colibri USBC */
&usbotg {
- disable-over-current;
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ extcon = <0>, <&extcon_usbc_det>;
status = "disabled";
};
/* Colibri MMC */
&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
- disable-wp;
- vqmmc-supply = <&reg_module_3v3>;
bus-width = <4>;
no-1-8-v;
+ disable-wp;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>;
+ vmmc-supply = <&reg_module_3v3>;
+ vqmmc-supply = <&vgen3_reg>;
status = "disabled";
};
/* eMMC */
&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- vqmmc-supply = <&reg_module_3v3>;
bus-width = <8>;
no-1-8-v;
non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vqmmc-supply = <&reg_module_3v3>;
status = "okay";
};
@@ -405,14 +730,34 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_oc_1>;
+ /* Atmel MXT touchsceen + Capacitive Touch Adapter */
+ /* NOTE: This pin group conflicts with pin groups
+ * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously.
+ */
+ pinctrl_atmel_adap: atmeladaptergrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */
+ >;
+ };
+
+ /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
+ /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and
+ * pinctrl_weim_cs2. Don't use them simultaneously.
+ */
+ pinctrl_atmel_conn: atmelconnectorgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */
+ >;
+ };
+
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
- /* SGTL5000 sys_mclk */
- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
>;
};
@@ -423,28 +768,52 @@
>;
};
+ /* CSI pins used as GPIOs */
+ pinctrl_csi_gpio_1: csigpio1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
+ MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_csi_gpio_2: csigpio2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0
+ >;
+ };
+
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
+ /* SPI CS */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
- /* SPI CS */
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
>;
};
@@ -462,13 +831,32 @@
>;
};
- pinctrl_gpio_bl_on: gpioblon {
+ pinctrl_gpio_1: gpio1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ >;
+ };
+ pinctrl_gpio_2: gpio2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
>;
};
- pinctrl_gpio_keys: gpiokeys {
+ pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
>;
@@ -483,15 +871,15 @@
pinctrl_i2c2: i2c2grp {
fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
>;
};
- pinctrl_i2c2_gpio: i2c2grp {
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
>;
};
@@ -523,8 +911,8 @@
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
/* Disable PWM pins on camera interface */
- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
+ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
>;
};
@@ -555,19 +943,34 @@
>;
};
- pinctrl_mic_gnd: gpiomicgnd {
+ pinctrl_lvds_transceiver: lvdstxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */
+ >;
+ };
+
+ pinctrl_mic_gnd: micgndgrp {
fsl,pins = <
/* Controls Mic GND, PU or '1' pull Mic GND to GND */
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
>;
};
- pinctrl_mmc_cd: gpiommccd {
+ pinctrl_mmc_cd: mmccdgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
>;
};
+ pinctrl_mmc_cd_sleep: mmccdslpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
@@ -576,15 +979,15 @@
pinctrl_pwm2: pwm2grp {
fsl,pins = <
- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
@@ -596,15 +999,15 @@
pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
fsl,pins = <
- /* USBH_EN */
+ /* SODIMM 129 / USBH_PEN */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
>;
};
- pinctrl_usbh_oc_1: usbhoc1grp {
+ pinctrl_sgtl5000: sgtl5000grp {
fsl,pins = <
- /* USBH_OC */
- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ /* SGTL5000 sys_mclk */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
>;
};
@@ -650,9 +1053,9 @@
pinctrl_uart2_dte: uart2dtegrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
>;
};
@@ -665,22 +1068,29 @@
pinctrl_usbc_det: usbcdetgrp {
fsl,pins = <
- /* USBC_DET */
+ /* SODIMM 137 / USBC_DET */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
- /* USBC_DET_EN */
- MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
/* USBC_DET_OVERWRITE */
MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
+ /* USBC_DET_EN */
+ MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
>;
};
- pinctrl_usbc_id_1: usbc_id-1 {
+ pinctrl_usbc_id_1: usbcid1grp {
fsl,pins = <
/* USBC_ID */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
>;
};
+ pinctrl_usbh_oc_1: usbhoc1grp {
+ fsl,pins = <
+ /* USBH_OC */
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
@@ -692,6 +1102,40 @@
>;
};
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
+ >;
+ };
+
+ /* avoid backfeeding with removed card power */
+ pinctrl_usdhc1_sleep: usdhc1sleepgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@@ -730,135 +1174,136 @@
>;
};
- pinctrl_weim_sram: weimsramgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
- /* Data */
- MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
- MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
- MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
- MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
- MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
- MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
- MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
- MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
- MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
- MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
- MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
- MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
- MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
- MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
- MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
- MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
- /* Address */
- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
- >;
- };
-
- pinctrl_weim_rdnwr: weimrdnwr {
- fsl,pins = <
- MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
- MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
- >;
- };
-
- pinctrl_weim_npwe: weimnpwe {
- fsl,pins = <
- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
- MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
- >;
- };
-
/* ADDRESS[16:18] [25] used as GPIO */
- pinctrl_weim_gpio_1: weimgpio-1 {
+ pinctrl_weim_gpio_1: weimgpio1grp {
fsl,pins = <
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
/* ADDRESS[19:24] used as GPIO */
- pinctrl_weim_gpio_2: weimgpio-2 {
+ pinctrl_weim_gpio_2: weimgpio2grp {
fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
/* DATA[16:31] used as GPIO */
- pinctrl_weim_gpio_3: weimgpio-3 {
+ pinctrl_weim_gpio_3: weimgpio3grp {
fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
>;
};
/* DQM[0:3] used as GPIO */
- pinctrl_weim_gpio_4: weimgpio-4 {
+ pinctrl_weim_gpio_4: weimgpio4grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
- MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
>;
};
/* RDY used as GPIO */
- pinctrl_weim_gpio_5: weimgpio-5 {
+ pinctrl_weim_gpio_5: weimgpio5grp {
fsl,pins = <
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
>;
};
/* ADDRESS[16] DATA[30] used as GPIO */
- pinctrl_weim_gpio_6: weimgpio-6 {
+ pinctrl_weim_gpio_6: weimgpio6grp {
fsl,pins = <
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_weim_npwe: weimnpwegrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
+ >;
+ };
+
+ pinctrl_weim_sram: weimsramgrp {
+ fsl,pins = <
+ /* Data */
+ MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
+ /* Address */
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ /* Ctrl */
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ >;
+ };
+
+ pinctrl_weim_rdnwr: weimrdnwrgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
+ MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
>;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
index 648f5fcb72e6..2c1d6f28e695 100644
--- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -35,7 +35,7 @@
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf040b", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi
index fe72650295a5..6248b126b557 100644
--- a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi
@@ -332,37 +332,4 @@
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
>;
};
-
- pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
- >;
- };
};
diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi
index 5befbe13d1a3..eaa87b333164 100644
--- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi
@@ -667,6 +667,39 @@
>;
};
+ pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
+ >;
+ };
+
pinctrl_pcie: pcie-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
index 7228b894a763..ee2dd75cead6 100644
--- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
@@ -46,14 +46,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_som_leds>;
- green {
+ led-green {
label = "som:green";
gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "on";
};
- red {
+ led-red {
label = "som:red";
gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 069c27fab432..e75e1a5364b8 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -71,14 +71,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index b1df2beb2832..47d9a8d08197 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -80,20 +80,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
@@ -137,6 +137,16 @@
regulator-always-on;
};
+ reg_can1_stby: regulator-can1-stby {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_can1>;
+ regulator-name = "can1_stby";
+ gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
@@ -170,6 +180,7 @@
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
@@ -612,7 +623,6 @@
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
>;
};
@@ -702,6 +712,12 @@
>;
};
+ pinctrl_reg_can1: regcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index a0710d562766..fb1d29abe099 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -80,20 +80,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
@@ -129,6 +129,16 @@
regulator-always-on;
};
+ reg_can1_stby: regulator-can1-stby {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_can1>;
+ regulator-name = "can1_stby";
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
@@ -170,6 +180,7 @@
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
@@ -600,7 +611,6 @@
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
@@ -691,6 +701,12 @@
>;
};
+ pinctrl_reg_can1: regcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index cda48bf2f168..4e20cb97058e 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -81,20 +81,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
@@ -137,6 +137,16 @@
regulator-always-on;
};
+ reg_can1_stby: regulator-can1-stby {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_can1>;
+ regulator-name = "can1_stby";
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
reg_usb_h1_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
@@ -200,6 +210,7 @@
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
@@ -687,7 +698,6 @@
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
@@ -786,6 +796,12 @@
>;
};
+ pinctrl_reg_can1: regcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 435dec6338fe..0fa4b8eeddee 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -115,7 +115,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
default-state = "on";
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index 2e61102ae694..77ae611b817a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -72,20 +72,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
index 4662408b225a..7f16c602cc07 100644
--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
@@ -113,14 +113,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
index 4bc4371e6bae..46cf4080fec3 100644
--- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
@@ -139,20 +139,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
@@ -632,7 +632,6 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
index 1fdb7ba630f1..a74cde050158 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
@@ -123,7 +123,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
index 612b6e068e28..9fc79af2bc9a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
@@ -120,20 +120,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
index fcd3bdfd6182..955a51226eda 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
@@ -71,14 +71,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
index 68e5ab2e27e2..218d6e667ed2 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
@@ -29,7 +29,7 @@
user-pb {
label = "user_pb";
- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
@@ -74,20 +74,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
index 0415bcb41640..40e235e315cc 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
@@ -72,20 +72,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
- led2: user3 {
+ led2: led-user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
index 8e23cec7149e..82f47c295b08 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
@@ -26,7 +26,7 @@
user-pb {
label = "user_pb";
- gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
@@ -71,14 +71,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- led0: user1 {
+ led0: led-user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user2 {
+ led1: led-user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index b167b33bd108..85aeebc9485d 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -51,16 +51,6 @@
vin-supply = <&reg_3p3v_s5>;
};
- reg_3p3v_s0: regulator-3p3v-s0 {
- compatible = "regulator-fixed";
- regulator-name = "V_3V3_S0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&reg_3p3v_s5>;
- };
-
reg_3p3v_s5: regulator-3p3v-s5 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_S5";
@@ -258,8 +248,8 @@
status = "okay";
/* default boot source: workaround #1 for errata ERR006282 */
- smarc_flash: spi-flash@0 {
- compatible = "winbond,w25q16dw", "jedec,spi-nor";
+ smarc_flash: flash@0 {
+ compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
@@ -270,7 +260,23 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ phy-handle = <&ethphy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1000>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
};
&i2c_intern {
@@ -397,7 +403,7 @@
/* HDMI_CTRL */
&i2c2 {
- clock-frequency = <375000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi
index f4dca20669d6..78555a618851 100644
--- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi
@@ -244,7 +244,6 @@
status = "okay";
};
-
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index ac34709e9741..6d4eab1942b9 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -85,31 +85,31 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
- j14-pin1 {
+ led-j14-pin1 {
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
retain-state-suspended;
default-state = "off";
};
- j14-pin3 {
+ led-j14-pin3 {
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
retain-state-suspended;
default-state = "off";
};
- j14-pins8-9 {
+ led-j14-pins8-9 {
gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
retain-state-suspended;
default-state = "off";
};
- j46-pin2 {
+ led-j46-pin2 {
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
retain-state-suspended;
default-state = "off";
};
- j46-pin3 {
+ led-j46-pin3 {
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
retain-state-suspended;
default-state = "off";
@@ -179,7 +179,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
@@ -192,6 +192,7 @@
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index c96f4d7e1e0d..81a9a302aec1 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -181,13 +181,13 @@
leds {
compatible = "gpio-leds";
- speaker-enable {
+ led-speaker-enable {
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
retain-state-suspended;
default-state = "off";
};
- ttymxc4-rs232 {
+ led-ttymxc4-rs232 {
gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
retain-state-suspended;
default-state = "on";
@@ -321,7 +321,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
@@ -334,6 +334,7 @@
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index 92d09a3ebe0e..000e9dc97b1a 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -252,7 +252,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
@@ -263,6 +263,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 49da30d7510c..731759bdd7f5 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -237,7 +237,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
@@ -267,6 +267,7 @@
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
index 393475cb0f4d..0020dbb1722c 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi
@@ -64,7 +64,7 @@
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_NONE>;
status = "disabled";
- };
+ };
};
&ipu1_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
index 120d6e997a4c..1a599c294ab8 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
@@ -25,17 +25,17 @@
pinctrl-0 = <&pinctrl_gpioleds>;
status = "disabled";
- red {
+ led-red {
label = "phyboard-mira:red";
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-green {
label = "phyboard-mira:green";
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
};
- blue {
+ led-blue {
label = "phyboard-mira:blue";
gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 1f2ba6f6254e..80adb2a02cc9 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -47,12 +47,12 @@
pinctrl-0 = <&pinctrl_leds>;
compatible = "gpio-leds";
- green {
+ led_green: led-green {
label = "phyflex:green";
gpios = <&gpio1 30 0>;
};
- red {
+ led_red: led-red {
label = "phyflex:red";
gpios = <&gpio2 31 0>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/imx6qdl-pico.dtsi
index f7a56d6b160c..c39a9ebdaba1 100644
--- a/arch/arm/boot/dts/imx6qdl-pico.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-pico.dtsi
@@ -233,7 +233,6 @@
pinctrl-0 = <&pinctrl_ov5645>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
- clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&reg_1p8v>;
vdda-supply = <&reg_2p8v>;
diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
index 19578f660b09..f0db0d4471f4 100644
--- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
@@ -94,6 +94,9 @@
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
non-removable;
+ no-1-8-v;
+ no-sd;
+ no-sdio;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index de514eb5aa99..f804ff95a6ad 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -55,7 +55,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- led0: usr {
+ led0: led-usr {
label = "usr";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
default-state = "off";
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 5e58740d40c5..f79caa36f3d2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -21,7 +21,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- user {
+ led-user {
label = "debug";
gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
};
@@ -272,7 +272,7 @@
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
@@ -295,6 +295,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
@@ -451,8 +452,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_egalax_int>;
interrupt-parent = <&gpio2>;
- interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
- wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index eb9a0b104f1c..12573e1f917c 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -1,43 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/imx6qdl-clock.h>
@@ -49,6 +14,11 @@
stdout-path = &uart2;
};
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc4;
+ };
+
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
@@ -313,7 +283,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 0c0105468a2f..53b080c97f2d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -130,7 +130,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- red {
+ led-red {
gpios = <&gpio1 2 0>;
default-state = "on";
};
@@ -197,7 +197,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
@@ -311,8 +311,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
interrupt-parent = <&gpio6>;
- interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
- wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
};
ov5640: camera@3c {
@@ -450,8 +450,8 @@
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio6>;
- interrupts = <7 2>;
- wakeup-gpios = <&gpio6 7 0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
};
magnetometer@e {
diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi
index 69ae430a53bd..b81799d7076a 100644
--- a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi
@@ -2,35 +2,60 @@
//
// Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>
+/ {
+ touchscreen {
+ compatible = "resistive-adc-touch";
+ io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>;
+ io-channel-names = "y", "z1", "z2", "x";
+ touchscreen-min-pressure = <65000>;
+ touchscreen-inverted-y;
+ touchscreen-swapped-x-y;
+ touchscreen-x-plate-ohms = <300>;
+ touchscreen-y-plate-ohms = <800>;
+ };
+};
+
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
status = "okay";
- touchscreen@0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touch>;
- compatible = "ti,tsc2046";
+ adc_ts: adc@0 {
+ compatible = "ti,tsc2046e-adc";
reg = <0>;
+ pinctrl-0 = <&pinctrl_touch>;
+ pinctrl-names ="default";
spi-max-frequency = <1000000>;
interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>;
- vcc-supply = <&reg_3v3>;
- pendown-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
- ti,x-plate-ohms = /bits/ 16 <850>;
- ti,y-plate-ohms = /bits/ 16 <295>;
- ti,pressure-min = /bits/ 16 <2>;
- ti,pressure-max = /bits/ 16 <1500>;
- ti,vref-mv = /bits/ 16 <3300>;
- ti,settle-delay-usec = /bits/ 16 <15>;
- ti,vref-delay-usecs = /bits/ 16 <0>;
- ti,penirq-recheck-delay-usecs = /bits/ 16 <100>;
- ti,debounce-max = /bits/ 16 <100>;
- ti,debounce-tol = /bits/ 16 <(~0)>;
- ti,debounce-rep = /bits/ 16 <4>;
- touchscreen-swapped-x-y;
- touchscreen-inverted-y;
- wakeup-source;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <1>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+
+ channel@4 {
+ reg = <4>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
index 77a91a97e6cf..2731faede1cb 100644
--- a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
@@ -105,6 +105,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_3v3: regulator-3v3 {
@@ -149,6 +150,16 @@
gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
};
+ reg_tft_vcom: regulator-tft-vcom {
+ compatible = "pwm-regulator";
+ pwms = <&pwm3 0 20000 0>;
+ regulator-name = "tft_vcom";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ voltage-table = <3600000 26>;
+ };
+
reg_vcc_mmc: regulator-vcc-mmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -222,13 +233,16 @@
};
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-mode = "rmii";
phy-supply = <&reg_3v3>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
index f86efd0ccc40..ce543e325cd3 100644
--- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
@@ -83,6 +83,16 @@
qca,clk-out-frequency = <125000000>;
qca,smarteee-tw-us-1g = <24>;
};
+
+ /*
+ * ADIN1300 (som rev 1.9 or later) is always at address 1. It
+ * will be enabled automatically by U-Boot if detected.
+ */
+ ethernet-phy@1 {
+ reg = <1>;
+ adi,phy-output-clock = "125mhz-free-running";
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi
index 7dc3f0005b0f..aff46f3040c1 100644
--- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
&fec {
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
@@ -35,6 +36,7 @@
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
+ vcc-supply = <&reg_3p3v>;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi
index dd0925766440..a3f6543c3aaa 100644
--- a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi
@@ -29,5 +29,6 @@
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
+ vcc-supply = <&reg_3p3v>;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
index fded07f370b3..1e0a041e9f60 100644
--- a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
@@ -73,13 +73,13 @@
default-state = "off";
};
- en-usb-5v {
+ en-usb-5v-led {
label = "en-usb-5v";
gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- sel_dc_usb {
+ sel-dc-usb-led {
label = "sel_dc_usb";
gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
@@ -192,6 +192,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
+ /delete-property/ interrupts;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
@@ -226,7 +227,7 @@
reg = <0x28>;
#gpio-cells = <2>;
gpio-controller;
- ngpio = <32>;
+ ngpios = <62>;
};
sgtl5000: codec@a {
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index bcc5bbcce769..a197bac95cba 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -92,7 +92,7 @@
leds {
compatible = "gpio-leds";
- user_led: user {
+ user_led: led-user {
label = "Heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_led>;
@@ -264,11 +264,6 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET_REF>,
- <&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp", "enet_out";
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <10>;
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index ccfa8e320be6..93a8123da27d 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -295,7 +295,7 @@
pinctrl-0 = <&pinctrl_usbh>;
vbus-supply = <&reg_usb_h1_vbus>;
clocks = <&clks IMX6QDL_CLK_CKO>;
- status = "okay";
+ status = "disabled";
};
&usbotg {
diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi
new file mode 100644
index 000000000000..f505f2704530
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 Protonic Holland
+ */
+
+/ {
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+ autorepeat;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ panel {
+ compatible = "kyo,tcg121xglp";
+ backlight = <&backlight_lcd>;
+ power-supply = <&reg_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&rgmii_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Microchip KSZ9031RNX PHY */
+ rgmii_phy: ethernet-phy@0 {
+ reg = <0>;
+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <300>;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
+ "CAM2_MIRROR", "", "", "SMBALERT",
+ "DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
+ "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
+ "SD1_DATA3", "ETH_MDIO", "",
+ "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
+ "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
+ "CAN2_SR", "CAN2_TX", "CAN2_RX",
+ "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL",
+ "HITCH_IN_OUT",
+ "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "",
+ "ISB_LED";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
+ "I2S_BITCLK", "I2S_DOUT",
+ "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
+ "YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
+ "ITU656_D6", "ITU656_D7", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2",
+ "RGMII_TD3",
+ "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1",
+ "RGMII_RD2", "RGMII_RD3", "", "";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
+ /* Phy reset */
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
+ >;
+ };
+
+ pinctrl_gpiokeys: gpiokeygrp {
+ fsl,pins = <
+ /* nON_SWITCH */
+ MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
index 1ac7e13249d2..c4e6cf0527ba 100644
--- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
@@ -16,18 +16,37 @@
stdout-path = &uart4;
};
- backlight: backlight {
+ backlight_lcd: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 16 64 255>;
num-interpolated-steps = <16>;
- default-brightness-level = <1>;
+ default-brightness-level = <48>;
power-supply = <&reg_3v3>;
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
};
+ backlight_led: backlight-led {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 5000000 0>;
+ brightness-levels = <0 16 64 255>;
+ num-interpolated-steps = <16>;
+ default-brightness-level = <48>;
+ power-supply = <&reg_3v3>;
+ };
+
+ /* only for backwards compatibility with old HW */
+ backlight_isb: backlight-isb {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 5000000 0>;
+ brightness-levels = <0 8 48 255>;
+ num-interpolated-steps = <5>;
+ default-brightness-level = <0>;
+ power-supply = <&reg_3v3>;
+ };
+
connector {
compatible = "composite-video-connector";
label = "Composite0";
@@ -61,54 +80,37 @@
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
};
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- power {
- label = "Power Button";
- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- wakeup-source;
- };
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
led-0 {
- label = "LED_DI0_DEBUG_0";
+ label = "debug0";
function = LED_FUNCTION_HEARTBEAT;
- gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-1 {
- label = "LED_DI0_DEBUG_1";
+ label = "debug1";
function = LED_FUNCTION_DISK;
- gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
};
led-2 {
- label = "POWER_LED";
+ label = "power_led";
function = LED_FUNCTION_POWER;
gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- };
-
- panel {
- compatible = "kyo,tcg121xglp";
- backlight = <&backlight>;
- power-supply = <&reg_3v3>;
- port {
- panel_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
+ led-3 {
+ label = "isb_led";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
};
};
@@ -135,18 +137,6 @@
enable-active-high;
};
- reg_wifi: regulator-wifi {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wifi_npd>;
- regulator-name = "wifi";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <70000>;
- };
-
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "prti6q-sgtl5000";
@@ -173,6 +163,14 @@
frame-master;
};
};
+
+ thermal-zones {
+ chassis-thermal {
+ polling-delay = <20000>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&tsens0>;
+ };
+ };
};
&audmux {
@@ -232,47 +230,13 @@
};
};
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii-id";
- phy-handle = <&rgmii_phy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Microchip KSZ9031RNX PHY */
- rgmii_phy: ethernet-phy@0 {
- reg = <0>;
- interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <300>;
- };
- };
-};
-
-&gpio1 {
- gpio-line-names =
- "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
- "CAM2_MIRROR", "", "", "SMBALERT",
- "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3",
- "SDIO_D2", "SDIO_D1", "SDIO_D0",
- "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
- "SD1_DATA3", "", "",
- "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "",
- "WL_IRQ", "ETH_MDC";
-};
-
&gpio2 {
gpio-line-names =
- "count0", "count1", "count2", "", "", "", "", "",
- "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
- "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
- "", "", "", "", "", "", "", "ON_SWITCH",
- "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", "";
+ "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "",
+ "", "LED_PWM", "", "", "",
+ "", "", "",
+ "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH",
+ "POWER_LED", "", "", "", "", "", "", "";
};
&gpio3 {
@@ -281,37 +245,8 @@
"", "", "", "", "", "", "", "",
"ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
"CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
- "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
- "CAN2_SR", "CAN2_TX", "CAN2_RX",
- "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "",
- "", "", "", "", "BL_EN", "BL_PWM", "", "";
-};
-
-&gpio5 {
- gpio-line-names =
- "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS",
- "PCIE_RESET", "", "", "", "", "", "", "",
- "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
- "I2S_BITCLK", "I2S_DOUT",
- "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
- "YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
-};
-
-&gpio6 {
- gpio-line-names =
- "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
- "ITU656_D6", "ITU656_D7", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2",
- "RGMII_TD3",
- "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1",
- "RGMII_RD2", "RGMII_RD3", "", "";
+ "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
+ "YACO_RESET";
};
&gpio7 {
@@ -406,9 +341,10 @@
reg = <0x51>;
};
- temperature-sensor@70 {
+ tsens0: temperature-sensor@70 {
compatible = "ti,tmp103";
reg = <0x70>;
+ #thermal-sensor-cells = <0>;
};
};
@@ -438,13 +374,21 @@
};
};
-&pcie {
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
-&pwm1 {
+&pwm2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
@@ -460,12 +404,6 @@
status = "okay";
};
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
@@ -513,26 +451,6 @@
status = "okay";
};
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- vmmc-supply = <&reg_wifi>;
- non-removable;
- cap-power-off-card;
- keep-power-in-suspend;
- no-1-8-v;
- no-mmc;
- no-sd;
- status = "okay";
-
- wifi {
- compatible = "ti,wl1271";
- interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
- ref-clock-frequency = "38400000";
- tcxo-clock-frequency = "19200000";
- };
-};
-
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
@@ -613,29 +531,6 @@
>;
};
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
- /* Phy reset */
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
- >;
- };
-
pinctrl_hog: hoggrp {
fsl,pins = <
/* ITU656_nRESET */
@@ -646,8 +541,6 @@
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0
/* CAM_nDETECT */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
- /* nON_SWITCH */
- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
/* ISB_IN1 */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
/* ISB_nIN2 */
@@ -669,27 +562,11 @@
/* ITU656_nPDN */
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
- /* HW revision detect */
- /* REV_ID0 */
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
- /* REV_ID1 */
- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
- /* REV_ID2 */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
- /* REV_ID3 */
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
- /* REV_ID4 */
- MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
-
/* New in HW revision 1 */
/* ON1_FB */
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0
/* DIP1_FB */
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
-
- /* New in UT2: FIXME: ISB PWM should start off, PD */
- /* ISB_LED_PWM */
- MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0
>;
};
@@ -729,6 +606,8 @@
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0
/* POWER_LED */
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0
+ /* ISB_LED */
+ MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0
>;
};
@@ -738,20 +617,23 @@
>;
};
- /* YaCO AUX Uart */
- pinctrl_uart1: uart1grp {
+ pinctrl_pwm2: pwm2grp {
fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
>;
};
- pinctrl_uart2: uart2grp {
+ /* YaCO AUX Uart */
+ pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
@@ -797,19 +679,6 @@
>;
};
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- /* WL12xx IRQ */
- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880
- >;
- };
-
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
@@ -825,10 +694,4 @@
MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
>;
};
-
- pinctrl_wifi_npd: wifinpdgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0
- >;
- };
};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index ec6fba5ee8fd..e4f63423d8ee 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -131,7 +131,6 @@
pinctrl-0 = <&pinctrl_ov5645>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
- clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&reg_1p8v>;
vdda-supply = <&reg_2p8v>;
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 525ff62b47f5..5bb47c79a4da 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -277,7 +277,7 @@
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d27beb47f9a3..b72ec745f6d1 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -143,7 +143,7 @@
#phy-cells = <0>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -157,7 +157,6 @@
<0 13 IRQ_TYPE_LEVEL_HIGH>,
<0 13 IRQ_TYPE_LEVEL_HIGH>,
<0 13 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
@@ -290,7 +289,7 @@
status = "disabled";
};
- bus@2000000 { /* AIPS1 */
+ aips1: bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -762,7 +761,7 @@
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
- regulator-enable-ramp-delay = <150>;
+ regulator-enable-ramp-delay = <380>;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
@@ -929,7 +928,7 @@
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
};
- sdma: sdma@20ec000 {
+ sdma: dma-controller@20ec000 {
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -941,7 +940,7 @@
};
};
- bus@2100000 { /* AIPS2 */
+ aips2: bus@2100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -1050,9 +1049,11 @@
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>,
- <&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp", "enet_out";
+ <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
fsl,stop-mode = <&gpr 0x34 27>;
+ nvmem-cells = <&fec_mac_addr>;
+ nvmem-cell-names = "mac-address";
status = "disabled";
};
@@ -1186,6 +1187,10 @@
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
+
+ fec_mac_addr: mac-addr@88 {
+ reg = <0x88 6>;
+ };
};
tzasc@21d0000 { /* TZASC1 */
diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/imx6qp-vicutp.dts
index 7bad7ca6b12e..49ff145fffe5 100644
--- a/arch/arm/boot/dts/imx6qp-vicutp.dts
+++ b/arch/arm/boot/dts/imx6qp-vicutp.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-vicut1.dtsi"
+#include "imx6qdl-vicut1-12inch.dtsi"
/ {
model = "Kverneland UT1P Board";
diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts
index cea165f2161a..afaf4a6759d4 100644
--- a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts
+++ b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts
@@ -33,6 +33,10 @@
status = "okay";
};
+&reg_pu {
+ regulator-always-on;
+};
+
&reg_usb_h1_vbus {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts
new file mode 100644
index 000000000000..4a961a33bf2d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2021 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6dl-yapp43-common.dtsi"
+
+/ {
+ model = "Y Soft IOTA Pegasus+ i.MX6QuadPlus board";
+ compatible = "ysoft,imx6qp-yapp4-pegasus-plus", "fsl,imx6qp";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0xf0000000>;
+ };
+};
+
+&gpio_oled {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+};
+
+&oled_1305 {
+ status = "okay";
+};
+
+&oled_1309 {
+ status = "okay";
+};
+
+&reg_pu {
+ regulator-always-on;
+};
+
+&reg_usb_h1_vbus {
+ status = "okay";
+};
+
+&touchkeys {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
index 050365513836..fc164991d2ae 100644
--- a/arch/arm/boot/dts/imx6qp.dtsi
+++ b/arch/arm/boot/dts/imx6qp.dtsi
@@ -9,12 +9,18 @@
ocram2: sram@940000 {
compatible = "mmio-sram";
reg = <0x00940000 0x20000>;
+ ranges = <0 0x00940000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
ocram3: sram@960000 {
compatible = "mmio-sram";
reg = <0x00960000 0x20000>;
+ ranges = <0 0x00960000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 25f6f2fb1555..dc5d596c18db 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -33,7 +33,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- user {
+ led-user {
label = "debug";
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -137,7 +137,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/imx6sl-kobo-aura2.dts b/arch/arm/boot/dts/imx6sl-kobo-aura2.dts
new file mode 100644
index 000000000000..657d0f1b6115
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-kobo-aura2.dts
@@ -0,0 +1,555 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for the Kobo Aura 2 ebook reader
+ *
+ * Name on mainboard is: 37NB-E60QL0+4B1
+ * Serials start with: E60QL2
+ *
+ * Copyright 2022 Andreas Kemnade
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "imx6sl.dtsi"
+
+/ {
+ model = "Kobo Aura 2";
+ compatible = "kobo,aura2", "fsl,imx6sl";
+
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-cover {
+ label = "Cover";
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-source;
+ };
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+
+ led-0 {
+ label = "koboaura2:white:on";
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_WHITE>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+ regulator-name = "SD3_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+ post-power-on-delay-ms = <20>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+ status = "okay";
+
+ lm3630a: backlight@36 {
+ compatible = "ti,lm3630a";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
+ reg = <0x36>;
+ enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0>;
+ label = "backlight";
+ default-brightness = <0>;
+ max-brightness = <255>;
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ /* eKTF2232 at 0x15 */
+ /* FP9928 at 0x48 */
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ ricoh619: pmic@32 {
+ compatible = "ricoh,rc5t619";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+ reg = <0x32>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ system-power-controller;
+
+ regulators {
+ dcdc1_reg: DCDC1 {
+ regulator-name = "DCDC1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <900000>;
+ regulator-suspend-min-microvolt = <900000>;
+ };
+ };
+
+ /* Core3_3V3 */
+ dcdc2_reg: DCDC2 {
+ regulator-name = "DCDC2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3100000>;
+ regulator-suspend-min-microvolt = <3100000>;
+ };
+ };
+
+ dcdc3_reg: DCDC3 {
+ regulator-name = "DCDC3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V2 */
+ dcdc4_reg: DCDC4 {
+ regulator-name = "DCDC4";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V8 */
+ dcdc5_reg: DCDC5 {
+ regulator-name = "DCDC5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1700000>;
+ regulator-suspend-min-microvolt = <1700000>;
+ };
+ };
+
+ /* IR_3V3 */
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* Core1_3V3 */
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3000000>;
+ regulator-suspend-min-microvolt = <3000000>;
+ };
+ };
+
+ /* Core5_1V2 */
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-boot-on;
+ };
+
+ /* SPD_3V3 */
+ ldo5_reg: LDO5 {
+ regulator-name = "LDO5";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* DDR_0V6 */
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* VDD_PWM */
+ ldo7_reg: LDO7 {
+ regulator-name = "LDO7";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* ldo_1v8 */
+ ldo8_reg: LDO8 {
+ regulator-name = "LDO8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "LDO9";
+ regulator-boot-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "LDO10";
+ regulator-boot-on;
+ };
+
+ ldortc1_reg: LDORTC1 {
+ regulator-name = "LDORTC1";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&reg_vdd1p1 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+&reg_arm {
+ vin-supply = <&dcdc3_reg>;
+};
+
+&reg_soc {
+ vin-supply = <&dcdc1_reg>;
+};
+
+&reg_pu {
+ vin-supply = <&dcdc1_reg>;
+};
+
+&snvs_rtc {
+ /*
+ * We are using the RTC in the PMIC, but this one is not disabled
+ * in imx6sl.dtsi.
+ */
+ status = "disabled";
+};
+
+&uart1 {
+ /* J4, through-holes */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart4 {
+ /* TP198, next to J4, SMD pads */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>;
+ non-removable;
+ status = "okay";
+
+ /* internal uSD card */
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+ vmmc-supply = <&reg_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ cap-power-off-card;
+ non-removable;
+ status = "okay";
+
+ /*
+ * RTL8189F SDIO WiFi
+ */
+};
+
+&usbotg1 {
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059
+ MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
+ >;
+ };
+
+ pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
+ MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
+ MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1
+ MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
+ MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
+ MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
+ MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
+ MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
+ MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
+ MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
+ MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
+ MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
index a17b8bbbdb95..815119c12bd4 100644
--- a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
@@ -18,6 +18,21 @@
model = "Tolino Shine 2 HD";
compatible = "kobo,tolino-shine2hd", "fsl,imx6sl";
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ec 0 50000>;
+ power-supply = <&backlight_regulator>;
+ };
+
+ backlight_regulator: regulator-backlight {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight_power>;
+ regulator-name = "backlight";
+ gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
chosen {
stdout-path = &uart1;
};
@@ -27,7 +42,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- cover {
+ key-cover {
label = "Cover";
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
@@ -35,19 +50,19 @@
wakeup-source;
};
- fl {
+ key-fl {
label = "Frontlight";
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BRIGHTNESS_CYCLE>;
};
- home {
+ key-home {
label = "Home";
gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
- power {
+ key-power {
label = "Power";
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -60,11 +75,17 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- on {
+ led-0 {
label = "tolinoshine2hd:white:on";
gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
+
+ led-1 {
+ label = "tolinoshine2hd:white:backlightboost";
+ gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "off";
+ };
};
memory@80000000 {
@@ -299,6 +320,12 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
+ pinctrl_backlight_power: backlight-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059
@@ -383,7 +410,8 @@
pinctrl_led: ledgrp {
fsl,pins = <
- MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059
+ MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059
+ MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059
>;
};
@@ -597,6 +625,7 @@
&usbotg1 {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
disable-over-current;
srp-disable;
hnp-disable;
diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
index e3f1e8d79528..db5d8509935f 100644
--- a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
@@ -52,6 +52,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
+ pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */
+ MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x10059 /* TP_RST */
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */
diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision.dts b/arch/arm/boot/dts/imx6sl-tolino-vision.dts
new file mode 100644
index 000000000000..2694fe18a91b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-tolino-vision.dts
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for the Tolino Vison ebook reader
+ *
+ * Name on mainboard is: 37NB-E60Q30+4A3
+ * Serials start with: 6032
+ *
+ * Copyright 2023 Andreas Kemnade
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+
+/ {
+ model = "Tolino Vision";
+ compatible = "kobo,tolino-vision", "fsl,imx6sl";
+
+ aliases {
+ mmc0 = &usdhc4;
+ mmc1 = &usdhc2;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&ec 0 50000>;
+ power-supply = <&backlight_regulator>;
+ };
+
+ backlight_regulator: regulator-backlight {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight_power>;
+ regulator-name = "backlight";
+ gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-cover {
+ /* magnetic sensor in the corner next to the uSD slot */
+ label = "Cover";
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-source;
+ };
+
+ key-fl {
+ label = "Frontlight";
+ gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BRIGHTNESS_CYCLE>;
+ };
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led-0 {
+ /* LED on home button */
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ /* LED on power button */
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+ regulator-name = "SD3_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ };
+
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+ post-power-on-delay-ms = <20>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+ status = "okay";
+
+ touchscreen@15 {
+ compatible = "elan,ektf2132";
+ reg = <0x15>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ts>;
+ power-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+ interrupts-extended = <&gpio5 6 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ accelerometer@1d {
+ compatible = "fsl,mma8652";
+ reg = <0x1d>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ ec: embedded-controller@43 {
+ compatible = "netronix,ntxec";
+ reg = <0x43>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ec>;
+ interrupts-extended = <&gpio5 11 IRQ_TYPE_EDGE_FALLING>;
+ system-power-controller;
+ };
+};
+
+&snvs_rtc {
+ /*
+ * We are using the RTC in the PMIC, but this one is not disabled
+ * in imx6sl.dtsi.
+ */
+ status = "disabled";
+};
+
+&uart1 {
+ /* J4 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart4 {
+ /* J9 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>;
+ cd-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ /* removable uSD card */
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+ vmmc-supply = <&reg_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ cap-power-off-card;
+ non-removable;
+ status = "okay";
+
+ /* CyberTan WC121 (BCM43362) SDIO WiFi */
+};
+
+&usdhc4 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc4_sleep>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+
+ /* internal eMMC */
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_backlight_power: backlight-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059
+ >;
+ };
+
+ pinctrl_ec: ecgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x17000
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x110B0
+ MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x110B0
+ MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x11030
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_leds: ledsgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
+ MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x17059
+ MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059
+ >;
+ };
+
+ pinctrl_ts: tsgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x110B0
+ MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x1B0B1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1
+ MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
+ MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
+ MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
+ MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
+ MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
+ MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
+ MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
+ MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
+ MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x17059
+ MX6SL_PAD_FEC_MDIO__SD4_CLK 0x13059
+ MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x17059
+ MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x17059
+ MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x17059
+ MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x17059
+ MX6SL_PAD_FEC_MDC__SD4_DATA4 0x17059
+ MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x17059
+ MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x17059
+ MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x17059
+ MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x17068
+ >;
+ };
+
+ pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170b9
+ MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130b9
+ MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170b9
+ MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170b9
+ MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170b9
+ MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170b9
+ MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170b9
+ MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170b9
+ MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170b9
+ MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170f9
+ MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130f9
+ MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170f9
+ MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170f9
+ MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170f9
+ MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170f9
+ MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170f9
+ MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170f9
+ MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170f9
+ MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc4_sleep: usdhc4-sleepgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x100c1
+ MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x100c1
+ MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x100c1
+ MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x100c1
+ MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x100c1
+ MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x100c1
+ MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x100c1
+ MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x100c1
+ MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x100c1
+ MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/imx6sl-tolino-vision5.dts
index ff6118df3946..6bc342035e2b 100644
--- a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts
+++ b/arch/arm/boot/dts/imx6sl-tolino-vision5.dts
@@ -52,6 +52,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
+ pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x17059 /* TP_INT */
+ MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x10059 /* TP_RST */
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c7d907c5c352..28111efb19a6 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -50,7 +50,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
@@ -61,10 +61,10 @@
<792000 1175000>,
<396000 975000>;
fsl,soc-operating-points =
- /* ARM kHz SOC-PU uV */
- <996000 1225000>,
- <792000 1175000>,
- <396000 1175000>;
+ /* ARM kHz SOC-PU uV */
+ <996000 1225000>,
+ <792000 1175000>,
+ <396000 1175000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
@@ -115,6 +115,9 @@
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
+ ranges = <0 0x00900000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
@@ -222,7 +225,7 @@
uart5: serial@2018000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -235,7 +238,7 @@
uart1: serial@2020000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -248,7 +251,7 @@
uart2: serial@2024000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -309,7 +312,7 @@
uart3: serial@2034000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -322,7 +325,7 @@
uart4: serial@2038000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02038000 0x4000>;
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -711,7 +714,7 @@
#power-domain-cells = <0>;
power-supply = <&reg_pu>;
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
- <&clks IMX6SL_CLK_GPU2D_PODF>;
+ <&clks IMX6SL_CLK_GPU2D_PODF>;
};
pd_disp: power-domain@2 {
@@ -747,7 +750,7 @@
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
};
- sdma: sdma@20ec000 {
+ sdma: dma-controller@20ec000 {
compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts
index 32b3d82fec53..269092ac881c 100644
--- a/arch/arm/boot/dts/imx6sll-evk.dts
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -37,7 +37,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- user {
+ led-user {
label = "debug";
gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
index 90b32f5eb529..c7cfe0b70f04 100644
--- a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
+++ b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
@@ -62,6 +62,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
+ pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x17059 /* TP_INT */
+ MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x10059 /* TP_RST */
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */
diff --git a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts
index a8b0e88064d9..7e4f38dd11e2 100644
--- a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts
+++ b/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts
@@ -62,6 +62,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
+ pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* TP_INT */
+ MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x10059 /* TP_RST */
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index d4a000c3dde7..2873369a57c0 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -115,6 +115,9 @@
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
+ ranges = <0 0x00900000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
intc: interrupt-controller@a01000 {
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
index 66af78e83b70..a2c79bcf9a11 100644
--- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
@@ -107,7 +107,7 @@
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 83ee97252ff1..b0c27b9b0244 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -20,7 +20,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
- user {
+ led-user {
label = "debug";
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index dce5dcf96c25..7dda42553f4b 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -123,7 +123,7 @@
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
- flash0: s25fl128s@0 {
+ flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
@@ -133,7 +133,7 @@
spi-tx-bus-width = <4>;
};
- flash1: s25fl128s@2 {
+ flash1: flash@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 99f4cf777a38..969cfe920d25 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -108,7 +108,7 @@
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
- flash0: n25q256a@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
@@ -118,7 +118,7 @@
reg = <0>;
};
- flash1: n25q256a@2 {
+ flash1: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
index 35861bbea94e..725d0b5cb55f 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
@@ -15,14 +15,14 @@
leds {
compatible = "gpio-leds";
- red {
+ led-red {
label = "udoo-neo:red:mmc";
gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
- orange {
+ led-orange {
label = "udoo-neo:orange:user";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
default-state = "keep";
@@ -226,7 +226,7 @@
&iomuxc {
pinctrl_bt_reg: btreggrp {
fsl,pins =
- <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
+ <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
};
pinctrl_enet1: enet1grp {
@@ -306,7 +306,6 @@
>;
};
-
pinctrl_uart1: uart1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>,
@@ -347,24 +346,23 @@
pinctrl_otg1_reg: otg1grp {
fsl,pins =
- <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>;
+ <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>;
};
-
pinctrl_otg2_reg: otg2grp {
fsl,pins =
- <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>;
+ <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins =
- <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>,
- <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>;
+ <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>,
+ <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins =
- <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>;
+ <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>;
};
pinctrl_usdhc2: usdhc2grp {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index fc6334336b3d..93ac2380ca1e 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -154,7 +154,7 @@
#phy-cells = <0>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -164,12 +164,18 @@
ocram_s: sram@8f8000 {
compatible = "mmio-sram";
reg = <0x008f8000 0x4000>;
+ ranges = <0 0x008f8000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX6SX_CLK_OCRAM_S>;
};
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
+ ranges = <0 0x00900000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
@@ -210,7 +216,6 @@
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
@@ -842,7 +847,7 @@
reg = <0x020e4000 0x4000>;
};
- sdma: sdma@20ec000 {
+ sdma: dma-controller@20ec000 {
compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -1385,7 +1390,7 @@
pwm8: pwm@22b0000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
- reg = <0x0022b0000 0x4000>;
+ reg = <0x022b0000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_PWM8>,
<&clks IMX6SX_CLK_PWM8>;
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index a3fde3316c73..7275a1366413 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -2,6 +2,8 @@
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.
+#include <dt-bindings/media/video-interfaces.h>
+
/ {
chosen {
stdout-path = &uart1;
@@ -82,7 +84,7 @@
"AMIC", "MICB";
};
- spi4 {
+ spi-4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
@@ -170,7 +172,7 @@
port {
parallel_from_ov5640: endpoint {
remote-endpoint = <&ov5640_to_parallel>;
- bus-type = <5>; /* Parallel bus */
+ bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
};
};
};
@@ -286,7 +288,7 @@
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
- flash0: n25q256a@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts b/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts
index 5bfad4655b22..0c643706a158 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
+++ b/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts
@@ -5,12 +5,12 @@
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
-#include "imx6ul-kontron-n6310-s.dts"
+#include "imx6ul-kontron-bl.dts"
/ {
- model = "Kontron N6310 S 43";
- compatible = "kontron,imx6ul-n6310-s-43", "kontron,imx6ul-n6310-s",
- "kontron,imx6ul-n6310-som", "fsl,imx6ul";
+ model = "Kontron BL i.MX6UL 43 (N631X S 43)";
+ compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
+ "kontron,sl-imx6ul", "fsl,imx6ul";
backlight {
compatible = "pwm-backlight";
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi
index 770f59b23102..43868311f48a 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
+++ b/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi
@@ -72,7 +72,6 @@
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
- num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
@@ -178,7 +177,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
- fsl,uart-has-rtscts;
+ uart-has-rtscts;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts b/arch/arm/boot/dts/imx6ul-kontron-bl.dts
index 5a3e06d6219b..dadf6d3d5f52 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
+++ b/arch/arm/boot/dts/imx6ul-kontron-bl.dts
@@ -7,11 +7,10 @@
/dts-v1/;
-#include "imx6ul-kontron-n6310-som.dtsi"
-#include "imx6ul-kontron-n6x1x-s.dtsi"
+#include "imx6ul-kontron-sl.dtsi"
+#include "imx6ul-kontron-bl-common.dtsi"
/ {
- model = "Kontron N6310 S";
- compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som",
- "fsl,imx6ul";
+ model = "Kontron BL i.MX6UL (N631X S)";
+ compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
deleted file mode 100644
index 47d3ce5d255f..000000000000
--- a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
- */
-
-#include "imx6ul.dtsi"
-#include "imx6ul-kontron-n6x1x-som-common.dtsi"
-
-/ {
- model = "Kontron N6310 SOM";
- compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul";
-
- memory@80000000 {
- reg = <0x80000000 0x10000000>;
- device_type = "memory";
- };
-};
-
-&qspi {
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <108000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- reg = <0>;
-
- partition@0 {
- label = "ubi1";
- reg = <0x00000000 0x08000000>;
- };
-
- partition@8000000 {
- label = "ubi2";
- reg = <0x08000000 0x08000000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts
deleted file mode 100644
index 239a1af3aeaa..000000000000
--- a/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- */
-
-/dts-v1/;
-
-#include "imx6ul-kontron-n6311-som.dtsi"
-#include "imx6ul-kontron-n6x1x-s.dtsi"
-
-/ {
- model = "Kontron N6311 S";
- compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som",
- "fsl,imx6ul";
-};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi
deleted file mode 100644
index a095a7654ac6..000000000000
--- a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- */
-
-#include "imx6ul.dtsi"
-#include "imx6ul-kontron-n6x1x-som-common.dtsi"
-
-/ {
- model = "Kontron N6311 SOM";
- compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul";
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- device_type = "memory";
- };
-};
-
-&qspi {
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <104000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- reg = <0>;
-
- partition@0 {
- label = "ubi1";
- reg = <0x00000000 0x08000000>;
- };
-
- partition@8000000 {
- label = "ubi2";
- reg = <0x08000000 0x18000000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi
index 2a449a3c1ae2..dcf88f610346 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi
+++ b/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi
@@ -11,6 +11,11 @@
chosen {
stdout-path = &uart4;
};
+
+ memory@80000000 {
+ reg = <0x80000000 0x10000000>;
+ device_type = "memory";
+ };
};
&ecspi2 {
@@ -19,7 +24,7 @@
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
@@ -55,6 +60,16 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
};
&wdog1 {
diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi b/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi
new file mode 100644
index 000000000000..0580d043e5ae
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-kontron-sl-common.dtsi"
+
+/ {
+ model = "Kontron SL i.MX6UL (N631X SOM)";
+ compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
+};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 3cddc68917a0..a3ea1b208462 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -30,7 +30,7 @@
pinctrl-0 = <&pinctrl_gpioleds_som>;
compatible = "gpio-leds";
- phycore-green {
+ led-phycore-green {
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
@@ -102,6 +102,10 @@
status = "disabled";
};
+&wdog1 {
+ fsl,suspend-in-wait;
+};
+
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
index 7cda6944501d..ec042648bd98 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
@@ -11,7 +11,7 @@
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <5>;
power-supply = <&reg_backlight_en>;
- pwms = <&pwm3 0 5000000>;
+ pwms = <&pwm3 0 5000000 0>;
status = "disabled";
};
@@ -72,8 +72,8 @@
st,settling = <2>;
st,fraction-z = <7>;
st,i-drive = <1>;
- touchscreen-inverted-x = <1>;
- touchscreen-inverted-y = <1>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
};
};
};
@@ -91,7 +91,6 @@
};
&pwm3 {
- #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 0d4ba9494cf2..38ea4dcfa228 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -83,11 +83,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
vref-supply = <&reg_adc1_vref_3v3>;
- /*
- * driver can not separate a specific channel so we request 4 channels
- * here - we need only the fourth channel
- */
- num-channels = <4>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts
index 162dc259edc8..5a74c7f68eb6 100644
--- a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts
+++ b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts
@@ -32,7 +32,7 @@
};
&i2c2 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/imx6ul-prti6g.dts
index c18390f238e1..b7c96fbe7a91 100644
--- a/arch/arm/boot/dts/imx6ul-prti6g.dts
+++ b/arch/arm/boot/dts/imx6ul-prti6g.dts
@@ -26,6 +26,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet1_ref_pad";
};
leds {
@@ -60,6 +61,13 @@
status = "okay";
};
+&clks {
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&clock_ksz8081_out>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "enet1_ref_pad";
+ assigned-clocks = <&clks IMX6UL_CLK_ENET1_REF_SEL>;
+ assigned-clock-parents = <&clock_ksz8081_out>;
+};
+
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -85,12 +93,6 @@
pinctrl-0 = <&pinctrl_eth1>;
phy-mode = "rmii";
phy-handle = <&rmii_phy>;
- clocks = <&clks IMX6UL_CLK_ENET>,
- <&clks IMX6UL_CLK_ENET_AHB>,
- <&clks IMX6UL_CLK_ENET_PTP>,
- <&clock_ksz8081_out>;
- clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref";
status = "okay";
mdio {
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi
new file mode 100644
index 000000000000..57e647fc3237
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/*
+ * Common for
+ * - TQMa6ULx
+ * - TQMa6ULxL
+ * - TQMa6ULLx
+ * - TQMa6ULLxL
+ */
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_recovery>;
+ scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pfuze3000: pmic@8 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ reg_sw1a: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-ramp-delay = <6250>;
+ /* not used */
+ };
+
+ reg_sw1b_core: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ reg_sw2: sw2 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_sw3_ddr: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_swbst: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ /* not used */
+ };
+
+ reg_snvs_3v0: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vrefddr: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vccsd: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_v33_3v3: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_vldo1_3v3: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ /* not used */
+ };
+
+ reg_vldo2: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ /* not used */
+ };
+
+ reg_vldo3: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ /* not used */
+ };
+
+ reg_vldo4: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ jc42_1a: eeprom-temperature@1a {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x1a>;
+ };
+
+ m24c64_50: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+
+ m24c02_52: eeprom@52 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ read-only;
+ };
+
+ rtc0: rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+
+ /*
+ * PMIC & temperature sensor IRQ
+ * Both do currently not use IRQ
+ * potentially dangerous if used on baseboard
+ */
+ pmic-int-hog {
+ gpio-hog;
+ gpios = <24 0>;
+ input;
+ };
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <33000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ reg = <0>;
+ };
+};
+
+/* eMMC */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz" , "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+
+ bus-width = <8>;
+ disable-wp;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4_recovery: i2c4recoverygrp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0
+ MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0
+ >;
+ };
+
+ pinctrl_pmic: pmic {
+ fsl,pins = <
+ /* PMIC irq */
+ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts
new file mode 100644
index 000000000000..f2a5f17f312e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-tqma6ul1.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";
+ compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
+};
+
+/*
+ * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage)
+ * and need to be disabled here again
+ */
+&can2 {
+ status = "disabled";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ max-speed = <100>;
+ reg = <0>;
+ };
+ };
+};
+
+&fec2 {
+ /delete-property/ phy-handle;
+ /delete-node/ mdio;
+};
+
+&iomuxc {
+ pinctrl_enet1_mdc: enet1mdcgrp {
+ fsl,pins = <
+ /* mdio */
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi
new file mode 100644
index 000000000000..24192d012ef7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ul-tqma6ul2.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL1 SoM";
+ compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
+};
+
+/*
+ * There are no module specific differences compared to TQMa6UL2,
+ * only external interfaces differ
+ */
+
+/*
+ * Devices not available on i.MX6ULG1 and should not be enabled on
+ * mainboard level (again)
+ */
+&can2 {
+ status = "disabled";
+};
+
+&csi {
+ status = "disabled";
+};
+
+&fec2 {
+ status = "disabled";
+};
+
+&lcdif {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts
new file mode 100644
index 000000000000..0757df2b8f48
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-tqma6ul2.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board";
+ compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi
new file mode 100644
index 000000000000..e2e95dd92263
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulx-common.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL2 SoM";
+ compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
+};
+
+&usdhc2 {
+ fsl,tuning-step = <6>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
new file mode 100644
index 000000000000..9d9b6b744a1c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-tqma6ul2l.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board";
+ compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
new file mode 100644
index 000000000000..4b87e2dc70dc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulxl-common.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6UL2L SoM";
+ compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
+};
+
+&usdhc2 {
+ fsl,tuning-step = <6>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi
new file mode 100644
index 000000000000..5afb9046c202
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/*
+ * Common for
+ * - TQMa6ULx
+ * - TQMa6ULLx
+ */
+
+&m24c64_50 {
+ vcc-supply = <&reg_sw2>;
+};
+
+&m24c02_52 {
+ vcc-supply = <&reg_sw2>;
+};
+
+&reg_sw2 {
+ regulator-boot-on;
+ regulator-always-on;
+};
+
+/* eMMC */
+&usdhc2 {
+ vmmc-supply = <&reg_sw2>;
+ vqmmc-supply = <&reg_vldo4>;
+};
+
+&iomuxc {
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
new file mode 100644
index 000000000000..ba84a4f70ebd
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/*
+ * Common for
+ * - TQMa6ULxL
+ * - TQMa6ULLxL
+ */
+
+/ {
+ reg_vin: reg-vin {
+ compatible = "regulator-fixed";
+ regulator-name = "VIN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&m24c64_50 {
+ vcc-supply = <&reg_vin>;
+};
+
+&m24c02_52 {
+ vcc-supply = <&reg_vin>;
+};
+
+/* eMMC */
+&usdhc2 {
+ vmmc-supply = <&reg_vin>;
+ vqmmc-supply = <&reg_vldo4>;
+};
+
+&iomuxc {
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index c485d058e079..70cef5e817bd 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -131,7 +131,7 @@
leds {
compatible = "gpio-leds";
- user_led: user {
+ user_led: led-user {
label = "Heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
@@ -212,7 +212,7 @@
enable-active-high;
};
- spi_gpio: spi-gpio {
+ spi_gpio: spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "spi-gpio";
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index afeec01f6522..3d9d0f823568 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -64,20 +64,18 @@
clock-frequency = <696000000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 696000 1275000
- 528000 1175000
- 396000 1025000
- 198000 950000
- >;
- fsl,soc-operating-points = <
+ <696000 1275000>,
+ <528000 1175000>,
+ <396000 1025000>,
+ <198000 950000>;
+ fsl,soc-operating-points =
/* KHz uV */
- 696000 1275000
- 528000 1175000
- 396000 1175000
- 198000 1175000
- >;
+ <696000 1275000>,
+ <528000 1175000>,
+ <396000 1175000>,
+ <198000 1175000>;
clocks = <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL2_BUS>,
<&clks IMX6UL_CLK_PLL2_PFD2>,
@@ -139,7 +137,7 @@
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -149,6 +147,9 @@
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
+ ranges = <0 0x00900000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
intc: interrupt-controller@a01000 {
@@ -170,7 +171,6 @@
<0 13 IRQ_TYPE_LEVEL_HIGH>,
<0 13 IRQ_TYPE_LEVEL_HIGH>,
<0 13 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clks IMX6UL_CLK_APBHDMA>;
@@ -531,10 +531,9 @@
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
- <&clks IMX6UL_CLK_ENET2_REF_125M>,
- <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ <&clks IMX6UL_CLK_ENET2_REF_SEL>;
clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
+ "enet_clk_ref";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
@@ -543,7 +542,7 @@
};
kpp: keypad@20b8000 {
- compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
+ compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_KPP>;
@@ -743,7 +742,7 @@
status = "disabled";
};
- sdma: sdma@20ec000 {
+ sdma: dma-controller@20ec000 {
compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
"fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
@@ -879,10 +878,9 @@
clocks = <&clks IMX6UL_CLK_ENET>,
<&clks IMX6UL_CLK_ENET_AHB>,
<&clks IMX6UL_CLK_ENET_PTP>,
- <&clks IMX6UL_CLK_ENET_REF>,
- <&clks IMX6UL_CLK_ENET_REF>;
+ <&clks IMX6UL_CLK_ENET1_REF_SEL>;
clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
+ "enet_clk_ref";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 3>;
@@ -923,7 +921,6 @@
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ADC1>;
- num-channels = <2>;
clock-names = "adc";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
@@ -998,7 +995,7 @@
};
csi: csi@21c4000 {
- compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
+ compatible = "fsl,imx6ul-csi";
reg = <0x021c4000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CSI>;
@@ -1007,7 +1004,7 @@
};
lcdif: lcdif@21c8000 {
- compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
+ compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
reg = <0x021c8000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
@@ -1028,7 +1025,7 @@
qspi: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
+ compatible = "fsl,imx6ul-qspi";
reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
new file mode 100644
index 000000000000..3e0897c3a296
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ /* Pin already used by atmel_mxt_ts touchscreen */
+ status = "disabled";
+};
+
+/* PWM <C> */
+&pwm6 {
+ /* Pin already used by atmel_mxt_ts touchscreen */
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
new file mode 100644
index 000000000000..de4dc7c1a03a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+
+ num-cs = <2>;
+ cs-gpios = <
+ &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */
+ &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */
+ >;
+};
+
+/*
+ * Following SODIMM Pins should not be accessed as GPIO on Aster board:
+ * 134 - AIN5_SCL (no connection)
+ * 127 - Voltage Level Translator OE# signal (IC11 and IC12)
+ *
+ * To configure GPIO to LED5, please disable FEC2 and uncomment the following:
+ * &iomuxc {
+ * pinctrl-names = "default";
+ * pinctrl-0 = <
+ * &pinctrl_gpio1
+ * &pinctrl_gpio2
+ * &pinctrl_gpio3
+ * &pinctrl_gpio4
+ * &pinctrl_gpio6 - for non-WiFi modules only
+ * &pinctrl_gpio7
+ * &pinctrl_gpio_aster
+ * >;
+ *
+ * pinctrl_gpio_aster: gpio-aster {
+ * fsl,pins = <
+ * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0
+ * >;
+ * };
+ * };
+ */
+
+&i2c1 {
+ status = "okay";
+
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ disable-over-current;
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ disable-over-current;
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <&reg_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
new file mode 100644
index 000000000000..919c0464d6cb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-emmc-aster",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
new file mode 100644
index 000000000000..b9060c2f7977
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
new file mode 100644
index 000000000000..0ab71f2f5daa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-emmc-iris",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
index a099abfdfa27..ea238525d5c0 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2021 Toradex
+ * Copyright 2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
@@ -8,7 +8,7 @@
/ {
aliases {
mmc0 = &usdhc2; /* eMMC */
- mmc1 = &usdhc1; /* MMC 4bit slot */
+ mmc1 = &usdhc1; /* MMC 4-bit slot */
};
memory@80000000 {
@@ -154,6 +154,7 @@
"SODIMM_127";
};
+/* NAND */
&gpmi {
status = "disabled";
};
@@ -170,6 +171,7 @@
pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
+/* eMMC */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2emmc>;
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
index 08669a18349e..d6da984e518d 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
@@ -9,6 +9,30 @@
#include "imx6ull-colibri-eval-v3.dtsi"
/ {
- model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index a78849fd2afa..692ef26fbab3 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
*/
/ {
@@ -8,20 +8,6 @@
stdout-path = "serial0:115200n8";
};
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
-
- power {
- label = "Wake-Up";
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";
@@ -29,18 +15,6 @@
clock-frequency = <16000000>;
};
- panel: panel {
- compatible = "edt,et057090dhu";
- backlight = <&bl>;
- power-supply = <&reg_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
-
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V";
@@ -71,14 +45,6 @@
status = "okay";
};
-&bl {
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- power-supply = <&reg_3v3>;
- pwms = <&pwm4 0 5000000 1>;
- status = "okay";
-};
-
&ecspi1 {
status = "okay";
@@ -107,16 +73,6 @@
};
};
-&lcdif {
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
/* PWM <A> */
&pwm4 {
status = "okay";
@@ -150,29 +106,18 @@
};
&usbotg1 {
+ disable-over-current;
+ vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
&usbotg2 {
+ disable-over-current;
vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- disable-wp;
- wakeup-source;
- keep-power-in-suspend;
vmmc-supply = <&reg_3v3>;
- vqmmc-supply = <&reg_sd1_vmmc>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
new file mode 100644
index 000000000000..f6b31118be17
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&gpio1 {
+ /* This turns the LVDS transceiver on */
+ lvds-power-on-hog {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode-hog {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+};
+
+&gpio5 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ /* Pin already used by atmel_mxt_ts touchscreen */
+ status = "disabled";
+};
+
+/* PWM <C> */
+&pwm6 {
+ /* Pin already used by atmel_mxt_ts touchscreen */
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
new file mode 100644
index 000000000000..93649cad0cc0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+
+&usdhc1 {
+ cap-power-off-card;
+ vmmc-supply = <&reg_3v3_vmmc>;
+ /delete-property/ keep-power-in-suspend;
+ /delete-property/ no-1-8-v;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts
new file mode 100644
index 000000000000..2a0d0fc3b9d6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
new file mode 100644
index 000000000000..f52f8b5ad8a6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&gpio1 {
+ /*
+ * uart25_tx_on turns the UART transceiver on. If one wants to turn the
+ * transceiver off, that property has to be deleted and the gpio handled
+ * in userspace.
+ * The same applies to uart1_tx_on.
+ */
+ uart25_tx_on-hog {
+ gpio-hog;
+ gpios = <15 0>;
+ output-high;
+ };
+};
+
+&gpio2 {
+ uart1_tx_on-hog {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ disable-over-current;
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ disable-over-current;
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <&reg_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
index 95a11b8bcbdb..88901db255d6 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
@@ -12,13 +12,150 @@
};
};
+&gpio1 {
+ gpio-line-names = "SODIMM_8",
+ "SODIMM_6",
+ "SODIMM_129",
+ "SODIMM_89",
+ "SODIMM_19",
+ "SODIMM_21",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184",
+ "SODIMM_4",
+ "SODIMM_2",
+ "SODIMM_106",
+ "SODIMM_71",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_99",
+ "SODIMM_102",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_32",
+ "SODIMM_34",
+ "SODIMM_135",
+ "SODIMM_77",
+ "SODIMM_100",
+ "SODIMM_186",
+ "SODIMM_196",
+ "SODIMM_194";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_73",
+ "SODIMM_30",
+ "SODIMM_67",
+ "SODIMM_104",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_190",
+ "SODIMM_47",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_29",
+ "SODIMM_37",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_59",
+ "",
+ "",
+ "SODIMM_133",
+ "",
+ "SODIMM_28",
+ "SODIMM_75",
+ "SODIMM_96",
+ "SODIMM_81",
+ "SODIMM_94",
+ "SODIMM_101",
+ "SODIMM_103",
+ "SODIMM_79",
+ "SODIMM_97",
+ "SODIMM_69",
+ "SODIMM_98",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_137",
+ "SODIMM_95",
+ "SODIMM_107",
+ "SODIMM_131",
+ "SODIMM_93",
+ "",
+ "SODIMM_138",
+ "",
+ "SODIMM_105",
+ "SODIMM_127";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
+ &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>;
};
&iomuxc_snvs {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>;
+ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
new file mode 100644
index 000000000000..c7da5b41966f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-wifi-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ /* Pin already used by atmel_mxt_ts touchscreen */
+ status = "disabled";
+};
+
+/* PWM <C> */
+&pwm6 {
+ /* Pin already used by atmel_mxt_ts touchscreen */
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
index df72ce1ae2cb..917f5dbe64ba 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
@@ -12,3 +12,27 @@
model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull";
};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
new file mode 100644
index 000000000000..488da6df56fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-wifi-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&gpio1 {
+ /* This turns the LVDS transceiver on */
+ lvds-power-on-hog {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode-hog {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+};
+
+&gpio5 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
new file mode 100644
index 000000000000..e63253254754
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-wifi-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 9f1e38282bee..db59ee6b1c86 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
@@ -23,16 +23,152 @@
clock-frequency = <792000000>;
};
+&gpio1 {
+ gpio-line-names = "SODIMM_8",
+ "SODIMM_6",
+ "SODIMM_129",
+ "",
+ "SODIMM_19",
+ "SODIMM_21",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184",
+ "SODIMM_4",
+ "SODIMM_2",
+ "SODIMM_106",
+ "SODIMM_71",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_99",
+ "SODIMM_102",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_32",
+ "SODIMM_34",
+ "SODIMM_135",
+ "SODIMM_77",
+ "SODIMM_100",
+ "SODIMM_186",
+ "SODIMM_196",
+ "SODIMM_194";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_73",
+ "SODIMM_30",
+ "SODIMM_67",
+ "SODIMM_104",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_190",
+ "SODIMM_47",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_29",
+ "SODIMM_37",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_59",
+ "",
+ "",
+ "SODIMM_133",
+ "",
+ "SODIMM_28",
+ "SODIMM_75",
+ "SODIMM_96",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_69",
+ "SODIMM_98",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_137",
+ "SODIMM_95",
+ "SODIMM_107",
+ "SODIMM_131",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_105";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>;
+ &pinctrl_gpio4 &pinctrl_gpio7>;
};
&iomuxc_snvs {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>;
+ pinctrl-0 = <&pinctrl_snvs_gpio1>;
};
&usdhc2 {
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 7f35a06dff95..fde8a19aac0f 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -1,24 +1,72 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018-2021 Toradex
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull.dtsi"
/ {
+ /* Ethernet aliases to ensure correct MAC addresses */
aliases {
ethernet0 = &fec2;
ethernet1 = &fec1;
};
- bl: backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
- enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ power-supply = <&reg_3v3>;
+ pwms = <&pwm4 0 5000000 1>;
status = "disabled";
};
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_usbc_det>;
+ id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
+ label = "USBC";
+ self-powered;
+ type = "micro";
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ key-wakeup {
+ debounce-interval = <10>;
+ gpios = <&gpio5 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ panel_dpi: panel-dpi {
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+ power-supply = <&reg_3v3>;
+ status = "disabled";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-always-on;
@@ -35,9 +83,9 @@
regulator-max-microvolt = <3300000>;
};
- reg_sd1_vmmc: regulator-sd1-vmmc {
+ reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio";
- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_reg_sd>;
regulator-always-on;
@@ -47,11 +95,24 @@
states = <1800000 0x1 3300000 0x0>;
vin-supply = <&reg_module_3v3>;
};
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed-clock";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "+V3.3_ETH";
+ regulator-type = "voltage";
+ vin-supply = <&reg_module_3v3>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ startup-delay-us = <150000>;
+ };
};
&adc1 {
- num-channels = <10>;
vref-supply = <&reg_module_3v3_avdd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
};
&can1 {
@@ -73,12 +134,14 @@
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
+/* Ethernet */
&fec2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
+ phy-supply = <&reg_eth_phy>;
status = "okay";
mdio {
@@ -93,9 +156,11 @@
};
};
+/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
@@ -103,15 +168,35 @@
status = "okay";
};
+/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "disabled";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
+ status = "disabled";
+ };
};
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
&i2c2 {
+ /* Use low frequency to compensate for the high pull-up values. */
+ clock-frequency = <40000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
@@ -119,7 +204,7 @@
scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
- ad7879@2c {
+ ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
@@ -133,6 +218,7 @@
adi,median-filter-size = /bits/ 8 <2>;
adi,averaging = /bits/ 8 <1>;
adi,conversion-interval = /bits/ 8 <255>;
+ status = "disabled";
};
};
@@ -140,23 +226,34 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
+ status = "disabled";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
};
+/* PWM <A> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
+/* PWM <B> */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
};
+/* PWM <C> */
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
};
+/* PWM <D> */
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
@@ -170,6 +267,7 @@
status = "disabled";
};
+/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
@@ -177,6 +275,7 @@
fsl,dte-mode;
};
+/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -184,27 +283,50 @@
fsl,dte-mode;
};
+/* Colibri UART_C */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,dte-mode;
};
+/* Colibri USBC */
&usbotg1 {
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
+ usb-role-switch;
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
+ };
};
+/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
};
+/* Colibri MMC/SD */
&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
+ bus-width = <4>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
+ disable-wp;
+ keep-power-in-suspend;
+ no-1-8-v;
+ vqmmc-supply = <&reg_sd1_vqmmc>;
+ wakeup-source;
};
&wdog1 {
@@ -214,13 +336,35 @@
};
&iomuxc {
- pinctrl_can_int: canint-grp {
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
+ >;
+ };
+
+ pinctrl_atmel_adap: atmeladapgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */
+ MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_atmel_conn: atmelconngrp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
+ >;
+ };
+
+ pinctrl_can_int: canintgrp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
>;
};
- pinctrl_enet2: enet2-grp {
+ pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
@@ -235,7 +379,7 @@
>;
};
- pinctrl_enet2_sleep: enet2sleepgrp {
+ pinctrl_enet2_sleep: enet2-sleepgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
@@ -250,13 +394,13 @@
>;
};
- pinctrl_ecspi1_cs: ecspi1-cs-grp {
+ pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
>;
};
- pinctrl_ecspi1: ecspi1-grp {
+ pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
@@ -264,27 +408,27 @@
>;
};
- pinctrl_flexcan1: flexcan1-grp {
+ pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
>;
};
- pinctrl_flexcan2: flexcan2-grp {
+ pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
>;
};
- pinctrl_gpio_bl_on: gpio-bl-on-grp {
+ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
>;
};
- pinctrl_gpio1: gpio1-grp {
+ pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
@@ -297,7 +441,7 @@
>;
};
- pinctrl_gpio2: gpio2-grp { /* Camera */
+ pinctrl_gpio2: gpio2grp { /* Camera */
fsl,pins = <
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
@@ -307,26 +451,20 @@
>;
};
- pinctrl_gpio3: gpio3-grp { /* CAN2 */
+ pinctrl_gpio3: gpio3grp { /* CAN2 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
>;
};
- pinctrl_gpio4: gpio4-grp {
+ pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
>;
};
- pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
- fsl,pins = <
- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
- >;
- };
-
- pinctrl_gpio6: gpio6-grp { /* Wifi pins */
+ pinctrl_gpio6: gpio6grp { /* Wifi pins */
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
@@ -338,7 +476,7 @@
>;
};
- pinctrl_gpio7: gpio7-grp { /* CAN1 */
+ pinctrl_gpio7: gpio7grp { /* CAN1 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
@@ -347,9 +485,9 @@
/*
* With an eMMC instead of a raw NAND device the following pins
- * are available at SODIMM pins
+ * are available at SODIMM pins.
*/
- pinctrl_gpmi_gpio: gpmi-gpio-grp {
+ pinctrl_gpmi_gpio: gpmigpiogrp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
@@ -358,7 +496,7 @@
>;
};
- pinctrl_gpmi_nand: gpmi-nand-grp {
+ pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
@@ -377,35 +515,35 @@
>;
};
- pinctrl_i2c1: i2c1-grp {
+ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
>;
};
- pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
>;
};
- pinctrl_i2c2: i2c2-grp {
+ pinctrl_i2c2: i2c2grp {
fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
>;
};
- pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
- MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
>;
};
- pinctrl_lcdif_dat: lcdif-dat-grp {
+ pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
@@ -428,7 +566,7 @@
>;
};
- pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
@@ -437,31 +575,31 @@
>;
};
- pinctrl_pwm4: pwm4-grp {
+ pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
>;
};
- pinctrl_pwm5: pwm5-grp {
+ pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
>;
};
- pinctrl_pwm6: pwm6-grp {
+ pinctrl_pwm6: pwm6grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
>;
};
- pinctrl_pwm7: pwm7-grp {
+ pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
>;
};
- pinctrl_uart1: uart1-grp {
+ pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
@@ -470,16 +608,16 @@
>;
};
- pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
+ pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
fsl,pins = <
- MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */
- MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */
- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */
- MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
>;
};
- pinctrl_uart2: uart2-grp {
+ pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
@@ -487,23 +625,23 @@
MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
>;
};
- pinctrl_uart5: uart5-grp {
+ pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
>;
};
- pinctrl_usbh_reg: gpio-usbh-reg {
+ pinctrl_usbh_reg: usbhreggrp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
>;
};
- pinctrl_usdhc1: usdhc1-grp {
+ pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
@@ -511,10 +649,10 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -522,25 +660,25 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
- pinctrl_usdhc2: usdhc2-grp {
+ pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069
+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
>;
@@ -561,7 +699,7 @@
>;
};
- pinctrl_wdog: wdog-grp {
+ pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
@@ -569,65 +707,65 @@
};
&iomuxc_snvs {
- pinctrl_snvs_gpio1: snvs-gpio1-grp {
+ pinctrl_atmel_snvs_conn: atmelsnvsconngrp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
- MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
- MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */
- MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
- pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
+ pinctrl_snvs_gpio1: snvsgpio1grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
+ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
- pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
+ pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
>;
};
- pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
+ pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
- pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+ pinctrl_snvs_reg_sd: snvsregsdgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
- pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
+ pinctrl_snvs_usbc_det: snvsusbcdetgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};
- pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
+ pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
>;
};
- pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
+ pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
>;
};
- pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp {
+ pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
>;
};
- pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
+ pinctrl_snvs_wifi_pdn: snvswifipdngrp {
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
>;
diff --git a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts
new file mode 100644
index 000000000000..b539975a872c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2023 DH electronics GmbH
+ *
+ * DHCOM iMX6ULL variant:
+ * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
+ * DHCOR PCB number: 578-200 or newer
+ * DHCOM PCB number: 579-200 or newer
+ * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM)
+ */
+/dts-v1/;
+
+#include "imx6ull-dhcom-som.dtsi"
+#include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
+
+/ {
+ model = "DH electronics i.MX6ULL DHCOM on DRC02";
+ compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som",
+ "dh,imx6ull-dhcor-som", "fsl,imx6ull";
+};
+
+/*
+ * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
+ * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
+ * node below.
+ */
+&can2 {
+ status = "okay";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "DRC02-In2",
+ "", "", "", "",
+ "", "", "DHCOM-I", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "DRC02-HW0", "DRC02-HW1", "DHCOM-M",
+ "DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S",
+ "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
+ "DHCOM-N", "", "", "";
+ /*
+ * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+ * GPIO line, however the i.MX6ULL UART driver assumes RX happens
+ * during TX anyway and that it only controls drive enable DE
+ * line. Hence, the RX is always enabled here.
+ */
+ rs485-rx-en-hog {
+ gpio-hog;
+ gpios = <25 0>; /* GPIO Q */
+ line-name = "rs485-rx-en";
+ output-low;
+ };
+};
+
+&gpio5 {
+ gpio-line-names =
+ "DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2",
+ "DHCOM-E", "", "", "DRC02-Out1",
+ "DRC02-In1", "DHCOM-H", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+/* DHCOM I2C2 */
+&i2c1 {
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
+
+&uart1 {
+ /delete-property/ uart-has-rtscts;
+ rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ cts-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* GPIO M */
+};
+
+/* Use UART as RS485 */
+&uart2 {
+ /delete-property/ uart-has-rtscts;
+ linux,rs485-enabled-at-boot-time;
+ rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */
+};
diff --git a/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts
new file mode 100644
index 000000000000..b29713831a74
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2023 DH electronics GmbH
+ *
+ * DHCOM iMX6ULL variant:
+ * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-RTC-WBT-ADC-I-01D2
+ * DHCOR PCB number: 578-200 or newer
+ * DHCOM PCB number: 579-200 or newer
+ * PDK2 PCB number: 516-400 or newer
+ */
+/dts-v1/;
+
+#include "imx6ull-dhcom-som.dtsi"
+
+/ {
+ model = "DH electronics i.MX6ULL DHCOM on Premium Developer Kit (2)";
+ compatible = "dh,imx6ull-dhcom-pdk2", "dh,imx6ull-dhcom-som",
+ "dh,imx6ull-dhcor-som", "fsl,imx6ull";
+
+ clk_ext_audio_codec: clock-codec {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ display_bl: display-bl {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+ default-brightness-level = <8>;
+ enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* GPIO G */
+ power-supply = <&reg_panel_3v3>;
+ pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-0 {
+ gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* GPIO A */
+ label = "TA1-GPIO-A";
+ linux,code = <KEY_A>;
+ wakeup-source;
+ };
+
+ button-1 {
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; /* GPIO B */
+ label = "TA2-GPIO-B";
+ linux,code = <KEY_B>;
+ wakeup-source;
+ };
+
+ button-2 {
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
+ label = "TA3-GPIO-C";
+ linux,code = <KEY_C>;
+ wakeup-source;
+ };
+
+ button-3 {
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; /* GPIO D */
+ label = "TA4-GPIO-D";
+ linux,code = <KEY_D>;
+ wakeup-source;
+ };
+ };
+
+ led: led {
+ compatible = "gpio-leds";
+
+ /*
+ * Disable PDK2 LED5, because GPIO E is
+ * already used as touch interrupt.
+ */
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <5>; /* PDK2 LED5 */
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; /* GPIO E */
+ status = "disabled";
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <6>; /* PDK2 LED6 */
+ gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; /* GPIO F */
+ };
+
+ /*
+ * Disable PDK2 LED7, because GPIO H is
+ * already used for WiFi pin WL_REG_ON.
+ */
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <7>; /* PDK2 LED7 */
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* GPIO H */
+ status = "disabled";
+ };
+
+ /*
+ * Disable PDK2 LED8, because GPIO I is
+ * already used for BT pin BT_REG_ON.
+ */
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <8>; /* PDK2 LED8 */
+ gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ status = "disabled";
+ };
+ };
+
+ panel {
+ compatible = "edt,etm0700g0edh6";
+ backlight = <&display_bl>;
+ power-supply = <&reg_panel_3v3>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ /* Filtered supply voltage */
+ reg_pdk2_24v: regulator-pdk2-24v {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <24000000>;
+ regulator-min-microvolt = <24000000>;
+ regulator-name = "24V_PDK2";
+ };
+
+ /* PDK2 U35 */
+ reg_pdk2_3v3: regulator-pdk2-3v3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "3V3_PDK2";
+ vin-supply = <&reg_pdk2_24v>;
+ };
+
+ /* 560-200 U1 */
+ reg_panel_3v3: regulator-panel-3v3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "3V3_PANEL";
+ vin-supply = <&reg_pdk2_24v>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,name = "sgtl5000";
+ simple-audio-card,routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In Jack",
+ "Headphone", "Headphone Jack";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ clocks = <&clk_ext_audio_codec>;
+ sound-dai = <&sgtl5000>;
+ };
+ };
+};
+
+/* DHCOM I2C1 */
+&i2c2 {
+ sgtl5000: audio-codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk_ext_audio_codec>;
+ VDDA-supply = <&reg_pdk2_3v3>;
+ VDDIO-supply = <&reg_pdk2_3v3>;
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+ power-supply = <&reg_panel_3v3>;
+ };
+};
+
+&lcdif {
+ status = "okay";
+
+ port {
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&sai2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts b/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts
new file mode 100644
index 000000000000..e4cc2223583a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2023 DH electronics GmbH
+ *
+ * DHCOM iMX6ULL variant:
+ * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
+ * DHCOR PCB number: 578-200 or newer
+ * DHCOM PCB number: 579-200 or newer
+ * PicoITX PCB number: 487-600 or newer
+ */
+/dts-v1/;
+
+#include "imx6ull-dhcom-som.dtsi"
+#include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
+
+/ {
+ model = "DH electronics i.MX6ULL DHCOM on PicoITX";
+ compatible = "dh,imx6ull-dhcom-picoitx", "dh,imx6ull-dhcom-som",
+ "dh,imx6ull-dhcor-som", "fsl,imx6ull";
+
+ led {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_YELLOW>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ };
+ };
+};
+
+&fec1 {
+ phy-handle = <&mdio1_phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio1_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clock-names = "rmii-ref";
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
+ pinctrl-names = "default";
+ reset-assert-us = <500>;
+ reset-deassert-us = <500>;
+ reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
+ };
+ };
+};
+
+&fec2 {
+ status = "disabled";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "PicoITX-HW2", "PicoITX-HW1", "DHCOM-M",
+ "PicoITX-HW0", "DHCOM-U", "DHCOM-T", "DHCOM-S",
+ "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
+ "DHCOM-N", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "DHCOM-A", "DHCOM-B", "PicoITX-In2", "PicoITX-Out2",
+ "PicoITX-In1", "", "", "PicoITX-Out1",
+ "DHCOM-G", "DHCOM-H", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi
new file mode 100644
index 000000000000..040421f9c970
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2023 DH electronics GmbH
+ */
+
+/*
+ * Special SoM configuration: SD card
+ *
+ * Enabled: Micro SD card on module or
+ * external SD card via DHCOM depends on hardware variant
+ * GPIO H and GPIO I will be available
+ * DHCOM UART2 will be available
+ * Disabled: WiFi and BT
+ */
+
+/*
+ * To use usdhc1 as SD card, the WiFi node must be deleted.
+ * BT is also not available, so remove BT from the UART node.
+ */
+/delete-node/ &brcmf;
+/delete-node/ &bluetooth;
+
+/ {
+ aliases {
+ mmc1 = &usdhc1;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ };
+};
+
+/* Micro SD card on module or external SD card via DHCOM */
+&usdhc1 {
+ /delete-property/ #address-cells;
+ /delete-property/ #size-cells;
+ /delete-property/ keep-power-in-suspend;
+ /delete-property/ mmc-pwrseq;
+ /delete-property/ non-removable;
+ /delete-property/ wakeup-source;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <&reg_sd1_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_usdhc1: usdhc1-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */
+
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi
new file mode 100644
index 000000000000..17837663c0b0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi
@@ -0,0 +1,633 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2023 DH electronics GmbH
+ */
+
+#include "imx6ull-dhcor-som.dtsi"
+
+/ {
+ aliases {
+ /delete-property/ mmc0; /* Avoid double definitions */
+ /delete-property/ mmc1;
+ /delete-property/ spi2;
+ /delete-property/ spi3;
+ i2c0 = &i2c2;
+ i2c1 = &i2c1;
+ mmc2 = &usdhc2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ serial0 = &uart1;
+ serial1 = &uart6; /* DHCOM UART2, special hardware required */
+ serial2 = &uart3;
+ serial3 = &uart2; /* Use BT UART always as ttymxc3 */
+ serial4 = &uart4;
+ serial5 = &uart5;
+ spi0 = &ecspi1;
+ spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_ext_3v3_ref: regulator-ext-3v3-ref {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VCC_3V3_REF";
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb-otg1-vbus";
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb-otg2-vbus";
+ };
+
+ /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
+ /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
+ };
+};
+
+/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */
+&bluetooth {
+ shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */
+};
+
+&can1 {
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/*
+ * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
+ * Only if this pins are used as CAN interface enable it on board layer.
+ */
+&can2 {
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default";
+};
+
+/* DHCOM SPI1 */
+&ecspi1 {
+ cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/*
+ * DHCOM SPI2
+ * Special hardware required that uses the pins of FEC2. Therefore this SPI
+ * interface can only be used if FEC2 is disabled.
+ */
+&ecspi4 {
+ cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ pinctrl-names = "default";
+};
+
+/* DHCOM ETH1 */
+&fec1 {
+ phy-handle = <&mdio2_phy0>;
+ phy-mode = "rmii";
+ pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* DHCOM ETH2 */
+&fec2 {
+ phy-handle = <&mdio2_phy1>;
+ phy-mode = "rmii";
+ pinctrl-0 = <&pinctrl_fec2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio2_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clock-names = "rmii-ref";
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>;
+ pinctrl-names = "default";
+ reset-assert-us = <500>;
+ reset-deassert-us = <500>;
+ reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
+ };
+
+ mdio2_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clock-names = "rmii-ref";
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>;
+ pinctrl-names = "default";
+ reset-assert-us = <500>;
+ reset-deassert-us = <500>;
+ reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "DHCOM-INT",
+ "", "", "", "",
+ "", "", "DHCOM-I", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+ pinctrl-0 = <&pinctrl_spi1_switch
+ &pinctrl_dhcom_i &pinctrl_dhcom_int>;
+ pinctrl-names = "default";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "DHCOM-L", "DHCOM-K", "DHCOM-M",
+ "DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S",
+ "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
+ "DHCOM-N", "", "", "";
+ pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k
+ &pinctrl_dhcom_l &pinctrl_dhcom_m
+ &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q
+ &pinctrl_dhcom_r &pinctrl_dhcom_s
+ &pinctrl_dhcom_t &pinctrl_dhcom_u>;
+ pinctrl-names = "default";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D",
+ "DHCOM-E", "", "", "DHCOM-F",
+ "DHCOM-G", "DHCOM-H", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+ pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b
+ &pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d
+ &pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f
+ &pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>;
+ pinctrl-names = "default";
+};
+
+/* DHCOM I2C2 */
+&i2c1 {
+ rtc_i2c: rtc@32 {
+ compatible = "microcrystal,rv8803";
+ reg = <0x32>;
+ };
+
+ /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ /* TI ADC101C027 */
+ adc@51 {
+ compatible = "ti,adc101c";
+ reg = <0x51>;
+ vref-supply = <&reg_ext_3v3_ref>;
+ };
+
+ /* TI ADC101C027 */
+ adc@52 {
+ compatible = "ti,adc101c";
+ reg = <0x52>;
+ vref-supply = <&reg_ext_3v3_ref>;
+ };
+
+ /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+};
+
+/* DHCOM I2C1 */
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-0 = <&pinctrl_lcdif>;
+ pinctrl-names = "default";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pinctrl_pwm1>;
+ pinctrl-names = "default";
+};
+
+&sai2 {
+ assigned-clock-rates = <320000000>;
+ assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
+ pinctrl-0 = <&pinctrl_sai2>;
+ pinctrl-names = "default";
+};
+
+&tsc {
+ measure-delay-time = <0xffff>;
+ pinctrl-0 = <&pinctrl_tsc>;
+ pinctrl-names = "default";
+ pre-charge-time = <0xfff>;
+ touchscreen-average-samples = <32>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+};
+
+/* DHCOM UART1 */
+&uart1 {
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/*
+ * DHCOM UART2 (alternative)
+ * Special hardware required that uses DHCOM GPIO pins for DHCOM UART2.
+ * Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are
+ * removed from GPIO hog muxing.
+ */
+&uart6 {
+ pinctrl-0 = <&pinctrl_uart6>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ pinctrl-names = "default";
+ srp-disable;
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ disable-over-current; /* Overcurrent pin is used for TSC */
+ dr_mode = "host";
+ pinctrl-0 = <&pinctrl_usbotg2>;
+ pinctrl-names = "default";
+ tpl-support;
+ vbus-supply = <&reg_usb_otg2_vbus>;
+ status = "okay";
+};
+
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <106>;
+};
+
+/* WiFi on LGA */
+&usdhc1 {
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+};
+
+/* eMMC on module */
+&usdhc2 {
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&iomuxc {
+ /* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */
+ pinctrl_dhcom_i: dhcom-i-grp {
+ fsl,pins = <MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0>;
+ };
+
+ pinctrl_dhcom_j: dhcom-j-grp {
+ fsl,pins = <MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x400120b0>;
+ };
+
+ pinctrl_dhcom_k: dhcom-k-grp {
+ fsl,pins = <MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0>;
+ };
+
+ pinctrl_dhcom_l: dhcom-l-grp {
+ fsl,pins = <MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x400120b0>;
+ };
+
+ pinctrl_dhcom_m: dhcom-m-grp {
+ fsl,pins = <MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x400120b0>;
+ };
+
+ pinctrl_dhcom_n: dhcom-n-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x400120b0>;
+ };
+
+ pinctrl_dhcom_o: dhcom-o-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x400120b0>;
+ };
+
+ pinctrl_dhcom_p: dhcom-p-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x400120b0>;
+ };
+
+ pinctrl_dhcom_q: dhcom-q-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x400120b0>;
+ };
+
+ pinctrl_dhcom_r: dhcom-r-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0>;
+ };
+
+ pinctrl_dhcom_s: dhcom-s-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0>;
+ };
+
+ pinctrl_dhcom_t: dhcom-t-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x400120b0>;
+ };
+
+ pinctrl_dhcom_u: dhcom-u-grp {
+ fsl,pins = <MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x400120b0>;
+ };
+
+ pinctrl_dhcom_int: dhcom-int-grp {
+ fsl,pins = <MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x400120b0>;
+ };
+
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1
+ MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1
+ MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1
+ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */
+ >;
+ };
+
+ pinctrl_fec1: fec1-grp {
+ fsl,pins = <
+ /* FEC1 uses MDIO bus from FEC2 */
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
+ >;
+ };
+
+ pinctrl_fec1_phy: fec1-phy-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */
+ >;
+ };
+
+ pinctrl_fec2: fec2-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
+ >;
+ };
+
+ pinctrl_fec2_phy: fec2-phy-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif: lcdif-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ >;
+ };
+
+ pinctrl_pwm1: pwm1-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_sai2: sai2-grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
+ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
+ >;
+ };
+
+ pinctrl_tsc: tsc-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart6: uart6-grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
+ MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
+ MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
+ MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usbotg2: usbotg2-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */
+ >;
+ };
+};
+
+&iomuxc_snvs {
+ /* DHCOM GPIOs A..H */
+ pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0>;
+ };
+
+ pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0>;
+ };
+
+ pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0>;
+ };
+
+ pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0>;
+ };
+
+ pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0>;
+ };
+
+ pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0>;
+ };
+
+ pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0>;
+ };
+
+ pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp {
+ fsl,pins = <MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0>;
+ };
+
+ pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */
+ >;
+ };
+
+ pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi
new file mode 100644
index 000000000000..5882c7565f64
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2023 DH electronics GmbH
+ */
+
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "imx6ull.dtsi"
+
+/ {
+ memory@80000000 {
+ /* Appropriate memory size will be filled by U-Boot */
+ reg = <0x80000000 0>;
+ device_type = "memory";
+ };
+};
+
+&cpu0 {
+ /*
+ * Due to the design as a solderable SOM, there are no capacitors
+ * below the SoC, therefore higher voltages are required.
+ */
+ operating-points = <
+ /* kHz uV */
+ 900000 1275000
+ 792000 1250000 /* Voltage increased */
+ 528000 1175000
+ 396000 1025000
+ 198000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 900000 1250000
+ 792000 1250000 /* Voltage increased */
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+};
+
+&gpio1 {
+ pinctrl-0 = <&pinctrl_spi1_switch>;
+ pinctrl-names = "default";
+ /*
+ * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the
+ * DHCOM SPI1 interface or accessing the SPI bootflash. Both using
+ * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
+ * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins
+ * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for
+ * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they
+ * are used for the bus interface to the SPI bootflash. The GPIOs are
+ * disconnected by a buffer which is also controlled via the pin
+ * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a
+ * special case and is disabled by setting GPIO 1.9 to high.
+ */
+ spi1-switch-hog {
+ gpio-hog;
+ gpios = <9 0>;
+ output-high;
+ line-name = "spi1-switch";
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic@58 {
+ compatible = "dlg,da9061";
+ reg = <0x58>;
+
+ onkey {
+ compatible = "dlg,da9061-onkey", "dlg,da9062-onkey";
+ status = "disabled";
+ };
+
+ regulators {
+ vdd_soc_in_1v4: buck1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1400000>;
+ regulator-min-microvolt = <1400000>;
+ regulator-name = "vdd_soc_in_1v4";
+ };
+
+ vcc_3v3: buck2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_3v3";
+ };
+
+ /*
+ * The current DRR3 memory can be supplied with a
+ * voltage of either 1.35V or 1.5V. For reasons of
+ * backward compatibility to only 1.5V DDR3 memory,
+ * the voltage is set to 1.5V.
+ */
+ vcc_ddr_1v35: buck3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1500000>;
+ regulator-min-microvolt = <1500000>;
+ regulator-name = "vcc_ddr_1v35";
+ };
+
+ vcc_2v5: ldo1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microvolt = <2500000>;
+ regulator-name = "vcc_2v5";
+ };
+
+ vdd_snvs_in_3v3: ldo2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vdd_snvs_in_3v3";
+ };
+
+ vcc_1v8: ldo3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ };
+
+ vcc_1v2: ldo4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "vcc_1v2";
+ };
+ };
+
+ thermal {
+ compatible = "dlg,da9061-thermal", "dlg,da9062-thermal";
+ status = "disabled";
+ };
+
+ watchdog {
+ compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
+ status = "disabled";
+ };
+ };
+};
+
+&ocotp {
+ /* Don't get write access by default */
+ read-only;
+};
+
+&reg_arm {
+ vin-supply = <&vdd_soc_in_1v4>;
+};
+
+&reg_soc {
+ vin-supply = <&vdd_soc_in_1v4>;
+};
+
+/* BT on LGA (BT_REG_ON is connected to LGA pin E1) */
+&uart2 {
+ pinctrl-0 = <&pinctrl_uart2>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ /*
+ * Actually, the maximum speed of the chip is 4MBdps, but there are
+ * limitations that prevent this speed. It hasn't yet been figured out
+ * what the reason for this is. Currently, the maximum speed of 3MBdps
+ * can be used without any problems. If the limitation can be overcome,
+ * the speed can be increased accordingly.
+ */
+ bluetooth: bluetooth {
+ compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */
+ max-speed = <3000000>;
+ vbat-supply = <&vcc_3v3>;
+ vddio-supply = <&vcc_3v3>;
+ };
+};
+
+/* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */
+&usdhc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ keep-power-in-suspend;
+ pinctrl-0 = <&pinctrl_usdhc1_wifi>;
+ pinctrl-names = "default";
+ wakeup-source;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */
+ reg = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+ >;
+ };
+
+ pinctrl_spi1_switch: spi1-switch-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x120b0 /* SPI_BOOT_FLASH_EN */
+ >;
+ };
+
+ pinctrl_uart2: uart2-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
+ MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1_wifi: usdhc1-wifi-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1b0b0
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10010
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x1b0b0
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x1b0b0
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x1b0b0
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-kontron-bl.dts b/arch/arm/boot/dts/imx6ull-kontron-bl.dts
new file mode 100644
index 000000000000..fa016465cdbc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-kontron-bl.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ull-kontron-sl.dtsi"
+#include "imx6ul-kontron-bl-common.dtsi"
+
+/ {
+ model = "Kontron BL i.MX6ULL (N641X S)";
+ compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts b/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts
deleted file mode 100644
index 57588a5e1e34..000000000000
--- a/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2019 Kontron Electronics GmbH
- */
-
-/dts-v1/;
-
-#include "imx6ull-kontron-n6411-som.dtsi"
-#include "imx6ul-kontron-n6x1x-s.dtsi"
-
-/ {
- model = "Kontron N6411 S";
- compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som",
- "fsl,imx6ull";
-};
diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi
deleted file mode 100644
index b7e984284e1a..000000000000
--- a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- */
-
-#include "imx6ull.dtsi"
-#include "imx6ul-kontron-n6x1x-som-common.dtsi"
-
-/ {
- model = "Kontron N6411 SOM";
- compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull";
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- device_type = "memory";
- };
-};
-
-&qspi {
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <104000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- reg = <0>;
-
- partition@0 {
- label = "ubi1";
- reg = <0x00000000 0x08000000>;
- };
-
- partition@8000000 {
- label = "ubi2";
- reg = <0x08000000 0x18000000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi b/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi
new file mode 100644
index 000000000000..93f10eb3494f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-kontron-sl-common.dtsi"
+
+/ {
+ model = "Kontron SL i.MX6ULL (N641X SOM)";
+ compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts
new file mode 100644
index 000000000000..14adb87da911
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Alexander Bauer <a.bauer@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull-phytec-tauri.dtsi"
+
+/ {
+ model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
+ compatible = "phytec,imx6ull-phygate-tauri",
+ "phytec,imx6ull-phygate-tauri-emmc",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+/* EMMC-Version */
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts
new file mode 100644
index 000000000000..ae396ac63443
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Alexander Bauer <a.bauer@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull-phytec-tauri.dtsi"
+
+/ {
+ model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
+ compatible = "phytec,imx6ull-phygate-tauri",
+ "phytec,imx6ull-phygate-tauri-nand",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+};
+
+/* NAND-Version */
+&gpmi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi
new file mode 100644
index 000000000000..5464a52a1f94
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Alexander Bauer <a.bauer@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-phytec-phycore-som.dtsi"
+
+/ {
+
+ model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
+ compatible = "phytec,imx6ull-phygate-tauri",
+ "phytec,imx6ull-pcl063", "fsl,imx6ull";
+
+ aliases {
+ rtc0 = &i2c_rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-key";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key {
+ label = "KEY-A";
+ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ wakeup-source;
+ };
+ };
+
+ reg_adc1_vref_3v3: regulator-vref-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_s25fl064_hold: regulator-s25fl064-hold {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_s25fl064_hold>;
+ compatible = "regulator-fixed";
+ regulator-name = "s25fl064_hold";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_hub_vbus: regulator-hub-otg1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhubpwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_hub_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1pwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ user_leds: user-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_user_leds>,
+ <&pinctrl_user_leds_snvs>;
+
+ user-led1 {
+ label = "yellow";
+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "off";
+ };
+
+ user-led2 {
+ label = "red";
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "off";
+ };
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>,
+ <&pinctrl_ecspi1_cs>;
+ cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>,
+ <&gpio3 10 GPIO_ACTIVE_LOW>,
+ <&gpio3 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm_tis: tpm@1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm>;
+ compatible = "tcg,tpm_tis-spi";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ s25fl064: flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = " jedec,spi-nor";
+ reg = <2>;
+ spi-max-frequency = <40000000>;
+ m25p,fast-read;
+ status = "disabled";
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ dmas = <&sdma 7 8 0>,
+ <&sdma 8 8 0>;
+ dma-names = "rx", "tx";
+ status = "okay";
+};
+
+&ethphy1 {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy2>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ tmp102: tmp@49 {
+ compatible = "ti,tmp102";
+ reg = <0x49>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tempsense>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ i2c_rtc: rtc@68 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_int>;
+ compatible = "microcrystal,rv4162";
+ reg = <0x68>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&mdio {
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <1>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ status = "okay";
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm6>;
+ status = "okay";
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm7>;
+ status = "okay";
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* UART4 * RS485 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ rs485-rts-active-high;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+/* UART5 * RS232 */
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7>;
+ status = "okay";
+};
+
+/* USB */
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usb_hub_vbus>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "disabled";
+};
+
+&iomuxc_snvs {
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
+ >;
+ };
+
+ pinctrl_stmpe: stmpegrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
+ >;
+ };
+
+ pinctrl_tempsense: tempsensegrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
+ >;
+ };
+
+ pinctrl_tpm: tpmgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
+ >;
+ };
+
+ pinctrl_usbhubpwr: usbhubpwrgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059
+ >;
+ };
+
+ pinctrl_user_leds_snvs: user_ledsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
+ >;
+ };
+};
+
+&iomuxc {
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */
+ MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1
+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1
+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1csgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
+ MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0
+ MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0
+ >;
+ };
+
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0
+ MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0
+ >;
+ };
+
+ princtrl_flexcan2_en: flexcan2engrp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0
+ MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0
+ MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0
+ MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0
+ MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0
+ MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm6: pwm6grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm7: pwm7grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0
+ >;
+ };
+
+ pinctrl_s25fl064_hold: s25fl064holdgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
+ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
+ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
+ MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
+ MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1
+ MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80
+ >;
+ };
+
+ pinctrl_usbotg1pwr: usbotg1pwrgrp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_user_leds: userledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi
new file mode 100644
index 000000000000..3fdece5bd31f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi
@@ -0,0 +1,852 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright (C) 2023 chargebyte GmbH
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "imx6ull.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &usdhc2; /* eMMC */
+ };
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <&pinctrl_emmc_rst>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_dcdc_3v3: regulator-dcdc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "dcdc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ldo-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_status_leds>;
+
+ led-1 {
+ function = LED_FUNCTION_BOOT;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "timer";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_PROGRAMMING;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-3 {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_motor
+ &pinctrl_adc_cp
+ &pinctrl_adc_pp>;
+ vref-supply = <&vgen1_reg>;
+ status = "okay";
+};
+
+&cpu0 {
+ clock-frequency = <792000000>;
+};
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ num-cs = <3>;
+ cs-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH
+ &gpio3 2 GPIO_ACTIVE_HIGH
+ &gpio3 4 GPIO_ACTIVE_HIGH>;
+};
+
+&ecspi4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ num-cs = <1>;
+ cs-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1
+ &pinctrl_enet1_phy_rst
+ &pinctrl_enet_mdio>;
+ phy-supply = <&reg_dcdc_3v3>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <25>;
+ phy-handle = <&ethphy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1_phy_int>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ interrupts-extended = <&gpio2 7 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ max-speed = <100>;
+ smsc,disable-energy-detect;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "", /* 5 */
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "CP_INVERT",
+ "",
+ "", /* 15 */
+ "",
+ "",
+ "",
+ "MOTOR_1_FAULT_N",
+ "", /* 20 */
+ "",
+ "ROTARY_SWITCH_1_2_N",
+ "ROTARY_SWITCH_1_4_N",
+ "ROTARY_SWITCH_1_8_N",
+ "MOTOR_2_FAULT_N"; /* 25 */
+};
+
+&gpio3 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "", /* 5 */
+ "EXT_GPIO",
+ "MOTOR_1_DRIVER_IN1_N",
+ "MOTOR_1_DRIVER_IN2",
+ "MOTOR_2_DRIVER_IN1",
+ "STM32_BOOT0", /* 10 */
+ "STM32_RST_N",
+ "RELAY_1_ENABLE",
+ "RELAY_2_ENABLE",
+ "",
+ "", /* 15 */
+ "QCA700X_MAINS_BOOTLOADER_N",
+ "QCA700X_CP_RST_N",
+ "QCA700X_CP_BOOTLOADER_N",
+ "",
+ "DIGITAL_OUT_1", /* 20 */
+ "DIGITAL_OUT_2",
+ "DIGITAL_OUT_3",
+ "DIGITAL_OUT_4",
+ "DIGITAL_OUT_5",
+ "DIGITAL_OUT_6", /* 25 */
+ "ROTARY_SWITCH_2_8_N",
+ "ROTARY_SWITCH_2_4_N",
+ "ROTARY_SWITCH_2_2_N";
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "", /* 5 */
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "BOARD_VARIANT_1",
+ "BOARD_VARIANT_2",
+ "BOARD_VARIANT_0", /* 15 */
+ "BOARD_VARIANT_3",
+ "",
+ "ROTARY_SWITCH_2_1_N",
+ "",
+ "DIGITAL_IN_5", /* 20 */
+ "",
+ "",
+ "DIGITAL_IN_6",
+ "",
+ "DIGITAL_IN_1", /* 25 */
+ "DIGITAL_IN_2",
+ "DIGITAL_IN_4",
+ "DIGITAL_IN_3";
+
+ pmic-int-hog {
+ gpio-hog;
+ gpios = <19 0>;
+ input;
+ };
+};
+
+&gpio5 {
+ gpio-line-names = "ROTARY_SWITCH_1_1_N", /* 0 */
+ "",
+ "RELAY_2_SENSE",
+ "RELAY_1_SENSE",
+ "",
+ "", /* 5 */
+ "",
+ "QCA700X_MAINS_RST_N",
+ "MOTOR_2_DRIVER_IN2",
+ "",
+ "CP_POSITIVE_PEAK_RST", /* 10 */
+ "CP_NEGATIVE_PEAK_RST";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pfuze3001: pmic@8 {
+ compatible = "fsl,pfuze3001";
+ reg = <0x08>;
+
+ regulators {
+ sw1_reg: sw1 {
+ regulator-name = "SW1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw2_reg: sw2 {
+ regulator-name = "SW2";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3_reg: sw3 {
+ regulator-name = "SW3";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-name = "VSNVS";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-name = "VLDO1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-name = "VLDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-name = "VCCSD";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-name = "V33";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-name = "VLDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-name = "VLDO4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ onewire@18 {
+ compatible = "maxim,ds2484";
+ reg = <0x18>;
+ };
+
+ accelerometer@19 {
+ compatible = "st,iis328dq", "st,h3lis331dl-accel";
+ reg = <0x19>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accelerometer_int1_snvs>;
+ vdd-supply = <&reg_dcdc_3v3>;
+ vddio-supply = <&reg_dcdc_3v3>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_board_var
+ &pinctrl_digital_input
+ &pinctrl_digital_output
+ &pinctrl_gpio_motor
+ &pinctrl_hog_pins
+ &pinctrl_rotary_switch1
+ &pinctrl_rotary_switch2>;
+
+ pinctrl_adc_cp: adc-cpgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ >;
+ };
+
+ pinctrl_adc_motor: adc-motorgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_adc_pp: adc-ppgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0
+ >;
+ };
+
+ pinctrl_board_var: board-vargrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_CLE__GPIO4_IO15 0xb0
+ MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0xb0
+ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0xb0
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0
+ >;
+ };
+
+ pinctrl_digital_input: digital-inputgrp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0xb0
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0xb0
+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0xb0
+ MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0xb0
+ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0xb0
+ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0xb0
+ >;
+ };
+
+ pinctrl_digital_output: digital-outputgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x400000b0
+ MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x400000b0
+ MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x400000b0
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x400000b0
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x400000b0
+ MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x400000b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0
+ MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0xb0
+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xb0
+ MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x10b0
+ MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x10b0
+ MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x10b0
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0
+ MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x10b0
+ MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x10b0
+ MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x10b0
+ >;
+ };
+
+ pinctrl_emmc_rst: emmc-rstgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x400010b0
+ >;
+ };
+
+ pinctrl_enet_mdio: enet-mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10b0
+ >;
+ };
+
+ pinctrl_enet1_phy_int: enet1-phy-intgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x100b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x100b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0xb0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0xb0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0xb0
+ >;
+ };
+
+ pinctrl_ext_uart: ext-uartgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0xb0
+ MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0xb0
+ >;
+ };
+
+ pinctrl_fan_enable: fan-enablegrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x400000b0
+ >;
+ };
+
+ pinctrl_gpio_motor: gpio-motorgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x400000b0
+ MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x400000b0
+ MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x400000b0
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0xb0
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0xb0
+ >;
+ };
+
+ pinctrl_hog_pins: hog-pinsgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x400000b0
+ MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x400000b0
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x400070a0
+ MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x400000b0
+ MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x400000b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x400008b0
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x400008b0
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x400008b0
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x400008b0
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x70b1
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0xb0
+ >;
+ };
+
+ pinctrl_pwm_cp: pinctrl-pwm-cpgrp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x60a0
+ >;
+ };
+
+ pinctrl_pwm_digital_input_ref: pwm-digital-input-refgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0xb0
+ >;
+ };
+
+ pinctrl_pwm_fan: pwm-fangrp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x60a0
+ >;
+ };
+
+ pinctrl_qca700x_cp_btld: qca700x-cp-btldgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x400000b0
+ >;
+ };
+
+ pinctrl_qca700x_cp_int: qca700x-cp-intgrp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x10b0
+ >;
+ };
+
+ pinctrl_qca700x_cp_rst: qca700x-cp-rstgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x400000b0
+ >;
+ };
+
+ pinctrl_qca700x_mains_btld: qca700x-mains-btldgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x400000b0
+ >;
+ };
+
+ pinctrl_rotary_switch1: rotary-switch1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0xb0
+ MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0xb0
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0xb0
+ >;
+ };
+
+ pinctrl_rotary_switch2: rotary-switch2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0xb0
+ MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0xb0
+ MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0xb0
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0xb0
+ >;
+ };
+
+ pinctrl_rs485_1: rs485-1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0xb0
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0xb0
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0xb0
+ >;
+ };
+
+ pinctrl_rs485_2: rs485-2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0
+ MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x10b0
+ MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x10b0
+ >;
+ };
+
+ pinctrl_status_leds: status-ledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0xb0
+ MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0xb0
+ MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0xb0
+ >;
+ };
+
+ pinctrl_stm32: stm32grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x10b0
+ MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x10b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0xb0
+ MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0xb0
+ >;
+ };
+
+ pinctrl_usb: usbgrp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x70b0
+ MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x70b0
+ >;
+ };
+
+ pinctrl_usb_pwr: usb-pwrgrp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0xb0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x7071
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x7071
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x7071
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x7071
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x7071
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x7071
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x7071
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x7071
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x7071
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x7071
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70b1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70b1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70b1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70b1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70b1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70b1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70b1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70b1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70b1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70b1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70f1
+ >;
+ };
+
+ pinctrl_wdog2: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x10b0
+ >;
+ };
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default_snvs";
+ pinctrl-0 = <&pinctrl_cp_peak_snvs
+ &pinctrl_gpio_motor_snvs
+ &pinctrl_relay_sense_snvs
+ &pinctrl_rotary_switch1_snvs>;
+
+ pinctrl_accelerometer_int1_snvs: accelerometer-int1-snvsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x130a0
+ >;
+ };
+
+ pinctrl_cp_peak_snvs: cp-peak-snvsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x130a0
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
+ >;
+ };
+
+ pinctrl_enet1_phy_rst: enet1-phy-rstgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x100a0
+ >;
+ };
+
+ pinctrl_fan_sense_snvs: fan-sense-snvsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x100a0
+ >;
+ };
+
+ pinctrl_gpio_motor_snvs: gpio-motor-snvsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0
+ >;
+ };
+
+ pinctrl_qca700x_mains_int: qca700x-mains-intgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x130a0
+ >;
+ };
+
+ pinctrl_qca700x_mains_rst: qca700x-mains-rstgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400100a0
+ >;
+ };
+
+ pinctrl_relay_sense_snvs: relay-sense-snvsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x100a0
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x100a0
+ >;
+ };
+
+ pinctrl_rotary_switch1_snvs: rotary-switch1-snvsgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x110a0
+ >;
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_digital_input_ref>;
+ status = "okay";
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_cp>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rs485_1>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ fsl,dte-mode;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rs485_2>;
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_stm32>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ext_uart>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb
+ &pinctrl_usb_pwr>;
+ dr_mode = "host";
+ power-active-high;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbphy1 {
+ fsl,tx-cal-45-dn-ohms = <35>;
+ fsl,tx-cal-45-dp-ohms = <35>;
+};
+
+&usbphy2 {
+ fsl,tx-cal-45-dn-ohms = <35>;
+ fsl,tx-cal-45-dp-ohms = <35>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <&sw2_reg>;
+ vqmmc-supply = <&reg_1v8>;
+ mmc-pwrseq = <&emmc_pwrseq>;
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&wdog2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog2>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/imx6ull-tarragon-master.dts
new file mode 100644
index 000000000000..67007ce383e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tarragon-master.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright (C) 2023 chargebyte GmbH
+
+#include "imx6ull-tarragon-common.dtsi"
+
+/ {
+ model = "chargebyte Tarragon Master";
+ compatible = "chargebyte,imx6ull-tarragon-master", "fsl,imx6ull";
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fan_sense_snvs>;
+ fan-supply = <&reg_fan>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ reg_fan: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "fan-supply";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fan_enable>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+};
+
+&ecspi2 {
+ status = "okay";
+
+ qca700x_cp: ethernet@0 {
+ reg = <0x0>;
+ compatible = "qca,qca7000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qca700x_cp_int
+ &pinctrl_qca700x_cp_rst
+ &pinctrl_qca700x_cp_btld>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <19 IRQ_TYPE_EDGE_RISING>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <16000000>;
+ };
+};
+
+&ecspi4 {
+ status = "okay";
+
+ qca700x_mains: ethernet@0 {
+ reg = <0x0>;
+ compatible = "qca,qca7000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qca700x_mains_int
+ &pinctrl_qca700x_mains_rst
+ &pinctrl_qca700x_mains_btld>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <9 IRQ_TYPE_EDGE_RISING>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <16000000>;
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_fan>;
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-tarragon-micro.dts b/arch/arm/boot/dts/imx6ull-tarragon-micro.dts
new file mode 100644
index 000000000000..e471c2005bee
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tarragon-micro.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright (C) 2023 chargebyte GmbH
+
+#include "imx6ull-tarragon-common.dtsi"
+
+/ {
+ model = "chargebyte Tarragon Micro";
+ compatible = "chargebyte,imx6ull-tarragon-micro", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/imx6ull-tarragon-slave.dts
new file mode 100644
index 000000000000..cee223b5f8e1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tarragon-slave.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright (C) 2023 chargebyte GmbH
+
+#include "imx6ull-tarragon-common.dtsi"
+
+/ {
+ model = "chargebyte Tarragon Slave";
+ compatible = "chargebyte,imx6ull-tarragon-slave", "fsl,imx6ull";
+};
+
+&ecspi2 {
+ status = "okay";
+
+ qca700x_cp: ethernet@0 {
+ reg = <0x0>;
+ compatible = "qca,qca7000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qca700x_cp_int
+ &pinctrl_qca700x_cp_rst
+ &pinctrl_qca700x_cp_btld>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <19 IRQ_TYPE_EDGE_RISING>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <16000000>;
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts
new file mode 100644
index 000000000000..7fd53b7a4372
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright (C) 2023 chargebyte GmbH
+
+#include "imx6ull-tarragon-common.dtsi"
+
+/ {
+ model = "chargebyte Tarragon SlaveXT";
+ compatible = "chargebyte,imx6ull-tarragon-slavext", "fsl,imx6ull";
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fan_sense_snvs>;
+ fan-supply = <&reg_fan>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ reg_fan: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "fan-supply";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fan_enable>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+};
+
+&ecspi2 {
+ status = "okay";
+
+ qca700x_cp: ethernet@0 {
+ reg = <0x0>;
+ compatible = "qca,qca7000";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qca700x_cp_int
+ &pinctrl_qca700x_cp_rst
+ &pinctrl_qca700x_cp_btld>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <19 IRQ_TYPE_EDGE_RISING>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <16000000>;
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_fan>;
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts
new file mode 100644
index 000000000000..e593b7036fc7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ull-tqma6ull2.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board";
+ compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi
new file mode 100644
index 000000000000..8541cb3f3b3e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulx-common.dtsi"
+
+/ {
+ model = "TQ-Systems TQMa6ULL2 SoM";
+ compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
+};
+
+&usdhc2 {
+ fsl,tuning-step = <6>;
+ /* Errata ERR010450 Workaround */
+ max-frequency = <99000000>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts
new file mode 100644
index 000000000000..33437aae9822
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ull-tqma6ull2l.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+ model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board";
+ compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi
new file mode 100644
index 000000000000..be593d47e3b1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulxl-common.dtsi"
+
+/ {
+ model = "TQ Systems TQMa6ULL2L SoM";
+ compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
+};
+
+&usdhc2 {
+ fsl,tuning-step = <6>;
+ /* Errata ERR010450 Workaround */
+ max-frequency = <99000000>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+};
+
+&iomuxc {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
+ /* rst */
+ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 9bf67490ac49..2bccd45e9fc2 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -50,7 +50,7 @@
};
/ {
- soc {
+ soc: soc {
aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts
index 59bcfc9a6b10..c92e4e2f6ab9 100644
--- a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts
+++ b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts
@@ -29,6 +29,10 @@
status = "okay";
};
+&snvs_poweroff {
+ status = "okay";
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
index b770fc937970..01612741f792 100644
--- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
@@ -1,169 +1,80 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017-2020 Toradex AG
- *
+ * Copyright 2017-2022 Toradex
*/
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpiokeys>;
-
- power {
- label = "Wake-Up";
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- panel: panel {
- compatible = "edt,et057090dhu";
- backlight = <&bl>;
- power-supply = <&reg_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_5v0: regulator-5v0 {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usbh_vbus: regulator-usbh-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh_reg>;
- regulator-name = "VCC_USB[1-4]";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
- vin-supply = <&reg_5v0>;
- };
-};
-
+/* Colibri AD0 to AD3 */
&adc1 {
status = "okay";
};
-/*
- * ADC2 is not available on the Aster board and
- * conflicts with AD7879 resistive touchscreen.
- */
-&adc2 {
- status = "disabled";
-};
-
-&bl {
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- power-supply = <&reg_3v3>;
+/* Colibri SSP */
+&ecspi3 {
+ cs-gpios = <
+ &gpio4 11 GPIO_ACTIVE_LOW /* SODIMM 86 / regular SSPFRM as UNO_SPI_CS or */
+ &gpio4 23 GPIO_ACTIVE_LOW /* SODIMM 65 / already muxed pinctrl_gpio2 as SPI_CE0_N */
+ &gpio4 22 GPIO_ACTIVE_LOW /* SODIMM 85 / already muxed pinctrl_gpio2 as SPI_CE1_N */
+ >;
status = "okay";
};
+/* Colibri Fast Ethernet */
&fec1 {
status = "okay";
};
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
status = "okay";
-
- /* Microchip/Atmel maxtouch controller */
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpiotouch>;
- reg = <0x4a>;
- interrupt-parent = <&gpio2>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
- reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 */
- };
-
- /* M41T0M6 real time clock on carrier board */
- rtc: rtc@68 {
- compatible = "st,m41t0";
- reg = <0x68>;
- };
-};
-
-&iomuxc {
- pinctrl_gpiotouch: touchgpios {
- fsl,pins = <
- MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74
- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14
- >;
- };
-};
-
-&lcdif {
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
};
+/* Colibri PWM<A> */
&pwm1 {
status = "okay";
};
+/* Colibri PWM<B> */
&pwm2 {
status = "okay";
};
+/* Colibri PWM<C> */
&pwm3 {
status = "okay";
};
+/* Colibri PWM<D> */
&pwm4 {
status = "okay";
};
+/* M41T0M6 real time clock */
+&rtc {
+ status = "okay";
+};
+
+/* Colibri UART_A */
&uart1 {
status = "okay";
};
+/* Colibri UART_B */
&uart2 {
status = "okay";
};
+/* Colibri UART_C */
&uart3 {
status = "okay";
};
+/* Colibri USBC */
&usbotg1 {
+ disable-over-current;
status = "okay";
};
+/* Colibri MMC/SD */
&usdhc1 {
- keep-power-in-suspend;
- no-1-8-v;
- wakeup-source;
- vmmc-supply = <&reg_3v3>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 3b9df8c82ae3..326440f2b4f4 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -1,194 +1,111 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
*/
/ {
- aliases {
- rtc0 = &rtc;
- rtc1 = &snvs_rtc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- /* fixed crystal dedicated to mpc258x */
+ /* Fixed crystal dedicated to MCP2515. */
clk16m: clk16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpiokeys>;
-
- power {
- label = "Wake-Up";
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- panel: panel {
- compatible = "edt,et057090dhu";
- backlight = <&bl>;
- power-supply = <&reg_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_5v0: regulator-5v0 {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usbh_vbus: regulator-usbh-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh_reg>;
- regulator-name = "VCC_USB[1-4]";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
- vin-supply = <&reg_5v0>;
- };
-};
-
-&bl {
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- power-supply = <&reg_3v3>;
-
- status = "okay";
};
+/* Colibri AD0 to AD3 */
&adc1 {
status = "okay";
};
-&adc2 {
- status = "okay";
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */
+ pinctrl-0 = <&pinctrl_atmel_adapter>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */
+ status = "disabled";
};
+/* Colibri SSP */
&ecspi3 {
status = "okay";
mcp2515: can@0 {
+ clocks = <&clk16m>;
compatible = "microchip,mcp2515";
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
reg = <0>;
- clocks = <&clk16m>;
- interrupt-parent = <&gpio5>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
vdd-supply = <&reg_3v3>;
xceiver-supply = <&reg_5v0>;
- status = "okay";
};
};
+/* Colibri Fast Ethernet */
&fec1 {
status = "okay";
};
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
status = "okay";
-
- /*
- * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
- * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
- */
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpiotouch>;
- reg = <0x4a>;
- interrupt-parent = <&gpio1>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
- reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */
- status = "disabled";
- };
-
- /* M41T0M6 real time clock on carrier board */
- rtc: rtc@68 {
- compatible = "st,m41t0";
- reg = <0x68>;
- };
-};
-
-&lcdif {
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
};
+/* Colibri PWM<A> */
&pwm1 {
status = "okay";
};
+/* Colibri PWM<B> */
&pwm2 {
+ /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
status = "okay";
};
+/* Colibri PWM<C> */
&pwm3 {
+ /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
status = "okay";
};
+/* Colibri PWM<D> */
&pwm4 {
status = "okay";
};
+/* M41T0M6 real time clock */
+&rtc {
+ status = "okay";
+};
+
+/* Colibri UART_A */
&uart1 {
status = "okay";
};
+/* Colibri UART_B */
&uart2 {
status = "okay";
};
+/* Colibri UART_C */
&uart3 {
status = "okay";
};
+/* Colibri USBC */
&usbotg1 {
+ disable-over-current;
status = "okay";
};
+/* Colibri MMC/SD */
&usdhc1 {
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <&reg_3v3>;
status = "okay";
};
-
-&iomuxc {
- pinctrl_gpiotouch: touchgpios {
- fsl,pins = <
- MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74
- MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
- >;
- };
-};
diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi
new file mode 100644
index 000000000000..b687727f956a
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/ {
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3v3_vmmc";
+ startup-delay-us = <100>;
+ };
+};
+
+/* Colibri AD0 to AD3 */
+&adc1 {
+ status = "okay";
+};
+
+/* Colibri SSP */
+&ecspi3 {
+ status = "okay";
+};
+
+/* Colibri Fast Ethernet */
+&fec1 {
+ status = "okay";
+};
+
+&gpio2 {
+ /*
+ * uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to
+ * turn the transceiver off, that property has to be deleted and the gpio handled in
+ * userspace.
+ * The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on.
+ */
+ uart-b-c-on-x14-enable-hog {
+ gpio-hog;
+ gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
+ output-high;
+ };
+};
+
+&gpio5 {
+ uart-a-on-x13-enable-hog {
+ gpio-hog;
+ gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
+ output-high;
+ };
+};
+
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
+&i2c4 {
+ status = "okay";
+};
+
+/* Colibri PWM<A> */
+&pwm1 {
+ status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+ status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+ status = "okay";
+};
+
+/* Colibri PWM<D> */
+&pwm4 {
+ status = "okay";
+};
+
+/* M41T0M6 real time clock */
+&rtc {
+ status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+ status = "okay";
+};
+
+/* Colibri UART_B */
+&uart2 {
+ status = "okay";
+};
+
+/* Colibri UART_C */
+&uart3 {
+ status = "okay";
+};
+
+/* Colibri USBC */
+&usbotg1 {
+ disable-over-current;
+ status = "okay";
+};
+
+/* Colibri MMC/SD, UHS-I capable uSD slot */
+&usdhc1 {
+ cap-power-off-card;
+ /delete-property/ keep-power-in-suspend;
+ /delete-property/ no-1-8-v;
+ vmmc-supply = <&reg_3v3_vmmc>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/imx7-colibri-iris.dtsi
new file mode 100644
index 000000000000..6a9e5ab59691
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri-iris.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/* Colibri AD0 to AD3 */
+&adc1 {
+ status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */
+ pinctrl-0 = <&pinctrl_atmel_adapter>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */
+};
+
+/* Colibri SSP */
+&ecspi3 {
+ status = "okay";
+};
+
+/* Colibri Fast Ethernet */
+&fec1 {
+ status = "okay";
+};
+
+&gpio2 {
+ /*
+ * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the
+ * transceiver off, that property has to be deleted and the gpio handled in userspace.
+ * The same applies to uart1_tx_on where the UART1 transceiver is turned on.
+ */
+ uart25-tx-on-hog {
+ gpio-hog;
+ gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
+ output-high;
+ };
+};
+
+&gpio5 {
+ uart1-tx-on-hog {
+ gpio-hog;
+ gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
+ output-high;
+ };
+};
+
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
+&i2c4 {
+ status = "okay";
+};
+
+/* Colibri PWM<A> */
+&pwm1 {
+ status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+ /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+ /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri PWM<D> */
+&pwm4 {
+ status = "okay";
+};
+
+/* M41T0M6 real time clock */
+&rtc {
+ status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+ status = "okay";
+};
+
+/* Colibri UART_B */
+&uart2 {
+ status = "okay";
+};
+
+/* Colibri UART_C */
+&uart3 {
+ status = "okay";
+};
+
+/* Colibri USBC */
+&usbotg1 {
+ disable-over-current;
+ status = "okay";
+};
+
+/* Colibri MMC/SD */
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index f1c60b0cb143..104580d51d74 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -1,96 +1,197 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
*/
+#include <dt-bindings/pwm/pwm.h>
+
/ {
- bl: backlight {
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ backlight: backlight {
+ brightness-levels = <0 45 63 88 119 158 203 255>;
compatible = "pwm-backlight";
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
- pwms = <&pwm1 0 5000000 0>;
- enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ power-supply = <&reg_module_3v3>;
+ pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
+ status = "disabled";
};
- reg_module_3v3: regulator-module-3v3 {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ extcon_usbc_det: usbc-det {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbc_det>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+
+ key-wakeup {
+ debounce-interval = <10>;
+ gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ panel_dpi: panel-dpi {
+ backlight = <&backlight>;
+ compatible = "edt,et057090dhu";
+ power-supply = <&reg_3v3>;
+ status = "disabled";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
- regulator-name = "+V3.3";
- regulator-min-microvolt = <3300000>;
+ regulator-always-on;
regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V";
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "5V";
+ };
+
+ reg_module_3v3: regulator-module-3v3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3";
};
reg_module_3v3_avdd: regulator-module-3v3-avdd {
compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_AVDD_AUDIO";
+ };
+
+ reg_module_3v3_eth: regulator-module-3v3-eth {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <200000>;
+ regulator-name = "+V3.3_ETH";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <200000>;
+ vin-supply = <&reg_LDO1>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "VCC_USB[1-4]";
+ vin-supply = <&reg_5v0>;
};
sound {
compatible = "simple-audio-card";
- simple-audio-card,name = "imx7-sgtl5000";
- simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,name = "imx7-sgtl5000";
+
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
- sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
+ sound-dai = <&codec>;
};
};
};
+/* Colibri AD0 to AD3 */
&adc1 {
vref-supply = <&reg_DCDC3>;
};
-&adc2 {
- vref-supply = <&reg_DCDC3>;
-};
+/* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */
&cpu0 {
cpu-supply = <&reg_DCDC2>;
};
+/* Colibri SSP */
&ecspi3 {
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
- cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
};
+/* Colibri Fast Ethernet */
&fec1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_enet1>;
- pinctrl-1 = <&pinctrl_enet1_sleep>;
- clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
- <&clks IMX7D_ENET_AXI_ROOT_CLK>,
- <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
- <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
- clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
- assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
- <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
- phy-mode = "rmii";
- phy-supply = <&reg_LDO1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+ clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
fsl,magic-packet;
+ phy-handle = <&ethphy0>;
+ phy-mode = "rmii";
+ phy-supply = <&reg_module_3v3_eth>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_enet1>;
+ pinctrl-1 = <&pinctrl_enet1_sleep>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Micrel KSZ8041RNL */
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ max-speed = <100>;
+ micrel,led-mode = <0>;
+ reg = <0>;
+ };
+ };
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
- status = "disabled";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
- status = "disabled";
};
&gpio1 {
@@ -271,14 +372,16 @@
"SODIMM_137";
};
+/* NAND on such SKUs */
&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
- nand-on-flash-bbt;
nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
};
+/* On-module Power I2C */
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
@@ -286,33 +389,33 @@
pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
status = "okay";
codec: sgtl5000@a {
- compatible = "fsl,sgtl5000";
#sound-dai-cells = <0>;
- reg = <0x0a>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
+ compatible = "fsl,sgtl5000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1_mclk>;
+ reg = <0xa>;
VDDA-supply = <&reg_module_3v3_avdd>;
- VDDIO-supply = <&reg_module_3v3>;
VDDD-supply = <&reg_DCDC3>;
+ VDDIO-supply = <&reg_module_3v3>;
};
- ad7879@2c {
+ ad7879_ts: touchscreen@2c {
+ adi,acquisition-time = /bits/ 8 <1>;
+ adi,averaging = /bits/ 8 <1>;
+ adi,conversion-interval = /bits/ 8 <255>;
+ adi,first-conversion-delay = /bits/ 8 <3>;
+ adi,median-filter-size = /bits/ 8 <2>;
+ adi,resistance-plate-x = <120>;
compatible = "adi,ad7879-1";
- reg = <0x2c>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0x2c>;
touchscreen-max-pressure = <4096>;
- adi,resistance-plate-x = <120>;
- adi,first-conversion-delay = /bits/ 8 <3>;
- adi,acquisition-time = /bits/ 8 <1>;
- adi,median-filter-size = /bits/ 8 <2>;
- adi,averaging = /bits/ 8 <1>;
- adi,conversion-interval = /bits/ 8 <255>;
+ status = "disabled";
};
pmic@33 {
@@ -320,71 +423,81 @@
reg = <0x33>;
regulators {
- reg_DCDC1: DCDC1 { /* V1.0_SOC */
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
+ reg_DCDC1: DCDC1 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-name = "+V1.0_SOC";
};
- reg_DCDC2: DCDC2 { /* V1.1_ARM */
- regulator-min-microvolt = <975000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
+ reg_DCDC2: DCDC2 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <975000>;
+ regulator-name = "+V1.1_ARM";
};
- reg_DCDC3: DCDC3 { /* V1.8 */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
+ reg_DCDC3: DCDC3 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8";
};
- reg_DCDC4: DCDC4 { /* V1.35_DRAM */
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
+ reg_DCDC4: DCDC4 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-name = "+V1.35_DRAM";
};
- reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
+ reg_LDO1: LDO1 {
regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "PWR_EN_+V3.3_ETH";
};
- reg_LDO2: LDO2 { /* +V1.8_SD */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
+ reg_LDO2: LDO2 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_SD";
};
- reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
+ reg_LDO3: LDO3 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "PWR_EN_+V3.3_LPSR";
};
- reg_LDO4: LDO4 { /* V1.8_LPSR */
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
+ reg_LDO4: LDO4 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_LPSR";
};
- reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
+ reg_LDO5: LDO5 {
regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "PWR_EN_+V3.3";
};
};
};
};
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
@@ -392,36 +505,69 @@
pinctrl-1 = <&pinctrl_i2c4_recovery>;
scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "disabled";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_atmel_connector>;
+ reg = <0x4a>;
+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
+ status = "disabled";
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ status = "disabled";
+ };
};
&lcdif {
+ assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
+ status = "disabled";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
};
+/* Colibri PWM<A> */
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
+/* Colibri PWM<B> */
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
};
+/* Colibri PWM<C> */
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
};
+/* Colibri PWM<D> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
&reg_1p0d {
- vin-supply = <&reg_DCDC3>;
+ vin-supply = <&reg_DCDC3>; /* VDDA_1P8_IN */
};
&sai1 {
@@ -430,237 +576,257 @@
status = "okay";
};
+/* Colibri UART_A */
&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
- uart-has-rtscts;
fsl,dte-mode;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
+ uart-has-rtscts;
};
+/* Colibri UART_B */
&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
- uart-has-rtscts;
fsl,dte-mode;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
};
+/* Colibri UART_C */
&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
fsl,dte-mode;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
};
+/* Colibri USBC */
&usbotg1 {
- dr_mode = "host";
+ dr_mode = "otg";
+ extcon = <0>, <&extcon_usbc_det>;
};
+/* Colibri MMC/SD */
&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
disable-wp;
+ no-1-8-v;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
+ pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>;
+ vmmc-supply = <&reg_3v3>;
vqmmc-supply = <&reg_LDO2>;
+ wakeup-source;
};
+/* eMMC on 1GB (eMMC) SKUs */
&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
fsl,tuning-step = <2>;
- vmmc-supply = <&reg_module_3v3>;
- vqmmc-supply = <&reg_DCDC3>;
non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
sdhci-caps-mask = <0x80000000 0x0>;
+ vmmc-supply = <&reg_module_3v3>;
+ vqmmc-supply = <&reg_DCDC3>;
};
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
- &pinctrl_gpio7 &pinctrl_usbc_det>;
-
- pinctrl_gpio1: gpio1-grp {
- fsl,pins = <
- MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
- MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
- MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
- MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
- MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
- MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
- MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
- MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
- MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
- MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
- MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
- MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
- MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
- MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
- MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
- MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
- MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
- MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
- MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
- MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
- MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
- MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
- MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
- MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
- MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
- MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
- MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
- MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
- MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
- MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
- MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
- MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
- MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
- MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
- MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
- MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
- MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
- MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
- MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
- >;
- };
-
- pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
+
+ /*
+ * Atmel MXT touchsceen + Capacitive Touch Adapter
+ * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3.
+ * Don't use them simultaneously.
+ */
+ pinctrl_atmel_adapter: atmeladaptergrp {
fsl,pins = <
- MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
- MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
- MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
- MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
- MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
- MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
- MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
- MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
- MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
- MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
- MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */
+ MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */
>;
};
- pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
+ /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
+ pinctrl_atmel_connector: atmelconnectorgrp {
fsl,pins = <
- MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
- MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
- MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
- MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
- MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
- MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */
+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */
>;
};
- pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
+ pinctrl_can_int: canintgrp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
- MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
>;
};
- pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
+ pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
- MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
+ MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */
+ MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */
+ MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */
>;
};
- pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
+ pinctrl_ecspi3_cs: ecspi3csgrp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
- >;
- };
-
- pinctrl_can_int: can-int-grp {
- fsl,pins = <
- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
+ MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
-
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
MX7D_PAD_SD2_WP__ENET1_MDC 0x3
>;
};
- pinctrl_enet1_sleep: enet1sleepgrp {
+ pinctrl_enet1_sleep: enet1-sleepgrp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
-
- MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
+ MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
+ MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
>;
};
- pinctrl_ecspi3_cs: ecspi3-cs-grp {
+ pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
- MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
+ MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
+ MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
>;
};
- pinctrl_ecspi3: ecspi3-grp {
+ pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
- MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
- MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
- MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
>;
};
- pinctrl_flexcan1: flexcan1-grp {
+ pinctrl_gpio1: gpio1grp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
- MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
+ MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
+ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
+ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
+ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
+ MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
+ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
+ MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
+ MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
+ MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
+ MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
+ MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
+ MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
+ MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
+ MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
+ MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
+ MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
+ MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
+ MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
+ MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
+ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
+ MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
+ MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
+ MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
+ MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
+ MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
+ MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
+ MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
+ MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
+ MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
+ MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
+ MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
+ MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
+ MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
+ MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
+ MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
+ MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
+ MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
+ MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
>;
};
- pinctrl_flexcan2: flexcan2-grp {
+ pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */
fsl,pins = <
- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
+ MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
+ MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
+ MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
+ MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
+ MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
+ MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
+ MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
+ MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
+ MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
+ MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
+ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
+ >;
+ };
+
+ pinctrl_gpio3: gpio3grp { /* LCD 18-23 */
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
+ MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
+ MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
+ MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
+ MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
+ MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
+ >;
+ };
+
+ pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
+ MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
+ >;
+ };
+
+ pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
+ MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
>;
};
- pinctrl_gpio_bl_on: gpio-bl-on {
+ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
>;
};
- pinctrl_gpmi_nand: gpmi-nand-grp {
+ pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
- MX7D_PAD_SD3_CLK__NAND_CLE 0x71
- MX7D_PAD_SD3_CMD__NAND_ALE 0x71
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
- MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
- MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
+ MX7D_PAD_SD3_CLK__NAND_CLE 0x71
+ MX7D_PAD_SD3_CMD__NAND_ALE 0x71
MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
@@ -669,13 +835,21 @@
MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
+ MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
+ MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
>;
};
- pinctrl_i2c4: i2c4-grp {
+ pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
- MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
+ MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */
+ MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */
>;
};
@@ -686,155 +860,176 @@
>;
};
- pinctrl_lcdif_dat: lcdif-dat-grp {
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */
+ MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */
+ MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */
+ MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */
+ MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */
+ MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */
+ MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */
+ MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */
+ MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */
+ MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */
+ MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */
+ MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */
+ MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */
+ MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */
+ MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */
+ MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */
+ MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */
+ MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */
+ >;
+ };
+
+ pinctrl_lcdif_dat_24: lcdifdat24grp {
fsl,pins = <
- MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
- MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
- MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
- MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
- MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
- MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
- MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
- MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
- MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
- MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
- MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
- MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
- MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
- MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
- MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
- MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
- MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
- MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */
+ MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */
+ MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */
+ MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */
+ MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */
+ MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */
>;
};
- pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
- MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
- MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
- MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
- MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
- MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
- MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
+ MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */
+ MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */
+ MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */
+ MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */
>;
};
- pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+ pinctrl_lvds_transceiver: lvdstx {
fsl,pins = <
- MX7D_PAD_LCD_CLK__LCD_CLK 0x79
- MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
- MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
- MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
+ MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
+ MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
+ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
>;
};
- pinctrl_pwm1: pwm1-grp {
+ pinctrl_pwm1: pwm1grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
- MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4
+ MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */
+ MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */
>;
};
- pinctrl_pwm2: pwm2-grp {
+ pinctrl_pwm2: pwm2grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79
+ MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */
>;
};
- pinctrl_pwm3: pwm3-grp {
+ pinctrl_pwm3: pwm3grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79
+ MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */
>;
};
- pinctrl_pwm4: pwm4-grp {
+ pinctrl_pwm4: pwm4grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
- MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4
+ MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */
+ MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */
>;
};
- pinctrl_uart1: uart1-grp {
+ pinctrl_uart1: uart1grp {
fsl,pins = <
- MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
- MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
- MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
- MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
+ MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */
+ MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */
+ MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */
+ MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */
>;
};
- pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
+ pinctrl_uart1_ctrl1: uart1ctrl1grp {
fsl,pins = <
- MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
- MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
+ MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */
+ MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */
>;
};
- pinctrl_uart2: uart2-grp {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */
+ MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */
+ MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */
+ MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */
+ >;
+ };
+ pinctrl_uart3: uart3grp {
fsl,pins = <
- MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
- MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
- MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
- MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
+ MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */
+ MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */
>;
};
- pinctrl_uart3: uart3-grp {
+
+ pinctrl_usbc_det: usbcdetgrp {
fsl,pins = <
- MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
- MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
+ MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */
>;
};
- pinctrl_usbc_det: gpio-usbc-det {
+ pinctrl_usbh_reg: usbhreggrp {
fsl,pins = <
- MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
+ MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */
>;
};
- pinctrl_usbh_reg: gpio-usbh-vbus {
+ pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */
>;
};
- pinctrl_usdhc1: usdhc1-grp {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x59
- MX7D_PAD_SD1_CLK__SD1_CLK 0x19
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
- MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ /* Avoid backfeeding with removed card power. */
+ pinctrl_usdhc1_sleep: usdhc1-slpgrp {
fsl,pins = <
- MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
- MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
- MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
- MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
- MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
- MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x10
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x10
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
@@ -847,10 +1042,10 @@
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
@@ -863,10 +1058,10 @@
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
- MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
@@ -879,16 +1074,16 @@
>;
};
- pinctrl_sai1: sai1-grp {
+ pinctrl_sai1: sai1grp {
fsl,pins = <
- MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
- MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
+ MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
+ MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
>;
};
- pinctrl_sai1_mclk: sai1grp_mclk {
+ pinctrl_sai1_mclk: sai1mclkgrp {
fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
>;
@@ -899,23 +1094,35 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_lpsr>;
- pinctrl_gpio_lpsr: gpio1-grp {
+ pinctrl_cd_usdhc1: cdusdhc1grp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
- MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
+ MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */
+ >;
+ };
+
+ pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0
+ >;
+ };
+
+ pinctrl_gpio_lpsr: gpiolpsrgrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */
+ MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */
>;
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
+ MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */
>;
};
- pinctrl_i2c1: i2c1-grp {
+ pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
>;
};
@@ -926,16 +1133,10 @@
>;
};
- pinctrl_cd_usdhc1: usdhc1-cd-grp {
- fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
- >;
- };
-
- pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
+ pinctrl_uart1_ctrl2: uart1ctrl2grp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */
- MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */
+ MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */
+ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */
>;
};
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts
index f3f0537d5a37..00ab92e56da4 100644
--- a/arch/arm/boot/dts/imx7d-colibri-aster.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts
@@ -1,7 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017-2020 Toradex AG
- *
+ * Copyright 2017-2022 Toradex
*/
/dts-v1/;
@@ -10,11 +9,33 @@
/ {
model = "Toradex Colibri iMX7D on Aster Carrier Board";
- compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d",
+ compatible = "toradex,colibri-imx7d-aster",
+ "toradex,colibri-imx7d",
"fsl,imx7d";
};
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+/* Colibri USBH */
&usbotg2 {
- vbus-supply = <&reg_usbh_vbus>;
+ disable-over-current;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
index 20480276cb0e..d9c7045a55ba 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017-2020 Toradex AG
+ * Copyright 2017-2022 Toradex
*
*/
@@ -11,10 +11,13 @@
/ {
model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board";
compatible = "toradex,colibri-imx7d-emmc-aster",
- "toradex,colibri-imx7d-emmc", "fsl,imx7d";
+ "toradex,colibri-imx7d-emmc",
+ "toradex,colibri-imx7d",
+ "fsl,imx7d";
};
+/* Colibri USBH */
&usbotg2 {
- vbus-supply = <&reg_usbh_vbus>;
+ disable-over-current;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
index 8ee73c870b12..96b599439dde 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
*/
/dts-v1/;
@@ -10,10 +10,13 @@
/ {
model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx7d-emmc-eval-v3",
- "toradex,colibri-imx7d-emmc", "fsl,imx7d";
+ "toradex,colibri-imx7d-emmc",
+ "toradex,colibri-imx7d",
+ "fsl,imx7d";
};
+/* Colibri USBH */
&usbotg2 {
- vbus-supply = <&reg_usbh_vbus>;
+ disable-over-current;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts
new file mode 100644
index 000000000000..5eccb837b158
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri-emmc.dtsi"
+#include "imx7-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board";
+ compatible = "toradex,colibri-imx7d-emmc-iris-v2",
+ "toradex,colibri-imx7d-emmc",
+ "toradex,colibri-imx7d",
+ "fsl,imx7d";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+ disable-over-current;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts
new file mode 100644
index 000000000000..ae10e8a66ff1
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri-emmc.dtsi"
+#include "imx7-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board";
+ compatible = "toradex,colibri-imx7d-emmc-iris",
+ "toradex,colibri-imx7d-emmc",
+ "toradex,colibri-imx7d",
+ "fsl,imx7d";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+ disable-over-current;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
index af39e5370fa1..3740e34ef99f 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
@@ -1,18 +1,28 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
*/
#include "imx7d.dtsi"
#include "imx7-colibri.dtsi"
/ {
+ aliases {
+ /* Required to properly pass MAC addresses from bootloader. */
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
};
+&cpu1 {
+ cpu-supply = <&reg_DCDC2>;
+};
+
&gpio6 {
gpio-line-names = "",
"",
@@ -39,10 +49,14 @@
"SODIMM_34";
};
+/* Colibri USBH */
&usbotg2 {
+ disable-over-current;
dr_mode = "host";
+ vbus-supply = <&reg_usbh_vbus>;
};
+/* eMMC */
&usdhc3 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
index 87b132bcd272..33d787617db0 100644
--- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
*/
/dts-v1/;
@@ -9,11 +9,49 @@
/ {
model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3";
- compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d",
+ compatible = "toradex,colibri-imx7d-eval-v3",
+ "toradex,colibri-imx7d",
"fsl,imx7d";
};
+&ad7879_ts {
+ status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+ status = "disabled";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+ /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+ /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri USBH */
&usbotg2 {
- vbus-supply = <&reg_usbh_vbus>;
+ disable-over-current;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts
new file mode 100644
index 000000000000..afdb1d06c7f6
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri.dtsi"
+#include "imx7-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D on Iris V2 Carrier Board";
+ compatible = "toradex,colibri-imx7d-iris-v2",
+ "toradex,colibri-imx7d",
+ "fsl,imx7d";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map-hog {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
+
+&gpio7 {
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /* This turns the LVDS transceiver on */
+ lvds-power-on-hog {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+ disable-over-current;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/imx7d-colibri-iris.dts
new file mode 100644
index 000000000000..531b0b99bd5a
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-iris.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri.dtsi"
+#include "imx7-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D on Iris Carrier Board";
+ compatible = "toradex,colibri-imx7d-iris",
+ "toradex,colibri-imx7d",
+ "fsl,imx7d";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+ status = "disabled";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+ /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+ /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+ disable-over-current;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
index 219a0404a058..531a45b176a1 100644
--- a/arch/arm/boot/dts/imx7d-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -1,12 +1,18 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
*/
#include "imx7d.dtsi"
#include "imx7-colibri.dtsi"
/ {
+ aliases {
+ /* Required to properly pass MAC addresses from bootloader. */
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
@@ -17,10 +23,13 @@
cpu-supply = <&reg_DCDC2>;
};
+/* NAND */
&gpmi {
status = "okay";
};
+/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
+ vbus-supply = <&reg_usbh_vbus>;
};
diff --git a/arch/arm/boot/dts/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/imx7d-pico-dwarf.dts
index 5162fe227d1e..fdc10563f147 100644
--- a/arch/arm/boot/dts/imx7d-pico-dwarf.dts
+++ b/arch/arm/boot/dts/imx7d-pico-dwarf.dts
@@ -32,7 +32,7 @@
};
&i2c1 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
@@ -52,7 +52,7 @@
};
&i2c4 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx7d-pico-nymph.dts b/arch/arm/boot/dts/imx7d-pico-nymph.dts
index 104a85254adb..5afb1674e012 100644
--- a/arch/arm/boot/dts/imx7d-pico-nymph.dts
+++ b/arch/arm/boot/dts/imx7d-pico-nymph.dts
@@ -43,7 +43,7 @@
};
&i2c1 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
@@ -64,7 +64,7 @@
};
&i2c2 {
- clock_frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index e519897fae08..e0bff39e8d3e 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -41,7 +41,7 @@
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
- };
+ };
reg_wlreg_on: regulator-wlreg_on {
compatible = "regulator-fixed";
@@ -432,7 +432,7 @@
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
+ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
>;
};
@@ -493,19 +493,19 @@
pinctrl_pwm1: pwm1 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
+ MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
>;
};
pinctrl_pwm2: pwm2 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
+ MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
>;
};
pinctrl_pwm3: pwm3 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
+ MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
>;
};
diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts
index a2a91bfdd98e..92cb45dacda6 100644
--- a/arch/arm/boot/dts/imx7d-remarkable2.dts
+++ b/arch/arm/boot/dts/imx7d-remarkable2.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "imx7d.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
/ {
model = "reMarkable 2.0";
@@ -22,6 +23,28 @@
reg = <0x80000000 0x40000000>;
};
+ thermal-zones {
+ epd-thermal {
+ thermal-sensors = <&sy7636a>;
+ polling-delay-passive = <30000>;
+ polling-delay = <30000>;
+
+ trips {
+ trip0 {
+ temperature = <49000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
regulator-name = "brcm_reg";
@@ -47,6 +70,17 @@
startup-delay-us = <100000>; /* 100 ms */
};
+ reg_touch: regulator-touch {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_TOUCH";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_reg>;
+ gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -57,6 +91,10 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck1>;
+};
+
&clks {
assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
<&clks IMX7D_CLKO2_ROOT_DIV>;
@@ -84,6 +122,217 @@
};
};
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ bd71815: pmic@4b {
+ compatible = "rohm,bd71815";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bd71815>;
+ interrupt-parent = <&gpio6>; /* PMIC_INT_B GPIO6_IO16 */
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ clocks = <&clks IMX7D_CLKO2_ROOT_SRC>;
+ clock-output-names = "bd71815-32k-out";
+ #clock-cells = <0>;
+ #gpio-cells = <2>;
+
+ regulators {
+ buck1: buck1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2: buck2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3: buck3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4: buck4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6: ldodvref {
+ regulator-name = "ldodvref";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo7: ldolpsr {
+ regulator-name = "ldolpsr";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ boost: wled {
+ regulator-name = "wled";
+ regulator-min-microamp = <10>;
+ regulator-max-microamp = <25000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ touchscreen@24 {
+ compatible = "cypress,tt21000";
+ reg = <0x24>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&reg_touch>;
+ touchscreen-size-x = <880>;
+ touchscreen-size-y = <1280>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@0 {
+ reg = <0>;
+ linux,keycodes = <KEY_HOMEPAGE>;
+ };
+
+ button@1 {
+ reg = <1>;
+ linux,keycodes = <KEY_MENU>;
+ };
+
+ button@2 {
+ reg = <2>;
+ linux,keycodes = <KEY_BACK>;
+ };
+
+ button@3 {
+ reg = <3>;
+ linux,keycodes = <KEY_SEARCH>;
+ };
+
+ button@4 {
+ reg = <4>;
+ linux,keycodes = <KEY_VOLUMEDOWN>;
+ };
+
+ button@5 {
+ reg = <5>;
+ linux,keycodes = <KEY_VOLUMEUP>;
+ };
+
+ button@6 {
+ reg = <6>;
+ linux,keycodes = <KEY_CAMERA>;
+ };
+
+ button@7 {
+ reg = <7>;
+ linux,keycodes = <KEY_POWER>;
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ sy7636a: pmic@62 {
+ compatible = "silergy,sy7636a";
+ reg = <0x62>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epdpmic>;
+ #thermal-sensor-cells = <0>;
+ epd-pwr-good-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ reg_epdpmic: vcom {
+ regulator-name = "vcom";
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -170,6 +419,12 @@
};
&iomuxc {
+ pinctrl_bd71815: bd71815grp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x59
+ >;
+ };
+
pinctrl_brcm_reg: brcmreggrp {
fsl,pins = <
/* WIFI_PWR_EN */
@@ -177,6 +432,22 @@
>;
};
+ pinctrl_epdpmic: epdpmicgrp {
+ fsl,pins = <
+ MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x00000074
+ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x00000014
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ /* CYTTSP interrupt */
+ MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x54
+ /* CYTTSP reset */
+ MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x04
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
@@ -184,6 +455,34 @@
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
+ MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
+ MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
+ MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_touch_reg: touchreggrp {
+ fsl,pins = <
+ /* TOUCH_PWR_EN */
+ MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x14
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index f053f5122741..f483bc0afe5e 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -24,14 +24,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
- volume-up {
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
- volume-down {
+ key-volume-down {
label = "Volume Down";
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
@@ -39,7 +39,7 @@
};
};
- spi4 {
+ spi-4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
@@ -201,17 +201,12 @@
compatible = "ti,tsc2046";
reg = <0>;
spi-max-frequency = <1000000>;
- pinctrl-names ="default";
+ pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc2046_pendown>;
interrupt-parent = <&gpio2>;
interrupts = <29 0>;
pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
- ti,x-min = /bits/ 16 <0>;
- ti,x-max = /bits/ 16 <0>;
- ti,y-min = /bits/ 16 <0>;
- ti,y-max = /bits/ 16 <0>;
- ti,pressure-max = /bits/ 16 <0>;
- ti,x-plate-ohms = /bits/ 16 <400>;
+ touchscreen-max-pressure = <255>;
wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts
new file mode 100644
index 000000000000..c0f00f5db11e
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-smegw01.dts
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright (C) 2020 PHYTEC Messtechnik GmbH
+// Author: Jens Lang <J.Lang@phytec.de>
+// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx7d.dtsi"
+
+/ {
+ model = "Storopack SMEGW01 board";
+ compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
+
+ aliases {
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc2;
+ rtc0 = &i2c_rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reg_lte_on: regulator-lte-on {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lte_on>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "lte_on";
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_lte_nreset: regulator-lte-nreset {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lte_nreset>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "LTE_nReset";
+ gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi>;
+ regulator-name = "wifi_reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_wlan_rfkill: regulator-wlan-rfkill {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-2 = <&pinctrl_rfkill>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "wlan_rfkill";
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usbotg_vbus: regulator-usbotg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ sram@0 {
+ compatible = "microchip,48l640";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <16000000>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ };
+
+ ethphy1: ethernet-phy@2 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy1>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ i2c_rtc: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_int>;
+ reg = <0x52>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
+ dr_mode = "otg";
+ vbus-supply = <&reg_usbotg_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2>;
+ over-current-active-low;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ wakeup-source;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ vmmc-supply = <&reg_wifi>;
+ wakeup-source;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <400000000>;
+ max-frequency = <200000000>;
+ bus-width = <8>;
+ fsl,tuning-step = <1>;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
+ MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
+ MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
+ MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
+ MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
+ MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
+ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
+ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
+ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
+ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
+ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
+ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
+ MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
+ MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
+ >;
+ };
+
+ pinctrl_lte_on: lteongrp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
+ >;
+ };
+
+ pinctrl_lte_nreset: ltenresetgrp {
+ fsl,pins = <
+ MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
+ >;
+ };
+
+ pinctrl_rfkill: rfkillrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
+ >;
+ };
+
+ pinctrl_rtc_int: rtcintgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
+ MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
+ >;
+ };
+
+ pinctrl_usbotg1_lpsr: usbotg1 {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
+ >;
+ };
+
+ pinctrl_usbotg1_pwr: usbotg1-pwr {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
+ >;
+ };
+
+ pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
+ >;
+ };
+
+ pinctrl_usbotg2: usbotg2grp {
+ fsl,pins = <
+ MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x5c
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CLK__SD2_CLK 0x19
+ MX7D_PAD_SD2_CMD__SD2_CMD 0x59
+ MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
+ MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
+ MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
+ MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
+ MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
+ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts
index 1065941807e8..521493342fe9 100644
--- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts
+++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts
@@ -24,7 +24,7 @@
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
- debug {
+ led-debug {
label = "zii:green:debug1";
gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -204,7 +204,7 @@
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts
index 893bd30aa2a3..decc19af3b83 100644
--- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts
+++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts
@@ -36,7 +36,7 @@
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
- debug {
+ led-debug {
label = "zii:green:debug1";
gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -607,7 +607,7 @@
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index f8cba47536a0..4b94b8afb55d 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -78,7 +78,7 @@
#phy-cells = <0>;
};
- soc {
+ soc: soc {
etm@3007d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x3007d000 0x1000>;
@@ -165,6 +165,15 @@
reg = <0x306d0000 0x10000>;
status = "disabled";
};
+
+ pxp: pxp@30700000 {
+ compatible = "fsl,imx7d-pxp";
+ reg = <0x30700000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_PXP_CLK>;
+ clock-names = "axi";
+ };
};
&aips3 {
diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts
index fca4e0a95c1b..58ebb02d948a 100644
--- a/arch/arm/boot/dts/imx7s-colibri-aster.dts
+++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017-2020 Toradex AG
+ * Copyright 2017-2022 Toradex
*
*/
@@ -10,6 +10,27 @@
/ {
model = "Toradex Colibri iMX7S on Aster Carrier Board";
- compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s",
+ compatible = "toradex,colibri-imx7s-aster",
+ "toradex,colibri-imx7s",
"fsl,imx7s";
};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
index aa70d3f2e2e2..38de76630d6a 100644
--- a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
*/
/dts-v1/;
@@ -9,6 +9,43 @@
/ {
model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3";
- compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s",
+ compatible = "toradex,colibri-imx7s-eval-v3",
+ "toradex,colibri-imx7s",
"fsl,imx7s";
};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+ status = "disabled";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+ /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+ /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts
new file mode 100644
index 000000000000..72b5c17ab1ab
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7s-colibri.dtsi"
+#include "imx7-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7S on Iris V2 Carrier Board";
+ compatible = "toradex,colibri-imx7s-iris-v2",
+ "toradex,colibri-imx7s",
+ "fsl,imx7s";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map-hog {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
+
+&gpio7 {
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /* This turns the LVDS transceiver on */
+ lvds-power-on-hog {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/imx7s-colibri-iris.dts
new file mode 100644
index 000000000000..26ba72c17feb
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri-iris.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7s-colibri.dtsi"
+#include "imx7-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7S on Iris Carrier Board";
+ compatible = "toradex,colibri-imx7s-iris",
+ "toradex,colibri-imx7s",
+ "fsl,imx7s";
+};
+
+&ad7879_ts {
+ status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+ status = "disabled";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&panel_dpi {
+ status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+ /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+ /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
index 94de220a5965..ef51395d3537 100644
--- a/arch/arm/boot/dts/imx7s-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
*/
#include "imx7s.dtsi"
@@ -13,6 +13,7 @@
};
};
+/* NAND */
&gpmi {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 5af6d58666f4..efe2525b62fa 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -120,6 +120,7 @@
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
clock-names = "main_clk";
+ power-domains = <&pgc_hsic_phy>;
#phy-cells = <0>;
};
@@ -175,7 +176,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -446,7 +447,7 @@
status = "disabled";
};
- iomuxc_lpsr: iomuxc-lpsr@302c0000 {
+ iomuxc_lpsr: pinctrl@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
@@ -512,7 +513,7 @@
mux: mux-controller {
compatible = "mmio-mux";
- #mux-control-cells = <0>;
+ #mux-control-cells = <1>;
mux-reg-masks = <0x14 0x00000010>;
};
@@ -1153,7 +1154,6 @@
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pgc_hsic_phy>;
clocks = <&clks IMX7D_USB_CTRL_CLK>;
fsl,usbphy = <&usbphynop3>;
fsl,usbmisc = <&usbmisc3 0>;
@@ -1224,7 +1224,7 @@
status = "disabled";
};
- sdma: sdma@30bd0000 {
+ sdma: dma-controller@30bd0000 {
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -1264,7 +1264,6 @@
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index bcec98b96411..f91bf719d4e2 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -189,7 +189,7 @@
};
usbotg1: usb@40330000 {
- compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
+ compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
reg = <0x40330000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc2 IMX7ULP_CLK_USB0>;
@@ -202,7 +202,8 @@
};
usbmisc1: usbmisc@40330200 {
- compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
+ "fsl,imx6q-usbmisc";
#index-cells = <1>;
reg = <0x40330200 0x200>;
};
@@ -328,8 +329,9 @@
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40a40000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
- clock-names = "ipg";
+ clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>,
+ <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
@@ -340,8 +342,9 @@
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40a50000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
- clock-names = "ipg";
+ clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>,
+ <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts
new file mode 100644
index 000000000000..6a9c10decf52
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1050-evk.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include "imxrt1050-pinfunc.h"
+
+/ {
+ model = "NXP IMXRT1050-evk board";
+ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x2000000>;
+ };
+};
+
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
+ MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
+ MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
+ MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
+ >;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi
new file mode 100644
index 000000000000..852861558b47
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1050.dtsi
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clocks {
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ osc3M: osc3M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
+ };
+ };
+
+ soc {
+ lpuart1: serial@40184000 {
+ compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <20>;
+ clocks = <&clks IMXRT1050_CLK_LPUART1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ iomuxc: pinctrl@401f8000 {
+ compatible = "fsl,imxrt1050-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ anatop: anatop@400d8000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x400d8000 0x4000>;
+ };
+
+ clks: clock-controller@400fc000 {
+ compatible = "fsl,imxrt1050-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <95>, <96>;
+ clocks = <&osc>;
+ clock-names = "osc";
+ #clock-cells = <1>;
+ assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL1_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL2_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL3_BYPASS>,
+ <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
+ <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
+ assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
+ <&clks IMXRT1050_CLK_PLL1_ARM>,
+ <&clks IMXRT1050_CLK_PLL2_SYS>,
+ <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+ <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+ <&clks IMXRT1050_CLK_PLL2_SYS>;
+ };
+
+ edma1: dma-controller@400e8000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x400e8000 0x4000>,
+ <0x400ec000 0x4000>;
+ dma-channels = <32>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&clks IMXRT1050_CLK_DMA>,
+ <&clks IMXRT1050_CLK_DMA_MUX>;
+ };
+
+ usdhc1: mmc@402c0000 {
+ compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x402c0000 0x4000>;
+ interrupts = <110>;
+ clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
+ <&clks IMXRT1050_CLK_OSC>,
+ <&clks IMXRT1050_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,wp-controller;
+ no-1-8-v;
+ max-frequency = <200000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@401b8000 {
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
+ reg = <0x401b8000 0x4000>;
+ interrupts = <80>, <81>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@401bc000 {
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
+ reg = <0x401bc000 0x4000>;
+ interrupts = <82>, <83>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@401c0000 {
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
+ reg = <0x401c0000 0x4000>;
+ interrupts = <84>, <85>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@401c4000 {
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
+ reg = <0x401c4000 0x4000>;
+ interrupts = <86>, <87>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@400c0000 {
+ compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
+ reg = <0x400c0000 0x4000>;
+ interrupts = <88>, <89>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpt: timer@401ec000 {
+ compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
+ reg = <0x401ec000 0x4000>;
+ interrupts = <100>;
+ clocks = <&osc3M>;
+ clock-names = "per";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imxrt1170-pinfunc.h b/arch/arm/boot/dts/imxrt1170-pinfunc.h
new file mode 100644
index 000000000000..3b9fff2f08e1
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1170-pinfunc.h
@@ -0,0 +1,1561 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
+#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H
+
+#define IMX_PAD_SION 0x40000000
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
+#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
+#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
+#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
+#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0
+#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0
+#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0
+#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0
+#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0
+#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0
+#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0
+#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0
+#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0
+#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0
+#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0
+#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1
+#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0
+#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0
+
+#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0
+#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1
+#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0
+#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0
+#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0
+#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0
+#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0
+#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0
+#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1
+#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0
+#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1
+#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0
+#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0
+#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1
+#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0
+#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0
+#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0
+#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1
+#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0
+#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1
+#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2
+#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1
+#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0
+#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1
+#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0
+
+#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0
+#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1
+#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0
+#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0
+#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0
+#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1
+#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2
+
+#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0
+#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1
+#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0
+#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0
+#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0
+#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0
+#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2
+#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0
+#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0
+#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0
+#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0
+#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1
+#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1
+
+#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1
+#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1
+#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1
+
+#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1
+#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1
+#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1
+#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0
+#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0
+#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1
+#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0
+#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0
+#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1
+#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1
+
+#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0
+#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1
+
+#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0
+#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0
+
+#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0
+#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0
+#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0
+
+#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0
+
+#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0
+
+#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0
+
+#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0
+#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0
+#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1
+
+#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1
+
+#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1
+
+#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1
+
+#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1
+
+#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1
+
+#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1
+#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1
+
+#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1
+
+#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1
+
+#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1
+
+#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0
+#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1
+#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0
+#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1
+#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0
+#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1
+#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0
+#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0
+
+#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0
+#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0
+#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0
+#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1
+#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0
+#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0
+#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0
+#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0
+#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1
+#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1
+#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0
+#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0
+#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1
+#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0
+#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1
+#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0
+#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1
+#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0
+#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1
+#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1
+#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1
+#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1
+#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1
+#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1
+#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0
+#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0
+#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1
+#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0
+#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0
+#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1
+#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0
+#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0
+#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0
+#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0
+#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0
+#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0
+#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0
+#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1
+#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0
+#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0
+#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0
+#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0
+#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1
+#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0
+#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0
+#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0
+#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0
+#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0
+#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1
+#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2
+#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0
+#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0
+#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1
+
+#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0
+#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0
+#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1
+#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0
+#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0
+#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0
+#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0
+#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0
+#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0
+#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0
+#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0
+#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0
+#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0
+#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0
+#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0
+#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0
+#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0
+#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0
+#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1
+#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0
+#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0
+#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0
+#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0
+#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1
+#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0
+
+#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0
+#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0
+#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1
+#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1
+
+#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0
+#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0
+#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1
+#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1
+#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1
+
+#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0
+#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1
+#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1
+#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1
+#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0
+#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0
+#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1
+#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0
+
+#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1
+#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1
+#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1
+#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1
+#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1
+#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1
+#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0
+#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1
+#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1
+#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1
+#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1
+#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0
+#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1
+#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3
+#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0
+#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0
+#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0
+#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0
+#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1
+#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0
+#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0
+#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0
+#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0
+#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0
+#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0
+#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1
+#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0
+#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1
+#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1
+#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1
+#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1
+#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1
+#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1
+#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1
+#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1
+#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1
+#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1
+#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0
+#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1
+#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1
+#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0
+#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0
+#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1
+#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1
+#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0
+#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0
+
+#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1
+#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1
+#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1
+#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1
+#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1
+#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2
+#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1
+#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0
+#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0
+#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0
+
+#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0
+#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1
+#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0
+#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1
+#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0
+#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1
+
+#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0
+#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1
+
+#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0
+#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0
+#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0
+#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1
+
+#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0
+#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1
+#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1
+#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1
+#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0
+#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0
+#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1
+#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2
+#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2
+#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1
+#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0
+#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2
+#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0
+#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1
+#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1
+
+#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2
+#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1
+#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2
+#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1
+#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2
+#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1
+#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1
+
+#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1
+#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1
+#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1
+#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1
+#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1
+
+#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1
+#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1
+#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1
+#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2
+#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1
+#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2
+#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2
+#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1
+#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0
+#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2
+#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0
+#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1
+#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0
+
+#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1
+#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1
+#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1
+#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1
+
+#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1
+#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1
+#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1
+
+#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1
+#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1
+#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1
+#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1
+#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1
+#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2
+
+#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1
+#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1
+#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1
+#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2
+
+#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1
+#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2
+#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2
+
+#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1
+#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0
+#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0
+
+#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1
+#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1
+
+#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0
+#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1
+#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2
+#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1
+#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1
+
+#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0
+#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1
+#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0
+#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3
+
+#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0
+#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1
+#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0
+#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0
+#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0
+#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0
+#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2
+#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0
+#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1
+#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0
+
+#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index ad868cfebc94..7f1c8ee9dd8a 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -88,12 +88,12 @@
interrupts = <8>;
};
- uart@16000000 {
+ serial@16000000 {
reg = <0x16000000 0x1000>;
interrupts = <1>;
};
- uart@17000000 {
+ serial@17000000 {
reg = <0x17000000 0x1000>;
interrupts = <2>;
};
diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts
index d47bfb66d069..7072a70da00d 100644
--- a/arch/arm/boot/dts/integratorap-im-pd1.dts
+++ b/arch/arm/boot/dts/integratorap-im-pd1.dts
@@ -162,7 +162,7 @@
};
};
- uart@100000 {
+ serial@100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00100000 0x1000>;
interrupts-extended = <&impd1_vic 1>;
@@ -170,7 +170,7 @@
clock-names = "uartclk", "apb_pclk";
};
- uart@200000 {
+ serial@200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00200000 0x1000>;
interrupts-extended = <&impd1_vic 2>;
@@ -178,12 +178,12 @@
clock-names = "uartclk", "apb_pclk";
};
- ssp@300000 {
+ spi@300000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00300000 0x1000>;
interrupts-extended = <&impd1_vic 3>;
clocks = <&impd1_sspclk>, <&sysclk>;
- clock-names = "spiclk", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
};
impd1_gpio0: gpio@400000 {
@@ -249,6 +249,7 @@
/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
max-memory-bandwidth = <40000000>;
memory-region = <&impd1_ram>;
+ dma-ranges;
port@0 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 9b652cc27b14..5b52d75bc6be 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -160,6 +160,7 @@
pci: pciv3@62000000 {
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
+ device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
@@ -217,14 +218,14 @@
clock-names = "apb_pclk";
};
- uart0: uart@16000000 {
+ uart0: serial@16000000 {
compatible = "arm,pl010", "arm,primecell";
arm,primecell-periphid = <0x00041010>;
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
- uart1: uart@17000000 {
+ uart1: serial@17000000 {
compatible = "arm,pl010", "arm,primecell";
arm,primecell-periphid = <0x00041010>;
clocks = <&uartclk>, <&pclk>;
@@ -261,7 +262,7 @@
lm0: bus@c0000000 {
compatible = "simple-bus";
ranges = <0x00000000 0xc0000000 0x10000000>;
- dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ dma-ranges = <0x00000000 0xc0000000 0x10000000>;
reg = <0xc0000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -269,7 +270,7 @@
lm1: bus@d0000000 {
compatible = "simple-bus";
ranges = <0x00000000 0xd0000000 0x10000000>;
- dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ dma-ranges = <0x00000000 0xd0000000 0x10000000>;
reg = <0xd0000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -277,7 +278,7 @@
lm2: bus@e0000000 {
compatible = "simple-bus";
ranges = <0x00000000 0xe0000000 0x10000000>;
- dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ dma-ranges = <0x00000000 0xe0000000 0x10000000>;
reg = <0xe0000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -285,7 +286,7 @@
lm3: bus@f0000000 {
compatible = "simple-bus";
ranges = <0x00000000 0xf0000000 0x10000000>;
- dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ dma-ranges = <0x00000000 0xf0000000 0x10000000>;
reg = <0xf0000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 38fc7e81bdb6..c011333eb165 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -244,13 +244,13 @@
clock-names = "apb_pclk";
};
- uart@16000000 {
+ serial@16000000 {
compatible = "arm,pl011", "arm,primecell";
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
- uart@17000000 {
+ serial@17000000 {
compatible = "arm,pl011", "arm,primecell";
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
diff --git a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
index bd4230d7dac9..765ab36e6f0c 100644
--- a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
@@ -56,7 +56,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from Coyote PCI boardfile.
@@ -80,7 +80,7 @@
/* EthB */
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -102,7 +102,7 @@
/* EthC */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
index 92b987bc3f99..6f5b4e4eb1cc 100644
--- a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts
@@ -112,7 +112,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from Vulcan PCI boardfile.
@@ -137,7 +137,7 @@
/* EthB */
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -159,7 +159,7 @@
/* EthC */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
index 5ab09fb10dae..b9d46eb06507 100644
--- a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
@@ -122,7 +122,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from DSM-G600 PCI boardfile (dsmg600-pci.c)
diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
index b740403b05a9..5a5e16cc7335 100644
--- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
@@ -159,7 +159,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Written based on the FSG-3 PCI boardfile.
@@ -187,7 +187,7 @@
/* EthB */
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -209,7 +209,7 @@
/* EthC */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
index b7cbc90e1c18..4d70f6afd13a 100644
--- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
@@ -53,7 +53,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c)
@@ -74,7 +74,7 @@
};
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -91,7 +91,7 @@
};
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts b/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
index a5943f51e8c2..97e3f25bb210 100644
--- a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts
@@ -108,7 +108,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from Avila PCI boardfile.
@@ -142,7 +142,7 @@
/* EthB */
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -164,7 +164,7 @@
/* EthC */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
index f80388b17a9e..9ec0169bacf8 100644
--- a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts
@@ -82,7 +82,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
@@ -148,7 +148,7 @@
/* EthB */
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 32>;
phy-mode = "rgmii";
@@ -170,7 +170,7 @@
/* EthC */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 33>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
index cbc87b344f6a..8da6823e1dbe 100644
--- a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts
@@ -109,7 +109,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from NAS 100D PCI boardfile (nas100d-pci.c)
@@ -129,7 +129,7 @@
};
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts
index beaadda4685f..194945748dc3 100644
--- a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts
@@ -40,7 +40,7 @@
/* EthB */
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -62,7 +62,7 @@
/* EthC */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
index f17cab12a64b..7011fea6205b 100644
--- a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
@@ -61,7 +61,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from IXDPG425 PCI boardfile.
@@ -95,7 +95,7 @@
/* EthB */
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -117,7 +117,7 @@
/* EthC */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
index 0edc5928e00b..da1e93212b86 100644
--- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
@@ -116,7 +116,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
@@ -143,7 +143,7 @@
};
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
index 5e7e31b74b04..4aba9e0214a0 100644
--- a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts
@@ -117,7 +117,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
@@ -141,7 +141,7 @@
* Do we need a new binding and property for this?
*/
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
@@ -165,7 +165,7 @@
/* EthC - connected to KS8995 switch port 5 */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts
index df2ca6d95ee5..19d56e9aec9d 100644
--- a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts
@@ -54,7 +54,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from WG302 v2 PCI boardfile (wg302v2-pci.c)
@@ -77,7 +77,7 @@
};
ethernet@c8009000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts
index f5846a50e4d4..c550c421b659 100644
--- a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts
@@ -76,5 +76,23 @@
};
};
};
+
+ /* LAN port */
+ ethernet@c8009000 {
+ status = "okay";
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy5>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
index cf4010d60187..1db849515f9e 100644
--- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
+++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
@@ -121,7 +121,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* In the boardfile for the Cambria from OpenWRT the interrupts
@@ -167,7 +167,7 @@
};
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
@@ -188,7 +188,7 @@
};
ethernet@c800c000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 2>;
queue-txready = <&qmgr 19>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts b/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts
index 3d7cfa1a5ed4..4703a8b24765 100644
--- a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts
+++ b/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts
@@ -36,7 +36,7 @@
/* CHECKME: ethernet set-up taken from Gateworks Cambria */
ethernet@c800a000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
@@ -57,7 +57,7 @@
};
ethernet@c800c000 {
- status = "ok";
+ status = "okay";
queue-rx = <&qmgr 2>;
queue-txready = <&qmgr 19>;
phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
index 146352ba848b..31c0a69771c4 100644
--- a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
+++ b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi
@@ -99,7 +99,7 @@
};
pci@c0000000 {
- status = "ok";
+ status = "okay";
/*
* Taken from IXDP425 PCI boardfile.
diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts
index 66fec5f5d081..abd5aef8b87d 100644
--- a/arch/arm/boot/dts/keystone-k2e-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2e-evm.dts
@@ -137,10 +137,10 @@
};
&spi0 {
- nor_flash: n25q128a11@0 {
+ nor_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "Micron,n25q128a11";
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <54000000>;
m25p,fast-read;
reg = <0>;
@@ -159,7 +159,7 @@
};
&mdio {
- status = "ok";
+ status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <0>;
diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
index 71064483d34f..42cf74db673c 100644
--- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
@@ -12,9 +12,9 @@ qmss: qmss@2a40000 {
#size-cells = <1>;
clocks = <&chipclk13>;
ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0 0x10000>;
+ queue-range = <0 0x2000>;
+ linkram0 = <0x100000 0x4000>;
+ linkram1 = <0 0x10000>;
qmgrs {
#address-cells = <1>;
@@ -176,40 +176,40 @@ netcp: netcp@24000000 {
interfaces {
gbe0: interface-0 {
slave-port = <0>;
- link-interface = <1>;
- phy-handle = <&ethphy0>;
+ link-interface = <1>;
+ phy-handle = <&ethphy0>;
};
gbe1: interface-1 {
slave-port = <1>;
- link-interface = <1>;
- phy-handle = <&ethphy1>;
+ link-interface = <1>;
+ phy-handle = <&ethphy1>;
};
};
secondary-slave-ports {
port-2 {
slave-port = <2>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-3 {
slave-port = <3>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-4 {
slave-port = <4>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-5 {
slave-port = <5>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-6 {
slave-port = <6>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-7 {
slave-port = <7>;
- link-interface = <2>;
+ link-interface = <2>;
};
};
};
diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index b8f152e7af7f..65c32946c522 100644
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -141,7 +141,7 @@
clock-names = "pcie";
#address-cells = <3>;
#size-cells = <2>;
- reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+ reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
ranges = <0x82000000 0 0x60000000 0x60000000
0 0x10000000>;
@@ -185,14 +185,14 @@
};
mdio: mdio@24200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x24200f00 0x100>;
status = "disabled";
clocks = <&clkcpgmac>;
clock-names = "fck";
- bus_freq = <2500000>;
+ bus_freq = <2500000>;
};
/include/ "keystone-k2e-netcp.dtsi"
};
diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index d800f26b6275..3a87b7943c70 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -392,7 +392,7 @@
pinctrl-0 = <&qspi_pins>;
cdns,rclk-en;
- flash0: m25p80@0 {
+ flash0: flash@0 {
compatible = "s25fl512s", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
@@ -534,7 +534,7 @@
&dss {
pinctrl-names = "default";
pinctrl-0 = <&vout_pins>;
- status = "ok";
+ status = "okay";
port {
dpi_out: endpoint {
diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts
index 2a2d38cf0fff..bd84d7f0f2fe 100644
--- a/arch/arm/boot/dts/keystone-k2g-ice.dts
+++ b/arch/arm/boot/dts/keystone-k2g-ice.dts
@@ -325,7 +325,7 @@
cdns,rclk-en;
status = "okay";
- flash0: m25p80@0 {
+ flash0: flash@0 {
compatible = "s25fl256s1", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi
index d0e6a9a43402..f6306933ff42 100644
--- a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi
@@ -125,7 +125,7 @@ netcp: netcp@4000000 {
interfaces {
gbe0: interface-0 {
slave-port = <0>;
- link-interface = <5>;
+ link-interface = <5>;
};
};
};
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 37198294f4b2..380dd9d637ee 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -262,7 +262,7 @@
*/
ti,system-reboot-controller;
mbox-names = "rx", "tx";
- mboxes= <&msgmgr 5 2>,
+ mboxes = <&msgmgr 5 2>,
<&msgmgr 0 0>;
reg-names = "debug_messages";
reg = <0x02921c00 0x400>;
@@ -326,13 +326,13 @@
dss: dss@02540000 {
compatible = "ti,k2g-dss";
- reg = <0x02540000 0x400>,
+ reg = <0x02540000 0x400>,
<0x02550000 0x1000>,
<0x02557000 0x1000>,
<0x0255a800 0x100>,
<0x0255ac00 0x100>;
reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
- clocks = <&k2g_clks 0x2 0>,
+ clocks = <&k2g_clks 0x2 0>,
<&k2g_clks 0x2 1>;
clock-names = "fck", "vp1";
interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
@@ -348,7 +348,7 @@
edma0: edma@2700000 {
compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
- reg = <0x02700000 0x8000>;
+ reg = <0x02700000 0x8000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 216 IRQ_TYPE_EDGE_RISING>,
@@ -367,19 +367,19 @@
edma0_tptc0: tptc@2760000 {
compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
- reg = <0x02760000 0x400>;
+ reg = <0x02760000 0x400>;
power-domains = <&k2g_pds 0x3f>;
};
edma0_tptc1: tptc@2768000 {
compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
- reg = <0x02768000 0x400>;
+ reg = <0x02768000 0x400>;
power-domains = <&k2g_pds 0x3f>;
};
edma1: edma@2728000 {
compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
- reg = <0x02728000 0x8000>;
+ reg = <0x02728000 0x8000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
@@ -402,13 +402,13 @@
edma1_tptc0: tptc@27b0000 {
compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
- reg = <0x027b0000 0x400>;
+ reg = <0x027b0000 0x400>;
power-domains = <&k2g_pds 0x4f>;
};
edma1_tptc1: tptc@27b8000 {
compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
- reg = <0x027b8000 0x400>;
+ reg = <0x027b8000 0x400>;
power-domains = <&k2g_pds 0x4f>;
};
diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts
index ad4e22afe133..1f762af6f502 100644
--- a/arch/arm/boot/dts/keystone-k2hk-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts
@@ -28,22 +28,22 @@
leds {
compatible = "gpio-leds";
- debug1_1 {
+ led-debug-1-1 {
label = "keystone:green:debug1";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
};
- debug1_2 {
+ led-debug-1-2 {
label = "keystone:red:debug1";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
};
- debug2 {
+ led-debug-2 {
label = "keystone:blue:debug2";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
};
- debug3 {
+ led-debug-3 {
label = "keystone:blue:debug3";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
};
@@ -161,10 +161,10 @@
};
&spi0 {
- nor_flash: n25q128a11@0 {
+ nor_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "Micron,n25q128a11";
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <54000000>;
m25p,fast-read;
reg = <0>;
@@ -183,7 +183,7 @@
};
&mdio {
- status = "ok";
+ status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <0>;
diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
index 022d93c366c7..8a421c65f920 100644
--- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
@@ -12,9 +12,9 @@ qmss: qmss@2a40000 {
#size-cells = <1>;
clocks = <&chipclk13>;
ranges;
- queue-range = <0 0x4000>;
- linkram0 = <0x100000 0x8000>;
- linkram1 = <0x0 0x10000>;
+ queue-range = <0 0x4000>;
+ linkram0 = <0x100000 0x8000>;
+ linkram1 = <0x0 0x10000>;
qmgrs {
#address-cells = <1>;
@@ -150,7 +150,7 @@ netcp: netcp@2000000 {
#size-cells = <1>;
/* NetCP address range */
- ranges = <0 0x2000000 0x100000>;
+ ranges = <0 0x2000000 0x100000>;
clocks = <&clkpa>, <&clkcpgmac>;
clock-names = "pa_clk", "ethss_clk";
@@ -207,11 +207,11 @@ netcp: netcp@2000000 {
secondary-slave-ports {
port-2 {
slave-port = <2>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-3 {
slave-port = <3>;
- link-interface = <2>;
+ link-interface = <2>;
};
};
};
diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi
index 8a9447703310..da6d3934c2e8 100644
--- a/arch/arm/boot/dts/keystone-k2hk.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk.dtsi
@@ -282,14 +282,14 @@
};
mdio: mdio@2090300 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02090300 0x100>;
status = "disabled";
clocks = <&clkcpgmac>;
clock-names = "fck";
- bus_freq = <2500000>;
+ bus_freq = <2500000>;
};
/include/ "keystone-k2hk-netcp.dtsi"
};
diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts
index e200533d26a4..3a69f65de81e 100644
--- a/arch/arm/boot/dts/keystone-k2l-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2l-evm.dts
@@ -110,10 +110,10 @@
};
&spi0 {
- nor_flash: n25q128a11@0 {
+ nor_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "Micron,n25q128a11";
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <54000000>;
m25p,fast-read;
reg = <0>;
@@ -132,7 +132,7 @@
};
&mdio {
- status = "ok";
+ status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
reg = <0>;
diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
index e96ca664abc2..5ec6680a533d 100644
--- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
@@ -12,9 +12,9 @@ qmss: qmss@2a40000 {
#size-cells = <1>;
clocks = <&chipclk13>;
ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
+ queue-range = <0 0x2000>;
+ linkram0 = <0x100000 0x4000>;
+ linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
qmgrs {
#address-cells = <1>;
@@ -174,24 +174,24 @@ netcp: netcp@26000000 {
interfaces {
gbe0: interface-0 {
slave-port = <0>;
- link-interface = <1>;
- phy-handle = <&ethphy0>;
+ link-interface = <1>;
+ phy-handle = <&ethphy0>;
};
gbe1: interface-1 {
slave-port = <1>;
- link-interface = <1>;
- phy-handle = <&ethphy1>;
+ link-interface = <1>;
+ phy-handle = <&ethphy1>;
};
};
secondary-slave-ports {
port-2 {
slave-port = <2>;
- link-interface = <2>;
+ link-interface = <2>;
};
port-3 {
slave-port = <3>;
- link-interface = <2>;
+ link-interface = <2>;
};
};
};
diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index dff5fea72b2f..421a02bbc9d3 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -47,7 +47,7 @@
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02348400 0x100>;
- clocks = <&clkuart2>;
+ clocks = <&clkuart2>;
interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
};
@@ -57,7 +57,7 @@
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02348800 0x100>;
- clocks = <&clkuart3>;
+ clocks = <&clkuart3>;
interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
};
@@ -388,14 +388,14 @@
};
mdio: mdio@26200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x26200f00 0x100>;
status = "disabled";
clocks = <&clkcpgmac>;
clock-names = "fck";
- bus_freq = <2500000>;
+ bus_freq = <2500000>;
};
/include/ "keystone-k2l-netcp.dtsi"
};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index fc9fdc857ae8..50789f9e2215 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -14,7 +14,7 @@
interrupt-parent = <&gic>;
aliases {
- serial0 = &uart0;
+ serial0 = &uart0;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
@@ -61,11 +61,11 @@
};
psci {
- compatible = "arm,psci";
- method = "smc";
- cpu_suspend = <0x84000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
};
soc0: soc@0 {
@@ -119,7 +119,7 @@
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02530c00 0x100>;
- clocks = <&clkuart0>;
+ clocks = <&clkuart0>;
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
};
@@ -129,7 +129,7 @@
reg-shift = <2>;
reg-io-width = <4>;
reg = <0x02531000 0x100>;
- clocks = <&clkuart1>;
+ clocks = <&clkuart1>;
interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
};
@@ -301,7 +301,7 @@
clock-names = "pcie";
#address-cells = <3>;
#size-cells = <2>;
- reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+ reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
ranges = <0x82000000 0 0x50000000 0x50000000
0 0x10000000>;
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
index 396bcba08adb..705c0d7effed 100644
--- a/arch/arm/boot/dts/kirkwood-6192.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
@@ -26,12 +26,22 @@
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 9>;
+ interrupt-names = "intx", "error";
+ interrupts = <9>, <44>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gate_clk 2>;
status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index faa05849a40d..8e311165fd13 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -26,12 +26,22 @@
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 9>;
+ interrupt-names = "intx", "error";
+ interrupts = <9>, <44>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gate_clk 2>;
status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index e84c54b77dea..e33723160ce7 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -30,12 +30,22 @@
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 9>;
+ interrupt-names = "intx", "error";
+ interrupts = <9>, <44>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gate_clk 2>;
status = "disabled";
+
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie1: pcie@2,0 {
@@ -48,12 +58,22 @@
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 10>;
+ interrupt-names = "intx", "error";
+ interrupts = <10>, <45>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gate_clk 18>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
index 299c147298c3..c3469a2fc58a 100644
--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
+++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
@@ -26,12 +26,22 @@
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 9>;
+ interrupt-names = "intx", "error";
+ interrupts = <9>, <44>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gate_clk 2>;
status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts
index a7636fe28501..681343c1357a 100644
--- a/arch/arm/boot/dts/kirkwood-b3.dts
+++ b/arch/arm/boot/dts/kirkwood-b3.dts
@@ -187,7 +187,7 @@
/* Wifi model has Atheros chipset on pcie port */
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
index 2adb17c955aa..a9a8e6b744c7 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -18,7 +18,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
index f84a48539917..6dc6579d4524 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -18,7 +18,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
index b3ad3f607d31..0c0851cd9bec 100644
--- a/arch/arm/boot/dts/kirkwood-dir665.dts
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -78,7 +78,7 @@
spi@10600 {
status = "okay";
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
@@ -211,18 +211,18 @@
};
port@1 {
- reg = <1>;
- label = "lan3";
+ reg = <1>;
+ label = "lan3";
};
port@2 {
- reg = <2>;
- label = "lan2";
+ reg = <2>;
+ label = "lan2";
};
port@3 {
- reg = <3>;
- label = "lan1";
+ reg = <3>;
+ label = "lan1";
};
port@4 {
@@ -232,7 +232,7 @@
port@6 {
reg = <6>;
- label = "cpu";
+ phy-mode = "rgmii-id";
ethernet = <&eth0port>;
fixed-link {
speed = <1000>;
@@ -251,6 +251,7 @@
ethernet0-port@0 {
speed = <1000>;
duplex = <1>;
+ phy-mode = "rgmii";
};
};
@@ -268,7 +269,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts
index f48609e95afe..3912f1b525b6 100644
--- a/arch/arm/boot/dts/kirkwood-ds112.dts
+++ b/arch/arm/boot/dts/kirkwood-ds112.dts
@@ -43,7 +43,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie1 {
diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts
index 86907be70cf9..1d4256ef325d 100644
--- a/arch/arm/boot/dts/kirkwood-ds411.dts
+++ b/arch/arm/boot/dts/kirkwood-ds411.dts
@@ -47,7 +47,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie1 {
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 95af7aa1fdcb..aed20185fd7a 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -187,7 +187,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/kirkwood-km_common.dtsi
index 75dc83914f56..52baffe45f12 100644
--- a/arch/arm/boot/dts/kirkwood-km_common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-km_common.dtsi
@@ -39,7 +39,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/kirkwood-l-50.dts
index 0d81c43a6a73..9fd3581bb24b 100644
--- a/arch/arm/boot/dts/kirkwood-l-50.dts
+++ b/arch/arm/boot/dts/kirkwood-l-50.dts
@@ -223,18 +223,18 @@
};
port@1 {
- reg = <1>;
- label = "lan1";
+ reg = <1>;
+ label = "lan1";
};
port@2 {
- reg = <2>;
- label = "lan6";
+ reg = <2>;
+ label = "lan6";
};
port@3 {
- reg = <3>;
- label = "lan2";
+ reg = <3>;
+ label = "lan2";
};
port@4 {
@@ -254,7 +254,6 @@
port@6 {
reg = <6>;
- label = "cpu";
phy-mode = "rgmii-id";
ethernet = <&eth1port>;
fixed-link {
@@ -282,18 +281,18 @@
};
port@1 {
- reg = <1>;
- label = "lan8";
+ reg = <1>;
+ label = "lan8";
};
port@2 {
- reg = <2>;
- label = "lan4";
+ reg = <2>;
+ label = "lan4";
};
port@3 {
- reg = <3>;
- label = "dmz";
+ reg = <3>;
+ label = "dmz";
};
switch1port5: port@5 {
@@ -330,6 +329,7 @@
ethernet1-port@0 {
speed = <1000>;
duplex = <1>;
+ phy-mode = "rgmii";
};
};
diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts
index 6158214a939a..8c2b540eaf4f 100644
--- a/arch/arm/boot/dts/kirkwood-laplug.dts
+++ b/arch/arm/boot/dts/kirkwood-laplug.dts
@@ -160,7 +160,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/kirkwood-linkstation.dtsi
index 407d6d8b3a7f..b54c9980f636 100644
--- a/arch/arm/boot/dts/kirkwood-linkstation.dtsi
+++ b/arch/arm/boot/dts/kirkwood-linkstation.dtsi
@@ -156,7 +156,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
index 2f9660f3b457..27fd6e2337d5 100644
--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts
+++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
@@ -198,7 +198,7 @@
port@5 {
reg = <5>;
- label = "cpu";
+ phy-mode = "rgmii-id";
ethernet = <&eth0port>;
fixed-link {
speed = <1000>;
@@ -221,6 +221,7 @@
ethernet0-port@0 {
speed = <1000>;
duplex = <1>;
+ phy-mode = "rgmii";
};
};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 7b151acb9984..88b70ba1c8fe 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -10,6 +10,11 @@
ocp@f1000000 {
pinctrl: pin-controller@10000 {
+ /* Non-default UART pins */
+ pmx_uart0: pmx-uart0 {
+ marvell,pins = "mpp4", "mpp5";
+ };
+
pmx_power_hdd: pmx-power-hdd {
marvell,pins = "mpp10";
marvell,function = "gpo";
@@ -213,22 +218,11 @@
&mdio {
status = "okay";
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-
ethphy1: ethernet-phy@8 {
reg = <8>;
};
};
-&eth0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <&ethphy0>;
- };
-};
-
&eth1 {
status = "okay";
ethernet1-port@0 {
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index b80d12f6aa49..e87ea7146546 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -8,10 +8,10 @@
model = "MPL CEC4";
compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood";
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>;
- };
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
@@ -66,8 +66,8 @@
};
};
- i2c@11000 {
- status = "okay";
+ i2c@11000 {
+ status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
@@ -79,7 +79,7 @@
reg = <0x57>;
};
- };
+ };
serial@12000 {
status = "okay";
@@ -208,7 +208,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 2e1a75348908..5a77286136c7 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -149,7 +149,7 @@
port@5 {
reg = <5>;
- label = "cpu";
+ phy-mode = "rgmii-id";
ethernet = <&eth0port>;
fixed-link {
speed = <1000>;
@@ -166,11 +166,12 @@
ethernet0-port@0 {
speed = <1000>;
duplex = <1>;
+ phy-mode = "rgmii";
};
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts
index 6a2934b7d0ce..0b0a15093146 100644
--- a/arch/arm/boot/dts/kirkwood-nas2big.dts
+++ b/arch/arm/boot/dts/kirkwood-nas2big.dts
@@ -131,7 +131,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts
index 3e3ac289e5b0..d5f6bb50ba11 100644
--- a/arch/arm/boot/dts/kirkwood-net2big.dts
+++ b/arch/arm/boot/dts/kirkwood-net2big.dts
@@ -46,11 +46,11 @@
};
clocks {
- g762_clk: g762-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ g762_clk: g762-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
};
diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts
index cba8a2b6f6d9..2497ad26b5b6 100644
--- a/arch/arm/boot/dts/kirkwood-net5big.dts
+++ b/arch/arm/boot/dts/kirkwood-net5big.dts
@@ -78,11 +78,11 @@
};
clocks {
- g762_clk: g762-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ g762_clk: g762-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
netxbig-leds {
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
index b13aee570804..6cf76430cfab 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
@@ -78,11 +78,11 @@
};
clocks {
- g762_clk: g762-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <8192>;
- };
+ g762_clk: g762-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <8192>;
+ };
};
i2c@11000 {
@@ -266,7 +266,7 @@
/* Connected to NEC uPD720200 USB 3.0 controller */
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 9b861c2e76c5..c1799a07816e 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -131,7 +131,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-nsa310s.dts b/arch/arm/boot/dts/kirkwood-nsa310s.dts
new file mode 100644
index 000000000000..49da633a1bc0
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310s.dts
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * ZyXEL NSA310S Board Description
+ * Copyright 2020-2022 Pawel Dembicki <paweldembicki@gmail.com>
+ * Copyright (c) 2015-2021, Tony Dinh <mibodhi@gmail.com>
+ * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk>
+ * Based upon the board setup file created by Peter Schildmann
+ */
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "ZyXEL NSA310S";
+ compatible = "zyxel,nsa310s", "marvell,kirkwood-88f6702", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&pmx_pwr_off>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_buttons>;
+ pinctrl-names = "default";
+
+ power {
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ copy {
+ label = "Copy Button";
+ linux,code = <KEY_COPY>;
+ gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+ };
+
+ reset {
+ label = "Reset Button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_leds>;
+ pinctrl-names = "default";
+
+ led-1 {
+ function = LED_FUNCTION_DISK_ERR;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "usb-host";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_DISK;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "ata1";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-5 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-6 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ usb0_power: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "USB Power";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata1_power: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "SATA1 Power";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ thermal-zones {
+ disk-thermal {
+ polling-delay = <20000>;
+ polling-delay-passive = <2000>;
+
+ thermal-sensors = <&hdd_temp>;
+
+ trips {
+ disk_alert: disk-alert {
+ temperature = <40000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+ disk_crit: disk-crit {
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+
+&eth0 {
+ status = "okay";
+
+ ethernet0-port@0 {
+ phy-handle = <&ethphy0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ rtc@68 {
+ compatible = "htk,ht1382";
+ reg = <0x68>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@1 {
+ reg = <1>;
+ phy-mode = "rgmii-id";
+ marvell,reg-init = <0x1 0x16 0x0 0x3>,
+ <0x1 0x10 0x0 0x1017>,
+ <0x1 0x11 0x0 0x4408>,
+ <0x1 0x16 0x0 0x0>;
+ };
+};
+
+&nand {
+ status = "okay";
+ chip-delay = <35>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0000000 0x00c0000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "uboot_env";
+ reg = <0x00c0000 0x0080000>;
+ };
+ partition@140000 {
+ label = "ubi";
+ reg = <0x0140000 0x7ec0000>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+
+ pmx_buttons: pmx-buttons {
+ marvell,pins = "mpp24", "mpp25", "mpp26";
+ marvell,function = "gpio";
+ };
+
+ pmx_leds: pmx-leds {
+ marvell,pins = "mpp13", "mpp15", "mpp16", "mpp22", "mpp23",
+ "mpp28", "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_power: pmx-power {
+ marvell,pins = "mpp21", "mpp33";
+ marvell,function = "gpio";
+ };
+
+ pmx_pwr_off: pmx-pwr-off {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&sata {
+ status = "okay";
+ nr-ports = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdd_temp: sata-port@0 {
+ reg = <0>;
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts
index b69b096f267b..652405e65006 100644
--- a/arch/arm/boot/dts/kirkwood-nsa320.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa320.dts
@@ -211,7 +211,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/kirkwood-nsa325.dts
index 6f8085dbb1f4..371456de34b2 100644
--- a/arch/arm/boot/dts/kirkwood-nsa325.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa325.dts
@@ -224,7 +224,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi
index 8f73197f251a..ea3d36512e9f 100644
--- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi
@@ -150,7 +150,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
index 712d6042b132..f00325ffde07 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
@@ -31,10 +31,10 @@
pinctrl-0 = <&pmx_usb_power>;
pinctrl-names = "default";
- pmx_usb_power: pmx-usb-power {
- marvell,pins = "mpp10";
- marvell,function = "gpo";
- };
+ pmx_usb_power: pmx-usb-power {
+ marvell,pins = "mpp10";
+ marvell,function = "gpo";
+ };
};
serial@12000 {
@@ -62,43 +62,43 @@
};
regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_usb_power>;
- pinctrl-names = "default";
-
- usb_power: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "USB VBUS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
- };
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_usb_power>;
+ pinctrl-names = "default";
+
+ usb_power: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "USB VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+ };
};
};
&mdio {
- status = "okay";
+ status = "okay";
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
+ ethphy0: ethernet-phy@8 {
+ reg = <8>;
+ };
};
&eth0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <&ethphy0>;
- };
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <&ethphy0>;
+ };
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
index 9d88301daf0e..72edd47e19ff 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
@@ -19,7 +19,7 @@
};
&eth1 {
- status = "disabled";
+ status = "disabled";
};
&switch {
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
index f1f8eee132e8..9d62f910cddf 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -48,7 +48,7 @@
cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
/* No WP GPIO */
};
- };
+ };
};
&nand {
@@ -105,7 +105,7 @@
port@5 {
reg = <5>;
- label = "cpu";
+ phy-mode = "rgmii-id";
ethernet = <&eth0port>;
fixed-link {
speed = <1000>;
@@ -126,7 +126,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts
index c51cea883215..4ad412115a24 100644
--- a/arch/arm/boot/dts/kirkwood-rs212.dts
+++ b/arch/arm/boot/dts/kirkwood-rs212.dts
@@ -43,7 +43,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie1 {
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
index 217bd374e52b..9b6666020cdd 100644
--- a/arch/arm/boot/dts/kirkwood-synology.dtsi
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -198,7 +198,7 @@
spi@10600 {
status = "okay";
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80", "jedec,spi-nor";
@@ -847,7 +847,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts
index fe63b3a03a72..ad093324e075 100644
--- a/arch/arm/boot/dts/kirkwood-t5325.dts
+++ b/arch/arm/boot/dts/kirkwood-t5325.dts
@@ -219,7 +219,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 994cabcf4b51..1939462a5f48 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -86,7 +86,7 @@
status = "okay";
ethphy0: ethernet-phy@X {
- /* overwrite reg property in board file */
+ /* overwrite reg property in board file */
};
};
@@ -98,7 +98,7 @@
};
&pciec {
- status = "okay";
+ status = "okay";
};
&pcie0 {
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fca31a5d5ac7..815ef7719d13 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -24,9 +24,9 @@
};
aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- i2c0 = &i2c0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ i2c0 = &i2c0;
};
mbus@f1000000 {
@@ -279,15 +279,15 @@
clocks = <&gate_clk 8>;
xor00 {
- interrupts = <5>;
- dmacap,memcpy;
- dmacap,xor;
+ interrupts = <5>;
+ dmacap,memcpy;
+ dmacap,xor;
};
xor01 {
- interrupts = <6>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
+ interrupts = <6>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
};
};
@@ -299,15 +299,15 @@
clocks = <&gate_clk 16>;
xor00 {
- interrupts = <7>;
- dmacap,memcpy;
- dmacap,xor;
+ interrupts = <7>;
+ dmacap,memcpy;
+ dmacap,xor;
};
xor01 {
- interrupts = <8>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
+ interrupts = <8>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
};
};
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
new file mode 100644
index 000000000000..0f555eb45bda
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
+ */
+
+/dts-v1/;
+#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
+
+/ {
+ model = "Kontron KSwitch D10 MMT 6G-2GS";
+ compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
+ "microchip,lan9668", "microchip,lan966";
+
+ aliases {
+ i2c0 = &i2c4;
+ i2c1 = &i2c1;
+ };
+
+ sfp0: sfp0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c4>;
+ los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2500>;
+ tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>;
+ rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2500>;
+ tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>;
+ rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&flx1 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c1: i2c@600 {
+ pinctrl-0 = <&fc1_c_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c4: i2c@600 {
+ pinctrl-0 = <&fc4_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+};
+
+&gpio {
+ fc1_c_pins: fc1-c-i2c-pins {
+ /* SCL, SDA */
+ pins = "GPIO_47", "GPIO_48";
+ function = "fc1_c";
+ };
+
+ fc4_b_pins: fc4-b-i2c-pins {
+ /* SCL, SDA */
+ pins = "GPIO_57", "GPIO_58";
+ function = "fc4_b";
+ };
+};
+
+&port2 {
+ phys = <&serdes 2 SERDES6G(0)>;
+ sfp = <&sfp0>;
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&port3 {
+ phys = <&serdes 3 SERDES6G(1)>;
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
new file mode 100644
index 000000000000..5feef9a59a79
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for the Kontron KSwitch D10 MMT 8G
+ */
+
+/dts-v1/;
+#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
+
+/ {
+ model = "Kontron KSwitch D10 MMT 8G";
+ compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
+ "microchip,lan9668", "microchip,lan966";
+};
+
+&mdio0 {
+ phy2: ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ phy3: ethernet-phy@4 {
+ reg = <4>;
+ };
+};
+
+&port2 {
+ phys = <&serdes 2 SERDES6G(0)>;
+ phy-handle = <&phy2>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&port3 {
+ phys = <&serdes 3 SERDES6G(1)>;
+ phy-handle = <&phy3>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
new file mode 100644
index 000000000000..0097e72e3fb2
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common part of the device tree for the Kontron KSwitch D10 MMT
+ */
+
+/dts-v1/;
+#include "lan966x.dtsi"
+#include "dt-bindings/phy/phy-lan966x-serdes.h"
+
+/ {
+ aliases {
+ serial0 = &usart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ usart0: serial@200 {
+ pinctrl-0 = <&usart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "okay";
+
+ spi3: spi@400 {
+ pinctrl-0 = <&fc3_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gpio {
+ fc3_b_pins: fc3-b-pins {
+ /* SCK, MISO, MOSI */
+ pins = "GPIO_51", "GPIO_52", "GPIO_53";
+ function = "fc3_b";
+ };
+
+ miim_c_pins: miim-c-pins {
+ /* MDC, MDIO */
+ pins = "GPIO_59", "GPIO_60";
+ function = "miim_c";
+ };
+
+ sgpio_a_pins: sgpio-a-pins {
+ /* SCK, D0, D1 */
+ pins = "GPIO_32", "GPIO_33", "GPIO_34";
+ function = "sgpio_a";
+ };
+
+ sgpio_b_pins: sgpio-b-pins {
+ /* LD */
+ pins = "GPIO_64";
+ function = "sgpio_b";
+ };
+
+ usart0_pins: usart0-pins {
+ /* RXD, TXD */
+ pins = "GPIO_25", "GPIO_26";
+ function = "fc0_b";
+ };
+
+ usbs_a_pins: usbs-a-pins {
+ /* VBUS_DET */
+ pins = "GPIO_66";
+ function = "gpio";
+ };
+};
+
+&mdio0 {
+ pinctrl-0 = <&miim_c_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+ clock-frequency = <2500000>;
+ status = "okay";
+
+ phy4: ethernet-phy@5 {
+ reg = <5>;
+ coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
+ };
+
+ phy5: ethernet-phy@6 {
+ reg = <6>;
+ coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
+ };
+
+ phy6: ethernet-phy@7 {
+ reg = <7>;
+ coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
+ };
+
+ phy7: ethernet-phy@8 {
+ reg = <8>;
+ coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
+ };
+};
+
+&mdio1 {
+ status = "okay";
+};
+
+&phy0 {
+ status = "okay";
+};
+
+&phy1 {
+ status = "okay";
+};
+
+&port0 {
+ phys = <&serdes 0 CU(0)>;
+ phy-handle = <&phy0>;
+ phy-mode = "gmii";
+ status = "okay";
+};
+
+&port1 {
+ phys = <&serdes 1 CU(1)>;
+ phy-handle = <&phy1>;
+ phy-mode = "gmii";
+ status = "okay";
+};
+
+&port4 {
+ phys = <&serdes 4 SERDES6G(2)>;
+ phy-handle = <&phy4>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&port5 {
+ phys = <&serdes 5 SERDES6G(2)>;
+ phy-handle = <&phy5>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&port6 {
+ phys = <&serdes 6 SERDES6G(2)>;
+ phy-handle = <&phy6>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&port7 {
+ phys = <&serdes 7 SERDES6G(2)>;
+ phy-handle = <&phy7>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&serdes {
+ status = "okay";
+};
+
+&sgpio {
+ pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
+ pinctrl-names = "default";
+ bus-frequency = <8000000>;
+ /* arbitrary range because all GPIOs are in software mode */
+ microchip,sgpio-port-ranges = <0 11>;
+ status = "okay";
+
+ sgpio_in: gpio@0 {
+ ngpios = <128>;
+ };
+
+ sgpio_out: gpio@1 {
+ ngpios = <128>;
+ };
+};
+
+&switch {
+ status = "okay";
+};
+
+&udc {
+ pinctrl-0 = <&usbs_a_pins>;
+ pinctrl-names = "default";
+ atmel,vbus-gpio = <&gpio 66 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/lan966x-pcb8290.dts
new file mode 100644
index 000000000000..8804e8ba5370
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-pcb8290.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Horatiu Vultur <horatiu.vultur@microchip.com>
+ */
+/dts-v1/;
+#include "lan966x.dtsi"
+#include "dt-bindings/phy/phy-lan966x-serdes.h"
+
+/ {
+ model = "Microchip EVB LAN9668";
+ compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
+
+&aes {
+ status = "disabled"; /* Reserved by secure OS */
+};
+
+&gpio {
+ miim_a_pins: mdio-pins {
+ /* MDC, MDIO */
+ pins = "GPIO_28", "GPIO_29";
+ function = "miim_a";
+ };
+
+ pps_out_pins: pps-out-pins {
+ /* 1pps output */
+ pins = "GPIO_38";
+ function = "ptpsync_3";
+ };
+
+ ptp_ext_pins: ptp-ext-pins {
+ /* 1pps input */
+ pins = "GPIO_35";
+ function = "ptpsync_0";
+ };
+
+ udc_pins: ucd-pins {
+ /* VBUS_DET B */
+ pins = "GPIO_8";
+ function = "usb_slave_b";
+ };
+};
+
+&mdio0 {
+ pinctrl-0 = <&miim_a_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ext_phy0: ethernet-phy@7 {
+ reg = <7>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+
+ ext_phy1: ethernet-phy@8 {
+ reg = <8>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+
+ ext_phy2: ethernet-phy@9 {
+ reg = <9>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+
+ ext_phy3: ethernet-phy@10 {
+ reg = <10>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+
+ ext_phy4: ethernet-phy@15 {
+ reg = <15>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+
+ ext_phy5: ethernet-phy@16 {
+ reg = <16>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+
+ ext_phy6: ethernet-phy@17 {
+ reg = <17>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+
+ ext_phy7: ethernet-phy@18 {
+ reg = <18>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
+ };
+};
+
+&port0 {
+ reg = <2>;
+ phy-handle = <&ext_phy2>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0 SERDES6G(1)>;
+ status = "okay";
+};
+
+&port1 {
+ reg = <3>;
+ phy-handle = <&ext_phy3>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1 SERDES6G(1)>;
+ status = "okay";
+};
+
+&port2 {
+ reg = <0>;
+ phy-handle = <&ext_phy0>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2 SERDES6G(1)>;
+ status = "okay";
+};
+
+&port3 {
+ reg = <1>;
+ phy-handle = <&ext_phy1>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3 SERDES6G(1)>;
+ status = "okay";
+};
+
+&port4 {
+ reg = <6>;
+ phy-handle = <&ext_phy6>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4 SERDES6G(2)>;
+ status = "okay";
+};
+
+&port5 {
+ reg = <7>;
+ phy-handle = <&ext_phy7>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5 SERDES6G(2)>;
+ status = "okay";
+};
+
+&port6 {
+ reg = <4>;
+ phy-handle = <&ext_phy4>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 6 SERDES6G(2)>;
+ status = "okay";
+};
+
+&port7 {
+ reg = <5>;
+ phy-handle = <&ext_phy5>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 7 SERDES6G(2)>;
+ status = "okay";
+};
+
+&serdes {
+ status = "okay";
+};
+
+&switch {
+ pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&udc {
+ pinctrl-0 = <&udc_pins>;
+ pinctrl-names = "default";
+ atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
index 3281af90ac6d..3a3d76af8612 100644
--- a/arch/arm/boot/dts/lan966x-pcb8291.dts
+++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
@@ -4,6 +4,7 @@
*/
/dts-v1/;
#include "lan966x.dtsi"
+#include "dt-bindings/phy/phy-lan966x-serdes.h"
/ {
model = "Microchip EVB - LAN9662";
@@ -16,36 +17,70 @@
aliases {
serial0 = &usart3;
};
-};
-&gpio {
- fc_shrd7_pins: fc_shrd7-pins {
- pins = "GPIO_49";
- function = "fc_shrd7";
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ priority = <200>;
};
- fc_shrd8_pins: fc_shrd8-pins {
- pins = "GPIO_54";
- function = "fc_shrd8";
+ leds {
+ compatible = "gpio-leds";
+
+ led-s0-blue {
+ label = "s0:blue";
+ gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-s0-green {
+ label = "s0:green";
+ gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-s1-blue {
+ label = "s1:blue";
+ gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-s1-green {
+ label = "s1:green";
+ gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
};
+};
+
+&aes {
+ status = "disabled"; /* Reserved by secure OS */
+};
- fc3_b_pins: fcb3-spi-pins {
- /* SCK, RXD, TXD */
- pins = "GPIO_51", "GPIO_52", "GPIO_53";
+&gpio {
+ fc3_b_pins: fc3-b-pins {
+ /* RX, TX */
+ pins = "GPIO_52", "GPIO_53";
function = "fc3_b";
};
- can0_b_pins: can0_b_pins {
+ can0_b_pins: can0-b-pins {
/* RX, TX */
pins = "GPIO_35", "GPIO_36";
function = "can0_b";
};
+
+ sgpio_a_pins: sgpio-a-pins {
+ /* SCK, D0, D1, LD */
+ pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
+ function = "sgpio_a";
+ };
};
&can0 {
pinctrl-0 = <&can0_b_pins>;
pinctrl-names = "default";
- status = "okay";
+ status = "disabled"; /* Conflict with switch */
};
&flx3 {
@@ -53,12 +88,60 @@
status = "okay";
usart3: serial@200 {
- pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
+ pinctrl-0 = <&fc3_b_pins>;
pinctrl-names = "default";
status = "okay";
};
};
+&mdio1 {
+ status = "okay";
+};
+
+&phy0 {
+ status = "okay";
+};
+
+&phy1 {
+ status = "okay";
+};
+
+&port0 {
+ phy-handle = <&phy0>;
+ phy-mode = "gmii";
+ phys = <&serdes 0 CU(0)>;
+ status = "okay";
+};
+
+&port1 {
+ phy-handle = <&phy1>;
+ phy-mode = "gmii";
+ phys = <&serdes 1 CU(1)>;
+ status = "okay";
+};
+
+&serdes {
+ status = "okay";
+};
+
+&sgpio {
+ pinctrl-0 = <&sgpio_a_pins>;
+ pinctrl-names = "default";
+ microchip,sgpio-port-ranges = <0 3>, <8 11>;
+ status = "okay";
+
+ gpio@0 {
+ ngpios = <64>;
+ };
+ gpio@1 {
+ ngpios = <64>;
+ };
+};
+
+&switch {
+ status = "okay";
+};
+
&watchdog {
status = "okay";
};
diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts b/arch/arm/boot/dts/lan966x-pcb8309.dts
new file mode 100644
index 000000000000..c436cd20d4b4
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-pcb8309.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x_pcb8309.dts - Device Tree file for PCB8309
+ */
+/dts-v1/;
+#include "lan966x.dtsi"
+#include "dt-bindings/phy/phy-lan966x-serdes.h"
+
+/ {
+ model = "Microchip EVB - LAN9662";
+ compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
+
+ aliases {
+ serial0 = &usart3;
+ i2c102 = &i2c102;
+ i2c103 = &i2c103;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-controls = <&mux>;
+ i2c-parent = <&i2c4>;
+
+ i2c102: i2c-sfp@1 {
+ reg = <1>;
+ };
+
+ i2c103: i2c-sfp@2 {
+ reg = <2>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-s0-green {
+ label = "s0:green";
+ gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-s0-red {
+ label = "s0:red";
+ gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-s1-green {
+ label = "s1:green";
+ gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-s1-red {
+ label = "s1:red";
+ gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /* p11b0 */
+ <&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1 */
+ };
+
+ sfp2: sfp2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c102>;
+ tx-disable-gpios = <&sgpio_out 10 0 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in 2 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 2 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp3: sfp3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c103>;
+ tx-disable-gpios = <&sgpio_out 10 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in 3 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 3 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&aes {
+ status = "disabled"; /* Reserved by secure OS */
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ usart3: serial@200 {
+ pinctrl-0 = <&fc3_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c4: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nic_clk>;
+ pinctrl-0 = <&fc4_b_pins>;
+ pinctrl-names = "default";
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ i2c-sda-hold-time-ns = <1500>;
+ status = "okay";
+ };
+};
+
+&gpio {
+ fc3_b_pins: fc3-b-pins {
+ /* RXD, TXD */
+ pins = "GPIO_52", "GPIO_53";
+ function = "fc3_b";
+ };
+
+ fc4_b_pins: fc4-b-pins {
+ /* SCL, SDA */
+ pins = "GPIO_57", "GPIO_58";
+ function = "fc4_b";
+ };
+
+ sgpio_a_pins: sgpio-a-pins {
+ /* SCK, D0, D1, LD */
+ pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
+ function = "sgpio_a";
+ };
+};
+
+&mdio1 {
+ status = "okay";
+};
+
+&phy0 {
+ status = "okay";
+};
+
+&phy1 {
+ status = "okay";
+};
+
+&port0 {
+ phy-handle = <&phy0>;
+ phy-mode = "gmii";
+ phys = <&serdes 0 CU(0)>;
+ status = "okay";
+};
+
+&port1 {
+ phy-handle = <&phy1>;
+ phy-mode = "gmii";
+ phys = <&serdes 1 CU(1)>;
+ status = "okay";
+};
+
+&port2 {
+ sfp = <&sfp2>;
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ phys = <&serdes 2 SERDES6G(0)>;
+ status = "okay";
+};
+
+&port3 {
+ sfp = <&sfp3>;
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ phys = <&serdes 3 SERDES6G(1)>;
+ status = "okay";
+};
+
+&serdes {
+ status = "okay";
+};
+
+&sgpio {
+ pinctrl-0 = <&sgpio_a_pins>;
+ pinctrl-names = "default";
+ microchip,sgpio-port-ranges = <0 3>, <8 11>;
+ status = "okay";
+
+ gpio@0 {
+ ngpios = <64>;
+ };
+ gpio@1 {
+ ngpios = <64>;
+ };
+};
+
+&switch {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 7d2869648050..05b73f7cf0c7 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -38,7 +38,7 @@
sys_clk: sys_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <162500000>;
+ clock-frequency = <165625000>;
};
cpu_clk: cpu_clk {
@@ -65,7 +65,7 @@
#clock-cells = <1>;
clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
clock-names = "cpu", "ddr", "sys";
- reg = <0xe00c00a8 0x38>;
+ reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
};
timer {
@@ -84,6 +84,84 @@
#size-cells = <1>;
ranges;
+ udc: usb@200000 {
+ compatible = "microchip,lan9662-udc",
+ "atmel,sama5d3-udc";
+ reg = <0x00200000 0x80000>,
+ <0xe0808000 0x400>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>;
+ clock-names = "pclk", "hclk";
+ status = "disabled";
+ };
+
+ switch: switch@e0000000 {
+ compatible = "microchip,lan966x-switch";
+ reg = <0xe0000000 0x0100000>,
+ <0xe2000000 0x0800000>;
+ reg-names = "cpu", "gcb";
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "xtr", "fdma", "ana", "ptp",
+ "ptp-ext";
+ resets = <&reset 0>;
+ reset-names = "switch";
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+
+ port5: port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+
+ port6: port@6 {
+ reg = <6>;
+ status = "disabled";
+ };
+
+ port7: port@7 {
+ reg = <7>;
+ status = "disabled";
+ };
+ };
+ };
+
+ otp: otp@e0021000 {
+ compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc";
+ reg = <0xe0021000 0x300>;
+ };
+
flx0: flexcom@e0040000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe0040000 0x100>;
@@ -92,6 +170,47 @@
#size-cells = <1>;
ranges = <0x0 0xe0040000 0x800>;
status = "disabled";
+
+ usart0: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi0: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+ <&dma0 AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx1: flexcom@e0044000 {
@@ -102,6 +221,47 @@
#size-cells = <1>;
ranges = <0x0 0xe0044000 0x800>;
status = "disabled";
+
+ usart1: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi1: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+ <&dma0 AT91_XDMAC_DT_PERID(4)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
trng: rng@e0048000 {
@@ -114,9 +274,9 @@
compatible = "atmel,at91sam9g46-aes";
reg = <0xe004c000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
- <&dma0 AT91_XDMAC_DT_PERID(12)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
+ <&dma0 AT91_XDMAC_DT_PERID(13)>;
+ dma-names = "tx", "rx";
clocks = <&nic_clk>;
clock-names = "aes_clk";
};
@@ -129,6 +289,47 @@
#size-cells = <1>;
ranges = <0x0 0xe0060000 0x800>;
status = "disabled";
+
+ usart2: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi2: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+ <&dma0 AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
flx3: flexcom@e0064000 {
@@ -144,11 +345,42 @@
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
clocks = <&nic_clk>;
clock-names = "usart";
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi3: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+ <&dma0 AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
dma0: dma-controller@e0068000 {
@@ -178,6 +410,47 @@
#size-cells = <1>;
ranges = <0x0 0xe0070000 0x800>;
status = "disabled";
+
+ usart4: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi4: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+ <&dma0 AT91_XDMAC_DT_PERID(10)>;
+ dma-names = "tx", "rx";
+ clocks = <&nic_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
timer0: timer@e008c000 {
@@ -196,6 +469,11 @@
status = "disabled";
};
+ cpu_ctrl: syscon@e00c0000 {
+ compatible = "microchip,lan966x-cpu-syscon", "syscon";
+ reg = <0xe00c0000 0x350>;
+ };
+
can0: can@e081c000 {
compatible = "bosch,m_can";
reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
@@ -211,10 +489,35 @@
status = "disabled";
};
+ can1: can@e0820000 {
+ compatible = "bosch,m_can";
+ reg = <0xe0820000 0xfc>, <0x00100000 0x8000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&clks GCK_ID_MCAN1>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>;
+ status = "disabled";
+ };
+
+ reset: reset-controller@e200400c {
+ compatible = "microchip,lan966x-switch-reset";
+ reg = <0xe200400c 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ };
+
gpio: pinctrl@e2004064 {
compatible = "microchip,lan966x-pinctrl";
reg = <0xe2004064 0xb4>,
<0xe2010024 0x138>;
+ resets = <&reset 0>;
+ reset-names = "switch";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 78>;
@@ -223,6 +526,81 @@
#interrupt-cells = <2>;
};
+ mdio0: mdio@e2004118 {
+ compatible = "microchip,lan966x-miim";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe2004118 0x24>;
+ clocks = <&sys_clk>;
+ status = "disabled";
+ };
+
+ mdio1: mdio@e200413c {
+ compatible = "microchip,lan966x-miim";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe200413c 0x24>,
+ <0xe2010020 0x4>;
+ clocks = <&sys_clk>;
+ status = "disabled";
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ phy1: ethernet-phy@2 {
+ reg = <2>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ sgpio: gpio@e2004190 {
+ compatible = "microchip,sparx5-sgpio";
+ reg = <0xe2004190 0x118>;
+ clocks = <&sys_clk>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgpio_in: gpio@0 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ sgpio_out: gpio@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ };
+ };
+
+ hwmon: hwmon@e2010180 {
+ compatible = "microchip,lan9668-hwmon";
+ reg = <0xe2010180 0xc>,
+ <0xe20042a8 0xc>;
+ reg-names = "pvt", "fan";
+ clocks = <&sys_clk>;
+ };
+
+ serdes: serdes@e202c000 {
+ compatible = "microchip,lan966x-serdes";
+ reg = <0xe202c000 0x9c>,
+ <0xe2004010 0x4>;
+ #phy-cells = <2>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
index 2a0a98fe67f0..3240c67e0c39 100644
--- a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
@@ -11,3 +11,18 @@
model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb2_2_pins>;
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins = <
+ OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
+ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
+ OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
+ OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
+ OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
+ OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts
index a604d92221a4..c757f0d7781c 100644
--- a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts
@@ -11,3 +11,18 @@
model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
};
+
+&omap3_pmx_core2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb2_2_pins>;
+ hsusb2_2_pins: pinmux_hsusb2_2_pins {
+ pinctrl-single,pins = <
+ OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
+ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
+ OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
+ OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
+ OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
+ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi
index b56524cc7fe2..9ba0ea4eb48a 100644
--- a/arch/arm/boot/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi
@@ -27,6 +27,8 @@
/* HS USB Host PHY on PORT 1 */
hsusb2_phy: hsusb2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb2_reset_pin>;
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
#phy-cells = <0>;
@@ -144,6 +146,8 @@
};
&usbhshost {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb2_pins>;
port2-mode = "ehci-phy";
};
@@ -151,10 +155,7 @@
phys = <0 &hsusb2_phy>;
};
-
&omap3_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_pins>;
mmc3_pins: pinmux_mm3_pins {
pinctrl-single,pins = <
@@ -250,8 +251,7 @@
};
&omap3_pmx_wkup {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_reset_pin>;
+
hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
@@ -265,21 +265,6 @@
};
};
-&omap3_pmx_core2 {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_2_pins>;
- hsusb2_2_pins: pinmux_hsusb2_2_pins {
- pinctrl-single,pins = <
- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
- >;
- };
-};
-
&uart2 {
interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
index b4664ab00256..e0cbac500e17 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
@@ -59,7 +59,7 @@
};
};
- pwm10: dmtimer-pwm {
+ pwm10: pwm-10 {
compatible = "ti,omap-dmtimer-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
@@ -118,8 +118,8 @@
gpmc,device-width = <2>;
gpmc,wait-pin = <0>;
gpmc,burst-length = <4>;
- gpmc,cycle2cycle-samecsen = <1>;
- gpmc,cycle2cycle-diffcsen = <1>;
+ gpmc,cycle2cycle-samecsen;
+ gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <45>;
gpmc,cs-wr-off-ns = <45>;
diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index 3a5228562b0d..72b5af475d09 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -20,7 +20,7 @@
leds {
compatible = "gpio-leds";
- user0 {
+ led-user0 {
label = "user0";
gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
linux,default-trigger = "none";
diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi
index 10b8249b8ab6..1bb686a7b3ec 100644
--- a/arch/arm/boot/dts/lpc18xx.dtsi
+++ b/arch/arm/boot/dts/lpc18xx.dtsi
@@ -121,7 +121,7 @@
status = "disabled";
};
- usb0: ehci@40006100 {
+ usb0: usb@40006100 {
compatible = "nxp,lpc1850-ehci", "generic-ehci";
reg = <0x40006100 0x100>;
interrupts = <8>;
@@ -133,7 +133,7 @@
status = "disabled";
};
- usb1: ehci@40007100 {
+ usb1: usb@40007100 {
compatible = "nxp,lpc1850-ehci", "generic-ehci";
reg = <0x40007100 0x100>;
interrupts = <9>;
@@ -183,7 +183,7 @@
compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
reg = <0x40010000 0x2000>;
interrupts = <5>;
- interrupt-names = "macirq";
+ interrupt-names = "macirq";
clocks = <&ccu1 CLK_CPU_ETHERNET>;
clock-names = "stmmaceth";
resets = <&rgu 22>;
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index c87066d6c995..974410918f35 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -315,7 +315,7 @@
/* System Control Block */
scb {
compatible = "simple-bus";
- ranges = <0x0 0x040004000 0x00001000>;
+ ranges = <0x0 0x40004000 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/ls1021a-iot.dts
new file mode 100644
index 000000000000..ce8e26d7791f
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-iot.dts
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021-2022 NXP
+ *
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "LS1021A-IOT Board";
+ compatible = "fsl,ls1021a-iot", "fsl,ls1021a";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ reg_3p3v: regulator-3V3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_2p5v: regulator-2V5 {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ frame-master;
+ bitclock-master;
+ };
+ };
+};
+
+&can0{
+ status = "disabled";
+};
+
+&can1{
+ status = "disabled";
+};
+
+&can2{
+ status = "disabled";
+};
+
+&can3{
+ status = "okay";
+};
+
+&dcu {
+ display = <&display>;
+ status = "okay";
+
+ display: display@0 {
+ bits-per-pixel = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+
+ timing0: mode0 {
+ clock-frequency = <25000000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <80>;
+ hfront-porch = <80>;
+ vback-porch = <16>;
+ vfront-porch = <16>;
+ hsync-len = <12>;
+ vsync-len = <2>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+};
+
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ fixed-link = <0 1 1000 0 0>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
+&esdhc{
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9555: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sgtl5000: audio-codec@2a {
+ #sound-dai-cells = <0x0>;
+ compatible = "fsl,sgtl5000";
+ reg = <0x2a>;
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_2p5v>;
+ clocks = <&sys_mclk>;
+ };
+
+ max1239: adc@35 {
+ compatible = "maxim,max1239";
+ reg = <0x35>;
+ #io-channel-cells = <1>;
+ };
+
+ ina2201: core-monitor@44 {
+ compatible = "ti,ina220";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+
+ ina2202: current-monitor@45 {
+ compatible = "ti,ina220";
+ reg = <0x45>;
+ shunt-resistor = <1000>;
+ };
+
+ lm75b: thermal-monitor@48 {
+ compatible = "national,lm75b";
+ reg = <0x48>;
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&mdio0 {
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ tbi1: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&qspi {
+ num-cs = <2>;
+ status = "okay";
+
+ s25fl128s: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
index f3ddea934f1b..d2cae8c7d7a6 100644
--- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -30,11 +30,11 @@
};
reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
leds {
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2e69d6eab4d1..49c78c84cd5d 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -122,13 +122,20 @@
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
};
- ifc: ifc@1530000 {
- compatible = "fsl,ifc", "simple-bus";
+ ifc: memory-controller@1530000 {
+ compatible = "fsl,ifc";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+ sfp: efuse@1e80000 {
+ compatible = "fsl,ls1021a-sfp";
+ reg = <0x0 0x1e80000 0x0 0x10000>;
+ clocks = <&clockgen 4 3>;
+ clock-names = "sfp";
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x1000>;
@@ -192,7 +199,7 @@
<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-map-mask = <0xffffffff 0x0>;
+ interrupt-map-mask = <0x7 0x0>;
};
};
@@ -640,7 +647,7 @@
status = "disabled";
};
- edma0: edma@2c00000 {
+ edma0: dma-controller@2c00000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x0 0x2c00000 0x0 0x10000>,
@@ -859,6 +866,7 @@
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
+ status = "disabled";
};
can1: can@2a80000 {
@@ -868,6 +876,7 @@
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
+ status = "disabled";
};
can2: can@2a90000 {
@@ -877,6 +886,7 @@
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
+ status = "disabled";
};
can3: can@2aa0000 {
@@ -886,6 +896,7 @@
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
+ status = "disabled";
};
ocram1: sram@10000000 {
diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi
new file mode 100644
index 000000000000..5bf831b072d6
--- /dev/null
+++ b/arch/arm/boot/dts/mba6ulx.dtsi
@@ -0,0 +1,569 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/ {
+ model = "TQ-Systems MBA6ULx Baseboard";
+
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc1;
+ rtc0 = &rtc0;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&reg_mba6ul_3v3>;
+ enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ beeper: beeper {
+ compatible = "gpio-beeper";
+ gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio_buttons: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_buttons>;
+
+ button1 {
+ label = "s14";
+ linux,code = <KEY_1>;
+ gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ button2 {
+ label = "s6";
+ linux,code = <KEY_2>;
+ gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button3 {
+ label = "s7";
+ linux,code = <KEY_3>;
+ gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ power-button {
+ label = "POWER";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ gpio-key,wakeup;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ led1 {
+ label = "led1";
+ gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_lcd_pwr: regulator-lcd-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-pwr";
+ gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ reg_mba6ul_3v3: regulator-mba6ul-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "supply-mba6ul-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_mba6ul_5v0: regulator-mba6ul-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "supply-mba6ul-5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_mpcie: regulator-mpcie-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "mpcie-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ startup-delay-us = <500000>;
+ vin-supply = <&reg_mba6ul_3v3>;
+ };
+
+ reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 {
+ compatible = "regulator-fixed";
+ gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "otg2-vbus-supply-5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_mpcie>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x6000000>;
+ linux,cma-default;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-tlv320aic32x4";
+ model = "imx-audio-tlv320aic32x4";
+ ssi-controller = <&sai1>;
+ audio-codec = <&tlv320aic32x4>;
+ audio-asrc = <&asrc>;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_mba6ul_3v3>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_mba6ul_3v3>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <768000000>;
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ num-cs = <1>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy0>;
+ phy-supply = <&reg_mba6ul_3v3>;
+ phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <25>;
+ phy-reset-post-delay = <1>;
+ status = "okay";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy1>;
+ phy-supply = <&reg_mba6ul_3v3>;
+ phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <25>;
+ phy-reset-post-delay = <1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ reg = <0>;
+ max-speed = <100>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ reg = <1>;
+ max-speed = <100>;
+ };
+ };
+};
+
+&i2c4 {
+ tlv320aic32x4: audio-codec@18 {
+ compatible = "ti,tlv320aic32x4";
+ reg = <0x18>;
+ clocks = <&clks IMX6UL_CLK_SAI1>;
+ clock-names = "mclk";
+ ldoin-supply = <&reg_mba6ul_3v3>;
+ iov-supply = <&reg_mba6ul_3v3>;
+ };
+
+ jc42: temperature-sensor@19 {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x19>;
+ };
+
+ expander_out0: gpio-expander@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ expander_in0: gpio-expander@21 {
+ compatible = "nxp,pca9554";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_expander_in0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ enet1_int-hog {
+ gpio-hog;
+ gpios = <6 0>;
+ input;
+ };
+
+ enet2_int-hog {
+ gpio-hog;
+ gpios = <7 0>;
+ input;
+ };
+ };
+
+ expander_out1: gpio-expander@22 {
+ compatible = "nxp,pca9554";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ analog_touch: touchscreen@41 {
+ compatible = "st,stmpe811";
+ reg = <0x41>;
+ interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio4>;
+ interrupt-controller;
+ status = "disabled";
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
+ st,ave-ctrl = <3>; /* 8 sample average control */
+ st,fraction-z = <7>; /* 7 length fractional part in z */
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ st,mod-12b = <1>; /* 12-bit ADC */
+ st,ref-sel = <0>; /* internal ADC reference */
+ st,sample-time = <4>; /* ADC converstion time: 80 clocks */
+ st,settling = <3>; /* 1 ms panel driver settling time */
+ st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */
+ };
+ };
+
+ /* NXP SE97BTP with temperature sensor + eeprom */
+ se97b: eeprom@51 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
+ <&clks IMX6UL_CLK_SAI1>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <24000000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ /* for DTE mode, add below change */
+ /* fsl,dte-mode; */
+ /* pinctrl-0 = <&pinctrl_uart6dte>; */
+ uart-has-rtscts;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+ status = "okay";
+};
+
+/* otg-port */
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ power-active-high;
+ over-current-active-low;
+ /* we implement only dual role but not a fully featured OTG */
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+/* 7-port usb hub */
+/* id, pwr, oc pins not connected */
+&usbotg2 {
+ disable-over-current;
+ vbus-supply = <&reg_otg2vbus_5v0>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_mba6ul_3v3>;
+ vqmmc-supply = <&reg_vccsd>;
+ no-1-8-v;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog1>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_buttons: buttonsgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020
+ MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020
+ MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020
+ MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8
+ >;
+ };
+
+ pinctrl_enet2_mdc: enet2mdcgrp {
+ fsl,pins = <
+ /* mdio */
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_expander_in0: expanderin0grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ /* 100 k PD, DSE 120 OHM, SPPEED LO */
+ MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1
+ MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1
+ MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
+ MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
+ MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart6: uart6grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
+ MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
+ MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
+ MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart6dte: uart6dte {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1
+ MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1
+ MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1
+ MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059
+ MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0
+ MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059
+ /* WP */
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
+ /* CD */
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9
+ /* WP */
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
+ /* CD */
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9
+ /* WP */
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
+ /* CD */
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
+ >;
+ };
+
+ pinctrl_wdog1: wdog1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 26eaba3fa96f..8e3860d5d916 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -214,14 +214,14 @@
ranges = <0x0 0xc8100000 0x100000>;
ao_arc_rproc: remoteproc@1c {
- compatible= "amlogic,meson-mx-ao-arc";
+ compatible = "amlogic,meson-mx-ao-arc";
reg = <0x1c 0x8>, <0x38 0x8>;
reg-names = "remap", "cpu";
status = "disabled";
};
ir_receiver: ir-receiver@480 {
- compatible= "amlogic,meson6-ir";
+ compatible = "amlogic,meson6-ir";
reg = <0x480 0x20>;
interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
index 61ec929ab86e..c6d1c5a8a3bf 100644
--- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts
+++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
@@ -27,7 +27,7 @@
gpio-leds {
compatible = "gpio-leds";
- blue {
+ led-blue {
label = "x8:blue:power";
gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>;
};
@@ -65,7 +65,7 @@
pinctrl-0 = <&spi_nor_pins>;
pinctrl-names = "default";
- spi-flash@0 {
+ flash@0 {
compatible = "mxicy,mx25l1606e";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 9997a5d0333a..4f22ab451aae 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -133,7 +133,7 @@
};
};
- gpu_opp_table: gpu-opp-table {
+ gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-182142857 {
@@ -430,7 +430,7 @@
};
&ao_arc_rproc {
- compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
+ compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
amlogic,secbus2 = <&secbus2>;
sram = <&ao_arc_sram>;
resets = <&reset RESET_MEDIA_CPU>;
@@ -506,6 +506,15 @@
};
};
+ sdxc_a_pins: sdxc-a {
+ mux {
+ groups = "sdxc_d0_a", "sdxc_d13_a",
+ "sdxc_clk_a", "sdxc_cmd_a";
+ function = "sdxc_a";
+ bias-pull-up;
+ };
+ };
+
sdxc_b_pins: sdxc-b {
mux {
groups = "sdxc_d0_b", "sdxc_d13_b",
@@ -568,6 +577,14 @@
bias-disable;
};
};
+
+ xtal_32k_out_pins: xtal-32k-out {
+ mux {
+ groups = "xtal_32k_out";
+ function = "xtal";
+ bias-disable;
+ };
+ };
};
};
@@ -651,6 +668,9 @@
arm,filter-ranges = <0x100000 0xc0000000>;
prefetch-data = <1>;
prefetch-instr = <1>;
+ arm,prefetch-offset = <7>;
+ arm,double-linefill = <1>;
+ arm,prefetch-drop = <1>;
arm,shared-override;
};
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index 77d4beeb8010..3da47349eaaf 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -73,7 +73,7 @@
leds {
compatible = "gpio-leds";
- power {
+ led-power {
label = "ec100:red:power";
/*
* Needs to go LOW (together with the poweroff GPIO)
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 04356bc639fa..941682844faf 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -34,7 +34,7 @@
leds {
compatible = "gpio-leds";
- blue {
+ led-blue {
label = "c1:blue:alive";
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
@@ -281,19 +281,6 @@
"J7 Header Pin 6", "J7 Header Pin 5",
"J7 Header Pin 7", "HDMI_CEC",
"SYS_LED", "", "";
-
- /*
- * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal
- * to be turned high in order to be detected by the USB Controller.
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- usb-hub {
- gpio-hog;
- gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
};
&ir_receiver {
@@ -381,5 +368,16 @@
};
&usb1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
+
+ hub@1 {
+ /* Genesys Logic GL852G usb hub */
+ compatible = "usb5e3,610";
+ reg = <1>;
+ vdd-supply = <&p5v0>;
+ reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ };
};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 94f1c03decce..5979209fe91e 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -125,7 +125,7 @@
};
};
- gpu_opp_table: gpu-opp-table {
+ gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-255000000 {
@@ -384,7 +384,7 @@
};
&ao_arc_rproc {
- compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
+ compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
amlogic,secbus2 = <&secbus2>;
sram = <&ao_arc_sram>;
resets = <&reset RESET_MEDIA_CPU>;
@@ -580,8 +580,8 @@
};
&gpio_intc {
- compatible = "amlogic,meson-gpio-intc",
- "amlogic,meson8b-gpio-intc";
+ compatible = "amlogic,meson8b-gpio-intc",
+ "amlogic,meson-gpio-intc";
status = "okay";
};
@@ -643,6 +643,9 @@
arm,filter-ranges = <0x100000 0xc0000000>;
prefetch-data = <1>;
prefetch-instr = <1>;
+ arm,prefetch-offset = <7>;
+ arm,double-linefill = <1>;
+ arm,prefetch-drop = <1>;
arm,shared-override;
};
diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
index fa6d55f1cfb9..aa4d4bf70629 100644
--- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
+++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
@@ -19,7 +19,6 @@
ethernet0 = &ethmac;
i2c0 = &i2c_AO;
serial0 = &uart_AO;
- serial1 = &uart_A;
mmc0 = &sd_card_slot;
};
@@ -45,12 +44,32 @@
};
};
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+
+ pinctrl-0 = <&xtal_32k_out_pins>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>,
+ <&gpio_ao GPIOAO_6 GPIO_ACTIVE_LOW>;
+
+ clocks = <&xtal_32k_out>;
+ clock-names = "ext_clock";
+ };
+
vcc_3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ xtal_32k_out: xtal-32k-out-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32k_out";
+ };
};
&cpu0 {
@@ -192,6 +211,27 @@
vref-supply = <&vddio_ao1v8>;
};
+/* SDIO wifi */
+&sdhc {
+ status = "okay";
+
+ pinctrl-0 = <&sdxc_a_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <4>;
+ max-frequency = <50000000>;
+
+ disable-wp;
+ non-removable;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_3v3>;
+};
+
&sdio {
status = "okay";
@@ -222,6 +262,12 @@
pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm20702a1";
+ shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ };
};
&uart_AO {
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 46984d4c5224..987d792f67ea 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -275,7 +275,9 @@
compatible = "marvell,pdma-1.0";
reg = <0xd4000000 0x10000>;
interrupts = <48>;
+ /* For backwards compatibility: */
#dma-channels = <16>;
+ dma-channels = <16>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi
index c7a1f3ffc48c..f7cc8fc678fa 100644
--- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi
+++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi
@@ -133,7 +133,7 @@
dais = <&mcbsp2_port>, <&mcbsp3_port>;
};
- pwm8: dmtimer-pwm-8 {
+ pwm8: pwm-8 {
pinctrl-names = "default";
pinctrl-0 = <&vibrator_direction_pin>;
@@ -143,7 +143,7 @@
ti,clock-source = <0x01>;
};
- pwm9: dmtimer-pwm-9 {
+ pwm9: pwm-9 {
pinctrl-names = "default";
pinctrl-0 = <&vibrator_enable_pin>;
diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts
index eb5291b0ee3a..e07b807b4cec 100644
--- a/arch/arm/boot/dts/moxart-uc7112lx.dts
+++ b/arch/arm/boot/dts/moxart-uc7112lx.dts
@@ -79,7 +79,7 @@
clocks = <&ref12>;
};
-&sdhci {
+&mmc {
status = "okay";
};
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
index f5f070a87482..11cbea5b94d2 100644
--- a/arch/arm/boot/dts/moxart.dtsi
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -93,8 +93,8 @@
clock-names = "PCLK";
};
- sdhci: sdhci@98e00000 {
- compatible = "moxa,moxart-sdhci";
+ mmc: mmc@98e00000 {
+ compatible = "moxa,moxart-mmc";
reg = <0x98e00000 0x5C>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_apb>;
@@ -138,7 +138,7 @@
status = "disabled";
};
- uart0: uart@98200000 {
+ uart0: serial@98200000 {
compatible = "ns16550a";
reg = <0x98200000 0x20>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index c26ba9b7b6dd..3eeafd8c7121 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -174,7 +174,7 @@
status = "disabled";
};
- pm_uart: uart@221000 {
+ pm_uart: serial@221000 {
compatible = "ns16550a";
reg = <0x221000 0x100>;
reg-shift = <3>;
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4776f85d6d5b..ce6a4015fed5 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -178,7 +178,6 @@
compatible = "mediatek,mt2701-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
- pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -360,7 +359,7 @@
mediatek,apmixedsys = <&apmixedsys>;
};
- nandc: nfi@1100d000 {
+ nandc: nand-controller@1100d000 {
compatible = "mediatek,mt2701-nfc";
reg = <0 0x1100d000 0 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
@@ -427,9 +426,9 @@
afe: audio-controller {
compatible = "mediatek,mt2701-audio";
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
+ interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
@@ -559,12 +558,11 @@
compatible = "mediatek,mt2701-jpgdec";
reg = <0 0x15004000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
+ clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
@@ -574,10 +572,9 @@
"mediatek,mtk-jpgenc";
reg = <0 0x1500a000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&imgsys CLK_IMG_VENC>;
+ clocks = <&imgsys CLK_IMG_VENC>;
clock-names = "jpgenc";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
<&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
};
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index f4848362b3be..11379c3e6b4c 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -241,7 +241,7 @@
};
pericfg: syscon@10003000 {
- compatible = "mediatek,mt7623-pericfg",
+ compatible = "mediatek,mt7623-pericfg",
"mediatek,mt2701-pericfg",
"syscon";
reg = <0 0x10003000 0 0x1000>;
@@ -253,7 +253,6 @@
compatible = "mediatek,mt7623-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
- pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -628,9 +627,9 @@
afe: audio-controller {
compatible = "mediatek,mt7623-audio",
"mediatek,mt2701-audio";
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
+ interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
index 13c86936d1c8..e8b4b6d30d19 100644
--- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
+++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
@@ -45,13 +45,13 @@
pinctrl-names = "default";
pinctrl-0 = <&key_pins_a>;
- factory {
+ button-factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 256 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mt7623a-rfb-nand.dts
index 88d8f0b2f4c2..61f5da68d4b0 100644
--- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts
+++ b/arch/arm/boot/dts/mt7623a-rfb-nand.dts
@@ -45,13 +45,13 @@
pinctrl-names = "default";
pinctrl-0 = <&key_pins_a>;
- factory {
+ button-factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 256 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
index 027c1b0c6a98..ece61a6a7a89 100644
--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -91,13 +91,13 @@
pinctrl-names = "default";
pinctrl-0 = <&key_pins_a>;
- factory {
+ button-factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 256 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
@@ -322,6 +322,12 @@
vqmmc-supply = <&reg_3p3v>;
};
+&mt6323keys {
+ home {
+ status = "disabled";
+ };
+};
+
&mt6323_leds {
status = "okay";
diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
index 1b9b9a8145a7..bf67a8e9be59 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
@@ -60,13 +60,13 @@
pinctrl-names = "default";
pinctrl-0 = <&key_pins_a>;
- factory {
+ button-factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 256 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi
index bcb0846e29fd..3adab5cd1fef 100644
--- a/arch/arm/boot/dts/mt7623n.dtsi
+++ b/arch/arm/boot/dts/mt7623n.dtsi
@@ -121,7 +121,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
@@ -144,7 +143,6 @@
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_OVL>;
iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
- mediatek,larb = <&larb0>;
};
rdma0: rdma@14008000 {
@@ -154,7 +152,6 @@
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
- mediatek,larb = <&larb0>;
};
wdma@14009000 {
@@ -164,7 +161,6 @@
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_WDMA>;
iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
- mediatek,larb = <&larb0>;
};
bls: pwm@1400a000 {
@@ -215,7 +211,6 @@
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb0>;
};
dpi0: dpi@14014000 {
diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
index eb536cbebd9b..84e14bee7235 100644
--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
@@ -23,13 +23,13 @@
gpio-keys {
compatible = "gpio-keys";
- reset {
+ button-reset {
label = "factory";
linux,code = <KEY_RESTART>;
gpios = <&pio 60 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 58 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
index 46fc236e1b89..acab0883a3bb 100644
--- a/arch/arm/boot/dts/mt7629.dtsi
+++ b/arch/arm/boot/dts/mt7629.dtsi
@@ -106,8 +106,7 @@
compatible = "mediatek,mt7629-timer",
"mediatek,mt6765-timer";
reg = <0x10009000 0x60>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk20m>;
clock-names = "clk20m";
};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index a031b3636318..0f291ad22d3a 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -152,7 +152,6 @@
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
- pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/mxs-pinfunc.h
index c6da987b20cb..31297abcbc71 100644
--- a/arch/arm/boot/dts/mxs-pinfunc.h
+++ b/arch/arm/boot/dts/mxs-pinfunc.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX28 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MXS_PINCTRL_H__
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
index 41744cc2bc72..01e1bb7c3c6c 100644
--- a/arch/arm/boot/dts/nspire-classic.dtsi
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -17,7 +17,7 @@
&fast_timer {
/* compatible = "lsi,zevio-timer"; */
- reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
+ reg = <0x90010000 0x1000>, <0x900a0010 0x8>;
};
&uart {
@@ -30,12 +30,12 @@
&timer0 {
/* compatible = "lsi,zevio-timer"; */
- reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
+ reg = <0x900c0000 0x1000>, <0x900a0018 0x8>;
};
&timer1 {
compatible = "lsi,zevio-timer";
- reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+ reg = <0x900d0000 0x1000>, <0x900a0020 0x8>;
};
&keypad {
@@ -66,10 +66,10 @@
#address-cells = <1>;
#size-cells = <1>;
- intc: interrupt-controller@DC000000 {
+ intc: interrupt-controller@dc000000 {
compatible = "lsi,zevio-intc";
interrupt-controller;
- reg = <0xDC000000 0x1000>;
+ reg = <0xdc000000 0x1000>;
#interrupt-cells = <1>;
};
};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
index 0c16b04e2744..590b7dff6ae5 100644
--- a/arch/arm/boot/dts/nspire-cx.dts
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -92,10 +92,10 @@
#address-cells = <1>;
#size-cells = <1>;
- intc: interrupt-controller@DC000000 {
+ intc: interrupt-controller@dc000000 {
compatible = "arm,pl190-vic";
interrupt-controller;
- reg = <0xDC000000 0x1000>;
+ reg = <0xdc000000 0x1000>;
#interrupt-cells = <1>;
};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
index 90e033d9141f..bb240e6a3a6f 100644
--- a/arch/arm/boot/dts/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -20,9 +20,9 @@
reg = <0x00000000 0x80000>;
};
- sram: sram@A4000000 {
+ sram: sram@a4000000 {
device = "memory";
- reg = <0xA4000000 0x20000>;
+ reg = <0xa4000000 0x20000>;
};
timer_clk: timer_clk {
@@ -33,12 +33,12 @@
base_clk: base_clk {
#clock-cells = <0>;
- reg = <0x900B0024 0x4>;
+ reg = <0x900b0024 0x4>;
};
ahb_clk: ahb_clk {
#clock-cells = <0>;
- reg = <0x900B0024 0x4>;
+ reg = <0x900b0024 0x4>;
clocks = <&base_clk>;
};
@@ -71,28 +71,28 @@
#size-cells = <1>;
ranges;
- spi: spi@A9000000 {
- reg = <0xA9000000 0x1000>;
+ spi: spi@a9000000 {
+ reg = <0xa9000000 0x1000>;
};
- usb0: usb@B0000000 {
+ usb0: usb@b0000000 {
compatible = "lsi,zevio-usb";
- reg = <0xB0000000 0x1000>;
+ reg = <0xb0000000 0x1000>;
interrupts = <8>;
usb-phy = <&usb_phy>;
vbus-supply = <&vbus_reg>;
};
- usb1: usb@B4000000 {
- reg = <0xB4000000 0x1000>;
+ usb1: usb@b4000000 {
+ reg = <0xb4000000 0x1000>;
interrupts = <9>;
status = "disabled";
};
- lcd: lcd@C0000000 {
+ lcd: lcd@c0000000 {
compatible = "arm,pl111", "arm,primecell";
- reg = <0xC0000000 0x1000>;
+ reg = <0xc0000000 0x1000>;
interrupts = <21>;
/*
@@ -105,17 +105,17 @@
clock-names = "clcdclk", "apb_pclk";
};
- adc: adc@C4000000 {
- reg = <0xC4000000 0x1000>;
+ adc: adc@c4000000 {
+ reg = <0xc4000000 0x1000>;
interrupts = <11>;
};
- tdes: crypto@C8010000 {
- reg = <0xC8010000 0x1000>;
+ tdes: crypto@c8010000 {
+ reg = <0xc8010000 0x1000>;
};
- sha256: crypto@CC000000 {
- reg = <0xCC000000 0x1000>;
+ sha256: crypto@cc000000 {
+ reg = <0xcc000000 0x1000>;
};
apb@90000000 {
@@ -143,16 +143,16 @@
interrupts = <1>;
};
- timer0: timer@900C0000 {
- reg = <0x900C0000 0x1000>;
+ timer0: timer@900c0000 {
+ reg = <0x900c0000 0x1000>;
clocks = <&timer_clk>, <&timer_clk>,
<&timer_clk>;
clock-names = "timer0clk", "timer1clk",
"apb_pclk";
};
- timer1: timer@900D0000 {
- reg = <0x900D0000 0x1000>;
+ timer1: timer@900d0000 {
+ reg = <0x900d0000 0x1000>;
interrupts = <19>;
clocks = <&timer_clk>, <&timer_clk>,
<&timer_clk>;
@@ -171,18 +171,18 @@
interrupts = <4>;
};
- misc: misc@900A0000 {
- reg = <0x900A0000 0x1000>;
+ misc: misc@900a0000 {
+ reg = <0x900a0000 0x1000>;
};
- pwr: pwr@900B0000 {
- reg = <0x900B0000 0x1000>;
+ pwr: pwr@900b0000 {
+ reg = <0x900b0000 0x1000>;
interrupts = <15>;
};
- keypad: input@900E0000 {
+ keypad: input@900e0000 {
compatible = "ti,nspire-keypad";
- reg = <0x900E0000 0x1000>;
+ reg = <0x900e0000 0x1000>;
interrupts = <16>;
scan-interval = <1000>;
@@ -191,8 +191,8 @@
clocks = <&apb_pclk>;
};
- contrast: contrast@900F0000 {
- reg = <0x900F0000 0x1000>;
+ contrast: contrast@900f0000 {
+ reg = <0x900f0000 0x1000>;
};
led: led@90110000 {
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 3696980a3da1..c7b5ef15b716 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -110,6 +110,7 @@
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
};
clk: clock-controller@f0801000 {
@@ -128,7 +129,7 @@
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
ethernet = <0>;
- clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
+ clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
clock-names = "stmmaceth", "clk_gmac";
pinctrl-names = "default";
pinctrl-0 = <&rg1_pins
diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts
index eb6eb21cb2a4..9e9eba8bad5e 100644
--- a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts
@@ -358,7 +358,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0cs1_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
@@ -366,7 +366,7 @@
spi-max-frequency = <20000000>;
spi-rx-bus-width = <2>;
label = "bmc";
- partitions@80000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -406,7 +406,7 @@
pinctrl-0 = <&spi3_pins>, <&spi3cs1_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
@@ -416,7 +416,7 @@
m25p,fast-read;
label = "pnor";
};
- spi-nor@1 {
+ flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
index d4ff49939a3d..2a394cc15284 100644
--- a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts
@@ -135,14 +135,14 @@
pinctrl-0 = <&spi0cs1_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-rx-bus-width = <2>;
- partitions@80000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts
index 82a104b2a65f..f7b38bee039b 100644
--- a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts
@@ -380,7 +380,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0cs1_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
@@ -388,7 +388,7 @@
spi-max-frequency = <5000000>;
spi-rx-bus-width = <2>;
label = "bmc";
- partitions@80000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -415,14 +415,14 @@
};
};
};
- spi-nor@1 {
+ flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <5000000>;
spi-rx-bus-width = <2>;
- partitions@88000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -440,14 +440,14 @@
&fiu3 {
pinctrl-0 = <&spi3_pins>;
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <5000000>;
spi-rx-bus-width = <2>;
- partitions@A0000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index 0334641f8829..f53d45fa1de8 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -67,14 +67,14 @@
&fiu0 {
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width = <2>;
reg = <0>;
spi-max-frequency = <5000000>;
- partitions@80000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -128,14 +128,14 @@
&fiu3 {
pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width = <2>;
reg = <0>;
spi-max-frequency = <5000000>;
- partitions@A0000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -324,7 +324,7 @@
&spi0 {
cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
status = "okay";
- Flash@0 {
+ flash@0 {
compatible = "winbond,w25q128",
"jedec,spi-nor";
reg = <0x0>;
@@ -345,7 +345,7 @@
&spi1 {
cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
status = "okay";
- Flash@0 {
+ flash@0 {
compatible = "winbond,w25q128fw",
"jedec,spi-nor";
reg = <0x0>;
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts
index 767e0ac0df7c..87359ab05db3 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts
@@ -100,14 +100,14 @@
pinctrl-0 = <&spi0cs1_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-rx-bus-width = <2>;
- partitions@80000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -139,14 +139,14 @@
};
};
- spi-nor@1 {
+ flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
npcm,fiu-rx-bus-width = <2>;
- partitions@88000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -166,14 +166,14 @@
pinctrl-0 = <&spi3_pins>;
status = "okay";
- spi-nor@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-rx-bus-width = <2>;
- partitions@A0000000 {
+ partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 13eee0fe5642..30eed40b89b5 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -51,7 +51,7 @@
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
ethernet = <1>;
- clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
+ clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
clock-names = "stmmaceth", "clk_gmac";
pinctrl-names = "default";
pinctrl-0 = <&rg2_pins
diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts
index 3ee61251a16d..b78c116cbc18 100644
--- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts
+++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts
@@ -15,6 +15,11 @@
model = "Supermicro X9SCi-LN4F BMC";
compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450";
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -53,6 +58,33 @@
};
};
+&fiu {
+ status = "okay";
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ };
+};
+
+&gpio0 {
+ gpio-line-names =
+ /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "",
+ /* 8 */ "", "", "", "", "power-chassis-control-n", "", "uid-button", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid",
+ /* 8 */ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ /* 0 */ "", "", "", "", "", "", "", "",
+ /* 8 */ "", "", "", "", "", "", "", "power-chassis-good";
+};
+
&pinctrl {
key_pins: mux-keys {
groups = "gspi", "sspi";
@@ -77,7 +109,3 @@
/* "Serial over LAN" port. Connected to ttyS2 of the host system. */
status = "okay";
};
-
-&watchdog0 {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
index 93595850a4c3..fd671c7a1e5d 100644
--- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
+++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
@@ -37,6 +37,14 @@
#clock-cells = <0>;
};
+ refclk: clock-48mhz {
+ /* 48 MHz reference oscillator */
+ compatible = "fixed-clock";
+ clock-output-names = "ref";
+ clock-frequency = <48000000>;
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -49,6 +57,15 @@
reg = <0xb0000000 0x200>;
};
+ clk: clock-controller@b0000200 {
+ compatible = "nuvoton,wpcm450-clk";
+ reg = <0xb0000200 0x100>;
+ clocks = <&refclk>;
+ clock-names = "ref";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
serial0: serial@b8000000 {
compatible = "nuvoton,wpcm450-uart";
reg = <0xb8000000 0x20>;
@@ -81,7 +98,6 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb800101c 0x4>;
clocks = <&clk24m>;
- status = "disabled";
};
aic: interrupt-controller@b8002000 {
@@ -456,5 +472,22 @@
function = "hg7";
};
};
+
+ fiu: spi-controller@c8000000 {
+ compatible = "nuvoton,wpcm450-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
+ reg-names = "control", "memory";
+ clocks = <&clk 0>;
+ nuvoton,shm = <&shm>;
+ status = "disabled";
+ };
+
+ shm: syscon@c8001000 {
+ compatible = "nuvoton,wpcm450-shm", "syscon";
+ reg = <0xc8001000 0x1000>;
+ reg-io-width = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index ce6c235f68ec..3046ec572632 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -8,9 +8,9 @@
/ {
vddvario: regulator-vddvario {
- compatible = "regulator-fixed";
- regulator-name = "vddvario";
- regulator-always-on;
+ compatible = "regulator-fixed";
+ regulator-name = "vddvario";
+ regulator-always-on;
};
vdd33a: regulator-vdd33a {
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
index e7534fe9c53c..bc8961f3690f 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
@@ -12,9 +12,9 @@
/ {
vddvario: regulator-vddvario {
- compatible = "regulator-fixed";
- regulator-name = "vddvario";
- regulator-always-on;
+ compatible = "regulator-fixed";
+ regulator-name = "vddvario";
+ regulator-always-on;
};
vdd33a: regulator-vdd33a {
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
index 1e96c865d41d..8adc0ef01f6c 100644
--- a/arch/arm/boot/dts/omap-zoom-common.dtsi
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -14,7 +14,7 @@
* they probably share the same GPIO IRQ
* REVISIT: Add timing support from slls644g.pdf
*/
- uart@3,0 {
+ serial@3,0 {
compatible = "ns16550a";
reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
bank-width = <2>;
@@ -50,7 +50,7 @@
gpmc,wr-data-mux-bus-ns = <45>;
gpmc,wr-access-ns = <145>;
};
- uart@3,1 {
+ serial@3,1 {
compatible = "ns16550a";
reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */
bank-width = <2>;
@@ -61,7 +61,7 @@
clock-frequency = <1843200>;
current-speed = <115200>;
};
- uart@3,2 {
+ serial@3,2 {
compatible = "ns16550a";
reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */
bank-width = <2>;
@@ -72,7 +72,7 @@
clock-frequency = <1843200>;
current-speed = <115200>;
};
- uart@3,3 {
+ serial@3,3 {
compatible = "ns16550a";
reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */
bank-width = <2>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 5750ca1233cc..afabb36a8ac1 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP2 SoC
*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index af964f139abf..5acf5dd87c59 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -21,7 +21,7 @@
nor@0,0 {
compatible = "cfi-flash";
- linux,mtd-name= "intel,ge28f256l18b85";
+ linux,mtd-name = "intel,ge28f256l18b85";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x04000000>;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index bb529a2a295d..821da51cb870 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP2420 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "omap2.dtsi"
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 23115ba61bc0..b9a9e6e45266 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP243x SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "omap2.dtsi"
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index a858ebfa1500..1a085bc01317 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 BeagleBoard xM";
- compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap3";
cpus {
cpu@0 {
@@ -370,7 +370,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 0548b391334f..47ff1ffddfc5 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -28,18 +28,18 @@
leds {
compatible = "gpio-leds";
- pmu_stat {
+ led-pmu-stat {
label = "beagleboard::pmu_stat";
gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
};
- heartbeat {
+ led-heartbeat {
label = "beagleboard::usr0";
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
linux,default-trigger = "heartbeat";
};
- mmc {
+ led-mmc {
label = "beagleboard::usr1";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
linux,default-trigger = "mmc0";
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index 3b8349094baa..f25c0a84a190 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -11,12 +11,12 @@
model = "CompuLab CM-T3517";
compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
- vmmc: regulator-vmmc {
- compatible = "regulator-fixed";
- regulator-name = "vmmc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+ vmmc: regulator-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
wl12xx_vmmc2: wl12xx_vmmc2 {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index 48e48b0c8190..e1b1a047f77a 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -9,7 +9,7 @@
/ {
model = "CompuLab CM-T3730";
- compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3";
wl12xx_vmmc2: wl12xx_vmmc2 {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
index a9069cca5888..0da759f8e2c2 100644
--- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP3 SoC CPU thermal
*
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index 54cd37336be7..38aa1febc33f 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -15,28 +15,28 @@
leds {
compatible = "gpio-leds";
- heartbeat {
+ led-heartbeat {
label = "devkit8000::led1";
gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */
default-state = "on";
linux,default-trigger = "heartbeat";
};
- mmc {
+ led-mmc {
label = "devkit8000::led2";
gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */
default-state = "on";
linux,default-trigger = "none";
};
- usr {
+ led-usr {
label = "devkit8000::led3";
gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */
default-state = "on";
linux,default-trigger = "usr";
};
- pmu_stat {
+ led-pmu-stat {
label = "devkit8000::pmu_stat";
gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
};
diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/omap3-echo.dts
index 8f02ff5e7da6..06d2377d28ad 100644
--- a/arch/arm/boot/dts/omap3-echo.dts
+++ b/arch/arm/boot/dts/omap3-echo.dts
@@ -146,7 +146,7 @@
label = "q1";
reg = <0x32>;
clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
- enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */
+ enable-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */
multi-led@0 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index c9332195d096..abd403c228c7 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -60,7 +60,7 @@
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name= "hynix,h8kds0un0mer-4em";
+ linux,mtd-name = "hynix,h8kds0un0mer-4em";
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 5cc0cf7cd16c..f95eea63b355 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -60,7 +60,7 @@
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name= "micron,mt29f2g16abdhc";
+ linux,mtd-name = "micron,mt29f2g16abdhc";
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index 7e3d8147e2c1..4183fde46059 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -11,8 +11,7 @@
/ {
model = "OMAP3 GTA04";
- compatible = "ti,omap3-gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3";
-
+ compatible = "goldelico,gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
@@ -31,6 +30,8 @@
aliases {
display0 = &lcd;
display1 = &tv0;
+ /delete-property/ mmc2;
+ /delete-property/ mmc3;
};
ldo_3v3: fixedregulator {
@@ -125,7 +126,7 @@
spi-cpol;
spi-cpha;
- backlight= <&backlight>;
+ backlight = <&backlight>;
label = "lcd";
port {
lcd_in: endpoint {
@@ -145,7 +146,7 @@
pinctrl-0 = <&backlight_pins>;
};
- pwm11: dmtimer-pwm {
+ pwm11: pwm-11 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer11>;
#pwm-cells = <3>;
@@ -330,7 +331,7 @@
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
- };
+ };
gps_pins: pinmux_gps_pins {
pinctrl-single,pins = <
@@ -610,6 +611,22 @@
clock-frequency = <100000>;
};
+&mcspi1 {
+ status = "disabled";
+};
+
+&mcspi2 {
+ status = "disabled";
+};
+
+&mcspi3 {
+ status = "disabled";
+};
+
+&mcspi4 {
+ status = "disabled";
+};
+
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
@@ -851,8 +868,8 @@
};
&hdqw1w {
- pinctrl-names = "default";
- pinctrl-0 = <&hdq_pins>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdq_pins>;
};
/* image signal processor within OMAP3 SoC */
diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts
index 0b5bd7388877..425081201fd4 100644
--- a/arch/arm/boot/dts/omap3-gta04a5.dts
+++ b/arch/arm/boot/dts/omap3-gta04a5.dts
@@ -75,6 +75,11 @@
>;
};
+ bno050_pins: pinmux-bno050-pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT | MUX_MODE4) /* gpin113 */
+ >;
+ };
};
/*
@@ -115,17 +120,17 @@
/delete-node/ itg3200@68;
/delete-node/ hmc5843@1e;
- bmg160@69 {
+ gyrometer@69 {
compatible = "bosch,bmg160";
reg = <0x69>;
};
- bmc150@10 {
+ accelerometer@10 {
compatible = "bosch,bmc150_accel";
reg = <0x10>;
};
- bmc150@12 {
+ magnetometer@12 {
compatible = "bosch,bmc150_magn";
reg = <0x12>;
};
@@ -136,4 +141,12 @@
vdda-supply = <&vio>;
vddd-supply = <&vio>;
};
+
+ imu@29 {
+ compatible = "bosch,bno055";
+ reg = <0x29>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bno050_pins>;
+ /* interrupt at &gpio4 17 */
+ };
};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 99f5585097a1..219202610463 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -111,7 +111,7 @@
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name= "micron,mt29c4g96maz";
+ linux,mtd-name = "micron,mt29c4g96maz";
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
index 9dca5bfc87ab..eadb5b857f48 100644
--- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index c6f863bc03ad..3f0197ceae09 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
index 8e9c12cf51a7..bc95a8df2e6a 100644
--- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 5188f96f431e..d36ceecb7328 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 9c6a92724590..85f33bbb566f 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -103,7 +103,7 @@
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name= "micron,nand";
+ linux,mtd-name = "micron,nand";
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
@@ -215,11 +215,11 @@
};
&mmc2 {
- status="disabled";
+ status = "disabled";
};
&mmc3 {
- status="disabled";
+ status = "disabled";
};
&omap3_pmx_core {
@@ -301,5 +301,5 @@
&vaux1 {
/* Needed for ads7846 */
- regulator-name = "vcc";
+ regulator-name = "vcc";
};
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index 73d477898ec2..c595afe4181d 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -372,7 +372,7 @@
gpmc,device-width = <2>;
gpmc,wait-pin = <0>;
gpmc,wait-monitoring-ns = <0>;
- gpmc,burst-length= <4>;
+ gpmc,burst-length = <4>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <100>;
gpmc,cs-wr-off-ns = <100>;
diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
index ecb4ef738e07..f6bbea2be54c 100644
--- a/arch/arm/boot/dts/omap3-lilly-dbb056.dts
+++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
@@ -8,7 +8,7 @@
/ {
model = "INCOstartec LILLY-DBB056 (DM3730)";
- compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap3";
};
&twl {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index d211bcc31174..a3cf3f443785 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N9";
- compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap3";
};
&i2c2 {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index d40c3d2c4914..f9f9eca0c56c 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -9,6 +9,7 @@
#include "omap34xx.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/media/video-interfaces.h>
/*
* Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
@@ -49,7 +50,7 @@
leds {
compatible = "gpio-leds";
- heartbeat {
+ led-heartbeat {
label = "debug::sleep";
gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */
linux,default-trigger = "default-on";
@@ -156,7 +157,7 @@
io-channel-names = "temp", "bsi", "vbat";
};
- pwm9: dmtimer-pwm {
+ pwm9: pwm-9 {
compatible = "ti,omap-dmtimer-pwm";
#pwm-cells = <3>;
ti,timers = <&timer9>;
@@ -194,7 +195,7 @@
csi_isp: endpoint {
remote-endpoint = <&csi_cam1>;
- bus-type = <3>; /* CCP2 */
+ bus-type = <MEDIA_BUS_TYPE_CCP2>;
clock-lanes = <1>;
data-lanes = <0>;
lane-polarity = <0 0>;
@@ -236,27 +237,27 @@
pinctrl-single,pins = <
/* address lines */
- OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
- OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
- OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
+ OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
+ OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
+ OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
/* data lines, gpmc_d0..d7 not muxable according to TRM */
- OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
- OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
- OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
- OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
- OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
- OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
- OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
- OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
+ OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
+ OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
+ OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
+ OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
+ OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
+ OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
+ OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
+ OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
/*
* gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
* according to TRM. OneNAND seems to require PIN_INPUT on clock.
*/
- OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
- OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
- >;
+ OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
+ OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
+ >;
};
i2c1_pins: pinmux_i2c1_pins {
@@ -568,8 +569,8 @@
};
&twl_gpio {
- ti,pullups = <0x0>;
- ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
+ ti,pullups = <0x0>;
+ ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
};
&i2c2 {
@@ -738,12 +739,12 @@
si4713: si4713@63 {
compatible = "silabs,si4713";
- reg = <0x63>;
+ reg = <0x63>;
- interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
- reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
- vio-supply = <&vio>;
- vdd-supply = <&vaux1>;
+ interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
+ reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
+ vio-supply = <&vio>;
+ vdd-supply = <&vaux1>;
};
bq24150a: bq24150a@6b {
@@ -767,56 +768,20 @@
clock-frequency = <400000>;
- lis302dl: lis3lv02d@1d {
- compatible = "st,lis3lv02d";
+ accelerometer@1d {
+ compatible = "st,lis302dl";
reg = <0x1d>;
- Vdd-supply = <&vaux1>;
- Vdd_IO-supply = <&vio>;
+ vdd-supply = <&vaux1>;
+ vddio-supply = <&vio>;
interrupt-parent = <&gpio6>;
- interrupts = <21 20>; /* 181 and 180 */
-
- /* click flags */
- st,click-single-x;
- st,click-single-y;
- st,click-single-z;
-
- /* Limits are 0.5g * value */
- st,click-threshold-x = <8>;
- st,click-threshold-y = <8>;
- st,click-threshold-z = <10>;
-
- /* Click must be longer than time limit */
- st,click-time-limit = <9>;
-
- /* Kind of debounce filter */
- st,click-latency = <50>;
-
- /* Interrupt line 2 for click detection */
- st,irq2-click;
-
- st,wakeup-x-hi;
- st,wakeup-y-hi;
- st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
-
- st,wakeup2-z-hi;
- st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
-
- st,hipass1-disable;
- st,hipass2-disable;
-
- st,axis-x = <1>; /* LIS3_DEV_X */
- st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
- st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
-
- st,min-limit-x = <(-32)>;
- st,min-limit-y = <3>;
- st,min-limit-z = <3>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>,
+ <20 IRQ_TYPE_EDGE_RISING>; /* 181 and 180 */
- st,max-limit-x = <(-3)>;
- st,max-limit-y = <32>;
- st,max-limit-z = <32>;
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
};
cam1: camera@3e {
@@ -835,7 +800,7 @@
port {
csi_cam1: endpoint {
- bus-type = <3>; /* CCP2 */
+ bus-type = <MEDIA_BUS_TYPE_CCP2>;
strobe = <1>;
clock-inv = <0>;
crc = <1>;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 7dde9fbb06d3..f68da828b050 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -162,8 +162,8 @@
};
&twl_gpio {
- ti,pullups = <0x000001>; /* BIT(0) */
- ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
+ ti,pullups = <0x000001>; /* BIT(0) */
+ ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
};
&vdac {
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index b2f480022ff6..cbaf79c4e842 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N950";
- compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap3";
keys {
compatible = "gpio-keys";
diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi
index bb932913c9e3..a6dbbba799b2 100644
--- a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi
@@ -17,19 +17,19 @@
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
- gpio148 {
+ led-gpio148 {
label = "overo:red:gpio148";
gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */
};
- gpio150 {
+ led-gpio150 {
label = "overo:yellow:gpio150";
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */
};
- gpio151 {
+ led-gpio151 {
label = "overo:blue:gpio151";
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */
};
- gpio170 {
+ led-gpio170 {
label = "overo:green:gpio170";
gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */
};
diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
index 006a6d97231c..adc714c39825 100644
--- a/arch/arm/boot/dts/omap3-overo-base.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
@@ -222,7 +222,7 @@
nand@0,0 {
compatible = "ti,omap2-nand";
- linux,mtd-name= "micron,mt29c4g96maz";
+ linux,mtd-name = "micron,mt29c4g96maz";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
index 2d2c61d7aa86..0d0e62c00916 100644
--- a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
@@ -17,12 +17,12 @@
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
- heartbeat {
+ led-heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
linux,default-trigger = "heartbeat";
};
- gpio22 {
+ led-gpio22 {
label = "overo:blue:gpio22";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */
};
diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi
index 155aec121400..5f6721326f86 100644
--- a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi
@@ -17,12 +17,12 @@
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
- heartbeat {
+ led-heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
linux,default-trigger = "heartbeat";
};
- gpio22 {
+ led-gpio22 {
label = "overo:blue:gpio22";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */
};
diff --git a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi
index 82a04466747a..4b66f622ac13 100644
--- a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi
@@ -17,12 +17,12 @@
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
- heartbeat {
+ led-heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
linux,default-trigger = "heartbeat";
};
- gpio22 {
+ led-gpio22 {
label = "overo:blue:gpio22";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */
};
diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi
index 453a55324fa1..a8f163a899f0 100644
--- a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi
@@ -17,12 +17,12 @@
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
- heartbeat {
+ led-heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
linux,default-trigger = "heartbeat";
};
- gpio22 {
+ led-gpio22 {
label = "overo:blue:gpio22";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */
};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
index 7f04dfad8203..3eb935df04dc 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35";
- compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
index bc5a04e03336..3af8d10d7224 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43";
- compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
index 065c31cbf0e2..813e3c9fe3b6 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43";
- compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
index e38c1c51392c..8405bd9262de 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35";
- compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
index e6dc23159c4d..b9558d736e79 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43";
- compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
index 587c08ce282d..fcfc449f2abe 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-summit.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit";
- compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
index f57de6010994..6d14466c180a 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
@@ -14,6 +14,6 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi";
- compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
index 281af6c113be..bcf20ff3f281 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo";
- compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi
index df7450f17ffd..ec03ca17e98b 100644
--- a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi
@@ -15,7 +15,7 @@
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
- heartbeat {
+ led-heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
index 9bf4b88a4b50..5432e4e16ab5 100644
--- a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
@@ -13,7 +13,7 @@
/ {
leds {
compatible = "gpio-leds";
- heartbeat {
+ led-heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
index ea509956d7ac..c0252f8a798a 100644
--- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts
+++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
@@ -16,7 +16,7 @@
/ {
model = "Pandora Handheld Console 1GHz";
- compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi
index 37608af6c07f..559853764487 100644
--- a/arch/arm/boot/dts/omap3-pandora-common.dtsi
+++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi
@@ -666,7 +666,7 @@
lcd: lcd@1 {
reg = <1>; /* CS1 */
- compatible = "tpo,td043mtea1";
+ compatible = "tpo,td043mtea1";
spi-max-frequency = <100000>;
spi-cpol;
spi-cpha;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index eb3893b9535e..4c36bde62491 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,7 +8,7 @@
/ {
model = "CompuLab SBC-T3730 with CM-T3730";
- compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3";
aliases {
display0 = &dvi0;
diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/omap3-sniper.dts
index b6879cdc5c13..0591af494184 100644
--- a/arch/arm/boot/dts/omap3-sniper.dts
+++ b/arch/arm/boot/dts/omap3-sniper.dts
@@ -9,7 +9,7 @@
/ {
model = "LG Optimus Black";
- compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index 0482676d1830..ab52e8d68f76 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -9,7 +9,7 @@
/ {
model = "TI Zoom3";
- compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap3";
cpus {
cpu@0 {
@@ -23,9 +23,9 @@
};
vddvario: regulator-vddvario {
- compatible = "regulator-fixed";
- regulator-name = "vddvario";
- regulator-always-on;
+ compatible = "regulator-fixed";
+ regulator-name = "vddvario";
+ regulator-always-on;
};
vdd33a: regulator-vdd33a {
@@ -84,28 +84,28 @@
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
- OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
- OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
- OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
+ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
+ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
+ OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
+ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
- OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
- OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
- OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
+ OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
+ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
+ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
+ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
- OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
- OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+ OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
+ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
+ OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
>;
};
@@ -205,22 +205,22 @@
};
&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
};
&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
};
&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
};
&uart4 {
- status = "disabled";
+ status = "disabled";
};
&usb_otg_hs {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 64b7e6fddd1b..92cd4c99dae7 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP3 SoC
*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
@@ -896,15 +893,37 @@
#gpio-cells = <2>;
};
- usb_otg_hs: usb_otg_hs@480ab000 {
- compatible = "ti,omap3-musb";
- reg = <0x480ab000 0x1000>;
- interrupts = <92>, <93>;
- interrupt-names = "mc", "dma";
- ti,hwmods = "usb_otg_hs";
- multipoint = <1>;
- num-eps = <16>;
- ram-bits = <12>;
+ usb_otg_target: target-module@480ab000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x480ab400 0x4>,
+ <0x480ab404 0x4>,
+ <0x480ab408 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Clock defined in the SoC specific dtsi file */
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x480ab000 0x1000>;
+
+ usb_otg_hs: usb@0 {
+ compatible = "ti,omap3-musb";
+ reg = <0 0x1000>;
+ interrupts = <92>, <93>;
+ interrupt-names = "mc", "dma";
+ multipoint = <1>;
+ num-eps = <16>;
+ ram-bits = <12>;
+ };
};
dss: dss@48050000 {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 7d530ae3483b..258ecd9e4519 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -53,7 +53,7 @@
nor@0,0 {
compatible = "cfi-flash";
- linux,mtd-name= "intel,pf48f6000m0y1be";
+ linux,mtd-name = "intel,pf48f6000m0y1be";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x08000000>;
@@ -105,7 +105,7 @@
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name= "micron,mt29f1g08abb";
+ linux,mtd-name = "micron,mt29f1g08abb";
#address-cells = <1>;
#size-cells = <1>;
ti,nand-ecc-opt = "sw";
@@ -148,7 +148,7 @@
};
onenand@2,0 {
- linux,mtd-name= "samsung,kfm2g16q2m-deb8";
+ linux,mtd-name = "samsung,kfm2g16q2m-deb8";
#address-cells = <1>;
#size-cells = <1>;
compatible = "ti,omap2-onenand";
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
index 2ec3628d3315..24adfac26be0 100644
--- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -46,37 +46,61 @@
ti,bit-shift = <2>;
};
- d2d_26m_fck: d2d_26m_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0a00>;
- ti,bit-shift = <3>;
- };
-
- fshostusb_fck: fshostusb_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <5>;
- };
-
- ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <0>;
- reg = <0x0a00>;
- };
-
- ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <8>;
- reg = <0x0a40>;
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ clock@a00 {
+ compatible = "ti,clksel";
+ reg = <0xa00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ d2d_26m_fck: clock-d2d-26m-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "d2d_26m_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <3>;
+ };
+
+ fshostusb_fck: clock-fshostusb-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "fshostusb_fck";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <5>;
+ };
+
+ ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "ssi_ssr_gate_fck_3430es1";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <0>;
+ };
+ };
+
+ clock@a40 {
+ compatible = "ti,clksel";
+ reg = <0xa40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clock-output-names = "ssi_ssr_div_fck_3430es1";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ };
+
+ usb_l4_div_ick: clock-usb-l4-div-ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clock-output-names = "usb_l4_div_ick";
+ clocks = <&l4_ick>;
+ ti,bit-shift = <4>;
+ ti,max-div = <1>;
+ ti,index-starts-at-one;
+ };
};
ssi_ssr_fck: ssi_ssr_fck_3430es1 {
@@ -93,20 +117,43 @@
clock-div = <2>;
};
- hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <4>;
- };
-
- fac_ick: fac_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <8>;
+ clock@a10 {
+ compatible = "ti,clksel";
+ reg = <0xa10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clock-output-names = "hsotgusb_ick_3430es1";
+ clocks = <&core_l3_ick>;
+ ti,bit-shift = <4>;
+ };
+
+ fac_ick: clock-fac-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "fac_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <8>;
+ };
+
+ ssi_ick: clock-ssi-ick-3430es1 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clock-output-names = "ssi_ick_3430es1";
+ clocks = <&ssi_l4_ick>;
+ ti,bit-shift = <0>;
+ };
+
+ usb_l4_gate_ick: clock-usb-l4-gate-ick {
+ #clock-cells = <0>;
+ compatible = "ti,composite-interface-clock";
+ clock-output-names = "usb_l4_gate_ick";
+ clocks = <&l4_ick>;
+ ti,bit-shift = <5>;
+ };
};
ssi_l4_ick: ssi_l4_ick {
@@ -117,45 +164,26 @@
clock-div = <1>;
};
- ssi_ick: ssi_ick_3430es1@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&ssi_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <0>;
- };
-
- usb_l4_gate_ick: usb_l4_gate_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clocks = <&l4_ick>;
- ti,bit-shift = <5>;
- reg = <0x0a10>;
- };
-
- usb_l4_div_ick: usb_l4_div_ick@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&l4_ick>;
- ti,bit-shift = <4>;
- ti,max-div = <1>;
- reg = <0x0a40>;
- ti,index-starts-at-one;
- };
-
usb_l4_ick: usb_l4_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
- dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m4x2_ck>;
- ti,bit-shift = <0>;
- reg = <0x0e00>;
- ti,set-rate-parent;
+ clock@e00 {
+ compatible = "ti,clksel";
+ reg = <0xe00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "dss1_alwon_fck_3430es1";
+ clocks = <&dpll4_m4x2_ck>;
+ ti,bit-shift = <0>;
+ ti,set-rate-parent;
+ };
};
dss_ick: dss_ick_3430es1@e10 {
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
index 21079cdf2663..8374532f20e2 100644
--- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -13,45 +13,76 @@
clock-div = <1>;
};
- aes1_ick: aes1_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- ti,bit-shift = <3>;
- reg = <0x0a14>;
- };
+ clock@a14 {
+ compatible = "ti,clksel";
+ reg = <0xa14>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- rng_ick: rng_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <2>;
- };
+ aes1_ick: clock-aes1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "aes1_ick";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <3>;
+ };
- sha11_ick: sha11_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <1>;
- };
+ rng_ick: clock-rng-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "rng_ick";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <2>;
+ };
- des1_ick: des1_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <0>;
+ sha11_ick: clock-sha11-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "sha11_ick";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <1>;
+ };
+
+ des1_ick: clock-des1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "des1_ick";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <0>;
+ };
+
+ pka_ick: clock-pka-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "pka_ick";
+ clocks = <&security_l3_ick>;
+ ti,bit-shift = <4>;
+ };
};
- cam_mclk: cam_mclk@f00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m5x2_ck>;
- ti,bit-shift = <0>;
- reg = <0x0f00>;
- ti,set-rate-parent;
+ /* CM_FCLKEN_CAM */
+ clock@f00 {
+ compatible = "ti,clksel";
+ reg = <0xf00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ cam_mclk: clock-cam-mclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "cam_mclk";
+ clocks = <&dpll4_m5x2_ck>;
+ ti,bit-shift = <0>;
+ ti,set-rate-parent;
+ };
+
+ csi2_96m_fck: clock-csi2-96m-fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "csi2_96m_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <1>;
+ };
};
cam_ick: cam_ick@f10 {
@@ -62,14 +93,6 @@
ti,bit-shift = <0>;
};
- csi2_96m_fck: csi2_96m_fck@f00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0f00>;
- ti,bit-shift = <1>;
- };
-
security_l3_ick: security_l3_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -78,44 +101,51 @@
clock-div = <1>;
};
- pka_ick: pka_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l3_ick>;
- reg = <0x0a14>;
- ti,bit-shift = <4>;
- };
+ clock@a10 {
+ compatible = "ti,clksel";
+ reg = <0xa10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- icr_ick: icr_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <29>;
- };
+ icr_ick: clock-icr-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "icr_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <29>;
+ };
- des2_ick: des2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <26>;
- };
+ des2_ick: clock-des2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "des2_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <26>;
+ };
- mspro_ick: mspro_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <23>;
- };
+ mspro_ick: clock-mspro-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mspro_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <23>;
+ };
- mailboxes_ick: mailboxes_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <7>;
+ mailboxes_ick: clock-mailboxes-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mailboxes_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <7>;
+ };
+
+ sad2d_ick: clock-sad2d-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "sad2d_ick";
+ clocks = <&l3_ick>;
+ ti,bit-shift = <3>;
+ };
};
ssi_l4_ick: ssi_l4_ick {
@@ -126,20 +156,27 @@
clock-div = <1>;
};
- sr1_fck: sr1_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0c00>;
- ti,bit-shift = <6>;
- };
+ clock@c00 {
+ compatible = "ti,clksel";
+ reg = <0xc00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- sr2_fck: sr2_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0c00>;
- ti,bit-shift = <7>;
+ sr1_fck: clock-sr1-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "sr1_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <6>;
+ };
+
+ sr2_fck: clock-sr2-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "sr2_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <7>;
+ };
};
sr_l4_ick: sr_l4_ick {
@@ -187,37 +224,45 @@
ti,bit-shift = <0>;
};
- modem_fck: modem_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- reg = <0x0a00>;
- ti,bit-shift = <31>;
- };
+ clock@a00 {
+ compatible = "ti,clksel";
+ reg = <0xa00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- sad2d_ick: sad2d_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <3>;
- };
+ modem_fck: clock-modem-fck {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "modem_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <31>;
+ };
- mad2d_ick: mad2d_ick@a18 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l3_ick>;
- reg = <0x0a18>;
- ti,bit-shift = <3>;
+ mspro_fck: clock-mspro-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mspro_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <23>;
+ };
};
- mspro_fck: mspro_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <23>;
+ /* CM_ICLKEN3_CORE */
+ clock@a18 {
+ compatible = "ti,clksel";
+ reg = <0xa18>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ mad2d_ick: clock-mad2d-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mad2d_ick";
+ clocks = <&l3_ick>;
+ ti,bit-shift = <3>;
+ };
};
+
};
&cm_clockdomains {
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 8b8451399784..9dbf62797f0f 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP34xx/OMAP35xx SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
@@ -192,6 +189,10 @@
"ssi_ick";
};
+&usb_otg_target {
+ clocks = <&hsotgusb_ick_3430es2>;
+};
+
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index 9974d5226971..dcc5cfcd1fe6 100644
--- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -133,37 +133,66 @@
ti,bit-shift = <2>;
};
- usbtll_ick: usbtll_ick@a18 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a18>;
- ti,bit-shift = <2>;
+ /* CM_ICLKEN3_CORE */
+ clock@a18 {
+ compatible = "ti,clksel";
+ reg = <0xa18>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ usbtll_ick: clock-usbtll-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "usbtll_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <2>;
+ };
};
- mmchs3_ick: mmchs3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <30>;
+ clock@a10 {
+ compatible = "ti,clksel";
+ reg = <0xa10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ mmchs3_ick: clock-mmchs3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mmchs3_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <30>;
+ };
};
- mmchs3_fck: mmchs3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <30>;
+ clock@a00 {
+ compatible = "ti,clksel";
+ reg = <0xa00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ mmchs3_fck: clock-mmchs3-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mmchs3_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <30>;
+ };
};
- dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
- #clock-cells = <0>;
- compatible = "ti,dss-gate-clock";
- clocks = <&dpll4_m4x2_ck>;
- ti,bit-shift = <0>;
- reg = <0x0e00>;
- ti,set-rate-parent;
+ clock@e00 {
+ compatible = "ti,clksel";
+ reg = <0xe00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clock-output-names = "dss1_alwon_fck_3430es2";
+ clocks = <&dpll4_m4x2_ck>;
+ ti,bit-shift = <0>;
+ ti,set-rate-parent;
+ };
};
dss_ick: dss_ick_3430es2@e10 {
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index 4e9cc9003594..c5fdb2bd765d 100644
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -58,12 +58,19 @@
ti,set-bit-to-disable;
};
- uart4_fck: uart4_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_48m_fck>;
+ clock@1000 {
+ compatible = "ti,clksel";
reg = <0x1000>;
- ti,bit-shift = <18>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ uart4_fck: clock-uart4-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "uart4_fck";
+ clocks = <&per_48m_fck>;
+ ti,bit-shift = <18>;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 945537aee3ca..c94eb86d3da7 100644
--- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -5,21 +5,35 @@
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&cm_clocks {
- ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <0>;
- reg = <0x0a00>;
- };
-
- ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <8>;
- reg = <0x0a40>;
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ clock@a00 {
+ compatible = "ti,clksel";
+ reg = <0xa00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "ssi_ssr_gate_fck_3430es2";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <0>;
+ };
+ };
+
+ clock@a40 {
+ compatible = "ti,clksel";
+ reg = <0xa40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clock-output-names = "ssi_ssr_div_fck_3430es2";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <8>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ };
};
ssi_ssr_fck: ssi_ssr_fck_3430es2 {
@@ -36,12 +50,27 @@
clock-div = <2>;
};
- hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-hsotgusb-interface-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <4>;
+ clock@a10 {
+ compatible = "ti,clksel";
+ reg = <0xa10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-hsotgusb-interface-clock";
+ clock-output-names = "hsotgusb_ick_3430es2";
+ clocks = <&core_l3_ick>;
+ ti,bit-shift = <4>;
+ };
+
+ ssi_ick: clock-ssi-ick-3430es2 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clock-output-names = "ssi_ick_3430es2";
+ clocks = <&ssi_l4_ick>;
+ ti,bit-shift = <0>;
+ };
};
ssi_l4_ick: ssi_l4_ick {
@@ -52,20 +81,19 @@
clock-div = <1>;
};
- ssi_ick: ssi_ick_3430es2@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-ssi-interface-clock";
- clocks = <&ssi_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <0>;
- };
+ clock@c00 {
+ compatible = "ti,clksel";
+ reg = <0xc00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
- usim_gate_fck: usim_gate_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&omap_96m_fck>;
- ti,bit-shift = <9>;
- reg = <0x0c00>;
+ usim_gate_fck: clock-usim-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "usim_gate_fck";
+ clocks = <&omap_96m_fck>;
+ ti,bit-shift = <9>;
+ };
};
sys_d2_ck: sys_d2_ck {
@@ -140,13 +168,20 @@
clock-div = <20>;
};
- usim_mux_fck: usim_mux_fck@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
- ti,bit-shift = <3>;
- reg = <0x0c40>;
- ti,index-starts-at-one;
+ clock@c40 {
+ compatible = "ti,clksel";
+ reg = <0xc40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ usim_mux_fck: clock-usim-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "usim_mux_fck";
+ clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
+ ti,bit-shift = <3>;
+ ti,index-starts-at-one;
+ };
};
usim_fck: usim_fck {
@@ -155,12 +190,19 @@
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
};
- usim_ick: usim_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <9>;
+ clock@c10 {
+ compatible = "ti,clksel";
+ reg = <0xc10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ usim_ick: clock-usim-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "usim_ick";
+ clocks = <&wkup_l4_ick>;
+ ti,bit-shift = <9>;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 22b33098b1a2..fff9c3d34193 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP3 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
@@ -243,6 +240,10 @@
"ssi_ick";
};
+&usb_otg_target {
+ clocks = <&hsotgusb_ick_3430es2>;
+};
+
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 0656c32439d2..2e13ca11ceea 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -78,12 +78,35 @@
};
&scm_clocks {
- mcbsp5_mux_fck: mcbsp5_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <4>;
+ /* CONTROL_DEVCONF1 */
+ clock@68 {
+ compatible = "ti,clksel";
reg = <0x68>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ mcbsp5_mux_fck: clock-mcbsp5-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "mcbsp5_mux_fck";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <4>;
+ };
+
+ mcbsp3_mux_fck: clock-mcbsp3-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "mcbsp3_mux_fck";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ };
+
+ mcbsp4_mux_fck: clock-mcbsp4-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "mcbsp4_mux_fck";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ };
};
mcbsp5_fck: mcbsp5_fck {
@@ -92,12 +115,28 @@
clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
};
- mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x04>;
+ /* CONTROL_DEVCONF0 */
+ clock@4 {
+ compatible = "ti,clksel";
+ reg = <0x4>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ mcbsp1_mux_fck: clock-mcbsp1-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "mcbsp1_mux_fck";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ };
+
+ mcbsp2_mux_fck: clock-mcbsp2-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "mcbsp2_mux_fck";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <6>;
+ };
};
mcbsp1_fck: mcbsp1_fck {
@@ -106,41 +145,18 @@
clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
};
- mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <6>;
- reg = <0x04>;
- };
-
mcbsp2_fck: mcbsp2_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
};
- mcbsp3_mux_fck: mcbsp3_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- reg = <0x68>;
- };
-
mcbsp3_fck: mcbsp3_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
};
- mcbsp4_mux_fck: mcbsp4_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x68>;
- };
-
mcbsp4_fck: mcbsp4_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
@@ -238,14 +254,87 @@
reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
};
- dpll3_m3_ck: dpll3_m3_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll3_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <31>;
+ /* CM_CLKSEL1_EMU */
+ clock@1140 {
+ compatible = "ti,clksel";
reg = <0x1140>;
- ti,index-starts-at-one;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ dpll3_m3_ck: clock-dpll3-m3 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll3_m3_ck";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m6_ck: clock-dpll4-m6 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll4_m6_ck";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <63>;
+ ti,index-starts-at-one;
+ };
+
+ emu_src_mux_ck: clock-emu-src-mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "emu_src_mux_ck";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ };
+
+ pclk_fck: clock-pclk-fck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "pclk_fck";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <7>;
+ ti,index-starts-at-one;
+ };
+
+ pclkx2_fck: clock-pclkx2-fck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "pclkx2_fck";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ ti,index-starts-at-one;
+ };
+
+ atclk_fck: clock-atclk-fck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "atclk_fck";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <3>;
+ ti,index-starts-at-one;
+ };
+
+ traceclk_src_fck: clock-traceclk-src-fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "traceclk_src_fck";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ ti,bit-shift = <2>;
+ };
+
+ traceclk_fck: clock-traceclk-fck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "traceclk_fck";
+ clocks = <&traceclk_src_fck>;
+ ti,bit-shift = <11>;
+ ti,max-div = <7>;
+ ti,index-starts-at-one;
+ };
};
dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
@@ -285,16 +374,6 @@
clock-frequency = <0x0>;
};
- dpll3_m2_ck: dpll3_m2_ck@d40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll3_ck>;
- ti,bit-shift = <27>;
- ti,max-div = <31>;
- reg = <0x0d40>;
- ti,index-starts-at-one;
- };
-
core_ck: core_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -345,22 +424,73 @@
clock-div = <1>;
};
- omap_96m_fck: omap_96m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&cm_96m_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0d40>;
- };
-
- dpll4_m3_ck: dpll4_m3_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
+ /* CM_CLKSEL1_PLL */
+ clock@d40 {
+ compatible = "ti,clksel";
+ reg = <0xd40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ dpll3_m2_ck: clock-dpll3-m2 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll3_m2_ck";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <31>;
+ ti,index-starts-at-one;
+ };
+
+ omap_96m_fck: clock-omap-96m-fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "omap_96m_fck";
+ clocks = <&cm_96m_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ };
+
+ omap_54m_fck: clock-omap-54m-fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "omap_54m_fck";
+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+ ti,bit-shift = <5>;
+ };
+
+ omap_48m_fck: clock-omap-48m-fck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "omap_48m_fck";
+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+ ti,bit-shift = <3>;
+ };
+ };
+
+ /* CM_CLKSEL_DSS */
+ clock@e40 {
+ compatible = "ti,clksel";
+ reg = <0xe40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ dpll4_m3_ck: clock-dpll4-m3 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll4_m3_ck";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <32>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m4_ck: clock-dpll4-m4 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll4_m4_ck";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <16>;
+ ti,index-starts-at-one;
+ };
};
dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
@@ -380,14 +510,6 @@
ti,set-bit-to-disable;
};
- omap_54m_fck: omap_54m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
- ti,bit-shift = <5>;
- reg = <0x0d40>;
- };
-
cm_96m_d2_fck: cm_96m_d2_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -396,14 +518,6 @@
clock-div = <2>;
};
- omap_48m_fck: omap_48m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
- ti,bit-shift = <3>;
- reg = <0x0d40>;
- };
-
omap_12m_fck: omap_12m_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -412,15 +526,6 @@
clock-div = <4>;
};
- dpll4_m4_ck: dpll4_m4_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <16>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
- };
-
dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
@@ -468,16 +573,6 @@
ti,set-rate-parent;
};
- dpll4_m6_ck: dpll4_m6_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <63>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -503,19 +598,37 @@
clock-div = <1>;
};
- clkout2_src_gate_ck: clkout2_src_gate_ck@d70 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <7>;
- reg = <0x0d70>;
- };
-
- clkout2_src_mux_ck: clkout2_src_mux_ck@d70 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
- reg = <0x0d70>;
+ /* CM_CLKOUT_CTRL */
+ clock@d70 {
+ compatible = "ti,clksel";
+ reg = <0xd70>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ clkout2_src_gate_ck: clock-clkout2-src-gate {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "clkout2_src_gate_ck";
+ clocks = <&core_ck>;
+ ti,bit-shift = <7>;
+ };
+
+ clkout2_src_mux_ck: clock-clkout2-src-mux {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "clkout2_src_mux_ck";
+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+ };
+
+ sys_clkout2: clock-sys-clkout2 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "sys_clkout2";
+ clocks = <&clkout2_src_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+ };
};
clkout2_src_ck: clkout2_src_ck {
@@ -524,16 +637,6 @@
clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
};
- sys_clkout2: sys_clkout2@d70 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout2_src_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <64>;
- reg = <0x0d70>;
- ti,index-power-of-two;
- };
-
mpu_ck: mpu_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -558,49 +661,208 @@
clock-div = <1>;
};
- l3_ick: l3_ick@a40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,max-div = <3>;
- reg = <0x0a40>;
- ti,index-starts-at-one;
- };
-
- l4_ick: l4_ick@a40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&l3_ick>;
- ti,bit-shift = <2>;
- ti,max-div = <3>;
- reg = <0x0a40>;
- ti,index-starts-at-one;
- };
-
- rm_ick: rm_ick@c40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&l4_ick>;
- ti,bit-shift = <1>;
- ti,max-div = <3>;
- reg = <0x0c40>;
- ti,index-starts-at-one;
- };
-
- gpt10_gate_fck: gpt10_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <11>;
- reg = <0x0a00>;
- };
-
- gpt10_mux_fck: gpt10_mux_fck@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0a40>;
+ /* CM_CLKSEL_CORE */
+ clock@a40 {
+ compatible = "ti,clksel";
+ reg = <0xa40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ l3_ick: clock-l3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "l3_ick";
+ clocks = <&core_ck>;
+ ti,max-div = <3>;
+ ti,index-starts-at-one;
+ };
+
+ l4_ick: clock-l4-ick {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "l4_ick";
+ clocks = <&l3_ick>;
+ ti,bit-shift = <2>;
+ ti,max-div = <3>;
+ ti,index-starts-at-one;
+ };
+
+ gpt10_mux_fck: clock-gpt10-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt10_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ };
+
+ gpt11_mux_fck: clock-gpt11-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt11_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <7>;
+ };
+ };
+
+ /* CM_CLKSEL_WKUP */
+ clock@c40 {
+ compatible = "ti,clksel";
+ reg = <0xc40>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ rm_ick: clock-rm-ick {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "rm_ick";
+ clocks = <&l4_ick>;
+ ti,bit-shift = <1>;
+ ti,max-div = <3>;
+ ti,index-starts-at-one;
+ };
+
+ gpt1_mux_fck: clock-gpt1-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt1_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ };
+ };
+
+ /* CM_FCLKEN1_CORE */
+ clock@a00 {
+ compatible = "ti,clksel";
+ reg = <0xa00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ gpt10_gate_fck: clock-gpt10-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt10_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <11>;
+ };
+
+ gpt11_gate_fck: clock-gpt11-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt11_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <12>;
+ };
+
+ mmchs2_fck: clock-mmchs2-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mmchs2_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <25>;
+ };
+
+ mmchs1_fck: clock-mmchs1-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mmchs1_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <24>;
+ };
+
+ i2c3_fck: clock-i2c3-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "i2c3_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <17>;
+ };
+
+ i2c2_fck: clock-i2c2-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "i2c2_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <16>;
+ };
+
+ i2c1_fck: clock-i2c1-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "i2c1_fck";
+ clocks = <&core_96m_fck>;
+ ti,bit-shift = <15>;
+ };
+
+ mcbsp5_gate_fck: clock-mcbsp5-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "mcbsp5_gate_fck";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <10>;
+ };
+
+ mcbsp1_gate_fck: clock-mcbsp1-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "mcbsp1_gate_fck";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <9>;
+ };
+
+ mcspi4_fck: clock-mcspi4-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mcspi4_fck";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <21>;
+ };
+
+ mcspi3_fck: clock-mcspi3-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mcspi3_fck";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <20>;
+ };
+
+ mcspi2_fck: clock-mcspi2-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mcspi2_fck";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <19>;
+ };
+
+ mcspi1_fck: clock-mcspi1-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "mcspi1_fck";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <18>;
+ };
+
+ uart2_fck: clock-uart2-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "uart2_fck";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <14>;
+ };
+
+ uart1_fck: clock-uart1-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "uart1_fck";
+ clocks = <&core_48m_fck>;
+ ti,bit-shift = <13>;
+ };
+
+ hdq_fck: clock-hdq-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "hdq_fck";
+ clocks = <&core_12m_fck>;
+ ti,bit-shift = <22>;
+ };
};
gpt10_fck: gpt10_fck {
@@ -609,22 +871,6 @@
clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
};
- gpt11_gate_fck: gpt11_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <12>;
- reg = <0x0a00>;
- };
-
- gpt11_mux_fck: gpt11_mux_fck@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x0a40>;
- };
-
gpt11_fck: gpt11_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
@@ -639,62 +885,6 @@
clock-div = <1>;
};
- mmchs2_fck: mmchs2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <25>;
- };
-
- mmchs1_fck: mmchs1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <24>;
- };
-
- i2c3_fck: i2c3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <17>;
- };
-
- i2c2_fck: i2c2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <16>;
- };
-
- i2c1_fck: i2c1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <15>;
- };
-
- mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <10>;
- reg = <0x0a00>;
- };
-
- mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <9>;
- reg = <0x0a00>;
- };
-
core_48m_fck: core_48m_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -703,54 +893,6 @@
clock-div = <1>;
};
- mcspi4_fck: mcspi4_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <21>;
- };
-
- mcspi3_fck: mcspi3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <20>;
- };
-
- mcspi2_fck: mcspi2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <19>;
- };
-
- mcspi1_fck: mcspi1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <18>;
- };
-
- uart2_fck: uart2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <14>;
- };
-
- uart1_fck: uart1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <13>;
- };
-
core_12m_fck: core_12m_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -759,14 +901,6 @@
clock-div = <1>;
};
- hdq_fck: hdq_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_12m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <22>;
- };
-
core_l3_ick: core_l3_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -775,12 +909,172 @@
clock-div = <1>;
};
- sdrc_ick: sdrc_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <1>;
+ /* CM_ICLKEN1_CORE */
+ clock@a10 {
+ compatible = "ti,clksel";
+ reg = <0xa10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ sdrc_ick: clock-sdrc-ick {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "sdrc_ick";
+ clocks = <&core_l3_ick>;
+ ti,bit-shift = <1>;
+ };
+
+ mmchs2_ick: clock-mmchs2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mmchs2_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <25>;
+ };
+
+ mmchs1_ick: clock-mmchs1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mmchs1_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <24>;
+ };
+
+ hdq_ick: clock-hdq-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "hdq_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <22>;
+ };
+
+ mcspi4_ick: clock-mcspi4-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcspi4_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <21>;
+ };
+
+ mcspi3_ick: clock-mcspi3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcspi3_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <20>;
+ };
+
+ mcspi2_ick: clock-mcspi2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcspi2_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <19>;
+ };
+
+ mcspi1_ick: clock-mcspi1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcspi1_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <18>;
+ };
+
+ i2c3_ick: clock-i2c3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "i2c3_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <17>;
+ };
+
+ i2c2_ick: clock-i2c2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "i2c2_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <16>;
+ };
+
+ i2c1_ick: clock-i2c1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "i2c1_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <15>;
+ };
+
+ uart2_ick: clock-uart2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "uart2_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <14>;
+ };
+
+ uart1_ick: clock-uart1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "uart1_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <13>;
+ };
+
+ gpt11_ick: clock-gpt11-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt11_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <12>;
+ };
+
+ gpt10_ick: clock-gpt10-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt10_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <11>;
+ };
+
+ mcbsp5_ick: clock-mcbsp5-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcbsp5_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <10>;
+ };
+
+ mcbsp1_ick: clock-mcbsp1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcbsp1_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <9>;
+ };
+
+ omapctrl_ick: clock-omapctrl-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "omapctrl_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <6>;
+ };
+
+ aes2_ick: clock-aes2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "aes2_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <28>;
+ };
+
+ sha12_ick: clock-sha12-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "sha12_ick";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <27>;
+ };
};
gpmc_fck: gpmc_fck {
@@ -799,164 +1093,36 @@
clock-div = <1>;
};
- mmchs2_ick: mmchs2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <25>;
- };
-
- mmchs1_ick: mmchs1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <24>;
- };
-
- hdq_ick: hdq_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <22>;
- };
-
- mcspi4_ick: mcspi4_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <21>;
- };
-
- mcspi3_ick: mcspi3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <20>;
- };
-
- mcspi2_ick: mcspi2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <19>;
- };
-
- mcspi1_ick: mcspi1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <18>;
- };
-
- i2c3_ick: i2c3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <17>;
- };
-
- i2c2_ick: i2c2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <16>;
- };
-
- i2c1_ick: i2c1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <15>;
- };
-
- uart2_ick: uart2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <14>;
- };
-
- uart1_ick: uart1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <13>;
- };
-
- gpt11_ick: gpt11_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <12>;
- };
-
- gpt10_ick: gpt10_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <11>;
- };
-
- mcbsp5_ick: mcbsp5_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <10>;
- };
-
- mcbsp1_ick: mcbsp1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <9>;
- };
-
- omapctrl_ick: omapctrl_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <6>;
- };
-
- dss_tv_fck: dss_tv_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_54m_fck>;
- reg = <0x0e00>;
- ti,bit-shift = <2>;
- };
-
- dss_96m_fck: dss_96m_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_96m_fck>;
- reg = <0x0e00>;
- ti,bit-shift = <2>;
- };
-
- dss2_alwon_fck: dss2_alwon_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0e00>;
- ti,bit-shift = <1>;
+ /* CM_FCLKEN_DSS */
+ clock@e00 {
+ compatible = "ti,clksel";
+ reg = <0xe00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ dss_tv_fck: clock-dss-tv-fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "dss_tv_fck";
+ clocks = <&omap_54m_fck>;
+ ti,bit-shift = <2>;
+ };
+
+ dss_96m_fck: clock-dss-96m-fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "dss_96m_fck";
+ clocks = <&omap_96m_fck>;
+ ti,bit-shift = <2>;
+ };
+
+ dss2_alwon_fck: clock-dss2-alwon-fck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "dss2_alwon_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <1>;
+ };
};
dummy_ck: dummy_ck {
@@ -965,19 +1131,36 @@
clock-frequency = <0>;
};
- gpt1_gate_fck: gpt1_gate_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <0>;
- reg = <0x0c00>;
- };
-
- gpt1_mux_fck: gpt1_mux_fck@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- reg = <0x0c40>;
+ /* CM_FCLKEN_WKUP */
+ clock@c00 {
+ compatible = "ti,clksel";
+ reg = <0xc00>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ gpt1_gate_fck: clock-gpt1-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt1_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <0>;
+ };
+
+ gpio1_dbck: clock-gpio1-dbck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "gpio1_dbck";
+ clocks = <&wkup_32k_fck>;
+ ti,bit-shift = <3>;
+ };
+
+ wdt2_fck: clock-wdt2-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "wdt2_fck";
+ clocks = <&wkup_32k_fck>;
+ ti,bit-shift = <5>;
+ };
};
gpt1_fck: gpt1_fck {
@@ -986,14 +1169,6 @@
clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
};
- aes2_ick: aes2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- ti,bit-shift = <28>;
- reg = <0x0a10>;
- };
-
wkup_32k_fck: wkup_32k_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -1002,76 +1177,60 @@
clock-div = <1>;
};
- gpio1_dbck: gpio1_dbck@c00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&wkup_32k_fck>;
- reg = <0x0c00>;
- ti,bit-shift = <3>;
- };
-
- sha12_ick: sha12_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <27>;
- };
-
- wdt2_fck: wdt2_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&wkup_32k_fck>;
- reg = <0x0c00>;
- ti,bit-shift = <5>;
- };
-
- wdt2_ick: wdt2_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <5>;
- };
-
- wdt1_ick: wdt1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <4>;
- };
-
- gpio1_ick: gpio1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <3>;
- };
-
- omap_32ksync_ick: omap_32ksync_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <2>;
- };
-
- gpt12_ick: gpt12_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <1>;
- };
-
- gpt1_ick: gpt1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <0>;
+ /* CM_ICLKEN_WKUP */
+ clock@c10 {
+ compatible = "ti,clksel";
+ reg = <0xc10>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ wdt2_ick: clock-wdt2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "wdt2_ick";
+ clocks = <&wkup_l4_ick>;
+ ti,bit-shift = <5>;
+ };
+
+ wdt1_ick: clock-wdt1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "wdt1_ick";
+ clocks = <&wkup_l4_ick>;
+ ti,bit-shift = <4>;
+ };
+
+ gpio1_ick: clock-gpio1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpio1_ick";
+ clocks = <&wkup_l4_ick>;
+ ti,bit-shift = <3>;
+ };
+
+ omap_32ksync_ick: clock-omap-32ksync-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "omap_32ksync_ick";
+ clocks = <&wkup_l4_ick>;
+ ti,bit-shift = <2>;
+ };
+
+ gpt12_ick: clock-gpt12-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt12_ick";
+ clocks = <&wkup_l4_ick>;
+ ti,bit-shift = <1>;
+ };
+
+ gpt1_ick: clock-gpt1-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt1_ick";
+ clocks = <&wkup_l4_ick>;
+ ti,bit-shift = <0>;
+ };
};
per_96m_fck: per_96m_fck {
@@ -1090,27 +1249,227 @@
clock-div = <1>;
};
- uart3_fck: uart3_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_48m_fck>;
- reg = <0x1000>;
- ti,bit-shift = <11>;
- };
-
- gpt2_gate_fck: gpt2_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <3>;
+ /* CM_FCLKEN_PER */
+ clock@1000 {
+ compatible = "ti,clksel";
reg = <0x1000>;
- };
-
- gpt2_mux_fck: gpt2_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ uart3_fck: clock-uart3-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "uart3_fck";
+ clocks = <&per_48m_fck>;
+ ti,bit-shift = <11>;
+ };
+
+ gpt2_gate_fck: clock-gpt2-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt2_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <3>;
+ };
+
+ gpt3_gate_fck: clock-gpt3-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt3_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <4>;
+ };
+
+ gpt4_gate_fck: clock-gpt4-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt4_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <5>;
+ };
+
+ gpt5_gate_fck: clock-gpt5-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt5_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <6>;
+ };
+
+ gpt6_gate_fck: clock-gpt6-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt6_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <7>;
+ };
+
+ gpt7_gate_fck: clock-gpt7-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt7_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <8>;
+ };
+
+ gpt8_gate_fck: clock-gpt8-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt8_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <9>;
+ };
+
+ gpt9_gate_fck: clock-gpt9-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "gpt9_gate_fck";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <10>;
+ };
+
+ gpio6_dbck: clock-gpio6-dbck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "gpio6_dbck";
+ clocks = <&per_32k_alwon_fck>;
+ ti,bit-shift = <17>;
+ };
+
+ gpio5_dbck: clock-gpio5-dbck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "gpio5_dbck";
+ clocks = <&per_32k_alwon_fck>;
+ ti,bit-shift = <16>;
+ };
+
+ gpio4_dbck: clock-gpio4-dbck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "gpio4_dbck";
+ clocks = <&per_32k_alwon_fck>;
+ ti,bit-shift = <15>;
+ };
+
+ gpio3_dbck: clock-gpio3-dbck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "gpio3_dbck";
+ clocks = <&per_32k_alwon_fck>;
+ ti,bit-shift = <14>;
+ };
+
+ gpio2_dbck: clock-gpio2-dbck {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "gpio2_dbck";
+ clocks = <&per_32k_alwon_fck>;
+ ti,bit-shift = <13>;
+ };
+
+ wdt3_fck: clock-wdt3-fck {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clock-output-names = "wdt3_fck";
+ clocks = <&per_32k_alwon_fck>;
+ ti,bit-shift = <12>;
+ };
+
+ mcbsp2_gate_fck: clock-mcbsp2-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "mcbsp2_gate_fck";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <0>;
+ };
+
+ mcbsp3_gate_fck: clock-mcbsp3-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "mcbsp3_gate_fck";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <1>;
+ };
+
+ mcbsp4_gate_fck: clock-mcbsp4-gate-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clock-output-names = "mcbsp4_gate_fck";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ };
+ };
+
+ /* CM_CLKSEL_PER */
+ clock@1040 {
+ compatible = "ti,clksel";
reg = <0x1040>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ gpt2_mux_fck: clock-gpt2-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt2_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ };
+
+ gpt3_mux_fck: clock-gpt3-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt3_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <1>;
+ };
+
+ gpt4_mux_fck: clock-gpt4-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt4_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <2>;
+ };
+
+ gpt5_mux_fck: clock-gpt5-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt5_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <3>;
+ };
+
+ gpt6_mux_fck: clock-gpt6-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt6_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <4>;
+ };
+
+ gpt7_mux_fck: clock-gpt7-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt7_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <5>;
+ };
+
+ gpt8_mux_fck: clock-gpt8-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt8_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ };
+
+ gpt9_mux_fck: clock-gpt9-mux-fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clock-output-names = "gpt9_mux_fck";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <7>;
+ };
};
gpt2_fck: gpt2_fck {
@@ -1119,154 +1478,42 @@
clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
};
- gpt3_gate_fck: gpt3_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x1000>;
- };
-
- gpt3_mux_fck: gpt3_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <1>;
- reg = <0x1040>;
- };
-
gpt3_fck: gpt3_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
};
- gpt4_gate_fck: gpt4_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x1000>;
- };
-
- gpt4_mux_fck: gpt4_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <2>;
- reg = <0x1040>;
- };
-
gpt4_fck: gpt4_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
};
- gpt5_gate_fck: gpt5_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x1000>;
- };
-
- gpt5_mux_fck: gpt5_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <3>;
- reg = <0x1040>;
- };
-
gpt5_fck: gpt5_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
};
- gpt6_gate_fck: gpt6_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x1000>;
- };
-
- gpt6_mux_fck: gpt6_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x1040>;
- };
-
gpt6_fck: gpt6_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
};
- gpt7_gate_fck: gpt7_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <8>;
- reg = <0x1000>;
- };
-
- gpt7_mux_fck: gpt7_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x1040>;
- };
-
gpt7_fck: gpt7_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
};
- gpt8_gate_fck: gpt8_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <9>;
- reg = <0x1000>;
- };
-
- gpt8_mux_fck: gpt8_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x1040>;
- };
-
gpt8_fck: gpt8_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
};
- gpt9_gate_fck: gpt9_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <10>;
- reg = <0x1000>;
- };
-
- gpt9_mux_fck: gpt9_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x1040>;
- };
-
gpt9_fck: gpt9_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
@@ -1281,54 +1528,6 @@
clock-div = <1>;
};
- gpio6_dbck: gpio6_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <17>;
- };
-
- gpio5_dbck: gpio5_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <16>;
- };
-
- gpio4_dbck: gpio4_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <15>;
- };
-
- gpio3_dbck: gpio3_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <14>;
- };
-
- gpio2_dbck: gpio2_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <13>;
- };
-
- wdt3_fck: wdt3_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <12>;
- };
-
per_l4_ick: per_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -1337,187 +1536,164 @@
clock-div = <1>;
};
- gpio6_ick: gpio6_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <17>;
- };
-
- gpio5_ick: gpio5_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <16>;
- };
-
- gpio4_ick: gpio4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <15>;
- };
-
- gpio3_ick: gpio3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <14>;
- };
-
- gpio2_ick: gpio2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <13>;
- };
-
- wdt3_ick: wdt3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <12>;
- };
-
- uart3_ick: uart3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <11>;
- };
-
- uart4_ick: uart4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <18>;
- };
-
- gpt9_ick: gpt9_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <10>;
- };
-
- gpt8_ick: gpt8_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <9>;
- };
-
- gpt7_ick: gpt7_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <8>;
- };
-
- gpt6_ick: gpt6_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <7>;
- };
-
- gpt5_ick: gpt5_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <6>;
- };
-
- gpt4_ick: gpt4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <5>;
- };
-
- gpt3_ick: gpt3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <4>;
- };
-
- gpt2_ick: gpt2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <3>;
- };
-
- mcbsp2_ick: mcbsp2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <0>;
- };
-
- mcbsp3_ick: mcbsp3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <1>;
- };
-
- mcbsp4_ick: mcbsp4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
+ /* CM_ICLKEN_PER */
+ clock@1010 {
+ compatible = "ti,clksel";
reg = <0x1010>;
- ti,bit-shift = <2>;
- };
-
- mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <0>;
- reg = <0x1000>;
- };
-
- mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <1>;
- reg = <0x1000>;
- };
-
- mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x1000>;
- };
-
- emu_src_mux_ck: emu_src_mux_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
- reg = <0x1140>;
+ #clock-cells = <2>;
+ #address-cells = <0>;
+
+ gpio6_ick: clock-gpio6-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpio6_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <17>;
+ };
+
+ gpio5_ick: clock-gpio5-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpio5_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <16>;
+ };
+
+ gpio4_ick: clock-gpio4-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpio4_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <15>;
+ };
+
+ gpio3_ick: clock-gpio3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpio3_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <14>;
+ };
+
+ gpio2_ick: clock-gpio2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpio2_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <13>;
+ };
+
+ wdt3_ick: clock-wdt3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "wdt3_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <12>;
+ };
+
+ uart3_ick: clock-uart3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "uart3_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <11>;
+ };
+
+ uart4_ick: clock-uart4-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "uart4_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <18>;
+ };
+
+ gpt9_ick: clock-gpt9-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt9_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <10>;
+ };
+
+ gpt8_ick: clock-gpt8-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt8_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <9>;
+ };
+
+ gpt7_ick: clock-gpt7-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt7_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <8>;
+ };
+
+ gpt6_ick: clock-gpt6-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt6_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <7>;
+ };
+
+ gpt5_ick: clock-gpt5-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt5_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <6>;
+ };
+
+ gpt4_ick: clock-gpt4-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt4_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <5>;
+ };
+
+ gpt3_ick: clock-gpt3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt3_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <4>;
+ };
+
+ gpt2_ick: clock-gpt2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "gpt2_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <3>;
+ };
+
+ mcbsp2_ick: clock-mcbsp2-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcbsp2_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <0>;
+ };
+
+ mcbsp3_ick: clock-mcbsp3-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcbsp3_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <1>;
+ };
+
+ mcbsp4_ick: clock-mcbsp4-ick {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clock-output-names = "mcbsp4_ick";
+ clocks = <&per_l4_ick>;
+ ti,bit-shift = <2>;
+ };
};
emu_src_ck: emu_src_ck {
@@ -1526,54 +1702,6 @@
clocks = <&emu_src_mux_ck>;
};
- pclk_fck: pclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <7>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- pclkx2_fck: pclkx2_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <6>;
- ti,max-div = <3>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- atclk_fck: atclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <4>;
- ti,max-div = <3>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- traceclk_src_fck: traceclk_src_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
- ti,bit-shift = <2>;
- reg = <0x1140>;
- };
-
- traceclk_fck: traceclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&traceclk_src_fck>;
- ti,bit-shift = <11>;
- ti,max-div = <7>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
secure_32k_fck: secure_32k_fck {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
index 03d054b2bf9a..801b4f10350c 100644
--- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP4/5 SoC CPU thermal
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/thermal/thermal.h>
@@ -16,20 +13,20 @@ cpu_thermal: cpu_thermal {
polling-delay = <1000>; /* milliseconds */
/* sensor ID */
- thermal-sensors = <&bandgap 0>;
+ thermal-sensors = <&bandgap 0>;
cpu_trips: trips {
- cpu_alert0: cpu_alert {
- temperature = <100000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- cpu_crit: cpu_crit {
- temperature = <125000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
+ cpu_alert0: cpu_alert {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <125000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
cpu_cooling_maps: cooling-maps {
map0 {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 609a8dea946b..0269424350aa 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -49,13 +49,13 @@
&led_wkgpio_pins
>;
- heartbeat {
+ led-heartbeat {
label = "pandaboard::status1";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- mmc {
+ led-mmc {
label = "pandaboard::status2";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
@@ -558,7 +558,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@1 {
+ ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 7c6886cd738f..7631029e4d7a 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -79,10 +79,10 @@
&led_wkgpio_pins
>;
- heartbeat {
+ led-heartbeat {
gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
};
- mmc {
+ led-mmc {
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
index 39297868ec85..581e088231b5 100644
--- a/arch/arm/boot/dts/omap443x-clocks.dtsi
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -8,6 +8,7 @@
bandgap_fclk: bandgap_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "bandgap_fclk";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 8466161197ae..238aceb799f8 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP443x SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "omap4.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 3d6db1db94e0..1b27a862ae81 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP4460 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "omap4.dtsi"
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
index 0f41714cffbb..d9362fef6720 100644
--- a/arch/arm/boot/dts/omap446x-clocks.dtsi
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -8,6 +8,7 @@
div_ts_ck: div_ts_ck@1888 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_ts_ck";
clocks = <&l4_wkup_clk_mux_ck>;
ti,bit-shift = <24>;
reg = <0x1888>;
@@ -17,6 +18,7 @@
bandgap_ts_fclk: bandgap_ts_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "bandgap_ts_fclk";
clocks = <&div_ts_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 1f1c04d8f472..8df73d285638 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -8,18 +8,21 @@
extalt_clkin_ck: extalt_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "extalt_clkin_ck";
clock-frequency = <59000000>;
};
pad_clks_src_ck: pad_clks_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_clks_src_ck";
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "pad_clks_ck";
clocks = <&pad_clks_src_ck>;
ti,bit-shift = <8>;
reg = <0x0108>;
@@ -28,24 +31,28 @@
pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_slimbus_core_clks_ck";
clock-frequency = <12000000>;
};
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
slimbus_src_clk: slimbus_src_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "slimbus_src_clk";
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus_clk";
clocks = <&slimbus_src_clk>;
ti,bit-shift = <10>;
reg = <0x0108>;
@@ -54,84 +61,98 @@
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_32k_ck";
clock-frequency = <32768>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
tie_low_clock_ck: tie_low_clock_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tie_low_clock_ck";
clock-frequency = <0>;
};
utmi_phy_clkout_ck: utmi_phy_clkout_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "utmi_phy_clkout_ck";
clock-frequency = <60000000>;
};
xclk60mhsp1_ck: xclk60mhsp1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp1_ck";
clock-frequency = <60000000>;
};
xclk60mhsp2_ck: xclk60mhsp2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp2_ck";
clock-frequency = <60000000>;
};
xclk60motg_ck: xclk60motg_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60motg_ck";
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
@@ -139,6 +160,7 @@
dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
reg = <0x01f0>;
};
@@ -146,6 +168,7 @@
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -157,6 +180,7 @@
abe_24m_fclk: abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -165,6 +189,7 @@
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
@@ -175,6 +200,7 @@
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -186,6 +212,7 @@
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "core_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
@@ -194,6 +221,7 @@
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@@ -201,12 +229,14 @@
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -218,6 +248,7 @@
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -229,6 +260,7 @@
ddrphy_ck: ddrphy_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "ddrphy_ck";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -237,6 +269,7 @@
dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -248,6 +281,7 @@
div_core_ck: div_core_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_core_ck";
clocks = <&dpll_core_m5x2_ck>;
reg = <0x0100>;
ti,max-div = <2>;
@@ -256,6 +290,7 @@
div_iva_hs_clk: div_iva_hs_clk@1dc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_iva_hs_clk";
clocks = <&dpll_core_m5x2_ck>;
ti,max-div = <4>;
reg = <0x01dc>;
@@ -265,6 +300,7 @@
div_mpu_hs_clk: div_mpu_hs_clk@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_mpu_hs_clk";
clocks = <&dpll_core_m5x2_ck>;
ti,max-div = <4>;
reg = <0x019c>;
@@ -274,6 +310,7 @@
dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -285,6 +322,7 @@
dll_clk_div_ck: dll_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dll_clk_div_ck";
clocks = <&dpll_core_m4x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -293,6 +331,7 @@
dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2_ck";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
reg = <0x01f0>;
@@ -302,6 +341,7 @@
dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "dpll_core_m3x2_gate_ck";
clocks = <&dpll_core_x2_ck>;
ti,bit-shift = <8>;
reg = <0x0134>;
@@ -310,6 +350,7 @@
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
+ clock-output-names = "dpll_core_m3x2_div_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
@@ -319,12 +360,14 @@
dpll_core_m3x2_ck: dpll_core_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "dpll_core_m3x2_ck";
clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
};
dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m7x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -336,6 +379,7 @@
iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "iva_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
ti,bit-shift = <23>;
reg = <0x01ac>;
@@ -344,6 +388,7 @@
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
@@ -353,12 +398,14 @@
dpll_iva_x2_ck: dpll_iva_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_iva_x2_ck";
clocks = <&dpll_iva_ck>;
};
dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m4x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -372,6 +419,7 @@
dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m5x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -385,6 +433,7 @@
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
@@ -392,6 +441,7 @@
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -403,6 +453,7 @@
per_hs_clk_div_ck: per_hs_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_hs_clk_div_ck";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -411,6 +462,7 @@
usb_hs_clk_div_ck: usb_hs_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_hs_clk_div_ck";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
@@ -419,6 +471,7 @@
l3_div_ck: l3_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_div_ck";
clocks = <&div_core_ck>;
ti,bit-shift = <4>;
ti,max-div = <2>;
@@ -428,6 +481,7 @@
l4_div_ck: l4_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l4_div_ck";
clocks = <&l3_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <2>;
@@ -437,6 +491,7 @@
lp_clk_div_ck: lp_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "lp_clk_div_ck";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -445,6 +500,7 @@
mpu_periphclk: mpu_periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_periphclk";
clocks = <&dpll_mpu_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -453,6 +509,7 @@
ocp_abe_iclk: ocp_abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "ocp_abe_iclk";
clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
ti,bit-shift = <24>;
reg = <0x0528>;
@@ -462,6 +519,7 @@
per_abe_24m_fclk: per_abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_abe_24m_fclk";
clocks = <&dpll_abe_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -470,6 +528,7 @@
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
@@ -478,6 +537,7 @@
sys_clkin_ck: sys_clkin_ck@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
@@ -486,6 +546,7 @@
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
reg = <0x0108>;
@@ -494,6 +555,7 @@
abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_refclk_mux_ck";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
reg = <0x010c>;
};
@@ -501,6 +563,7 @@
dbgclk_mux_ck: dbgclk_mux_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dbgclk_mux_ck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -509,6 +572,7 @@
l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "l4_wkup_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
reg = <0x0108>;
};
@@ -516,6 +580,7 @@
syc_clk_div_ck: syc_clk_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "syc_clk_div_ck";
clocks = <&sys_clkin_ck>;
reg = <0x0100>;
ti,max-div = <2>;
@@ -524,6 +589,7 @@
usim_ck: usim_ck@1858 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "usim_ck";
clocks = <&dpll_per_m4x2_ck>;
ti,bit-shift = <24>;
reg = <0x1858>;
@@ -533,6 +599,7 @@
usim_fclk: usim_fclk@1858 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usim_fclk";
clocks = <&usim_ck>;
ti,bit-shift = <8>;
reg = <0x1858>;
@@ -541,6 +608,7 @@
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
+ clock-output-names = "trace_clk_div_ck";
clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
};
};
@@ -548,6 +616,7 @@
&prm_clockdomains {
emu_sys_clkdm: emu_sys_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "emu_sys_clkdm";
clocks = <&trace_clk_div_ck>;
};
};
@@ -556,6 +625,7 @@
per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "per_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
ti,bit-shift = <23>;
reg = <0x014c>;
@@ -564,6 +634,7 @@
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@@ -571,6 +642,7 @@
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -580,6 +652,7 @@
dpll_per_x2_ck: dpll_per_x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
reg = <0x0150>;
};
@@ -587,6 +660,7 @@
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -598,6 +672,7 @@
dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "dpll_per_m3x2_gate_ck";
clocks = <&dpll_per_x2_ck>;
ti,bit-shift = <8>;
reg = <0x0154>;
@@ -606,6 +681,7 @@
dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
+ clock-output-names = "dpll_per_m3x2_div_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0154>;
@@ -615,12 +691,14 @@
dpll_per_m3x2_ck: dpll_per_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "dpll_per_m3x2_ck";
clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
};
dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m4x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -632,6 +710,7 @@
dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m5x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -643,6 +722,7 @@
dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m6x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -654,6 +734,7 @@
dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m7x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -665,6 +746,7 @@
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
@@ -672,6 +754,7 @@
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo_ck";
clocks = <&dpll_usb_ck>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
@@ -683,6 +766,7 @@
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -694,6 +778,7 @@
ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "ducati_clk_mux_ck";
clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
reg = <0x0100>;
};
@@ -701,6 +786,7 @@
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -709,6 +795,7 @@
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -717,6 +804,7 @@
func_24mc_fclk: func_24mc_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24mc_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -725,6 +813,7 @@
func_48m_fclk: func_48m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
reg = <0x0108>;
ti,dividers = <4>, <8>;
@@ -733,6 +822,7 @@
func_48mc_fclk: func_48mc_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48mc_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -741,6 +831,7 @@
func_64m_fclk: func_64m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_64m_fclk";
clocks = <&dpll_per_m4x2_ck>;
reg = <0x0108>;
ti,dividers = <2>, <4>;
@@ -749,6 +840,7 @@
func_96m_fclk: func_96m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
reg = <0x0108>;
ti,dividers = <2>, <4>;
@@ -757,6 +849,7 @@
init_60m_fclk: init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
@@ -765,6 +858,7 @@
per_abe_nc_fclk: per_abe_nc_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_nc_fclk";
clocks = <&dpll_abe_m2_ck>;
reg = <0x0108>;
ti,max-div = <2>;
@@ -773,6 +867,7 @@
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy_cm_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
@@ -782,6 +877,7 @@
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "l3_init_clkdm";
clocks = <&dpll_usb_ck>;
};
};
@@ -790,6 +886,7 @@
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk0_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0310>;
@@ -798,6 +895,7 @@
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk0_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0310>;
@@ -806,12 +904,14 @@
auxclk0_src_ck: auxclk0_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk0_src_ck";
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk0_ck";
clocks = <&auxclk0_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -821,6 +921,7 @@
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk1_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0314>;
@@ -829,6 +930,7 @@
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk1_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0314>;
@@ -837,12 +939,14 @@
auxclk1_src_ck: auxclk1_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk1_src_ck";
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk1_ck";
clocks = <&auxclk1_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -852,6 +956,7 @@
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk2_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0318>;
@@ -860,6 +965,7 @@
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk2_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0318>;
@@ -868,12 +974,14 @@
auxclk2_src_ck: auxclk2_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk2_src_ck";
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk2_ck";
clocks = <&auxclk2_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -883,6 +991,7 @@
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk3_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x031c>;
@@ -891,6 +1000,7 @@
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk3_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x031c>;
@@ -899,12 +1009,14 @@
auxclk3_src_ck: auxclk3_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk3_src_ck";
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk3_ck";
clocks = <&auxclk3_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -914,6 +1026,7 @@
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk4_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0320>;
@@ -922,6 +1035,7 @@
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk4_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0320>;
@@ -930,12 +1044,14 @@
auxclk4_src_ck: auxclk4_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk4_src_ck";
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk4_ck";
clocks = <&auxclk4_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -945,6 +1061,7 @@
auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk5_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0324>;
@@ -953,6 +1070,7 @@
auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk5_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0324>;
@@ -961,12 +1079,14 @@
auxclk5_src_ck: auxclk5_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk5_src_ck";
clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
};
auxclk5_ck: auxclk5_ck@324 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk5_ck";
clocks = <&auxclk5_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -976,6 +1096,7 @@
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq0_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0210>;
@@ -984,6 +1105,7 @@
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq1_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0214>;
@@ -992,6 +1114,7 @@
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq2_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0218>;
@@ -1000,6 +1123,7 @@
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq3_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x021c>;
@@ -1008,6 +1132,7 @@
auxclkreq4_ck: auxclkreq4_ck@220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq4_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0220>;
@@ -1016,6 +1141,7 @@
auxclkreq5_ck: auxclkreq5_ck@224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq5_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0224>;
@@ -1025,6 +1151,7 @@
&cm1 {
mpuss_cm: mpuss_cm@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpuss_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1032,6 +1159,7 @@
mpuss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpuss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1039,6 +1167,7 @@
tesla_cm: tesla_cm@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "tesla_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1046,6 +1175,7 @@
tesla_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "tesla_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1053,6 +1183,7 @@
abe_cm: abe_cm@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "abe_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1060,6 +1191,7 @@
abe_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "abe_clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
@@ -1070,6 +1202,7 @@
&cm2 {
l4_ao_cm: l4_ao_cm@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_ao_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1077,6 +1210,7 @@
l4_ao_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_ao_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1084,6 +1218,7 @@
l3_1_cm: l3_1_cm@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1091,6 +1226,7 @@
l3_1_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1098,6 +1234,7 @@
l3_2_cm: l3_2_cm@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_2_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1105,6 +1242,7 @@
l3_2_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_2_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1112,6 +1250,7 @@
ducati_cm: ducati_cm@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ducati_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1119,6 +1258,7 @@
ducati_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ducati_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1126,6 +1266,7 @@
l3_dma_cm: l3_dma_cm@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1133,6 +1274,7 @@
l3_dma_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1140,6 +1282,7 @@
l3_emif_cm: l3_emif_cm@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1147,6 +1290,7 @@
l3_emif_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_emif_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1154,6 +1298,7 @@
d2d_cm: d2d_cm@c00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "d2d_cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1161,6 +1306,7 @@
d2d_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "d2d_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1168,6 +1314,7 @@
l4_cfg_cm: l4_cfg_cm@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1175,6 +1322,7 @@
l4_cfg_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_cfg_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1182,6 +1330,7 @@
l3_instr_cm: l3_instr_cm@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1189,6 +1338,7 @@
l3_instr_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_instr_clkctrl";
reg = <0x20 0x24>;
#clock-cells = <2>;
};
@@ -1196,6 +1346,7 @@
ivahd_cm: ivahd_cm@f00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ivahd_cm";
reg = <0xf00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1203,6 +1354,7 @@
ivahd_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ivahd_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
@@ -1210,6 +1362,7 @@
iss_cm: iss_cm@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "iss_cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1217,6 +1370,7 @@
iss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "iss_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
@@ -1224,6 +1378,7 @@
l3_dss_cm: l3_dss_cm@1100 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_dss_cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1231,6 +1386,7 @@
l3_dss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_dss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1238,6 +1394,7 @@
l3_gfx_cm: l3_gfx_cm@1200 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_gfx_cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1245,6 +1402,7 @@
l3_gfx_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_gfx_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1252,6 +1410,7 @@
l3_init_cm: l3_init_cm@1300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_init_cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1259,26 +1418,30 @@
l3_init_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_init_clkctrl";
reg = <0x20 0xc4>;
#clock-cells = <2>;
};
};
- l4_per_cm: l4_per_cm@1400 {
+ l4_per_cm: clock@1400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_per_cm";
reg = <0x1400 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1400 0x200>;
l4_per_clkctrl: clock@20 {
- compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_per_clkctrl";
reg = <0x20 0x144>;
#clock-cells = <2>;
};
l4_secure_clkctrl: clock@1a0 {
- compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_secure_clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
@@ -1288,6 +1451,7 @@
&prm {
l4_wkup_cm: l4_wkup_cm@1800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_wkup_cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1295,6 +1459,7 @@
l4_wkup_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x20 0x5c>;
#clock-cells = <2>;
};
@@ -1302,6 +1467,7 @@
emu_sys_cm: emu_sys_cm@1a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emu_sys_cm";
reg = <0x1a00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1309,6 +1475,7 @@
emu_sys_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emu_sys_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index ca759b7b8a58..2d87b9fc230e 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -84,36 +84,36 @@
};
lcd0: display {
- compatible = "startek,startek-kd050c", "panel-dpi";
- label = "lcd";
-
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins>;
-
- enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
-
- panel-timing {
- clock-frequency = <33000000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <40>;
- hback-porch = <40>;
- hsync-len = <43>;
- vback-porch = <29>;
- vfront-porch = <13>;
- vsync-len = <3>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-
- port {
- lcd_in: endpoint {
- remote-endpoint = <&dpi_lcd_out>;
- };
- };
- };
+ compatible = "startek,startek-kd050c", "panel-dpi";
+ label = "lcd";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins>;
+
+ enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
+
+ panel-timing {
+ clock-frequency = <33000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hfront-porch = <40>;
+ hback-porch = <40>;
+ hsync-len = <43>;
+ vback-porch = <29>;
+ vfront-porch = <13>;
+ vsync-len = <3>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_lcd_out>;
+ };
+ };
+ };
hdmi0: connector0 {
compatible = "hdmi-connector";
@@ -644,8 +644,8 @@
};
&usb3 {
- extcon = <&extcon_usb3>;
- vbus-supply = <&smps10_out1_reg>;
+ extcon = <&extcon_usb3>;
+ vbus-supply = <&smps10_out1_reg>;
};
&cpu0 {
diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi
index 02e76338bfbc..e0d8e39a0014 100644
--- a/arch/arm/boot/dts/omap5-core-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP543x SoC CORE thermal
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
index bf8fa9372e57..1b4b7d9136c8 100644
--- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP543x SoC GPU thermal
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts
index 76e499d89d24..3851120857d7 100644
--- a/arch/arm/boot/dts/omap5-igep0050.dts
+++ b/arch/arm/boot/dts/omap5-igep0050.dts
@@ -128,7 +128,7 @@
#address-cells = <1>;
#size-cells = <0>;
- ethernet: usbether@3 {
+ ethernet: ethernet@3 {
compatible = "usb424,7500";
reg = <3>;
};
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi
index 06cc3a19ddaa..3b505fe415ed 100644
--- a/arch/arm/boot/dts/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/omap5-l4.dtsi
@@ -482,7 +482,7 @@
clocks = <&usb_phy_cm_clk32k>,
<&sys_clkin>,
<&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
- clock-names = "wkupclk",
+ clock-names = "wkupclk",
"sysclk",
"refclk";
#phy-cells = <0>;
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 51d5fcae5081..453da9f18a99 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -209,7 +209,7 @@
#size-cells = <0>;
};
- ethernet: usbether@3 {
+ ethernet: ethernet@3 {
compatible = "usb424,9730";
reg = <3>;
};
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 42f2c447727d..5cf3b0e78c15 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -8,12 +8,14 @@
pad_clks_src_ck: pad_clks_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_clks_src_ck";
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "pad_clks_ck";
clocks = <&pad_clks_src_ck>;
ti,bit-shift = <8>;
reg = <0x0108>;
@@ -22,18 +24,21 @@
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
slimbus_src_clk: slimbus_src_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "slimbus_src_clk";
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus_clk";
clocks = <&slimbus_src_clk>;
ti,bit-shift = <10>;
reg = <0x0108>;
@@ -42,66 +47,77 @@
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_32k_ck";
clock-frequency = <32768>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
xclk60mhsp1_ck: xclk60mhsp1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp1_ck";
clock-frequency = <60000000>;
};
xclk60mhsp2_ck: xclk60mhsp2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp2_ck";
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
@@ -109,12 +125,14 @@
dpll_abe_x2_ck: dpll_abe_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
reg = <0x01f0>;
@@ -124,6 +142,7 @@
abe_24m_fclk: abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -132,6 +151,7 @@
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
@@ -141,6 +161,7 @@
abe_iclk: abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_iclk";
clocks = <&aess_fclk>;
ti,bit-shift = <24>;
reg = <0x0528>;
@@ -150,6 +171,7 @@
abe_lp_clk_div: abe_lp_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_lp_clk_div";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -158,6 +180,7 @@
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
reg = <0x01f4>;
@@ -167,6 +190,7 @@
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_core_byp_mux";
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
@@ -175,6 +199,7 @@
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@@ -182,12 +207,14 @@
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h21x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0150>;
@@ -197,6 +224,7 @@
c2c_fclk: c2c_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "c2c_fclk";
clocks = <&dpll_core_h21x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -205,6 +233,7 @@
c2c_iclk: c2c_iclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "c2c_iclk";
clocks = <&c2c_fclk>;
clock-mult = <1>;
clock-div = <2>;
@@ -213,6 +242,7 @@
dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h11x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0138>;
@@ -222,6 +252,7 @@
dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h12x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x013c>;
@@ -231,6 +262,7 @@
dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h13x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0140>;
@@ -240,6 +272,7 @@
dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h14x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0144>;
@@ -249,6 +282,7 @@
dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h22x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0154>;
@@ -258,6 +292,7 @@
dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h23x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0158>;
@@ -267,6 +302,7 @@
dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h24x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x015c>;
@@ -276,6 +312,7 @@
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
reg = <0x0130>;
@@ -285,6 +322,7 @@
dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m3x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
@@ -294,6 +332,7 @@
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -302,6 +341,7 @@
dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_iva_byp_mux";
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
@@ -310,6 +350,7 @@
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
@@ -319,12 +360,14 @@
dpll_iva_x2_ck: dpll_iva_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_iva_x2_ck";
clocks = <&dpll_iva_ck>;
};
dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_h11x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
reg = <0x01b8>;
@@ -336,6 +379,7 @@
dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_h12x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
reg = <0x01bc>;
@@ -347,6 +391,7 @@
mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -355,6 +400,7 @@
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
@@ -362,6 +408,7 @@
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
reg = <0x0170>;
@@ -371,6 +418,7 @@
per_dpll_hs_clk_div: per_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -379,6 +427,7 @@
usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
@@ -387,6 +436,7 @@
l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_iclk_div";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x100>;
@@ -397,6 +447,7 @@
gpu_l3_iclk: gpu_l3_iclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gpu_l3_iclk";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <1>;
@@ -405,6 +456,7 @@
l4_root_clk_div: l4_root_clk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l4_root_clk_div";
ti,max-div = <2>;
ti,bit-shift = <8>;
reg = <0x100>;
@@ -415,6 +467,7 @@
slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus1_slimbus_clk";
clocks = <&slimbus_clk>;
ti,bit-shift = <11>;
reg = <0x0560>;
@@ -423,6 +476,7 @@
aess_fclk: aess_fclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "aess_fclk";
clocks = <&abe_clk>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -432,6 +486,7 @@
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mcasp_sync_mux_ck";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
ti,bit-shift = <26>;
reg = <0x0540>;
@@ -440,6 +495,7 @@
mcasp_gfclk: mcasp_gfclk@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mcasp_gfclk";
clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
ti,bit-shift = <24>;
reg = <0x0540>;
@@ -448,6 +504,7 @@
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
@@ -455,6 +512,7 @@
sys_clkin: sys_clkin@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
@@ -463,6 +521,7 @@
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux";
clocks = <&sys_clkin>, <&sys_32k_ck>;
reg = <0x0108>;
};
@@ -470,6 +529,7 @@
abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_clk_mux";
clocks = <&sys_clkin>, <&sys_32k_ck>;
reg = <0x010c>;
};
@@ -477,6 +537,7 @@
custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "custefuse_sys_gfclk_div";
clocks = <&sys_clkin>;
clock-mult = <1>;
clock-div = <2>;
@@ -485,6 +546,7 @@
dss_syc_gfclk_div: dss_syc_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dss_syc_gfclk_div";
clocks = <&sys_clkin>;
clock-mult = <1>;
clock-div = <1>;
@@ -493,6 +555,7 @@
wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wkupaon_iclk_mux";
clocks = <&sys_clkin>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
@@ -500,6 +563,7 @@
l3instr_ts_gclk_div: l3instr_ts_gclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3instr_ts_gclk_div";
clocks = <&wkupaon_iclk_mux>;
clock-mult = <1>;
clock-div = <1>;
@@ -511,6 +575,7 @@
dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_per_byp_mux";
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
@@ -519,6 +584,7 @@
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@@ -526,12 +592,14 @@
dpll_per_x2_ck: dpll_per_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
};
dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h11x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x0158>;
@@ -541,6 +609,7 @@
dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h12x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x015c>;
@@ -550,6 +619,7 @@
dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h14x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x0164>;
@@ -559,6 +629,7 @@
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -568,6 +639,7 @@
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -577,6 +649,7 @@
dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m3x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0154>;
@@ -586,6 +659,7 @@
dpll_unipro1_ck: dpll_unipro1_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_unipro1_ck";
clocks = <&sys_clkin>, <&sys_clkin>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
@@ -593,6 +667,7 @@
dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_unipro1_clkdcoldo";
clocks = <&dpll_unipro1_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -601,6 +676,7 @@
dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_unipro1_m2_ck";
clocks = <&dpll_unipro1_ck>;
ti,max-div = <127>;
reg = <0x0210>;
@@ -610,6 +686,7 @@
dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_unipro2_ck";
clocks = <&sys_clkin>, <&sys_clkin>;
reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
};
@@ -617,6 +694,7 @@
dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_unipro2_clkdcoldo";
clocks = <&dpll_unipro2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -625,6 +703,7 @@
dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_unipro2_m2_ck";
clocks = <&dpll_unipro2_ck>;
ti,max-div = <127>;
reg = <0x01d0>;
@@ -634,6 +713,7 @@
dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_usb_byp_mux";
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
@@ -642,6 +722,7 @@
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
@@ -649,6 +730,7 @@
dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -657,6 +739,7 @@
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
reg = <0x0190>;
@@ -666,6 +749,7 @@
func_128m_clk: func_128m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_128m_clk";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -674,6 +758,7 @@
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -682,6 +767,7 @@
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -690,6 +776,7 @@
func_48m_fclk: func_48m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -698,6 +785,7 @@
func_96m_fclk: func_96m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -706,6 +794,7 @@
l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
@@ -714,6 +803,7 @@
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "iss_ctrlclk";
clocks = <&func_96m_fclk>;
ti,bit-shift = <8>;
reg = <0x1320>;
@@ -722,6 +812,7 @@
lli_txphy_clk: lli_txphy_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "lli_txphy_clk";
clocks = <&dpll_unipro1_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x0f20>;
@@ -730,6 +821,7 @@
lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "lli_txphy_ls_clk";
clocks = <&dpll_unipro1_m2_ck>;
ti,bit-shift = <9>;
reg = <0x0f20>;
@@ -738,6 +830,7 @@
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy_cm_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
@@ -746,6 +839,7 @@
fdif_fclk: fdif_fclk@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "fdif_fclk";
clocks = <&dpll_per_h11x2_ck>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -755,6 +849,7 @@
gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_core_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
ti,bit-shift = <24>;
reg = <0x1520>;
@@ -763,6 +858,7 @@
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_hyd_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
ti,bit-shift = <25>;
reg = <0x1520>;
@@ -771,6 +867,7 @@
hsi_fclk: hsi_fclk@1638 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "hsi_fclk";
clocks = <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -781,6 +878,7 @@
&cm_core_clockdomains {
l3init_clkdm: l3init_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "l3init_clkdm";
clocks = <&dpll_usb_ck>;
};
};
@@ -789,6 +887,7 @@
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk0_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0310>;
@@ -797,6 +896,7 @@
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk0_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0310>;
@@ -805,12 +905,14 @@
auxclk0_src_ck: auxclk0_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk0_src_ck";
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk0_ck";
clocks = <&auxclk0_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -820,6 +922,7 @@
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk1_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0314>;
@@ -828,6 +931,7 @@
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk1_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0314>;
@@ -836,12 +940,14 @@
auxclk1_src_ck: auxclk1_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk1_src_ck";
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk1_ck";
clocks = <&auxclk1_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -851,6 +957,7 @@
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk2_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0318>;
@@ -859,6 +966,7 @@
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk2_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0318>;
@@ -867,12 +975,14 @@
auxclk2_src_ck: auxclk2_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk2_src_ck";
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk2_ck";
clocks = <&auxclk2_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -882,6 +992,7 @@
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk3_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x031c>;
@@ -890,6 +1001,7 @@
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk3_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x031c>;
@@ -898,12 +1010,14 @@
auxclk3_src_ck: auxclk3_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk3_src_ck";
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk3_ck";
clocks = <&auxclk3_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -913,6 +1027,7 @@
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk4_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0320>;
@@ -921,6 +1036,7 @@
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk4_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0320>;
@@ -929,12 +1045,14 @@
auxclk4_src_ck: auxclk4_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk4_src_ck";
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk4_ck";
clocks = <&auxclk4_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -944,6 +1062,7 @@
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq0_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0210>;
@@ -952,6 +1071,7 @@
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq1_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0214>;
@@ -960,6 +1080,7 @@
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq2_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0218>;
@@ -968,6 +1089,7 @@
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq3_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x021c>;
@@ -977,6 +1099,7 @@
&cm_core_aon {
mpu_cm: mpu_cm@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -984,6 +1107,7 @@
mpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -991,6 +1115,7 @@
dsp_cm: dsp_cm@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -998,6 +1123,7 @@
dsp_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1005,6 +1131,7 @@
abe_cm: abe_cm@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "abe_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1012,6 +1139,7 @@
abe_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "abe_clkctrl";
reg = <0x20 0x64>;
#clock-cells = <2>;
};
@@ -1022,6 +1150,7 @@
&cm_core {
l3main1_cm: l3main1_cm@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1029,6 +1158,7 @@
l3main1_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1036,6 +1166,7 @@
l3main2_cm: l3main2_cm@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main2_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1043,6 +1174,7 @@
l3main2_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1050,6 +1182,7 @@
ipu_cm: ipu_cm@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1057,6 +1190,7 @@
ipu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1064,6 +1198,7 @@
dma_cm: dma_cm@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1071,6 +1206,7 @@
dma_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1078,6 +1214,7 @@
emif_cm: emif_cm@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1085,6 +1222,7 @@
emif_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1092,6 +1230,7 @@
l4cfg_cm: l4cfg_cm@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1099,6 +1238,7 @@
l4cfg_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4cfg_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1106,6 +1246,7 @@
l3instr_cm: l3instr_cm@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1113,26 +1254,30 @@
l3instr_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3instr_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
- l4per_cm: l4per_cm@1000 {
+ l4per_cm: clock@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4per_cm";
reg = <0x1000 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x200>;
l4per_clkctrl: clock@20 {
- compatible = "ti,clkctrl-l4per", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4per_clkctrl";
reg = <0x20 0x15c>;
#clock-cells = <2>;
};
l4sec_clkctrl: clock@1a0 {
- compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4sec_clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
@@ -1140,6 +1285,7 @@
dss_cm: dss_cm@1400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dss_cm";
reg = <0x1400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1147,6 +1293,7 @@
dss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1154,6 +1301,7 @@
gpu_cm: gpu_cm@1500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gpu_cm";
reg = <0x1500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1161,6 +1309,7 @@
gpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1168,6 +1317,7 @@
l3init_cm: l3init_cm@1600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3init_cm";
reg = <0x1600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1175,6 +1325,7 @@
l3init_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3init_clkctrl";
reg = <0x20 0xd4>;
#clock-cells = <2>;
};
@@ -1184,6 +1335,7 @@
&prm {
wkupaon_cm: wkupaon_cm@1900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkupaon_cm";
reg = <0x1900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1191,6 +1343,7 @@
wkupaon_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "wkupaon_clkctrl";
reg = <0x20 0x5c>;
#clock-cells = <2>;
};
@@ -1201,6 +1354,7 @@
fref_xtal_ck: fref_xtal_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "fref_xtal_ck";
clocks = <&sys_clkin>;
ti,bit-shift = <28>;
reg = <0x14>;
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
index 422958d13d42..03471d30bfd9 100644
--- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 0043e0040153..f17e25ac98dd 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
/*
* TODO: add Orion USB device port init when kernel.org support is added.
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
index 0ca6208a267d..d57859998350 100644
--- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
+++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
index f667012b26ca..819f9efb7058 100644
--- a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
+++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
#include "orion5x.dtsi"
diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
index d1ed71c60209..86b87fb26dc9 100644
--- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
#include "orion5x.dtsi"
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index ea081afa469d..fb203e7d37f5 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
/dts-v1/;
@@ -142,8 +137,12 @@
port@3 {
reg = <3>;
- label = "cpu";
ethernet = <&ethport>;
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
port@5 {
@@ -213,6 +212,7 @@
/* Hardwired to DSA switch */
speed = <1000>;
duplex = <1>;
+ phy-mode = "rgmii";
};
};
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
index 487324f7c54e..fd78aa02a3c5 100644
--- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
/dts-v1/;
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 61e631b3fd8b..2d41f5c166ee 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
diff --git a/arch/arm/boot/dts/ox810se-wd-mbwe.dts b/arch/arm/boot/dts/ox810se-wd-mbwe.dts
deleted file mode 100644
index c59e06ff2423..000000000000
--- a/arch/arm/boot/dts/ox810se-wd-mbwe.dts
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition
- *
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-#include "ox810se.dtsi"
-
-/ {
- model = "Western Digital My Book World Edition";
-
- compatible = "wd,mbwe", "oxsemi,ox810se";
-
- chosen {
- bootargs = "console=ttyS1,115200n8 earlyprintk=serial";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x48000000 0x8000000>;
- };
-
- aliases {
- serial1 = &uart1;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- power {
- label = "power";
- gpios = <&gpio0 0 1>;
- linux,code = <0x198>;
- };
-
- recovery {
- label = "recovery";
- gpios = <&gpio0 4 1>;
- linux,code = <0xab>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- a0 {
- label = "activity0";
- gpios = <&gpio0 25 0>;
- default-state = "keep";
- };
-
- a1 {
- label = "activity1";
- gpios = <&gpio0 26 0>;
- default-state = "keep";
- };
-
- a2 {
- label = "activity2";
- gpios = <&gpio0 5 0>;
- default-state = "keep";
- };
-
- a3 {
- label = "activity3";
- gpios = <&gpio0 6 0>;
- default-state = "keep";
- };
-
- a4 {
- label = "activity4";
- gpios = <&gpio0 7 0>;
- default-state = "keep";
- };
-
- a5 {
- label = "activity5";
- gpios = <&gpio1 2 0>;
- default-state = "keep";
- };
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- gpios = <&gpio0 3 0 /* sda */
- &gpio0 2 0 /* scl */
- >;
- i2c-gpio,delay-us = <2>; /* ~100 kHz */
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc0: rtc@48 {
- compatible = "st,m41t00";
- reg = <0x68>;
- };
- };
-};
-
-&etha {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
-};
diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi
deleted file mode 100644
index 96c0745f7b70..000000000000
--- a/arch/arm/boot/dts/ox810se.dtsi
+++ /dev/null
@@ -1,357 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
- *
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <dt-bindings/clock/oxsemi,ox810se.h>
-#include <dt-bindings/reset/oxsemi,ox810se.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "oxsemi,ox810se";
-
- cpus {
- #address-cells = <0>;
- #size-cells = <0>;
-
- cpu {
- device_type = "cpu";
- compatible = "arm,arm926ej-s";
- clocks = <&armclk>;
- };
- };
-
- memory {
- device_type = "memory";
- /* Max 256MB @ 0x48000000 */
- reg = <0x48000000 0x10000000>;
- };
-
- clocks {
- osc: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- gmacclk: gmacclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- rpsclk: rpsclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&osc>;
- };
-
- pll400: pll400 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <733333333>;
- };
-
- sysclk: sysclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <4>;
- clock-mult = <1>;
- clocks = <&pll400>;
- };
-
- armclk: armclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- clocks = <&pll400>;
- };
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges;
- interrupt-parent = <&intc>;
-
- etha: ethernet@40400000 {
- compatible = "oxsemi,ox810se-dwmac", "snps,dwmac";
- reg = <0x40400000 0x2000>;
- interrupts = <8>;
- interrupt-names = "macirq";
- mac-address = [000000000000]; /* Filled in by U-Boot */
- phy-mode = "rgmii";
-
- clocks = <&stdclk 6>, <&gmacclk>;
- clock-names = "gmac", "stmmaceth";
- resets = <&reset 6>;
-
- /* Regmap for sys registers */
- oxsemi,sys-ctrl = <&sys>;
-
- status = "disabled";
- };
-
- apb-bridge@44000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0x44000000 0x1000000>;
-
- pinctrl: pinctrl {
- compatible = "oxsemi,ox810se-pinctrl";
-
- /* Regmap for sys registers */
- oxsemi,sys-ctrl = <&sys>;
-
- pinctrl_uart0: uart0 {
- uart0a {
- pins = "gpio31";
- function = "fct3";
- };
- uart0b {
- pins = "gpio32";
- function = "fct3";
- };
- };
-
- pinctrl_uart0_modem: uart0_modem {
- uart0c {
- pins = "gpio27";
- function = "fct3";
- };
- uart0d {
- pins = "gpio28";
- function = "fct3";
- };
- uart0e {
- pins = "gpio29";
- function = "fct3";
- };
- uart0f {
- pins = "gpio30";
- function = "fct3";
- };
- uart0g {
- pins = "gpio33";
- function = "fct3";
- };
- uart0h {
- pins = "gpio34";
- function = "fct3";
- };
- };
-
- pinctrl_uart1: uart1 {
- uart1a {
- pins = "gpio20";
- function = "fct3";
- };
- uart1b {
- pins = "gpio22";
- function = "fct3";
- };
- };
-
- pinctrl_uart1_modem: uart1_modem {
- uart1c {
- pins = "gpio8";
- function = "fct3";
- };
- uart1d {
- pins = "gpio9";
- function = "fct3";
- };
- uart1e {
- pins = "gpio23";
- function = "fct3";
- };
- uart1f {
- pins = "gpio24";
- function = "fct3";
- };
- uart1g {
- pins = "gpio25";
- function = "fct3";
- };
- uart1h {
- pins = "gpio26";
- function = "fct3";
- };
- };
-
- pinctrl_uart2: uart2 {
- uart2a {
- pins = "gpio6";
- function = "fct3";
- };
- uart2b {
- pins = "gpio7";
- function = "fct3";
- };
- };
-
- pinctrl_uart2_modem: uart2_modem {
- uart2c {
- pins = "gpio0";
- function = "fct3";
- };
- uart2d {
- pins = "gpio1";
- function = "fct3";
- };
- uart2e {
- pins = "gpio2";
- function = "fct3";
- };
- uart2f {
- pins = "gpio3";
- function = "fct3";
- };
- uart2g {
- pins = "gpio4";
- function = "fct3";
- };
- uart2h {
- pins = "gpio5";
- function = "fct3";
- };
- };
- };
-
- gpio0: gpio@0 {
- compatible = "oxsemi,ox810se-gpio";
- reg = <0x000000 0x100000>;
- interrupts = <21>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <32>;
- oxsemi,gpio-bank = <0>;
- gpio-ranges = <&pinctrl 0 0 32>;
- };
-
- gpio1: gpio@100000 {
- compatible = "oxsemi,ox810se-gpio";
- reg = <0x100000 0x100000>;
- interrupts = <22>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <3>;
- oxsemi,gpio-bank = <1>;
- gpio-ranges = <&pinctrl 0 32 3>;
- };
-
- uart0: serial@200000 {
- compatible = "ns16550a";
- reg = <0x200000 0x100000>;
- clocks = <&sysclk>;
- interrupts = <23>;
- reg-shift = <0>;
- fifo-size = <16>;
- reg-io-width = <1>;
- current-speed = <115200>;
- no-loopback-test;
- status = "disabled";
- resets = <&reset RESET_UART1>;
- };
-
- uart1: serial@300000 {
- compatible = "ns16550a";
- reg = <0x300000 0x100000>;
- clocks = <&sysclk>;
- interrupts = <24>;
- reg-shift = <0>;
- fifo-size = <16>;
- reg-io-width = <1>;
- current-speed = <115200>;
- no-loopback-test;
- status = "disabled";
- resets = <&reset RESET_UART2>;
- };
-
- uart2: serial@900000 {
- compatible = "ns16550a";
- reg = <0x900000 0x100000>;
- clocks = <&sysclk>;
- interrupts = <29>;
- reg-shift = <0>;
- fifo-size = <16>;
- reg-io-width = <1>;
- current-speed = <115200>;
- no-loopback-test;
- status = "disabled";
- resets = <&reset RESET_UART3>;
- };
-
- uart3: serial@a00000 {
- compatible = "ns16550a";
- reg = <0xa00000 0x100000>;
- clocks = <&sysclk>;
- interrupts = <30>;
- reg-shift = <0>;
- fifo-size = <16>;
- reg-io-width = <1>;
- current-speed = <115200>;
- no-loopback-test;
- status = "disabled";
- resets = <&reset RESET_UART4>;
- };
- };
-
- apb-bridge@45000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0x45000000 0x1000000>;
-
- sys: sys-ctrl@0 {
- compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
- reg = <0x000000 0x100000>;
-
- reset: reset-controller {
- compatible = "oxsemi,ox810se-reset";
- #reset-cells = <1>;
- };
-
- stdclk: stdclk {
- compatible = "oxsemi,ox810se-stdclk";
- #clock-cells = <1>;
- };
- };
-
- rps@300000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0x300000 0x100000>;
-
- intc: interrupt-controller@0 {
- compatible = "oxsemi,ox810se-rps-irq";
- interrupt-controller;
- reg = <0 0x200>;
- #interrupt-cells = <1>;
- valid-mask = <0xffffffff>;
- clear-mask = <0xffffffff>;
- };
-
- timer0: timer@200 {
- compatible = "oxsemi,ox810se-rps-timer";
- reg = <0x200 0x40>;
- clocks = <&rpsclk>;
- interrupts = <4 5>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
deleted file mode 100644
index c3daceccde55..000000000000
--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
- *
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-
-/ {
- model = "Cloud Engines PogoPlug Series 3";
-
- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- };
-
- leds {
- compatible = "gpio-leds";
-
- blue {
- label = "pogoplug:blue";
- gpios = <&gpio0 2 0>;
- default-state = "keep";
- };
-
- orange {
- label = "pogoplug:orange";
- gpios = <&gpio1 16 1>;
- default-state = "keep";
- };
-
- green {
- label = "pogoplug:green";
- gpios = <&gpio1 17 1>;
- default-state = "keep";
- };
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "boot";
- reg = <0x00000000 0x00e00000>;
- read-only;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
- };
- };
-};
-
-&etha {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi
deleted file mode 100644
index 90846a7655b4..000000000000
--- a/arch/arm/boot/dts/ox820.dtsi
+++ /dev/null
@@ -1,299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
- *
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/oxsemi,ox820.h>
-#include <dt-bindings/reset/oxsemi,ox820.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "oxsemi,ox820";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "oxsemi,ox820-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,arm11mpcore";
- clocks = <&armclk>;
- reg = <0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,arm11mpcore";
- clocks = <&armclk>;
- reg = <1>;
- };
- };
-
- memory {
- device_type = "memory";
- /* Max 512MB @ 0x60000000 */
- reg = <0x60000000 0x20000000>;
- };
-
- clocks {
- osc: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- gmacclk: gmacclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- sysclk: sysclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <4>;
- clock-mult = <1>;
- clocks = <&osc>;
- };
-
- plla: plla {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <850000000>;
- };
-
- armclk: armclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- clocks = <&plla>;
- };
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges;
- interrupt-parent = <&gic>;
-
- nandc: nand-controller@41000000 {
- compatible = "oxsemi,ox820-nand";
- reg = <0x41000000 0x100000>;
- clocks = <&stdclk CLK_820_NAND>;
- resets = <&reset RESET_NAND>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- etha: ethernet@40400000 {
- compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
- reg = <0x40400000 0x2000>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq", "eth_wake_irq";
- mac-address = [000000000000]; /* Filled in by U-Boot */
- phy-mode = "rgmii";
-
- clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
- clock-names = "gmac", "stmmaceth";
- resets = <&reset RESET_MAC>;
-
- /* Regmap for sys registers */
- oxsemi,sys-ctrl = <&sys>;
-
- status = "disabled";
- };
-
- apb-bridge@44000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0x44000000 0x1000000>;
-
- pinctrl: pinctrl {
- compatible = "oxsemi,ox820-pinctrl";
-
- /* Regmap for sys registers */
- oxsemi,sys-ctrl = <&sys>;
-
- pinctrl_uart0: uart0 {
- uart0 {
- pins = "gpio30", "gpio31";
- function = "fct5";
- };
- };
-
- pinctrl_uart0_modem: uart0_modem {
- uart0_modem_a {
- pins = "gpio24", "gpio24", "gpio26", "gpio27";
- function = "fct4";
- };
- uart0_modem_b {
- pins = "gpio28", "gpio29";
- function = "fct5";
- };
- };
-
- pinctrl_uart1: uart1 {
- uart1 {
- pins = "gpio7", "gpio8";
- function = "fct4";
- };
- };
-
- pinctrl_uart1_modem: uart1_modem {
- uart1_modem {
- pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
- function = "fct4";
- };
- };
-
- pinctrl_etha_mdio: etha_mdio {
- etha_mdio {
- pins = "gpio3", "gpio4";
- function = "fct1";
- };
- };
-
- pinctrl_nand: nand {
- nand {
- pins = "gpio12", "gpio13", "gpio14", "gpio15",
- "gpio16", "gpio17", "gpio18", "gpio19",
- "gpio20", "gpio21", "gpio22", "gpio23",
- "gpio24";
- function = "fct1";
- };
- };
- };
-
- gpio0: gpio@0 {
- compatible = "oxsemi,ox820-gpio";
- reg = <0x000000 0x100000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <32>;
- oxsemi,gpio-bank = <0>;
- gpio-ranges = <&pinctrl 0 0 32>;
- };
-
- gpio1: gpio@100000 {
- compatible = "oxsemi,ox820-gpio";
- reg = <0x100000 0x100000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- ngpios = <18>;
- oxsemi,gpio-bank = <1>;
- gpio-ranges = <&pinctrl 0 32 18>;
- };
-
- uart0: serial@200000 {
- compatible = "ns16550a";
- reg = <0x200000 0x100000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <0>;
- fifo-size = <16>;
- reg-io-width = <1>;
- current-speed = <115200>;
- no-loopback-test;
- status = "disabled";
- clocks = <&sysclk>;
- resets = <&reset RESET_UART1>;
- };
-
- uart1: serial@300000 {
- compatible = "ns16550a";
- reg = <0x200000 0x100000>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <0>;
- fifo-size = <16>;
- reg-io-width = <1>;
- current-speed = <115200>;
- no-loopback-test;
- status = "disabled";
- clocks = <&sysclk>;
- resets = <&reset RESET_UART2>;
- };
-
- rps@400000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0x400000 0x100000>;
-
- intc: interrupt-controller@0 {
- compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
- interrupt-controller;
- reg = <0 0x200>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- valid-mask = <0xffffffff>;
- clear-mask = <0xffffffff>;
- };
-
- timer0: timer@200 {
- compatible = "oxsemi,ox820-rps-timer";
- reg = <0x200 0x40>;
- clocks = <&sysclk>;
- interrupt-parent = <&intc>;
- interrupts = <4>;
- };
- };
-
- sys: sys-ctrl@e00000 {
- compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
- reg = <0xe00000 0x200000>;
-
- reset: reset-controller {
- compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
- #reset-cells = <1>;
- };
-
- stdclk: stdclk {
- compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
- #clock-cells = <1>;
- };
- };
- };
-
- apb-bridge@47000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0x47000000 0x1000000>;
-
- scu: scu@0 {
- compatible = "arm,arm11mp-scu";
- reg = <0x0 0x100>;
- };
-
- local-timer@600 {
- compatible = "arm,arm11mp-twd-timer";
- reg = <0x600 0x20>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&armclk>;
- };
-
- gic: gic@1000 {
- compatible = "arm,arm11mp-gic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0x1000 0x1000>,
- <0x100 0x500>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 4fe7735c7c58..16212b912b94 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -53,6 +53,8 @@
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
+ clocks = <&soc_clocks PXA168_CLK_TIMER>;
+ resets = <&soc_clocks PXA168_CLK_TIMER>;
};
uart1: serial@d4017000 {
diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi
index a248bf038033..5f8300e356ad 100644
--- a/arch/arm/boot/dts/pxa25x.dtsi
+++ b/arch/arm/boot/dts/pxa25x.dtsi
@@ -38,9 +38,12 @@
compatible = "marvell,pdma-1.0";
reg = <0x40000000 0x10000>;
interrupts = <25>;
- #dma-channels = <16>;
#dma-cells = <2>;
+ /* For backwards compatibility: */
+ #dma-channels = <16>;
+ dma-channels = <16>;
#dma-requests = <40>;
+ dma-requests = <40>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index ccbecad9c5c7..a2cbfb3be609 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -12,9 +12,12 @@
compatible = "marvell,pdma-1.0";
reg = <0x40000000 0x10000>;
interrupts = <25>;
- #dma-channels = <32>;
#dma-cells = <2>;
+ /* For backwards compatibility: */
+ #dma-channels = <32>;
+ dma-channels = <32>;
#dma-requests = <75>;
+ dma-requests = <75>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi
index 8a6721d436bd..147c99191dc2 100644
--- a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi
+++ b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi
@@ -189,31 +189,31 @@
regulators {
regulator-v3 {
- regulator-compatible= "V3(DCDC)";
+ regulator-compatible = "V3(DCDC)";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1800000>;
};
regulator-v4 {
- regulator-compatible= "V4(DCDC)";
+ regulator-compatible = "V4(DCDC)";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1800000>;
};
regulator-v5 {
- regulator-compatible= "V5(LDO)";
+ regulator-compatible = "V5(LDO)";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2000000>;
};
reg_vcc_sdio: regulator-v6 {
- regulator-compatible= "V6(LDO)";
+ regulator-compatible = "V6(LDO)";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator-v7 {
- regulator-compatible= "V7(LDO)";
+ regulator-compatible = "V7(LDO)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index d19674812cd2..f9c216f91865 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -122,9 +122,12 @@
compatible = "marvell,pdma-1.0";
reg = <0x40000000 0x10000>;
interrupts = <25>;
- #dma-channels = <32>;
#dma-cells = <2>;
+ /* For backwards compatibility: */
+ #dma-channels = <32>;
+ dma-channels = <32>;
#dma-requests = <100>;
+ dma-requests = <100>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts
new file mode 100644
index 000000000000..7a80e1c9f126
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Luca Weiss <luca@z3ntu.xyz>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "qcom-pm8226.dtsi"
+
+/delete-node/ &adsp_region;
+
+/ {
+ model = "ASUS ZenWatch 2";
+ compatible = "asus,sparrow", "qcom,apq8026";
+ chassis-type = "watch";
+ qcom,msm-id = <199 0x20000>;
+ qcom,board-id = <8 3005>;
+
+ reserved-memory {
+ sbl_region: sbl@2f00000 {
+ reg = <0x02f00000 0x100000>;
+ no-map;
+ };
+ external_image_region: external-image@3100000 {
+ reg = <0x3100000 0x200000>;
+ no-map;
+ };
+ peripheral_region: peripheral@3300000 {
+ reg = <0x3300000 0x600000>;
+ no-map;
+ };
+ adsp_region: adsp@3900000 {
+ reg = <0x3900000 0x1400000>;
+ no-map;
+ };
+ modem_region: modem@4d00000 {
+ reg = <0x4d00000 0x1b00000>;
+ no-map;
+ };
+ modem_efs_region: modem-efs@7f00000 {
+ reg = <0x7f00000 0x100000>;
+ no-map;
+ };
+ };
+
+ vreg_wlan: wlan-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_regulator_default_state>;
+ };
+};
+
+&adsp {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_uart1_default_state>;
+
+ bluetooth {
+ compatible = "brcm,bcm43430a1-bt";
+ max-speed = <3000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bluetooth_default_state>;
+
+ host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&pm8226_vib {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <1900000>;
+ };
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+};
+
+&sdhc_3 {
+ status = "okay";
+
+ max-frequency = <100000000>;
+ non-removable;
+
+ vmmc-supply = <&vreg_wlan>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wifi@1 {
+ compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "host-wake";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_hostwake_default_state>;
+ };
+};
+
+&smbb {
+ qcom,fast-charge-safe-current = <1500000>;
+ qcom,fast-charge-current-limit = <350000>;
+ qcom,fast-charge-safe-voltage = <4430000>;
+ qcom,fast-charge-high-threshold-voltage = <4400000>;
+ qcom,auto-recharge-threshold-voltage = <4300000>;
+ qcom,minimum-input-voltage = <4400000>;
+};
+
+&tlmm {
+ blsp1_uart1_default_state: blsp1-uart1-default-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "blsp_uart1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ bluetooth_default_state: bluetooth-default-state {
+ pins = "gpio48", "gpio61";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ input-enable;
+ };
+
+ wlan_hostwake_default_state: wlan-hostwake-default-state {
+ pins = "gpio46";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ wlan_regulator_default_state: wlan-regulator-default-state {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&usb {
+ status = "okay";
+ extcon = <&smbb>;
+ dr_mode = "peripheral";
+};
+
+&usb_hs_phy {
+ extcon = <&smbb>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
diff --git a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts
new file mode 100644
index 000000000000..d64096028ab1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Luca Weiss <luca@z3ntu.xyz>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "qcom-pm8226.dtsi"
+
+/delete-node/ &adsp_region;
+
+/ {
+ model = "Huawei Watch";
+ compatible = "huawei,sturgeon", "qcom,apq8026";
+ chassis-type = "watch";
+ qcom,msm-id = <199 0x20000>;
+ qcom,board-id = <8 4>;
+
+ reserved-memory {
+ sbl_region: sbl@2f00000 {
+ reg = <0x02f00000 0x100000>;
+ no-map;
+ };
+
+ external_image_region: external-image@3100000 {
+ reg = <0x3100000 0x200000>;
+ no-map;
+ };
+
+ peripheral_region: peripheral@3300000 {
+ reg = <0x3300000 0x600000>;
+ no-map;
+ };
+
+ adsp_region: adsp@3900000 {
+ reg = <0x3900000 0x1400000>;
+ no-map;
+ };
+
+ modem_region: modem@4d00000 {
+ reg = <0x4d00000 0x1b00000>;
+ no-map;
+ };
+
+ modem_efs_region: modem-efs@7f00000 {
+ reg = <0x7f00000 0x100000>;
+ no-map;
+ };
+ };
+
+ vreg_wlan: wlan-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_regulator_default_state>;
+ };
+};
+
+&adsp {
+ status = "okay";
+};
+
+&blsp1_i2c5 {
+ clock-frequency = <384000>;
+
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l19>;
+ vio-supply = <&pm8226_lvs1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_default_state>;
+
+ syna,startup-delay-ms = <160>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_uart4_default_state>;
+
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43430a0-bt";
+ max-speed = <3000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bluetooth_default_state>;
+
+ host-wakeup-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&sdhc_3 {
+ max-frequency = <100000000>;
+ non-removable;
+
+ vmmc-supply = <&vreg_wlan>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm43430a0-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "host-wake";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_hostwake_default_state>;
+ };
+};
+
+&smbb {
+ qcom,fast-charge-safe-voltage = <4370000>;
+ qcom,fast-charge-high-threshold-voltage = <4350000>;
+ qcom,minimum-input-voltage = <4350000>;
+ qcom,fast-charge-current-limit = <300000>;
+ qcom,fast-charge-safe-current = <600000>;
+ qcom,auto-recharge-threshold-voltage = <4240000>;
+};
+
+&tlmm {
+ blsp1_uart4_default_state: blsp1-uart4-default-state {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "blsp_uart4";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ bluetooth_default_state: bluetooth-default-state {
+ pins = "gpio63", "gpio64";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ touch_default_state: touch-default-state {
+ irq-pins {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ reset-pins {
+ pins = "gpio16";
+ function = "gpio";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ wlan_hostwake_default_state: wlan-hostwake-default-state {
+ pins = "gpio66";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ wlan_regulator_default_state: wlan-regulator-default-state {
+ pins = "gpio110";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&usb {
+ extcon = <&smbb>;
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&smbb>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
diff --git a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
index 2b7e52fda6a7..b82381229adf 100644
--- a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
+++ b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
@@ -8,9 +8,12 @@
#include "qcom-msm8226.dtsi"
#include "qcom-pm8226.dtsi"
+/delete-node/ &adsp_region;
+
/ {
model = "LG G Watch R";
compatible = "lg,lenok", "qcom,apq8026";
+ chassis-type = "watch";
qcom,board-id = <132 0x0a>;
qcom,msm-id = <199 0x20000>;
@@ -23,6 +26,23 @@
stdout-path = "serial0:115200n8";
};
+ reserved-memory {
+ sbl_region: sbl@2f00000 {
+ reg = <0x02f00000 0x100000>;
+ no-map;
+ };
+
+ external_image_region: external-image@3100000 {
+ reg = <0x03100000 0x200000>;
+ no-map;
+ };
+
+ adsp_region: adsp@3300000 {
+ reg = <0x03300000 0x1400000>;
+ no-map;
+ };
+ };
+
vreg_wlan: wlan-regulator {
compatible = "regulator-fixed";
@@ -38,6 +58,10 @@
};
};
+&adsp {
+ status = "okay";
+};
+
&blsp1_i2c1 {
status = "okay";
@@ -102,7 +126,7 @@
};
&rpm_requests {
- pm8226-regulators {
+ regulators {
compatible = "qcom,rpm-pm8226-regulators";
pm8226_s3: s3 {
@@ -286,8 +310,8 @@
input-enable;
};
- touch_pins: touch {
- irq {
+ touch_pins: touch-state {
+ irq-pins {
pins = "gpio17";
function = "gpio";
@@ -296,7 +320,7 @@
input-enable;
};
- reset {
+ reset-pins {
pins = "gpio16";
function = "gpio";
diff --git a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts
new file mode 100644
index 000000000000..91b860e24681
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "qcom-msm8226.dtsi"
+#include "qcom-pm8226.dtsi"
+
+/delete-node/ &adsp_region;
+/delete-node/ &smem_region;
+
+/ {
+ model = "Samsung Galaxy Tab 4 10.1";
+ compatible = "samsung,matisse-wifi", "qcom,apq8026";
+ chassis-type = "tablet";
+
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ display0 = &framebuffer0;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ stdout-path = "display0";
+
+ framebuffer0: framebuffer@3200000 {
+ compatible = "simple-framebuffer";
+ reg = <0x03200000 0x800000>;
+ width = <1280>;
+ height = <800>;
+ stride = <(1280 * 3)>;
+ format = "r8g8b8";
+ };
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+ interrupts = <&tlmm 110 IRQ_TYPE_EDGE_FALLING>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <15>;
+ wakeup-source;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ key-home {
+ label = "Home";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ i2c-backlight {
+ compatible = "i2c-gpio";
+ sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-0 = <&backlight_i2c_default_state>;
+ pinctrl-names = "default";
+
+ i2c-gpio,delay-us = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ backlight@2c {
+ compatible = "ti,lp8556";
+ reg = <0x2c>;
+
+ dev-ctrl = /bits/ 8 <0x80>;
+ init-brt = /bits/ 8 <0x3f>;
+ pwm-period = <100000>;
+
+ pwms = <&backlight_pwm 0 100000>;
+ pwm-names = "lp8556";
+
+ rom-a0h {
+ rom-addr = /bits/ 8 <0xa0>;
+ rom-val = /bits/ 8 <0x44>;
+ };
+
+ rom-a1h {
+ rom-addr = /bits/ 8 <0xa1>;
+ rom-val = /bits/ 8 <0x6c>;
+ };
+
+ rom-a5h {
+ rom-addr = /bits/ 8 <0xa5>;
+ rom-val = /bits/ 8 <0x24>;
+ };
+ };
+ };
+
+ backlight_pwm: pwm {
+ compatible = "clk-pwm";
+ #pwm-cells = <2>;
+ clocks = <&mmcc CAMSS_GP0_CLK>;
+ pinctrl-0 = <&backlight_pwm_default_state>;
+ pinctrl-names = "default";
+ };
+
+ reg_tsp_1p8v: regulator-tsp-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_1p8v";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_en_default_state>;
+ };
+
+ reg_tsp_3p3v: regulator-tsp-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_3p3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_en1_default_state>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@3200000 {
+ reg = <0x03200000 0x800000>;
+ no-map;
+ };
+
+ mpss@8400000 {
+ reg = <0x08400000 0x1f00000>;
+ no-map;
+ };
+
+ mba@a300000 {
+ reg = <0x0a300000 0x100000>;
+ no-map;
+ };
+
+ reserved@cb00000 {
+ reg = <0x0cb00000 0x700000>;
+ no-map;
+ };
+
+ wcnss@d200000 {
+ reg = <0x0d200000 0x700000>;
+ no-map;
+ };
+
+ adsp_region: adsp@d900000 {
+ reg = <0x0d900000 0x1800000>;
+ no-map;
+ };
+
+ venus@f100000 {
+ reg = <0x0f100000 0x500000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+
+ reserved@fb00000 {
+ reg = <0x0fb00000 0x260000>;
+ no-map;
+ };
+
+ rfsa@fd60000 {
+ reg = <0x0fd60000 0x20000>;
+ no-map;
+ };
+
+ rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0fd80000 0x180000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ };
+ };
+};
+
+&adsp {
+ status = "okay";
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ accelerometer@1d {
+ compatible = "st,lis2hh12";
+ reg = <0x1d>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_int_default_state>;
+
+ st,drdy-int-pin = <1>;
+
+ vdd-supply = <&pm8226_l19>;
+ vddio-supply = <&pm8226_lvs1>;
+ };
+};
+
+&blsp1_i2c4 {
+ status = "okay";
+
+ muic: usb-switch@25 {
+ compatible = "siliconmitus,sm5502-muic";
+ reg = <0x25>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&muic_int_default_state>;
+ };
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_int_rst_default_state>;
+
+ reset-gpios = <&pm8226_gpios 6 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&reg_tsp_1p8v>;
+ vdda-supply = <&reg_tsp_3p3v>;
+ };
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ regulator-always-on;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&tlmm {
+ accel_int_default_state: accel-int-default-state {
+ pins = "gpio54";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ backlight_i2c_default_state: backlight-i2c-default-state {
+ pins = "gpio20", "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ backlight_pwm_default_state: backlight-pwm-default-state {
+ pins = "gpio33";
+ function = "gp0_clk";
+ };
+
+ muic_int_default_state: muic-int-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_en_default_state: tsp-en-default-state {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_en1_default_state: tsp-en1-default-state {
+ pins = "gpio73";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_int_rst_default_state: tsp-int-rst-default-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&muic>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 138d6478ac84..8e4b61e4d4b1 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
#include "qcom-msm8660.dtsi"
@@ -80,858 +81,897 @@
pinctrl-names = "default";
pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>;
};
+};
- soc {
- pinctrl@800000 {
- /* eMMC pins, all 8 data lines connected */
- dragon_sdcc1_pins: sdcc1 {
- mux {
- pins = "gpio159", "gpio160", "gpio161",
- "gpio162", "gpio163", "gpio164",
- "gpio165", "gpio166", "gpio167",
- "gpio168";
- function = "sdc1";
- };
- clk {
- pins = "gpio167"; /* SDC1 CLK */
- drive-strength = <16>;
- bias-disable;
- };
- cmd {
- pins = "gpio168"; /* SDC1 CMD */
- drive-strength = <10>;
- bias-pull-up;
- };
- data {
- /* SDC1 D0 to D7 */
- pins = "gpio159", "gpio160", "gpio161", "gpio162",
- "gpio163", "gpio164", "gpio165", "gpio166";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
+&ebi2 {
+ /* The EBI2 will instantiate first, then populate its children */
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ebi2_pins>;
+ status = "okay";
- /*
- * The SDCC3 pins are hardcoded (non-muxable) but need some pin
- * configuration.
- */
- dragon_sdcc3_pins: sdcc3 {
- clk {
- pins = "sdc3_clk";
- drive-strength = <8>;
- bias-disable;
- };
- cmd {
- pins = "sdc3_cmd";
- drive-strength = <8>;
- bias-pull-up;
- };
- data {
- pins = "sdc3_data";
- drive-strength = <8>;
- bias-pull-up;
- };
- };
+ /*
+ * An on-board SMSC LAN9221 chip for "debug ethernet",
+ * which is actually just an ordinary ethernet on the
+ * EBI2. This has a 25MHz chrystal next to it, so no
+ * clocking is needed.
+ */
+ ethernet@2,0 {
+ compatible = "smsc,lan9221", "smsc,lan9115";
+ reg = <2 0x0 0x100>;
+ /*
+ * The second interrupt is the PME interrupt
+ * for network wakeup, connected to the TLMM.
+ */
+ interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
+ <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ vdd33a-supply = <&dragon_veth>;
+ vddvario-supply = <&dragon_vario>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ethernet_gpios>;
+ phy-mode = "mii";
+ reg-io-width = <2>;
+ smsc,force-external-phy;
+ smsc,irq-push-pull;
+
+ /*
+ * SLOW chipselect config
+ * Delay 9 cycles (140ns@64MHz) between SMSC
+ * LAN9221 Ethernet controller reads and writes
+ * on CS2.
+ */
+ qcom,xmem-recovery-cycles = <0>;
+ qcom,xmem-write-hold-cycles = <3>;
+ qcom,xmem-write-delta-cycles = <31>;
+ qcom,xmem-read-delta-cycles = <28>;
+ qcom,xmem-write-wait-cycles = <9>;
+ qcom,xmem-read-wait-cycles = <9>;
+ };
+};
- /* Second SD card slot pins */
- dragon_sdcc5_pins: sdcc5 {
- mux {
- pins = "gpio95", "gpio96", "gpio97",
- "gpio98", "gpio99", "gpio100";
- function = "sdc5";
- };
- clk {
- pins = "gpio97"; /* SDC5 CLK */
- drive-strength = <16>;
- bias-disable;
- };
- cmd {
- pins = "gpio95"; /* SDC5 CMD */
- drive-strength = <10>;
- bias-pull-up;
- };
- data {
- /* SDC5 D0 to D3 */
- pins = "gpio96", "gpio98", "gpio99", "gpio100";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
+&gsbi3 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
- dragon_gsbi8_i2c_pins: gsbi8_i2c {
- mux {
- pins = "gpio64", "gpio65";
- function = "gsbi8";
- };
- pinconf {
- pins = "gpio64", "gpio65";
- drive-strength = <16>;
- /* These have external pull-up 2.2kOhm to 1.8V */
- bias-disable;
- };
- };
+&gsbi3_i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_gsbi3_i2c_pins>;
+ status = "okay";
+
+ touchscreen@24 {
+ compatible = "cypress,cy8ctma340";
+ reg = <0x24>;
+ /* Certainly we can do at least 400 kHz */
+ clock-frequency = <400000>;
+ /* IRQ on GPIO61 called /CTP_INT */
+ interrupt-parent = <&tlmm>;
+ interrupts = <61 IRQ_TYPE_EDGE_FALLING>;
+ /*
+ * The I2C bus is using a PCA9306 level translator from L16A
+ * to L2B so these two voltages are needed and L16A is
+ * kind of the IO voltage, however L16Aisn't really fed to
+ * the TMA340, which relies entirely on L2B (PM8901 L2).
+ */
+ vcpin-supply = <&pm8058_l16>;
+ vdd-supply = <&pm8901_l2>;
+ /* GPIO58, called WAKE_CTP */
+ reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ active-interval-ms = <0>;
+ touch-timeout-ms = <255>;
+ lowpower-interval-ms = <10>;
+ bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_tma340_gpios>;
+ };
+};
- dragon_gsbi12_i2c_pins: gsbi12_i2c {
- mux {
- pins = "gpio115", "gpio116";
- function = "gsbi12";
- };
- pinconf {
- pins = "gpio115", "gpio116";
- drive-strength = <16>;
- /* These have external pull-up 4.7kOhm to 1.8V */
- bias-disable;
- };
- };
+&gsbi8 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
- /* Primary serial port uart 0 pins */
- dragon_gsbi12_serial_pins: gsbi12_serial {
- mux {
- pins = "gpio117", "gpio118";
- function = "gsbi12";
- };
- tx {
- pins = "gpio117";
- drive-strength = <8>;
- bias-disable;
- };
- rx {
- pins = "gpio118";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
+&gsbi8_i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_gsbi8_i2c_pins>;
+ status = "okay";
+
+ eeprom@52 {
+ /* A 16KiB Platform ID EEPROM on the CPU carrier board */
+ compatible = "atmel,24c128";
+ reg = <0x52>;
+ vcc-supply = <&pm8058_s3>;
+ pagesize = <64>;
+ };
+ wm8903: wm8903@1a {
+ /* This Woolfson Micro device has an unrouted interrupt line */
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+
+ AVDD-supply = <&pm8058_l16>;
+ CPVDD-supply = <&pm8058_l16>;
+ DBVDD-supply = <&pm8058_s3>;
+ DCVDD-supply = <&pm8058_l0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+ };
+};
- dragon_ebi2_pins: ebi2 {
- /*
- * Pins used by EBI2 on the Dragonboard, actually only
- * CS2 is used by a real peripheral. CS0 is just
- * routed to a test point.
- */
- mux0 {
- pins =
- /* "gpio39", CS1A_N this is not good to mux */
- "gpio40", /* CS2A_N */
- "gpio134"; /* CS0_N testpoint TP29 */
- function = "ebi2cs";
- };
- mux1 {
- pins =
- /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
- "gpio123", "gpio124", "gpio125", "gpio126",
- "gpio127", "gpio128", "gpio129", "gpio130",
- /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
- "gpio135", "gpio136", "gpio137", "gpio138",
- "gpio139", "gpio140", "gpio141", "gpio142",
- "gpio143", "gpio144", "gpio145", "gpio146",
- "gpio147", "gpio148", "gpio149", "gpio150",
- "gpio151", /* EBI2_OE_N */
- "gpio153", /* EBI2_ADV */
- "gpio157"; /* EBI2_WE_N */
- function = "ebi2";
- };
- };
+&gsbi12 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
+
+&gsbi12_serial {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_gsbi12_serial_pins>;
+ status = "okay";
+};
+
+&gsbi12_i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_gsbi12_i2c_pins>;
+ status = "okay";
+
+ ak8975@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+ interrupt-parent = <&pm8058_gpio>;
+ interrupts = <33 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ak8975_gpios>;
+ vid-supply = <&pm8058_lvs0>; // 1.8V
+ vdd-supply = <&pm8058_l14>; // 2.85V
+ };
+ bmp085@77 {
+ compatible = "bosch,bmp085";
+ reg = <0x77>;
+ interrupt-parent = <&pm8058_gpio>;
+ interrupts = <16 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_bmp085_gpios>;
+ vddd-supply = <&pm8058_lvs0>; // 1.8V
+ vdda-supply = <&pm8058_l14>; // 2.85V
+ };
+ mpu3050@68 {
+ compatible = "invensense,mpu3050";
+ reg = <0x68>;
+ /*
+ * GPIO17 is pulled high by a 10k
+ * resistor to VLOGIC so needs to be
+ * active low/falling edge.
+ */
+ interrupts-extended = <&pm8058_gpio 17 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_mpu3050_gpios>;
+ vlogic-supply = <&pm8058_lvs0>; // 1.8V
+ vdd-supply = <&pm8058_l14>; // 2.85V
- /* Interrupt line for the KXSD9 accelerometer */
- dragon_kxsd9_gpios: kxsd9 {
- irq {
- pins = "gpio57"; /* IRQ line */
- bias-pull-up;
- };
+ /*
+ * The MPU-3050 acts as a hub for the
+ * accelerometer.
+ */
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ kxsd9@18 {
+ compatible = "kionix,kxsd9";
+ reg = <0x18>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_kxsd9_gpios>;
+ iovdd-supply = <&pm8058_lvs0>; // 1.8V
+ vdd-supply = <&pm8058_l14>; // 2.85V
};
};
+ };
+};
- qcom,ssbi@500000 {
- pmic@0 {
- keypad@148 {
- linux,keymap = <
- MATRIX_KEY(0, 0, KEY_MENU)
- MATRIX_KEY(0, 2, KEY_1)
- MATRIX_KEY(0, 3, KEY_4)
- MATRIX_KEY(0, 4, KEY_7)
- MATRIX_KEY(1, 0, KEY_UP)
- MATRIX_KEY(1, 1, KEY_LEFT)
- MATRIX_KEY(1, 2, KEY_DOWN)
- MATRIX_KEY(1, 3, KEY_5)
- MATRIX_KEY(1, 3, KEY_8)
- MATRIX_KEY(2, 0, KEY_HOME)
- MATRIX_KEY(2, 1, KEY_REPLY)
- MATRIX_KEY(2, 2, KEY_2)
- MATRIX_KEY(2, 3, KEY_6)
- MATRIX_KEY(3, 0, KEY_VOLUMEUP)
- MATRIX_KEY(3, 1, KEY_RIGHT)
- MATRIX_KEY(3, 2, KEY_3)
- MATRIX_KEY(3, 3, KEY_9)
- MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE)
- MATRIX_KEY(4, 0, KEY_VOLUMEDOWN)
- MATRIX_KEY(4, 1, KEY_BACK)
- MATRIX_KEY(4, 2, KEY_CAMERA)
- MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE)
- >;
- keypad,num-rows = <6>;
- keypad,num-columns = <5>;
- };
-
- gpio@150 {
- dragon_ethernet_gpios: ethernet-gpios {
- pinconf {
- pins = "gpio7";
- function = "normal";
- input-enable;
- bias-disable;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- dragon_bmp085_gpios: bmp085-gpios {
- pinconf {
- pins = "gpio16";
- function = "normal";
- input-enable;
- bias-disable;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- dragon_mpu3050_gpios: mpu3050-gpios {
- pinconf {
- pins = "gpio17";
- function = "normal";
- input-enable;
- bias-disable;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- dragon_sdcc3_gpios: sdcc3-gpios {
- pinconf {
- pins = "gpio22";
- function = "normal";
- input-enable;
- bias-disable;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- dragon_sdcc5_gpios: sdcc5-gpios {
- pinconf {
- pins = "gpio26";
- function = "normal";
- input-enable;
- bias-pull-up;
- qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- dragon_ak8975_gpios: ak8975-gpios {
- pinconf {
- pins = "gpio33";
- function = "normal";
- input-enable;
- bias-disable;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- dragon_cm3605_gpios: cm3605-gpios {
- /* Pin 34 connected to the proxy IRQ */
- pinconf_gpio34 {
- pins = "gpio34";
- function = "normal";
- input-enable;
- bias-disable;
- power-source = <PM8058_GPIO_S3>;
- };
- /* Pin 35 connected to ASET */
- pinconf_gpio35 {
- pins = "gpio35";
- function = "normal";
- output-high;
- bias-disable;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- dragon_veth_gpios: veth-gpios {
- pinconf {
- pins = "gpio40";
- function = "normal";
- bias-disable;
- drive-push-pull;
- };
- };
- };
-
- mpps@50 {
- dragon_cm3605_mpps: cm3605-mpps-state {
- mpp5 {
- pins = "mpp5";
- function = "analog";
- input-enable;
- bias-high-impedance;
- /* Let's use channel 5 */
- qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH5>;
- power-source = <PM8058_GPIO_S3>;
- };
- };
- };
-
- xoadc@197 {
- /* Reference voltage 2.2 V */
- xoadc-ref-supply = <&pm8058_l18>;
-
- /* Board-specific channels */
- mpp5@5 {
- /* Connected to AOUT of ALS sensor */
- reg = <0x00 0x05>;
- };
- mpp6@6 {
- /* Connected to test point TP43 */
- reg = <0x00 0x06>;
- };
- mpp7@7 {
- /* Connected to battery thermistor */
- reg = <0x00 0x07>;
- };
- mpp8@8 {
- /* Connected to battery ID detector */
- reg = <0x00 0x08>;
- };
- mpp9@9 {
- /* Connected to XO thermistor */
- reg = <0x00 0x09>;
- };
- };
-
- led@48 {
- /*
- * The keypad LED @0x48 is routed to
- * the sensor board where it is
- * connected to an infrared LED
- * SFH4650 (60mW, @850nm) next to the
- * ambient light and proximity sensor
- * Capella Microsystems CM3605.
- */
- compatible = "qcom,pm8058-keypad-led";
- reg = <0x48>;
- label = "pm8058:infrared:proximitysensor";
- default-state = "off";
- linux,default-trigger = "cm3605";
- };
- led@131 {
- compatible = "qcom,pm8058-led";
- reg = <0x131>;
- label = "pm8058:red";
- default-state = "off";
- };
- led@132 {
- /*
- * This is actually green too on my
- * board, but documented as yellow.
- */
- compatible = "qcom,pm8058-led";
- reg = <0x132>;
- label = "pm8058:yellow";
- default-state = "off";
- linux,default-trigger = "mmc0";
- };
- led@133 {
- compatible = "qcom,pm8058-led";
- reg = <0x133>;
- label = "pm8058:green";
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
- };
+&pm8058_gpio {
+ dragon_ethernet_gpios: ethernet-state {
+ pinconf {
+ pins = "gpio7";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ dragon_bmp085_gpios: bmp085-state {
+ pinconf {
+ pins = "gpio16";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ dragon_mpu3050_gpios: mpu3050-state {
+ pinconf {
+ pins = "gpio17";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ dragon_sdcc3_gpios: sdcc3-state {
+ pinconf {
+ pins = "gpio22";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ dragon_sdcc5_gpios: sdcc5-state {
+ pinconf {
+ pins = "gpio26";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ dragon_ak8975_gpios: ak8975-state {
+ pinconf {
+ pins = "gpio33";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ dragon_cm3605_gpios: cm3605-state {
+ /* Pin 34 connected to the proxy IRQ */
+ gpio34-pins {
+ pins = "gpio34";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ /* Pin 35 connected to ASET */
+ gpio35-pins {
+ pins = "gpio35";
+ function = "normal";
+ output-high;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
+ dragon_veth_gpios: veth-state {
+ pinconf {
+ pins = "gpio40";
+ function = "normal";
+ bias-disable;
+ drive-push-pull;
};
+ };
+};
- gsbi@19800000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
+&pm8058_keypad {
+ linux,keymap = <
+ MATRIX_KEY(0, 0, KEY_MENU)
+ MATRIX_KEY(0, 2, KEY_1)
+ MATRIX_KEY(0, 3, KEY_4)
+ MATRIX_KEY(0, 4, KEY_7)
+ MATRIX_KEY(1, 0, KEY_UP)
+ MATRIX_KEY(1, 1, KEY_LEFT)
+ MATRIX_KEY(1, 2, KEY_DOWN)
+ MATRIX_KEY(1, 3, KEY_5)
+ MATRIX_KEY(1, 3, KEY_8)
+ MATRIX_KEY(2, 0, KEY_HOME)
+ MATRIX_KEY(2, 1, KEY_REPLY)
+ MATRIX_KEY(2, 2, KEY_2)
+ MATRIX_KEY(2, 3, KEY_6)
+ MATRIX_KEY(3, 0, KEY_VOLUMEUP)
+ MATRIX_KEY(3, 1, KEY_RIGHT)
+ MATRIX_KEY(3, 2, KEY_3)
+ MATRIX_KEY(3, 3, KEY_9)
+ MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE)
+ MATRIX_KEY(4, 0, KEY_VOLUMEDOWN)
+ MATRIX_KEY(4, 1, KEY_BACK)
+ MATRIX_KEY(4, 2, KEY_CAMERA)
+ MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE)
+ >;
+ keypad,num-rows = <6>;
+ keypad,num-columns = <5>;
+};
- i2c@19880000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_gsbi8_i2c_pins>;
-
- eeprom@52 {
- /* A 16KiB Platform ID EEPROM on the CPU carrier board */
- compatible = "atmel,24c128";
- reg = <0x52>;
- vcc-supply = <&pm8058_s3>;
- pagesize = <64>;
- };
- wm8903: wm8903@1a {
- /* This Woolfson Micro device has an unrouted interrupt line */
- compatible = "wlf,wm8903";
- reg = <0x1a>;
-
- AVDD-supply = <&pm8058_l16>;
- CPVDD-supply = <&pm8058_l16>;
- DBVDD-supply = <&pm8058_s3>;
- DCVDD-supply = <&pm8058_l0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- micdet-cfg = <0>;
- micdet-delay = <100>;
- gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
- };
- };
+&pm8058_led48 {
+ /*
+ * The keypad LED @0x48 is routed to
+ * the sensor board where it is
+ * connected to an infrared LED
+ * SFH4650 (60mW, @850nm) next to the
+ * ambient light and proximity sensor
+ * Capella Microsystems CM3605.
+ */
+ label = "pm8058:infrared:proximitysensor";
+ default-state = "off";
+ linux,default-trigger = "cm3605";
+ status = "okay";
+};
+
+&pm8058_led131 {
+ label = "pm8058:red";
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ status = "okay";
+};
+
+&pm8058_led132 {
+ /*
+ * This is actually green too on my
+ * board, but documented as yellow.
+ */
+ label = "pm8058:yellow";
+ color = <LED_COLOR_ID_YELLOW>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ status = "okay";
+};
+
+&pm8058_led133 {
+ label = "pm8058:green";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ status = "okay";
+};
+
+&pm8058_mpps {
+ dragon_cm3605_mpps: cm3605-mpps-state {
+ pins = "mpp5";
+ function = "analog";
+ input-enable;
+ bias-high-impedance;
+ /* Let's use channel 5 */
+ qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH5>;
+ power-source = <PM8058_GPIO_S3>;
+ };
+};
+
+&rpm {
+ /*
+ * Set up of the PMIC RPM regulators for this board
+ * PM8901 supplies "preliminary regulators" whatever
+ * that means
+ */
+ pm8901-regulators {
+ vdd_l0-supply = <&pm8901_s4>;
+ vdd_l1-supply = <&vph>;
+ vdd_l2-supply = <&vph>;
+ vdd_l3-supply = <&vph>;
+ vdd_l4-supply = <&vph>;
+ vdd_l5-supply = <&vph>;
+ vdd_l6-supply = <&vph>;
+ /* vdd_s0-supply, vdd_s1-supply: SAW regulators */
+ vdd_s2-supply = <&vph>;
+ vdd_s3-supply = <&vph>;
+ vdd_s4-supply = <&vph>;
+ lvs0_in-supply = <&pm8058_s3>;
+ lvs1_in-supply = <&pm8901_s4>;
+ lvs2_in-supply = <&pm8058_l0>;
+ lvs3_in-supply = <&pm8058_s2>;
+ mvs_in-supply = <&pm8058_s3>;
+
+ l0 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+ l1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ bias-pull-down;
+ };
+ l2 {
+ /* TMA340 requires strictly 3.3V */
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ bias-pull-down;
+ };
+ l3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ bias-pull-down;
+ };
+ l4 {
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2600000>;
+ bias-pull-down;
+ };
+ l5 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+ l6 {
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ bias-pull-down;
};
- gsbi@19c00000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
+ /* s0 and s1 are SAW regulators controlled over SPM */
+ s2 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+ s3 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+ s4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
- serial@19c40000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_gsbi12_serial_pins>;
- };
+ /* LVS0 thru 3 and mvs are just switches */
+ lvs0 {
+ regulator-always-on;
+ };
+ lvs1 { };
+ lvs2 { };
+ lvs3 { };
+ mvs { };
- i2c@19c80000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_gsbi12_i2c_pins>;
-
- ak8975@c {
- compatible = "asahi-kasei,ak8975";
- reg = <0x0c>;
- interrupt-parent = <&pm8058_gpio>;
- interrupts = <33 IRQ_TYPE_EDGE_RISING>;
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_ak8975_gpios>;
- vid-supply = <&pm8058_lvs0>; // 1.8V
- vdd-supply = <&pm8058_l14>; // 2.85V
- };
- bmp085@77 {
- compatible = "bosch,bmp085";
- reg = <0x77>;
- interrupt-parent = <&pm8058_gpio>;
- interrupts = <16 IRQ_TYPE_EDGE_RISING>;
- reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_bmp085_gpios>;
- vddd-supply = <&pm8058_lvs0>; // 1.8V
- vdda-supply = <&pm8058_l14>; // 2.85V
- };
- mpu3050@68 {
- compatible = "invensense,mpu3050";
- reg = <0x68>;
- /*
- * GPIO17 is pulled high by a 10k
- * resistor to VLOGIC so needs to be
- * active low/falling edge.
- */
- interrupts-extended = <&pm8058_gpio 17 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_mpu3050_gpios>;
- vlogic-supply = <&pm8058_lvs0>; // 1.8V
- vdd-supply = <&pm8058_l14>; // 2.85V
-
- /*
- * The MPU-3050 acts as a hub for the
- * accelerometer.
- */
- i2c-gate {
- #address-cells = <1>;
- #size-cells = <0>;
-
- kxsd9@18 {
- compatible = "kionix,kxsd9";
- reg = <0x18>;
- interrupt-parent = <&tlmm>;
- interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_kxsd9_gpios>;
- iovdd-supply = <&pm8058_lvs0>; // 1.8V
- vdd-supply = <&pm8058_l14>; // 2.85V
- };
- };
- };
- };
+ };
+
+ pm8058-regulators {
+ vdd_l0_l1_lvs-supply = <&pm8058_s3>;
+ vdd_l2_l11_l12-supply = <&vph>;
+ vdd_l3_l4_l5-supply = <&vph>;
+ vdd_l6_l7-supply = <&vph>;
+ vdd_l8-supply = <&vph>;
+ vdd_l9-supply = <&vph>;
+ vdd_l10-supply = <&vph>;
+ vdd_l13_l16-supply = <&pm8058_s4>;
+ vdd_l14_l15-supply = <&vph>;
+ vdd_l17_l18-supply = <&vph>;
+ vdd_l19_l20-supply = <&vph>;
+ vdd_l21-supply = <&pm8058_s3>;
+ vdd_l22-supply = <&pm8058_s3>;
+ vdd_l23_l24_l25-supply = <&pm8058_s3>;
+ vdd_s0-supply = <&vph>;
+ vdd_s1-supply = <&vph>;
+ vdd_s2-supply = <&vph>;
+ vdd_s3-supply = <&vph>;
+ vdd_s4-supply = <&vph>;
+ vdd_ncp-supply = <&vph>;
+
+ l0 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+ l1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+ l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2600000>;
+ bias-pull-down;
+ };
+ l3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+ l4 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+ l5 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+ l6 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ bias-pull-down;
+ };
+ l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+ l8 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3050000>;
+ bias-pull-down;
+ };
+ l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+ l10 {
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2600000>;
+ bias-pull-down;
+ };
+ l11 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ bias-pull-down;
+ };
+ l12 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ bias-pull-down;
+ };
+ l13 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ bias-pull-down;
+ };
+ l14 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+ l15 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+ l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ regulator-always-on;
+ };
+ l17 {
+ // 1.5V according to schematic
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2600000>;
+ bias-pull-down;
+ };
+ l18 {
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ bias-pull-down;
+ };
+ l19 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ bias-pull-down;
+ };
+ l20 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+ l21 {
+ // 1.1 V according to schematic
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ regulator-always-on;
+ };
+ l22 {
+ // 1.2 V according to schematic
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ bias-pull-down;
+ };
+ l23 {
+ // Unused
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+ l24 {
+ // Unused
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+ l25 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
};
- external-bus@1a100000 {
- /* The EBI2 will instantiate first, then populate its children */
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_ebi2_pins>;
-
- /*
- * An on-board SMSC LAN9221 chip for "debug ethernet",
- * which is actually just an ordinary ethernet on the
- * EBI2. This has a 25MHz chrystal next to it, so no
- * clocking is needed.
- */
- ethernet@2,0 {
- compatible = "smsc,lan9221", "smsc,lan9115";
- reg = <2 0x0 0x100>;
- /*
- * The second interrupt is the PME interrupt
- * for network wakeup, connected to the TLMM.
- */
- interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
- <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
- reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
- vdd33a-supply = <&dragon_veth>;
- vddvario-supply = <&dragon_vario>;
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_ethernet_gpios>;
- phy-mode = "mii";
- reg-io-width = <2>;
- smsc,force-external-phy;
- smsc,irq-push-pull;
-
- /*
- * SLOW chipselect config
- * Delay 9 cycles (140ns@64MHz) between SMSC
- * LAN9221 Ethernet controller reads and writes
- * on CS2.
- */
- qcom,xmem-recovery-cycles = <0>;
- qcom,xmem-write-hold-cycles = <3>;
- qcom,xmem-write-delta-cycles = <31>;
- qcom,xmem-read-delta-cycles = <28>;
- qcom,xmem-write-wait-cycles = <9>;
- qcom,xmem-read-wait-cycles = <9>;
- };
+ s0 {
+ // regulator-min-microvolt = <500000>;
+ // regulator-max-microvolt = <1325000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+ s1 {
+ // regulator-min-microvolt = <500000>;
+ // regulator-max-microvolt = <1250000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+ s2 {
+ // 1.3 V according to schematic
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+ s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ regulator-always-on;
+ bias-pull-down;
+ };
+ s4 {
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ qcom,switch-mode-frequency = <1600000>;
+ regulator-always-on;
+ bias-pull-down;
};
- rpm@104000 {
- /*
- * Set up of the PMIC RPM regulators for this board
- * PM8901 supplies "preliminary regulators" whatever
- * that means
- */
- pm8901-regulators {
- vdd_l0-supply = <&pm8901_s4>;
- vdd_l1-supply = <&vph>;
- vdd_l2-supply = <&vph>;
- vdd_l3-supply = <&vph>;
- vdd_l4-supply = <&vph>;
- vdd_l5-supply = <&vph>;
- vdd_l6-supply = <&vph>;
- /* vdd_s0-supply, vdd_s1-supply: SAW regulators */
- vdd_s2-supply = <&vph>;
- vdd_s3-supply = <&vph>;
- vdd_s4-supply = <&vph>;
- lvs0_in-supply = <&pm8058_s3>;
- lvs1_in-supply = <&pm8901_s4>;
- lvs2_in-supply = <&pm8058_l0>;
- lvs3_in-supply = <&pm8058_s2>;
- mvs_in-supply = <&pm8058_s3>;
-
- l0 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
- l1 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- bias-pull-down;
- };
- l2 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <3300000>;
- bias-pull-down;
- };
- l3 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- bias-pull-down;
- };
- l4 {
- regulator-min-microvolt = <2600000>;
- regulator-max-microvolt = <2600000>;
- bias-pull-down;
- };
- l5 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
- l6 {
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- bias-pull-down;
- };
-
- /* s0 and s1 are SAW regulators controlled over SPM */
- s2 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
- s3 {
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
- s4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- /* LVS0 thru 3 and mvs are just switches */
- lvs0 {
- regulator-always-on;
- };
- lvs1 { };
- lvs2 { };
- lvs3 { };
- mvs { };
+ /* LVS0 and LVS1 are just switches */
+ lvs0 {
+ bias-pull-down;
+ };
+ lvs1 {
+ bias-pull-down;
+ };
- };
+ ncp {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ };
+ };
+};
- pm8058-regulators {
- vdd_l0_l1_lvs-supply = <&pm8058_s3>;
- vdd_l2_l11_l12-supply = <&vph>;
- vdd_l3_l4_l5-supply = <&vph>;
- vdd_l6_l7-supply = <&vph>;
- vdd_l8-supply = <&vph>;
- vdd_l9-supply = <&vph>;
- vdd_l10-supply = <&vph>;
- vdd_l13_l16-supply = <&pm8058_s4>;
- vdd_l14_l15-supply = <&vph>;
- vdd_l17_l18-supply = <&vph>;
- vdd_l19_l20-supply = <&vph>;
- vdd_l21-supply = <&pm8058_s3>;
- vdd_l22-supply = <&pm8058_s3>;
- vdd_l23_l24_l25-supply = <&pm8058_s3>;
- vdd_s0-supply = <&vph>;
- vdd_s1-supply = <&vph>;
- vdd_s2-supply = <&vph>;
- vdd_s3-supply = <&vph>;
- vdd_s4-supply = <&vph>;
- vdd_ncp-supply = <&vph>;
-
- l0 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
- l1 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
- l2 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2600000>;
- bias-pull-down;
- };
- l3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
- l4 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
- l5 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
- l6 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3600000>;
- bias-pull-down;
- };
- l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
- l8 {
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <3050000>;
- bias-pull-down;
- };
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
- l10 {
- regulator-min-microvolt = <2600000>;
- regulator-max-microvolt = <2600000>;
- bias-pull-down;
- };
- l11 {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- bias-pull-down;
- };
- l12 {
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- bias-pull-down;
- };
- l13 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- bias-pull-down;
- };
- l14 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
- l15 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
- l16 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- regulator-always-on;
- };
- l17 {
- // 1.5V according to schematic
- regulator-min-microvolt = <2600000>;
- regulator-max-microvolt = <2600000>;
- bias-pull-down;
- };
- l18 {
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- bias-pull-down;
- };
- l19 {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- bias-pull-down;
- };
- l20 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
- l21 {
- // 1.1 V according to schematic
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- regulator-always-on;
- };
- l22 {
- // 1.2 V according to schematic
- regulator-min-microvolt = <1150000>;
- regulator-max-microvolt = <1150000>;
- bias-pull-down;
- };
- l23 {
- // Unused
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
- l24 {
- // Unused
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
- l25 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
-
- s0 {
- // regulator-min-microvolt = <500000>;
- // regulator-max-microvolt = <1325000>;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
- s1 {
- // regulator-min-microvolt = <500000>;
- // regulator-max-microvolt = <1250000>;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
- s2 {
- // 1.3 V according to schematic
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1400000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
- s3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <1600000>;
- regulator-always-on;
- bias-pull-down;
- };
- s4 {
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- qcom,switch-mode-frequency = <1600000>;
- regulator-always-on;
- bias-pull-down;
- };
-
- /* LVS0 and LVS1 are just switches */
- lvs0 {
- bias-pull-down;
- };
- lvs1 {
- bias-pull-down;
- };
-
- ncp {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <1600000>;
- };
- };
+/* Internal 3.69 GiB eMMC */
+&sdcc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_sdcc1_pins>;
+ vmmc-supply = <&pm8901_l5>;
+ vqmmc-supply = <&pm8901_lvs0>;
+ status = "okay";
+};
+
+/* External micro SD card, directly connected, pulled up to 2.85 V */
+&sdcc3 {
+ /* Enable SSBI GPIO 22 as input, use for card detect */
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>;
+ cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&pm8058_l14>;
+ status = "okay";
+};
+
+/*
+ * Second external micro SD card, using two TXB104RGYR levelshifters
+ * to lift from 1.8 V to 2.85 V
+ */
+&sdcc5 {
+ /* Enable SSBI GPIO 26 as input, use for card detect */
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>;
+ cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&pm8058_l14>;
+ vqmmc-supply = <&dragon_vio_txb>;
+ status = "okay";
+};
+
+&tlmm {
+ /* eMMC pins, all 8 data lines connected */
+ dragon_sdcc1_pins: sdcc1-state {
+ clk-pins {
+ pins = "gpio167"; /* SDC1 CLK */
+ function = "sdc1";
+ drive-strength = <16>;
+ bias-disable;
};
- amba {
- /* Internal 3.69 GiB eMMC */
- mmc@12400000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_sdcc1_pins>;
- vmmc-supply = <&pm8901_l5>;
- vqmmc-supply = <&pm8901_lvs0>;
- };
+ cmd-pins {
+ pins = "gpio168"; /* SDC1 CMD */
+ function = "sdc1";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ data-pins {
+ /* SDC1 D0 to D7 */
+ pins = "gpio159", "gpio160", "gpio161", "gpio162",
+ "gpio163", "gpio164", "gpio165", "gpio166";
+ function = "sdc1";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
- /* External micro SD card, directly connected, pulled up to 2.85 V */
- mmc@12180000 {
- status = "okay";
- /* Enable SSBI GPIO 22 as input, use for card detect */
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>;
- cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>;
- wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
- vmmc-supply = <&pm8058_l14>;
- };
+ /*
+ * The SDCC3 pins are hardcoded (non-muxable) but need some pin
+ * configuration.
+ */
+ dragon_sdcc3_pins: sdcc3-state {
+ clk-pins {
+ pins = "sdc3_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ cmd-pins {
+ pins = "sdc3_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ data-pins {
+ pins = "sdc3_data";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
- /*
- * Second external micro SD card, using two TXB104RGYR levelshifters
- * to lift from 1.8 V to 2.85 V
- */
- mmc@12200000 {
- status = "okay";
- /* Enable SSBI GPIO 26 as input, use for card detect */
- pinctrl-names = "default";
- pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>;
- cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>;
- wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>;
- vmmc-supply = <&pm8058_l14>;
- vqmmc-supply = <&dragon_vio_txb>;
- };
+ /* Second SD card slot pins */
+ dragon_sdcc5_pins: sdcc5-state {
+ clk-pins {
+ pins = "gpio97"; /* SDC5 CLK */
+ function = "sdc5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ cmd-pins {
+ pins = "gpio95"; /* SDC5 CMD */
+ function = "sdc5";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ data-pins {
+ /* SDC5 D0 to D3 */
+ pins = "gpio96", "gpio98", "gpio99", "gpio100";
+ function = "sdc5";
+ drive-strength = <10>;
+ bias-pull-up;
};
};
+
+ dragon_gsbi3_i2c_pins: gsbi3-i2c-state {
+ pins = "gpio43", "gpio44";
+ function = "gsbi3";
+ drive-strength = <8>;
+ /* These have external pull-up 2.2kOhm to 1.8V */
+ bias-disable;
+ };
+
+ dragon_gsbi8_i2c_pins: gsbi8-i2c-state {
+ pins = "gpio64", "gpio65";
+ function = "gsbi8";
+ drive-strength = <16>;
+ /* These have external pull-up 2.2kOhm to 1.8V */
+ bias-disable;
+ };
+
+ dragon_gsbi12_i2c_pins: gsbi12-i2c-state {
+ pins = "gpio115", "gpio116";
+ function = "gsbi12";
+ drive-strength = <16>;
+ /* These have external pull-up 4.7kOhm to 1.8V */
+ bias-disable;
+ };
+
+ /* Primary serial port uart 0 pins */
+ dragon_gsbi12_serial_pins: gsbi12-serial-state {
+ tx-pins {
+ pins = "gpio117";
+ function = "gsbi12";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ rx-pins {
+ pins = "gpio118";
+ function = "gsbi12";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ dragon_ebi2_pins: ebi2-state {
+ /*
+ * Pins used by EBI2 on the Dragonboard, actually only
+ * CS2 is used by a real peripheral. CS0 is just
+ * routed to a test point.
+ */
+ mux0-pins {
+ pins =
+ /* "gpio39", CS1A_N this is not good to mux */
+ "gpio40", /* CS2A_N */
+ "gpio134"; /* CS0_N testpoint TP29 */
+ function = "ebi2cs";
+ };
+ mux1-pins {
+ pins =
+ /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
+ "gpio123", "gpio124", "gpio125", "gpio126",
+ "gpio127", "gpio128", "gpio129", "gpio130",
+ /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
+ "gpio135", "gpio136", "gpio137", "gpio138",
+ "gpio139", "gpio140", "gpio141", "gpio142",
+ "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149", "gpio150",
+ "gpio151", /* EBI2_OE_N */
+ "gpio153", /* EBI2_ADV */
+ "gpio157"; /* EBI2_WE_N */
+ function = "ebi2";
+ };
+ };
+
+ /* Interrupt line for the KXSD9 accelerometer */
+ dragon_kxsd9_gpios: kxsd9-state {
+ pins = "gpio57"; /* IRQ line */
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ dragon_tma340_gpios: tma340-state {
+ reset-pins {
+ /* RESET line, TS_ATTN, WAKE_CTP */
+ pins = "gpio58";
+ function = "gpio";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ irq-pins {
+ pins = "gpio61"; /* IRQ line */
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&xoadc {
+ /* Reference voltage 2.2 V */
+ xoadc-ref-supply = <&pm8058_l18>;
+
+ /* Board-specific channels */
+ mpp5@5 {
+ /* Connected to AOUT of ALS sensor */
+ reg = <0x00 0x05>;
+ };
+ mpp6@6 {
+ /* Connected to test point TP43 */
+ reg = <0x00 0x06>;
+ };
+ mpp7@7 {
+ /* Connected to battery thermistor */
+ reg = <0x00 0x07>;
+ };
+ mpp8@8 {
+ /* Connected to battery ID detector */
+ reg = <0x00 0x08>;
+ };
+ mpp9@9 {
+ /* Connected to XO thermistor */
+ reg = <0x00 0x09>;
+ };
};
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index ca9f73528196..c57c27cd8a20 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -6,6 +6,7 @@
/ {
model = "Asus Nexus7(flo)";
compatible = "asus,nexus7-flo", "qcom,apq8064";
+ chassis-type = "tablet";
aliases {
serial0 = &gsbi7_serial;
@@ -21,16 +22,16 @@
#size-cells = <1>;
ranges;
- ramoops@88d00000{
+ ramoops@88d00000 {
compatible = "ramoops";
reg = <0x88d00000 0x100000>;
- record-size = <0x00020000>;
- console-size = <0x00020000>;
- ftrace-size = <0x00020000>;
+ record-size = <0x00020000>;
+ console-size = <0x00020000>;
+ ftrace-size = <0x00020000>;
};
};
- ext_3p3v: regulator-fixed@1 {
+ ext_3p3v: regulator-ext-3p3v {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -44,12 +45,12 @@
gpio-keys {
compatible = "gpio-keys";
- volume_up {
+ key-volume-up {
label = "Volume Up";
gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_VOLUMEUP>;
};
- volume_down {
+ key-volume-down {
label = "Volume Down";
gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_VOLUMEDOWN>;
@@ -57,302 +58,291 @@
};
soc {
- rpm@108000 {
- regulators {
- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
- vin_lvs1_3_6-supply = <&pm8921_s4>;
- vin_lvs4_5_7-supply = <&pm8921_s4>;
-
-
- vdd_l24-supply = <&pm8921_s1>;
- vdd_l25-supply = <&pm8921_s1>;
- vin_lvs2-supply = <&pm8921_s1>;
-
- vdd_l26-supply = <&pm8921_s7>;
- vdd_l27-supply = <&pm8921_s7>;
- vdd_l28-supply = <&pm8921_s7>;
-
- vdd_ncp-supply = <&pm8921_l6>;
-
- /* Buck SMPS */
- s1 {
- regulator-always-on;
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- qcom,switch-mode-frequency = <3200000>;
- bias-pull-down;
- };
-
- /* msm otg HSUSB_VDDCX */
- s3 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1150000>;
- qcom,switch-mode-frequency = <4800000>;
- };
-
- /*
- * msm_sdcc.1-sdc-vdd_io
- * tabla2x-slim-CDC_VDDA_RX
- * tabla2x-slim-CDC_VDDA_TX
- * tabla2x-slim-CDC_VDD_CP
- * tabla2x-slim-VDDIO_CDC
- */
- s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <3200000>;
- regulator-always-on;
- };
-
- s7 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <3200000>;
- };
-
- /* mipi_dsi.1-dsi1_pll_vdda */
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- /* msm_otg-HSUSB_3p3 */
- l3 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
- bias-pull-down;
- };
-
- /* msm_otg-HSUSB_1p8 */
- l4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- /* msm_sdcc.1-sdc_vdd */
- l5 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- regulator-always-on;
- bias-pull-down;
- };
-
- l6 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- };
-
- /* mipi_dsi.1-dsi1_avdd */
- l11 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- regulator-always-on;
- };
-
- /* pwm_power for backlight */
- l17 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- /* camera, qdsp6 */
- l23 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- /*
- * tabla2x-slim-CDC_VDDA_A_1P2V
- * tabla2x-slim-VDDD_CDC_D
- */
- l25 {
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <1250000>;
- bias-pull-down;
- };
-
- lvs1 {
- bias-pull-down;
- };
-
- lvs4 {
- bias-pull-down;
- };
-
- lvs5 {
- bias-pull-down;
- };
-
- lvs6 {
- bias-pull-down;
- };
- /*
- * mipi_dsi.1-dsi1_vddio
- * pil_riva-pll_vdd
- */
- lvs7 {
- bias-pull-down;
- };
- };
- };
+ sram@2a03f000 {
+ compatible = "qcom,apq8064-imem", "syscon", "simple-mfd";
+ reg = <0x2a03f000 0x1000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x65c>;
- mdp@5100000 {
- status = "okay";
- ports {
- port@1 {
- mdp_dsi1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
- };
- };
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
};
};
+ };
+};
- dsi0: dsi@4700000 {
- status = "okay";
- vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/
- vdd-supply = <&pm8921_l8>;
- vddio-supply = <&pm8921_lvs7>;
- avdd-supply = <&pm8921_l11>;
-
- panel@0 {
- reg = <0>;
- compatible = "jdi,lt070me05000";
-
- vddp-supply = <&pm8921_l17>;
- iovcc-supply = <&pm8921_lvs7>;
-
- enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
- dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
- };
- ports {
- port@0 {
- dsi0_in: endpoint {
- remote-endpoint = <&mdp_dsi1_out>;
- };
- };
-
- port@1 {
- dsi0_out: endpoint {
- remote-endpoint = <&panel_in>;
- data-lanes = <0 1 2 3>;
- };
- };
+&dsi0 {
+ vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/
+ vdd-supply = <&pm8921_l8>;
+ vddio-supply = <&pm8921_lvs7>;
+ avdd-supply = <&pm8921_l11>;
+ status = "okay";
+
+ panel@0 {
+ reg = <0>;
+ compatible = "jdi,lt070me05000";
+
+ vddp-supply = <&pm8921_l17>;
+ iovcc-supply = <&pm8921_lvs7>;
+
+ enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
+ dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
};
};
+ };
+};
+
+&dsi0_in {
+ remote-endpoint = <&mdp_dsi1_out>;
+};
+
+&dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&dsi0_phy {
+ vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/
+ status = "okay";
+};
+
+&gsbi1 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
+
+&gsbi1_i2c {
+ status = "okay";
+ clock-frequency = <200000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ eeprom@52 {
+ compatible = "atmel,24c128";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+
+ bq27541@55 {
+ compatible = "ti,bq27541";
+ reg = <0x55>;
+ };
+
+};
+
+&gsbi3 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
+
+&gsbi3_i2c {
+ clock-frequency = <200000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ trackpad@10 {
+ compatible = "elan,ekth3500";
+ reg = <0x10>;
+ interrupt-parent = <&tlmm_pinmux>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&gsbi6 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
+
+&gsbi6_serial {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsbi6_uart_4pins>;
+ status = "okay";
+};
- dsi-phy@4700200 {
- status = "okay";
- vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/
+&gsbi7 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
+
+&gsbi7_serial {
+ status = "okay";
+};
+
+&mdp {
+ status = "okay";
+};
+
+/* eMMC */
+&sdcc1 {
+ vmmc-supply = <&pm8921_l5>;
+ vqmmc-supply = <&pm8921_s4>;
+ status = "okay";
+};
+
+&mdp_dsi1_out {
+ remote-endpoint = <&dsi0_in>;
+};
+
+&rpm {
+ regulators {
+ vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
+ vin_lvs1_3_6-supply = <&pm8921_s4>;
+ vin_lvs4_5_7-supply = <&pm8921_s4>;
+
+
+ vdd_l24-supply = <&pm8921_s1>;
+ vdd_l25-supply = <&pm8921_s1>;
+ vin_lvs2-supply = <&pm8921_s1>;
+
+ vdd_l26-supply = <&pm8921_s7>;
+ vdd_l27-supply = <&pm8921_s7>;
+ vdd_l28-supply = <&pm8921_s7>;
+
+ vdd_ncp-supply = <&pm8921_l6>;
+
+ /* Buck SMPS */
+ s1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ qcom,switch-mode-frequency = <3200000>;
+ bias-pull-down;
};
- gsbi@16200000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
- i2c@16280000 {
- status = "okay";
- clock-frequency = <200000>;
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-names = "default";
-
- trackpad@10 {
- compatible = "elan,ekth3500";
- reg = <0x10>;
- interrupt-parent = <&tlmm_pinmux>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
- };
- };
+ /* msm otg HSUSB_VDDCX */
+ s3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,switch-mode-frequency = <4800000>;
};
+ /*
+ * msm_sdcc.1-sdc-vdd_io
+ * tabla2x-slim-CDC_VDDA_RX
+ * tabla2x-slim-CDC_VDDA_TX
+ * tabla2x-slim-CDC_VDD_CP
+ * tabla2x-slim-VDDIO_CDC
+ */
+ s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <3200000>;
+ regulator-always-on;
+ };
- gsbi@12440000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
+ s7 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <3200000>;
+ };
- i2c@12460000 {
- status = "okay";
- clock-frequency = <200000>;
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
+ /* mipi_dsi.1-dsi1_pll_vdda */
+ l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
- eeprom@52 {
- compatible = "atmel,24c128";
- reg = <0x52>;
- pagesize = <32>;
- };
+ /* msm_otg-HSUSB_3p3 */
+ l3 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ bias-pull-down;
+ };
- bq27541@55 {
- compatible = "ti,bq27541";
- reg = <0x55>;
- };
+ /* msm_otg-HSUSB_1p8 */
+ l4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
- };
+ /* msm_sdcc.1-sdc_vdd */
+ l5 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-always-on;
+ bias-pull-down;
};
- gsbi@16500000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
+ l6 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
- serial@16540000 {
- status = "okay";
+ /* mipi_dsi.1-dsi1_avdd */
+ l11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
+ regulator-always-on;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&gsbi6_uart_4pins>;
- };
+ /* pwm_power for backlight */
+ l17 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
};
- gsbi@16600000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
- serial@16640000 {
- status = "okay";
- };
+ /* camera, qdsp6 */
+ l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
};
- /* OTG */
- usb@12500000 {
- status = "okay";
- dr_mode = "otg";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
- };
+ /*
+ * tabla2x-slim-CDC_VDDA_A_1P2V
+ * tabla2x-slim-VDDD_CDC_D
+ */
+ l25 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ bias-pull-down;
};
- amba {
- /* eMMC */
- mmc@12400000 {
- status = "okay";
- vmmc-supply = <&pm8921_l5>;
- vqmmc-supply = <&pm8921_s4>;
- };
+ lvs1 {
+ bias-pull-down;
};
- imem@2a03f000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x2a03f000 0x1000>;
+ lvs4 {
+ bias-pull-down;
+ };
- reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x65c>;
+ lvs5 {
+ bias-pull-down;
+ };
- mode-normal = <0x77665501>;
- mode-bootloader = <0x77665500>;
- mode-recovery = <0x77665502>;
- };
+ lvs6 {
+ bias-pull-down;
+ };
+ /*
+ * mipi_dsi.1-dsi1_vddio
+ * pil_riva-pll_vdd
+ */
+ lvs7 {
+ bias-pull-down;
};
};
};
+
+&usb_hs1_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+};
+
+/* OTG */
+&usb1 {
+ dr_mode = "otg";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index e068a8d0adf0..d6ecfd8addb7 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -15,232 +15,216 @@
stdout-path = "serial0:115200n8";
};
- pwrseq {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- compatible = "simple-bus";
-
- sdcc4_pwrseq: sdcc4_pwrseq {
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_default_gpios>;
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
- };
+ sdcc4_pwrseq: pwrseq-sdcc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default_gpios>;
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
};
- soc {
- pinctrl@800000 {
- card_detect: card_detect {
- mux {
- pins = "gpio26";
- function = "gpio";
- bias-disable;
- };
- };
-
- pcie_pins: pcie_pinmux {
- mux {
- pins = "gpio27";
- function = "gpio";
- };
- conf {
- pins = "gpio27";
- drive-strength = <12>;
- bias-disable;
- };
- };
- };
+ /* on board fixed 3.3v supply */
+ v3p3_fixed: regulator-v3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE V3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
- rpm@108000 {
- regulators {
- vin_lvs1_3_6-supply = <&pm8921_s4>;
- vin_lvs2-supply = <&pm8921_s1>;
- vin_lvs4_5_7-supply = <&pm8921_s4>;
-
- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
- vdd_l24-supply = <&pm8921_s1>;
- vdd_l25-supply = <&pm8921_s1>;
- vdd_l26-supply = <&pm8921_s7>;
- vdd_l27-supply = <&pm8921_s7>;
- vdd_l28-supply = <&pm8921_s7>;
-
-
- /* Buck SMPS */
- s1 {
- regulator-always-on;
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- qcom,switch-mode-frequency = <3200000>;
- bias-pull-down;
- };
-
- s3 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1400000>;
- qcom,switch-mode-frequency = <4800000>;
- };
-
- s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <3200000>;
- };
-
- s7 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <3200000>;
- };
-
- l3 {
- regulator-min-microvolt = <3050000>;
- regulator-max-microvolt = <3300000>;
- bias-pull-down;
- };
-
- l4 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- l5 {
- regulator-min-microvolt = <2750000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- };
-
- l23 {
- regulator-min-microvolt = <1700000>;
- regulator-max-microvolt = <1900000>;
- bias-pull-down;
- };
-
- pm8921_lvs6: lvs6 {
- bias-pull-down;
- };
-
- };
- };
+&gsbi1 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
- gsbi@12440000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
+&gsbi1_i2c {
+ clock-frequency = <200000>;
+ status = "okay";
- i2c@12460000 {
- status = "okay";
- clock-frequency = <200000>;
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&gsbi7 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <32>;
- };
- };
+&gsbi7_serial {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsbi7_uart_2pins>;
+ status = "okay";
+};
+
+&pcie {
+ vdda-supply = <&pm8921_s3>;
+ vdda_phy-supply = <&pm8921_lvs6>;
+ vdda_refclk-supply = <&v3p3_fixed>;
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+ perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pm8921_gpio {
+ wlan_default_gpios: wlan-gpios-state {
+ pinconf {
+ pins = "gpio43";
+ function = "normal";
+ bias-disable;
+ power-source = <PM8921_GPIO_S4>;
};
+ };
+};
+
+&rpm {
+ regulators {
+ vin_lvs1_3_6-supply = <&pm8921_s4>;
+ vin_lvs2-supply = <&pm8921_s1>;
+ vin_lvs4_5_7-supply = <&pm8921_s4>;
+
+ vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
+ vdd_l24-supply = <&pm8921_s1>;
+ vdd_l25-supply = <&pm8921_s1>;
+ vdd_l26-supply = <&pm8921_s7>;
+ vdd_l27-supply = <&pm8921_s7>;
+ vdd_l28-supply = <&pm8921_s7>;
+
- gsbi@16600000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
- serial@16640000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&gsbi7_uart_2pins>;
- };
+ /* Buck SMPS */
+ s1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ qcom,switch-mode-frequency = <3200000>;
+ bias-pull-down;
};
- /* OTG */
- usb@12500000 {
- status = "okay";
- dr_mode = "otg";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
- };
+ s3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ qcom,switch-mode-frequency = <4800000>;
};
- usb@12520000 {
- status = "okay";
- dr_mode = "host";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
- };
+ s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <3200000>;
};
- usb@12530000 {
- status = "okay";
- dr_mode = "host";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
- };
+ s7 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <3200000>;
};
- /* on board fixed 3.3v supply */
- v3p3_fixed: v3p3 {
- compatible = "regulator-fixed";
- regulator-name = "PCIE V3P3";
- regulator-min-microvolt = <3300000>;
+ l3 {
+ regulator-min-microvolt = <3050000>;
regulator-max-microvolt = <3300000>;
- regulator-always-on;
+ bias-pull-down;
+ };
+
+ l4 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ l5 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
};
- qcom,ssbi@500000 {
- pmic@0 {
- gpio@150 {
- wlan_default_gpios: wlan-gpios {
- pios {
- pins = "gpio43";
- function = "normal";
- bias-disable;
- power-source = <PM8921_GPIO_S4>;
- };
- };
- };
- };
+ l23 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ bias-pull-down;
};
- pci@1b500000 {
- status = "okay";
- vdda-supply = <&pm8921_s3>;
- vdda_phy-supply = <&pm8921_lvs6>;
- vdda_refclk-supply = <&v3p3_fixed>;
- pinctrl-0 = <&pcie_pins>;
- pinctrl-names = "default";
- perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+ lvs6 {
+ bias-pull-down;
};
- amba {
- /* eMMC */
- sdcc1: mmc@12400000 {
- status = "okay";
- vmmc-supply = <&pm8921_l5>;
- vqmmc-supply = <&pm8921_s4>;
- };
-
- /* External micro SD card */
- sdcc3: mmc@12180000 {
- status = "okay";
- vmmc-supply = <&v3p3_fixed>;
- pinctrl-names = "default";
- pinctrl-0 = <&card_detect>;
- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
- };
- /* WLAN */
- sdcc4: mmc@121c0000 {
- status = "okay";
- vmmc-supply = <&v3p3_fixed>;
- vqmmc-supply = <&v3p3_fixed>;
- mmc-pwrseq = <&sdcc4_pwrseq>;
- };
+ };
+};
+
+/* eMMC */
+&sdcc1 {
+ vmmc-supply = <&pm8921_l5>;
+ vqmmc-supply = <&pm8921_s4>;
+ status = "okay";
+};
+
+/* External micro SD card */
+&sdcc3 {
+ vmmc-supply = <&v3p3_fixed>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&card_detect>;
+ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* WLAN */
+&sdcc4 {
+ status = "okay";
+ vmmc-supply = <&v3p3_fixed>;
+ vqmmc-supply = <&v3p3_fixed>;
+ mmc-pwrseq = <&sdcc4_pwrseq>;
+};
+
+&tlmm_pinmux {
+ card_detect: card_detect {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ bias-disable;
+ };
+ };
+
+ pcie_pins: pcie_pinmux {
+ mux {
+ pins = "gpio27";
+ function = "gpio";
+ };
+ conf {
+ pins = "gpio27";
+ drive-strength = <12>;
+ bias-disable;
};
};
};
+
+&usb_hs1_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+};
+
+&usb_hs3_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+};
+
+&usb_hs4_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+};
+
+/* OTG */
+&usb1 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb4 {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 2638b380be20..96307550523a 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-apq8064-v2.0.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
@@ -21,24 +22,14 @@
stdout-path = "serial0:115200n8";
};
- pwrseq {
- compatible = "simple-bus";
-
- sdcc4_pwrseq: sdcc4_pwrseq {
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_default_gpios>;
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
- };
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&notify_led>;
- led@1 {
+ led-user1 {
label = "apq8064:green:user1";
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
@@ -55,327 +46,314 @@
};
};
- soc {
- pinctrl@800000 {
- card_detect: card_detect {
- mux {
- pins = "gpio26";
- function = "gpio";
- bias-disable;
- };
- };
+ sdcc4_pwrseq: pwrseq-sdcc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default_gpios>;
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
+ };
- pcie_pins: pcie_pinmux {
- mux {
- pins = "gpio27";
- function = "gpio";
- };
- conf {
- pins = "gpio27";
- drive-strength = <12>;
- bias-disable;
- };
- };
- };
+ ext_3p3v: regulator-ext-3p3v {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "ext_3p3v";
+ regulator-type = "voltage";
+ startup-delay-us = <0>;
+ gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+};
- rpm@108000 {
- regulators {
- vin_lvs1_3_6-supply = <&pm8921_s4>;
- vin_lvs2-supply = <&pm8921_s1>;
- vin_lvs4_5_7-supply = <&pm8921_s4>;
-
- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
- vdd_l24-supply = <&pm8921_s1>;
- vdd_l25-supply = <&pm8921_s1>;
- vdd_l26-supply = <&pm8921_s7>;
- vdd_l27-supply = <&pm8921_s7>;
- vdd_l28-supply = <&pm8921_s7>;
-
-
- /* Buck SMPS */
- s1 {
- regulator-always-on;
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- qcom,switch-mode-frequency = <3200000>;
- bias-pull-down;
- };
-
- s3 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1400000>;
- qcom,switch-mode-frequency = <4800000>;
- };
-
- s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <3200000>;
- };
-
- s7 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <3200000>;
- };
-
- l3 {
- regulator-min-microvolt = <3050000>;
- regulator-max-microvolt = <3300000>;
- bias-pull-down;
- };
-
- l4 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- l5 {
- regulator-min-microvolt = <2750000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- };
-
- l6 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- l23 {
- regulator-min-microvolt = <1700000>;
- regulator-max-microvolt = <1900000>;
- bias-pull-down;
- };
-
- lvs1 {
- bias-pull-down;
- };
-
- lvs6 {
- bias-pull-down;
- };
- };
- };
+&gsbi1 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
- ext_3p3v: regulator-fixed@1 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "ext_3p3v";
- regulator-type = "voltage";
- startup-delay-us = <0>;
- gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-boot-on;
- };
+&gsbi1_i2c {
+ clock-frequency = <200000>;
+ status = "okay";
- gsbi3: gsbi@16200000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
- i2c@16280000 {
- status = "okay";
- };
- };
+ eeprom@52 {
+ compatible = "atmel,24c128";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
- gsbi@16300000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
- /* CAM I2C MIPI-CSI connector */
- i2c@16380000 {
- status = "okay";
- };
- };
+&gsbi3 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
+
+&gsbi3_i2c {
+ status = "okay";
+};
- gsbi@12440000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C>;
+ status = "okay";
+};
- i2c@12460000 {
- status = "okay";
- clock-frequency = <200000>;
+/* CAM I2C MIPI-CSI connector */
+&gsbi4_i2c {
+ status = "okay";
+};
- eeprom@52 {
- compatible = "atmel,24c128";
- reg = <0x52>;
- pagesize = <32>;
- };
- };
- };
+&gsbi5 {
+ qcom,mode = <GSBI_PROT_SPI>;
+ status = "okay";
+};
- gsbi@1a200000 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
- spi4: spi@1a280000 {
- status = "okay";
- num-cs = <1>;
- cs-gpios = <&tlmm_pinmux 53 0>;
- };
- };
+&gsbi5_spi {
+ num-cs = <1>;
+ cs-gpios = <&tlmm_pinmux 53 0>;
+ status = "okay";
+};
- gsbi@16500000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_UART_W_FC>;
+&gsbi6 {
+ qcom,mode = <GSBI_PROT_UART_W_FC>;
+ status = "okay";
+};
- serial@16540000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&gsbi6_uart_4pins>;
- };
+&gsbi6_serial {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsbi6_uart_4pins>;
+ status = "okay";
+};
+
+&gsbi7 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
+
+&gsbi7_serial {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsbi7_uart_2pins>;
+ status = "okay";
+};
+
+&hdmi {
+ core-vdda-supply = <&pm8921_hdmi_switch>;
+ hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&hdmi_in {
+ remote-endpoint = <&mdp_dtv_out>;
+};
+
+&hdmi_out {
+ remote-endpoint = <&hdmi_con>;
+};
+
+&hdmi_phy {
+ status = "okay";
+ core-vdda-supply = <&pm8921_hdmi_switch>;
+};
+
+&mdp {
+ status = "okay";
+};
+
+&mdp_dtv_out {
+ remote-endpoint = <&hdmi_in>;
+};
+
+&pcie {
+ status = "okay";
+ vdda-supply = <&pm8921_s3>;
+ vdda_phy-supply = <&pm8921_lvs6>;
+ vdda_refclk-supply = <&ext_3p3v>;
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+ perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+};
+
+&pm8921_gpio {
+ wlan_default_gpios: wlan-gpios-state {
+ pinconf {
+ pins = "gpio43";
+ function = "normal";
+ bias-disable;
+ power-source = <PM8921_GPIO_S4>;
};
+ };
- gsbi@16600000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
- serial@16640000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&gsbi7_uart_2pins>;
- };
+ notify_led: nled-state {
+ pinconf {
+ pins = "gpio18";
+ function = "normal";
+ bias-disable;
+ power-source = <PM8921_GPIO_S4>;
};
+ };
+};
- sata_phy0: phy@1b400000 {
- status = "okay";
+&rpm {
+ regulators {
+ vin_lvs1_3_6-supply = <&pm8921_s4>;
+ vin_lvs2-supply = <&pm8921_s1>;
+ vin_lvs4_5_7-supply = <&pm8921_s4>;
+
+ vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
+ vdd_l24-supply = <&pm8921_s1>;
+ vdd_l25-supply = <&pm8921_s1>;
+ vdd_l26-supply = <&pm8921_s7>;
+ vdd_l27-supply = <&pm8921_s7>;
+ vdd_l28-supply = <&pm8921_s7>;
+
+
+ /* Buck SMPS */
+ s1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ qcom,switch-mode-frequency = <3200000>;
+ bias-pull-down;
};
- sata0: sata@29000000 {
- status = "okay";
- target-supply = <&pm8921_s4>;
+ s3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ qcom,switch-mode-frequency = <4800000>;
};
- /* OTG */
- usb@12500000 {
- status = "okay";
- dr_mode = "otg";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
- };
+ s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <3200000>;
};
- usb@12520000 {
- status = "okay";
- dr_mode = "host";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
- };
+ s7 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <3200000>;
};
- usb@12530000 {
- status = "okay";
- dr_mode = "host";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l23>;
- };
- };
+ l3 {
+ regulator-min-microvolt = <3050000>;
+ regulator-max-microvolt = <3300000>;
+ bias-pull-down;
};
- pci@1b500000 {
- status = "okay";
- vdda-supply = <&pm8921_s3>;
- vdda_phy-supply = <&pm8921_lvs6>;
- vdda_refclk-supply = <&ext_3p3v>;
- pinctrl-0 = <&pcie_pins>;
- pinctrl-names = "default";
- perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+ l4 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
};
- qcom,ssbi@500000 {
- pmic@0 {
- gpio@150 {
- wlan_default_gpios: wlan-gpios {
- pios {
- pins = "gpio43";
- function = "normal";
- bias-disable;
- power-source = <PM8921_GPIO_S4>;
- };
- };
-
- notify_led: nled {
- pios {
- pins = "gpio18";
- function = "normal";
- bias-disable;
- power-source = <PM8921_GPIO_S4>;
- };
- };
- };
- };
+ l5 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
};
- amba {
- /* eMMC */
- sdcc1: mmc@12400000 {
- status = "okay";
- vmmc-supply = <&pm8921_l5>;
- vqmmc-supply = <&pm8921_s4>;
- };
+ l6 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
- /* External micro SD card */
- sdcc3: mmc@12180000 {
- status = "okay";
- vmmc-supply = <&pm8921_l6>;
- pinctrl-names = "default";
- pinctrl-0 = <&card_detect>;
- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
- };
- /* WLAN */
- sdcc4: mmc@121c0000 {
- status = "okay";
- vmmc-supply = <&ext_3p3v>;
- vqmmc-supply = <&pm8921_lvs1>;
- mmc-pwrseq = <&sdcc4_pwrseq>;
- };
+ l23 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ bias-pull-down;
+ };
+
+ lvs1 {
+ bias-pull-down;
};
- hdmi-tx@4a00000 {
- status = "okay";
+ lvs6 {
+ bias-pull-down;
+ };
+ };
+};
- core-vdda-supply = <&pm8921_hdmi_switch>;
- hdmi-mux-supply = <&ext_3p3v>;
+&sata_phy0 {
+ status = "okay";
+};
- hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
+&sata0 {
+ target-supply = <&pm8921_s4>;
+ status = "okay";
+};
- ports {
- port@0 {
- endpoint {
- remote-endpoint = <&mdp_dtv_out>;
- };
- };
+/* eMMC */
+&sdcc1 {
+ vmmc-supply = <&pm8921_l5>;
+ vqmmc-supply = <&pm8921_s4>;
+ status = "okay";
+};
- port@1 {
- endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
+/* External micro SD card */
+&sdcc3 {
+ vmmc-supply = <&pm8921_l6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&card_detect>;
+ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
- hdmi-phy@4a00400 {
- status = "okay";
+/* WLAN */
+&sdcc4 {
+ vmmc-supply = <&ext_3p3v>;
+ vqmmc-supply = <&pm8921_lvs1>;
+ mmc-pwrseq = <&sdcc4_pwrseq>;
+ status = "okay";
+};
- core-vdda-supply = <&pm8921_hdmi_switch>;
+&tlmm_pinmux {
+ card_detect: card_detect {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ bias-disable;
};
+ };
- mdp@5100000 {
- status = "okay";
-
- ports {
- port@3 {
- endpoint {
- remote-endpoint = <&hdmi_in>;
- };
- };
- };
+ pcie_pins: pcie_pinmux {
+ mux {
+ pins = "gpio27";
+ function = "gpio";
+ };
+ conf {
+ pins = "gpio27";
+ drive-strength = <12>;
+ bias-disable;
};
};
};
+
+&usb_hs1_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+};
+
+&usb_hs3_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+};
+
+&usb_hs4_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l23>;
+};
+
+/* OTG */
+&usb1 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb4 {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index cbe42c4153a0..b4d286a6fab1 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -76,7 +76,7 @@
pinconf {
pins = "gpio20", "gpio21";
drive-strength = <2>;
- bias-disable = <0>;
+ bias-disable;
};
};
@@ -116,7 +116,7 @@
pinconf {
pins = "gpio24", "gpio25";
drive-strength = <2>;
- bias-disable = <0>;
+ bias-disable;
};
};
@@ -141,7 +141,7 @@
pinconf {
pins = "gpio8", "gpio9";
drive-strength = <2>;
- bias-disable = <0>;
+ bias-disable;
};
};
@@ -166,7 +166,7 @@
pinconf {
pins = "gpio12", "gpio13";
drive-strength = <2>;
- bias-disable = <0>;
+ bias-disable;
};
};
@@ -229,7 +229,7 @@
pinconf {
pins = "gpio16", "gpio17";
drive-strength = <2>;
- bias-disable = <0>;
+ bias-disable;
};
};
@@ -282,7 +282,7 @@
pinconf {
pins = "gpio84", "gpio85";
drive-strength = <2>;
- bias-disable = <0>;
+ bias-disable;
};
};
diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts
new file mode 100644
index 000000000000..9244512b74d1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts
@@ -0,0 +1,389 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-apq8064-v2.0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "Sony Xperia Z";
+ compatible = "sony,xperia-yuga", "qcom,apq8064";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &gsbi5_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ key-camera-focus {
+ label = "camera_focus";
+ gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ };
+
+ key-camera-snapshot {
+ label = "camera_snapshot";
+ gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA>;
+ };
+
+ key-volume-down {
+ label = "volume_down";
+ gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+};
+
+&gsbi5 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
+
+&gsbi5_serial {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsbi5_uart_pin_a>;
+ status = "okay";
+};
+
+&pm8921_gpio {
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio3", "gpio4", "gpio29", "gpio35";
+ function = "normal";
+
+ bias-pull-up;
+ drive-push-pull;
+ input-enable;
+ power-source = <2>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ qcom,pull-up-strength = <0>;
+ };
+};
+
+&riva {
+ pinctrl-names = "default";
+ pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+ status = "okay";
+};
+
+&rpm {
+ regulators {
+ vin_l1_l2_l12_l18-supply = <&pm8921_s4>;
+ vin_lvs_1_3_6-supply = <&pm8921_s4>;
+ vin_lvs_4_5_7-supply = <&pm8921_s4>;
+ vin_ncp-supply = <&pm8921_l6>;
+ vin_lvs2-supply = <&pm8921_s4>;
+ vin_l24-supply = <&pm8921_s1>;
+ vin_l25-supply = <&pm8921_s1>;
+ vin_l27-supply = <&pm8921_s7>;
+ vin_l28-supply = <&pm8921_s7>;
+
+ /* Buck SMPS */
+ s1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ qcom,switch-mode-frequency = <3200000>;
+ bias-pull-down;
+ };
+
+ s2 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ s3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,switch-mode-frequency = <4800000>;
+ bias-pull-down;
+ };
+
+ s4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>;
+ };
+
+ s7 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <3200000>;
+ };
+
+ s8 {
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ qcom,switch-mode-frequency = <1600000>;
+ };
+
+ /* PMOS LDO */
+ l1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ bias-pull-down;
+ };
+
+ l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+
+ l3 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ bias-pull-down;
+ };
+
+ l4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ l5 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ l6 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ l8 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ bias-pull-down;
+ };
+
+ l9 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
+ };
+
+ l10 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ bias-pull-down;
+ };
+
+ l11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
+ };
+
+ l12 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+
+ l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ l16 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ bias-pull-down;
+ };
+
+ l17 {
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ bias-pull-down;
+ };
+
+ l18 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+
+ l21 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ l22 {
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2600000>;
+ bias-pull-down;
+ };
+
+ l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ l24 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1150000>;
+ bias-pull-down;
+ };
+
+ l25 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ bias-pull-down;
+ };
+
+ l27 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ l28 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ l29 {
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ bias-pull-down;
+ };
+
+ /* Low Voltage Switch */
+ lvs1 {
+ bias-pull-down;
+ };
+
+ lvs2 {
+ bias-pull-down;
+ };
+
+ lvs3 {
+ bias-pull-down;
+ };
+
+ lvs4 {
+ bias-pull-down;
+ };
+
+ lvs5 {
+ bias-pull-down;
+ };
+
+ lvs6 {
+ bias-pull-down;
+ };
+
+ lvs7 {
+ bias-pull-down;
+ };
+
+ usb-switch {};
+
+ hdmi-switch {};
+
+ ncp {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ };
+ };
+};
+
+&sdcc1 {
+ vmmc-supply = <&pm8921_l5>;
+ vqmmc-supply = <&pm8921_s4>;
+ status = "okay";
+};
+
+&sdcc3 {
+ vmmc-supply = <&pm8921_l6>;
+ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>;
+
+ status = "okay";
+};
+
+&tlmm_pinmux {
+ gsbi5_uart_pin_a: gsbi5-uart-pin-active {
+ rx {
+ pins = "gpio52";
+ function = "gsbi5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ tx {
+ pins = "gpio51";
+ function = "gsbi5";
+ drive-strength = <4>;
+ bias-disable;
+ };
+ };
+
+
+ sdcc3_cd_pin_a: sdcc3-cd-pin-active {
+ pins = "gpio26";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&usb_hs1_phy {
+ v3p3-supply = <&pm8921_l3>;
+ v1p8-supply = <&pm8921_l4>;
+};
+
+&usb1 {
+ dr_mode = "otg";
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
deleted file mode 100644
index 0cee62c7b8b0..000000000000
--- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
+++ /dev/null
@@ -1,401 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "qcom-apq8064-v2.0.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/mfd/qcom-rpm.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-
-/ {
- model = "Sony Xperia Z";
- compatible = "sony,xperia-yuga", "qcom,apq8064";
-
- aliases {
- serial0 = &gsbi5_serial;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pin_a>;
-
- camera-focus {
- label = "camera_focus";
- gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA_FOCUS>;
- };
-
- camera-snapshot {
- label = "camera_snapshot";
- gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA>;
- };
-
- volume-down {
- label = "volume_down";
- gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEDOWN>;
- };
-
- volume-up {
- label = "volume_up";
- gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEUP>;
- };
- };
-
- soc {
- pinctrl@800000 {
- gsbi5_uart_pin_a: gsbi5-uart-pin-active {
- rx {
- pins = "gpio52";
- function = "gsbi5";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- tx {
- pins = "gpio51";
- function = "gsbi5";
- drive-strength = <4>;
- bias-disable;
- };
- };
-
-
- sdcc3_cd_pin_a: sdcc3-cd-pin-active {
- pins = "gpio26";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
-
- rpm@108000 {
- regulators {
- vin_l1_l2_l12_l18-supply = <&pm8921_s4>;
- vin_lvs_1_3_6-supply = <&pm8921_s4>;
- vin_lvs_4_5_7-supply = <&pm8921_s4>;
- vin_ncp-supply = <&pm8921_l6>;
- vin_lvs2-supply = <&pm8921_s4>;
- vin_l24-supply = <&pm8921_s1>;
- vin_l25-supply = <&pm8921_s1>;
- vin_l27-supply = <&pm8921_s7>;
- vin_l28-supply = <&pm8921_s7>;
-
- /* Buck SMPS */
- s1 {
- regulator-always-on;
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- qcom,switch-mode-frequency = <3200000>;
- bias-pull-down;
- };
-
- s2 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- s3 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1150000>;
- qcom,switch-mode-frequency = <4800000>;
- bias-pull-down;
- };
-
- s4 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>;
- };
-
- s7 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <3200000>;
- };
-
- s8 {
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
- qcom,switch-mode-frequency = <1600000>;
- };
-
- /* PMOS LDO */
- l1 {
- regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- bias-pull-down;
- };
-
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
-
- l3 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
- bias-pull-down;
- };
-
- l4 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- l5 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- l6 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- l7 {
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- l8 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- bias-pull-down;
- };
-
- l9 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- };
-
- l10 {
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- bias-pull-down;
- };
-
- l11 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- };
-
- l12 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
-
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- l15 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- l16 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- bias-pull-down;
- };
-
- l17 {
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- bias-pull-down;
- };
-
- l18 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
-
- l21 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- bias-pull-down;
- };
-
- l22 {
- regulator-min-microvolt = <2600000>;
- regulator-max-microvolt = <2600000>;
- bias-pull-down;
- };
-
- l23 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- l24 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1150000>;
- bias-pull-down;
- };
-
- l25 {
- regulator-always-on;
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <1250000>;
- bias-pull-down;
- };
-
- l27 {
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- l28 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- bias-pull-down;
- };
-
- l29 {
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- bias-pull-down;
- };
-
- /* Low Voltage Switch */
- lvs1 {
- bias-pull-down;
- };
-
- lvs2 {
- bias-pull-down;
- };
-
- lvs3 {
- bias-pull-down;
- };
-
- lvs4 {
- bias-pull-down;
- };
-
- lvs5 {
- bias-pull-down;
- };
-
- lvs6 {
- bias-pull-down;
- };
-
- lvs7 {
- bias-pull-down;
- };
-
- usb-switch {};
-
- hdmi-switch {};
-
- ncp {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <1600000>;
- };
- };
- };
-
- qcom,ssbi@500000 {
- pmic@0 {
- gpio@150 {
- gpio_keys_pin_a: gpio-keys-pin-active {
- pins = "gpio3", "gpio4", "gpio29", "gpio35";
- function = "normal";
-
- bias-pull-up;
- drive-push-pull;
- input-enable;
- power-source = <2>;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- qcom,pull-up-strength = <0>;
- };
- };
- };
- };
-
- usb@12500000 {
- status = "okay";
- dr_mode = "otg";
- ulpi {
- phy {
- v3p3-supply = <&pm8921_l3>;
- v1p8-supply = <&pm8921_l4>;
- };
- };
- };
-
- gsbi@1a200000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-
- serial@1a240000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gsbi5_uart_pin_a>;
- };
- };
-
- amba {
- sdcc1: mmc@12400000 {
- status = "okay";
-
- vmmc-supply = <&pm8921_l5>;
- vqmmc-supply = <&pm8921_s4>;
- };
-
- sdcc3: mmc@12180000 {
- status = "okay";
-
- vmmc-supply = <&pm8921_l6>;
- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>;
- };
- };
-
- riva-pil@3204000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index a1c8ae516d21..672b246afbba 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -2,6 +2,7 @@
/dts-v1/;
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
@@ -105,7 +106,7 @@
polling-delay-passive = <250>;
polling-delay = <1000>;
- thermal-sensors = <&gcc 7>;
+ thermal-sensors = <&tsens 7>;
coefficients = <1199 0>;
trips {
@@ -126,7 +127,7 @@
polling-delay-passive = <250>;
polling-delay = <1000>;
- thermal-sensors = <&gcc 8>;
+ thermal-sensors = <&tsens 8>;
coefficients = <1132 0>;
trips {
@@ -147,7 +148,7 @@
polling-delay-passive = <250>;
polling-delay = <1000>;
- thermal-sensors = <&gcc 9>;
+ thermal-sensors = <&tsens 9>;
coefficients = <1199 0>;
trips {
@@ -168,7 +169,7 @@
polling-delay-passive = <250>;
polling-delay = <1000>;
- thermal-sensors = <&gcc 10>;
+ thermal-sensors = <&tsens 10>;
coefficients = <1132 0>;
trips {
@@ -227,7 +228,7 @@
smd {
compatible = "qcom,smd";
- modem@0 {
+ modem-edge {
interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&l2cc 8 3>;
@@ -236,7 +237,7 @@
status = "disabled";
};
- q6@1 {
+ q6-edge {
interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&l2cc 8 15>;
@@ -245,7 +246,7 @@
status = "disabled";
};
- dsps@3 {
+ dsps-edge {
interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
@@ -254,7 +255,7 @@
status = "disabled";
};
- riva@6 {
+ riva-edge {
interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&l2cc 8 25>;
@@ -315,7 +316,7 @@
firmware {
scm {
- compatible = "qcom,scm-apq8064";
+ compatible = "qcom,scm-apq8064", "qcom,scm";
clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
clock-names = "core";
@@ -374,35 +375,50 @@
};
timer@200a000 {
- compatible = "qcom,kpss-timer",
- "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
+ compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
+ "qcom,msm-timer";
interrupts = <1 1 0x301>,
<1 2 0x301>,
<1 3 0x301>;
reg = <0x0200a000 0x100>;
- clock-frequency = <27000000>,
- <32768>;
+ clock-frequency = <27000000>;
cpu-offset = <0x80000>;
};
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
+ #clock-cells = <0>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu1_aux";
+ #clock-cells = <0>;
};
acc2: clock-controller@20a8000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu2_aux";
+ #clock-cells = <0>;
};
acc3: clock-controller@20b8000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu3_aux";
+ #clock-cells = <0>;
};
saw0: power-controller@2089000 {
@@ -430,8 +446,8 @@
};
sps_sic_non_secure: sps-sic-non-secure@12100000 {
- compatible = "syscon";
- reg = <0x12100000 0x10000>;
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
};
gsbi1: gsbi@12440000 {
@@ -671,7 +687,7 @@
reg = <0x00c00000 0x1000>;
qcom,controller-type = "pmic-arbiter";
- pm8821: pmic@1 {
+ pm8821: pmic {
compatible = "qcom,pm8821";
interrupt-parent = <&tlmm_pinmux>;
interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
@@ -692,12 +708,12 @@
};
};
- qcom,ssbi@500000 {
+ ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x00500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
- pmicintc: pmic@0 {
+ pmicintc: pmic {
compatible = "qcom,pm8921";
interrupt-parent = <&tlmm_pinmux>;
interrupts = <74 8>;
@@ -796,28 +812,41 @@
};
qfprom: qfprom@700000 {
- compatible = "qcom,qfprom";
- reg = <0x00700000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
+ compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
+ reg = <0x00700000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
ranges;
- tsens_calib: calib {
+ tsens_calib: calib@404 {
reg = <0x404 0x10>;
};
- tsens_backup: backup_calib {
+ tsens_backup: backup_calib@414 {
reg = <0x414 0x10>;
};
};
gcc: clock-controller@900000 {
- compatible = "qcom,gcc-apq8064";
+ compatible = "qcom,gcc-apq8064", "syscon";
reg = <0x00900000 0x4000>;
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
- #thermal-sensor-cells = <1>;
+ clocks = <&cxo_board>,
+ <&pxo_board>,
+ <&lcc PLL4>;
+ clock-names = "cxo", "pxo", "pll4";
+
+ tsens: thermal-sensor {
+ compatible = "qcom,msm8960-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
};
lcc: clock-controller@28000000 {
@@ -825,6 +854,20 @@
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ clocks = <&pxo_board>,
+ <&gcc PLL4_VOTE>,
+ <0>,
+ <0>, <0>,
+ <0>, <0>,
+ <0>;
+ clock-names = "pxo",
+ "pll4_vote",
+ "mi2s_codec_clk",
+ "codec_i2s_mic_codec_clk",
+ "spare_i2s_mic_codec_clk",
+ "codec_i2s_spkr_codec_clk",
+ "spare_i2s_spkr_codec_clk",
+ "pcm_codec_clk";
};
mmcc: clock-controller@4000000 {
@@ -833,26 +876,47 @@
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
+ clocks = <&pxo_board>,
+ <&gcc PLL3>,
+ <&gcc PLL8_VOTE>,
+ <&dsi0_phy 1>,
+ <&dsi0_phy 0>,
+ <&dsi1_phy 1>,
+ <&dsi1_phy 0>,
+ <&hdmi_phy>;
+ clock-names = "pxo",
+ "pll3",
+ "pll8_vote",
+ "dsi1pll",
+ "dsi1pllbyte",
+ "dsi2pll",
+ "dsi2pllbyte",
+ "hdmipll";
};
l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x2011000 0x1000>;
+ compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
};
- rpm@108000 {
- compatible = "qcom,rpm-apq8064";
- reg = <0x108000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-apq8064";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
rpmcc: clock-controller {
- compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
+ compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
#clock-cells = <1>;
+ clocks = <&pxo_board>, <&cxo_board>;
+ clock-names = "pxo", "cxo";
};
regulators {
@@ -1004,53 +1068,59 @@
};
sata_phy0: phy@1b400000 {
- compatible = "qcom,apq8064-sata-phy";
- status = "disabled";
- reg = <0x1b400000 0x200>;
- reg-names = "phy_mem";
- clocks = <&gcc SATA_PHY_CFG_CLK>;
- clock-names = "cfg";
- #phy-cells = <0>;
+ compatible = "qcom,apq8064-sata-phy";
+ status = "disabled";
+ reg = <0x1b400000 0x200>;
+ reg-names = "phy_mem";
+ clocks = <&gcc SATA_PHY_CFG_CLK>;
+ clock-names = "cfg";
+ #phy-cells = <0>;
};
sata0: sata@29000000 {
- compatible = "qcom,apq8064-ahci", "generic-ahci";
- status = "disabled";
- reg = <0x29000000 0x180>;
- interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&gcc SFAB_SATA_S_H_CLK>,
- <&gcc SATA_H_CLK>,
- <&gcc SATA_A_CLK>,
- <&gcc SATA_RXOOB_CLK>,
- <&gcc SATA_PMALIVE_CLK>;
- clock-names = "slave_iface",
- "iface",
- "bus",
- "rxoob",
- "core_pmalive";
-
- assigned-clocks = <&gcc SATA_RXOOB_CLK>,
- <&gcc SATA_PMALIVE_CLK>;
- assigned-clock-rates = <100000000>, <100000000>;
-
- phys = <&sata_phy0>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- };
-
- /* Temporary fixed regulator */
- sdcc1bam:dma@12402000{
- compatible = "qcom,bam-v1.3.0";
- reg = <0x12402000 0x8000>;
- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc SDC1_H_CLK>;
- clock-names = "bam_clk";
- #dma-cells = <1>;
- qcom,ee = <0>;
- };
-
- sdcc3bam:dma@12182000{
+ compatible = "qcom,apq8064-ahci", "generic-ahci";
+ status = "disabled";
+ reg = <0x29000000 0x180>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc SFAB_SATA_S_H_CLK>,
+ <&gcc SATA_H_CLK>,
+ <&gcc SATA_A_CLK>,
+ <&gcc SATA_RXOOB_CLK>,
+ <&gcc SATA_PMALIVE_CLK>;
+ clock-names = "slave_iface",
+ "iface",
+ "bus",
+ "rxoob",
+ "core_pmalive";
+
+ assigned-clocks = <&gcc SATA_RXOOB_CLK>,
+ <&gcc SATA_PMALIVE_CLK>;
+ assigned-clock-rates = <100000000>, <100000000>;
+
+ phys = <&sata_phy0>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ };
+
+ sdcc3: mmc@12180000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <192000000>;
+ no-1-8-v;
+ dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+ dma-names = "tx", "rx";
+ };
+
+ sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
@@ -1060,7 +1130,25 @@
qcom,ee = <0>;
};
- sdcc4bam:dma@121c2000{
+ sdcc4: mmc@121c0000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x121c0000 0x2000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <48000000>;
+ dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdc4_gpios>;
+ };
+
+ sdcc4bam: dma-controller@121c2000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x121c2000 0x8000>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -1070,67 +1158,33 @@
qcom,ee = <0>;
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
- pinctrl-names = "default";
- pinctrl-0 = <&sdcc1_pins>;
- arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x2000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <96000000>;
- non-removable;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
- dma-names = "tx", "rx";
- };
-
- sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x2000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <192000000>;
- no-1-8-v;
- dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
- dma-names = "tx", "rx";
- };
-
- sdcc4: mmc@121c0000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x121c0000 0x2000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <48000000>;
- dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- pinctrl-0 = <&sdc4_gpios>;
- };
+ sdcc1: mmc@12400000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcc1_pins>;
+ arm,primecell-periphid = <0x00051180>;
+ reg = <0x12400000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
+ non-removable;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+ dma-names = "tx", "rx";
+ };
+
+ sdcc1bam: dma-controller@12402000 {
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12402000 0x8000>;
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
};
tcsr: syscon@1a400000 {
@@ -1225,7 +1279,7 @@
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-320000000 {
+ opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
};
@@ -1241,7 +1295,8 @@
};
dsi0: dsi@4700000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ compatible = "qcom,apq8064-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
label = "MDSS DSI CTRL->0";
#address-cells = <1>;
#size-cells = <0>;
@@ -1270,7 +1325,8 @@
<&dsi0_phy 1>;
syscon-sfpb = <&mmss_sfpb>;
phys = <&dsi0_phy>;
- phy-names = "dsi";
+ status = "disabled";
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1290,7 +1346,7 @@
};
- dsi0_phy: dsi-phy@4700200 {
+ dsi0_phy: phy@4700200 {
compatible = "qcom,dsi-phy-28nm-8960";
#clock-cells = <1>;
#phy-cells = <0>;
@@ -1299,11 +1355,86 @@
<0x04700300 0x200>,
<0x04700500 0x5c>;
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
- clock-names = "iface_clk", "ref";
+ clock-names = "iface", "ref";
clocks = <&mmcc DSI_M_AHB_CLK>,
<&pxo_board>;
+ status = "disabled";
};
+ dsi1: dsi@5800000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x05800000 0x200>;
+ reg-names = "dsi_ctrl";
+
+ clocks = <&mmcc DSI2_M_AHB_CLK>,
+ <&mmcc DSI2_S_AHB_CLK>,
+ <&mmcc AMP_AHB_CLK>,
+ <&mmcc DSI2_CLK>,
+ <&mmcc DSI2_BYTE_CLK>,
+ <&mmcc DSI2_PIXEL_CLK>,
+ <&mmcc DSI2_ESC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core_mmss",
+ "src",
+ "byte",
+ "pixel",
+ "core";
+
+ assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
+ <&mmcc DSI2_ESC_SRC>,
+ <&mmcc DSI2_SRC>,
+ <&mmcc DSI2_PIXEL_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>,
+ <&dsi1_phy 0>,
+ <&dsi1_phy 1>,
+ <&dsi1_phy 1>;
+
+ syscon-sfpb = <&mmss_sfpb>;
+ phys = <&dsi1_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+
+ dsi1_phy: dsi-phy@5800200 {
+ compatible = "qcom,dsi-phy-28nm-8960";
+ reg = <0x05800200 0x100>,
+ <0x05800300 0x200>,
+ <0x05800500 0x5c>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+ clock-names = "iface",
+ "ref";
+ clocks = <&mmcc DSI2_M_AHB_CLK>,
+ <&pxo_board>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
mdp_port0: iommu@7500000 {
compatible = "qcom,apq8064-iommu";
@@ -1370,7 +1501,7 @@
};
pcie: pci@1b500000 {
- compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
+ compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
<0x1b600000 0x100>,
@@ -1382,8 +1513,8 @@
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */
- <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
+ ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
+ <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@@ -1420,7 +1551,8 @@
"slave_iface";
phys = <&hdmi_phy>;
- phy-names = "hdmi-phy";
+
+ status = "disabled";
ports {
#address-cells = <1>;
@@ -1440,7 +1572,7 @@
};
};
- hdmi_phy: hdmi-phy@4a00400 {
+ hdmi_phy: phy@4a00400 {
compatible = "qcom,hdmi-phy-8960";
reg = <0x4a00400 0x60>,
<0x4a00500 0x100>;
@@ -1450,9 +1582,12 @@
clocks = <&mmcc HDMI_S_AHB_CLK>;
clock-names = "slave_iface";
#phy-cells = <0>;
+ #clock-cells = <0>;
+
+ status = "disabled";
};
- mdp: mdp@5100000 {
+ mdp: display-controller@5100000 {
compatible = "qcom,mdp4";
reg = <0x05100000 0xf0000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -1504,7 +1639,7 @@
};
};
- riva: riva-pil@3204000 {
+ riva: riva-pil@3200800 {
compatible = "qcom,riva-pil";
reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
@@ -1548,7 +1683,7 @@
qcom,mmio = <&riva>;
- bt {
+ bluetooth {
compatible = "qcom,wcnss-bt";
};
@@ -1567,7 +1702,7 @@
};
etb@1a01000 {
- compatible = "coresight-etb10", "arm,primecell";
+ compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x1a01000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 83793b835d40..1345df7cbd00 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/gpio/gpio.h>
#include "qcom-msm8974.dtsi"
#include "qcom-pm8841.dtsi"
#include "qcom-pm8941.dtsi"
@@ -16,331 +17,291 @@
chosen {
stdout-path = "serial0:115200n8";
};
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&blsp2_i2c5 {
+ status = "okay";
+ clock-frequency = <200000>;
+
+ eeprom: eeprom@52 {
+ compatible = "atmel,24c128";
+ reg = <0x52>;
+ pagesize = <32>;
+ read-only;
+ };
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s4: s4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ vdd_l1_l3-supply = <&pm8941_s1>;
+ vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+ vdd_l4_l11-supply = <&pm8941_s1>;
+ vdd_l5_l7-supply = <&pm8941_s2>;
+ vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+ vin_5vs-supply = <&pm8941_5v>;
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ regulator-boot-on;
+ };
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
- soc {
- serial@f991e000 {
- status = "okay";
- };
-
- sdhci@f9824900 {
- bus-width = <8>;
- non-removable;
- status = "okay";
-
- vmmc-supply = <&pm8941_l20>;
- vqmmc-supply = <&pm8941_s3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_pin_a>;
- };
-
- sdhci@f98a4900 {
- cd-gpios = <&msmgpio 62 0x1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
- bus-width = <4>;
- status = "okay";
-
- vmmc-supply = <&pm8941_l21>;
- vqmmc-supply = <&pm8941_l13>;
- };
-
- usb@f9a55000 {
- status = "okay";
- phys = <&usb_hs2_phy>;
- phy-select = <&tcsr 0xb000 1>;
- extcon = <&smbb>, <&usb_id>;
- vbus-supply = <&chg_otg>;
- hnp-disable;
- srp-disable;
- adp-disable;
- ulpi {
- phy@b {
- status = "okay";
- v3p3-supply = <&pm8941_l24>;
- v1p8-supply = <&pm8941_l6>;
- extcon = <&smbb>;
- qcom,init-seq = /bits/ 8 <0x1 0x63>;
- };
- };
- };
-
-
- pinctrl@fd510000 {
- i2c11_pins: i2c11 {
- mux {
- pins = "gpio83", "gpio84";
- function = "blsp_i2c11";
- };
- };
-
- spi8_default: spi8_default {
- mosi {
- pins = "gpio45";
- function = "blsp_spi8";
- };
- miso {
- pins = "gpio46";
- function = "blsp_spi8";
- };
- cs {
- pins = "gpio47";
- function = "blsp_spi8";
- };
- clk {
- pins = "gpio48";
- function = "blsp_spi8";
- };
- };
-
- sdhc1_pin_a: sdhc1-pin-active {
- clk {
- pins = "sdc1_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc2_cd_pin_a: sdhc2-cd-pin-active {
- pins = "gpio62";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- sdhc2_pin_a: sdhc2-pin-active {
- clk {
- pins = "sdc2_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <6>;
- bias-pull-up;
- };
- };
- };
-
- i2c@f9967000 {
- status = "okay";
- clock-frequency = <200000>;
- pinctrl-0 = <&i2c11_pins>;
- pinctrl-names = "default";
-
- eeprom: eeprom@52 {
- compatible = "atmel,24c128";
- reg = <0x52>;
- pagesize = <32>;
- read-only;
- };
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ regulator-boot-on;
};
};
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
- smd {
- rpm {
- rpm_requests {
- pm8841-regulators {
- s1 {
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s3 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s4 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
- };
-
- pm8941-regulators {
- vdd_l1_l3-supply = <&pm8941_s1>;
- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
- vdd_l4_l11-supply = <&pm8941_s1>;
- vdd_l5_l7-supply = <&pm8941_s2>;
- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
- vin_5vs-supply = <&pm8941_5v>;
-
- s1 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- s2 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
- regulator-boot-on;
- };
-
- s3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l3 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l10 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- l11 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l15 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l17 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l18 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l19 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-allow-set-load;
- regulator-boot-on;
- regulator-system-load = <200000>;
- };
-
- l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l22 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- l23 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
-
- regulator-boot-on;
- };
- };
- };
+ cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&pm8941_l21>;
+ vqmmc-supply = <&pm8941_l13>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_on>;
+ pinctrl-1 = <&sdc2_off>;
+};
+
+&tlmm {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
};
};
+
+ sdc2_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc2_cmd", "sdc2_data";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ cd-pins {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+};
+
+&usb {
+ status = "okay";
+
+ phys = <&usb_hs2_phy>;
+ phy-select = <&tcsr 0xb000 1>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+};
+
+&usb_hs2_phy {
+ status = "okay";
+ v3p3-supply = <&pm8941_l24>;
+ v1p8-supply = <&pm8941_l6>;
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x63>;
};
diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
index 44cd72f1b1be..116e59a3b76d 100644
--- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
@@ -19,16 +19,16 @@
serial@f995e000 {
status = "okay";
};
+ };
+};
- sdhci@f9824900 {
- bus-width = <8>;
- non-removable;
- status = "okay";
- };
+&sdhc_1 {
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
- sdhci@f98a4900 {
- cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- };
- };
+&sdhc_2 {
+ cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 52240fc7a1a6..b653ea40c441 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -72,7 +72,7 @@
};
L2: l2-cache {
- compatible = "qcom,arch-cache";
+ compatible = "cache";
cache-level = <2>;
qcom,saw = <&saw_l2>;
};
@@ -95,7 +95,7 @@
firmware {
scm {
- compatible = "qcom,scm";
+ compatible = "qcom,scm-apq8084", "qcom,scm";
clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
clock-names = "core", "bus", "iface";
};
@@ -239,26 +239,334 @@
reg = <0xf9011000 0x1000>;
};
+ sram@fc190000 {
+ compatible = "qcom,apq8084-rpm-stats";
+ reg = <0xfc190000 0x10000>;
+ };
+
qfprom: qfprom@fc4bc000 {
+ compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
+ reg = <0xfc4bc000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "qcom,qfprom";
- reg = <0xfc4bc000 0x1000>;
- tsens_calib: calib@d0 {
- reg = <0xd0 0x18>;
+
+ tsens_base1: base1@d0 {
+ reg = <0xd0 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_s0_p1: s0-p1@d1 {
+ reg = <0xd1 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s1_p1: s1-p1@d2 {
+ reg = <0xd1 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s2_p1: s2-p1@d2 {
+ reg = <0xd2 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s3_p1: s3-p1@d3 {
+ reg = <0xd3 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s4_p1: s4-p1@d4 {
+ reg = <0xd4 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s5_p1: s5-p1@d4 {
+ reg = <0xd4 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s6_p1: s6-p1@d5 {
+ reg = <0xd5 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s7_p1: s7-p1@d6 {
+ reg = <0xd6 0x1>;
+ bits = <2 6>;
};
- tsens_backup: backup@440 {
- reg = <0x440 0x10>;
+
+ tsens_s8_p1: s8-p1@d7 {
+ reg = <0xd7 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_mode: mode@d7 {
+ reg = <0xd7 0x1>;
+ bits = <6 2>;
+ };
+
+ tsens_s9_p1: s9-p1@d8 {
+ reg = <0xd8 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s10_p1: s10_p1@d8 {
+ reg = <0xd8 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_base2: base2@d9 {
+ reg = <0xd9 0x2>;
+ bits = <4 8>;
+ };
+
+ tsens_s0_p2: s0-p2@da {
+ reg = <0xda 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s1_p2: s1-p2@db {
+ reg = <0xdb 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s2_p2: s2-p2@dc {
+ reg = <0xdc 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s3_p2: s3-p2@dc {
+ reg = <0xdc 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s4_p2: s4-p2@dd {
+ reg = <0xdd 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s5_p2: s5-p2@de {
+ reg = <0xde 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s6_p2: s6-p2@df {
+ reg = <0xdf 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s7_p2: s7-p2@e0 {
+ reg = <0xe0 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s8_p2: s8-p2@e0 {
+ reg = <0xe0 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s9_p2: s9-p2@e1 {
+ reg = <0xe1 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s10_p2: s10_p2@e2 {
+ reg = <0xe2 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s5_p2_backup: s5-p2_backup@e3 {
+ reg = <0xe3 0x2>;
+ bits = <0 6>;
+ };
+
+ tsens_mode_backup: mode_backup@e3 {
+ reg = <0xe3 0x1>;
+ bits = <6 2>;
+ };
+
+ tsens_s6_p2_backup: s6-p2_backup@e4 {
+ reg = <0xe4 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s7_p2_backup: s7-p2_backup@e4 {
+ reg = <0xe4 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s8_p2_backup: s8-p2_backup@e5 {
+ reg = <0xe5 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s9_p2_backup: s9-p2_backup@e6 {
+ reg = <0xe6 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s10_p2_backup: s10_p2_backup@e7 {
+ reg = <0xe7 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_base1_backup: base1_backup@440 {
+ reg = <0x440 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_s0_p1_backup: s0-p1_backup@441 {
+ reg = <0x441 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s1_p1_backup: s1-p1_backup@442 {
+ reg = <0x441 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s2_p1_backup: s2-p1_backup@442 {
+ reg = <0x442 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s3_p1_backup: s3-p1_backup@443 {
+ reg = <0x443 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s4_p1_backup: s4-p1_backup@444 {
+ reg = <0x444 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s5_p1_backup: s5-p1_backup@444 {
+ reg = <0x444 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s6_p1_backup: s6-p1_backup@445 {
+ reg = <0x445 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s7_p1_backup: s7-p1_backup@446 {
+ reg = <0x446 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_use_backup: use_backup@447 {
+ reg = <0x447 0x1>;
+ bits = <5 3>;
+ };
+
+ tsens_s8_p1_backup: s8-p1_backup@448 {
+ reg = <0x448 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s9_p1_backup: s9-p1_backup@448 {
+ reg = <0x448 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s10_p1_backup: s10_p1_backup@449 {
+ reg = <0x449 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_base2_backup: base2_backup@44a {
+ reg = <0x44a 0x2>;
+ bits = <2 8>;
+ };
+
+ tsens_s0_p2_backup: s0-p2_backup@44b {
+ reg = <0x44b 0x3>;
+ bits = <2 6>;
+ };
+
+ tsens_s1_p2_backup: s1-p2_backup@44c {
+ reg = <0x44c 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s2_p2_backup: s2-p2_backup@44c {
+ reg = <0x44c 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s3_p2_backup: s3-p2_backup@44d {
+ reg = <0x44d 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s4_p2_backup: s4-p2_backup@44e {
+ reg = <0x44e 0x1>;
+ bits = <2 6>;
};
};
tsens: thermal-sensor@fc4a8000 {
- compatible = "qcom,msm8974-tsens";
+ compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
reg = <0xfc4a9000 0x1000>, /* TM */
<0xfc4a8000 0x1000>; /* SROT */
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>, <&tsens_base2>,
+ <&tsens_use_backup>,
+ <&tsens_mode_backup>,
+ <&tsens_base1_backup>, <&tsens_base2_backup>,
+ <&tsens_s0_p1>, <&tsens_s0_p2>,
+ <&tsens_s1_p1>, <&tsens_s1_p2>,
+ <&tsens_s2_p1>, <&tsens_s2_p2>,
+ <&tsens_s3_p1>, <&tsens_s3_p2>,
+ <&tsens_s4_p1>, <&tsens_s4_p2>,
+ <&tsens_s5_p1>, <&tsens_s5_p2>,
+ <&tsens_s6_p1>, <&tsens_s6_p2>,
+ <&tsens_s7_p1>, <&tsens_s7_p2>,
+ <&tsens_s8_p1>, <&tsens_s8_p2>,
+ <&tsens_s9_p1>, <&tsens_s9_p2>,
+ <&tsens_s10_p1>, <&tsens_s10_p2>,
+ <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
+ <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
+ <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
+ <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
+ <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
+ <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
+ <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
+ <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
+ <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
+ <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
+ <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
+ nvmem-cell-names = "mode",
+ "base1", "base2",
+ "use_backup",
+ "mode_backup",
+ "base1_backup", "base2_backup",
+ "s0_p1", "s0_p2",
+ "s1_p1", "s1_p2",
+ "s2_p1", "s2_p2",
+ "s3_p1", "s3_p2",
+ "s4_p1", "s4_p2",
+ "s5_p1", "s5_p2",
+ "s6_p1", "s6_p2",
+ "s7_p1", "s7_p2",
+ "s8_p1", "s8_p2",
+ "s9_p1", "s9_p2",
+ "s10_p1", "s10_p2",
+ "s0_p1_backup", "s0_p2_backup",
+ "s1_p1_backup", "s1_p2_backup",
+ "s2_p1_backup", "s2_p2_backup",
+ "s3_p1_backup", "s3_p2_backup",
+ "s4_p1_backup", "s4_p2_backup",
+ "s5_p1_backup", "s5_p2_backup",
+ "s6_p1_backup", "s6_p2_backup",
+ "s7_p1_backup", "s7_p2_backup",
+ "s8_p1_backup", "s8_p2_backup",
+ "s9_p1_backup", "s9_p2_backup",
+ "s10_p1_backup", "s10_p2_backup";
#qcom,sensors = <11>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
timer@f9020000 {
@@ -346,25 +654,25 @@
regulator;
};
- acc0: clock-controller@f9088000 {
+ acc0: power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>,
<0xf9008000 0x1000>;
};
- acc1: clock-controller@f9098000 {
+ acc1: power-manager@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>,
<0xf9008000 0x1000>;
};
- acc2: clock-controller@f90a8000 {
+ acc2: power-manager@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>,
<0xf9008000 0x1000>;
};
- acc3: clock-controller@f90b8000 {
+ acc3: power-manager@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>,
<0xf9008000 0x1000>;
@@ -381,20 +689,33 @@
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
- };
-
- tcsr_mutex_regs: syscon@fd484000 {
- compatible = "syscon";
- reg = <0xfd484000 0x2000>;
- };
-
- tcsr_mutex: hwlock {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_regs 0 0x80>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <0>, /* ufs */
+ <0>,
+ <0>,
+ <0>,
+ <0>, /* sata */
+ <0>,
+ <0>; /* pcie */
+ clock-names = "xo",
+ "sleep_clk",
+ "ufs_rx_symbol_0_clk_src",
+ "ufs_rx_symbol_1_clk_src",
+ "ufs_tx_symbol_0_clk_src",
+ "ufs_tx_symbol_1_clk_src",
+ "sata_asic0_clk",
+ "sata_rx_clk",
+ "pcie_pipe";
+ };
+
+ tcsr_mutex: hwlock@fd484000 {
+ compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
+ reg = <0xfd484000 0x1000>;
#hwlock-cells = <1>;
};
- rpm_msg_ram: memory@fc428000 {
+ rpm_msg_ram: sram@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
@@ -419,29 +740,29 @@
status = "disabled";
};
- sdhci@f9824900 {
+ sdhc_1: mmc@f9824900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
status = "disabled";
};
- sdhci@f98a4900 {
+ sdhc_2: mmc@f98a4900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
status = "disabled";
};
@@ -470,11 +791,11 @@
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
- rpm_requests {
+ rpm-requests {
compatible = "qcom,rpm-apq8084";
qcom,smd-channels = "rpm_requests";
- pma8084-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pma8084-regulators";
pma8084_s1: s1 {};
diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts
index 028ac8e24797..1b27edce9d4f 100644
--- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts
+++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#include <dt-bindings/leds/common.h>
#include "qcom-ipq4018-ap120c-ac.dtsi"
/ {
@@ -8,19 +9,24 @@
leds {
compatible = "gpio-leds";
- power {
+ led-power {
label = "ap120c-ac:green:power";
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- wlan {
+ led-wlan {
label = "ap120c-ac:green:wlan";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
- support {
+ led-support {
label = "ap120c-ac:green:support";
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
index b7916fc26d68..a707057c887d 100644
--- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
+++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
@@ -1,25 +1,32 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#include <dt-bindings/leds/common.h>
#include "qcom-ipq4018-ap120c-ac.dtsi"
/ {
leds {
compatible = "gpio-leds";
- status: status {
+ status: led-status {
label = "ap120c-ac:blue:status";
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- wlan2g {
+ led-wlan2g {
label = "ap120c-ac:green:wlan2g";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
- wlan5g {
+ led-wlan5g {
label = "ap120c-ac:red:wlan5g";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_RED>;
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi
index 1f3b1ce82108..d90b4f4c63af 100644
--- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi
@@ -6,12 +6,20 @@
/ {
model = "ALFA Network AP120C-AC";
- compatible = "alfa-network,ap120c-ac";
+ compatible = "alfa-network,ap120c-ac", "qcom,ipq4018";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
keys {
compatible = "gpio-keys";
- reset {
+ key-reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
@@ -68,7 +76,7 @@
};
};
- usb-power {
+ usb-power-hog {
line-name = "USB-power";
gpios = <1 GPIO_ACTIVE_HIGH>;
gpio-hog;
@@ -162,6 +170,17 @@
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ precal_art_1000: precal@1000 {
+ reg = <0x1000 0x2f20>;
+ };
+
+ precal_art_5000: precal@5000 {
+ reg = <0x5000 0x2f20>;
+ };
};
partition@180000 {
@@ -178,7 +197,7 @@
};
};
- nand@1 {
+ flash@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <40000000>;
@@ -225,10 +244,14 @@
&wifi0 {
status = "okay";
+ nvmem-cell-names = "pre-calibration";
+ nvmem-cells = <&precal_art_1000>;
};
&wifi1 {
status = "okay";
+ nvmem-cell-names = "pre-calibration";
+ nvmem-cells = <&precal_art_5000>;
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts
index 394412619894..365fbac417fd 100644
--- a/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts
+++ b/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts
@@ -7,7 +7,7 @@
/ {
model = "8devices Jalapeno";
- compatible = "8dev,jalapeno";
+ compatible = "8dev,jalapeno", "qcom,ipq4018";
};
&tlmm {
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 0c10d9e096db..0505270cf508 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -14,6 +14,7 @@
*
*/
+#include <dt-bindings/gpio/gpio.h>
#include "qcom-ipq4019.dtsi"
/ {
@@ -64,7 +65,7 @@
};
};
- blsp_dma: dma@7884000 {
+ blsp_dma: dma-controller@7884000 {
status = "okay";
};
@@ -72,7 +73,7 @@
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
- cs-gpios = <&tlmm 54 0>;
+ cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l25635e@0 {
#address-cells = <1>;
@@ -89,7 +90,7 @@
status = "okay";
};
- cryptobam: dma@8e04000 {
+ cryptobam: dma-controller@8e04000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
index a7b1201dd614..79b0c6318e52 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -8,7 +8,7 @@
compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019";
soc {
- dma@7984000 {
+ dma-controller@7984000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
index 7a337dc08741..a63b3778636d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -79,7 +79,7 @@
status = "okay";
};
- dma@7884000 {
+ dma-controller@7884000 {
status = "okay";
};
@@ -87,20 +87,20 @@
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
- cs-gpios = <&tlmm 12 0>;
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- compatible = "n25q128a11";
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <24000000>;
};
};
pci@40000000 {
status = "okay";
- perst-gpio = <&tlmm 38 0x1>;
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
qpic-nand@79b0000 {
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
index 06f9f2cb2fe9..ea2987fcbff8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+#include <dt-bindings/gpio/gpio.h>
#include "qcom-ipq4019-ap.dk07.1.dtsi"
/ {
@@ -10,7 +11,7 @@
soc {
pci@40000000 {
status = "okay";
- perst-gpio = <&tlmm 38 0x1>;
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
spi@78b6000 {
@@ -50,13 +51,13 @@
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
- cs-gpios = <&tlmm 12 0>;
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- compatible = "n25q128a11";
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <24000000>;
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
index 94872518b5a2..0107f552f520 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -52,7 +52,7 @@
status = "okay";
};
- dma@7884000 {
+ dma-controller@7884000 {
status = "okay";
};
@@ -62,7 +62,7 @@
status = "okay";
};
- dma@7984000 {
+ dma-controller@7984000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index a9d0566a3190..dfcfb3339c23 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -106,7 +106,7 @@
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
@@ -143,7 +143,6 @@
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
- clock-output-names = "gcc_sleep_clk_src";
#clock-cells = <0>;
};
@@ -156,7 +155,7 @@
firmware {
scm {
- compatible = "qcom,scm-ipq4019";
+ compatible = "qcom,scm-ipq4019", "qcom,scm";
};
};
@@ -190,6 +189,8 @@
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x1800000 0x60000>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
};
prng: rng@22000 {
@@ -221,19 +222,20 @@
status = "disabled";
};
- sdhci: sdhci@7824900 {
+ sdhci: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_DCD_XO_CLK>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
status = "disabled";
};
- blsp_dma: dma@7884000 {
+ blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
@@ -253,8 +255,8 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 5>, <&blsp_dma 4>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -267,8 +269,8 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 7>, <&blsp_dma 6>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -276,13 +278,13 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 9>, <&blsp_dma 8>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -290,17 +292,17 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 11>, <&blsp_dma 10>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
status = "disabled";
};
- cryptobam: dma@8e04000 {
+ cryptobam: dma-controller@8e04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x08e04000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
@@ -324,22 +326,22 @@
status = "disabled";
};
- acc0: clock-controller@b088000 {
+ acc0: power-manager@b088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
};
- acc1: clock-controller@b098000 {
+ acc1: power-manager@b098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
};
- acc2: clock-controller@b0a8000 {
+ acc2: power-manager@b0a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
};
- acc3: clock-controller@b0b8000 {
+ acc3: power-manager@b0b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
@@ -347,7 +349,7 @@
saw0: regulator@b089000 {
compatible = "qcom,saw2";
reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
- regulator;
+ regulator;
};
saw1: regulator@b099000 {
@@ -382,8 +384,8 @@
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 1>, <&blsp_dma 0>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 0>, <&blsp_dma 1>;
+ dma-names = "tx", "rx";
};
blsp1_uart2: serial@78b0000 {
@@ -394,12 +396,12 @@
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 3>, <&blsp_dma 2>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 2>, <&blsp_dma 3>;
+ dma-names = "tx", "rx";
};
watchdog: watchdog@b017000 {
- compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
+ compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt";
reg = <0xb017000 0x40>;
clocks = <&sleep_clk>;
timeout-sec = <10>;
@@ -412,7 +414,7 @@
};
pcie0: pci@40000000 {
- compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d
0x40000f20 0xa8
0x80000 0x2000
@@ -425,8 +427,8 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
- <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
+ ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
+ <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -471,7 +473,7 @@
status = "disabled";
};
- qpic_bam: dma@7984000 {
+ qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x7984000 0x1a000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@@ -646,7 +648,7 @@
clocks = <&gcc GCC_USB3_MASTER_CLK>,
<&gcc GCC_USB3_SLEEP_CLK>,
<&gcc GCC_USB3_MOCK_UTMI_CLK>;
- clock-names = "master", "sleep", "mock_utmi";
+ clock-names = "core", "sleep", "mock_utmi";
ranges;
status = "disabled";
diff --git a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
new file mode 100644
index 000000000000..9d06255104c7
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "qcom-ipq8062.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom-ipq8062.dtsi
new file mode 100644
index 000000000000..5d3ebd3e2e51
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "qcom-ipq8064-v2.0.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8062";
+ compatible = "qcom,ipq8062", "qcom,ipq8064";
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index b63d01d10189..a654d3c22c4f 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -7,12 +7,6 @@
soc {
pinmux@800000 {
- i2c4_pins: i2c4_pinmux {
- pins = "gpio12", "gpio13";
- function = "gsbi4";
- bias-disable;
- };
-
buttons_pins: buttons_pins {
mux {
pins = "gpio54", "gpio65";
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 596d129d4a95..4d509876294b 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "MikroTik RB3011UiAS-RM";
- compatible = "mikrotik,rb3011";
+ compatible = "mikrotik,rb3011", "qcom,ipq8064";
aliases {
serial0 = &gsbi7_serial;
@@ -37,8 +38,6 @@
switch0: switch@10 {
compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
dsa,member = <0 0>;
@@ -66,26 +65,86 @@
port@1 {
reg = <1>;
label = "sw1";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@2 {
reg = <2>;
label = "sw2";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@3 {
reg = <3>;
label = "sw3";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@4 {
reg = <4>;
label = "sw4";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@5 {
reg = <5>;
label = "sw5";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
};
@@ -104,8 +163,6 @@
switch1: switch@14 {
compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
dsa,member = <1 0>;
@@ -133,26 +190,86 @@
port@1 {
reg = <1>;
label = "sw6";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@2 {
reg = <2>;
label = "sw7";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@3 {
reg = <3>;
label = "sw8";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@4 {
reg = <4>;
label = "sw9";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
port@5 {
reg = <5>;
label = "sw10";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
};
@@ -187,12 +304,12 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&buttons_pins>;
pinctrl-names = "default";
- button@1 {
+ button {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>;
@@ -208,6 +325,7 @@
led@7 {
label = "rb3011:green:user";
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
@@ -262,8 +380,7 @@
&nand {
status = "okay";
- nandcs@0 {
- compatible = "qcom,nandcs";
+ nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
@@ -305,15 +422,6 @@
};
};
- mdio0_pins: mdio0_pins {
- mux {
- pins = "gpio0", "gpio1";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- };
-
mdio1_pins: mdio1_pins {
mux {
pins = "gpio10", "gpio11";
diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
new file mode 100644
index 000000000000..ac9c44f0c164
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
index 65330065390a..411c8d63c38e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
@@ -36,7 +37,7 @@
cs-gpios = <&qcom_pinmux 20 0>;
- flash: m25p80@0 {
+ flash: flash@0 {
compatible = "s25fl256s1";
#address-cells = <1>;
#size-cells = <1>;
@@ -65,19 +66,19 @@
status = "okay";
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&buttons_pins>;
pinctrl-names = "default";
- button@1 {
+ button-1 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
- button@2 {
+ button-2 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
@@ -107,6 +108,7 @@
led@9 {
label = "status_led_fail";
+ function = LED_FUNCTION_STATUS;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
@@ -119,6 +121,7 @@
led@53 {
label = "status_led_pass";
+ function = LED_FUNCTION_STATUS;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
new file mode 100644
index 000000000000..0442580b22de
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064-v2.0.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
new file mode 100644
index 000000000000..2f117d576daf
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";
+
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@41200000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@16340000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 996f4458d9fc..af6764770fd1 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -292,19 +292,22 @@
};
smem: smem@41000000 {
+ compatible = "qcom,smem";
reg = <0x41000000 0x200000>;
no-map;
+
+ hwlocks = <&sfpb_mutex 3>;
};
};
clocks {
- cxo_board {
+ cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
- pxo_board {
+ pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
@@ -323,30 +326,70 @@
};
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <7>;
+ snps,rd_osr_lmt = <7>;
+ snps,blen = <16 0 0 0 0 0 0>;
+ };
+
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
- lpass@28100000 {
- compatible = "qcom,lpass-cpu";
- status = "disabled";
- clocks = <&lcc AHBIX_CLK>,
- <&lcc MI2S_OSR_CLK>,
- <&lcc MI2S_BIT_CLK>;
- clock-names = "ahbix-clk",
- "mi2s-osr-clk",
- "mi2s-bit-clk";
- interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "lpass-irq-lpaif";
- reg = <0x28100000 0x10000>;
- reg-names = "lpass-lpaif";
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-ipq8064";
+ reg = <0x00108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ack", "err", "wakeup";
+
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
+ clock-names = "ram";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+ };
+
+ qcom,ssbi@500000 {
+ compatible = "qcom,ssbi";
+ reg = <0x00500000 0x1000>;
+ qcom,controller-type = "pmic-arbiter";
+ };
+
+ qfprom: qfprom@700000 {
+ compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
+ reg = <0x00700000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ speedbin_efuse: speedbin@c0 {
+ reg = <0xc0 0x4>;
+ };
+ tsens_calib: calib@400 {
+ reg = <0x400 0xb>;
+ };
+ tsens_calib_backup: calib_backup@410 {
+ reg = <0x410 0xb>;
+ };
};
qcom_pinmux: pinmux@800000 {
compatible = "qcom,ipq8064-pinctrl";
- reg = <0x800000 0x4000>;
+ reg = <0x00800000 0x4000>;
gpio-controller;
gpio-ranges = <&qcom_pinmux 0 0 69>;
@@ -382,6 +425,13 @@
};
};
+ i2c4_pins: i2c4-default {
+ pins = "gpio12", "gpio13";
+ function = "gsbi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -424,6 +474,8 @@
pullups {
pins = "gpio39";
+ function = "nand";
+ drive-strength = <10>;
bias-pull-up;
};
@@ -431,9 +483,61 @@
pins = "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
bias-bus-hold;
};
};
+
+ mdio0_pins: mdio0-pins {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ rgmii2_pins: rgmii2-pins {
+ mux {
+ pins = "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32",
+ "gpio51", "gpio52", "gpio59",
+ "gpio60", "gpio61", "gpio62";
+ function = "rgmii2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+ };
+
+ gcc: clock-controller@900000 {
+ compatible = "qcom,gcc-ipq8064", "syscon";
+ clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
+ clock-names = "pxo", "cxo", "pll4";
+ reg = <0x00900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ tsens: thermal-sensor@900000 {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ sfpb_mutex: hwlock@1200600 {
+ compatible = "qcom,sfpb-mutex";
+ reg = <0x01200600 0x100>;
+
+ #hwlock-cells = <1>;
};
intc: interrupt-controller@2000000 {
@@ -445,8 +549,8 @@
};
timer@200a000 {
- compatible = "qcom,kpss-timer",
- "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
+ compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
+ "qcom,msm-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
@@ -458,53 +562,247 @@
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
- clock-frequency = <25000000>,
- <32768>;
+ clock-frequency = <25000000>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;
};
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
+ reg = <0x02011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
+ };
+
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
+ #clock-cells = <0>;
+ };
+
+ saw0: regulator@2089000 {
+ compatible = "qcom,saw2";
+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+ regulator;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu1_aux";
+ #clock-cells = <0>;
};
- adm_dma: dma-controller@18300000 {
- compatible = "qcom,adm";
- reg = <0x18300000 0x100000>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
+ saw1: regulator@2099000 {
+ compatible = "qcom,saw2";
+ reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+ regulator;
+ };
- clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
- clock-names = "core", "iface";
+ nss_common: syscon@03000000 {
+ compatible = "syscon";
+ reg = <0x03000000 0x0000FFFF>;
+ };
- resets = <&gcc ADM0_RESET>,
- <&gcc ADM0_PBUS_RESET>,
- <&gcc ADM0_C0_RESET>,
- <&gcc ADM0_C1_RESET>,
- <&gcc ADM0_C2_RESET>;
- reset-names = "clk", "pbus", "c0", "c1", "c2";
- qcom,ee = <0>;
+ usb3_0: usb3@100f8800 {
+ compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x100f8800 0x8000>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_0_MASTER_RESET>;
+ reset-names = "master";
status = "disabled";
+
+ dwc3_0: dwc3@10000000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000000 0xcd00>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_0>, <&ss_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
};
- saw0: regulator@2089000 {
- compatible = "qcom,saw2";
- reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
+ hs_phy_0: phy@100f8800 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
};
- saw1: regulator@2099000 {
- compatible = "qcom,saw2";
- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
+ ss_phy_0: phy@100f8830 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb3_1: usb3@110f8800 {
+ compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x110f8800 0x8000>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_1_MASTER_RESET>;
+ reset-names = "master";
+
+ status = "disabled";
+
+ dwc3_1: dwc3@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0xcd00>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_1>, <&ss_phy_1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ hs_phy_1: phy@110f8800 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x110f8800 0x30>;
+ clocks = <&gcc USB30_1_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ss_phy_1: phy@110f8830 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x110f8830 0x30>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ sdcc3bam: dma-controller@12182000 {
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12182000 0x8000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC3_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ sdcc1bam: dma-controller@12402000 {
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12402000 0x8000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sdcc3: mmc@12180000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <192000000>;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ vqmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+ dma-names = "tx", "rx";
+ };
+
+ sdcc1: mmc@12400000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ reg = <0x12400000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
+ non-removable;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ gsbi1: gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x12440000 0x100>;
+ cell-index = <1>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi1_serial: serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+
+ status = "disabled";
+ };
+
+ gsbi1_i2c: i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
};
gsbi2: gsbi@12480000 {
@@ -530,7 +828,7 @@
status = "disabled";
};
- i2c@124a0000 {
+ gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -581,6 +879,106 @@
};
};
+ gsbi6: gsbi@16500000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16500000 0x100>;
+ cell-index = <6>;
+ clocks = <&gcc GSBI6_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi6_i2c: i2c@16580000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ gsbi6_spi: spi@16580000 {
+ compatible = "qcom,spi-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gsbi7: gsbi@16600000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <7>;
+ reg = <0x16600000 0x100>;
+ clocks = <&gcc GSBI7_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ syscon-tcsr = <&tcsr>;
+
+ gsbi7_serial: serial@16640000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x16640000 0x1000>,
+ <0x16600000 0x1000>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ gsbi7_i2c: i2c@16680000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ adm_dma: dma-controller@18300000 {
+ compatible = "qcom,adm";
+ reg = <0x18300000 0x100000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+ clock-names = "core", "iface";
+
+ resets = <&gcc ADM0_RESET>,
+ <&gcc ADM0_PBUS_RESET>,
+ <&gcc ADM0_C0_RESET>,
+ <&gcc ADM0_C1_RESET>,
+ <&gcc ADM0_C2_RESET>;
+ reset-names = "clk", "pbus", "c0", "c1", "c2";
+ qcom,ee = <0>;
+
+ status = "disabled";
+ };
+
gsbi5: gsbi@1a200000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <5>;
@@ -588,6 +986,7 @@
clocks = <&gcc GSBI5_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
+
#size-cells = <1>;
ranges;
status = "disabled";
@@ -631,27 +1030,9 @@
};
};
- gsbi7: gsbi@16600000 {
- status = "disabled";
- compatible = "qcom,gsbi-v1.0.0";
- cell-index = <7>;
- reg = <0x16600000 0x100>;
- clocks = <&gcc GSBI7_H_CLK>;
- clock-names = "iface";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- syscon-tcsr = <&tcsr>;
-
- gsbi7_serial: serial@16640000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x16640000 0x1000>,
- <0x16600000 0x1000>;
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-ipq8064", "syscon";
+ reg = <0x1a400000 0x100>;
};
rng@1a500000 {
@@ -661,17 +1042,6 @@
clock-names = "core";
};
- sata_phy: sata-phy@1b400000 {
- compatible = "qcom,ipq806x-sata-phy";
- reg = <0x1b400000 0x200>;
-
- clocks = <&gcc SATA_PHY_CFG_CLK>;
- clock-names = "cfg";
-
- #phy-cells = <0>;
- status = "disabled";
- };
-
nand: nand-controller@1ac00000 {
compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
@@ -694,106 +1064,17 @@
status = "disabled";
};
- sata: sata@29000000 {
- compatible = "qcom,ipq806x-ahci", "generic-ahci";
- reg = <0x29000000 0x180>;
-
- interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&gcc SFAB_SATA_S_H_CLK>,
- <&gcc SATA_H_CLK>,
- <&gcc SATA_A_CLK>,
- <&gcc SATA_RXOOB_CLK>,
- <&gcc SATA_PMALIVE_CLK>;
- clock-names = "slave_face", "iface", "core",
- "rxoob", "pmalive";
+ sata_phy: sata-phy@1b400000 {
+ compatible = "qcom,ipq806x-sata-phy";
+ reg = <0x1b400000 0x200>;
- assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
- assigned-clock-rates = <100000000>, <100000000>;
+ clocks = <&gcc SATA_PHY_CFG_CLK>;
+ clock-names = "cfg";
- phys = <&sata_phy>;
- phy-names = "sata-phy";
+ #phy-cells = <0>;
status = "disabled";
};
- qcom,ssbi@500000 {
- compatible = "qcom,ssbi";
- reg = <0x00500000 0x1000>;
- qcom,controller-type = "pmic-arbiter";
- };
-
- qfprom: qfprom@700000 {
- compatible = "qcom,qfprom";
- reg = <0x00700000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- tsens_calib: calib@400 {
- reg = <0x400 0xb>;
- };
- tsens_calib_backup: calib_backup@410 {
- reg = <0x410 0xb>;
- };
- };
-
- gcc: clock-controller@900000 {
- compatible = "qcom,gcc-ipq8064";
- reg = <0x00900000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
-
- tsens: thermal-sensor@900000 {
- compatible = "qcom,ipq8064-tsens";
-
- nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
- nvmem-cell-names = "calib", "calib_backup";
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
-
- #qcom,sensors = <11>;
- #thermal-sensor-cells = <1>;
- };
- };
-
- rpm: rpm@108000 {
- compatible = "qcom,rpm-ipq8064";
- reg = <0x108000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
-
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ack", "err", "wakeup";
-
- clocks = <&gcc RPM_MSG_RAM_H_CLK>;
- clock-names = "ram";
-
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
- #clock-cells = <1>;
- };
- };
-
- tcsr: syscon@1a400000 {
- compatible = "qcom,tcsr-ipq8064", "syscon";
- reg = <0x1a400000 0x100>;
- };
-
- l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x2011000 0x1000>;
- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu_l2_aux";
- };
-
- lcc: clock-controller@28000000 {
- compatible = "qcom,lcc-ipq8064";
- reg = <0x28000000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
@@ -808,8 +1089,8 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
- 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
+ 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -842,7 +1123,7 @@
pinctrl-names = "default";
status = "disabled";
- perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
};
pcie1: pci@1b700000 {
@@ -859,8 +1140,8 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
- 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
+ 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -893,7 +1174,7 @@
pinctrl-names = "default";
status = "disabled";
- perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
};
pcie2: pci@1b900000 {
@@ -910,8 +1191,8 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
- 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
+ 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -944,12 +1225,7 @@
pinctrl-names = "default";
status = "disabled";
- perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
- };
-
- nss_common: syscon@03000000 {
- compatible = "syscon";
- reg = <0x03000000 0x0000FFFF>;
+ perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
};
qsgmii_csr: syscon@1bb00000 {
@@ -957,22 +1233,60 @@
reg = <0x1bb00000 0x000001FF>;
};
- stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <7>;
- snps,rd_osr_lmt = <7>;
- snps,blen = <16 0 0 0 0 0 0>;
+ lcc: clock-controller@28000000 {
+ compatible = "qcom,lcc-ipq8064";
+ reg = <0x28000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ lpass@28100000 {
+ compatible = "qcom,lpass-cpu";
+ status = "disabled";
+ clocks = <&lcc AHBIX_CLK>,
+ <&lcc MI2S_OSR_CLK>,
+ <&lcc MI2S_BIT_CLK>;
+ clock-names = "ahbix-clk",
+ "mi2s-osr-clk",
+ "mi2s-bit-clk";
+ interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "lpass-irq-lpaif";
+ reg = <0x28100000 0x10000>;
+ reg-names = "lpass-lpaif";
+ };
+
+ sata: sata@29000000 {
+ compatible = "qcom,ipq806x-ahci", "generic-ahci";
+ reg = <0x29000000 0x180>;
+
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc SFAB_SATA_S_H_CLK>,
+ <&gcc SATA_H_CLK>,
+ <&gcc SATA_A_CLK>,
+ <&gcc SATA_RXOOB_CLK>,
+ <&gcc SATA_PMALIVE_CLK>;
+ clock-names = "slave_face", "iface", "core",
+ "rxoob", "pmalive";
+
+ assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
+ assigned-clock-rates = <100000000>, <100000000>;
+
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ status = "disabled";
};
gmac0: ethernet@37000000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
- snps,aal = <1>;
+ snps,aal;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
@@ -989,14 +1303,14 @@
gmac1: ethernet@37200000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
- snps,aal = <1>;
+ snps,aal;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
@@ -1013,14 +1327,14 @@
gmac2: ethernet@37400000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
- snps,aal = <1>;
+ snps,aal;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
@@ -1037,14 +1351,14 @@
gmac3: ethernet@37600000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
- snps,aal = <1>;
+ snps,aal;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
@@ -1058,168 +1372,5 @@
status = "disabled";
};
-
- hs_phy_0: phy@100f8800 {
- compatible = "qcom,ipq806x-usb-phy-hs";
- reg = <0x100f8800 0x30>;
- clocks = <&gcc USB30_0_UTMI_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- ss_phy_0: phy@100f8830 {
- compatible = "qcom,ipq806x-usb-phy-ss";
- reg = <0x100f8830 0x30>;
- clocks = <&gcc USB30_0_MASTER_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb3_0: usb3@100f8800 {
- compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x100f8800 0x8000>;
- clocks = <&gcc USB30_0_MASTER_CLK>;
- clock-names = "core";
-
- ranges;
-
- resets = <&gcc USB30_0_MASTER_RESET>;
- reset-names = "master";
-
- status = "disabled";
-
- dwc3_0: dwc3@10000000 {
- compatible = "snps,dwc3";
- reg = <0x10000000 0xcd00>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&hs_phy_0>, <&ss_phy_0>;
- phy-names = "usb2-phy", "usb3-phy";
- dr_mode = "host";
- snps,dis_u3_susphy_quirk;
- };
- };
-
- hs_phy_1: phy@110f8800 {
- compatible = "qcom,ipq806x-usb-phy-hs";
- reg = <0x110f8800 0x30>;
- clocks = <&gcc USB30_1_UTMI_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
- };
-
- ss_phy_1: phy@110f8830 {
- compatible = "qcom,ipq806x-usb-phy-ss";
- reg = <0x110f8830 0x30>;
- clocks = <&gcc USB30_1_MASTER_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
- };
-
- usb3_1: usb3@110f8800 {
- compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x110f8800 0x8000>;
- clocks = <&gcc USB30_1_MASTER_CLK>;
- clock-names = "core";
-
- ranges;
-
- resets = <&gcc USB30_1_MASTER_RESET>;
- reset-names = "master";
-
- status = "disabled";
-
- dwc3_1: dwc3@11000000 {
- compatible = "snps,dwc3";
- reg = <0x11000000 0xcd00>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&hs_phy_1>, <&ss_phy_1>;
- phy-names = "usb2-phy", "usb3-phy";
- dr_mode = "host";
- snps,dis_u3_susphy_quirk;
- };
- };
-
- vsdcc_fixed: vsdcc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "SDCC Power";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- sdcc1bam: dma@12402000 {
- compatible = "qcom,bam-v1.3.0";
- reg = <0x12402000 0x8000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc SDC1_H_CLK>;
- clock-names = "bam_clk";
- #dma-cells = <1>;
- qcom,ee = <0>;
- };
-
- sdcc3bam: dma@12182000 {
- compatible = "qcom,bam-v1.3.0";
- reg = <0x12182000 0x8000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc SDC3_H_CLK>;
- clock-names = "bam_clk";
- #dma-cells = <1>;
- qcom,ee = <0>;
- };
-
- amba: amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x2000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <96000000>;
- non-removable;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- vmmc-supply = <&vsdcc_fixed>;
- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
- dma-names = "tx", "rx";
- };
-
- sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x2000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <192000000>;
- sd-uhs-sdr104;
- sd-uhs-ddr50;
- vqmmc-supply = <&vsdcc_fixed>;
- dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
- dma-names = "tx", "rx";
- };
- };
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
new file mode 100644
index 000000000000..803e6ff99ef8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8065.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom-ipq8065.dtsi
new file mode 100644
index 000000000000..ea49f6cc416d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064-v2.0.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8065";
+ compatible = "qcom,ipq8065", "qcom,ipq8064";
+};
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
index 0827de5426c1..a8304769b509 100644
--- a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Device Tree Source for mangOH Green Board with WP8548 Module
*
* Copyright (C) 2016 BayLibre, SAS.
* Author : Neil Armstrong <narmstrong@baylibre.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
@@ -82,8 +45,8 @@
* - 42: IOT0_GPIO1 and SD Card Detect
*/
- gpioext1_pins: gpioext1_pins {
- pins {
+ gpioext1_pins: gpioext1-state {
+ gpioext1-pins {
pins = "gpio2";
function = "gpio";
input-enable;
@@ -91,8 +54,8 @@
};
};
- sdc_cd_pins: sdc_cd_pins {
- pins {
+ sdc_cd_pins: sdc-cd-state {
+ sdc-cd-pins {
pins = "gpio42";
function = "gpio";
drive-strength = <2>;
@@ -153,7 +116,7 @@
#size-cells = <0>;
reg = <4>;
- gpioext0: gpio@3e {
+ gpioext0: pinctrl@3e {
/* GPIO Expander 0 Mapping :
* - 0: ARDUINO_RESET_Level shift
* - 1: BattChrgr_PG_N
@@ -179,7 +142,7 @@
interrupt-parent = <&gpioext1>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
- probe-reset;
+ semtech,probe-reset;
gpio-controller;
interrupt-controller;
@@ -191,7 +154,7 @@
#size-cells = <0>;
reg = <5>;
- gpioext1: gpio@3f {
+ gpioext1: pinctrl@3f {
/* GPIO Expander 1 Mapping :
* - 0: GPIOEXP_INT1
* - 1: Battery detect
@@ -220,7 +183,7 @@
interrupt-parent = <&msmgpio>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
- probe-reset;
+ semtech,probe-reset;
gpio-controller;
interrupt-controller;
@@ -232,7 +195,7 @@
#size-cells = <0>;
reg = <6>;
- gpioext2: gpio@70 {
+ gpioext2: pinctrl@70 {
/* GPIO Expander 2 Mapping :
* - 0: USB_HUB_INTn
* - 1: HUB_CONNECT
@@ -258,7 +221,7 @@
interrupt-parent = <&gpioext1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
- probe-reset;
+ semtech,probe-reset;
gpio-controller;
interrupt-controller;
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
index 10ad929759ed..92c8003dac25 100644
--- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Device Tree Source for Sierra Wireless WP8548 Module
*
* Copyright (C) 2016 BayLibre, SAS.
* Author : Neil Armstrong <narmstrong@baylibre.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "qcom-mdm9615.dtsi"
@@ -59,8 +22,8 @@
pinctrl-0 = <&reset_out_pins>;
pinctrl-names = "default";
- gsbi3_pins: gsbi3_pins {
- mux {
+ gsbi3_pins: gsbi3-state {
+ gsbi3-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "gsbi3";
drive-strength = <8>;
@@ -68,8 +31,8 @@
};
};
- gsbi4_pins: gsbi4_pins {
- mux {
+ gsbi4_pins: gsbi4-state {
+ gsbi4-pins {
pins = "gpio12", "gpio13", "gpio14", "gpio15";
function = "gsbi4";
drive-strength = <8>;
@@ -77,15 +40,15 @@
};
};
- gsbi5_i2c_pins: gsbi5_i2c_pins {
- pin16 {
+ gsbi5_i2c_pins: gsbi5-i2c-state {
+ sda-pins {
pins = "gpio16";
function = "gsbi5_i2c";
drive-strength = <8>;
bias-disable;
};
- pin17 {
+ scl-pins {
pins = "gpio17";
function = "gsbi5_i2c";
drive-strength = <2>;
@@ -93,8 +56,8 @@
};
};
- gsbi5_uart_pins: gsbi5_uart_pins {
- mux {
+ gsbi5_uart_pins: gsbi5-uart-state {
+ gsbi5-uart-pins {
pins = "gpio18", "gpio19";
function = "gsbi5_uart";
drive-strength = <8>;
@@ -102,8 +65,8 @@
};
};
- reset_out_pins: reset_out_pins {
- pins {
+ reset_out_pins: reset-out-state {
+ reset-out-pins {
pins = "gpio66";
function = "gpio";
drive-strength = <2>;
@@ -114,7 +77,7 @@
};
&pmicgpio {
- usb_vbus_5v_pins: usb_vbus_5v_pins {
+ usb_vbus_5v_pins: usb-vbus-5v-state {
pins = "gpio4";
function = "normal";
output-high;
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index 4d4f37cebf21..b40c52ddf9b4 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -1,46 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Device Tree Source for Qualcomm MDM9615 SoC
*
* Copyright (C) 2016 BayLibre, SAS.
* Author : Neil Armstrong <narmstrong@baylibre.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -64,6 +27,7 @@
cpu0: cpu@0 {
compatible = "arm,cortex-a5";
+ reg = <0>;
device_type = "cpu";
next-level-cache = <&L2>;
};
@@ -115,13 +79,13 @@
};
timer@200a000 {
- compatible = "qcom,kpss-timer", "qcom,msm-timer";
+ compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer",
+ "qcom,msm-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
- clock-frequency = <27000000>,
- <32768>;
+ clock-frequency = <27000000>;
cpu-offset = <0x80000>;
};
@@ -152,7 +116,7 @@
};
l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc", "syscon";
+ compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
reg = <0x02011000 0x1000>;
};
@@ -206,7 +170,6 @@
#size-cells = <0>;
reg = <0x16280000 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <24000000>;
clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
clock-names = "core", "iface";
@@ -283,7 +246,7 @@
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
- pmicintc: pmic@0 {
+ pmicintc: pmic {
compatible = "qcom,pm8018", "qcom,pm8921";
interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
@@ -321,6 +284,7 @@
pmicgpio: gpio@150 {
compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
+ reg = <0x150>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
@@ -330,7 +294,7 @@
};
};
- sdcc1bam: dma@12182000{
+ sdcc1bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -340,7 +304,7 @@
qcom,ee = <0>;
};
- sdcc2bam: dma@12142000{
+ sdcc2bam: dma-controller@12142000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12142000 0x8000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -350,51 +314,43 @@
qcom,ee = <0>;
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- sdcc1: mmc@12180000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- reg = <0x12180000 0x2000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <48000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- vmmc-supply = <&vsdcc_fixed>;
- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
- dma-names = "tx", "rx";
- assigned-clocks = <&gcc SDC1_CLK>;
- assigned-clock-rates = <400000>;
- };
+ sdcc1: mmc@12180000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <48000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+ dma-names = "tx", "rx";
+ assigned-clocks = <&gcc SDC1_CLK>;
+ assigned-clock-rates = <400000>;
+ };
- sdcc2: mmc@12140000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12140000 0x2000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <48000000>;
- no-1-8-v;
- vmmc-supply = <&vsdcc_fixed>;
- dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
- dma-names = "tx", "rx";
- assigned-clocks = <&gcc SDC2_CLK>;
- assigned-clock-rates = <400000>;
- };
+ sdcc2: mmc@12140000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12140000 0x2000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <48000000>;
+ no-1-8-v;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
+ dma-names = "tx", "rx";
+ assigned-clocks = <&gcc SDC2_CLK>;
+ assigned-clock-rates = <400000>;
};
tcsr: syscon@1a400000 {
@@ -411,7 +367,7 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ interrupt-names = "ack", "err", "wakeup";
regulators {
compatible = "qcom,rpm-pm8018-regulators";
diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
index d159188c8b95..288cacd5d1fa 100644
--- a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
+++ b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
@@ -8,6 +8,7 @@
/ {
model = "Samsung Galaxy S III Neo";
compatible = "samsung,s3ve3g", "qcom,msm8226";
+ chassis-type = "handset";
aliases {
serial0 = &blsp1_uart3;
@@ -18,8 +19,6 @@
};
};
-&soc {
- serial@f991f000 {
- status = "ok";
- };
+&blsp1_uart3 {
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
index 85e56992d2d0..42acb9ddb8cc 100644
--- a/arch/arm/boot/dts/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -7,7 +7,10 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
/ {
@@ -44,13 +47,6 @@
};
};
- tcsr_mutex: hwlock {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_block 0 0x80>;
-
- #hwlock-cells = <1>;
- };
-
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
@@ -60,6 +56,11 @@
reg = <0x3000000 0x100000>;
no-map;
};
+
+ adsp_region: adsp@dc00000 {
+ reg = <0x0dc00000 0x1900000>;
+ no-map;
+ };
};
smd {
@@ -74,6 +75,13 @@
compatible = "qcom,rpm-msm8226";
qcom,smd-channels = "rpm_requests";
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
rpmpd: power-controller {
compatible = "qcom,msm8226-rpmpd";
#power-domain-cells = <1>;
@@ -115,6 +123,31 @@
hwlocks = <&tcsr_mutex 3>;
};
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -134,54 +167,63 @@
reg = <0xf9011000 0x1000>;
};
- sdhc_1: sdhci@f9824900 {
+ sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc1_default_state>;
status = "disabled";
};
- sdhc_2: sdhci@f98a4900 {
+ sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc2_default_state>;
status = "disabled";
};
- sdhc_3: sdhci@f9864900 {
+ sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC3_APPS_CLK>,
- <&gcc GCC_SDCC3_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC3_AHB_CLK>,
+ <&gcc GCC_SDCC3_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
pinctrl-names = "default";
pinctrl-0 = <&sdhc3_default_state>;
status = "disabled";
};
+ blsp1_uart1: serial@f991d000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991d000 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_uart3: serial@f991f000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991f000 0x1000>;
@@ -265,6 +307,33 @@
#size-cells = <0>;
};
+ cci: cci@fda0c000 {
+ compatible = "qcom,msm8226-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfda0c000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci_default>;
+ pinctrl-1 = <&cci_sleep>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usb: usb@f9a55000 {
compatible = "qcom,ci-hdrc";
reg = <0xf9a55000 0x200>,
@@ -309,6 +378,19 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>;
+ clock-names = "xo",
+ "sleep_clk";
+ };
+
+ mmcc: clock-controller@fd8c0000 {
+ compatible = "qcom,mmcc-msm8226";
+ reg = <0xfd8c0000 0x6000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
};
tlmm: pinctrl@fd510000 {
@@ -321,49 +403,65 @@
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- blsp1_i2c1_pins: blsp1-i2c1 {
+ blsp1_i2c1_pins: blsp1-i2c1-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c2_pins: blsp1-i2c2 {
+ blsp1_i2c2_pins: blsp1-i2c2-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c3_pins: blsp1-i2c3 {
+ blsp1_i2c3_pins: blsp1-i2c3-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c4_pins: blsp1-i2c4 {
+ blsp1_i2c4_pins: blsp1-i2c4-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c5_pins: blsp1-i2c5 {
+ blsp1_i2c5_pins: blsp1-i2c5-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
+ cci_default: cci-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c0";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci_sleep: cci-sleep-state {
+ pins = "gpio29", "gpio30";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdhc1_default_state: sdhc1-default-state {
- clk {
+ clk-pins {
pins = "sdc1_clk";
drive-strength = <10>;
bias-disable;
};
- cmd-data {
+ cmd-data-pins {
pins = "sdc1_cmd", "sdc1_data";
drive-strength = <10>;
bias-pull-up;
@@ -371,13 +469,13 @@
};
sdhc2_default_state: sdhc2-default-state {
- clk {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <10>;
bias-disable;
};
- cmd-data {
+ cmd-data-pins {
pins = "sdc2_cmd", "sdc2_data";
drive-strength = <10>;
bias-pull-up;
@@ -385,21 +483,21 @@
};
sdhc3_default_state: sdhc3-default-state {
- clk {
+ clk-pins {
pins = "gpio44";
function = "sdc3";
drive-strength = <8>;
bias-disable;
};
- cmd {
+ cmd-pins {
pins = "gpio43";
function = "sdc3";
drive-strength = <8>;
bias-pull-up;
};
- data {
+ data-pins {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "sdc3";
drive-strength = <8>;
@@ -494,14 +592,49 @@
};
};
- rpm_msg_ram: memory@fc428000 {
+ rpm_msg_ram: sram@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
- tcsr_mutex_block: syscon@fd484000 {
- compatible = "syscon";
- reg = <0xfd484000 0x2000>;
+ tcsr_mutex: hwlock@fd484000 {
+ compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
+ reg = <0xfd484000 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ adsp: remoteproc@fe200000 {
+ compatible = "qcom,msm8226-adsp-pil";
+ reg = <0xfe200000 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ power-domains = <&rpmpd MSM8226_VDDCX>;
+ power-domain-names = "cx";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ memory-region = <&adsp_region>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ smd-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 8>;
+ qcom,smd-edge = <1>;
+
+ label = "lpass";
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 414280d9bdba..be18f1be29a1 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -15,38 +15,23 @@
stdout-path = "serial0:115200n8";
};
- soc {
- gsbi@19c00000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
- serial@19c40000 {
- status = "okay";
- };
- };
-
- /* Temporary fixed regulator */
- vsdcc_fixed: vsdcc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "SDCC Power";
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- regulator-always-on;
- };
+ /* Temporary fixed regulator */
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-always-on;
+ };
+};
- amba {
- /* eMMC */
- sdcc1: mmc@12400000 {
- status = "okay";
- vmmc-supply = <&vsdcc_fixed>;
- };
+&gsbi12 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
- /* External micro SD card */
- sdcc3: mmc@12180000 {
- status = "okay";
- vmmc-supply = <&vsdcc_fixed>;
- };
- };
- };
+&gsbi12_serial {
+ status = "okay";
};
&pm8058 {
@@ -76,3 +61,15 @@
keypad,num-columns = <5>;
};
};
+
+/* eMMC */
+&sdcc1 {
+ vmmc-supply = <&vsdcc_fixed>;
+ status = "okay";
+};
+
+/* External micro SD card */
+&sdcc3 {
+ vmmc-supply = <&vsdcc_fixed>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index a258abb23a64..f601b40ebcf4 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -50,22 +50,25 @@
};
clocks {
- cxo_board {
+ cxo_board: cxo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
+ clock-output-names = "cxo_board";
};
- pxo_board {
+ pxo_board: pxo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
+ clock-output-names = "pxo_board";
};
- sleep_clk {
+ sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
+ clock-output-names = "sleep_clk";
};
};
@@ -129,6 +132,59 @@
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
+ clocks = <&pxo_board>, <&cxo_board>;
+ clock-names = "pxo", "cxo";
+ };
+
+ gsbi1: gsbi@16000000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <12>;
+ reg = <0x16000000 0x100>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi1_spi: spi@16080000 {
+ compatible = "qcom,spi-qup-v1.1.1";
+ reg = <0x16080000 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ gsbi3: gsbi@16200000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <12>;
+ reg = <0x16200000 0x100>;
+ clocks = <&gcc GSBI3_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+ status = "disabled";
+
+ gsbi3_i2c: i2c@16280000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16280000 0x1000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
gsbi6: gsbi@16500000 {
@@ -212,6 +268,7 @@
ranges;
syscon-tcsr = <&tcsr>;
+ status = "disabled";
gsbi8_i2c: i2c@19880000 {
compatible = "qcom,i2c-qup-v1.1.1";
@@ -259,7 +316,7 @@
};
};
- external-bus@1a100000 {
+ ebi2: external-bus@1a100000 {
compatible = "qcom,msm8660-ebi2";
#address-cells = <2>;
#size-cells = <1>;
@@ -276,12 +333,12 @@
status = "disabled";
};
- qcom,ssbi@500000 {
+ ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
- pm8058: pmic@0 {
+ pm8058: pmic {
compatible = "qcom,pm8058";
interrupt-parent = <&tlmm>;
interrupts = <88 8>;
@@ -322,7 +379,7 @@
pull-up;
};
- keypad@148 {
+ pm8058_keypad: keypad@148 {
compatible = "qcom,pm8058-keypad";
reg = <0x148>;
interrupt-parent = <&pm8058>;
@@ -387,32 +444,59 @@
compatible = "qcom,pm8058-vib";
reg = <0x4a>;
};
+
+ pm8058_led48: led@48 {
+ compatible = "qcom,pm8058-keypad-led";
+ reg = <0x48>;
+ status = "disabled";
+ };
+
+ pm8058_led131: led@131 {
+ compatible = "qcom,pm8058-led";
+ reg = <0x131>;
+ status = "disabled";
+ };
+
+ pm8058_led132: led@132 {
+ compatible = "qcom,pm8058-led";
+ reg = <0x132>;
+ status = "disabled";
+ };
+
+ pm8058_led133: led@133 {
+ compatible = "qcom,pm8058-led";
+ reg = <0x133>;
+ status = "disabled";
+ };
+
};
};
l2cc: clock-controller@2082000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x02082000 0x1000>;
+ compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
+ reg = <0x02082000 0x1000>;
};
rpm: rpm@104000 {
- compatible = "qcom,rpm-msm8660";
- reg = <0x00104000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
-
- interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ compatible = "qcom,rpm-msm8660";
+ reg = <0x00104000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
rpmcc: clock-controller {
- compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
+ compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
#clock-cells = <1>;
+ clocks = <&pxo_board>;
+ clock-names = "pxo";
};
- pm8901-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8901-regulators";
pm8901_l0: l0 {};
@@ -436,7 +520,7 @@
pm8901_mvs: mvs {};
};
- pm8058-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pm8058-regulators";
pm8058_l0: l0 {};
@@ -485,80 +569,75 @@
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x8000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <48000000>;
+ reg = <0x12400000 0x8000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <48000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc2: mmc@12140000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- reg = <0x12140000 0x8000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <48000000>;
+ reg = <0x12140000 0x8000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <48000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x8000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
+ status = "disabled";
+ reg = <0x12180000 0x8000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <48000000>;
+ max-frequency = <48000000>;
no-1-8-v;
};
sdcc4: mmc@121c0000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x121c0000 0x8000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
- max-frequency = <48000000>;
+ status = "disabled";
+ reg = <0x121c0000 0x8000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ max-frequency = <48000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc5: mmc@12200000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12200000 0x8000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
+ status = "disabled";
+ reg = <0x12200000 0x8000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <48000000>;
+ max-frequency = <48000000>;
};
};
diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts
new file mode 100644
index 000000000000..c8d34de8a71e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "arm64/qcom/msm8916-samsung-e5.dts"
+#include "qcom-msm8916-smp.dtsi"
diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts
new file mode 100644
index 000000000000..85be286c8608
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "arm64/qcom/msm8916-samsung-e7.dts"
+#include "qcom-msm8916-smp.dtsi"
diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts
new file mode 100644
index 000000000000..d3abe0536238
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "arm64/qcom/msm8916-samsung-grandmax.dts"
+#include "qcom-msm8916-smp.dtsi"
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index d1fd0fe12ffe..8fa2befa629a 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -15,322 +15,10 @@
stdout-path = "serial0:115200n8";
};
- soc {
- gsbi@16400000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
- serial@16440000 {
- status = "okay";
- };
- };
-
- amba {
- /* eMMC */
- sdcc1: mmc@12400000 {
- status = "okay";
- };
-
- /* External micro SD card */
- sdcc3: mmc@12180000 {
- status = "okay";
- };
- };
-
- rpm@108000 {
- regulators {
- compatible = "qcom,rpm-pm8921-regulators";
- vin_lvs1_3_6-supply = <&pm8921_s4>;
- vin_lvs2-supply = <&pm8921_s4>;
- vin_lvs4_5_7-supply = <&pm8921_s4>;
- vdd_ncp-supply = <&pm8921_l6>;
- vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
- vdd_l21_l23_l29-supply = <&pm8921_s8>;
- vdd_l24-supply = <&pm8921_s1>;
- vdd_l25-supply = <&pm8921_s1>;
- vdd_l27-supply = <&pm8921_s7>;
- vdd_l28-supply = <&pm8921_s7>;
-
- /* Buck SMPS */
- pm8921_s1: s1 {
- regulator-always-on;
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- qcom,switch-mode-frequency = <3200000>;
- bias-pull-down;
- };
-
- pm8921_s2: s2 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- pm8921_s3: s3 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1150000>;
- qcom,switch-mode-frequency = <4800000>;
- bias-pull-down;
- };
-
- pm8921_s4: s4 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>;
- };
-
- pm8921_s7: s7 {
- regulator-min-microvolt = <1150000>;
- regulator-max-microvolt = <1150000>;
- qcom,switch-mode-frequency = <3200000>;
- bias-pull-down;
- };
-
- pm8921_s8: s8 {
- regulator-always-on;
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- /* PMOS LDO */
- pm8921_l1: l1 {
- regulator-always-on;
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- bias-pull-down;
- };
-
- pm8921_l2: l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
-
- pm8921_l3: l3 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
- bias-pull-down;
- };
-
- pm8921_l4: l4 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- pm8921_l5: l5 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- pm8921_l6: l6 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- pm8921_l7: l7 {
- regulator-always-on;
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- pm8921_l8: l8 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- };
-
- pm8921_l9: l9 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- };
-
- pm8921_l10: l10 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- bias-pull-down;
- };
-
- pm8921_l11: l11 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
-
- pm8921_l12: l12 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
-
- pm8921_l14: l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- pm8921_l15: l15 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- pm8921_l16: l16 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- bias-pull-down;
- };
-
- pm8921_l17: l17 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- pm8921_l18: l18 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- bias-pull-down;
- };
-
- pm8921_l21: l21 {
- regulator-min-microvolt = <1900000>;
- regulator-max-microvolt = <1900000>;
- bias-pull-down;
- };
-
- pm8921_l22: l22 {
- regulator-min-microvolt = <2750000>;
- regulator-max-microvolt = <2750000>;
- bias-pull-down;
- };
-
- pm8921_l23: l23 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- pm8921_l24: l24 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1150000>;
- bias-pull-down;
- };
-
- pm8921_l25: l25 {
- regulator-always-on;
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <1250000>;
- bias-pull-down;
- };
-
- /* Low Voltage Switch */
- pm8921_lvs1: lvs1 {
- bias-pull-down;
- };
-
- pm8921_lvs2: lvs2 {
- bias-pull-down;
- };
-
- pm8921_lvs3: lvs3 {
- bias-pull-down;
- };
-
- pm8921_lvs4: lvs4 {
- bias-pull-down;
- };
-
- pm8921_lvs5: lvs5 {
- bias-pull-down;
- };
-
- pm8921_lvs6: lvs6 {
- bias-pull-down;
- };
-
- pm8921_lvs7: lvs7 {
- bias-pull-down;
- };
-
- pm8921_ncp: ncp {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <1600000>;
- };
- };
- };
-
- gsbi@16000000 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_default>;
- spi@16080000 {
- status = "okay";
- ethernet@0 {
- compatible = "micrel,ks8851";
- reg = <0>;
- interrupt-parent = <&msmgpio>;
- interrupts = <90 8>;
- spi-max-frequency = <5400000>;
- vdd-supply = <&ext_l2>;
- vdd-io-supply = <&pm8921_lvs6>;
- reset-gpios = <&msmgpio 89 0>;
- };
- };
- };
-
- pinctrl@800000 {
- spi1_default: spi1_default {
- mux {
- pins = "gpio6", "gpio7", "gpio9";
- function = "gsbi1";
- };
-
- mosi {
- pins = "gpio6";
- drive-strength = <12>;
- bias-disable;
- };
-
- miso {
- pins = "gpio7";
- drive-strength = <12>;
- bias-disable;
- };
-
- cs {
- pins = "gpio8";
- drive-strength = <12>;
- bias-disable;
- output-low;
- };
-
- clk {
- pins = "gpio9";
- drive-strength = <12>;
- bias-disable;
- };
- };
- };
- };
-
regulators {
compatible = "simple-bus";
- ext_l2: gpio-regulator@91 {
+ ext_l2: gpio-regulator {
compatible = "regulator-fixed";
regulator-name = "ext_l2";
gpio = <&msmgpio 91 0>;
@@ -340,6 +28,70 @@
};
};
+&gsbi1 {
+ qcom,mode = <GSBI_PROT_SPI>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_default>;
+ status = "okay";
+};
+
+&gsbi1_spi {
+ status = "okay";
+
+ ethernet@0 {
+ compatible = "micrel,ks8851";
+ reg = <0>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <90 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <5400000>;
+ vdd-supply = <&ext_l2>;
+ vdd-io-supply = <&pm8921_lvs6>;
+ reset-gpios = <&msmgpio 89 0>;
+ };
+};
+
+&gsbi5 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+};
+
+&gsbi5_serial {
+ status = "okay";
+};
+
+&msmgpio {
+ spi1_default: spi1-default-state {
+ mosi-pins {
+ pins = "gpio6";
+ function = "gsbi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ miso-pins {
+ pins = "gpio7";
+ function = "gsbi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio8";
+ function = "gsbi1";
+ drive-strength = <12>;
+ bias-disable;
+ output-low;
+ };
+
+ clk-pins {
+ pins = "gpio9";
+ function = "gsbi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
+};
+
&pmicintc {
keypad@148 {
linux,keymap = <
@@ -352,3 +104,249 @@
keypad,num-columns = <5>;
};
};
+
+&rpm {
+ regulators {
+ compatible = "qcom,rpm-pm8921-regulators";
+ vin_lvs1_3_6-supply = <&pm8921_s4>;
+ vin_lvs2-supply = <&pm8921_s4>;
+ vin_lvs4_5_7-supply = <&pm8921_s4>;
+ vdd_ncp-supply = <&pm8921_l6>;
+ vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
+ vdd_l21_l23_l29-supply = <&pm8921_s8>;
+ vdd_l24-supply = <&pm8921_s1>;
+ vdd_l25-supply = <&pm8921_s1>;
+ vdd_l27-supply = <&pm8921_s7>;
+ vdd_l28-supply = <&pm8921_s7>;
+
+ /* Buck SMPS */
+ pm8921_s1: s1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ qcom,switch-mode-frequency = <3200000>;
+ bias-pull-down;
+ };
+
+ pm8921_s2: s2 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8921_s3: s3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,switch-mode-frequency = <4800000>;
+ bias-pull-down;
+ };
+
+ pm8921_s4: s4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>;
+ };
+
+ pm8921_s7: s7 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,switch-mode-frequency = <3200000>;
+ bias-pull-down;
+ };
+
+ pm8921_s8: s8 {
+ regulator-always-on;
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ /* PMOS LDO */
+ pm8921_l1: l1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ pm8921_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+
+ pm8921_l3: l3 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ bias-pull-down;
+ };
+
+ pm8921_l4: l4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ pm8921_l5: l5 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ pm8921_l6: l6 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ pm8921_l7: l7 {
+ regulator-always-on;
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ pm8921_l8: l8 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
+ };
+
+ pm8921_l9: l9 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
+ };
+
+ pm8921_l10: l10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ bias-pull-down;
+ };
+
+ pm8921_l11: l11 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+
+ pm8921_l12: l12 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+
+ pm8921_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ pm8921_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ pm8921_l16: l16 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ bias-pull-down;
+ };
+
+ pm8921_l17: l17 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ pm8921_l18: l18 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ bias-pull-down;
+ };
+
+ pm8921_l21: l21 {
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <1900000>;
+ bias-pull-down;
+ };
+
+ pm8921_l22: l22 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ bias-pull-down;
+ };
+
+ pm8921_l23: l23 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ pm8921_l24: l24 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1150000>;
+ bias-pull-down;
+ };
+
+ pm8921_l25: l25 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ bias-pull-down;
+ };
+
+ /* Low Voltage Switch */
+ pm8921_lvs1: lvs1 {
+ bias-pull-down;
+ };
+
+ pm8921_lvs2: lvs2 {
+ bias-pull-down;
+ };
+
+ pm8921_lvs3: lvs3 {
+ bias-pull-down;
+ };
+
+ pm8921_lvs4: lvs4 {
+ bias-pull-down;
+ };
+
+ pm8921_lvs5: lvs5 {
+ bias-pull-down;
+ };
+
+ pm8921_lvs6: lvs6 {
+ bias-pull-down;
+ };
+
+ pm8921_lvs7: lvs7 {
+ bias-pull-down;
+ };
+
+ pm8921_ncp: ncp {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ };
+ };
+};
+
+/* eMMC */
+&sdcc1 {
+ status = "okay";
+};
+
+/* External micro SD card */
+&sdcc3 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 4a2d74cf01d2..2a668cd535cc 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>
@@ -16,7 +17,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <1 14 0x304>;
+ interrupts = <GIC_PPI 14 0x304>;
cpu@0 {
compatible = "qcom,krait";
@@ -51,19 +52,19 @@
cpu-pmu {
compatible = "qcom,krait-pmu";
- interrupts = <1 10 0x304>;
+ interrupts = <GIC_PPI 10 0x304>;
qcom,no-pc-write;
};
clocks {
- cxo_board {
+ cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "cxo_board";
};
- pxo_board {
+ pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
@@ -102,14 +103,13 @@
};
timer@200a000 {
- compatible = "qcom,kpss-timer",
- "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
- interrupts = <1 1 0x301>,
- <1 2 0x301>,
- <1 3 0x301>;
+ compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
+ "qcom,msm-timer";
+ interrupts = <GIC_PPI 1 0x301>,
+ <GIC_PPI 2 0x301>,
+ <GIC_PPI 3 0x301>;
reg = <0x0200a000 0x100>;
- clock-frequency = <27000000>,
- <32768>;
+ clock-frequency = <27000000>;
cpu-offset = <0x80000>;
};
@@ -118,7 +118,7 @@
gpio-controller;
gpio-ranges = <&msmgpio 0 0 152>;
#gpio-cells = <2>;
- interrupts = <0 16 0x4>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x800000 0x4000>;
@@ -130,6 +130,10 @@
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
+ clocks = <&cxo_board>,
+ <&pxo_board>,
+ <&lcc PLL4>;
+ clock-names = "cxo", "pxo", "pll4";
};
lcc: clock-controller@28000000 {
@@ -137,6 +141,20 @@
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ clocks = <&pxo_board>,
+ <&gcc PLL4_VOTE>,
+ <0>,
+ <0>, <0>,
+ <0>, <0>,
+ <0>;
+ clock-names = "pxo",
+ "pll4_vote",
+ "mi2s_codec_clk",
+ "codec_i2s_mic_codec_clk",
+ "spare_i2s_mic_codec_clk",
+ "codec_i2s_spkr_codec_clk",
+ "spare_i2s_spkr_codec_clk",
+ "pcm_codec_clk";
};
clock-controller@4000000 {
@@ -145,22 +163,41 @@
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
+ clocks = <&pxo_board>,
+ <&gcc PLL3>,
+ <&gcc PLL8_VOTE>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "pxo",
+ "pll3",
+ "pll8_vote",
+ "dsi1pll",
+ "dsi1pllbyte",
+ "dsi2pll",
+ "dsi2pllbyte",
+ "hdmipll";
};
l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x2011000 0x1000>;
+ compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
};
- rpm@108000 {
- compatible = "qcom,rpm-msm8960";
- reg = <0x108000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-msm8960";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
regulators {
compatible = "qcom,rpm-pm8921-regulators";
@@ -170,11 +207,19 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
+ #clock-cells = <0>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu1_aux";
+ #clock-cells = <0>;
};
saw0: regulator@2089000 {
@@ -212,15 +257,15 @@
};
};
- qcom,ssbi@500000 {
+ ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
- pmicintc: pmic@0 {
+ pmicintc: pmic {
compatible = "qcom,pm8921";
interrupt-parent = <&msmgpio>;
- interrupts = <104 8>;
+ interrupts = <104 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <2>;
interrupt-controller;
#address-cells = <1>;
@@ -230,7 +275,8 @@
compatible = "qcom,pm8921-pwrkey";
reg = <0x1c>;
interrupt-parent = <&pmicintc>;
- interrupts = <50 1>, <51 1>;
+ interrupts = <50 IRQ_TYPE_EDGE_RISING>,
+ <51 IRQ_TYPE_EDGE_RISING>;
debounce = <15625>;
pull-up;
};
@@ -239,7 +285,8 @@
compatible = "qcom,pm8921-keypad";
reg = <0x148>;
interrupt-parent = <&pmicintc>;
- interrupts = <74 1>, <75 1>;
+ interrupts = <74 IRQ_TYPE_EDGE_RISING>,
+ <75 IRQ_TYPE_EDGE_RISING>;
debounce = <15>;
scan-delay = <32>;
row-hold = <91500>;
@@ -248,7 +295,7 @@
rtc@11d {
compatible = "qcom,pm8921-rtc";
interrupt-parent = <&pmicintc>;
- interrupts = <39 1>;
+ interrupts = <39 IRQ_TYPE_EDGE_RISING>;
reg = <0x11d>;
allow-set-time;
};
@@ -262,44 +309,36 @@
clock-names = "core";
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x8000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <96000000>;
- non-removable;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- vmmc-supply = <&vsdcc_fixed>;
- };
+ sdcc3: mmc@12180000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12180000 0x8000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <192000000>;
+ no-1-8-v;
+ vmmc-supply = <&vsdcc_fixed>;
+ };
- sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x8000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <192000000>;
- no-1-8-v;
- vmmc-supply = <&vsdcc_fixed>;
- };
+ sdcc1: mmc@12400000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ reg = <0x12400000 0x8000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
+ non-removable;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ vmmc-supply = <&vsdcc_fixed>;
};
tcsr: syscon@1a400000 {
@@ -307,7 +346,7 @@
reg = <0x1a400000 0x100>;
};
- gsbi@16000000 {
+ gsbi1: gsbi@16000000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <1>;
reg = <0x16000000 0x100>;
@@ -317,7 +356,7 @@
#size-cells = <1>;
ranges;
- spi@16080000 {
+ gsbi1_spi: spi@16080000 {
compatible = "qcom,spi-qup-v1.1.1";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
deleted file mode 100644
index 6d77e0f8ca4d..000000000000
--- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
+++ /dev/null
@@ -1,409 +0,0 @@
-#include "qcom-msm8974.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-
-
-/ {
- model = "Fairphone 2";
- compatible = "fairphone,fp2", "qcom,msm8974";
-
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pin_a>;
-
- camera-snapshot {
- label = "camera_snapshot";
- gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_CAMERA>;
- wakeup-source;
- debounce-interval = <15>;
- };
-
- volume-down {
- label = "volume_down";
- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- wakeup-source;
- debounce-interval = <15>;
- };
-
- volume-up {
- label = "volume_up";
- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- wakeup-source;
- debounce-interval = <15>;
- };
- };
-
- vibrator {
- compatible = "gpio-vibrator";
- enable-gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>;
- vcc-supply = <&pm8941_l18>;
- };
-
- smd {
- rpm {
- rpm_requests {
- pm8841-regulators {
- s1 {
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s3 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
- };
-
- pm8941-regulators {
- vdd_l1_l3-supply = <&pm8941_s1>;
- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
- vdd_l4_l11-supply = <&pm8941_s1>;
- vdd_l5_l7-supply = <&pm8941_s2>;
- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
- vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
- vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
- vdd_l21-supply = <&vreg_boost>;
-
- s1 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- s2 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
-
- regulator-boot-on;
- };
-
- s3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l3 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l10 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l11 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1350000>;
- };
-
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l15 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l17 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l18 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l19 {
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <3350000>;
- };
-
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- regulator-system-load = <200000>;
- regulator-allow-set-load;
- };
-
- l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l22 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- };
-
- l23 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
-
- regulator-boot-on;
- };
- };
- };
- };
- };
-};
-
-&soc {
- serial@f991e000 {
- status = "okay";
- };
-
- remoteproc@fb21b000 {
- status = "okay";
-
- vddmx-supply = <&pm8841_s1>;
- vddcx-supply = <&pm8841_s2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&wcnss_pin_a>;
-
- smd-edge {
- qcom,remote-pid = <4>;
- label = "pronto";
-
- wcnss {
- status = "okay";
- };
- };
- };
-
- pinctrl@fd510000 {
- sdhc1_pin_a: sdhc1-pin-active {
- clk {
- pins = "sdc1_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc2_pin_a: sdhc2-pin-active {
- clk {
- pins = "sdc2_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <6>;
- bias-pull-up;
- };
- };
-
- wcnss_pin_a: wcnss-pin-active {
- wlan {
- pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
- function = "wlan";
-
- drive-strength = <6>;
- bias-pull-down;
- };
-
- bt {
- pins = "gpio35", "gpio43", "gpio44";
- function = "bt";
-
- drive-strength = <2>;
- bias-pull-down;
- };
-
- fm {
- pins = "gpio41", "gpio42";
- function = "fm";
-
- drive-strength = <2>;
- bias-pull-down;
- };
- };
- };
-
- sdhci@f9824900 {
- status = "okay";
-
- vmmc-supply = <&pm8941_l20>;
- vqmmc-supply = <&pm8941_s3>;
-
- bus-width = <8>;
- non-removable;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_pin_a>;
- };
-
- sdhci@f98a4900 {
- status = "okay";
-
- vmmc-supply = <&pm8941_l21>;
- vqmmc-supply = <&pm8941_l13>;
-
- bus-width = <4>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a>;
- };
-
- usb@f9a55000 {
- status = "okay";
-
- phys = <&usb_hs1_phy>;
- phy-select = <&tcsr 0xb000 0>;
- extcon = <&smbb>, <&usb_id>;
- vbus-supply = <&chg_otg>;
-
- hnp-disable;
- srp-disable;
- adp-disable;
-
- ulpi {
- phy@a {
- status = "okay";
-
- v1p8-supply = <&pm8941_l6>;
- v3p3-supply = <&pm8941_l24>;
-
- extcon = <&smbb>;
- qcom,init-seq = /bits/ 8 <0x1 0x64>;
- };
- };
- };
-
- imem@fe805000 {
- status = "okay";
-
- reboot-mode {
- mode-normal = <0x77665501>;
- mode-bootloader = <0x77665500>;
- mode-recovery = <0x77665502>;
- };
- };
-};
-
-&spmi_bus {
- pm8941@0 {
- gpios@c000 {
- gpio_keys_pin_a: gpio-keys-active {
- pins = "gpio1", "gpio2", "gpio5";
- function = "normal";
-
- bias-pull-up;
- power-source = <PM8941_GPIO_S3>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index 069136170198..ab35f2d644c0 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -2,223 +2,42 @@
#include "qcom-msm8974.dtsi"
#include "qcom-pm8841.dtsi"
#include "qcom-pm8941.dtsi"
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "LGE MSM 8974 HAMMERHEAD";
compatible = "lge,hammerhead", "qcom,msm8974";
+ chassis-type = "handset";
aliases {
serial0 = &blsp1_uart1;
- serial1 = &blsp2_uart10;
+ serial1 = &blsp2_uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
- smd {
- rpm {
- rpm_requests {
- pm8841-regulators {
- s1 {
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s3 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s4 {
- regulator-min-microvolt = <815000>;
- regulator-max-microvolt = <900000>;
- };
- };
-
- pm8941-regulators {
- vdd_l1_l3-supply = <&pm8941_s1>;
- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
- vdd_l4_l11-supply = <&pm8941_s1>;
- vdd_l5_l7-supply = <&pm8941_s2>;
- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
- vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>;
- vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
- vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
- vdd_l21-supply = <&vreg_boost>;
-
- s1 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- s2 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
-
- regulator-boot-on;
- };
-
- s3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l3 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l10 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l11 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l15 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l17 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l18 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l19 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- };
-
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- regulator-system-load = <200000>;
- regulator-allow-set-load;
- };
-
- l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l22 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- };
-
- l23 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
-
- regulator-boot-on;
- };
- };
- };
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ key-volume-down {
+ label = "volume_down";
+ gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
};
};
@@ -229,7 +48,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>;
+ gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
@@ -237,525 +56,608 @@
};
};
-&soc {
- serial@f991d000 {
- status = "okay";
+&blsp1_i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ charger: bq24192@6b {
+ compatible = "ti,bq24192";
+ reg = <0x6b>;
+ interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>;
+
+ omit-battery-class;
+
+ usb_otg_vbus: usb-otg-vbus { };
};
- pinctrl@fd510000 {
- sdhc1_pin_a: sdhc1-pin-active {
- clk {
- pins = "sdc1_clk";
- drive-strength = <16>;
- bias-disable;
- };
+ fuelgauge: max17048@36 {
+ compatible = "maxim,max17048";
+ reg = <0x36>;
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
+ maxim,double-soc;
+ maxim,rcomp = /bits/ 8 <0x4d>;
- sdhc2_pin_a: sdhc2-pin-active {
- clk {
- pins = "sdc2_clk";
- drive-strength = <6>;
- bias-disable;
- };
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <6>;
- bias-pull-up;
- };
- };
+ pinctrl-names = "default";
+ pinctrl-0 = <&fuelgauge_pin>;
- i2c1_pins: i2c1 {
- mux {
- pins = "gpio2", "gpio3";
- function = "blsp_i2c1";
+ maxim,alert-low-soc-level = <2>;
+ };
+};
- drive-strength = <2>;
- bias-disable;
- };
- };
+&blsp1_i2c2 {
+ status = "okay";
+ clock-frequency = <355000>;
- i2c2_pins: i2c2 {
- mux {
- pins = "gpio6", "gpio7";
- function = "blsp_i2c2";
+ synaptics@70 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x70>;
- drive-strength = <2>;
- bias-disable;
- };
- };
+ interrupts-extended = <&tlmm 5 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8941_l22>;
+ vio-supply = <&pm8941_lvs3>;
- i2c3_pins: i2c3 {
- mux {
- pins = "gpio10", "gpio11";
- function = "blsp_i2c3";
- drive-strength = <2>;
- bias-disable;
- };
- };
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_pin>;
- i2c11_pins: i2c11 {
- mux {
- pins = "gpio83", "gpio84";
- function = "blsp_i2c11";
+ #address-cells = <1>;
+ #size-cells = <0>;
- drive-strength = <2>;
- bias-disable;
- };
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
};
- i2c12_pins: i2c12 {
- mux {
- pins = "gpio87", "gpio88";
- function = "blsp_i2c12";
- drive-strength = <2>;
- bias-disable;
- };
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
};
+ };
+};
- mpu6515_pin: mpu6515 {
- irq {
- pins = "gpio73";
- function = "gpio";
- bias-disable;
- input-enable;
- };
- };
+&blsp1_i2c3 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ avago_apds993@39 {
+ compatible = "avago,apds9930";
+ reg = <0x39>;
+ interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8941_l17>;
+ vddio-supply = <&pm8941_lvs1>;
+ led-max-microamp = <100000>;
+ amstaos,proximity-diodes = <0>;
+ };
+};
- touch_pin: touch {
- int {
- pins = "gpio5";
- function = "gpio";
+&blsp2_i2c5 {
+ status = "okay";
+ clock-frequency = <355000>;
- drive-strength = <2>;
- bias-disable;
- input-enable;
- };
+ led-controller@38 {
+ compatible = "ti,lm3630a";
+ status = "okay";
+ reg = <0x38>;
- reset {
- pins = "gpio8";
- function = "gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
- drive-strength = <2>;
- bias-pull-up;
- };
+ led@0 {
+ reg = <0>;
+ led-sources = <0 1>;
+ label = "lcd-backlight";
+ default-brightness = <200>;
};
+ };
+};
- panel_pin: panel {
- te {
- pins = "gpio12";
- function = "mdp_vsync";
+&blsp2_i2c6 {
+ status = "okay";
+ clock-frequency = <100000>;
- drive-strength = <2>;
- bias-disable;
- };
- };
+ mpu6515@68 {
+ compatible = "invensense,mpu6515";
+ reg = <0x68>;
+ interrupts-extended = <&tlmm 73 IRQ_TYPE_EDGE_FALLING>;
+ vddio-supply = <&pm8941_lvs1>;
- bt_pin: bt {
- hostwake {
- pins = "gpio42";
- function = "gpio";
- };
+ pinctrl-names = "default";
+ pinctrl-0 = <&mpu6515_pin>;
+
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
- devwake {
- pins = "gpio62";
- function = "gpio";
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ak8963@f {
+ compatible = "asahi-kasei,ak8963";
+ reg = <0x0f>;
+ gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+ vid-supply = <&pm8941_lvs1>;
+ vdd-supply = <&pm8941_l17>;
};
- shutdown {
- pins = "gpio41";
- function = "gpio";
+ bmp280@76 {
+ compatible = "bosch,bmp280";
+ reg = <0x76>;
+ vdda-supply = <&pm8941_lvs1>;
+ vddd-supply = <&pm8941_l17>;
};
};
+ };
+};
- blsp2_uart10_pin_a: blsp2-uart10-pin-active {
- tx {
- pins = "gpio53";
- function = "blsp_uart10";
+&blsp1_uart1 {
+ status = "okay";
+};
- drive-strength = <2>;
- bias-disable;
- };
+&blsp2_uart4 {
+ status = "okay";
- rx {
- pins = "gpio54";
- function = "blsp_uart10";
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
- drive-strength = <2>;
- bias-pull-up;
- };
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pin>;
+
+ host-wakeup-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>;
+ };
+};
- cts {
- pins = "gpio55";
- function = "blsp_uart10";
+&dsi0 {
+ status = "okay";
- drive-strength = <2>;
- bias-pull-up;
- };
+ vdda-supply = <&pm8941_l2>;
+ vdd-supply = <&pm8941_lvs3>;
+ vddio-supply = <&pm8941_l12>;
+
+ panel: panel@0 {
+ reg = <0>;
+ compatible = "lg,acx467akm-7";
- rts {
- pins = "gpio56";
- function = "blsp_uart10";
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_pin>;
- drive-strength = <2>;
- bias-disable;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
};
};
};
+};
- sdhci@f9824900 {
- status = "okay";
+&dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
- vmmc-supply = <&pm8941_l20>;
- vqmmc-supply = <&pm8941_s3>;
+&dsi0_phy {
+ status = "okay";
- bus-width = <8>;
- non-removable;
+ vddio-supply = <&pm8941_l12>;
+};
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_pin_a>;
+&mdss {
+ status = "okay";
+};
+
+&pm8941_gpios {
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio2", "gpio3";
+ function = "normal";
+
+ bias-pull-up;
+ power-source = <PM8941_GPIO_S3>;
};
- sdhci@f98a4900 {
- status = "okay";
+ fuelgauge_pin: fuelgauge-int-state {
+ pins = "gpio9";
+ function = "normal";
- max-frequency = <100000000>;
- bus-width = <4>;
- non-removable;
- vmmc-supply = <&vreg_wlan>;
- vqmmc-supply = <&pm8941_s3>;
+ bias-disable;
+ input-enable;
+ power-source = <PM8941_GPIO_S3>;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a>;
+ wlan_sleep_clk_pin: wl-sleep-clk-state {
+ pins = "gpio16";
+ function = "func2";
+
+ output-high;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ wlan_regulator_pin: wl-reg-active-state {
+ pins = "gpio17";
+ function = "normal";
+
+ bias-disable;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ otg {
+ gpio-hog;
+ gpios = <35 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "otg-gpio";
+ };
+};
+
+&pm8941_lpg {
+ status = "okay";
+
+ qcom,power-source = <1>;
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
- bcrmf@1 {
- compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac";
- reg = <1>;
+ led@7 {
+ reg = <7>;
+ color = <LED_COLOR_ID_RED>;
+ };
- brcm,drive-strength = <10>;
+ led@6 {
+ reg = <6>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_sleep_clk_pin>;
+ led@5 {
+ reg = <5>;
+ color = <LED_COLOR_ID_BLUE>;
};
};
+};
- gpio-keys {
- compatible = "gpio-keys";
+&remoteproc_adsp {
+ cx-supply = <&pm8841_s2>;
+};
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pin_a>;
+&remoteproc_mss {
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+};
- volume-up {
- label = "volume_up";
- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEUP>;
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
};
- volume-down {
- label = "volume_down";
- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEDOWN>;
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
};
- };
- serial@f9960000 {
- status = "okay";
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&blsp2_uart10_pin_a>;
+ pm8841_s4: s4 {
+ regulator-min-microvolt = <815000>;
+ regulator-max-microvolt = <900000>;
+ };
+ };
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <3000000>;
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ vdd_l1_l3-supply = <&pm8941_s1>;
+ vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+ vdd_l4_l11-supply = <&pm8941_s1>;
+ vdd_l5_l7-supply = <&pm8941_s2>;
+ vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+ vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>;
+ vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
+ vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
+ vdd_l21-supply = <&vreg_boost>;
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&bt_pin>;
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ regulator-boot-on;
+ };
- host-wakeup-gpios = <&msmgpio 42 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&msmgpio 62 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&msmgpio 41 GPIO_ACTIVE_HIGH>;
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
};
- };
- i2c@f9967000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c11_pins>;
- clock-frequency = <355000>;
- qcom,src-freq = <50000000>;
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- led-controller@38 {
- compatible = "ti,lm3630a";
- status = "okay";
- reg = <0x38>;
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
- #address-cells = <1>;
- #size-cells = <0>;
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
- led@0 {
- reg = <0>;
- led-sources = <0 1>;
- label = "lcd-backlight";
- default-brightness = <200>;
- };
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
};
- };
- i2c@f9968000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c12_pins>;
- clock-frequency = <100000>;
- qcom,src-freq = <50000000>;
-
- mpu6515@68 {
- compatible = "invensense,mpu6515";
- reg = <0x68>;
- interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>;
- vddio-supply = <&pm8941_lvs1>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&mpu6515_pin>;
-
- mount-matrix = "0", "-1", "0",
- "-1", "0", "0",
- "0", "0", "1";
-
- i2c-gate {
- #address-cells = <1>;
- #size-cells = <0>;
- ak8963@f {
- compatible = "asahi-kasei,ak8963";
- reg = <0x0f>;
- gpios = <&msmgpio 67 0>;
- vid-supply = <&pm8941_lvs1>;
- vdd-supply = <&pm8941_l17>;
- };
-
- bmp280@76 {
- compatible = "bosch,bmp280";
- reg = <0x76>;
- vdda-supply = <&pm8941_lvs1>;
- vddd-supply = <&pm8941_l17>;
- };
- };
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
- };
- i2c@f9923000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <100000>;
- qcom,src-freq = <50000000>;
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
- charger: bq24192@6b {
- compatible = "ti,bq24192";
- reg = <0x6b>;
- interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>;
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
- omit-battery-class;
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
- usb_otg_vbus: usb-otg-vbus { };
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
};
- fuelgauge: max17048@36 {
- compatible = "maxim,max17048";
- reg = <0x36>;
+ pm8941_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
- maxim,double-soc;
- maxim,rcomp = /bits/ 8 <0x4d>;
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
- interrupt-parent = <&msmgpio>;
- interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&fuelgauge_pin>;
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
- maxim,alert-low-soc-level = <2>;
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
- };
- i2c@f9924000 {
- status = "okay";
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
- clock-frequency = <355000>;
- qcom,src-freq = <50000000>;
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
- synaptics@70 {
- compatible = "syna,rmi4-i2c";
- reg = <0x70>;
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
- interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>;
- vdd-supply = <&pm8941_l22>;
- vio-supply = <&pm8941_lvs3>;
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&touch_pin>;
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
- #address-cells = <1>;
- #size-cells = <0>;
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
- rmi4-f01@1 {
- reg = <0x1>;
- syna,nosleep-mode = <1>;
- };
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
- rmi4-f12@12 {
- reg = <0x12>;
- syna,sensor-type = <1>;
- };
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
};
- };
- i2c@f9925000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <100000>;
- qcom,src-freq = <50000000>;
-
- avago_apds993@39 {
- compatible = "avago,apds9930";
- reg = <0x39>;
- interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
- vdd-supply = <&pm8941_l17>;
- vddio-supply = <&pm8941_lvs1>;
- led-max-microamp = <100000>;
- amstaos,proximity-diodes = <0>;
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ regulator-boot-on;
};
+
+ pm8941_lvs1: lvs1 {};
+ pm8941_lvs3: lvs3 {};
};
+};
- usb@f9a55000 {
- status = "okay";
+&sdhc_1 {
+ status = "okay";
- phys = <&usb_hs1_phy>;
- phy-select = <&tcsr 0xb000 0>;
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
- extcon = <&charger>, <&usb_id>;
- vbus-supply = <&usb_otg_vbus>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+};
- hnp-disable;
- srp-disable;
- adp-disable;
+&sdhc_2 {
+ status = "okay";
- ulpi {
- phy@a {
- status = "okay";
+ max-frequency = <100000000>;
+ vmmc-supply = <&vreg_wlan>;
+ vqmmc-supply = <&pm8941_s3>;
+ non-removable;
- v1p8-supply = <&pm8941_l6>;
- v3p3-supply = <&pm8941_l24>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_on>;
+ pinctrl-1 = <&sdc2_off>;
- qcom,init-seq = /bits/ 8 <0x1 0x64>;
- };
+ bcrmf@1 {
+ compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ brcm,drive-strength = <10>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_sleep_clk_pin>;
+ };
+};
+
+&tlmm {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
};
};
- mdss@fd900000 {
- status = "okay";
+ sdc2_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <6>;
+ bias-disable;
+ };
- mdp@fd900000 {
- status = "okay";
+ cmd-data-pins {
+ pins = "sdc2_cmd", "sdc2_data";
+ drive-strength = <6>;
+ bias-pull-up;
};
+ };
- dsi@fd922800 {
- status = "okay";
+ mpu6515_pin: mpu6515-state {
+ pins = "gpio73";
+ function = "gpio";
+ bias-disable;
+ input-enable;
+ };
- vdda-supply = <&pm8941_l2>;
- vdd-supply = <&pm8941_lvs3>;
- vddio-supply = <&pm8941_l12>;
+ touch_pin: touch-state {
+ int-pins {
+ pins = "gpio5";
+ function = "gpio";
- #address-cells = <1>;
- #size-cells = <0>;
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
- ports {
- port@1 {
- endpoint {
- remote-endpoint = <&panel_in>;
- data-lanes = <0 1 2 3>;
- };
- };
- };
+ reset-pins {
+ pins = "gpio8";
+ function = "gpio";
- panel: panel@0 {
- reg = <0>;
- compatible = "lg,acx467akm-7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
- pinctrl-names = "default";
- pinctrl-0 = <&panel_pin>;
+ panel_pin: panel-state {
+ pins = "gpio12";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-disable;
+ };
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
- };
+ bt_pin: bt-state {
+ hostwake-pins {
+ pins = "gpio42";
+ function = "gpio";
};
- dsi-phy@fd922a00 {
- status = "okay";
+ devwake-pins {
+ pins = "gpio62";
+ function = "gpio";
+ };
- vddio-supply = <&pm8941_l12>;
+ shutdown-pins {
+ pins = "gpio41";
+ function = "gpio";
};
};
};
-&spmi_bus {
- pm8941@0 {
- gpios@c000 {
- gpio_keys_pin_a: gpio-keys-active {
- pins = "gpio2", "gpio3";
- function = "normal";
-
- bias-pull-up;
- power-source = <PM8941_GPIO_S3>;
- };
-
- fuelgauge_pin: fuelgauge-int {
- pins = "gpio9";
- function = "normal";
+&usb {
+ status = "okay";
- bias-disable;
- input-enable;
- power-source = <PM8941_GPIO_S3>;
- };
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
- wlan_sleep_clk_pin: wl-sleep-clk {
- pins = "gpio16";
- function = "func2";
+ extcon = <&charger>, <&usb_id>;
+ vbus-supply = <&usb_otg_vbus>;
- output-high;
- power-source = <PM8941_GPIO_S3>;
- };
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+};
- wlan_regulator_pin: wl-reg-active {
- pins = "gpio17";
- function = "normal";
+&usb_hs1_phy {
+ status = "okay";
- bias-disable;
- power-source = <PM8941_GPIO_S3>;
- };
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
- otg {
- gpio-hog;
- gpios = <35 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "otg-gpio";
- };
- };
- };
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
};
diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
deleted file mode 100644
index 96e1c978b878..000000000000
--- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
+++ /dev/null
@@ -1,908 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "qcom-msm8974pro.dtsi"
-#include "qcom-pma8084.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Samsung Galaxy S5";
- compatible = "samsung,klte", "qcom,msm8974";
-
- aliases {
- serial0 = &blsp1_uart1;
- mmc0 = &sdhc_1; /* SDC1 eMMC slot */
- mmc1 = &sdhc_2; /* SDC2 SD card slot */
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- smd {
- rpm {
- rpm_requests {
- pma8084-regulators {
- compatible = "qcom,rpm-pma8084-regulators";
- status = "okay";
-
- pma8084_s1: s1 {
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- };
-
- pma8084_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- pma8084_s3: s3 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- pma8084_s4: s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pma8084_s5: s5 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
- };
-
- pma8084_s6: s6 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- };
-
- pma8084_l1: l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- pma8084_l2: l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- pma8084_l3: l3 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1200000>;
- };
-
- pma8084_l4: l4 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1225000>;
- };
-
- pma8084_l5: l5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pma8084_l6: l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pma8084_l7: l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pma8084_l8: l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pma8084_l9: l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- pma8084_l10: l10 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- pma8084_l11: l11 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- pma8084_l12: l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- pma8084_l13: l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- pma8084_l14: l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pma8084_l15: l15 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- pma8084_l16: l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- pma8084_l17: l17 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- pma8084_l18: l18 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- pma8084_l19: l19 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- pma8084_l20: l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-allow-set-load;
- regulator-system-load = <200000>;
- };
-
- pma8084_l21: l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-allow-set-load;
- regulator-system-load = <200000>;
- };
-
- pma8084_l22: l22 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- };
-
- pma8084_l23: l23 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- pma8084_l24: l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
- };
-
- pma8084_l25: l25 {
- regulator-min-microvolt = <2100000>;
- regulator-max-microvolt = <2100000>;
- };
-
- pma8084_l26: l26 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2050000>;
- };
-
- pma8084_l27: l27 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1225000>;
- };
-
- pma8084_lvs1: lvs1 {};
- pma8084_lvs2: lvs2 {};
- pma8084_lvs3: lvs3 {};
- pma8084_lvs4: lvs4 {};
-
- pma8084_5vs1: 5vs1 {};
- };
- };
- };
- };
-
- i2c-gpio-touchkey {
- compatible = "i2c-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- sda-gpios = <&msmgpio 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&msmgpio 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_touchkey_pins>;
-
- touchkey@20 {
- compatible = "cypress,tm2-touchkey";
- reg = <0x20>;
-
- interrupt-parent = <&pma8084_gpios>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&touchkey_pin>;
-
- vcc-supply = <&max77826_ldo15>;
- vdd-supply = <&pma8084_l19>;
-
- linux,keycodes = <KEY_APPSELECT KEY_BACK>;
- };
- };
-
- i2c-gpio-led {
- compatible = "i2c-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_led_gpioex_pins>;
-
- i2c-gpio,delay-us = <2>;
-
- gpio_expander: gpio@20 {
- compatible = "nxp,pcal6416";
- reg = <0x20>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- vcc-supply = <&pma8084_s4>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpioex_pin>;
-
- reset-gpios = <&msmgpio 145 GPIO_ACTIVE_LOW>;
- };
-
- led-controller@30 {
- compatible = "panasonic,an30259a";
- reg = <0x30>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@1 {
- reg = <1>;
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- };
-
- led@2 {
- reg = <2>;
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led@3 {
- reg = <3>;
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- };
- };
- };
-
- vreg_wlan: wlan-regulator {
- compatible = "regulator-fixed";
-
- regulator-name = "wl-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vreg_panel: panel-regulator {
- compatible = "regulator-fixed";
-
- pinctrl-names = "default";
- pinctrl-0 = <&panel_en_pin>;
-
- regulator-name = "panel-vddr-reg";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
-
- gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- /delete-node/ vreg-boost;
-
- adsp-pil {
- cx-supply = <&pma8084_s2>;
- };
-};
-
-&soc {
- serial@f991e000 {
- status = "okay";
- };
-
- /* blsp2_uart8 */
- serial@f995e000 {
- status = "okay";
-
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart8_pins_active>;
- pinctrl-1 = <&blsp2_uart8_pins_sleep>;
-
- bluetooth {
- compatible = "brcm,bcm43540-bt";
- max-speed = <3000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_pins>;
- device-wakeup-gpios = <&msmgpio 91 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>;
- interrupt-parent = <&msmgpio>;
- interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wakeup";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pin_a>;
-
- volume-down {
- label = "volume_down";
- gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <15>;
- };
-
- home-key {
- label = "home_key";
- gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_HOMEPAGE>;
- wakeup-source;
- debounce-interval = <15>;
- };
-
- volume-up {
- label = "volume_up";
- gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <15>;
- };
- };
-
- pinctrl@fd510000 {
- blsp2_uart8_pins_active: blsp2-uart8-pins-active {
- pins = "gpio45", "gpio46", "gpio47", "gpio48";
- function = "blsp_uart8";
- drive-strength = <8>;
- bias-disable;
- };
-
- blsp2_uart8_pins_sleep: blsp2-uart8-pins-sleep {
- pins = "gpio45", "gpio46", "gpio47", "gpio48";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- bt_pins: bt-pins {
- hostwake {
- pins = "gpio75";
- function = "gpio";
- drive-strength = <16>;
- input-enable;
- };
-
- devwake {
- pins = "gpio91";
- function = "gpio";
- drive-strength = <2>;
- };
- };
-
- sdhc1_pin_a: sdhc1-pin-active {
- clk {
- pins = "sdc1_clk";
- drive-strength = <4>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <4>;
- bias-pull-up;
- };
- };
-
- sdhc2_pin_a: sdhc2-pin-active {
- clk-cmd-data {
- pins = "gpio35", "gpio36", "gpio37", "gpio38",
- "gpio39", "gpio40";
- function = "sdc3";
- drive-strength = <8>;
- bias-disable;
- };
- };
-
- sdhc2_cd_pin: sdhc2-cd {
- pins = "gpio62";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- sdhc3_pin_a: sdhc3-pin-active {
- clk {
- pins = "sdc2_clk";
- drive-strength = <6>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <6>;
- bias-pull-up;
- };
- };
-
- i2c2_pins: i2c2 {
- mux {
- pins = "gpio6", "gpio7";
- function = "blsp_i2c2";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- i2c6_pins: i2c6 {
- mux {
- pins = "gpio29", "gpio30";
- function = "blsp_i2c6";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- i2c12_pins: i2c12 {
- mux {
- pins = "gpio87", "gpio88";
- function = "blsp_i2c12";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- i2c_touchkey_pins: i2c-touchkey {
- mux {
- pins = "gpio95", "gpio96";
- function = "gpio";
- input-enable;
- bias-pull-up;
- };
- };
-
- i2c_led_gpioex_pins: i2c-led-gpioex {
- mux {
- pins = "gpio120", "gpio121";
- function = "gpio";
- input-enable;
- bias-pull-down;
- };
- };
-
- gpioex_pin: gpioex {
- res {
- pins = "gpio145";
- function = "gpio";
-
- bias-pull-up;
- drive-strength = <2>;
- };
- };
-
- wifi_pin: wifi {
- int {
- pins = "gpio92";
- function = "gpio";
-
- input-enable;
- bias-pull-down;
- };
- };
-
- panel_te_pin: panel {
- te {
- pins = "gpio12";
- function = "mdp_vsync";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
- };
-
- sdhc_1: sdhci@f9824900 {
- status = "okay";
-
- vmmc-supply = <&pma8084_l20>;
- vqmmc-supply = <&pma8084_s4>;
-
- bus-width = <8>;
- non-removable;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_pin_a>;
- };
-
- sdhc_2: sdhci@f9864900 {
- status = "okay";
-
- max-frequency = <100000000>;
-
- vmmc-supply = <&pma8084_l21>;
- vqmmc-supply = <&pma8084_l13>;
-
- bus-width = <4>;
-
- /* cd-gpio is intentionally disabled. If enabled, an SD card
- * present during boot is not initialized correctly. Without
- * cd-gpios the driver resorts to polling, so hotplug works.
- */
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>;
- // cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>;
- };
-
- sdhci@f98a4900 {
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- max-frequency = <100000000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc3_pin_a>;
-
- vmmc-supply = <&vreg_wlan>;
- vqmmc-supply = <&pma8084_s4>;
-
- bus-width = <4>;
- non-removable;
-
- wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
-
- interrupt-parent = <&msmgpio>;
- interrupts = <92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
-
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>;
- };
- };
-
- usb@f9a55000 {
- status = "okay";
-
- phys = <&usb_hs1_phy>;
- phy-select = <&tcsr 0xb000 0>;
- /*extcon = <&smbb>, <&usb_id>;*/
- /*vbus-supply = <&chg_otg>;*/
-
- hnp-disable;
- srp-disable;
- adp-disable;
-
- ulpi {
- phy@a {
- status = "okay";
-
- v1p8-supply = <&pma8084_l6>;
- v3p3-supply = <&pma8084_l24>;
-
- /*extcon = <&smbb>;*/
- qcom,init-seq = /bits/ 8 <0x1 0x64>;
- };
- };
- };
-
- i2c@f9924000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
-
- touchscreen@20 {
- compatible = "syna,rmi4-i2c";
- reg = <0x20>;
-
- interrupt-parent = <&pma8084_gpios>;
- interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
-
- vdd-supply = <&max77826_ldo13>;
- vio-supply = <&pma8084_lvs2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&touch_pin>;
-
- syna,startup-delay-ms = <100>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- rmi4-f01@1 {
- reg = <0x1>;
- syna,nosleep-mode = <1>;
- };
-
- rmi4-f12@12 {
- reg = <0x12>;
- syna,sensor-type = <1>;
- };
- };
- };
-
- i2c@f9928000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&i2c6_pins>;
-
- pmic@60 {
- reg = <0x60>;
- compatible = "maxim,max77826";
-
- regulators {
- max77826_ldo1: LDO1 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- max77826_ldo2: LDO2 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- max77826_ldo3: LDO3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- max77826_ldo4: LDO4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- max77826_ldo5: LDO5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- max77826_ldo6: LDO6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- max77826_ldo7: LDO7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- max77826_ldo8: LDO8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- max77826_ldo9: LDO9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- max77826_ldo10: LDO10 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- max77826_ldo11: LDO11 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2950000>;
- };
-
- max77826_ldo12: LDO12 {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <3300000>;
- };
-
- max77826_ldo13: LDO13 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- max77826_ldo14: LDO14 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- max77826_ldo15: LDO15 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- max77826_buck: BUCK {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- max77826_buckboost: BUCKBOOST {
- regulator-min-microvolt = <3400000>;
- regulator-max-microvolt = <3400000>;
- };
- };
- };
- };
-
- i2c@f9968000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&i2c12_pins>;
-
- fuelgauge@36 {
- compatible = "maxim,max17048";
- reg = <0x36>;
-
- maxim,double-soc;
- maxim,rcomp = /bits/ 8 <0x56>;
-
- interrupt-parent = <&pma8084_gpios>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&fuelgauge_pin>;
- };
- };
-
- adreno@fdb00000 {
- status = "ok";
- };
-
- mdss@fd900000 {
- status = "ok";
-
- mdp@fd900000 {
- status = "ok";
- };
-
- dsi@fd922800 {
- status = "ok";
-
- vdda-supply = <&pma8084_l2>;
- vdd-supply = <&pma8084_l22>;
- vddio-supply = <&pma8084_l12>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- port@1 {
- endpoint {
- remote-endpoint = <&panel_in>;
- data-lanes = <0 1 2 3>;
- };
- };
- };
-
- panel: panel@0 {
- reg = <0>;
- compatible = "samsung,s6e3fa2";
-
- pinctrl-names = "default";
- pinctrl-0 = <&panel_te_pin &panel_rst_pin>;
-
- iovdd-supply = <&pma8084_lvs4>;
- vddr-supply = <&vreg_panel>;
-
- reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>;
- te-gpios = <&msmgpio 12 GPIO_ACTIVE_HIGH>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
- };
- };
-
- dsi-phy@fd922a00 {
- status = "ok";
-
- vddio-supply = <&pma8084_l12>;
- };
- };
-
- remoteproc@fc880000 {
- cx-supply = <&pma8084_s2>;
- mss-supply = <&pma8084_s6>;
- mx-supply = <&pma8084_s1>;
- pll-supply = <&pma8084_l12>;
- };
-};
-
-&spmi_bus {
- pma8084@0 {
- gpios@c000 {
- gpio_keys_pin_a: gpio-keys-active {
- pins = "gpio2", "gpio3", "gpio5";
- function = "normal";
-
- bias-pull-up;
- power-source = <PMA8084_GPIO_S4>;
- };
-
- touchkey_pin: touchkey-int-pin {
- pins = "gpio6";
- function = "normal";
- bias-disable;
- input-enable;
- power-source = <PMA8084_GPIO_S4>;
- };
-
- touch_pin: touchscreen-int-pin {
- pins = "gpio8";
- function = "normal";
- bias-disable;
- input-enable;
- power-source = <PMA8084_GPIO_S4>;
- };
-
- panel_en_pin: panel-en-pin {
- pins = "gpio14";
- function = "normal";
- bias-pull-up;
- power-source = <PMA8084_GPIO_S4>;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
- };
-
- wlan_sleep_clk_pin: wlan-sleep-clk-pin {
- pins = "gpio16";
- function = "func2";
-
- output-high;
- power-source = <PMA8084_GPIO_S4>;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
- };
-
- panel_rst_pin: panel-rst-pin {
- pins = "gpio17";
- function = "normal";
- bias-disable;
- power-source = <PMA8084_GPIO_S4>;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
- };
-
-
- fuelgauge_pin: fuelgauge-int-pin {
- pins = "gpio21";
- function = "normal";
- bias-disable;
- input-enable;
- power-source = <PMA8084_GPIO_S4>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts
deleted file mode 100644
index 79e2cfbbb1ba..000000000000
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts
+++ /dev/null
@@ -1,435 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "qcom-msm8974.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-
-/ {
- model = "Sony Xperia Z1 Compact";
- compatible = "sony,xperia-amami", "qcom,msm8974";
-
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pin_a>;
-
- volume-down {
- label = "volume_down";
- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEDOWN>;
- };
-
- camera-snapshot {
- label = "camera_snapshot";
- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA>;
- };
-
- camera-focus {
- label = "camera_focus";
- gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA_FOCUS>;
- };
-
- volume-up {
- label = "volume_up";
- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEUP>;
- };
- };
-
- memory@0 {
- reg = <0 0x40000000>, <0x40000000 0x40000000>;
- device_type = "memory";
- };
-
- smd {
- rpm {
- rpm_requests {
- pm8841-regulators {
- s1 {
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s3 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s4 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
- };
-
- pm8941-regulators {
- vdd_l1_l3-supply = <&pm8941_s1>;
- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
- vdd_l4_l11-supply = <&pm8941_s1>;
- vdd_l5_l7-supply = <&pm8941_s2>;
- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
- vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
- vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
- vdd_l21-supply = <&vreg_boost>;
-
- s1 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- s2 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
- regulator-boot-on;
- };
-
- s3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- s4 {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l11 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1350000>;
- };
-
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l15 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l17 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l18 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l19 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-allow-set-load;
- regulator-boot-on;
- regulator-system-load = <200000>;
- };
-
- l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l22 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- l23 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
-
- regulator-boot-on;
- };
- };
- };
- };
- };
-};
-
-&soc {
- sdhci@f9824900 {
- status = "okay";
-
- vmmc-supply = <&pm8941_l20>;
- vqmmc-supply = <&pm8941_s3>;
-
- bus-width = <8>;
- non-removable;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_pin_a>;
- };
-
- sdhci@f98a4900 {
- status = "okay";
-
- bus-width = <4>;
-
- vmmc-supply = <&pm8941_l21>;
- vqmmc-supply = <&pm8941_l13>;
-
- cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
- };
-
- serial@f991e000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_uart2_pin_a>;
- };
-
-
- pinctrl@fd510000 {
- blsp1_uart2_pin_a: blsp1-uart2-pin-active {
- rx {
- pins = "gpio5";
- function = "blsp_uart2";
-
- drive-strength = <2>;
- bias-pull-up;
- };
-
- tx {
- pins = "gpio4";
- function = "blsp_uart2";
-
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- i2c2_pins: i2c2 {
- mux {
- pins = "gpio6", "gpio7";
- function = "blsp_i2c2";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- sdhc1_pin_a: sdhc1-pin-active {
- clk {
- pins = "sdc1_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc2_cd_pin_a: sdhc2-cd-pin-active {
- pins = "gpio62";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- sdhc2_pin_a: sdhc2-pin-active {
- clk {
- pins = "sdc2_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <6>;
- bias-pull-up;
- };
- };
- };
-
- dma-controller@f9944000 {
- qcom,controlled-remotely;
- };
-
- usb@f9a55000 {
- status = "okay";
-
- phys = <&usb_hs1_phy>;
- phy-select = <&tcsr 0xb000 0>;
- extcon = <&smbb>, <&usb_id>;
- vbus-supply = <&chg_otg>;
-
- hnp-disable;
- srp-disable;
- adp-disable;
-
- ulpi {
- phy@a {
- status = "okay";
-
- v1p8-supply = <&pm8941_l6>;
- v3p3-supply = <&pm8941_l24>;
-
- extcon = <&smbb>;
- qcom,init-seq = /bits/ 8 <0x1 0x64>;
- };
- };
- };
-};
-
-&spmi_bus {
- pm8941@0 {
- charger@1000 {
- qcom,fast-charge-safe-current = <1300000>;
- qcom,fast-charge-current-limit = <1300000>;
- qcom,dc-current-limit = <1300000>;
- qcom,fast-charge-safe-voltage = <4400000>;
- qcom,fast-charge-high-threshold-voltage = <4350000>;
- qcom,fast-charge-low-threshold-voltage = <3400000>;
- qcom,auto-recharge-threshold-voltage = <4200000>;
- qcom,minimum-input-voltage = <4300000>;
- };
-
- gpios@c000 {
- gpio_keys_pin_a: gpio-keys-active {
- pins = "gpio2", "gpio3", "gpio4", "gpio5";
- function = "normal";
-
- bias-pull-up;
- power-source = <PM8941_GPIO_S3>;
- };
- };
-
- coincell@2800 {
- status = "okay";
- qcom,rset-ohms = <2100>;
- qcom,vset-millivolts = <3000>;
- };
- };
-
- pm8941@1 {
- wled@d800 {
- status = "okay";
-
- qcom,cs-out;
- qcom,current-limit = <20>;
- qcom,current-boost-limit = <805>;
- qcom,switching-freq = <1600>;
- qcom,ovp = <29>;
- qcom,num-strings = <2>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
deleted file mode 100644
index e66937e3f7dd..000000000000
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
+++ /dev/null
@@ -1,723 +0,0 @@
-#include "qcom-msm8974pro.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-
-/ {
- model = "Sony Xperia Z2 Tablet";
- compatible = "sony,xperia-castor", "qcom,msm8974";
-
- aliases {
- serial0 = &blsp1_uart2;
- serial1 = &blsp2_uart7;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pin_a>;
-
- volume-down {
- label = "volume_down";
- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEDOWN>;
- };
-
- camera-snapshot {
- label = "camera_snapshot";
- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA>;
- };
-
- camera-focus {
- label = "camera_focus";
- gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA_FOCUS>;
- };
-
- volume-up {
- label = "volume_up";
- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEUP>;
- };
- };
-
- smd {
- rpm {
- rpm_requests {
- pm8941-regulators {
- vdd_l1_l3-supply = <&pm8941_s1>;
- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
- vdd_l4_l11-supply = <&pm8941_s1>;
- vdd_l5_l7-supply = <&pm8941_s2>;
- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
- vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
- vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
- vdd_l21-supply = <&vreg_boost>;
-
- s1 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- s2 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
- regulator-boot-on;
- };
-
- s3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-system-load = <154000>;
- };
-
- s4 {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l11 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1350000>;
- };
-
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l15 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l17 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l18 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l19 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-allow-set-load;
- regulator-boot-on;
- regulator-allow-set-load;
- regulator-system-load = <500000>;
- };
-
- l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l22 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- l23 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
-
- regulator-boot-on;
- };
- };
- };
- };
- };
-
- vreg_bl_vddio: lcd-backlight-vddio {
- compatible = "regulator-fixed";
- regulator-name = "vreg_bl_vddio";
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3150000>;
-
- gpio = <&msmgpio 69 0>;
- enable-active-high;
-
- vin-supply = <&pm8941_s3>;
- startup-delay-us = <70000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_backlight_en_pin_a>;
- };
-
- vreg_vsp: lcd-dcdc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vreg_vsp";
- regulator-min-microvolt = <5600000>;
- regulator-max-microvolt = <5600000>;
-
- gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_dcdc_en_pin_a>;
- };
-
- vreg_wlan: wlan-regulator {
- compatible = "regulator-fixed";
-
- regulator-name = "wl-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_regulator_pin>;
- };
-};
-
-&soc {
- sdhci@f9824900 {
- status = "okay";
-
- vmmc-supply = <&pm8941_l20>;
- vqmmc-supply = <&pm8941_s3>;
-
- bus-width = <8>;
- non-removable;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_pin_a>;
- };
-
- sdhci@f9864900 {
- status = "okay";
-
- max-frequency = <100000000>;
- non-removable;
- vmmc-supply = <&vreg_wlan>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc3_pin_a>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- bcrmf@1 {
- compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac";
- reg = <1>;
-
- brcm,drive-strength = <10>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_sleep_clk_pin>;
- };
- };
-
- sdhci@f98a4900 {
- status = "okay";
-
- bus-width = <4>;
-
- vmmc-supply = <&pm8941_l21>;
- vqmmc-supply = <&pm8941_l13>;
-
- cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
- };
-
- serial@f991e000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_uart2_pin_a>;
- };
-
- serial@f995d000 {
- status = "ok";
-
- pinctrl-names = "default";
- pinctrl-0 = <&blsp2_uart7_pin_a>;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <3000000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_pin>,
- <&bt_dev_wake_pin>,
- <&bt_reg_on_pin>;
-
- host-wakeup-gpios = <&msmgpio 95 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&msmgpio 96 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>;
- };
- };
-
- usb@f9a55000 {
- status = "okay";
-
- phys = <&usb_hs1_phy>;
- phy-select = <&tcsr 0xb000 0>;
- extcon = <&smbb>, <&usb_id>;
- vbus-supply = <&chg_otg>;
-
- hnp-disable;
- srp-disable;
- adp-disable;
-
- ulpi {
- phy@a {
- status = "okay";
-
- v1p8-supply = <&pm8941_l6>;
- v3p3-supply = <&pm8941_l24>;
-
- extcon = <&smbb>;
- qcom,init-seq = /bits/ 8 <0x1 0x64>;
- };
- };
- };
-
- pinctrl@fd510000 {
- blsp1_uart2_pin_a: blsp1-uart2-pin-active {
- rx {
- pins = "gpio5";
- function = "blsp_uart2";
-
- drive-strength = <2>;
- bias-pull-up;
- };
-
- tx {
- pins = "gpio4";
- function = "blsp_uart2";
-
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- blsp2_uart7_pin_a: blsp2-uart7-pin-active {
- tx {
- pins = "gpio41";
- function = "blsp_uart7";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- rx {
- pins = "gpio42";
- function = "blsp_uart7";
-
- drive-strength = <2>;
- bias-pull-up;
- };
-
- cts {
- pins = "gpio43";
- function = "blsp_uart7";
-
- drive-strength = <2>;
- bias-pull-up;
- };
-
- rts {
- pins = "gpio44";
- function = "blsp_uart7";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- i2c8_pins: i2c8 {
- mux {
- pins = "gpio47", "gpio48";
- function = "blsp_i2c8";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- i2c11_pins: i2c11 {
- mux {
- pins = "gpio83", "gpio84";
- function = "blsp_i2c11";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- lcd_backlight_en_pin_a: lcd-backlight-vddio {
- pins = "gpio69";
- drive-strength = <10>;
- output-low;
- bias-disable;
- };
-
- sdhc1_pin_a: sdhc1-pin-active {
- clk {
- pins = "sdc1_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc2_cd_pin_a: sdhc2-cd-pin-active {
- pins = "gpio62";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- sdhc2_pin_a: sdhc2-pin-active {
- clk {
- pins = "sdc2_clk";
- drive-strength = <6>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <6>;
- bias-pull-up;
- };
- };
-
- sdhc3_pin_a: sdhc3-pin-active {
- clk {
- pins = "gpio40";
- function = "sdc3";
-
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd {
- pins = "gpio39";
- function = "sdc3";
-
- drive-strength = <10>;
- bias-pull-up;
- };
-
- data {
- pins = "gpio35", "gpio36", "gpio37", "gpio38";
- function = "sdc3";
-
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- ts_int_pin: synaptics {
- pin {
- pins = "gpio86";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- input-enable;
- };
- };
-
- bt_host_wake_pin: bt-host-wake {
- pins = "gpio95";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- output-low;
- };
-
- bt_dev_wake_pin: bt-dev-wake {
- pins = "gpio96";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- i2c@f9964000 {
- status = "okay";
-
- clock-frequency = <355000>;
- qcom,src-freq = <50000000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&i2c8_pins>;
-
- synaptics@2c {
- compatible = "syna,rmi4-i2c";
- reg = <0x2c>;
-
- interrupt-parent = <&msmgpio>;
- interrupts = <86 IRQ_TYPE_EDGE_FALLING>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd-supply = <&pm8941_l22>;
- vio-supply = <&pm8941_lvs3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&ts_int_pin>;
-
- syna,startup-delay-ms = <10>;
-
- rmi-f01@1 {
- reg = <0x1>;
- syna,nosleep = <1>;
- };
-
- rmi-f11@11 {
- reg = <0x11>;
- syna,f11-flip-x = <1>;
- syna,sensor-type = <1>;
- };
- };
- };
-
- i2c@f9967000 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c11_pins>;
- clock-frequency = <355000>;
- qcom,src-freq = <50000000>;
-
- lp8566_wled: backlight@2c {
- compatible = "ti,lp8556";
- reg = <0x2c>;
- power-supply = <&vreg_bl_vddio>;
-
- bl-name = "backlight";
- dev-ctrl = /bits/ 8 <0x05>;
- init-brt = /bits/ 8 <0x3f>;
- rom_a0h {
- rom-addr = /bits/ 8 <0xa0>;
- rom-val = /bits/ 8 <0xff>;
- };
- rom_a1h {
- rom-addr = /bits/ 8 <0xa1>;
- rom-val = /bits/ 8 <0x3f>;
- };
- rom_a2h {
- rom-addr = /bits/ 8 <0xa2>;
- rom-val = /bits/ 8 <0x20>;
- };
- rom_a3h {
- rom-addr = /bits/ 8 <0xa3>;
- rom-val = /bits/ 8 <0x5e>;
- };
- rom_a4h {
- rom-addr = /bits/ 8 <0xa4>;
- rom-val = /bits/ 8 <0x02>;
- };
- rom_a5h {
- rom-addr = /bits/ 8 <0xa5>;
- rom-val = /bits/ 8 <0x04>;
- };
- rom_a6h {
- rom-addr = /bits/ 8 <0xa6>;
- rom-val = /bits/ 8 <0x80>;
- };
- rom_a7h {
- rom-addr = /bits/ 8 <0xa7>;
- rom-val = /bits/ 8 <0xf7>;
- };
- rom_a9h {
- rom-addr = /bits/ 8 <0xa9>;
- rom-val = /bits/ 8 <0x80>;
- };
- rom_aah {
- rom-addr = /bits/ 8 <0xaa>;
- rom-val = /bits/ 8 <0x0f>;
- };
- rom_aeh {
- rom-addr = /bits/ 8 <0xae>;
- rom-val = /bits/ 8 <0x0f>;
- };
- };
- };
-};
-
-&spmi_bus {
- pm8941@0 {
- charger@1000 {
- qcom,fast-charge-safe-current = <1500000>;
- qcom,fast-charge-current-limit = <1500000>;
- qcom,dc-current-limit = <1800000>;
- qcom,fast-charge-safe-voltage = <4400000>;
- qcom,fast-charge-high-threshold-voltage = <4350000>;
- qcom,fast-charge-low-threshold-voltage = <3400000>;
- qcom,auto-recharge-threshold-voltage = <4200000>;
- qcom,minimum-input-voltage = <4300000>;
- };
-
- gpios@c000 {
- gpio_keys_pin_a: gpio-keys-active {
- pins = "gpio2", "gpio5";
- function = "normal";
-
- bias-pull-up;
- power-source = <PM8941_GPIO_S3>;
- };
-
- bt_reg_on_pin: bt-reg-on {
- pins = "gpio16";
- function = "normal";
-
- output-low;
- power-source = <PM8941_GPIO_S3>;
- };
-
- wlan_sleep_clk_pin: wl-sleep-clk {
- pins = "gpio17";
- function = "func2";
-
- output-high;
- power-source = <PM8941_GPIO_S3>;
- };
-
- wlan_regulator_pin: wl-reg-active {
- pins = "gpio18";
- function = "normal";
-
- bias-disable;
- power-source = <PM8941_GPIO_S3>;
- };
-
- lcd_dcdc_en_pin_a: lcd-dcdc-en-active {
- pins = "gpio20";
- function = "normal";
-
- bias-disable;
- power-source = <PM8941_GPIO_S3>;
- input-disable;
- output-low;
- };
-
- };
-
- coincell@2800 {
- status = "okay";
- qcom,rset-ohms = <2100>;
- qcom,vset-millivolts = <3000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
deleted file mode 100644
index a62e5c25b23c..000000000000
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ /dev/null
@@ -1,484 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "qcom-msm8974.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-
-/ {
- model = "Sony Xperia Z1";
- compatible = "sony,xperia-honami", "qcom,msm8974";
-
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pin_a>;
-
- volume-down {
- label = "volume_down";
- gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEDOWN>;
- };
-
- camera-snapshot {
- label = "camera_snapshot";
- gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA>;
- };
-
- camera-focus {
- label = "camera_focus";
- gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_CAMERA_FOCUS>;
- };
-
- volume-up {
- label = "volume_up";
- gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- linux,code = <KEY_VOLUMEUP>;
- };
- };
-
- memory@0 {
- reg = <0 0x40000000>, <0x40000000 0x40000000>;
- device_type = "memory";
- };
-
- smd {
- rpm {
- rpm_requests {
- pm8841-regulators {
- s1 {
- regulator-min-microvolt = <675000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s3 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
- s4 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
- };
-
- pm8941-regulators {
- vdd_l1_l3-supply = <&pm8941_s1>;
- vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
- vdd_l4_l11-supply = <&pm8941_s1>;
- vdd_l5_l7-supply = <&pm8941_s2>;
- vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
- vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
- vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
- vdd_l21-supply = <&vreg_boost>;
-
- s1 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- s2 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
- regulator-boot-on;
- };
-
- s3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- s4 {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- l1 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l3 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
-
- l5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-boot-on;
- };
-
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
-
- l11 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1350000>;
- };
-
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- l15 {
- regulator-min-microvolt = <2050000>;
- regulator-max-microvolt = <2050000>;
- };
-
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l17 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
-
- l18 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- };
-
- l19 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-allow-set-load;
- regulator-boot-on;
- regulator-system-load = <200000>;
- };
-
- l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
-
- regulator-boot-on;
- };
-
- l22 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- l23 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
-
- regulator-boot-on;
- };
- };
- };
- };
- };
-};
-
-&soc {
- usb@f9a55000 {
- status = "okay";
-
- phys = <&usb_hs1_phy>;
- phy-select = <&tcsr 0xb000 0>;
- extcon = <&smbb>, <&usb_id>;
- vbus-supply = <&chg_otg>;
-
- hnp-disable;
- srp-disable;
- adp-disable;
-
- ulpi {
- phy@a {
- status = "okay";
-
- v1p8-supply = <&pm8941_l6>;
- v3p3-supply = <&pm8941_l24>;
-
- extcon = <&smbb>;
- qcom,init-seq = /bits/ 8 <0x1 0x64>;
- };
- };
- };
-
- sdhci@f9824900 {
- status = "okay";
-
- vmmc-supply = <&pm8941_l20>;
- vqmmc-supply = <&pm8941_s3>;
-
- bus-width = <8>;
- non-removable;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_pin_a>;
- };
-
- sdhci@f98a4900 {
- status = "okay";
-
- bus-width = <4>;
-
- vmmc-supply = <&pm8941_l21>;
- vqmmc-supply = <&pm8941_l13>;
-
- cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
- };
-
- serial@f991e000 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_uart2_pin_a>;
- };
-
- i2c@f9924000 {
- status = "okay";
-
- clock-frequency = <355000>;
- qcom,src-freq = <50000000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
-
- synaptics@2c {
- compatible = "syna,rmi4-i2c";
- reg = <0x2c>;
-
- interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd-supply = <&pm8941_l22>;
- vio-supply = <&pm8941_lvs3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&ts_int_pin>;
-
- syna,startup-delay-ms = <10>;
-
- rmi4-f01@1 {
- reg = <0x1>;
- syna,nosleep-mode = <1>;
- };
-
- rmi4-f11@11 {
- reg = <0x11>;
- touchscreen-inverted-x;
- syna,sensor-type = <1>;
- };
- };
- };
-
- pinctrl@fd510000 {
- blsp1_uart2_pin_a: blsp1-uart2-pin-active {
- rx {
- pins = "gpio5";
- function = "blsp_uart2";
-
- drive-strength = <2>;
- bias-pull-up;
- };
-
- tx {
- pins = "gpio4";
- function = "blsp_uart2";
-
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- i2c2_pins: i2c2 {
- mux {
- pins = "gpio6", "gpio7";
- function = "blsp_i2c2";
-
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- sdhc1_pin_a: sdhc1-pin-active {
- clk {
- pins = "sdc1_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc2_cd_pin_a: sdhc2-cd-pin-active {
- pins = "gpio62";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- sdhc2_pin_a: sdhc2-pin-active {
- clk {
- pins = "sdc2_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <6>;
- bias-pull-up;
- };
- };
-
- ts_int_pin: touch-int {
- pin {
- pins = "gpio61";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- input-enable;
- };
- };
- };
-
- dma-controller@f9944000 {
- qcom,controlled-remotely;
- };
-};
-
-&spmi_bus {
- pm8941@0 {
- charger@1000 {
- qcom,fast-charge-safe-current = <1500000>;
- qcom,fast-charge-current-limit = <1500000>;
- qcom,dc-current-limit = <1800000>;
- qcom,fast-charge-safe-voltage = <4400000>;
- qcom,fast-charge-high-threshold-voltage = <4350000>;
- qcom,fast-charge-low-threshold-voltage = <3400000>;
- qcom,auto-recharge-threshold-voltage = <4200000>;
- qcom,minimum-input-voltage = <4300000>;
- };
-
- gpios@c000 {
- gpio_keys_pin_a: gpio-keys-active {
- pins = "gpio2", "gpio3", "gpio4", "gpio5";
- function = "normal";
-
- bias-pull-up;
- power-source = <PM8941_GPIO_S3>;
- };
- };
-
- coincell@2800 {
- status = "okay";
- qcom,rset-ohms = <2100>;
- qcom,vset-millivolts = <3000>;
- };
- };
-
- pm8941@1 {
- wled@d800 {
- status = "okay";
-
- qcom,cs-out;
- qcom,current-limit = <20>;
- qcom,current-boost-limit = <805>;
- qcom,switching-freq = <1600>;
- qcom,ovp = <29>;
- qcom,num-strings = <2>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts
new file mode 100644
index 000000000000..9f2ab5c122d0
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974-sony-xperia-rhine.dtsi"
+
+/ {
+ model = "Sony Xperia Z1 Compact";
+ compatible = "sony,xperia-amami", "qcom,msm8974";
+ chassis-type = "handset";
+};
+
+&smbb {
+ qcom,fast-charge-safe-current = <1300000>;
+ qcom,fast-charge-current-limit = <1300000>;
+ qcom,dc-current-limit = <1300000>;
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts
new file mode 100644
index 000000000000..9028f17e5c4a
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974-sony-xperia-rhine.dtsi"
+
+/ {
+ model = "Sony Xperia Z1";
+ compatible = "sony,xperia-honami", "qcom,msm8974";
+ chassis-type = "handset";
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
new file mode 100644
index 000000000000..d3bec03b126c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
@@ -0,0 +1,496 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ key-volume-down {
+ label = "volume_down";
+ gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ key-camera-snapshot {
+ label = "camera_snapshot";
+ gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA>;
+ };
+
+ key-camera-focus {
+ label = "camera_focus";
+ gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ };
+
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ramoops@3e8e0000 {
+ compatible = "ramoops";
+ reg = <0x3e8e0000 0x200000>;
+
+ console-size = <0x100000>;
+ record-size = <0x10000>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x80000>;
+ };
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+ clock-frequency = <355000>;
+
+ synaptics@2c {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x2c>;
+
+ interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd-supply = <&pm8941_l22>;
+ vio-supply = <&pm8941_lvs3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_pin>;
+
+ syna,startup-delay-ms = <10>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ touchscreen-inverted-x;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+ clock-frequency = <355000>;
+
+ nfc@28 {
+ compatible = "nxp,pn544-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <59 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&pm8941_gpios 23 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&blsp2_dma {
+ qcom,controlled-remotely;
+};
+
+&blsp2_i2c5 {
+ status = "okay";
+ clock-frequency = <355000>;
+
+ /* sii8334 MHL HDMI bridge */
+};
+
+&pm8941_coincell {
+ status = "okay";
+ qcom,rset-ohms = <2100>;
+ qcom,vset-millivolts = <3000>;
+};
+
+&pm8941_gpios {
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio2", "gpio3", "gpio4", "gpio5";
+ function = "normal";
+
+ bias-pull-up;
+ power-source = <PM8941_GPIO_S3>;
+ };
+};
+
+&pm8941_lpg {
+ status = "okay";
+
+ qcom,power-source = <1>;
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@5 {
+ reg = <5>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ led@6 {
+ reg = <6>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@7 {
+ reg = <7>;
+ color = <LED_COLOR_ID_RED>;
+ };
+ };
+};
+
+&pm8941_wled {
+ status = "okay";
+
+ qcom,cs-out;
+ qcom,current-limit = <20>;
+ qcom,current-boost-limit = <805>;
+ qcom,switching-freq = <1600>;
+ qcom,ovp = <29>;
+ qcom,num-strings = <2>;
+};
+
+&remoteproc_adsp {
+ cx-supply = <&pm8841_s2>;
+};
+
+&remoteproc_mss {
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s4: s4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ vdd_l1_l3-supply = <&pm8941_s1>;
+ vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+ vdd_l4_l11-supply = <&pm8941_s1>;
+ vdd_l5_l7-supply = <&pm8941_s2>;
+ vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+ vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
+ vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
+ vdd_l21-supply = <&vreg_boost>;
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ regulator-boot-on;
+ };
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s4: s4 {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ regulator-boot-on;
+ };
+
+ pm8941_lvs3: lvs3 {};
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ vmmc-supply = <&pm8941_l21>;
+ vqmmc-supply = <&pm8941_l13>;
+
+ cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_on>;
+ pinctrl-1 = <&sdc2_off>;
+};
+
+&smbb {
+ qcom,fast-charge-safe-current = <1500000>;
+ qcom,fast-charge-current-limit = <1500000>;
+ qcom,dc-current-limit = <1800000>;
+ qcom,fast-charge-safe-voltage = <4400000>;
+ qcom,fast-charge-high-threshold-voltage = <4350000>;
+ qcom,fast-charge-low-threshold-voltage = <3400000>;
+ qcom,auto-recharge-threshold-voltage = <4200000>;
+ qcom,minimum-input-voltage = <4300000>;
+};
+
+&tlmm {
+ ts_int_pin: touch-int-state {
+ pins = "gpio61";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ sdc1_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_on: sdc-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc2_cmd", "sdc2_data";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ cd-pins {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+};
+
+&usb {
+ status = "okay";
+
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+};
+
+&usb_hs1_phy {
+ status = "okay";
+
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 412d94736c35..8208012684d4 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -12,61 +12,19 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
- model = "Qualcomm MSM8974";
- compatible = "qcom,msm8974";
interrupt-parent = <&intc>;
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mpss_region: mpss@8000000 {
- reg = <0x08000000 0x5100000>;
- no-map;
- };
-
- mba_region: mba@d100000 {
- reg = <0x0d100000 0x100000>;
- no-map;
- };
-
- wcnss_region: wcnss@d200000 {
- reg = <0x0d200000 0xa00000>;
- no-map;
- };
-
- adsp_region: adsp@dc00000 {
- reg = <0x0dc00000 0x1900000>;
- no-map;
- };
-
- venus@f500000 {
- reg = <0x0f500000 0x500000>;
- no-map;
- };
-
- smem_region: smem@fa00000 {
- reg = <0xfa00000 0x200000>;
- no-map;
- };
-
- tz@fc00000 {
- reg = <0x0fc00000 0x160000>;
- no-map;
- };
-
- rfsa@fd60000 {
- reg = <0x0fd60000 0x20000>;
- no-map;
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
};
- rmtfs@fd80000 {
- compatible = "qcom,rmtfs-mem";
- reg = <0x0fd80000 0x180000>;
- no-map;
-
- qcom,client-id = <1>;
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
};
};
@@ -136,238 +94,75 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-msm8974", "qcom,scm";
+ clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
+ clock-names = "core", "bus", "iface";
+ };
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x0>;
};
- thermal-zones {
- cpu0-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 5>;
-
- trips {
- cpu_alert0: trip0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit0: trip1 {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
-
- cpu1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 6>;
-
- trips {
- cpu_alert1: trip0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit1: trip1 {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
-
- cpu2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 7>;
-
- trips {
- cpu_alert2: trip0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit2: trip1 {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
-
- cpu3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 8>;
-
- trips {
- cpu_alert3: trip0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit3: trip1 {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
-
- q6-dsp-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ pmu {
+ compatible = "qcom,krait-pmu";
+ interrupts = <GIC_PPI 7 0xf04>;
+ };
- thermal-sensors = <&tsens 1>;
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- trips {
- q6_dsp_alert0: trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
+ mpss_region: mpss@8000000 {
+ reg = <0x08000000 0x5100000>;
+ no-map;
};
- modemtx-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 2>;
-
- trips {
- modemtx_alert0: trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
+ mba_region: mba@d100000 {
+ reg = <0x0d100000 0x100000>;
+ no-map;
};
- video-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 3>;
-
- trips {
- video_alert0: trip-point0 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
+ wcnss_region: wcnss@d200000 {
+ reg = <0x0d200000 0xa00000>;
+ no-map;
};
- wlan-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 4>;
-
- trips {
- wlan_alert0: trip-point0 {
- temperature = <105000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
+ adsp_region: adsp@dc00000 {
+ reg = <0x0dc00000 0x1900000>;
+ no-map;
};
- gpu-top-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 9>;
-
- trips {
- gpu1_alert0: trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
+ venus_region: memory@f500000 {
+ reg = <0x0f500000 0x500000>;
+ no-map;
};
- gpu-bottom-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 10>;
-
- trips {
- gpu2_alert0: trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
+ smem_region: smem@fa00000 {
+ reg = <0xfa00000 0x200000>;
+ no-map;
};
- };
- cpu-pmu {
- compatible = "qcom,krait-pmu";
- interrupts = <GIC_PPI 7 0xf04>;
- };
-
- clocks {
- xo_board: xo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
+ tz_region: memory@fc00000 {
+ reg = <0x0fc00000 0x160000>;
+ no-map;
};
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
+ rfsa_mem: memory@fd60000 {
+ reg = <0x0fd60000 0x20000>;
+ no-map;
};
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 2 0xf08>,
- <GIC_PPI 3 0xf08>,
- <GIC_PPI 4 0xf08>,
- <GIC_PPI 1 0xf08>;
- clock-frequency = <19200000>;
- };
-
- adsp-pil {
- compatible = "qcom,msm8974-adsp-pil";
-
- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
-
- cx-supply = <&pm8841_s2>;
- clocks = <&xo_board>;
- clock-names = "xo";
-
- memory-region = <&adsp_region>;
-
- qcom,smem-states = <&adsp_smp2p_out 0>;
- qcom,smem-state-names = "stop";
-
- smd-edge {
- interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
-
- qcom,ipc = <&apcs 8 8>;
- qcom,smd-edge = <1>;
+ rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0fd80000 0x180000>;
+ no-map;
- label = "lpass";
+ qcom,client-id = <1>;
};
};
@@ -497,11 +292,25 @@
};
};
- firmware {
- scm {
- compatible = "qcom,scm";
- clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
- clock-names = "core", "bus", "iface";
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests: rpm_requests {
+ compatible = "qcom,rpm-msm8974";
+ qcom,smd-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+ };
};
};
@@ -524,31 +333,6 @@
reg = <0xf9011000 0x1000>;
};
- qfprom: qfprom@fc4bc000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "qcom,qfprom";
- reg = <0xfc4bc000 0x1000>;
- tsens_calib: calib@d0 {
- reg = <0xd0 0x18>;
- };
- tsens_backup: backup@440 {
- reg = <0x440 0x10>;
- };
- };
-
- tsens: thermal-sensor@fc4a9000 {
- compatible = "qcom,msm8974-tsens";
- reg = <0xfc4a9000 0x1000>, /* TM */
- <0xfc4a8000 0x1000>; /* SROT */
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
- #qcom,sensors = <11>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
- #thermal-sensor-cells = <1>;
- };
-
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -634,67 +418,79 @@
regulator;
};
- acc0: clock-controller@f9088000 {
+ acc0: power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
- acc1: clock-controller@f9098000 {
+ acc1: power-manager@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
- acc2: clock-controller@f90a8000 {
+ acc2: power-manager@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
- acc3: clock-controller@f90b8000 {
+ acc3: power-manager@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
- restart@fc4ab000 {
- compatible = "qcom,pshold";
- reg = <0xfc4ab000 0x4>;
- };
+ sdhc_1: mmc@f9824900 {
+ compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+ reg-names = "hc", "core";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "core", "xo";
+ bus-width = <8>;
+ non-removable;
- gcc: clock-controller@fc400000 {
- compatible = "qcom,gcc-msm8974";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- reg = <0xfc400000 0x4000>;
+ status = "disabled";
};
- tcsr: syscon@fd4a0000 {
- compatible = "syscon";
- reg = <0xfd4a0000 0x10000>;
- };
+ sdhc_3: mmc@f9864900 {
+ compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
+ reg-names = "hc", "core";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC3_AHB_CLK>,
+ <&gcc GCC_SDCC3_APPS_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "core", "xo";
+ bus-width = <4>;
- tcsr_mutex_block: syscon@fd484000 {
- compatible = "syscon";
- reg = <0xfd484000 0x2000>;
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
- mmcc: clock-controller@fd8c0000 {
- compatible = "qcom,mmcc-msm8974";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- reg = <0xfd8c0000 0x6000>;
+ status = "disabled";
};
- tcsr_mutex: tcsr-mutex {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_block 0 0x80>;
+ sdhc_2: mmc@f98a4900 {
+ compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+ reg-names = "hc", "core";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "core", "xo";
+ bus-width = <4>;
- #hwlock-cells = <1>;
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
- rpm_msg_ram: memory@fc428000 {
- compatible = "qcom,rpm-msg-ram";
- reg = <0xfc428000 0x4000>;
+ status = "disabled";
};
blsp1_uart1: serial@f991d000 {
@@ -712,19 +508,90 @@
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ status = "disabled";
+ };
+
+ blsp1_i2c1: i2c@f9923000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9923000 0x1000>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c1_default>;
+ pinctrl-1 = <&blsp1_i2c1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c2: i2c@f9924000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9924000 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c2_default>;
+ pinctrl-1 = <&blsp1_i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c3: i2c@f9925000 {
status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9925000 0x1000>;
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c3_default>;
+ pinctrl-1 = <&blsp1_i2c3_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp1_i2c6: i2c@f9928000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9928000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c6_default>;
+ pinctrl-1 = <&blsp1_i2c6_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ blsp2_dma: dma-controller@f9944000 {
+ compatible = "qcom,bam-v1.4.0";
+ reg = <0xf9944000 0x19000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
};
- blsp2_uart7: serial@f995d000 {
+ blsp2_uart1: serial@f995d000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995d000 0x1000>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart1_default>;
+ pinctrl-1 = <&blsp2_uart1_sleep>;
status = "disabled";
};
- blsp2_uart8: serial@f995e000 {
+ blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -733,58 +600,62 @@
status = "disabled";
};
- blsp2_uart10: serial@f9960000 {
+ blsp2_uart4: serial@f9960000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf9960000 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp2_uart4_default>;
status = "disabled";
};
- sdhci@f9824900 {
- compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
+ blsp2_i2c2: i2c@f9964000 {
status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9964000 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c2_default>;
+ pinctrl-1 = <&blsp2_i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- sdhci@f9864900 {
- compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
- reg-names = "hc_mem", "core_mem";
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC3_APPS_CLK>,
- <&gcc GCC_SDCC3_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
+ blsp2_i2c5: i2c@f9967000 {
status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9967000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c5_default>;
+ pinctrl-1 = <&blsp2_i2c5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- sdhci@f98a4900 {
- compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
+ blsp2_i2c6: i2c@f9968000 {
status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9968000 0x1000>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c6_default>;
+ pinctrl-1 = <&blsp2_i2c6_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- otg: usb@f9a55000 {
+ usb: usb@f9a55000 {
compatible = "qcom,ci-hdrc";
reg = <0xf9a55000 0x200>,
<0xf9a55200 0x200>;
@@ -810,7 +681,7 @@
#phy-cells = <0>;
clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ref", "sleep";
- resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
+ resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
reset-names = "phy", "por";
status = "disabled";
};
@@ -821,7 +692,7 @@
#phy-cells = <0>;
clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
clock-names = "ref", "sleep";
- resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
+ resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
reset-names = "phy", "por";
status = "disabled";
};
@@ -835,55 +706,6 @@
clock-names = "core";
};
- remoteproc@fc880000 {
- compatible = "qcom,msm8974-mss-pil";
- reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
- reg-names = "qdsp6", "rmb";
-
- interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
-
- clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
- <&gcc GCC_MSS_CFG_AHB_CLK>,
- <&gcc GCC_BOOT_ROM_AHB_CLK>,
- <&xo_board>;
- clock-names = "iface", "bus", "mem", "xo";
-
- resets = <&gcc GCC_MSS_RESTART>;
- reset-names = "mss_restart";
-
- cx-supply = <&pm8841_s2>;
- mss-supply = <&pm8841_s3>;
- mx-supply = <&pm8841_s1>;
- pll-supply = <&pm8941_l12>;
-
- qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
-
- qcom,smem-states = <&modem_smp2p_out 0>;
- qcom,smem-state-names = "stop";
-
- mba {
- memory-region = <&mba_region>;
- };
-
- mpss {
- memory-region = <&mpss_region>;
- };
-
- smd-edge {
- interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
-
- qcom,ipc = <&apcs 8 12>;
- qcom,smd-edge = <0>;
-
- label = "modem";
- };
- };
-
pronto: remoteproc@fb21b000 {
compatible = "qcom,pronto-v2-pil", "qcom,pronto";
reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
@@ -898,8 +720,6 @@
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
- vddpx-supply = <&pm8941_s3>;
-
qcom,smem-states = <&wcnss_smp2p_out 0>;
qcom,smem-state-names = "stop";
@@ -910,11 +730,6 @@
clocks = <&rpmcc RPM_SMD_CXO_A2>;
clock-names = "xo";
-
- vddxo-supply = <&pm8941_l6>;
- vddrfa-supply = <&pm8941_l11>;
- vddpa-supply = <&pm8941_l19>;
- vdddig-supply = <&pm8941_s3>;
};
smd-edge {
@@ -942,139 +757,37 @@
interrupt-names = "tx", "rx";
qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
- qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ qcom,smem-state-names = "tx-enable",
+ "tx-rings-empty";
};
};
};
};
- msmgpio: pinctrl@fd510000 {
- compatible = "qcom,msm8974-pinctrl";
- reg = <0xfd510000 0x4000>;
- gpio-controller;
- gpio-ranges = <&msmgpio 0 0 146>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ sram@fc190000 {
+ compatible = "qcom,msm8974-rpm-stats";
+ reg = <0xfc190000 0x10000>;
};
- i2c@f9923000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9923000 0x1000>;
- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c@f9924000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9924000 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp_i2c3: i2c@f9925000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9925000 0x1000>;
- interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp_i2c6: i2c@f9928000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9928000 0x1000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp_i2c8: i2c@f9964000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9964000 0x1000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp_i2c11: i2c@f9967000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9967000 0x1000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
- dma-names = "tx", "rx";
- };
-
- blsp_i2c12: i2c@f9968000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9968000 0x1000>;
- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spmi_bus: spmi@fc4cf000 {
- compatible = "qcom,spmi-pmic-arb";
- reg-names = "core", "intr", "cnfg";
- reg = <0xfc4cf000 0x1000>,
- <0xfc4cb000 0x1000>,
- <0xfc4ca000 0x1000>;
- interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
-
- blsp2_dma: dma-controller@f9944000 {
- compatible = "qcom,bam-v1.4.0";
- reg = <0xf9944000 0x19000>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "bam_clk";
- #dma-cells = <1>;
- qcom,ee = <0>;
- };
-
- etr@fc322000 {
+ etf@fc307000 {
compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0xfc322000 0x1000>;
+ reg = <0xfc307000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint = <&replicator_in>;
+ };
+ };
+ };
+
in-ports {
port {
- etr_in: endpoint {
- remote-endpoint = <&replicator_out0>;
+ etf_in: endpoint {
+ remote-endpoint = <&merger_out>;
};
};
};
@@ -1096,59 +809,39 @@
};
};
- replicator@fc31c000 {
- compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
- reg = <0xfc31c000 0x1000>;
+ funnel@fc31a000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0xfc31a000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- out-ports {
+ in-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
- reg = <0>;
- replicator_out0: endpoint {
- remote-endpoint = <&etr_in>;
- };
- };
- port@1 {
- reg = <1>;
- replicator_out1: endpoint {
- remote-endpoint = <&tpiu_in>;
- };
- };
- };
-
- in-ports {
- port {
- replicator_in: endpoint {
- remote-endpoint = <&etf_out>;
+ /*
+ * Not described input ports:
+ * 0 - not-connected
+ * 1 - connected trought funnel to Multimedia CPU
+ * 2 - connected to Wireless CPU
+ * 3 - not-connected
+ * 4 - not-connected
+ * 6 - not-connected
+ * 7 - connected to STM
+ */
+ port@5 {
+ reg = <5>;
+ funnel1_in5: endpoint {
+ remote-endpoint = <&kpss_out>;
};
};
};
- };
-
- etf@fc307000 {
- compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0xfc307000 0x1000>;
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
out-ports {
port {
- etf_out: endpoint {
- remote-endpoint = <&replicator_in>;
- };
- };
- };
-
- in-ports {
- port {
- etf_in: endpoint {
- remote-endpoint = <&merger_out>;
+ funnel1_out: endpoint {
+ remote-endpoint = <&merger_in1>;
};
};
};
@@ -1188,85 +881,51 @@
};
};
- funnel@fc31a000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0xfc31a000 0x1000>;
+ replicator@fc31c000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0xfc31c000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- in-ports {
+ out-ports {
#address-cells = <1>;
#size-cells = <0>;
- /*
- * Not described input ports:
- * 0 - not-connected
- * 1 - connected trought funnel to Multimedia CPU
- * 2 - connected to Wireless CPU
- * 3 - not-connected
- * 4 - not-connected
- * 6 - not-connected
- * 7 - connected to STM
- */
- port@5 {
- reg = <5>;
- funnel1_in5: endpoint {
- remote-endpoint = <&kpss_out>;
+ port@0 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint = <&tpiu_in>;
};
};
};
- out-ports {
+ in-ports {
port {
- funnel1_out: endpoint {
- remote-endpoint = <&merger_in1>;
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
};
};
};
};
- funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0xfc345000 0x1000>;
+ etr@fc322000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0xfc322000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- kpss_in0: endpoint {
- remote-endpoint = <&etm0_out>;
- };
- };
- port@1 {
- reg = <1>;
- kpss_in1: endpoint {
- remote-endpoint = <&etm1_out>;
- };
- };
- port@2 {
- reg = <2>;
- kpss_in2: endpoint {
- remote-endpoint = <&etm2_out>;
- };
- };
- port@3 {
- reg = <3>;
- kpss_in3: endpoint {
- remote-endpoint = <&etm3_out>;
- };
- };
- };
-
- out-ports {
port {
- kpss_out: endpoint {
- remote-endpoint = <&funnel1_in5>;
+ etr_in: endpoint {
+ remote-endpoint = <&replicator_out0>;
};
};
};
@@ -1344,25 +1003,71 @@
};
};
- ocmem@fdd00000 {
- compatible = "qcom,msm8974-ocmem";
- reg = <0xfdd00000 0x2000>,
- <0xfec00000 0x180000>;
- reg-names = "ctrl",
- "mem";
- clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
- <&mmcc OCMEMCX_OCMEMNOC_CLK>;
- clock-names = "core",
- "iface";
+ /* KPSS funnel, only 4 inputs are used */
+ funnel@fc345000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0xfc345000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- gmu_sram: gmu-sram@0 {
- reg = <0x0 0x100000>;
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ kpss_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ kpss_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ kpss_in2: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ kpss_in3: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ kpss_out: endpoint {
+ remote-endpoint = <&funnel1_in5>;
+ };
+ };
};
};
+ gcc: clock-controller@fc400000 {
+ compatible = "qcom,gcc-msm8974";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xfc400000 0x4000>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>;
+ clock-names = "xo",
+ "sleep_clk";
+ };
+
+ rpm_msg_ram: sram@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
+
bimc: interconnect@fc380000 {
reg = <0xfc380000 0x6a000>;
compatible = "qcom,msm8974-bimc";
@@ -1417,94 +1122,777 @@
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
- gpu: adreno@fdb00000 {
+ tsens: thermal-sensor@fc4a9000 {
+ compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
+ reg = <0xfc4a9000 0x1000>, /* TM */
+ <0xfc4a8000 0x1000>; /* SROT */
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>, <&tsens_base2>,
+ <&tsens_use_backup>,
+ <&tsens_mode_backup>,
+ <&tsens_base1_backup>, <&tsens_base2_backup>,
+ <&tsens_s0_p1>, <&tsens_s0_p2>,
+ <&tsens_s1_p1>, <&tsens_s1_p2>,
+ <&tsens_s2_p1>, <&tsens_s2_p2>,
+ <&tsens_s3_p1>, <&tsens_s3_p2>,
+ <&tsens_s4_p1>, <&tsens_s4_p2>,
+ <&tsens_s5_p1>, <&tsens_s5_p2>,
+ <&tsens_s6_p1>, <&tsens_s6_p2>,
+ <&tsens_s7_p1>, <&tsens_s7_p2>,
+ <&tsens_s8_p1>, <&tsens_s8_p2>,
+ <&tsens_s9_p1>, <&tsens_s9_p2>,
+ <&tsens_s10_p1>, <&tsens_s10_p2>,
+ <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
+ <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
+ <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
+ <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
+ <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
+ <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
+ <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
+ <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
+ <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
+ <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
+ <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
+ nvmem-cell-names = "mode",
+ "base1", "base2",
+ "use_backup",
+ "mode_backup",
+ "base1_backup", "base2_backup",
+ "s0_p1", "s0_p2",
+ "s1_p1", "s1_p2",
+ "s2_p1", "s2_p2",
+ "s3_p1", "s3_p2",
+ "s4_p1", "s4_p2",
+ "s5_p1", "s5_p2",
+ "s6_p1", "s6_p2",
+ "s7_p1", "s7_p2",
+ "s8_p1", "s8_p2",
+ "s9_p1", "s9_p2",
+ "s10_p1", "s10_p2",
+ "s0_p1_backup", "s0_p2_backup",
+ "s1_p1_backup", "s1_p2_backup",
+ "s2_p1_backup", "s2_p2_backup",
+ "s3_p1_backup", "s3_p2_backup",
+ "s4_p1_backup", "s4_p2_backup",
+ "s5_p1_backup", "s5_p2_backup",
+ "s6_p1_backup", "s6_p2_backup",
+ "s7_p1_backup", "s7_p2_backup",
+ "s8_p1_backup", "s8_p2_backup",
+ "s9_p1_backup", "s9_p2_backup",
+ "s10_p1_backup", "s10_p2_backup";
+ #qcom,sensors = <11>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+ #thermal-sensor-cells = <1>;
+ };
+
+ restart@fc4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
+
+ qfprom: qfprom@fc4bc000 {
+ compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
+ reg = <0xfc4bc000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tsens_base1: base1@d0 {
+ reg = <0xd0 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_s0_p1: s0-p1@d1 {
+ reg = <0xd1 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s1_p1: s1-p1@d2 {
+ reg = <0xd1 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s2_p1: s2-p1@d2 {
+ reg = <0xd2 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s3_p1: s3-p1@d3 {
+ reg = <0xd3 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s4_p1: s4-p1@d4 {
+ reg = <0xd4 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s5_p1: s5-p1@d4 {
+ reg = <0xd4 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s6_p1: s6-p1@d5 {
+ reg = <0xd5 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s7_p1: s7-p1@d6 {
+ reg = <0xd6 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s8_p1: s8-p1@d7 {
+ reg = <0xd7 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_mode: mode@d7 {
+ reg = <0xd7 0x1>;
+ bits = <6 2>;
+ };
+
+ tsens_s9_p1: s9-p1@d8 {
+ reg = <0xd8 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s10_p1: s10_p1@d8 {
+ reg = <0xd8 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_base2: base2@d9 {
+ reg = <0xd9 0x2>;
+ bits = <4 8>;
+ };
+
+ tsens_s0_p2: s0-p2@da {
+ reg = <0xda 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s1_p2: s1-p2@db {
+ reg = <0xdb 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s2_p2: s2-p2@dc {
+ reg = <0xdc 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s3_p2: s3-p2@dc {
+ reg = <0xdc 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s4_p2: s4-p2@dd {
+ reg = <0xdd 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s5_p2: s5-p2@de {
+ reg = <0xde 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s6_p2: s6-p2@df {
+ reg = <0xdf 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s7_p2: s7-p2@e0 {
+ reg = <0xe0 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s8_p2: s8-p2@e0 {
+ reg = <0xe0 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s9_p2: s9-p2@e1 {
+ reg = <0xe1 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s10_p2: s10_p2@e2 {
+ reg = <0xe2 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s5_p2_backup: s5-p2_backup@e3 {
+ reg = <0xe3 0x2>;
+ bits = <0 6>;
+ };
+
+ tsens_mode_backup: mode_backup@e3 {
+ reg = <0xe3 0x1>;
+ bits = <6 2>;
+ };
+
+ tsens_s6_p2_backup: s6-p2_backup@e4 {
+ reg = <0xe4 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s7_p2_backup: s7-p2_backup@e4 {
+ reg = <0xe4 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s8_p2_backup: s8-p2_backup@e5 {
+ reg = <0xe5 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s9_p2_backup: s9-p2_backup@e6 {
+ reg = <0xe6 0x2>;
+ bits = <2 6>;
+ };
+
+ tsens_s10_p2_backup: s10_p2_backup@e7 {
+ reg = <0xe7 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_base1_backup: base1_backup@440 {
+ reg = <0x440 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_s0_p1_backup: s0-p1_backup@441 {
+ reg = <0x441 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s1_p1_backup: s1-p1_backup@442 {
+ reg = <0x441 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s2_p1_backup: s2-p1_backup@442 {
+ reg = <0x442 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s3_p1_backup: s3-p1_backup@443 {
+ reg = <0x443 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s4_p1_backup: s4-p1_backup@444 {
+ reg = <0x444 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s5_p1_backup: s5-p1_backup@444 {
+ reg = <0x444 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s6_p1_backup: s6-p1_backup@445 {
+ reg = <0x445 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s7_p1_backup: s7-p1_backup@446 {
+ reg = <0x446 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_use_backup: use_backup@447 {
+ reg = <0x447 0x1>;
+ bits = <5 3>;
+ };
+
+ tsens_s8_p1_backup: s8-p1_backup@448 {
+ reg = <0x448 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s9_p1_backup: s9-p1_backup@448 {
+ reg = <0x448 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s10_p1_backup: s10_p1_backup@449 {
+ reg = <0x449 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_base2_backup: base2_backup@44a {
+ reg = <0x44a 0x2>;
+ bits = <2 8>;
+ };
+
+ tsens_s0_p2_backup: s0-p2_backup@44b {
+ reg = <0x44b 0x3>;
+ bits = <2 6>;
+ };
+
+ tsens_s1_p2_backup: s1-p2_backup@44c {
+ reg = <0x44c 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s2_p2_backup: s2-p2_backup@44c {
+ reg = <0x44c 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s3_p2_backup: s3-p2_backup@44d {
+ reg = <0x44d 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s4_p2_backup: s4-p2_backup@44e {
+ reg = <0x44e 0x1>;
+ bits = <2 6>;
+ };
+ };
+
+ spmi_bus: spmi@fc4cf000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg-names = "core", "intr", "cnfg";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ bam_dmux_dma: dma-controller@fc834000 {
+ compatible = "qcom,bam-v1.4.0";
+ reg = <0xfc834000 0x7000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+
+ num-channels = <6>;
+ qcom,num-ees = <1>;
+ qcom,powered-remotely;
+ };
+
+ remoteproc_mss: remoteproc@fc880000 {
+ compatible = "qcom,msm8974-mss-pil";
+ reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "bus", "mem", "xo";
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
status = "disabled";
- compatible = "qcom,adreno-330.1",
- "qcom,adreno";
- reg = <0xfdb00000 0x10000>;
- reg-names = "kgsl_3d0_reg_memory";
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "kgsl_3d0_irq";
- clock-names = "core",
- "iface",
- "mem_iface";
- clocks = <&mmcc OXILI_GFX3D_CLK>,
- <&mmcc OXILICX_AHB_CLK>,
- <&mmcc OXILICX_AXI_CLK>;
- sram = <&gmu_sram>;
- power-domains = <&mmcc OXILICX_GDSC>;
- operating-points-v2 = <&gpu_opp_table>;
+ mba {
+ memory-region = <&mba_region>;
+ };
- interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
- <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
- interconnect-names = "gfx-mem",
- "ocmem";
+ mpss {
+ memory-region = <&mpss_region>;
+ };
- // iommus = <&gpu_iommu 0>;
+ bam_dmux: bam-dmux {
+ compatible = "qcom,bam-dmux";
- gpu_opp_table: opp_table {
- compatible = "operating-points-v2";
+ interrupt-parent = <&modem_smsm>;
+ interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pc", "pc-ack";
- opp-320000000 {
- opp-hz = /bits/ 64 <320000000>;
+ qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
+ qcom,smem-state-names = "pc", "pc-ack";
+
+ dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
+ dma-names = "tx", "rx";
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 12>;
+ qcom,smd-edge = <0>;
+
+ label = "modem";
+ };
+ };
+
+ tcsr_mutex: hwlock@fd484000 {
+ compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
+ reg = <0xfd484000 0x2000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: syscon@fd4a0000 {
+ compatible = "qcom,tcsr-msm8974", "syscon";
+ reg = <0xfd4a0000 0x10000>;
+ };
+
+ tlmm: pinctrl@fd510000 {
+ compatible = "qcom,msm8974-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 146>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ sdc1_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
};
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
};
- opp-27000000 {
- opp-hz = /bits/ 64 <27000000>;
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
};
};
- };
- mdss: mdss@fd900000 {
- status = "disabled";
+ sdc2_off: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ cd-pins {
+ pins = "gpio54";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ };
+ };
+
+ blsp1_uart2_default: blsp1-uart2-default-state {
+ rx-pins {
+ pins = "gpio5";
+ function = "blsp_uart2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ tx-pins {
+ pins = "gpio4";
+ function = "blsp_uart2";
+ drive-strength = <4>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart1_default: blsp2-uart1-default-state {
+ tx-rts-pins {
+ pins = "gpio41", "gpio44";
+ function = "blsp_uart7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-cts-pins {
+ pins = "gpio42", "gpio43";
+ function = "blsp_uart7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ blsp2_uart1_sleep: blsp2-uart1-sleep-state {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_uart4_default: blsp2-uart4-default-state {
+ tx-rts-pins {
+ pins = "gpio53", "gpio56";
+ function = "blsp_uart10";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-cts-pins {
+ pins = "gpio54", "gpio55";
+ function = "blsp_uart10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ blsp1_i2c1_default: blsp1-i2c1-default-state {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ blsp1_i2c2_default: blsp1-i2c2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ blsp1_i2c3_default: blsp1-i2c3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ /* BLSP1_I2C4 info is missing */
+
+ /* BLSP1_I2C5 info is missing */
+
+ blsp1_i2c6_default: blsp1-i2c6-default-state {
+ pins = "gpio29", "gpio30";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
+ pins = "gpio29", "gpio30";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
+
+ /* BLSP2_I2C1 info is missing */
+
+ blsp2_i2c2_default: blsp2-i2c2-default-state {
+ pins = "gpio47", "gpio48";
+ function = "blsp_i2c8";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
+ pins = "gpio47", "gpio48";
+ function = "blsp_i2c8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ /* BLSP2_I2C3 info is missing */
+
+ /* BLSP2_I2C4 info is missing */
+
+ blsp2_i2c5_default: blsp2-i2c5-default-state {
+ pins = "gpio83", "gpio84";
+ function = "blsp_i2c11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
+ pins = "gpio83", "gpio84";
+ function = "blsp_i2c11";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ blsp2_i2c6_default: blsp2-i2c6-default-state {
+ pins = "gpio87", "gpio88";
+ function = "blsp_i2c12";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
+ pins = "gpio87", "gpio88";
+ function = "blsp_i2c12";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci_default: cci-default-state {
+ cci_i2c0_default: cci-i2c0-default-pins {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c0";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci_i2c1_default: cci-i2c1-default-pins {
+ pins = "gpio21", "gpio22";
+ function = "cci_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cci_sleep: cci-sleep-state {
+ cci_i2c0_sleep: cci-i2c0-sleep-pins {
+ pins = "gpio19", "gpio20";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ cci_i2c1_sleep: cci-i2c1-sleep-pins {
+ pins = "gpio21", "gpio22";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ spi8_default: spi8_default-state {
+ mosi-pins {
+ pins = "gpio45";
+ function = "blsp_spi8";
+ };
+ miso-pins {
+ pins = "gpio46";
+ function = "blsp_spi8";
+ };
+ cs-pins {
+ pins = "gpio47";
+ function = "blsp_spi8";
+ };
+ clk-pins {
+ pins = "gpio48";
+ function = "blsp_spi8";
+ };
+ };
+ };
+
+ mmcc: clock-controller@fd8c0000 {
+ compatible = "qcom,mmcc-msm8974";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xfd8c0000 0x6000>;
+ clocks = <&xo_board>,
+ <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
+ <&gcc GPLL0_VOTE>,
+ <&gcc GPLL1_VOTE>,
+ <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
+ <&dsi0_phy 1>,
+ <&dsi0_phy 0>,
+ <&dsi1_phy 1>,
+ <&dsi1_phy 0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "xo",
+ "mmss_gpll0_vote",
+ "gpll0_vote",
+ "gpll1_vote",
+ "gfx3d_clk_src",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "dsi1pll",
+ "dsi1pllbyte",
+ "hdmipll",
+ "edp_link_clk",
+ "edp_vco_div";
+ };
+
+ mdss: display-subsystem@fd900000 {
compatible = "qcom,mdss";
- reg = <0xfd900000 0x100>,
- <0xfd924000 0x1000>;
- reg-names = "mdss_phys",
- "vbif_phys";
+ reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
+ reg-names = "mdss_phys", "vbif_phys";
power-domains = <&mmcc MDSS_GDSC>;
clocks = <&mmcc MDSS_AHB_CLK>,
- <&mmcc MDSS_AXI_CLK>,
- <&mmcc MDSS_VSYNC_CLK>;
- clock-names = "iface",
- "bus",
- "vsync";
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "vsync";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
+ status = "disabled";
+
#address-cells = <1>;
#size-cells = <1>;
ranges;
- mdp: mdp@fd900000 {
- status = "disabled";
-
- compatible = "qcom,mdp5";
+ mdp: display-controller@fd900000 {
+ compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
reg = <0xfd900100 0x22000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
- interrupts = <0 0>;
+ interrupts = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
- clock-names = "iface",
- "bus",
- "core",
- "vsync";
+ clock-names = "iface", "bus", "core", "vsync";
interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
interconnect-names = "mdp0-mem";
@@ -1519,41 +1907,49 @@
remote-endpoint = <&dsi0_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ mdp5_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
};
};
dsi0: dsi@fd922800 {
- status = "disabled";
-
- compatible = "qcom,mdss-dsi-ctrl";
+ compatible = "qcom,msm8974-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0xfd922800 0x1f8>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <4>;
- assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
- <&mmcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy0 0>,
- <&dsi_phy0 1>;
+ assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
clocks = <&mmcc MDSS_MDP_CLK>,
- <&mmcc MDSS_AHB_CLK>,
- <&mmcc MDSS_AXI_CLK>,
- <&mmcc MDSS_BYTE0_CLK>,
- <&mmcc MDSS_PCLK0_CLK>,
- <&mmcc MDSS_ESC0_CLK>,
- <&mmcc MMSS_MISC_AHB_CLK>;
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>;
clock-names = "mdp_core",
- "iface",
- "bus",
- "byte",
- "pixel",
- "core",
- "core_mmss";
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core",
+ "core_mmss";
+
+ phys = <&dsi0_phy>;
- phys = <&dsi_phy0>;
- phy-names = "dsi-phy";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
ports {
#address-cells = <1>;
@@ -1574,29 +1970,222 @@
};
};
- dsi_phy0: dsi-phy@fd922a00 {
- status = "disabled";
-
+ dsi0_phy: phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x280>,
<0xfd922d80 0x30>;
reg-names = "dsi_pll",
- "dsi_phy",
- "dsi_phy_regulator";
+ "dsi_phy",
+ "dsi_phy_regulator";
#clock-cells = <1>;
#phy-cells = <0>;
- qcom,dsi-phy-index = <0>;
clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ dsi1: dsi@fd922e00 {
+ compatible = "qcom,msm8974-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0xfd922e00 0x1f8>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_BYTE1_CLK>,
+ <&mmcc MDSS_PCLK1_CLK>,
+ <&mmcc MDSS_ESC1_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core",
+ "core_mmss";
+
+ phys = <&dsi1_phy>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&mdp5_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: phy@fd923000 {
+ compatible = "qcom,dsi-phy-28nm-hpm";
+ reg = <0xfd923000 0xd4>,
+ <0xfd923100 0x280>,
+ <0xfd923380 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ cci: cci@fda0c000 {
+ compatible = "qcom,msm8974-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfda0c000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CCI_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cci_default>;
+ pinctrl-1 = <&cci_sleep>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
- imem@fe805000 {
+ gpu: adreno@fdb00000 {
+ compatible = "qcom,adreno-330.1", "qcom,adreno";
+ reg = <0xfdb00000 0x10000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clocks = <&mmcc OXILI_GFX3D_CLK>,
+ <&mmcc OXILICX_AHB_CLK>,
+ <&mmcc OXILICX_AXI_CLK>;
+ clock-names = "core", "iface", "mem_iface";
+
+ sram = <&gmu_sram>;
+ power-domains = <&mmcc OXILICX_GDSC>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
+ <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
+ interconnect-names = "gfx-mem", "ocmem";
+
+ // iommus = <&gpu_iommu 0>;
+
status = "disabled";
- compatible = "syscon", "simple-mfd";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+
+ opp-27000000 {
+ opp-hz = /bits/ 64 <27000000>;
+ };
+ };
+ };
+
+ sram@fdd00000 {
+ compatible = "qcom,msm8974-ocmem";
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x180000>;
+ reg-names = "ctrl", "mem";
+ ranges = <0 0xfec00000 0x180000>;
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&mmcc OCMEMCX_OCMEMNOC_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmu_sram: gmu-sram@0 {
+ reg = <0x0 0x100000>;
+ };
+ };
+
+ remoteproc_adsp: remoteproc@fe200000 {
+ compatible = "qcom,msm8974-adsp-pil";
+ reg = <0xfe200000 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ memory-region = <&adsp_region>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ smd-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 8>;
+ qcom,smd-edge = <1>;
+ label = "lpass";
+ };
+ };
+
+ imem: sram@fe805000 {
+ compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
reg = <0xfe805000 0x1000>;
reboot-mode {
@@ -1606,76 +2195,187 @@
};
};
- smd {
- compatible = "qcom,smd";
+ thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- rpm {
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
- qcom,smd-edge = <15>;
+ thermal-sensors = <&tsens 5>;
- rpm_requests {
- compatible = "qcom,rpm-msm8974";
- qcom,smd-channels = "rpm_requests";
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
- #clock-cells = <1>;
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 6>;
+
+ trips {
+ cpu_alert1: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit1: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ cpu_alert2: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit2: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ cpu_alert3: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit3: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ q6-dsp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ q6_dsp_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ modemtx-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 2>;
+
+ trips {
+ modemtx_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
};
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- pm8841-regulators {
- compatible = "qcom,rpm-pm8841-regulators";
-
- pm8841_s1: s1 {};
- pm8841_s2: s2 {};
- pm8841_s3: s3 {};
- pm8841_s4: s4 {};
- pm8841_s5: s5 {};
- pm8841_s6: s6 {};
- pm8841_s7: s7 {};
- pm8841_s8: s8 {};
- };
-
- pm8941-regulators {
- compatible = "qcom,rpm-pm8941-regulators";
-
- pm8941_s1: s1 {};
- pm8941_s2: s2 {};
- pm8941_s3: s3 {};
-
- pm8941_l1: l1 {};
- pm8941_l2: l2 {};
- pm8941_l3: l3 {};
- pm8941_l4: l4 {};
- pm8941_l5: l5 {};
- pm8941_l6: l6 {};
- pm8941_l7: l7 {};
- pm8941_l8: l8 {};
- pm8941_l9: l9 {};
- pm8941_l10: l10 {};
- pm8941_l11: l11 {};
- pm8941_l12: l12 {};
- pm8941_l13: l13 {};
- pm8941_l14: l14 {};
- pm8941_l15: l15 {};
- pm8941_l16: l16 {};
- pm8941_l17: l17 {};
- pm8941_l18: l18 {};
- pm8941_l19: l19 {};
- pm8941_l20: l20 {};
- pm8941_l21: l21 {};
- pm8941_l22: l22 {};
- pm8941_l23: l23 {};
- pm8941_l24: l24 {};
-
- pm8941_lvs1: lvs1 {};
- pm8941_lvs2: lvs2 {};
- pm8941_lvs3: lvs3 {};
+ thermal-sensors = <&tsens 3>;
+
+ trips {
+ video_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ wlan-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ wlan_alert0: trip-point0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ gpu-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ gpu1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ gpu-bottom-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 10>;
+
+ trips {
+ gpu2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
};
};
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 2 0xf08>,
+ <GIC_PPI 3 0xf08>,
+ <GIC_PPI 4 0xf08>,
+ <GIC_PPI 1 0xf08>;
+ clock-frequency = <19200000>;
+ };
+
vreg_boost: vreg-boost {
compatible = "regulator-fixed";
@@ -1692,6 +2392,7 @@
pinctrl-names = "default";
pinctrl-0 = <&boost_bypass_n_pin>;
};
+
vreg_vph_pwr: vreg-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph-pwr";
diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts
new file mode 100644
index 000000000000..f531d2679f6c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts
@@ -0,0 +1,463 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974pro.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "Fairphone 2";
+ compatible = "fairphone,fp2", "qcom,msm8974pro", "qcom,msm8974";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2;
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ key-camera-snapshot {
+ label = "camera_snapshot";
+ gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_CAMERA>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ key-volume-down {
+ label = "volume_down";
+ gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&pm8941_l18>;
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ touchscreen@41 {
+ compatible = "ilitek,ili2120";
+ reg = <0x41>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&imem {
+ reboot-mode {
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
+ };
+};
+
+&pm8941_gpios {
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio1", "gpio2", "gpio5";
+ function = "normal";
+
+ bias-pull-up;
+ power-source = <PM8941_GPIO_S3>;
+ };
+};
+
+&pm8941_lpg {
+ status = "okay";
+
+ qcom,power-source = <1>;
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@7 {
+ reg = <7>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@6 {
+ reg = <6>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@5 {
+ reg = <5>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pronto {
+ status = "okay";
+
+ vddmx-supply = <&pm8841_s1>;
+ vddcx-supply = <&pm8841_s2>;
+ vddpx-supply = <&pm8941_s3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcnss_pin_a>;
+
+ iris {
+ vddxo-supply = <&pm8941_l6>;
+ vddrfa-supply = <&pm8941_l11>;
+ vddpa-supply = <&pm8941_l19>;
+ vdddig-supply = <&pm8941_s3>;
+ };
+
+ smd-edge {
+ qcom,remote-pid = <4>;
+ label = "pronto";
+
+ wcnss {
+ status = "okay";
+ };
+ };
+};
+
+&remoteproc_adsp {
+ status = "okay";
+ cx-supply = <&pm8841_s2>;
+};
+
+&remoteproc_mss {
+ status = "okay";
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ vdd_l1_l3-supply = <&pm8941_s1>;
+ vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+ vdd_l4_l11-supply = <&pm8941_s1>;
+ vdd_l5_l7-supply = <&pm8941_s2>;
+ vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+ vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
+ vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
+ vdd_l21-supply = <&vreg_boost>;
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ regulator-boot-on;
+ };
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ regulator-boot-on;
+ };
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ vmmc-supply = <&pm8941_l21>;
+ vqmmc-supply = <&pm8941_l13>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_on>;
+ pinctrl-1 = <&sdc2_off>;
+};
+
+&smbb {
+ usb-charge-current-limit = <1500000>;
+ qcom,fast-charge-safe-current = <1500000>;
+ qcom,fast-charge-current-limit = <1500000>;
+ qcom,fast-charge-safe-voltage = <4380000>;
+ qcom,fast-charge-high-threshold-voltage = <4350000>;
+ qcom,auto-recharge-threshold-voltage = <4240000>;
+ qcom,minimum-input-voltage = <4450000>;
+};
+
+&tlmm {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc2_cmd", "sdc2_data";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ wcnss_pin_a: wcnss-pin-active-state {
+ wlan-pins {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "wlan";
+
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ bt-pins {
+ pins = "gpio35", "gpio43", "gpio44";
+ function = "bt";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ fm-pins {
+ pins = "gpio41", "gpio42";
+ function = "fm";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+};
+
+&usb {
+ status = "okay";
+
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+};
+
+&usb_hs1_phy {
+ status = "okay";
+
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts
new file mode 100644
index 000000000000..8d2a054d8fee
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974pro.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "OnePlus One";
+ compatible = "oneplus,bacon", "qcom,msm8974pro", "qcom,msm8974";
+ chassis-type = "handset";
+ qcom,msm-id = <194 0x10000>;
+ qcom,board-id = <8 0>;
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>, <&gpio_hall_sensor_default>;
+ pinctrl-names = "default";
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ debounce-interval = <150>;
+ };
+ };
+};
+
+&blsp1_i2c1 {
+ status = "okay";
+
+ fuel-gauge@55 {
+ compatible = "ti,bq27541";
+ reg = <0x55>;
+ power-supplies = <&bq24196_charger>;
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ rmi4-i2c-dev@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ syna,startup-delay-ms = <100>;
+
+ interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8941_l22>;
+ vio-supply = <&pm8941_lvs3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_default_state>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ /*
+ * Touchscreen size is 2040x1080, y-values between
+ * 1920-2040 are used for touchkey (menu, home & back).
+ * For now clip it off so we don't get touch events
+ * outside of the display area.
+ */
+ syna,clip-y-high = <1920>;
+ };
+ };
+
+ led-controller@36 {
+ compatible = "ti,lm3630a";
+ reg = <0x36>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0 1>;
+ label = "lcd-backlight";
+ default-brightness = <80>;
+ };
+ };
+
+ led-controller@68 {
+ compatible = "si-en,sn3193";
+ reg = <0x68>;
+
+ shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ label = "red:status";
+ led-max-microamp = <17500>;
+ };
+
+ led@2 {
+ reg = <2>;
+ label = "green:status";
+ led-max-microamp = <17500>;
+ };
+
+ led@3 {
+ reg = <3>;
+ label = "blue:status";
+ led-max-microamp = <17500>;
+ };
+ };
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+
+ bq24196_charger: charger@6b {
+ compatible = "ti,bq24196";
+ reg = <0x6b>;
+ interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+ omit-battery-class;
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&gcc {
+ compatible = "qcom,gcc-msm8974pro-ac";
+};
+
+&pm8941_coincell {
+ qcom,rset-ohms = <800>;
+ qcom,vset-millivolts = <3200>;
+
+ status = "okay";
+};
+
+&pm8941_gpios {
+ gpio_keys_default: gpio-keys-active-state {
+ pins = "gpio2", "gpio5";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8941_GPIO_S3>;
+ };
+};
+
+&pm8941_vib {
+ status = "okay";
+};
+
+&pronto {
+ vddmx-supply = <&pm8841_s1>;
+ vddcx-supply = <&pm8841_s2>;
+ vddpx-supply = <&pm8941_s3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcnss_pin_a>;
+
+ status = "okay";
+
+ iris {
+ vddxo-supply = <&pm8941_l6>;
+ vddrfa-supply = <&pm8941_l11>;
+ vddpa-supply = <&pm8941_l19>;
+ vdddig-supply = <&pm8941_s3>;
+ };
+
+ smd-edge {
+ qcom,remote-pid = <4>;
+ label = "pronto";
+
+ wcnss {
+ status = "okay";
+ };
+ };
+};
+
+&remoteproc_adsp {
+ cx-supply = <&pm8841_s2>;
+
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ };
+
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ vdd_l1_l3-supply = <&pm8941_s1>;
+ vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+ vdd_l4_l11-supply = <&pm8941_s1>;
+ vdd_l5_l7-supply = <&pm8941_s2>;
+ vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+ vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>;
+ vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
+ vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
+ vdd_l21-supply = <&vreg_boost>;
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+
+ regulator-boot-on;
+ };
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-system-load = <154000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+ };
+
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-boot-on;
+ };
+
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-boot-on;
+ };
+
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+ };
+
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-boot-on;
+ };
+
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-boot-on;
+ };
+
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-allow-set-load;
+ };
+
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+
+ regulator-boot-on;
+ };
+
+ pm8941_lvs3: lvs3 {};
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
+ pins = "gpio68";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ sdc1_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <4>;
+ bias-pull-up;
+ };
+ };
+
+ touch_default_state: touch-default-state {
+ int-pins {
+ pins = "gpio61";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ reset-pins {
+ pins = "gpio60";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ wcnss_pin_a: wcnss-pin-active-state {
+ wlan-pins {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "wlan";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ bt-pins {
+ pins = "gpio35", "gpio43", "gpio44";
+ function = "bt";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+};
+
+&usb {
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+
+ status = "okay";
+};
+
+&usb_hs1_phy {
+ status = "okay";
+
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
new file mode 100644
index 000000000000..b9698ffb66ca
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974pro.dtsi"
+#include "qcom-pma8084.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Samsung Galaxy S5";
+ compatible = "samsung,klte", "qcom,msm8974pro", "qcom,msm8974";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_3; /* SDC2 SD card slot */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ key-volume-down {
+ label = "volume_down";
+ gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+
+ key-home {
+ label = "home_key";
+ gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_HOMEPAGE>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ i2c-gpio-touchkey {
+ compatible = "i2c-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_touchkey_pins>;
+
+ touchkey@20 {
+ compatible = "cypress,tm2-touchkey";
+ reg = <0x20>;
+
+ interrupt-parent = <&pma8084_gpios>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchkey_pin>;
+
+ vcc-supply = <&max77826_ldo15>;
+ vdd-supply = <&pma8084_l19>;
+
+ linux,keycodes = <KEY_APPSELECT KEY_BACK>;
+ };
+ };
+
+ i2c-gpio-led {
+ compatible = "i2c-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ scl-gpios = <&tlmm 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&tlmm 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_led_gpioex_pins>;
+
+ i2c-gpio,delay-us = <2>;
+
+ gpio_expander: gpio@20 {
+ compatible = "nxp,pcal6416";
+ reg = <0x20>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ vcc-supply = <&pma8084_s4>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpioex_pin>;
+
+ reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+ };
+
+ led-controller@30 {
+ compatible = "panasonic,an30259a";
+ reg = <0x30>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+ };
+
+ vreg_wlan: wlan-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vreg_panel: panel-regulator {
+ compatible = "regulator-fixed";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_en_pin>;
+
+ regulator-name = "panel-vddr-reg";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+
+ gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /delete-node/ vreg-boost;
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupt-parent = <&pma8084_gpios>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&max77826_ldo13>;
+ vio-supply = <&pma8084_lvs2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_pin>;
+
+ syna,startup-delay-ms = <100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+
+ pmic@60 {
+ reg = <0x60>;
+ compatible = "maxim,max77826";
+
+ regulators {
+ max77826_ldo1: LDO1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ max77826_ldo2: LDO2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ max77826_ldo3: LDO3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ max77826_ldo4: LDO4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo5: LDO5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo6: LDO6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo7: LDO7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo8: LDO8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo9: LDO9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo10: LDO10 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ max77826_ldo11: LDO11 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ max77826_ldo12: LDO12 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo13: LDO13 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo14: LDO14 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo15: LDO15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_buck: BUCK {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ max77826_buckboost: BUCKBOOST {
+ regulator-min-microvolt = <3400000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&blsp2_i2c6 {
+ status = "okay";
+
+ fuelgauge@36 {
+ compatible = "maxim,max17048";
+ reg = <0x36>;
+
+ maxim,double-soc;
+ maxim,rcomp = /bits/ 8 <0x56>;
+
+ interrupt-parent = <&pma8084_gpios>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fuelgauge_pin>;
+ };
+};
+
+&blsp2_uart2 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart2_pins_active>;
+ pinctrl-1 = <&blsp2_uart2_pins_sleep>;
+
+ bluetooth {
+ compatible = "brcm,bcm43540-bt";
+ max-speed = <3000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pins>;
+ device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wakeup";
+ };
+};
+
+&dsi0 {
+ status = "okay";
+
+ vdda-supply = <&pma8084_l2>;
+ vdd-supply = <&pma8084_l22>;
+ vddio-supply = <&pma8084_l12>;
+
+ panel: panel@0 {
+ reg = <0>;
+ compatible = "samsung,s6e3fa2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_te_pin &panel_rst_pin>;
+
+ iovdd-supply = <&pma8084_lvs4>;
+ vddr-supply = <&vreg_panel>;
+
+ reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>;
+ te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+};
+
+&dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&dsi0_phy {
+ status = "okay";
+
+ vddio-supply = <&pma8084_l12>;
+};
+
+&gpu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&pma8084_gpios {
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio2", "gpio3", "gpio5";
+ function = "normal";
+
+ bias-pull-up;
+ power-source = <PMA8084_GPIO_S4>;
+ };
+
+ touchkey_pin: touchkey-int-state {
+ pins = "gpio6";
+ function = "normal";
+ bias-disable;
+ input-enable;
+ power-source = <PMA8084_GPIO_S4>;
+ };
+
+ touch_pin: touchscreen-int-state {
+ pins = "gpio8";
+ function = "normal";
+ bias-disable;
+ input-enable;
+ power-source = <PMA8084_GPIO_S4>;
+ };
+
+ panel_en_pin: panel-en-state {
+ pins = "gpio14";
+ function = "normal";
+ bias-pull-up;
+ power-source = <PMA8084_GPIO_S4>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ };
+
+ wlan_sleep_clk_pin: wlan-sleep-clk-state {
+ pins = "gpio16";
+ function = "func2";
+
+ output-high;
+ power-source = <PMA8084_GPIO_S4>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ };
+
+ panel_rst_pin: panel-rst-state {
+ pins = "gpio17";
+ function = "normal";
+ bias-disable;
+ power-source = <PMA8084_GPIO_S4>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ };
+
+ fuelgauge_pin: fuelgauge-int-state {
+ pins = "gpio21";
+ function = "normal";
+ bias-disable;
+ input-enable;
+ power-source = <PMA8084_GPIO_S4>;
+ };
+};
+
+&remoteproc_adsp {
+ status = "okay";
+ cx-supply = <&pma8084_s2>;
+};
+
+&remoteproc_mss {
+ status = "okay";
+ cx-supply = <&pma8084_s2>;
+ mss-supply = <&pma8084_s6>;
+ mx-supply = <&pma8084_s1>;
+ pll-supply = <&pma8084_l12>;
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pma8084-regulators";
+
+ pma8084_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ };
+
+ pma8084_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pma8084_s3: s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pma8084_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_s5: s5 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+
+ pma8084_s6: s6 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pma8084_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pma8084_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pma8084_l3: l3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pma8084_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pma8084_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pma8084_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pma8084_l11: l11 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pma8084_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pma8084_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pma8084_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pma8084_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pma8084_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pma8084_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pma8084_l19: l19 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pma8084_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pma8084_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pma8084_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pma8084_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pma8084_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pma8084_l25: l25 {
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ pma8084_l26: l26 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pma8084_l27: l27 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pma8084_lvs1: lvs1 {};
+ pma8084_lvs2: lvs2 {};
+ pma8084_lvs3: lvs3 {};
+ pma8084_lvs4: lvs4 {};
+
+ pma8084_5vs1: 5vs1 {};
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pma8084_l20>;
+ vqmmc-supply = <&pma8084_s4>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
+ max-frequency = <100000000>;
+ vmmc-supply = <&vreg_wlan>;
+ vqmmc-supply = <&pma8084_s4>;
+ non-removable;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_on>;
+ pinctrl-1 = <&sdc2_off>;
+
+ wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>;
+ };
+};
+
+&sdhc_3 {
+ status = "okay";
+ max-frequency = <100000000>;
+ vmmc-supply = <&pma8084_l21>;
+ vqmmc-supply = <&pma8084_l13>;
+
+ /*
+ * cd-gpio is intentionally disabled. If enabled, an SD card
+ * present during boot is not initialized correctly. Without
+ * cd-gpios the driver resorts to polling, so hotplug works.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>;
+ /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */
+};
+
+&tlmm {
+ /* This seems suspicious, but somebody with this device should look into it. */
+ blsp2_uart2_pins_active: blsp2-uart2-pins-active-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ function = "blsp_uart8";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ bt_pins: bt-pins-state {
+ hostwake-pins {
+ pins = "gpio75";
+ function = "gpio";
+ drive-strength = <16>;
+ input-enable;
+ };
+
+ devwake-pins {
+ pins = "gpio91";
+ function = "gpio";
+ drive-strength = <2>;
+ };
+ };
+
+ sdc1_on: sdhc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <4>;
+ bias-pull-up;
+ };
+ };
+
+ sdc3_on: sdc3-on-state {
+ pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "sdc3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ sdhc3_cd_pin: sdc3-cd-on-state {
+ pins = "gpio62";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_on: sdhc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc2_cmd", "sdc2_data";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ i2c_touchkey_pins: i2c-touchkey-state {
+ pins = "gpio95", "gpio96";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
+ };
+
+ i2c_led_gpioex_pins: i2c-led-gpioex-state {
+ pins = "gpio120", "gpio121";
+ function = "gpio";
+ input-enable;
+ bias-pull-down;
+ };
+
+ gpioex_pin: gpioex-state {
+ pins = "gpio145";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ wifi_pin: wifi-state {
+ pins = "gpio92";
+ function = "gpio";
+ input-enable;
+ bias-pull-down;
+ };
+
+ panel_te_pin: panel-state {
+ pins = "gpio12";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&usb {
+ status = "okay";
+
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+};
+
+&usb_hs1_phy {
+ status = "okay";
+
+ v1p8-supply = <&pma8084_l6>;
+ v3p3-supply = <&pma8084_l24>;
+
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
new file mode 100644
index 000000000000..04bc58d87abf
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974pro.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "Sony Xperia Z2 Tablet";
+ compatible = "sony,xperia-castor", "qcom,msm8974pro", "qcom,msm8974";
+ chassis-type = "tablet";
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ serial1 = &blsp2_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ key-volume-down {
+ label = "volume_down";
+ gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ key-camera-snapshot {
+ label = "camera_snapshot";
+ gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA>;
+ };
+
+ key-camera-focus {
+ label = "camera_focus";
+ gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ };
+
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ vreg_bl_vddio: lcd-backlight-vddio {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_bl_vddio";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ gpio = <&tlmm 69 0>;
+ enable-active-high;
+
+ vin-supply = <&pm8941_s3>;
+ startup-delay-us = <70000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_backlight_en_pin_a>;
+ };
+
+ vreg_vsp: lcd-dcdc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_vsp";
+ regulator-min-microvolt = <5600000>;
+ regulator-max-microvolt = <5600000>;
+
+ gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_dcdc_en_pin_a>;
+ };
+
+ vreg_wlan: wlan-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_regulator_pin>;
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&blsp2_i2c2 {
+ status = "okay";
+ clock-frequency = <355000>;
+
+ synaptics@2c {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x2c>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <86 IRQ_TYPE_EDGE_FALLING>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd-supply = <&pm8941_l22>;
+ vio-supply = <&pm8941_lvs3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_pin>;
+
+ syna,startup-delay-ms = <100>;
+
+ rmi-f01@1 {
+ reg = <0x1>;
+ syna,nosleep = <1>;
+ };
+
+ rmi-f11@11 {
+ reg = <0x11>;
+ syna,f11-flip-x = <1>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp2_i2c5 {
+ status = "okay";
+ clock-frequency = <355000>;
+
+ lp8566_wled: backlight@2c {
+ compatible = "ti,lp8556";
+ reg = <0x2c>;
+ power-supply = <&vreg_bl_vddio>;
+
+ bl-name = "backlight";
+ dev-ctrl = /bits/ 8 <0x05>;
+ init-brt = /bits/ 8 <0x3f>;
+ rom_a0h {
+ rom-addr = /bits/ 8 <0xa0>;
+ rom-val = /bits/ 8 <0xff>;
+ };
+ rom_a1h {
+ rom-addr = /bits/ 8 <0xa1>;
+ rom-val = /bits/ 8 <0x3f>;
+ };
+ rom_a2h {
+ rom-addr = /bits/ 8 <0xa2>;
+ rom-val = /bits/ 8 <0x20>;
+ };
+ rom_a3h {
+ rom-addr = /bits/ 8 <0xa3>;
+ rom-val = /bits/ 8 <0x5e>;
+ };
+ rom_a4h {
+ rom-addr = /bits/ 8 <0xa4>;
+ rom-val = /bits/ 8 <0x02>;
+ };
+ rom_a5h {
+ rom-addr = /bits/ 8 <0xa5>;
+ rom-val = /bits/ 8 <0x04>;
+ };
+ rom_a6h {
+ rom-addr = /bits/ 8 <0xa6>;
+ rom-val = /bits/ 8 <0x80>;
+ };
+ rom_a7h {
+ rom-addr = /bits/ 8 <0xa7>;
+ rom-val = /bits/ 8 <0xf7>;
+ };
+ rom_a9h {
+ rom-addr = /bits/ 8 <0xa9>;
+ rom-val = /bits/ 8 <0x80>;
+ };
+ rom_aah {
+ rom-addr = /bits/ 8 <0xaa>;
+ rom-val = /bits/ 8 <0x0f>;
+ };
+ rom_aeh {
+ rom-addr = /bits/ 8 <0xae>;
+ rom-val = /bits/ 8 <0x0f>;
+ };
+ };
+};
+
+&blsp2_uart1 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_pin>, <&bt_dev_wake_pin>, <&bt_reg_on_pin>;
+
+ host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&pm8941_coincell {
+ status = "okay";
+
+ qcom,rset-ohms = <2100>;
+ qcom,vset-millivolts = <3000>;
+};
+
+&pm8941_gpios {
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio2", "gpio5";
+ function = "normal";
+
+ bias-pull-up;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ bt_reg_on_pin: bt-reg-on-state {
+ pins = "gpio16";
+ function = "normal";
+
+ output-low;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ wlan_sleep_clk_pin: wl-sleep-clk-state {
+ pins = "gpio17";
+ function = "func2";
+
+ output-high;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ wlan_regulator_pin: wl-reg-active-state {
+ pins = "gpio18";
+ function = "normal";
+
+ bias-disable;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state {
+ pins = "gpio20";
+ function = "normal";
+
+ bias-disable;
+ power-source = <PM8941_GPIO_S3>;
+ input-disable;
+ output-low;
+ };
+
+};
+
+&pm8941_lpg {
+ status = "okay";
+
+ qcom,power-source = <1>;
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@5 {
+ reg = <5>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ led@6 {
+ reg = <6>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@7 {
+ reg = <7>;
+ color = <LED_COLOR_ID_RED>;
+ };
+ };
+};
+
+&remoteproc_adsp {
+ cx-supply = <&pm8841_s2>;
+};
+
+&remoteproc_mss {
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s4: s4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ vdd_l1_l3-supply = <&pm8941_s1>;
+ vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+ vdd_l4_l11-supply = <&pm8941_s1>;
+ vdd_l5_l7-supply = <&pm8941_s2>;
+ vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+ vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
+ vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
+ vdd_l21-supply = <&vreg_boost>;
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ regulator-boot-on;
+ };
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-system-load = <154000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s4: s4 {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <500000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ regulator-boot-on;
+ };
+
+ pm8941_lvs3: lvs3 {};
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ vmmc-supply = <&pm8941_l21>;
+ vqmmc-supply = <&pm8941_l13>;
+
+ cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_on>;
+ pinctrl-1 = <&sdc2_off>;
+};
+
+&sdhc_3 {
+ status = "okay";
+
+ max-frequency = <100000000>;
+ vmmc-supply = <&vreg_wlan>;
+ non-removable;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdc3_on>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bcrmf@1 {
+ compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ brcm,drive-strength = <10>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_sleep_clk_pin>;
+ };
+};
+
+&smbb {
+ qcom,fast-charge-safe-current = <1500000>;
+ qcom,fast-charge-current-limit = <1500000>;
+ qcom,dc-current-limit = <1800000>;
+ usb-charge-current-limit = <1800000>;
+ qcom,fast-charge-safe-voltage = <4400000>;
+ qcom,fast-charge-high-threshold-voltage = <4350000>;
+ qcom,fast-charge-low-threshold-voltage = <3400000>;
+ qcom,auto-recharge-threshold-voltage = <4200000>;
+ qcom,minimum-input-voltage = <4300000>;
+};
+
+&tlmm {
+ lcd_backlight_en_pin_a: lcd-backlight-vddio-state {
+ pins = "gpio69";
+ function = "gpio";
+ drive-strength = <10>;
+ output-low;
+ bias-disable;
+ };
+
+ sdc1_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc2_cmd", "sdc2_data";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ cd-pins {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ sdc3_on: sdc3-on-state {
+ clk-pins {
+ pins = "gpio40";
+ function = "sdc3";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio39";
+ function = "sdc3";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio35", "gpio36", "gpio37", "gpio38";
+ function = "sdc3";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ ts_int_pin: ts-int-pin-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ bt_host_wake_pin: bt-host-wake-state {
+ pins = "gpio95";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ bt_dev_wake_pin: bt-dev-wake-state {
+ pins = "gpio96";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&usb {
+ status = "okay";
+
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+};
+
+&usb_hs1_phy {
+ status = "okay";
+
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi
index b64c28036dd0..58df6e75ab6d 100644
--- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi
@@ -1,23 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974.dtsi"
-/ {
- soc {
- sdhci@f9824900 {
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
- <&xo_board>,
- <&gcc GCC_SDCC1_CDCCAL_FF_CLK>,
- <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>;
- clock-names = "core", "iface", "xo", "cal", "sleep";
- };
+&gcc {
+ compatible = "qcom,gcc-msm8974pro";
+};
- clock-controller@fc400000 {
- compatible = "qcom,gcc-msm8974pro";
- };
+&gpu {
+ compatible = "qcom,adreno-330.2", "qcom,adreno";
+};
- adreno@fdb00000 {
- compatible = "qcom,adreno-330.2",
- "qcom,adreno";
- };
- };
+&sdhc_1 {
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>,
+ <&gcc GCC_SDCC1_CDCCAL_FF_CLK>,
+ <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>;
+ clock-names = "iface", "core", "xo", "cal", "sleep";
};
diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi
index b3d0f7b5874d..46ba84f86c9f 100644
--- a/arch/arm/boot/dts/qcom-pm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8226.dtsi
@@ -1,4 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
@@ -9,12 +11,25 @@
#address-cells = <1>;
#size-cells = <0>;
- pwrkey@800 {
- compatible = "qcom,pm8941-pwrkey";
+ pon@800 {
+ compatible = "qcom,pm8916-pon";
reg = <0x800>;
- interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+ };
+
+ pm8226_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
};
smbb: charger@1000 {
@@ -40,6 +55,52 @@
chg_otg: otg-vbus { };
};
+ pm8226_vadc: adc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ adc-chan@7 {
+ reg = <VADC_VSYS>;
+ qcom,pre-scaling = <1 3>;
+ label = "vph_pwr";
+ };
+ adc-chan@8 {
+ reg = <VADC_DIE_TEMP>;
+ label = "die_temp";
+ };
+ adc-chan@9 {
+ reg = <VADC_REF_625MV>;
+ label = "ref_625mv";
+ };
+ adc-chan@a {
+ reg = <VADC_REF_1250MV>;
+ label = "ref_1250mv";
+ };
+ adc-chan@e {
+ reg = <VADC_GND_REF>;
+ };
+ adc-chan@f {
+ reg = <VADC_VDD_VADC>;
+ };
+ };
+
+ pm8226_iadc: adc@3600 {
+ compatible = "qcom,pm8226-iadc", "qcom,spmi-iadc";
+ reg = <0x3600>;
+ interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
pm8226_mpps: mpps@a000 {
compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
@@ -49,6 +110,16 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ pm8226_gpios: gpio@c000 {
+ compatible = "qcom,pm8226-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8226_gpios 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
pm8226_1: pm8226@1 {
@@ -57,7 +128,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pm8226_spmi_regulators: pm8226-regulators {
+ pm8226_spmi_regulators: regulators {
compatible = "qcom,pm8226-regulators";
};
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi
index 2caf71eacb52..b5cdde034d18 100644
--- a/arch/arm/boot/dts/qcom-pm8841.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -24,6 +24,7 @@
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <0>;
};
};
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
index da00b8f5eecd..a821f0368a28 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -27,7 +27,7 @@
bias-pull-up;
};
- usb_id: misc@900 {
+ usb_id: usb-detect@900 {
compatible = "qcom,pm8941-misc";
reg = <0x900>;
interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
@@ -59,7 +59,7 @@
chg_otg: otg-vbus { };
};
- pm8941_gpios: gpios@c000 {
+ pm8941_gpios: gpio@c000 {
compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
@@ -68,7 +68,7 @@
interrupt-controller;
#interrupt-cells = <2>;
- boost_bypass_n_pin: boost-bypass {
+ boost_bypass_n_pin: boost-bypass-state {
pins = "gpio21";
function = "normal";
};
@@ -93,7 +93,7 @@
#thermal-sensor-cells = <0>;
};
- pm8941_vadc: vadc@3100 {
+ pm8941_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
@@ -101,37 +101,44 @@
#size-cells = <0>;
#io-channel-cells = <1>;
- bat_temp {
- reg = <VADC_LR_MUX1_BAT_THERM>;
+
+ adc-chan@6 {
+ reg = <VADC_VBAT_SNS>;
};
- die_temp {
+
+ adc-chan@8 {
reg = <VADC_DIE_TEMP>;
};
- ref_625mv {
+
+ adc-chan@9 {
reg = <VADC_REF_625MV>;
};
- ref_1250v {
+
+ adc-chan@a {
reg = <VADC_REF_1250MV>;
};
- ref_gnd {
+
+ adc-chan@e {
reg = <VADC_GND_REF>;
};
- ref_vdd {
+
+ adc-chan@f {
reg = <VADC_VDD_VADC>;
};
- vbat_sns {
- reg = <VADC_VBAT_SNS>;
+
+ adc-chan@30 {
+ reg = <VADC_LR_MUX1_BAT_THERM>;
};
};
- pm8941_iadc: iadc@3600 {
+ pm8941_iadc: adc@3600 {
compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc";
reg = <0x3600>;
interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
qcom,external-resistor-micro-ohms = <10000>;
};
- coincell@2800 {
+ pm8941_coincell: charger@2800 {
compatible = "qcom,pm8941-coincell";
reg = <0x2800>;
status = "disabled";
@@ -144,6 +151,22 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm8941_lpg: pwm {
+ compatible = "qcom,pm8941-lpg";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pwm-cells = <2>;
+
+ status = "disabled";
+ };
+
+ pm8941_vib: vibrator@c000 {
+ compatible = "qcom,pm8916-vib";
+ reg = <0xc000>;
+ status = "disabled";
+ };
+
pm8941_wled: wled@d800 {
compatible = "qcom,pm8941-wled";
reg = <0xd800>;
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi
index 7b8a8d9695da..2dd4c6aa71c9 100644
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -27,7 +27,7 @@
bias-pull-up;
};
- pma8084_gpios: gpios@c000 {
+ pma8084_gpios: gpio@c000 {
compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
@@ -56,7 +56,7 @@
io-channel-names = "thermal";
};
- pma8084_vadc: vadc@3100 {
+ pma8084_vadc: adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
@@ -64,22 +64,27 @@
#size-cells = <0>;
#io-channel-cells = <1>;
- die_temp {
+ adc-chan@8 {
reg = <VADC_DIE_TEMP>;
};
- ref_625mv {
+
+ adc-chan@9 {
reg = <VADC_REF_625MV>;
};
- ref_1250v {
+
+ adc-chan@a {
reg = <VADC_REF_1250MV>;
};
- ref_buf_625mv {
+
+ adc-chan@c {
reg = <VADC_SPARE1>;
};
- ref_gnd {
+
+ adc-chan@e {
reg = <VADC_GND_REF>;
};
- ref_vdd {
+
+ adc-chan@f {
reg = <VADC_VDD_VADC>;
};
};
diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom-pmx55.dtsi
index 6571b88d018a..e1b869480bbd 100644
--- a/arch/arm/boot/dts/qcom-pmx55.dtsi
+++ b/arch/arm/boot/dts/qcom-pmx55.dtsi
@@ -16,7 +16,7 @@
#address-cells = <1>;
#size-cells = <0>;
- power-on@800 {
+ pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
@@ -69,6 +69,7 @@
compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
+ gpio-ranges = <&pmx55_gpios 0 0 11>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi
new file mode 100644
index 000000000000..1c7fdf59c1f5
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pmx65.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pmic@1 {
+ compatible = "qcom,pmx65", "qcom,spmi-pmic";
+ reg = <1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmx65_temp: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmx65_gpios: gpio@8800 {
+ compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmx65_gpios 0 0 16>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts
index 9649c1e11311..7e97ad5803d8 100644
--- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts
@@ -75,7 +75,7 @@
};
&apps_rsc {
- pmx55-rpmh-regulators {
+ regulators-0 {
compatible = "qcom,pmx55-rpmh-regulators";
qcom,pmic-id = "e";
@@ -229,6 +229,10 @@
};
};
+&remoteproc_mpss {
+ memory-region = <&mpss_adsp_mem>;
+};
+
&usb {
status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts
index 7ed8feb99afb..51058b065279 100644
--- a/arch/arm/boot/dts/qcom-sdx55-t55.dts
+++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts
@@ -98,7 +98,7 @@
};
&apps_rsc {
- pmx55-rpmh-regulators {
+ regulators-0 {
compatible = "qcom,pmx55-rpmh-regulators";
qcom,pmic-id = "e";
@@ -233,21 +233,38 @@
};
&blsp1_uart3 {
- status = "ok";
+ status = "okay";
};
&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
status = "okay";
+};
- memory-region = <&ipa_fw_mem>;
+&pcie_phy {
+ vdda-phy-supply = <&vreg_l1e_bb_1p2>;
+ vdda-pll-supply = <&vreg_l4e_bb_0p875>;
+
+ status = "okay";
+};
+
+&pcie_rc {
+ perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
};
&qpic_bam {
- status = "ok";
+ status = "okay";
};
&qpic_nand {
- status = "ok";
+ status = "okay";
nand@0 {
reg = <0>;
@@ -261,21 +278,48 @@
};
&remoteproc_mpss {
- status = "okay";
memory-region = <&mpss_adsp_mem>;
+ status = "okay";
+};
+
+&tlmm {
+ pcie_default: pcie-default-state {
+ clkreq-pins {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-pins {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-pins {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
&usb_hsphy {
- status = "okay";
vdda-pll-supply = <&vreg_l4e_bb_0p875>;
vdda33-supply = <&vreg_l10e_3p1>;
vdda18-supply = <&vreg_l5e_bb_1p7>;
+
+ status = "okay";
};
&usb_qmpphy {
- status = "okay";
vdda-phy-supply = <&vreg_l4e_bb_0p875>;
vdda-pll-supply = <&vreg_l1e_bb_1p2>;
+
+ status = "okay";
};
&usb {
diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
index a4fa468a095f..8fadc6e70692 100644
--- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
+++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
@@ -98,7 +98,7 @@
};
&apps_rsc {
- pmx55-rpmh-regulators {
+ regulators-0 {
compatible = "qcom,pmx55-rpmh-regulators";
qcom,pmic-id = "e";
@@ -233,36 +233,39 @@
};
&blsp1_uart3 {
- status = "ok";
+ status = "okay";
};
&ipa {
- status = "okay";
-
+ qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
-};
-
-&pcie0_phy {
status = "okay";
+};
+&pcie_phy {
vdda-phy-supply = <&vreg_l1e_bb_1p2>;
vdda-pll-supply = <&vreg_l4e_bb_0p875>;
-};
-&pcie_ep {
status = "okay";
+};
+&pcie_ep {
pinctrl-names = "default";
pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
&pcie_ep_wake_default>;
+
+ reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
};
&qpic_bam {
- status = "ok";
+ status = "okay";
};
&qpic_nand {
- status = "ok";
+ status = "okay";
nand@0 {
reg = <0>;
@@ -277,59 +280,46 @@
};
&remoteproc_mpss {
- status = "okay";
memory-region = <&mpss_adsp_mem>;
+ status = "okay";
};
&tlmm {
- pcie_ep_clkreq_default: pcie_ep_clkreq_default {
- mux {
- pins = "gpio56";
- function = "pcie_clkreq";
- };
- config {
- pins = "gpio56";
- drive-strength = <2>;
- bias-disable;
- };
+ pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ drive-strength = <2>;
+ bias-disable;
};
- pcie_ep_perst_default: pcie_ep_perst_default {
- mux {
- pins = "gpio57";
- function = "gpio";
- };
- config {
- pins = "gpio57";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pcie_ep_perst_default: pcie-ep-perst-default-state {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
};
- pcie_ep_wake_default: pcie_ep_wake_default {
- mux {
- pins = "gpio53";
- function = "gpio";
- };
- config {
- pins = "gpio53";
- drive-strength = <2>;
- bias-disable;
- };
+ pcie_ep_wake_default: pcie-ep-wake-default-state {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
&usb_hsphy {
- status = "okay";
vdda-pll-supply = <&vreg_l4e_bb_0p875>;
vdda33-supply = <&vreg_l10e_3p1>;
vdda18-supply = <&vreg_l5e_bb_1p7>;
+
+ status = "okay";
};
&usb_qmpphy {
- status = "okay";
vdda-phy-supply = <&vreg_l4e_bb_0p875>;
vdda-pll-supply = <&vreg_l1e_bb_1p2>;
+
+ status = "okay";
};
&usb {
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index d455795da44c..342c3d14001e 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -62,7 +62,13 @@
};
};
- cpu_opp_table: cpu-opp-table {
+ firmware {
+ scm {
+ compatible = "qcom,scm-sdx55", "qcom,scm";
+ };
+ };
+
+ cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -87,12 +93,6 @@
};
};
- firmware {
- scm {
- compatible = "qcom,scm-sdx55", "qcom,scm";
- };
- };
-
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -206,7 +206,7 @@
blsp1_uart3: serial@831000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x00831000 0x200>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc 30>,
<&gcc 9>;
clock-names = "core", "iface";
@@ -214,7 +214,8 @@
};
usb_hsphy: phy@ff4000 {
- compatible = "qcom,usb-snps-hs-7nm-phy";
+ compatible = "qcom,sdx55-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
reg = <0x00ff4000 0x114>;
status = "disabled";
#phy-cells = <0>;
@@ -275,13 +276,6 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- ipa_virt: interconnect@1e00000 {
- compatible = "qcom,sdx55-ipa-virt";
- reg = <0x01e00000 0x100000>;
- #interconnect-cells = <1>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
qpic_bam: dma-controller@1b04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x01b04000 0x1c000>;
@@ -310,7 +304,135 @@
status = "disabled";
};
- pcie0_phy: phy@1c07000 {
+ pcie_rc: pcie@1c00000 {
+ compatible = "qcom,pcie-sdx55";
+ reg = <0x01c00000 0x3000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xc8>,
+ <0x40001000 0x1000>,
+ <0x40100000 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
+
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "msi8";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_PIPE_CLK>,
+ <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep";
+
+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
+ <0x100 &apps_smmu 0x0201 0x1>,
+ <0x200 &apps_smmu 0x0202 0x1>,
+ <0x300 &apps_smmu 0x0203 0x1>,
+ <0x400 &apps_smmu 0x0204 0x1>;
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ phys = <&pcie_lane>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie_ep: pcie-ep@1c00000 {
+ compatible = "qcom,sdx55-pcie-ep";
+ reg = <0x01c00000 0x3000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xc8>,
+ <0x40001000 0x1000>,
+ <0x40200000 0x100000>,
+ <0x01c03000 0x3000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "addr_space",
+ "mmio";
+
+ qcom,perst-regs = <&tcsr 0xb258 0xb270>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep",
+ "ref";
+
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global",
+ "doorbell";
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE_GDSC>;
+ phys = <&pcie_lane>;
+ phy-names = "pciephy";
+ max-link-speed = <3>;
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
+ pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
reg = <0x01c07000 0x1c4>;
#address-cells = <1>;
@@ -320,7 +442,10 @@
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen";
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";
@@ -330,7 +455,7 @@
status = "disabled";
- pcie0_lane: lanes@1c06000 {
+ pcie_lane: lanes@1c06000 {
reg = <0x01c06000 0x104>, /* tx0 */
<0x01c06200 0x328>, /* rx0 */
<0x01c07200 0x1e8>, /* pcs */
@@ -391,11 +516,11 @@
};
tcsr: syscon@1fcb000 {
- compatible = "syscon";
+ compatible = "qcom,sdx55-tcsr", "syscon";
reg = <0x01fc0000 0x1000>;
};
- sdhc_1: sdhci@8804000 {
+ sdhc_1: mmc@8804000 {
compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
@@ -407,45 +532,6 @@
status = "disabled";
};
- pcie_ep: pcie-ep@40000000 {
- compatible = "qcom,sdx55-pcie-ep";
- reg = <0x01c00000 0x3000>,
- <0x40000000 0xf1d>,
- <0x40000f20 0xc8>,
- <0x40001000 0x1000>,
- <0x40200000 0x100000>,
- <0x01c03000 0x3000>;
- reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
- "mmio";
-
- qcom,perst-regs = <&tcsr 0xb258 0xb270>;
-
- clocks = <&gcc GCC_PCIE_AUX_CLK>,
- <&gcc GCC_PCIE_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_SLV_AXI_CLK>,
- <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
- <&gcc GCC_PCIE_SLEEP_CLK>,
- <&gcc GCC_PCIE_0_CLKREF_CLK>;
- clock-names = "aux", "cfg", "bus_master", "bus_slave",
- "slave_q2a", "sleep", "ref";
-
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global", "doorbell";
- reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
- resets = <&gcc GCC_PCIE_BCR>;
- reset-names = "core";
- power-domains = <&gcc PCIE_GDSC>;
- phys = <&pcie0_lane>;
- phy-names = "pciephy";
- max-link-speed = <3>;
- num-lanes = <2>;
-
- status = "disabled";
- };
-
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sdx55-mpss-pas";
reg = <0x04080000 0x4040>;
@@ -490,10 +576,13 @@
clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_USB30_MSTR_AXI_CLK>,
- <&gcc GCC_USB30_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_SLEEP_CLK>;
- clock-names = "cfg_noc", "core", "iface", "mock_utmi",
- "sleep";
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
@@ -563,10 +652,11 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 108>;
};
- imem@1468f000 {
- compatible = "simple-mfd";
+ sram@1468f000 {
+ compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
reg = <0x1468f000 0x1000>;
#address-cells = <1>;
@@ -581,7 +671,7 @@
};
apps_smmu: iommu@15000000 {
- compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
+ compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x15000000 0x20000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
@@ -770,7 +860,7 @@
};
};
- apps_bcm_voter: bcm_voter {
+ apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
};
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 59457da8e5f1..57bc3b03d3aa 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -5,6 +5,10 @@
/dts-v1/;
#include "qcom-sdx65.dtsi"
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <arm64/qcom/pmk8350.dtsi>
+#include <arm64/qcom/pm8150b.dtsi>
+#include "qcom-pmx65.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDX65 MTP";
@@ -18,8 +22,275 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mpss_dsm: memory@8c400000 {
+ no-map;
+ reg = <0x8c400000 0x3200000>;
+ };
+
+ ipa_fw_mem: memory@8fced000 {
+ no-map;
+ reg = <0x8fced000 0x10000>;
+ };
+
+ mpss_adsp_mem: memory@90800000 {
+ no-map;
+ reg = <0x90800000 0x10000000>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ vreg_bob_3p3: pmx65_bob {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_bob_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pmx65-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-supply = <&vreg_s2b_1p224>;
+ vdd-l2-l18-supply = <&vreg_s2b_1p224>;
+ vdd-l3-supply = <&vreg_s8b_0p824>;
+ vdd-l4-supply = <&vreg_s7b_0p936>;
+ vdd-l5-l6-l16-supply = <&vreg_s4b_1p824>;
+ vdd-l7-supply = <&vreg_s3b_0p776>;
+ vdd-l8-l9-supply = <&vreg_s8b_0p824>;
+ vdd-l10-supply = <&vreg_bob_3p3>;
+ vdd-l11-l13-supply = <&vreg_bob_3p3>;
+ vdd-l12-supply = <&vreg_s2b_1p224>;
+ vdd-l14-supply = <&vreg_s3b_0p776>;
+ vdd-l15-supply = <&vreg_s2b_1p224>;
+ vdd-l17-supply = <&vreg_s8b_0p824>;
+ vdd-l19-supply = <&vreg_s3b_0p776>;
+ vdd-l20-supply = <&vreg_s7b_0p936>;
+ vdd-l21-supply = <&vreg_s7b_0p936>;
+
+ vreg_s2b_1p224: smps2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
+ };
+
+ vreg_s3b_0p776: smps3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1040000>;
+ };
+
+ vreg_s4b_1p824: smps4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2024000>;
+ };
+
+ vreg_s7b_0p936: smps7 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1040000>;
+ };
+
+ vreg_s8b_0p824: smps8 {
+ regulator-min-microvolt = <304000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ vreg_l1b_1p2: ldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo2 {
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo3 {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_0p88: ldo4 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_1p8: ldo5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo7 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo8 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo9 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_3p08: ldo10 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3088000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo11 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo12 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo13 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo14 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo15 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo16 {
+ regulator-min-microvolt = <1776000>;
+ regulator-max-microvolt = <1776000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo17 {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo19 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo20 {
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ ldo21 {
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
};
&blsp1_uart3 {
- status = "ok";
+ status = "okay";
+};
+
+&ipa {
+ qcom,gsi-loader = "skip";
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ /* ico and efs2 partitions are secured */
+ secure-regions = /bits/ 64 <0x500000 0x500000
+ 0xa00000 0xb00000>;
+ };
+};
+
+&remoteproc_mpss {
+ memory-region = <&mpss_adsp_mem>;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_hsphy {
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+ vdda33-supply = <&vreg_l10b_3p08>;
+ vdda18-supply = <&vreg_l5b_1p8>;
+ status = "okay";
+};
+
+&usb_qmpphy {
+ vdda-phy-supply = <&vreg_l4b_0p88>;
+ vdda-pll-supply = <&vreg_l1b_1p2>;
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 796641d30e06..525dd8a1f664 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -9,7 +9,9 @@
#include <dt-bindings/clock/qcom,gcc-sdx65.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/interconnect/qcom,sdx65.h>
/ {
#address-cells = <1>;
@@ -36,6 +38,12 @@
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
+
+ nand_clk_dummy: nand-clk-dummy {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
};
cpus {
@@ -47,6 +55,47 @@
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
+ clocks = <&apcs>;
+ power-domains = <&rpmhpd SDX65_CX_AO>;
+ power-domain-names = "rpmhpd";
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-sdx65", "qcom,scm";
+ };
+ };
+
+ mc_virt: interconnect-mc-virt {
+ compatible = "qcom,sdx65-mc-virt";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-345600000 {
+ opp-hz = /bits/ 64 <345600000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ required-opps = <&rpmhpd_opp_turbo>;
};
};
@@ -60,11 +109,89 @@
#size-cells = <1>;
ranges;
+ tz_heap_mem: memory@8fcad000 {
+ no-map;
+ reg = <0x8fcad000 0x40000>;
+ };
+
+ secdata_mem: memory@8fcfd000 {
+ no-map;
+ reg = <0x8fcfd000 0x1000>;
+ };
+
+ hyp_mem: memory@8fd00000 {
+ no-map;
+ reg = <0x8fd00000 0x80000>;
+ };
+
+ access_control_mem: memory@8fd80000 {
+ no-map;
+ reg = <0x8fd80000 0x80000>;
+ };
+
+ aop_mem: memory@8fe00000 {
+ no-map;
+ reg = <0x8fe00000 0x20000>;
+ };
+
+ smem_mem: memory@8fe20000 {
+ compatible = "qcom,smem";
+ reg = <0x8fe20000 0xc0000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
cmd_db: reserved-memory@8fee0000 {
compatible = "qcom,cmd-db";
reg = <0x8fee0000 0x20000>;
no-map;
};
+
+ tz_mem: memory@8ff00000 {
+ no-map;
+ reg = <0x8ff00000 0x100000>;
+ };
+
+ tz_apps_mem: memory@90000000 {
+ no-map;
+ reg = <0x90000000 0x500000>;
+ };
+
+ llcc_tcm_mem: memory@15800000 {
+ no-map;
+ reg = <0x15800000 0x800000>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
soc: soc {
@@ -78,6 +205,7 @@
reg = <0x00100000 0x001f7400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ #power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -91,6 +219,249 @@
status = "disabled";
};
+ usb_hsphy: phy@ff4000 {
+ compatible = "qcom,sdx65-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0xff4000 0x120>;
+ #phy-cells = <0>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_BCR>;
+ status = "disabled";
+ };
+
+ usb_qmpphy: phy@ff6000 {
+ compatible = "qcom,sdx65-qmp-usb3-uni-phy";
+ reg = <0x00ff6000 0x1c8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_EN>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB3PHY_PHY_BCR>,
+ <&gcc GCC_USB3_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ status = "disabled";
+
+ usb_ssphy: phy@ff6200 {
+ reg = <0x00ff6e00 0x160>,
+ <0x00ff7000 0x1ec>,
+ <0x00ff6200 0x1e00>;
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ };
+ };
+
+ system_noc: interconnect@1620000 {
+ compatible = "qcom,sdx65-system-noc";
+ reg = <0x01620000 0x31200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ qpic_bam: dma-controller@1b04000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x01b04000 0x1c000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rpmhcc RPMH_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ status = "disabled";
+ };
+
+ qpic_nand: nand-controller@1b30000 {
+ compatible = "qcom,sdx55-nand";
+ reg = <0x01b30000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&rpmhcc RPMH_QPIC_CLK>,
+ <&nand_clk_dummy>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01f40000 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ ipa: ipa@3f40000 {
+ compatible = "qcom,sdx65-ipa";
+
+ reg = <0x03f40000 0x10000>,
+ <0x03f50000 0x5000>,
+ <0x03e04000 0xfc000>;
+ reg-names = "ipa-reg",
+ "ipa-shared",
+ "gsi";
+
+ interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ipa",
+ "gsi",
+ "ipa-clock-query",
+ "ipa-setup-ready";
+
+ iommus = <&apps_smmu 0x5e0 0x0>,
+ <&apps_smmu 0x5e2 0x0>;
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ clock-names = "core";
+
+ interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
+ <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
+ interconnect-names = "memory",
+ "config";
+
+ qcom,smem-states = <&ipa_smp2p_out 0>,
+ <&ipa_smp2p_out 1>;
+ qcom,smem-state-names = "ipa-clock-enabled-valid",
+ "ipa-clock-enabled";
+
+ status = "disabled";
+ };
+
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sdx55-mpss-pas";
+ reg = <0x04080000 0x4040>;
+
+ interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SDX65_CX>,
+ <&rpmhpd SDX65_MSS>;
+ power-domain-names = "cx", "mss";
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
+ label = "mpss";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs 15>;
+ };
+ };
+
+ sdhc_1: mmc@8804000 {
+ compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x08804000 0x1000>;
+ reg-names = "hc";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ mem_noc: interconnect@9680000 {
+ compatible = "qcom,sdx65-mem-noc";
+ reg = <0x09680000 0x27200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ usb: usb@a6f8800 {
+ compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
+ reg = <0x0a6f8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_USB30_MSTR_AXI_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ "sleep";
+
+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 18 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
+
+ power-domains = <&gcc USB30_GDSC>;
+
+ resets = <&gcc GCC_USB30_BCR>;
+
+ status = "disabled";
+
+ usb_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a600000 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x1a0 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_hsphy>, <&usb_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
+ restart@c264000 {
+ compatible = "qcom,pshold";
+ reg = <0x0c264000 0x1000>;
+ };
+
+ spmi_bus: qcom,spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xc440000 0xd00>,
+ <0xc600000 0x2000000>,
+ <0xe600000 0x100000>,
+ <0xe700000 0xa0000>,
+ <0xc40a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ qcom,channel = <0>;
+ qcom,ee = <0>;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sdx65-tlmm";
reg = <0xf100000 0x300000>;
@@ -112,6 +483,59 @@
interrupt-controller;
};
+ sram@1468f000 {
+ compatible = "qcom,sdx65-imem", "syscon", "simple-mfd";
+ reg = <0x1468f000 0x1000>;
+ ranges = <0x0 0x1468f000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x15000000 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17800000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@@ -121,6 +545,29 @@
<0x17802000 0x1000>;
};
+ a7pll: clock@17808000 {
+ compatible = "qcom,sdx55-a7pll";
+ reg = <0x17808000 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <0>;
+ };
+
+ apcs: mailbox@17810000 {
+ compatible = "qcom,sdx55-apcs-gcc", "syscon";
+ reg = <0x17810000 0x2000>;
+ #mbox-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
+ clock-names = "ref", "pll", "aux";
+ #clock-cells = <0>;
+ };
+
+ watchdog@17817000 {
+ compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
+ reg = <0x17817000 0x1000>;
+ clocks = <&sleep_clk>;
+ };
+
timer@17820000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -202,12 +649,67 @@
<WAKE_TCS 2>,
<CONTROL_TCS 1>;
- rpmhcc: clock-controller@1 {
+ rpmhcc: clock-controller {
compatible = "qcom,sdx65-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sdx65-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
};
};
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index 9c0d9686fe01..69a5a44b8a2f 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -71,10 +71,10 @@
leds {
compatible = "gpio-leds";
- red {
+ led-red {
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
};
- green {
+ led-green {
gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 0af63ddc4473..fa09295052c6 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -196,6 +196,19 @@
&i2c0 {
status = "okay";
+
+ wm8978: codec@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8978";
+ reg = <0x1a>;
+ };
+
+ eeprom@50 {
+ compatible = "st,24c01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
touchscreen@55 {
compatible = "sitronix,st1232";
reg = <0x55>;
@@ -205,12 +218,6 @@
pinctrl-names = "default";
gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
};
-
- wm8978: codec@1a {
- #sound-dai-cells = <0>;
- compatible = "wlf,wm8978";
- reg = <0x1a>;
- };
};
&i2c2 {
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
index 4e58c54cde17..33ac4bd1e63b 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -7,6 +7,9 @@
*/
/dts-v1/;
+
+#include <dt-bindings/media/video-interfaces.h>
+
#include "r8a7742-iwg21d-q7.dts"
/ {
@@ -242,7 +245,7 @@
vin0ep: endpoint {
remote-endpoint = <&cam0ep>;
bus-width = <8>;
- bus-type = <6>;
+ bus-type = <MEDIA_BUS_TYPE_BT656>;
};
};
};
@@ -273,7 +276,7 @@
vin1ep: endpoint {
remote-endpoint = <&cam1ep>;
bus-width = <8>;
- bus-type = <6>;
+ bus-type = <MEDIA_BUS_TYPE_BT656>;
};
};
};
@@ -305,7 +308,7 @@
remote-endpoint = <&cam2ep>;
bus-width = <8>;
data-shift = <8>;
- bus-type = <6>;
+ bus-type = <MEDIA_BUS_TYPE_BT656>;
};
};
};
@@ -335,7 +338,7 @@
vin3ep: endpoint {
remote-endpoint = <&cam3ep>;
bus-width = <8>;
- bus-type = <6>;
+ bus-type = <MEDIA_BUS_TYPE_BT656>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi
index 40cef0b1d1e6..c73160df619d 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi
@@ -7,6 +7,8 @@
* Copyright (C) 2020 Renesas Electronics Corp.
*/
+#include <dt-bindings/media/video-interfaces.h>
+
#define CAM_ENABLED 1
&CAM_PARENT_I2C {
@@ -26,7 +28,7 @@
CAM_EP: endpoint {
bus-width = <8>;
data-shift = <2>;
- bus-type = <6>;
+ bus-type = <MEDIA_BUS_TYPE_BT656>;
pclk-sample = <1>;
remote-endpoint = <&VIN_EP>;
};
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi
index f5e77f024251..a7f5cfec64b8 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi
@@ -7,6 +7,8 @@
* Copyright (C) 2020 Renesas Electronics Corp.
*/
+#include <dt-bindings/media/video-interfaces.h>
+
#define CAM_ENABLED 1
&CAM_PARENT_I2C {
@@ -21,7 +23,7 @@
port {
CAM_EP: endpoint {
bus-width = <8>;
- bus-type = <6>;
+ bus-type = <MEDIA_BUS_TYPE_BT656>;
remote-endpoint = <&VIN_EP>;
};
};
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 420e0b3259d4..16d146db824a 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -633,7 +633,7 @@
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
+ usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7742",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -645,11 +645,11 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- usb2: usb-channel@2 {
+ usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@@ -1155,7 +1155,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1298,7 +1298,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 3502b5dcc04f..2245d19a23bb 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -140,6 +140,7 @@
compatible = "renesas,r8a7743-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -583,7 +584,7 @@
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
+ usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7743",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -595,11 +596,11 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- usb2: usb-channel@2 {
+ usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@@ -1189,7 +1190,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index f5d4b8b85b6d..aa13841f9781 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -140,6 +140,7 @@
compatible = "renesas,r8a7744-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -583,7 +584,7 @@
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
+ usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7744",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -595,11 +596,11 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- usb2: usb-channel@2 {
+ usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@@ -1189,7 +1190,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index f877c51f769c..44688b8431c3 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -270,6 +270,7 @@
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7745-wdt",
"renesas,rcar-gen2-wdt";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
@@ -524,7 +525,7 @@
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
+ usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7745",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -536,11 +537,11 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- usb2: usb-channel@2 {
+ usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@@ -1119,7 +1120,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 13ef1e9bf4d5..a5cf663a0118 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -91,6 +91,7 @@
compatible = "renesas,r8a77470-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -356,7 +357,7 @@
status = "disabled";
};
- usbphy0: usb-phy@e6590100 {
+ usbphy0: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a77470",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -368,7 +369,7 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
@@ -392,7 +393,7 @@
status = "disabled";
};
- usbphy1: usb-phy@e6598100 {
+ usbphy1: usb-phy-controller@e6598100 {
compatible = "renesas,usb-phy-r8a77470",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6598100 0 0x100>;
@@ -404,7 +405,7 @@
resets = <&cpg 706>;
status = "disabled";
- usb1: usb-channel@0 {
+ usb1: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 95efbafb0b70..8d4530ed2fc6 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -241,7 +241,7 @@
rcar_sound: sound@ffd90000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 5f05f2b44a48..fd40890bd77b 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -9,6 +9,7 @@
/dts-v1/;
#include "r8a7779.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@@ -66,6 +67,51 @@
vdd33a-supply = <&fixedregulator3v3>;
};
+ keyboard-irq {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keyboard_irq_pins>;
+ pinctrl-names = "default";
+
+ interrupt-parent = <&gpio0>;
+
+ key-1 {
+ interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_1>;
+ label = "SW1-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_2>;
+ label = "SW1-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
+ keyboard-gpio {
+ compatible = "gpio-keys-polled";
+ poll-interval = <50>;
+
+ pinctrl-0 = <&keyboard_gpio_pins>;
+ pinctrl-names = "default";
+
+ key-3 {
+ gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW1-3";
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW1-4";
+ debounce-interval = <20>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
led2 {
@@ -161,6 +207,20 @@
};
};
+&gpio0 {
+ keyboard-irq-hog {
+ gpio-hog;
+ gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ clock-frequency = <100000>;
+};
+
&irqpin0 {
status = "okay";
};
@@ -223,6 +283,15 @@
groups = "hspi0";
function = "hspi0";
};
+
+ keyboard_irq_pins: keyboard-irq {
+ pins = "GP_0_17", "GP_0_18";
+ bias-pull-up;
+ };
+ keyboard_gpio_pins: keyboard-gpio {
+ pins = "GP_0_19", "GP_0_20";
+ bias-pull-up;
+ };
};
&sata {
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 39fc58f32df6..97b767d81d92 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -324,6 +324,69 @@
status = "disabled";
};
+ pwm0: pwm@ffe50000 {
+ compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
+ reg = <0xffe50000 0x8>;
+ clocks = <&mstp0_clks R8A7779_CLK_PWM>;
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@ffe51000 {
+ compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
+ reg = <0xffe51000 0x8>;
+ clocks = <&mstp0_clks R8A7779_CLK_PWM>;
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@ffe52000 {
+ compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
+ reg = <0xffe52000 0x8>;
+ clocks = <&mstp0_clks R8A7779_CLK_PWM>;
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@ffe53000 {
+ compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
+ reg = <0xffe53000 0x8>;
+ clocks = <&mstp0_clks R8A7779_CLK_PWM>;
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@ffe54000 {
+ compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
+ reg = <0xffe54000 0x8>;
+ clocks = <&mstp0_clks R8A7779_CLK_PWM>;
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@ffe55000 {
+ compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
+ reg = <0xffe55000 0x8>;
+ clocks = <&mstp0_clks R8A7779_CLK_PWM>;
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@ffe56000 {
+ compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
+ reg = <0xffe56000 0x8>;
+ clocks = <&mstp0_clks R8A7779_CLK_PWM>;
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
pfc: pinctrl@fffc0000 {
compatible = "renesas,pfc-r8a7779";
reg = <0xfffc0000 0x23c>;
@@ -554,7 +617,8 @@
compatible = "renesas,r8a7779-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xffc80030 4>;
- clocks = <&cpg_clocks R8A7779_CLK_S>,
+ clocks = <&cpg_clocks R8A7779_CLK_P>,
+ <&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
@@ -572,20 +636,21 @@
<&cpg_clocks R8A7779_CLK_P>;
#clock-cells = <1>;
clock-indices = <
- R8A7779_CLK_HSPI R8A7779_CLK_TMU2
- R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
- R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
- R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
- R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
- R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
- R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
- R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
+ R8A7779_CLK_PWM R8A7779_CLK_HSPI
+ R8A7779_CLK_TMU2 R8A7779_CLK_TMU1
+ R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1
+ R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5
+ R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3
+ R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
+ R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3
+ R8A7779_CLK_I2C2 R8A7779_CLK_I2C1
+ R8A7779_CLK_I2C0
>;
clock-output-names =
- "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
- "hscif0", "scif5", "scif4", "scif3", "scif2",
- "scif1", "scif0", "i2c3", "i2c2", "i2c1",
- "i2c0";
+ "pwm", "hspi", "tmu2", "tmu1", "tmu0",
+ "hscif1", "hscif0", "scif5", "scif4", "scif3",
+ "scif2", "scif1", "scif0", "i2c3", "i2c2",
+ "i2c1", "i2c0";
};
mstp1_clks: clocks@ffc80034 {
compatible = "renesas,r8a7779-mstp-clocks",
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 57cd2fa72249..5ad5349a50dc 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -442,7 +442,7 @@
compatible = "dlg,da9063-rtc";
};
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
index c802f9f13c18..fe14727eefe1 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -341,7 +341,7 @@
compatible = "dlg,da9063-rtc";
};
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index ed6dd4fcc503..46fb81f5062f 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -274,6 +274,7 @@
compatible = "renesas,r8a7790-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -375,6 +376,17 @@
reg = <0 0xe6060000 0 0x250>;
};
+ tpu: pwm@e60f0000 {
+ compatible = "renesas,tpu-r8a7790", "renesas,tpu";
+ reg = <0 0xe60f0000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7790-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -653,7 +665,7 @@
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
+ usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7790",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -665,11 +677,11 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- usb2: usb-channel@2 {
+ usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@@ -1036,6 +1048,76 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
can0: can@e6e80000 {
compatible = "renesas,can-r8a7790",
"renesas,rcar-gen2-can";
@@ -1108,7 +1190,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1251,7 +1333,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 6e691b6cac05..26a40782cc89 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -805,7 +805,7 @@
compatible = "dlg,da9063-rtc";
};
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index 38e2ab928707..ec0a20d5130d 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -390,7 +390,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 0ccc162d3c2c..b9d34147628e 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -161,6 +161,7 @@
compatible = "renesas,r8a7791-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -607,7 +608,7 @@
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
+ usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7791",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -619,11 +620,11 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- usb2: usb-channel@2 {
+ usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@@ -1222,7 +1223,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1364,7 +1365,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index 62aa9f61321b..c66de9dd12df 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -335,7 +335,7 @@
compatible = "dlg,da9063-rtc";
};
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 9cdb73894ac2..a6d9367f8fa0 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -111,6 +111,7 @@
compatible = "renesas,r8a7792-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 402>;
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index c8978f4f62e9..79b537b24642 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -740,7 +740,7 @@
compatible = "dlg,da9063-rtc";
};
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index dea4b1e108af..f51bf687f4bd 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -146,6 +146,7 @@
compatible = "renesas,r8a7793-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -987,7 +988,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
@@ -1110,7 +1111,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 99d554fe3329..4d93319674c6 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -463,7 +463,7 @@
compatible = "dlg,da9063-rtc";
};
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 92a76164432a..b7af1befa126 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -433,7 +433,7 @@
compatible = "dlg,da9063-rtc";
};
- wdt {
+ watchdog {
compatible = "dlg,da9063-watchdog";
};
};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index eac9ed8df0be..371dd4715dde 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -128,6 +128,7 @@
compatible = "renesas,r8a7794-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -505,7 +506,7 @@
status = "disabled";
};
- usbphy: usb-phy@e6590100 {
+ usbphy: usb-phy-controller@e6590100 {
compatible = "renesas,usb-phy-r8a7794",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
@@ -517,11 +518,11 @@
resets = <&cpg 704>;
status = "disabled";
- usb0: usb-channel@0 {
+ usb0: usb-phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- usb2: usb-channel@2 {
+ usb2: usb-phy@2 {
reg = <2>;
#phy-cells = <1>;
};
@@ -954,7 +955,7 @@
rcar_sound: sound@ec500000 {
/*
- * #sound-dai-cells is required
+ * #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi
deleted file mode 100644
index 79fce67ebb1c..000000000000
--- a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Common file for the AA104XD12 panel connected to Renesas R-Car boards
- *
- * Copyright (C) 2014 Renesas Electronics Corp.
- */
-
-/ {
- panel {
- compatible = "mitsubishi,aa104xd12", "panel-lvds";
-
- width-mm = <210>;
- height-mm = <158>;
- data-mapping = "jeida-18";
-
- panel-timing {
- /* 1024x768 @65Hz */
- clock-frequency = <65000000>;
- hactive = <1024>;
- vactive = <768>;
- hsync-len = <136>;
- hfront-porch = <20>;
- hback-porch = <160>;
- vfront-porch = <3>;
- vback-porch = <29>;
- vsync-len = <6>;
- };
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lvds_connector>;
- };
- };
- };
-};
-
-&lvds_connector {
- remote-endpoint = <&panel_in>;
-};
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
index 3f8f3ce87e12..c18bbd7141c4 100644
--- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -8,6 +8,9 @@
/dts-v1/;
+#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
+#include <dt-bindings/net/pcs-rzn1-miic.h>
+
#include "r9a06g032.dtsi"
/ {
@@ -23,6 +26,150 @@
};
};
+&can0 {
+ pinctrl-0 = <&pins_can0>;
+ pinctrl-names = "default";
+
+ /* Assuming CN10/CN11 are wired for CAN1 */
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-0 = <&pins_can1>;
+ pinctrl-names = "default";
+
+ /* Please only enable can0 or can1, depending on CN10/CN11 */
+ /* status = "okay"; */
+};
+
+&eth_miic {
+ status = "okay";
+ renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "gmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&mii_conv4 {
+ renesas,miic-input = <MIIC_SWITCH_PORTB>;
+ status = "okay";
+};
+
+&mii_conv5 {
+ renesas,miic-input = <MIIC_SWITCH_PORTA>;
+ status = "okay";
+};
+
+&pinctrl{
+ pins_can0: pins_can0 {
+ pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */
+ <RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */
+ drive-strength = <6>;
+ };
+
+ pins_can1: pins_can1 {
+ pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>, /* CAN1_TXD */
+ <RZN1_PINMUX(110, RZN1_FUNC_CAN)>; /* CAN1_RXD */
+ drive-strength = <6>;
+ };
+
+ pins_eth3: pins_eth3 {
+ pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ pins_eth4: pins_eth4 {
+ pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ pins_mdio1: pins_mdio1 {
+ pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
+ <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
+ };
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;
+
+ dsa,member = <0 0>;
+
+ mdio {
+ clock-frequency = <2500000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy4: ethernet-phy@4 {
+ reg = <4>;
+ micrel,led-mode = <1>;
+ };
+
+ switch0phy5: ethernet-phy@5 {
+ reg = <5>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
+&switch_port0 {
+ label = "lan0";
+ phy-mode = "mii";
+ phy-handle = <&switch0phy5>;
+ status = "okay";
+};
+
+&switch_port1 {
+ label = "lan1";
+ phy-mode = "mii";
+ phy-handle = <&switch0phy4>;
+ status = "okay";
+};
+
+&switch_port4 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 636a6ab31c58..0fa565a1c3ad 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -66,6 +66,19 @@
interrupt-parent = <&gic>;
ranges;
+ rtc0: rtc@40006000 {
+ compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
+ reg = <0x40006000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "alarm", "timer", "pps";
+ clocks = <&sysctrl R9A06G032_HCLK_RTC>;
+ clock-names = "hclk";
+ power-domains = <&sysctrl>;
+ status = "disabled";
+ };
+
wdt0: watchdog@40008000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40008000 0x1000>;
@@ -87,10 +100,74 @@
reg = <0x4000c000 0x1000>;
status = "okay";
#clock-cells = <1>;
+ #power-domain-cells = <0>;
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dmamux: dma-router@a0 {
+ compatible = "renesas,rzn1-dmamux";
+ reg = <0xa0 4>;
+ #dma-cells = <6>;
+ dma-requests = <32>;
+ dma-masters = <&dma0 &dma1>;
+ };
+ };
+
+ udc: usb@4001e000 {
+ compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf";
+ reg = <0x4001e000 0x2000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl R9A06G032_HCLK_USBF>,
+ <&sysctrl R9A06G032_HCLK_USBPM>;
+ clock-names = "hclkf", "hclkpm";
+ power-domains = <&sysctrl>;
+ status = "disabled";
+ };
+
+ pci_usb: pci@40030000 {
+ compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
+ device_type = "pci";
+ clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+ <&sysctrl R9A06G032_HCLK_USBPM>,
+ <&sysctrl R9A06G032_CLK_PCI_USB>;
+ clock-names = "hclkh", "hclkpm", "pciclk";
+ power-domains = <&sysctrl>;
+ reg = <0x40030000 0xc00>,
+ <0x40020000 0x1100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
+ /* Should map all possible DDR as inbound ranges, but
+ * the IP only supports a 256MB, 512MB, or 1GB window.
+ * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
+ */
+ dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usbphy>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usbphy>;
+ phy-names = "usb";
+ };
};
uart0: serial@40060000 {
@@ -134,6 +211,8 @@
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -145,6 +224,8 @@
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -156,6 +237,8 @@
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -167,6 +250,8 @@
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -178,6 +263,8 @@
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -195,9 +282,146 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
clock-names = "hclk", "eclk";
+ power-domains = <&sysctrl>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dma0: dma-controller@40104000 {
+ compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
+ reg = <0x40104000 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "hclk";
+ clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
+ dma-channels = <8>;
+ dma-requests = <16>;
+ dma-masters = <1>;
+ #dma-cells = <3>;
+ block_size = <0xfff>;
+ data-width = <8>;
+ };
+
+ dma1: dma-controller@40105000 {
+ compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
+ reg = <0x40105000 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "hclk";
+ clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
+ dma-channels = <8>;
+ dma-requests = <16>;
+ dma-masters = <1>;
+ #dma-cells = <3>;
+ block_size = <0xfff>;
+ data-width = <8>;
+ };
+
+ gmac2: ethernet@44002000 {
+ compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
+ reg = <0x44002000 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
+ clock-names = "stmmaceth";
+ power-domains = <&sysctrl>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <2048>;
+ rx-fifo-depth = <4096>;
+ status = "disabled";
+ };
+
+ eth_miic: eth-miic@44030000 {
+ compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
#address-cells = <1>;
#size-cells = <0>;
+ reg = <0x44030000 0x10000>;
+ clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
+ <&sysctrl R9A06G032_CLK_RGMII_REF>,
+ <&sysctrl R9A06G032_CLK_RMII_REF>,
+ <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
+ clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
+ power-domains = <&sysctrl>;
status = "disabled";
+
+ mii_conv1: mii-conv@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ mii_conv2: mii-conv@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ mii_conv3: mii-conv@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ mii_conv4: mii-conv@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+
+ mii_conv5: mii-conv@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ switch: switch@44050000 {
+ compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
+ reg = <0x44050000 0x10000>;
+ clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
+ <&sysctrl R9A06G032_CLK_SWITCH>;
+ clock-names = "hclk", "clk";
+ power-domains = <&sysctrl>;
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch_port0: port@0 {
+ reg = <0>;
+ pcs-handle = <&mii_conv5>;
+ status = "disabled";
+ };
+
+ switch_port1: port@1 {
+ reg = <1>;
+ pcs-handle = <&mii_conv4>;
+ status = "disabled";
+ };
+
+ switch_port2: port@2 {
+ reg = <2>;
+ pcs-handle = <&mii_conv3>;
+ status = "disabled";
+ };
+
+ switch_port3: port@3 {
+ reg = <3>;
+ pcs-handle = <&mii_conv2>;
+ status = "disabled";
+ };
+
+ switch_port4: port@4 {
+ reg = <4>;
+ ethernet = <&gmac2>;
+ label = "cpu";
+ phy-mode = "internal";
+ status = "disabled";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
};
gic: interrupt-controller@44101000 {
@@ -211,11 +435,30 @@
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ can0: can@52104000 {
+ compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
+ reg = <0x52104000 0x800>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
+ power-domains = <&sysctrl>;
+ status = "disabled";
+ };
+
+ can1: can@52105000 {
+ compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
+ reg = <0x52105000 0x800>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
+ power-domains = <&sysctrl>;
+ status = "disabled";
+ };
};
timer {
- compatible = "arm,cortex-a7-timer",
- "arm,armv7-timer";
+ compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
arm,cpu-registers-not-fw-configured;
always-on;
@@ -225,4 +468,10 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
+
+ usbphy: usb-phy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
index 2a7e6624efb9..becdc0b664bf 100644
--- a/arch/arm/boot/dts/rk3036-evb.dts
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -15,27 +15,30 @@
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
- phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
-
+ phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
status = "okay";
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
&i2c1 {
status = "okay";
- hym8563: hym8563@51 {
+ hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index e817eba8c622..67e1e04139e7 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -80,16 +80,20 @@
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
phy = <&phy0>;
- phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
phy-reset-duration = <10>; /* millisecond */
-
+ phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
status = "okay";
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index ba2b8891bbb7..78686fc72ce6 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -225,11 +225,9 @@
};
emac: ethernet@10200000 {
- compatible = "rockchip,rk3036-emac", "snps,arc-emac";
+ compatible = "rockchip,rk3036-emac";
reg = <0x10200000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
rockchip,grf = <&grf>;
clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
clock-names = "hclk", "macref", "macclk";
@@ -330,6 +328,8 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3036-cru";
reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -556,7 +556,7 @@
status = "disabled";
};
- pdma: pdma@20078000 {
+ pdma: dma-controller@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -614,7 +614,7 @@
#interrupt-cells = <2>;
};
- pcfg_pull_default: pcfg_pull_default {
+ pcfg_pull_default: pcfg-pull-default {
bias-pull-pin-default;
};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 390aa33cd55a..962b4d1291db 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -48,7 +48,7 @@
compatible = "gpio-keys";
autorepeat;
- power {
+ key-power {
gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
@@ -56,7 +56,7 @@
wakeup-source;
debounce-interval = <100>;
};
- volume-down {
+ key-volume-down {
gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
linux,code = <KEY_VOLUMEDOWN>;
label = "GPIO Key Vol-";
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index a66d915aa0f6..8beecd628282 100644
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -150,18 +150,21 @@
#include "tps65910.dtsi"
&emac {
- status = "okay";
-
phy = <&phy0>;
phy-supply = <&vcc_rmii>;
-
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
- phy0: ethernet-phy@0 {
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ };
};
};
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index 667d57a4ff45..06790f05b395 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -32,7 +32,7 @@
keyup-threshold-microvolt = <2500000>;
poll-interval = <100>;
- recovery {
+ button-recovery {
label = "recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <0>;
@@ -157,7 +157,32 @@
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
pinctrl-names = "default";
vmmc-supply = <&vcc_wifi>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
+&nfc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ label = "rk-nand";
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <40>;
+ nand-is-boot-medium;
+ rockchip,boot-blks = <8>;
+ rockchip,boot-ecc-strength = <24>;
+ };
};
&pinctrl {
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 12b2e59aebc4..3eee42137b6d 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -32,7 +32,7 @@
keys: gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
wakeup-source;
gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
@@ -142,15 +142,20 @@
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
phy = <&phy0>;
phy-supply = <&vcc_rmii>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
status = "okay";
- phy0: ethernet-phy@0 {
- reg = <0>;
- reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+ };
};
};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index c25b9695db4b..de9915d946f7 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -202,8 +202,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3066a-cru";
reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
-
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
diff --git a/arch/arm/boot/dts/rk3128-evb.dts b/arch/arm/boot/dts/rk3128-evb.dts
new file mode 100644
index 000000000000..c38f42497cbd
--- /dev/null
+++ b/arch/arm/boot/dts/rk3128-evb.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+
+#include "rk3128.dtsi"
+
+/ {
+ model = "Rockchip RK3128 Evaluation board";
+ compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ i2c1 = &i2c1;
+ mmc0 = &emmc;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&usb2phy {
+ status = "okay";
+};
+
+&usb2phy_host {
+ status = "okay";
+};
+
+&usb2phy_otg {
+ status = "okay";
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci {
+ status = "okay";
+};
+
+&usb_otg {
+ vbus-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb-host {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-otg {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rk3128.dtsi b/arch/arm/boot/dts/rk3128.dtsi
new file mode 100644
index 000000000000..b63bd4ad3143
--- /dev/null
+++ b/arch/arm/boot/dts/rk3128.dtsi
@@ -0,0 +1,916 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#include <dt-bindings/clock/rk3128-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+ compatible = "rockchip,rk3128";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ operating-points = <
+ /* KHz uV */
+ 816000 1000000
+ >;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ cpu1: cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ };
+
+ cpu2: cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ };
+
+ cpu3: cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ arm,cpu-registers-not-fw-configured;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ pmu: syscon@100a0000 {
+ compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
+ reg = <0x100a0000 0x1000>;
+ };
+
+ gic: interrupt-controller@10139000 {
+ compatible = "arm,cortex-a7-gic";
+ reg = <0x10139000 0x1000>,
+ <0x1013a000 0x1000>,
+ <0x1013c000 0x2000>,
+ <0x1013e000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ usb_otg: usb@10180000 {
+ compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
+ reg = <0x10180000 0x40000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ phys = <&usb2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@101c0000 {
+ compatible = "generic-ehci";
+ reg = <0x101c0000 0x20000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@101e0000 {
+ compatible = "generic-ohci";
+ reg = <0x101e0000 0x20000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ sdmmc: mmc@10214000 {
+ compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x10214000 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ dmas = <&pdma 10>;
+ dma-names = "rx-tx";
+ fifo-depth = <256>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdio: mmc@10218000 {
+ compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x10218000 0x4000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ dmas = <&pdma 11>;
+ dma-names = "rx-tx";
+ fifo-depth = <256>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ emmc: mmc@1021c000 {
+ compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x1021c000 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ dmas = <&pdma 12>;
+ dma-names = "rx-tx";
+ fifo-depth = <256>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ nfc: nand-controller@10500000 {
+ compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
+ reg = <0x10500000 0x4000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
+ &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
+ status = "disabled";
+ };
+
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3128-cru";
+ reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>;
+ assigned-clock-rates = <594000000>;
+ };
+
+ grf: syscon@20008000 {
+ compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
+ reg = <0x20008000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ usb2phy: usb2phy@17c {
+ compatible = "rockchip,rk3128-usb2phy";
+ reg = <0x017c 0x0c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ usb2phy_host: host-port {
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb2phy_otg: otg-port {
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer0: timer@20044000 {
+ compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
+ reg = <0x20044000 0x20>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
+ };
+
+ timer1: timer@20044020 {
+ compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
+ reg = <0x20044020 0x20>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
+ };
+
+ timer2: timer@20044040 {
+ compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
+ reg = <0x20044040 0x20>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
+ };
+
+ timer3: timer@20044060 {
+ compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
+ reg = <0x20044060 0x20>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
+ };
+
+ timer4: timer@20044080 {
+ compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
+ reg = <0x20044080 0x20>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
+ };
+
+ timer5: timer@200440a0 {
+ compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
+ reg = <0x200440a0 0x20>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
+ };
+
+ watchdog: watchdog@2004c000 {
+ compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
+ reg = <0x2004c000 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_WDT>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@20050000 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050000 0x10>;
+ clocks = <&cru PCLK_PWM>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@20050010 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050010 0x10>;
+ clocks = <&cru PCLK_PWM>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@20050020 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050020 0x10>;
+ clocks = <&cru PCLK_PWM>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@20050030 {
+ compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20050030 0x10>;
+ clocks = <&cru PCLK_PWM>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@20056000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x20056000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2005a000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x2005a000 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2005e000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <0x2005e000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@20060000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20060000 0x100>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 2>, <&pdma 3>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@20064000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20064000 0x100>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 4>, <&pdma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@20068000 {
+ compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
+ reg = <0x20068000 0x100>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 6>, <&pdma 7>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ saradc: saradc@2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@20072000 {
+ compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
+ reg = <20072000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@20074000 {
+ compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
+ reg = <0x20074000 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&pdma 8>, <&pdma 9>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pdma: dma-controller@20078000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x20078000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-broken-no-flushp;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3128-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio@2007c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2007c000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@20080000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@20084000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20084000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@20088000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20088000 0x100>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_default: pcfg-pull-default {
+ bias-pull-pin-default;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
+ };
+
+ emmc_cmd1: emmc-cmd1 {
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
+ };
+
+ emmc_pwr: emmc-pwr {
+ rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
+ };
+
+ emmc_bus1: emmc-bus1 {
+ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
+ };
+
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
+ <1 RK_PD1 2 &pcfg_pull_default>,
+ <1 RK_PD2 2 &pcfg_pull_default>,
+ <1 RK_PD3 2 &pcfg_pull_default>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
+ <1 RK_PD1 2 &pcfg_pull_default>,
+ <1 RK_PD2 2 &pcfg_pull_default>,
+ <1 RK_PD3 2 &pcfg_pull_default>,
+ <1 RK_PD4 2 &pcfg_pull_default>,
+ <1 RK_PD5 2 &pcfg_pull_default>,
+ <1 RK_PD6 2 &pcfg_pull_default>,
+ <1 RK_PD7 2 &pcfg_pull_default>;
+ };
+ };
+
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
+ <2 RK_PB1 3 &pcfg_pull_default>,
+ <2 RK_PB3 3 &pcfg_pull_default>,
+ <2 RK_PB4 3 &pcfg_pull_default>,
+ <2 RK_PB5 3 &pcfg_pull_default>,
+ <2 RK_PB6 3 &pcfg_pull_default>,
+ <2 RK_PC0 3 &pcfg_pull_default>,
+ <2 RK_PC1 3 &pcfg_pull_default>,
+ <2 RK_PC2 3 &pcfg_pull_default>,
+ <2 RK_PC3 3 &pcfg_pull_default>,
+ <2 RK_PD1 3 &pcfg_pull_default>,
+ <2 RK_PC4 4 &pcfg_pull_default>,
+ <2 RK_PC5 4 &pcfg_pull_default>,
+ <2 RK_PC6 4 &pcfg_pull_default>,
+ <2 RK_PC7 4 &pcfg_pull_default>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
+ <2 RK_PB4 3 &pcfg_pull_default>,
+ <2 RK_PB5 3 &pcfg_pull_default>,
+ <2 RK_PB6 3 &pcfg_pull_default>,
+ <2 RK_PB7 3 &pcfg_pull_default>,
+ <2 RK_PC0 3 &pcfg_pull_default>,
+ <2 RK_PC1 3 &pcfg_pull_default>,
+ <2 RK_PC2 3 &pcfg_pull_default>,
+ <2 RK_PC3 3 &pcfg_pull_default>,
+ <2 RK_PD1 3 &pcfg_pull_default>;
+ };
+ };
+
+ hdmi {
+ hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
+ <0 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ hdmi_hpd: hdmi-hpd {
+ rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ hdmi_cec: hdmi-cec {
+ rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
+ <2 RK_PC5 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
+ <0 RK_PA7 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s {
+ i2s_bus: i2s-bus {
+ rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
+ <0 RK_PB1 1 &pcfg_pull_none>,
+ <0 RK_PB3 1 &pcfg_pull_none>,
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ <0 RK_PB5 1 &pcfg_pull_none>,
+ <0 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ i2s1_bus: i2s1-bus {
+ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
+ <1 RK_PA1 1 &pcfg_pull_none>,
+ <1 RK_PA2 1 &pcfg_pull_none>,
+ <1 RK_PA3 1 &pcfg_pull_none>,
+ <1 RK_PA4 1 &pcfg_pull_none>,
+ <1 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ lcdc {
+ lcdc_dclk: lcdc-dclk {
+ rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ lcdc_den: lcdc-den {
+ rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ lcdc_hsync: lcdc-hsync {
+ rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ lcdc_vsync: lcdc-vsync {
+ rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ lcdc_rgb24: lcdc-rgb24 {
+ rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
+ <2 RK_PB5 1 &pcfg_pull_none>,
+ <2 RK_PB6 1 &pcfg_pull_none>,
+ <2 RK_PB7 1 &pcfg_pull_none>,
+ <2 RK_PC0 1 &pcfg_pull_none>,
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ <2 RK_PC2 1 &pcfg_pull_none>,
+ <2 RK_PC3 1 &pcfg_pull_none>,
+ <2 RK_PC4 1 &pcfg_pull_none>,
+ <2 RK_PC5 1 &pcfg_pull_none>,
+ <2 RK_PC6 1 &pcfg_pull_none>,
+ <2 RK_PC7 1 &pcfg_pull_none>,
+ <2 RK_PD0 1 &pcfg_pull_none>,
+ <2 RK_PD1 1 &pcfg_pull_none>;
+ };
+ };
+
+ nfc {
+ flash_ale: flash-ale {
+ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ flash_cle: flash-cle {
+ rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ flash_wrn: flash-wrn {
+ rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ flash_rdn: flash-rdn {
+ rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ flash_rdy: flash-rdy {
+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ flash_cs0: flash-cs0 {
+ rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
+ };
+
+ flash_dqs: flash-dqs {
+ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ flash_bus8: flash-bus8 {
+ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ <1 RK_PD2 1 &pcfg_pull_none>,
+ <1 RK_PD3 1 &pcfg_pull_none>,
+ <1 RK_PD4 1 &pcfg_pull_none>,
+ <1 RK_PD5 1 &pcfg_pull_none>,
+ <1 RK_PD6 1 &pcfg_pull_none>,
+ <1 RK_PD7 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdio {
+ sdio_clk: sdio-clk {
+ rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
+ };
+
+ sdio_pwren: sdio-pwren {
+ rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
+ <1 RK_PA2 2 &pcfg_pull_default>,
+ <1 RK_PA4 2 &pcfg_pull_default>,
+ <1 RK_PA5 2 &pcfg_pull_default>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
+ };
+
+ sdmmc_wp: sdmmc-wp {
+ rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
+ };
+
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
+ <1 RK_PC3 1 &pcfg_pull_default>,
+ <1 RK_PC4 1 &pcfg_pull_default>,
+ <1 RK_PC5 1 &pcfg_pull_default>;
+ };
+ };
+
+ spdif {
+ spdif_tx: spdif-tx {
+ rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ spi0_clk: spi0-clk {
+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
+ };
+
+ spi0_cs0: spi0-cs0 {
+ rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
+ };
+
+ spi0_tx: spi0-tx {
+ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
+ };
+
+ spi0_rx: spi0-rx {
+ rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
+ };
+
+ spi0_cs1: spi0-cs1 {
+ rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
+ };
+
+ spi1_clk: spi1-clk {
+ rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
+ };
+
+ spi1_cs0: spi1-cs0 {
+ rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
+ };
+
+ spi1_tx: spi1-tx {
+ rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
+ };
+
+ spi1_rx: spi1-rx {
+ rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
+ };
+
+ spi1_cs1: spi1-cs1 {
+ rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
+ };
+
+ spi2_clk: spi2-clk {
+ rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
+ };
+
+ spi2_cs0: spi2-cs0 {
+ rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
+ };
+
+ spi2_tx: spi2-tx {
+ rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
+ };
+
+ spi2_rx: spi2-rx {
+ rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
+ <2 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
+ <1 RK_PB2 2 &pcfg_pull_default>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
+ <1 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ uart2_cts: uart2-cts {
+ rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ uart2_rts: uart2-rts {
+ rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
index 85d3fce0142f..9312be362a7a 100644
--- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts
+++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "rk3188.dtsi"
/ {
@@ -36,7 +37,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwr_key &usb_int>;
- power {
+ key-power {
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
@@ -45,7 +46,7 @@
wakeup-source;
};
- wake_on_usb: wake-on-usb {
+ wake_on_usb: key-wake-on-usb {
label = "Wake-on-USB";
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -485,7 +486,7 @@
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio3>;
- interrupts = <RK_PD2 GPIO_ACTIVE_HIGH>;
+ interrupts = <RK_PD2 IRQ_TYPE_NONE>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index fc478ac4e781..0a1ae689b162 100644
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -29,7 +29,7 @@
compatible = "gpio-keys";
autorepeat;
- power {
+ key-power {
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 36c0945f43b2..118deacd38c4 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -24,7 +24,7 @@
compatible = "gpio-keys";
autorepeat;
- power {
+ key-power {
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
@@ -71,7 +71,7 @@
#sound-dai-cells = <0>;
};
- ir_recv: gpio-ir-receiver {
+ ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -126,18 +126,21 @@
};
&emac {
- status = "okay";
-
+ phy = <&phy0>;
+ phy-supply = <&vcc_rmii>;
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+ status = "okay";
- phy = <&phy0>;
- phy-supply = <&vcc_rmii>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
- phy0: ethernet-phy@0 {
- reg = <0>;
- interrupt-parent = <&gpio3>;
- interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ };
};
};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index a94321e90014..44b54af0bbf9 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -195,8 +195,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
-
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -378,7 +379,7 @@
rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
};
- lcdc1_rgb24: ldcd1-rgb24 {
+ lcdc1_rgb24: lcdc1-rgb24 {
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
<2 RK_PA1 1 &pcfg_pull_none>,
<2 RK_PA2 1 &pcfg_pull_none>,
@@ -606,7 +607,6 @@
&global_timer {
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
- status = "disabled";
};
&local_timer {
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index 797476e8bef1..5c3d08e3eea3 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -107,7 +107,7 @@
regulator-boot-on;
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 5868eb512f69..ffc16d6b97e1 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -484,6 +484,8 @@
cru: clock-controller@110e0000 {
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -501,7 +503,7 @@
<75000000>;
};
- pdma: pdma@110f0000 {
+ pdma: dma-controller@110f0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x110f0000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index be695b8c1f67..8a635c243127 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -54,7 +54,7 @@
vin-supply = <&vcc_sys>;
};
- hym8563@51 {
+ rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index c4ca73b40d4a..382d2839cf47 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -28,19 +28,19 @@
press-threshold-microvolt = <300000>;
};
- menu {
+ button-menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <640000>;
};
- esc {
+ button-esc {
label = "Esc";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <1000000>;
};
- home {
+ button-home {
label = "Home";
linux,code = <KEY_HOME>;
press-threshold-microvolt = <1300000>;
@@ -118,7 +118,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
- power {
+ key-power {
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
index 9a4a9749c405..a5a0826341e6 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
@@ -27,7 +27,7 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
wakeup-source;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 7fb582302b32..3836c61cfb76 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -49,7 +49,7 @@
keys: gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
wakeup-source;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
@@ -233,11 +233,10 @@
vin-supply = <&vcc_sys>;
};
- hym8563: hym8563@51 {
+ hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio7>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 713f55e143c6..db1eb648e0e1 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -162,11 +162,10 @@
vin-supply = <&vcc_sys>;
};
- hym8563: hym8563@51 {
+ hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
};
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index 1e33859de484..1a5156951492 100644
--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -20,14 +20,14 @@
pinctrl-names = "default";
pinctrl-0 = <&user_button_pins>;
- button@0 {
+ button-0 {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
- button@1 {
+ button-1 {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 8c7376d64bc4..fd90f3b8fc32 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -30,7 +30,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
- power {
+ key-power {
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index 55467bc30fa6..633e5a032463 100644
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -31,7 +31,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
- power {
+ key-power {
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index c4d1d142d8c6..13cfdaa95cc7 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -28,7 +28,7 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
@@ -165,11 +165,10 @@
};
&i2c0 {
- hym8563: hym8563@51 {
+ hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
index 9c1e38c54eae..09618bb7d872 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -26,14 +26,12 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
- button@0 {
+ button {
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
index a10d25ac8f7b..f9dde0eef527 100644
--- a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
@@ -13,10 +13,10 @@
<&bt_dev_wake>;
compatible = "brcm,bcm43540-bt";
- host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- max-speed = <3000000>;
- brcm,bt-pcm-int-params = [01 02 00 01 01];
+ host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index 05112c25176d..700bb548d6b2 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -32,7 +32,7 @@
pinctrl-names = "default";
pinctrl-0 = <&ap_lid_int_l>;
- lid {
+ switch-lid {
label = "Lid";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
wakeup-source;
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index 82fc6fba9999..dcdcc55c4098 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -21,14 +21,14 @@
pinctrl-names = "default";
pinctrl-0 = <&volum_down_l &volum_up_l>;
- volum_down {
+ key-volum-down {
label = "Volum_down";
gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <100>;
};
- volum_up {
+ key-volum-up {
label = "Volum_up";
gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index 4e9fdb0f722d..e2a4e6232eb5 100644
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -45,7 +45,7 @@
&lid_switch {
pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
- power {
+ key-power {
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
index 27fb06ce907e..8b58773e592e 100644
--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
@@ -5,6 +5,12 @@
* Copyright 2015 Google, Inc
*/
+/ {
+ aliases {
+ mmc1 = &sdmmc;
+ };
+};
+
&io_domains {
sdcard-supply = <&vccio_sd>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 54a6838d73f5..d838bf0d5d9a 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -10,6 +10,10 @@
#include "rk3288.dtsi"
/ {
+ aliases {
+ mmc0 = &emmc;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
@@ -29,7 +33,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pwr_key_l>;
- power {
+ key-power {
label = "Power";
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
index 0ae2bd150e37..793951655b73 100644
--- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
@@ -241,7 +241,6 @@
interrupt-parent = <&gpio5>;
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 26b9bbe310af..cb9cdaddffd4 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -862,6 +862,8 @@
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3288-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -940,7 +942,7 @@
status = "disabled";
};
- spdif: sound@ff88b0000 {
+ spdif: sound@ff8b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
@@ -1112,7 +1114,7 @@
status = "disabled";
};
- mipi_dsi: mipi@ff960000 {
+ mipi_dsi: dsi@ff960000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -1123,18 +1125,28 @@
status = "disabled";
ports {
- mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
};
+
mipi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+ mipi_out: port@1 {
+ reg = <1>;
+ };
};
};
@@ -1155,7 +1167,6 @@
lvds_in: port@0 {
reg = <0>;
-
#address-cells = <1>;
#size-cells = <0>;
@@ -1163,11 +1174,16 @@
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
+
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
+
+ lvds_out: port@1 {
+ reg = <1>;
+ };
};
};
@@ -1179,6 +1195,7 @@
clock-names = "dp", "pclk";
phys = <&edp_phy>;
phy-names = "dp";
+ power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_EDP>;
reset-names = "dp";
rockchip,grf = <&grf>;
@@ -1187,19 +1204,26 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
+
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
+
+ edp_out: port@1 {
+ reg = <1>;
+ };
};
};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 616a828e0c6e..cb4e42ede56a 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -76,6 +76,13 @@
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cru CORE_PERI>;
+ status = "disabled";
+ /* The clock source and the sched_clock provided by the arm_global_timer
+ * on Rockchip rk3066a/rk3188 are quite unstable because their rates
+ * depend on the CPU frequency.
+ * Keep the arm_global_timer disabled in order to have the
+ * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
+ */
};
local_timer: local-timer@1013c600 {
@@ -186,8 +193,6 @@
compatible = "snps,arc-emac";
reg = <0x10204000 0x3c>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
rockchip,grf = <&grf>;
diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts
index 0c99a5934ebf..2d9994379eb2 100644
--- a/arch/arm/boot/dts/rv1108-elgin-r1.dts
+++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts
@@ -83,7 +83,7 @@
regulators {
vdd_core: DCDC_REG1 {
- regulator-name= "vdd_core";
+ regulator-name = "vdd_core";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
@@ -95,7 +95,7 @@
};
vdd_buck2: DCDC_REG2 {
- regulator-name= "vdd_buck2";
+ regulator-name = "vdd_buck2";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
regulator-always-on;
@@ -106,7 +106,7 @@
};
vcc_ddr: DCDC_REG3 {
- regulator-name= "vcc_ddr";
+ regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
@@ -115,7 +115,7 @@
};
vcc_io: DCDC_REG4 {
- regulator-name= "vcc_io";
+ regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
@@ -127,7 +127,7 @@
};
vdd_10: LDO_REG1 {
- regulator-name= "vdd_10";
+ regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -138,7 +138,7 @@
};
vcc_18: LDO_REG2 {
- regulator-name= "vcc_18";
+ regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -149,7 +149,7 @@
};
vdd10_pmu: LDO_REG3 {
- regulator-name= "vdd10_pmu";
+ regulator-name = "vdd10_pmu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 46cad7cb94bf..ef150f4ee99d 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -96,7 +96,7 @@
regulators {
vdd_core: DCDC_REG1 {
- regulator-name= "vdd_core";
+ regulator-name = "vdd_core";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
@@ -108,7 +108,7 @@
};
vdd_cam: DCDC_REG2 {
- regulator-name= "vdd_cam";
+ regulator-name = "vdd_cam";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <2000000>;
regulator-state-mem {
@@ -117,7 +117,7 @@
};
vcc_ddr: DCDC_REG3 {
- regulator-name= "vcc_ddr";
+ regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
@@ -126,7 +126,7 @@
};
vcc_io: DCDC_REG4 {
- regulator-name= "vcc_io";
+ regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
@@ -138,7 +138,7 @@
};
vdd_10: LDO_REG1 {
- regulator-name= "vdd_10";
+ regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -149,7 +149,7 @@
};
vcc_18: LDO_REG2 {
- regulator-name= "vcc_18";
+ regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -160,7 +160,7 @@
};
vdd10_pmu: LDO_REG3 {
- regulator-name= "vdd10_pmu";
+ regulator-name = "vdd10_pmu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 448254906452..abf3006f0a84 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -85,24 +85,6 @@
#clock-cells = <0>;
};
- amba: bus {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@102a0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x102a0000 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- arm,pl330-broken-no-flushp;
- arm,pl330-periph-burst;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- };
- };
-
bus_intmem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
@@ -259,6 +241,17 @@
status = "disabled";
};
+ pdma: dma-controller@102a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x102a0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+
grf: syscon@10300000 {
compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
reg = <0x10300000 0x1000>;
@@ -456,6 +449,8 @@
cru: clock-controller@20200000 {
compatible = "rockchip,rv1108-cru";
reg = <0x20200000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -753,7 +748,7 @@
gmac {
rmii_pins: rmii-pins {
- rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
+ rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
<1 RK_PC3 2 &pcfg_pull_none>,
<1 RK_PC4 2 &pcfg_pull_none>,
<1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
new file mode 100644
index 000000000000..3340fc3f0739
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-edgeble-neu2.dtsi"
+
+/ {
+ model = "Edgeble Neu2 IO Board";
+ compatible = "edgeble,neural-compute-module-2-io",
+ "edgeble,neural-compute-module-2", "rockchip,rv1126";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&gmac {
+ assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
+ <&cru CLK_GMAC_ETHERNET_OUT>;
+ assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
+ assigned-clock-rates = <125000000>, <0>, <25000000>;
+ clock_in_out = "input";
+ phy-handle = <&phy>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
+ tx_delay = <0x2a>;
+ rx_delay = <0x1a>;
+ status = "okay";
+};
+
+&mdio {
+ phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth_phy_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ eth_phy_rst: eth-phy-rst {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
new file mode 100644
index 000000000000..cc64ba4be344
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
+
+ aliases {
+ mmc0 = &emmc;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccio_flash: vccio-flash-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_vol_sel>;
+ regulator-name = "vccio_flash";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ sdio_pwrseq: pwrseq-sdio {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ rockchip,default-sample-phase = <90>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_flash>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc_buck5>;
+ vcc6-supply = <&vcc_buck5>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_npu_vepu: DCDC_REG1 {
+ regulator-name = "vdd_npu_vepu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_buck5: DCDC_REG5 {
+ regulator-name = "vcc_buck5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2200000>;
+ };
+ };
+
+ vcc_0v8: LDO_REG1 {
+ regulator-name = "vcc_0v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG2 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd0v8_pmu: LDO_REG3 {
+ regulator-name = "vcc0v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <800000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_dovdd: LDO_REG5 {
+ regulator-name = "vcc_dovdd";
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_dvdd: LDO_REG6 {
+ regulator-name = "vcc_dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_avdd: LDO_REG7 {
+ regulator-name = "vcc_avdd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG8 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: LDO_REG9 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_5v0: SWITCH_REG1 {
+ regulator-name = "vcc_5v0";
+ };
+
+ vcc_3v3: SWITCH_REG2 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable: bt-enable {
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ flash {
+ flash_vol_sel: flash-vol-sel {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio0-supply = <&vcc1v8_pmu>;
+ pmuio1-supply = <&vcc3v3_sys>;
+ vccio1-supply = <&vccio_flash>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_1v8>;
+ vccio4-supply = <&vcc_dovdd>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_dovdd>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,qca9377-bt";
+ clocks = <&rk809 1>;
+ enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
+ max-speed = <2000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable>;
+ vddxo-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
new file mode 100644
index 000000000000..b77021772781
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <arm64/rockchip/rockchip-pinconf.dtsi>
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ clk_out_ethernet {
+ /omit-if-no-ref/
+ clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
+ rockchip,pins =
+ /* clk_out_ethernet_m1 */
+ <2 RK_PC5 2 &pcfg_pull_none>;
+ };
+ };
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clko */
+ <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c0_sda */
+ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ rgmii {
+ /omit-if-no-ref/
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* rgmii_mdc_m1 */
+ <2 RK_PC2 2 &pcfg_pull_none>,
+ /* rgmii_mdio_m1 */
+ <2 RK_PC1 2 &pcfg_pull_none>,
+ /* rgmii_rxclk_m1 */
+ <2 RK_PD3 2 &pcfg_pull_none>,
+ /* rgmii_rxd0_m1 */
+ <2 RK_PB5 2 &pcfg_pull_none>,
+ /* rgmii_rxd1_m1 */
+ <2 RK_PB6 2 &pcfg_pull_none>,
+ /* rgmii_rxd2_m1 */
+ <2 RK_PC7 2 &pcfg_pull_none>,
+ /* rgmii_rxd3_m1 */
+ <2 RK_PD0 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_m1 */
+ <2 RK_PB4 2 &pcfg_pull_none>,
+ /* rgmii_txclk_m1 */
+ <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
+ /* rgmii_txd0_m1 */
+ <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
+ /* rgmii_txd1_m1 */
+ <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
+ /* rgmii_txd2_m1 */
+ <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
+ /* rgmii_txd3_m1 */
+ <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>,
+ /* rgmii_txen_m1 */
+ <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_pwr: sdmmc0-pwr {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_pwr: sdmmc1-pwr {
+ rockchip,pins =
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <1 RK_PC2 1 &pcfg_pull_up>,
+ /* uart0_tx */
+ <1 RK_PC3 1 &pcfg_pull_up>;
+ };
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn_gpio: uart0-rts-pin {
+ rockchip,pins =
+ <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ };
+ uart2 {
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA3 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA2 1 &pcfg_pull_up>;
+ };
+ };
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <3 RK_PC7 4 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <3 RK_PC6 4 &pcfg_pull_up>;
+ };
+ };
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PA5 4 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
new file mode 100644
index 000000000000..1f07d0a4fa73
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rv1126-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rockchip,rv1126-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1126";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ i2c0 = &i2c0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1: cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu2: cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu3: cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ grf: syscon@fe000000 {
+ compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
+ reg = <0xfe000000 0x20000>;
+ };
+
+ pmugrf: syscon@fe020000 {
+ compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
+ reg = <0xfe020000 0x1000>;
+
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rv1126-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+ };
+
+ qos_emmc: qos@fe860000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860000 0x20>;
+ };
+
+ qos_nandc: qos@fe860080 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860080 0x20>;
+ };
+
+ qos_sfc: qos@fe860200 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860200 0x20>;
+ };
+
+ qos_sdio: qos@fe86c000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe86c000 0x20>;
+ };
+
+ gic: interrupt-controller@feff0000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0xfeff1000 0x1000>,
+ <0xfeff2000 0x2000>,
+ <0xfeff4000 0x2000>,
+ <0xfeff6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pmu: power-management@ff3e0000 {
+ compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
+ reg = <0xff3e0000 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rv1126-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RV1126_PD_NVM {
+ reg = <RV1126_PD_NVM>;
+ clocks = <&cru HCLK_EMMC>,
+ <&cru CLK_EMMC>,
+ <&cru HCLK_NANDC>,
+ <&cru CLK_NANDC>,
+ <&cru HCLK_SFC>,
+ <&cru HCLK_SFCXIP>,
+ <&cru SCLK_SFC>;
+ pm_qos = <&qos_emmc>,
+ <&qos_nandc>,
+ <&qos_sfc>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RV1126_PD_SDIO {
+ reg = <RV1126_PD_SDIO>;
+ clocks = <&cru HCLK_SDIO>,
+ <&cru CLK_SDIO>;
+ pm_qos = <&qos_sdio>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ i2c0: i2c@ff3f0000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff3f0000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,grf = <&pmugrf>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff410000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff410000 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 7>, <&dmac 6>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ dmac: dma-controller@ff4e0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xff4e0000 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+
+ uart0: serial@ff560000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff560000 0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 5>, <&dmac 4>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff570000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff570000 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 9>, <&dmac 8>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ff580000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff580000 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 11>, <&dmac 10>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@ff590000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff590000 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 13>, <&dmac 12>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@ff5a0000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff5a0000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 15>, <&dmac 14>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ saradc: adc@ff5e0000 {
+ compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
+ reg = <0xff5e0000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC_P>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ timer0: timer@ff660000 {
+ compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
+ reg = <0xff660000 0x20>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
+ gmac: ethernet@ffc40000 {
+ compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
+ reg = <0xffc40000 0x4000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&grf>;
+ clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
+ <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
+ <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "aclk_mac", "pclk_mac",
+ "clk_mac_speed", "ptp_ref";
+ resets = <&cru SRST_GMAC_A>;
+ reset-names = "stmmaceth";
+
+ snps,mixed-burst;
+ snps,tso;
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ emmc: mmc@ffc50000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc50000 0x4000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_NVM>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc60000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc60000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdio: mmc@ffc70000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc70000 0x4000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_SDIO>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1126-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio@ff460000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff460000 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff620000 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff630000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ff640000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff640000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ff650000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff650000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rv1126-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
deleted file mode 100644
index 20a7d72827c2..000000000000
--- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
+++ /dev/null
@@ -1,172 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung S3C2416 pinctrl settings
- *
- * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
- */
-
-#include <dt-bindings/pinctrl/samsung.h>
-
-&pinctrl_0 {
- /*
- * Pin banks
- */
-
- gpa: gpa-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpb: gpb-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpc: gpc-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpd: gpd-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpe: gpe-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpf: gpf-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpg: gpg-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gph: gph-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpj: gpj-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpk: gpk-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpl: gpl-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpm: gpm-gpio-bank {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- /*
- * Pin groups
- */
-
- uart0_data: uart0-data-pins {
- samsung,pins = "gph-0", "gph-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- uart0_fctl: uart0-fctl-pins {
- samsung,pins = "gph-8", "gph-9";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- uart1_data: uart1-data-pins {
- samsung,pins = "gph-2", "gph-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- uart1_fctl: uart1-fctl-pins {
- samsung,pins = "gph-10", "gph-11";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- uart2_data: uart2-data-pins {
- samsung,pins = "gph-4", "gph-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- uart2_fctl: uart2-fctl-pins {
- samsung,pins = "gph-6", "gph-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- uart3_data: uart3-data-pins {
- samsung,pins = "gph-6", "gph-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- extuart_clk: extuart-clk-pins {
- samsung,pins = "gph-12";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- i2c0_bus: i2c0-bus-pins {
- samsung,pins = "gpe-14", "gpe-15";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- spi0_bus: spi0-bus-pins {
- samsung,pins = "gpe-11", "gpe-12", "gpe-13";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd0_clk: sd0-clk-pins {
- samsung,pins = "gpe-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd0_cmd: sd0-cmd-pins {
- samsung,pins = "gpe-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd0_bus1: sd0-bus1-pins {
- samsung,pins = "gpe-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd0_bus4: sd0-bus4-pins {
- samsung,pins = "gpe-8", "gpe-9", "gpe-10";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd1_cmd: sd1-cmd-pins {
- samsung,pins = "gpl-8";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd1_clk: sd1-clk-pins {
- samsung,pins = "gpl-9";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd1_bus1: sd1-bus1-pins {
- samsung,pins = "gpl-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-
- sd1_bus4: sd1-bus4-pins {
- samsung,pins = "gpl-1", "gpl-2", "gpl-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- };
-};
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
deleted file mode 100644
index e7c379a9842e..000000000000
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung SMDK2416 board device tree source
- *
- * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
- */
-
-/dts-v1/;
-#include "s3c2416.dtsi"
-
-/ {
- model = "SMDK2416";
- compatible = "samsung,smdk2416", "samsung,s3c2416";
-
- memory@30000000 {
- device_type = "memory";
- reg = <0x30000000 0x4000000>;
- };
-
- xti: clock-0 {
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- clock-output-names = "xti";
- #clock-cells = <0>;
- };
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdhci_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&sd1_clk>, <&sd1_cmd>,
- <&sd1_bus1>, <&sd1_bus4>;
- bus-width = <4>;
- broken-cd;
- status = "okay";
-};
-
-&sdhci_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk>, <&sd0_cmd>,
- <&sd0_bus1>, <&sd0_bus4>;
- bus-width = <4>;
- cd-gpios = <&gpf 1 0>;
- cd-inverted;
- status = "okay";
-};
-
-&uart_0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
-};
-
-&uart_1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
-};
-
-&uart_2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_data>;
-};
-
-&uart_3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_data>;
-};
-
-&watchdog {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
deleted file mode 100644
index 4f084f4fe44f..000000000000
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ /dev/null
@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung's S3C2416 SoC device tree source
- *
- * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
- */
-
-#include <dt-bindings/clock/s3c2443.h>
-#include "s3c24xx.dtsi"
-#include "s3c2416-pinctrl.dtsi"
-
-/ {
- model = "Samsung S3C2416 SoC";
- compatible = "samsung,s3c2416";
-
- aliases {
- serial3 = &uart_3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,arm926ej-s";
- reg = <0x0>;
- };
- };
-
- clocks: clock-controller@4c000000 {
- compatible = "samsung,s3c2416-clock";
- reg = <0x4c000000 0x40>;
- #clock-cells = <1>;
- };
-
- uart_3: serial@5000c000 {
- compatible = "samsung,s3c2440-uart";
- reg = <0x5000C000 0x4000>;
- interrupts = <1 18 24 4>, <1 18 25 4>;
- clock-names = "uart", "clk_uart_baud2",
- "clk_uart_baud3";
- clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
- <&clocks SCLK_UART>;
- status = "disabled";
- };
-
- sdhci_1: sdhci@4ac00000 {
- compatible = "samsung,s3c6410-sdhci";
- reg = <0x4AC00000 0x100>;
- interrupts = <0 0 21 3>;
- clock-names = "hsmmc", "mmc_busclk.0",
- "mmc_busclk.2";
- clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
- <&clocks MUX_HSMMC0>;
- status = "disabled";
- };
-
- sdhci_0: sdhci@4a800000 {
- compatible = "samsung,s3c6410-sdhci";
- reg = <0x4A800000 0x100>;
- interrupts = <0 0 20 3>;
- clock-names = "hsmmc", "mmc_busclk.0",
- "mmc_busclk.2";
- clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
- <&clocks MUX_HSMMC1>;
- status = "disabled";
- };
-};
-
-&i2c {
- compatible = "samsung,s3c2440-i2c";
- clocks = <&clocks PCLK_I2C0>;
- clock-names = "i2c";
-};
-
-&intc {
- compatible = "samsung,s3c2416-irq";
-};
-
-&pinctrl_0 {
- compatible = "samsung,s3c2416-pinctrl";
-};
-
-&rtc {
- compatible = "samsung,s3c2416-rtc";
- clocks = <&clocks PCLK_RTC>;
- clock-names = "rtc";
-};
-
-&timer {
- clocks = <&clocks PCLK_PWM>;
- clock-names = "timers";
-};
-
-&uart_0 {
- compatible = "samsung,s3c2440-uart";
- clock-names = "uart", "clk_uart_baud2",
- "clk_uart_baud3";
- clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
- <&clocks SCLK_UART>;
-};
-
-&uart_1 {
- compatible = "samsung,s3c2440-uart";
- clock-names = "uart", "clk_uart_baud2",
- "clk_uart_baud3";
- clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
- <&clocks SCLK_UART>;
-};
-
-&uart_2 {
- compatible = "samsung,s3c2440-uart";
- clock-names = "uart", "clk_uart_baud2",
- "clk_uart_baud3";
- clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
- <&clocks SCLK_UART>;
-};
-
-&watchdog {
- interrupts = <1 9 27 3>;
- clocks = <&clocks PCLK_WDT>;
- clock-names = "watchdog";
-};
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
deleted file mode 100644
index 06f82c7e458e..000000000000
--- a/arch/arm/boot/dts/s3c24xx.dtsi
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung's S3C24XX family device tree source
- *
- * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
- */
-
-/ {
- compatible = "samsung,s3c24xx";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- pinctrl0 = &pinctrl_0;
- serial0 = &uart_0;
- serial1 = &uart_1;
- serial2 = &uart_2;
- };
-
- intc: interrupt-controller@4a000000 {
- compatible = "samsung,s3c2410-irq";
- reg = <0x4a000000 0x100>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
-
- pinctrl_0: pinctrl@56000000 {
- reg = <0x56000000 0x1000>;
-
- wakeup-interrupt-controller {
- compatible = "samsung,s3c2410-wakeup-eint";
- interrupts = <0 0 0 3>,
- <0 0 1 3>,
- <0 0 2 3>,
- <0 0 3 3>,
- <0 0 4 4>,
- <0 0 5 4>;
- };
- };
-
- timer: pwm@51000000 {
- compatible = "samsung,s3c2410-pwm";
- reg = <0x51000000 0x1000>;
- interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
- #pwm-cells = <3>;
- };
-
- uart_0: serial@50000000 {
- compatible = "samsung,s3c2410-uart";
- reg = <0x50000000 0x4000>;
- interrupts = <1 28 0 4>, <1 28 1 4>;
- status = "disabled";
- };
-
- uart_1: serial@50004000 {
- compatible = "samsung,s3c2410-uart";
- reg = <0x50004000 0x4000>;
- interrupts = <1 23 3 4>, <1 23 4 4>;
- status = "disabled";
- };
-
- uart_2: serial@50008000 {
- compatible = "samsung,s3c2410-uart";
- reg = <0x50008000 0x4000>;
- interrupts = <1 15 6 4>, <1 15 7 4>;
- status = "disabled";
- };
-
- watchdog: watchdog@53000000 {
- compatible = "samsung,s3c2410-wdt";
- reg = <0x53000000 0x100>;
- interrupts = <0 0 9 3>;
- status = "disabled";
- };
-
- rtc: rtc@57000000 {
- compatible = "samsung,s3c2410-rtc";
- reg = <0x57000000 0x100>;
- interrupts = <0 0 30 3>, <0 0 8 3>;
- status = "disabled";
- };
-
- i2c: i2c@54000000 {
- compatible = "samsung,s3c2410-i2c";
- reg = <0x54000000 0x100>;
- interrupts = <0 0 27 3>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
index 0a3186d57cb5..f53959b7d031 100644
--- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
@@ -9,7 +9,7 @@
* listed as device tree nodes in this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "s3c64xx-pinctrl.h"
&pinctrl0 {
/*
@@ -133,219 +133,219 @@
uart0_data: uart0-data-pins {
samsung,pins = "gpa-0", "gpa-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
uart0_fctl: uart0-fctl-pins {
samsung,pins = "gpa-2", "gpa-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
uart1_data: uart1-data-pins {
samsung,pins = "gpa-4", "gpa-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
uart1_fctl: uart1-fctl-pins {
samsung,pins = "gpa-6", "gpa-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
uart2_data: uart2-data-pins {
samsung,pins = "gpb-0", "gpb-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
uart3_data: uart3-data-pins {
samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
ext_dma_0: ext-dma-0-pins {
samsung,pins = "gpb-0", "gpb-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
ext_dma_1: ext-dma-1-pins {
samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
irda_data_0: irda-data-0-pins {
samsung,pins = "gpb-0", "gpb-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
irda_data_1: irda-data-1-pins {
samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
irda_sdbw: irda-sdbw-pins {
samsung,pins = "gpb-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
i2c0_bus: i2c0-bus-pins {
samsung,pins = "gpb-5", "gpb-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
};
i2c1_bus: i2c1-bus-pins {
/* S3C6410-only */
samsung,pins = "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_6>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_6>;
samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
};
spi0_bus: spi0-bus-pins {
samsung,pins = "gpc-0", "gpc-1", "gpc-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
};
spi0_cs: spi0-cs-pins {
samsung,pins = "gpc-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
spi1_bus: spi1-bus-pins {
samsung,pins = "gpc-4", "gpc-5", "gpc-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
};
spi1_cs: spi1-cs-pins {
samsung,pins = "gpc-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd0_cmd: sd0-cmd-pins {
samsung,pins = "gpg-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd0_clk: sd0-clk-pins {
samsung,pins = "gpg-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd0_bus1: sd0-bus1-pins {
samsung,pins = "gpg-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd0_bus4: sd0-bus4-pins {
samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd0_cd: sd0-cd-pins {
samsung,pins = "gpg-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
};
sd1_cmd: sd1-cmd-pins {
samsung,pins = "gph-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd1_clk: sd1-clk-pins {
samsung,pins = "gph-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd1_bus1: sd1-bus1-pins {
samsung,pins = "gph-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd1_bus4: sd1-bus4-pins {
samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd1_bus8: sd1-bus8-pins {
samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5",
"gph-6", "gph-7", "gph-8", "gph-9";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd1_cd: sd1-cd-pins {
samsung,pins = "gpg-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
};
sd2_cmd: sd2-cmd-pins {
samsung,pins = "gpc-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd2_clk: sd2-clk-pins {
samsung,pins = "gpc-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd2_bus1: sd2-bus1-pins {
samsung,pins = "gph-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
sd2_bus4: sd2-bus4-pins {
samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
i2s0_bus: i2s0-bus-pins {
samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
i2s0_cdclk: i2s0-cdclk-pins {
samsung,pins = "gpd-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
i2s1_bus: i2s1-bus-pins {
samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
i2s1_cdclk: i2s1-cdclk-pins {
samsung,pins = "gpe-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
@@ -353,50 +353,50 @@
/* S3C6410-only */
samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
"gph-8", "gph-9";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_5>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
i2s2_cdclk: i2s2-cdclk-pins {
/* S3C6410-only */
samsung,pins = "gph-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_5>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
pcm0_bus: pcm0-bus-pins {
samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
pcm0_extclk: pcm0-extclk-pins {
samsung,pins = "gpd-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
pcm1_bus: pcm1-bus-pins {
samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
pcm1_extclk: pcm1-extclk-pins {
samsung,pins = "gpe-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
ac97_bus_0: ac97-bus-0-pins {
samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
ac97_bus_1: ac97-bus-1-pins {
samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
@@ -404,242 +404,242 @@
samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4",
"gpf-5", "gpf-6", "gpf-7", "gpf-8",
"gpf-9", "gpf-10", "gpf-11", "gpf-12";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
cam_rst: cam-rst-pins {
samsung,pins = "gpf-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
cam_field: cam-field-pins {
/* S3C6410-only */
samsung,pins = "gpb-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
pwm_extclk: pwm-extclk-pins {
samsung,pins = "gpf-13";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
pwm0_out: pwm0-out-pins {
samsung,pins = "gpf-14";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
pwm1_out: pwm1-out-pins {
samsung,pins = "gpf-15";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
clkout0: clkout-0-pins {
samsung,pins = "gpf-14";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col0_0: keypad-col0-0-pins {
samsung,pins = "gph-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col1_0: keypad-col1-0-pins {
samsung,pins = "gph-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col2_0: keypad-col2-0-pins {
samsung,pins = "gph-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col3_0: keypad-col3-0-pins {
samsung,pins = "gph-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col4_0: keypad-col4-0-pins {
samsung,pins = "gph-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col5_0: keypad-col5-0-pins {
samsung,pins = "gph-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col6_0: keypad-col6-0-pins {
samsung,pins = "gph-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col7_0: keypad-col7-0-pins {
samsung,pins = "gph-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col0_1: keypad-col0-1-pins {
samsung,pins = "gpl-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col1_1: keypad-col1-1-pins {
samsung,pins = "gpl-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col2_1: keypad-col2-1-pins {
samsung,pins = "gpl-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col3_1: keypad-col3-1-pins {
samsung,pins = "gpl-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col4_1: keypad-col4-1-pins {
samsung,pins = "gpl-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col5_1: keypad-col5-1-pins {
samsung,pins = "gpl-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col6_1: keypad-col6-1-pins {
samsung,pins = "gpl-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_col7_1: keypad-col7-1-pins {
samsung,pins = "gpl-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row0_0: keypad-row0-0-pins {
samsung,pins = "gpk-8";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row1_0: keypad-row1-0-pins {
samsung,pins = "gpk-9";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row2_0: keypad-row2-0-pins {
samsung,pins = "gpk-10";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row3_0: keypad-row3-0-pins {
samsung,pins = "gpk-11";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row4_0: keypad-row4-0-pins {
samsung,pins = "gpk-12";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row5_0: keypad-row5-0-pins {
samsung,pins = "gpk-13";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row6_0: keypad-row6-0-pins {
samsung,pins = "gpk-14";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row7_0: keypad-row7-0-pins {
samsung,pins = "gpk-15";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row0_1: keypad-row0-1-pins {
samsung,pins = "gpn-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row1_1: keypad-row1-1-pins {
samsung,pins = "gpn-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row2_1: keypad-row2-1-pins {
samsung,pins = "gpn-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row3_1: keypad-row3-1-pins {
samsung,pins = "gpn-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row4_1: keypad-row4-1-pins {
samsung,pins = "gpn-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row5_1: keypad-row5-1-pins {
samsung,pins = "gpn-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row6_1: keypad-row6-1-pins {
samsung,pins = "gpn-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
keypad_row7_1: keypad-row7-1-pins {
samsung,pins = "gpn-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
lcd_ctrl: lcd-ctrl-pins {
samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
@@ -648,7 +648,7 @@
"gpi-7", "gpi-10", "gpi-11", "gpi-12",
"gpi-13", "gpi-14", "gpi-15", "gpj-3",
"gpj-4", "gpj-5", "gpj-6", "gpj-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
@@ -658,7 +658,7 @@
"gpi-12", "gpi-13", "gpi-14", "gpi-15",
"gpj-2", "gpj-3", "gpj-4", "gpj-5",
"gpj-6", "gpj-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
@@ -669,14 +669,14 @@
"gpi-12", "gpi-13", "gpi-14", "gpi-15",
"gpj-0", "gpj-1", "gpj-2", "gpj-3",
"gpj-4", "gpj-5", "gpj-6", "gpj-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
hsi_bus: hsi-bus-pins {
samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3",
"gpk-4", "gpk-5", "gpk-6", "gpk-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.h b/arch/arm/boot/dts/s3c64xx-pinctrl.h
new file mode 100644
index 000000000000..645c591db357
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung S3C64xx DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__
+#define __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__
+
+#define S3C64XX_PIN_PULL_NONE 0
+#define S3C64XX_PIN_PULL_DOWN 1
+#define S3C64XX_PIN_PULL_UP 2
+
+#define S3C64XX_PIN_FUNC_INPUT 0
+#define S3C64XX_PIN_FUNC_OUTPUT 1
+#define S3C64XX_PIN_FUNC_2 2
+#define S3C64XX_PIN_FUNC_3 3
+#define S3C64XX_PIN_FUNC_4 4
+#define S3C64XX_PIN_FUNC_5 5
+#define S3C64XX_PIN_FUNC_6 6
+#define S3C64XX_PIN_FUNC_EINT 7
+
+#endif /* __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
index 67a7a66e11d5..c03df6355500 100644
--- a/arch/arm/boot/dts/s3c64xx.dtsi
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -59,7 +59,7 @@
#interrupt-cells = <1>;
};
- sdhci0: sdhci@7c200000 {
+ sdhci0: mmc@7c200000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x7c200000 0x100>;
interrupt-parent = <&vic1>;
@@ -70,7 +70,7 @@
status = "disabled";
};
- sdhci1: sdhci@7c300000 {
+ sdhci1: mmc@7c300000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x7c300000 0x100>;
interrupt-parent = <&vic1>;
@@ -81,7 +81,7 @@
status = "disabled";
};
- sdhci2: sdhci@7c400000 {
+ sdhci2: mmc@7c400000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x7c400000 0x100>;
interrupt-parent = <&vic1>;
diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts
index 54de3bc77c30..0f5c6cd0f3a1 100644
--- a/arch/arm/boot/dts/s5pv210-aquila.dts
+++ b/arch/arm/boot/dts/s5pv210-aquila.dts
@@ -29,8 +29,7 @@
memory@30000000 {
device_type = "memory";
- reg = <0x30000000 0x05000000
- 0x40000000 0x18000000>;
+ reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>;
};
pmic_ap_clk: clock-0 {
@@ -393,7 +392,7 @@
&pinctrl0 {
t_flash_detect: t-flash-detect-pins {
samsung,pins = "gph3-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
};
};
diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi
index c8f1c324a6c2..f628d3660493 100644
--- a/arch/arm/boot/dts/s5pv210-aries.dtsi
+++ b/arch/arm/boot/dts/s5pv210-aries.dtsi
@@ -24,9 +24,9 @@
memory@30000000 {
device_type = "memory";
- reg = <0x30000000 0x05000000
- 0x40000000 0x10000000
- 0x50000000 0x08000000>;
+ reg = <0x30000000 0x05000000>,
+ <0x40000000 0x10000000>,
+ <0x50000000 0x08000000>;
};
reserved-memory {
@@ -135,8 +135,8 @@
0xa101 0x0100 0x8100 0x0100 0x0100
0x0100>;
- wlf,ldo1ena = <&gpf3 4 GPIO_ACTIVE_HIGH>;
- wlf,ldo2ena = <&gpf3 4 GPIO_ACTIVE_HIGH>;
+ wlf,ldo1ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>;
+ wlf,ldo2ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>;
wlf,lineout1-se;
wlf,lineout2-se;
@@ -564,7 +564,6 @@
reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>;
vdd3-supply = <&ldo7_reg>;
vci-supply = <&ldo17_reg>;
- spi-cs-high;
spi-max-frequency = <1200000>;
pinctrl-names = "default";
@@ -636,7 +635,7 @@
};
&i2s0 {
- dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>;
+ dmas = <&pdma0 10>, <&pdma0 9>, <&pdma0 11>;
status = "okay";
};
@@ -647,183 +646,183 @@
&pinctrl0 {
bt_reset: bt-reset-pins {
samsung,pins = "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
wlan_bt_en: wlan-bt-en-pins {
samsung,pins = "gpb-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
samsung,pin-val = <1>;
};
codec_ldo: codec-ldo-pins {
samsung,pins = "gpf3-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
};
prox_i2c_pins: gp2a-i2c-pins {
samsung,pins = "gpg0-2", "gpg2-2";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
wlan_gpio_rst: wlan-gpio-rst-pins {
samsung,pins = "gpg1-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
};
bt_wake: bt-wake-pins {
samsung,pins = "gpg3-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
};
gp2a_irq: gp2a-irq-pins {
samsung,pins = "gph0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
pmic_dvs_pins: pmic-dvs-pins {
samsung,pins = "gph0-3", "gph0-4", "gph0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
samsung,pin-val = <0>;
};
pmic_irq: pmic-irq-pins {
samsung,pins = "gph0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
wifi_host_wake: wifi-host-wake-pins {
samsung,pins = "gph2-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
bt_host_wake: bt-host-wake-pins {
samsung,pins = "gph2-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
musb_irq: musq-irq-pins {
samsung,pins = "gph2-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
tf_detect: tf-detect-pins {
samsung,pins = "gph3-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
wifi_wake: wifi-wake-pins {
samsung,pins = "gph3-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
};
- magnetometer_i2c_pins: yas529-i2c-pins-pins {
+ magnetometer_i2c_pins: yas529-i2c-pins {
samsung,pins = "gpj0-0", "gpj0-1";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
ts_irq: ts-irq-pins {
samsung,pins = "gpj0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
vibrator_ena: vibrator-ena-pins {
samsung,pins = "gpj1-1";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
gp2a_power: gp2a-power-pins {
samsung,pins = "gpj1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
touchkey_i2c_pins: touchkey-i2c-pins {
samsung,pins = "gpj3-0", "gpj3-1";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
touchkey_vdd_ena: touchkey-vdd-ena-pins {
samsung,pins = "gpj3-2";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
musb_i2c_pins: musb-i2c-pins {
samsung,pins = "gpj3-4", "gpj3-5";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
accel_i2c_pins: accel-i2c-pins {
samsung,pins = "gpj3-6", "gpj3-7";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
- pmic_i2c_pins: pmic-i2c-pins-pins {
+ pmic_i2c_pins: pmic-i2c-pins {
samsung,pins = "gpj4-0", "gpj4-3";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
touchkey_irq: touchkey-irq-pins {
samsung,pins = "gpj4-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
lcd_spi_pins: spi-lcd-pins {
samsung,pins = "mp01-1", "mp04-1", "mp04-3";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
fg_i2c_pins: fg-i2c-pins {
samsung,pins = "mp05-0", "mp05-1";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
sound_i2c_pins: sound-i2c-pins {
samsung,pins = "mp05-2", "mp05-3";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
panel_rst: panel-rst-pins {
samsung,pins = "mp05-5";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
};
@@ -895,7 +894,7 @@
device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gph2>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
+ interrupt-names = "host-wakeup";
};
};
diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
index dfb2ee65e4a8..eaa7c4f0e257 100644
--- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts
+++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
@@ -17,20 +17,20 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "power";
gpios = <&gph2 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- vol-down {
+ key-vol-down {
label = "volume_down";
gpios = <&gph3 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
- vol-up {
+ key-vol-up {
label = "volume_up";
gpios = <&gph3 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
@@ -128,33 +128,33 @@
headset_det: headset-det-pins {
samsung,pins = "gph0-6", "gph3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
};
fg_irq: fg-irq-pins {
samsung,pins = "gph3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
headset_micbias_ena: headset-micbias-ena-pins {
samsung,pins = "gpj2-5";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
earpath_sel: earpath-sel-pins {
samsung,pins = "gpj2-6";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
main_micbias_ena: main-micbias-ena-pins {
samsung,pins = "gpj4-2";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
/* Based on vendor kernel v2.6.35.7 */
diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts
index a78caaa1f3c5..532d3f5bceb1 100644
--- a/arch/arm/boot/dts/s5pv210-galaxys.dts
+++ b/arch/arm/boot/dts/s5pv210-galaxys.dts
@@ -24,26 +24,26 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "power";
gpios = <&gph2 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- vol-down {
+ key-vol-down {
label = "volume_down";
gpios = <&gph3 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
- vol-up {
+ key-vol-up {
label = "volume_up";
gpios = <&gph3 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
- home {
+ key-home {
label = "home";
gpios = <&gph3 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
@@ -150,49 +150,49 @@
pinctrl-names = "default";
pinctrl-0 = <&sleep_cfg>;
- fm_i2c_pins: fm-i2c-pins-pins {
+ fm_i2c_pins: fm-i2c-pins {
samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
headset_det: headset-det-pins {
samsung,pins = "gph0-6", "gph3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
};
fm_irq: fm-irq-pins {
samsung,pins = "gpj2-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
fm_rst: fm-rst-pins {
samsung,pins = "gpj2-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
earpath_sel: earpath-sel-pins {
samsung,pins = "gpj2-6";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
massmemory_en: massmemory-en-pins {
samsung,pins = "gpj2-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
micbias_reg_ena: micbias-reg-ena-pins {
samsung,pins = "gpj4-2";
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
/* Based on CyanogenMod 3.0.101 kernel */
diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts
index c6f39147cb96..d32f42dd1bf5 100644
--- a/arch/arm/boot/dts/s5pv210-goni.dts
+++ b/arch/arm/boot/dts/s5pv210-goni.dts
@@ -30,9 +30,9 @@
memory@30000000 {
device_type = "memory";
- reg = <0x30000000 0x05000000
- 0x40000000 0x10000000
- 0x50000000 0x08000000>;
+ reg = <0x30000000 0x05000000>,
+ <0x40000000 0x10000000>,
+ <0x50000000 0x08000000>;
};
pmic_ap_clk: clock-0 {
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
index ae34e7e57892..6d6daef9fb7a 100644
--- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
@@ -16,13 +16,13 @@
* nodes can be added to this file.
*/
-#include <dt-bindings/pinctrl/samsung.h>
+#include "s5pv210-pinctrl.h"
#define PIN_SLP(_pin, _mode, _pull) \
_pin { \
samsung,pins = #_pin; \
- samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
- samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \
+ samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
+ samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
}
&pinctrl0 {
@@ -280,559 +280,559 @@
uart0_data: uart0-data-pins {
samsung,pins = "gpa0-0", "gpa0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
uart0_fctl: uart0-fctl-pins {
samsung,pins = "gpa0-2", "gpa0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
uart1_data: uart1-data-pins {
samsung,pins = "gpa0-4", "gpa0-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
uart1_fctl: uart1-fctl-pins {
samsung,pins = "gpa0-6", "gpa0-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
uart2_data: uart2-data-pins {
samsung,pins = "gpa1-0", "gpa1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
uart2_fctl: uart2-fctl-pins {
samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
uart3_data: uart3-data-pins {
samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
uart_audio: uart-audio-pins {
samsung,pins = "gpa1-2", "gpa1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
spi0_bus: spi0-bus-pins {
samsung,pins = "gpb-0", "gpb-2", "gpb-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
spi1_bus: spi1-bus-pins {
samsung,pins = "gpb-4", "gpb-6", "gpb-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
i2s0_bus: i2s0-bus-pins {
samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
"gpi-4", "gpi-5", "gpi-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
i2s1_bus: i2s1-bus-pins {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
i2s2_bus: i2s2-bus-pins {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
pcm1_bus: pcm1-bus-pins {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
ac97_bus: ac97-bus-pins {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
i2s2_bus: i2s2-bus-pins {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
pcm2_bus: pcm2-bus-pins {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
spdif_bus: spdif-bus-pins {
samsung,pins = "gpc1-0", "gpc1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
spi2_bus: spi2-bus-pins {
samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_5>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
i2c0_bus: i2c0-bus-pins {
samsung,pins = "gpd1-0", "gpd1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
i2c1_bus: i2c1-bus-pins {
samsung,pins = "gpd1-2", "gpd1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
i2c2_bus: i2c2-bus-pins {
samsung,pins = "gpd1-4", "gpd1-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
pwm0_out: pwm0-out-pins {
samsung,pins = "gpd0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
pwm1_out: pwm1-out-pins {
samsung,pins = "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
pwm2_out: pwm2-out-pins {
samsung,pins = "gpd0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
pwm3_out: pwm3-out-pins {
samsung,pins = "gpd0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row0: keypad-row-0-pins {
samsung,pins = "gph3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row1: keypad-row-1-pins {
samsung,pins = "gph3-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row2: keypad-row-2-pins {
samsung,pins = "gph3-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row3: keypad-row-3-pins {
samsung,pins = "gph3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row4: keypad-row-4-pins {
samsung,pins = "gph3-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row5: keypad-row-5-pins {
samsung,pins = "gph3-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row6: keypad-row-6-pins {
samsung,pins = "gph3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_row7: keypad-row-7-pins {
samsung,pins = "gph3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col0: keypad-col-0-pins {
samsung,pins = "gph2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col1: keypad-col-1-pins {
samsung,pins = "gph2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col2: keypad-col-2-pins {
samsung,pins = "gph2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col3: keypad-col-3-pins {
samsung,pins = "gph2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col4: keypad-col-4-pins {
samsung,pins = "gph2-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col5: keypad-col-5-pins {
samsung,pins = "gph2-5";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col6: keypad-col-6-pins {
samsung,pins = "gph2-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
keypad_col7: keypad-col-7-pins {
samsung,pins = "gph2-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
sd0_clk: sd0-clk-pins {
samsung,pins = "gpg0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd0_cmd: sd0-cmd-pins {
samsung,pins = "gpg0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd0_cd: sd0-cd-pins {
samsung,pins = "gpg0-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd0_bus1: sd0-bus-width1-pins {
samsung,pins = "gpg0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd0_bus4: sd0-bus-width4-pins {
samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd0_bus8: sd0-bus-width8-pins {
samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd1_clk: sd1-clk-pins {
samsung,pins = "gpg1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd1_cmd: sd1-cmd-pins {
samsung,pins = "gpg1-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd1_cd: sd1-cd-pins {
samsung,pins = "gpg1-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd1_bus1: sd1-bus-width1-pins {
samsung,pins = "gpg1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd1_bus4: sd1-bus-width4-pins {
samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd2_clk: sd2-clk-pins {
samsung,pins = "gpg2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd2_cmd: sd2-cmd-pins {
samsung,pins = "gpg2-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd2_cd: sd2-cd-pins {
samsung,pins = "gpg2-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd2_bus1: sd2-bus-width1-pins {
samsung,pins = "gpg2-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd2_bus4: sd2-bus-width4-pins {
samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd2_bus8: sd2-bus-width8-pins {
samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd3_clk: sd3-clk-pins {
samsung,pins = "gpg3-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd3_cmd: sd3-cmd-pins {
samsung,pins = "gpg3-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd3_cd: sd3-cd-pins {
samsung,pins = "gpg3-2";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd3_bus1: sd3-bus-width1-pins {
samsung,pins = "gpg3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
sd3_bus4: sd3-bus-width4-pins {
samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
eint0: ext-int0-pins {
samsung,pins = "gph0-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
eint8: ext-int8-pins {
samsung,pins = "gph1-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
eint15: ext-int15-pins {
samsung,pins = "gph1-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
eint16: ext-int16-pins {
samsung,pins = "gph2-0";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
eint31: ext-int31-pins {
samsung,pins = "gph3-7";
- samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
cam_port_a_io: cam-port-a-io-pins {
samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
"gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
cam_port_a_clk_active: cam-port-a-clk-active-pins {
samsung,pins = "gpe1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
cam_port_a_clk_idle: cam-port-a-clk-idle-pins {
samsung,pins = "gpe1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
cam_port_b_io: cam-port-b-io-pins {
samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
"gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
"gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
cam_port_b_clk_active: cam-port-b-clk-active-pins {
samsung,pins = "gpj1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
};
cam_port_b_clk_idle: cam-port-b-clk-idle-pins {
samsung,pins = "gpj1-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
lcd_ctrl: lcd-ctrl-pins {
samsung,pins = "gpd0-0", "gpd0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
lcd_sync: lcd-sync-pins {
samsung,pins = "gpf0-0", "gpf0-1";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
lcd_clk: lcd-clk-pins {
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
lcd_data24: lcd-data-width24-pins {
@@ -842,8 +842,8 @@
"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
"gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
- samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
- samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
- samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
};
};
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.h b/arch/arm/boot/dts/s5pv210-pinctrl.h
new file mode 100644
index 000000000000..29bdf376d8f1
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung S5PV210 DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__
+#define __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__
+
+#define S5PV210_PIN_PULL_NONE 0
+#define S5PV210_PIN_PULL_DOWN 1
+#define S5PV210_PIN_PULL_UP 2
+
+/* Pin function in power down mode */
+#define S5PV210_PIN_PDN_OUT0 0
+#define S5PV210_PIN_PDN_OUT1 1
+#define S5PV210_PIN_PDN_INPUT 2
+#define S5PV210_PIN_PDN_PREV 3
+
+#define S5PV210_PIN_DRV_LV1 0
+#define S5PV210_PIN_DRV_LV2 2
+#define S5PV210_PIN_DRV_LV3 1
+#define S5PV210_PIN_DRV_LV4 3
+
+#define S5PV210_PIN_FUNC_INPUT 0
+#define S5PV210_PIN_FUNC_OUTPUT 1
+#define S5PV210_PIN_FUNC_2 2
+#define S5PV210_PIN_FUNC_3 3
+#define S5PV210_PIN_FUNC_4 4
+#define S5PV210_PIN_FUNC_5 5
+#define S5PV210_PIN_FUNC_6 6
+#define S5PV210_PIN_FUNC_EINT 0xf
+#define S5PV210_PIN_FUNC_F S5PV210_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index 353ba7b09a0c..1a9e4a96b2ff 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -117,7 +117,7 @@
};
};
- pdma0: dma@e0900000 {
+ pdma0: dma-controller@e0900000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xe0900000 0x1000>;
interrupt-parent = <&vic0>;
@@ -125,11 +125,9 @@
clocks = <&clocks CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
- pdma1: dma@e0a00000 {
+ pdma1: dma-controller@e0a00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xe0a00000 0x1000>;
interrupt-parent = <&vic0>;
@@ -137,8 +135,6 @@
clocks = <&clocks CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
};
adc: adc@e1700000 {
@@ -239,8 +235,8 @@
reg = <0xeee30000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <16>;
- dma-names = "rx", "tx", "tx-sec";
- dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>;
+ dma-names = "tx", "rx", "tx-sec";
+ dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 11>;
clock-names = "iis",
"i2s_opclk0",
"i2s_opclk1";
@@ -259,8 +255,8 @@
reg = <0xe2100000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <17>;
- dma-names = "rx", "tx";
- dmas = <&pdma1 12>, <&pdma1 13>;
+ dma-names = "tx", "rx";
+ dmas = <&pdma1 13>, <&pdma1 12>;
clock-names = "iis", "i2s_opclk0";
clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>;
pinctrl-names = "default";
@@ -274,8 +270,8 @@
reg = <0xe2a00000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <18>;
- dma-names = "rx", "tx";
- dmas = <&pdma1 14>, <&pdma1 15>;
+ dma-names = "tx", "rx";
+ dmas = <&pdma1 15>, <&pdma1 14>;
clock-names = "iis", "i2s_opclk0";
clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
pinctrl-names = "default";
@@ -361,7 +357,7 @@
status = "disabled";
};
- sdhci0: sdhci@eb000000 {
+ sdhci0: mmc@eb000000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb000000 0x100000>;
interrupt-parent = <&vic1>;
@@ -372,7 +368,7 @@
status = "disabled";
};
- sdhci1: sdhci@eb100000 {
+ sdhci1: mmc@eb100000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb100000 0x100000>;
interrupt-parent = <&vic1>;
@@ -383,7 +379,7 @@
status = "disabled";
};
- sdhci2: sdhci@eb200000 {
+ sdhci2: mmc@eb200000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb200000 0x100000>;
interrupt-parent = <&vic1>;
@@ -394,7 +390,7 @@
status = "disabled";
};
- sdhci3: sdhci@eb300000 {
+ sdhci3: mmc@eb300000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb300000 0x100000>;
interrupt-parent = <&vic3>;
@@ -427,38 +423,28 @@
status = "disabled";
};
- ehci: ehci@ec200000 {
+ ehci: usb@ec200000 {
compatible = "samsung,exynos4210-ehci";
reg = <0xec200000 0x100>;
interrupts = <23>;
interrupt-parent = <&vic1>;
clocks = <&clocks CLK_USB_HOST>;
clock-names = "usbhost";
- #address-cells = <1>;
- #size-cells = <0>;
+ phys = <&usbphy 1>;
+ phy-names = "host";
status = "disabled";
-
- port@0 {
- reg = <0>;
- phys = <&usbphy 1>;
- };
};
- ohci: ohci@ec300000 {
+ ohci: usb@ec300000 {
compatible = "samsung,exynos4210-ohci";
reg = <0xec300000 0x100>;
interrupts = <23>;
interrupt-parent = <&vic1>;
clocks = <&clocks CLK_USB_HOST>;
clock-names = "usbhost";
- #address-cells = <1>;
- #size-cells = <0>;
+ phys = <&usbphy 1>;
+ phy-names = "host";
status = "disabled";
-
- port@0 {
- reg = <0>;
- phys = <&usbphy 1>;
- };
};
mfc: codec@f1700000 {
@@ -528,7 +514,7 @@
clock-names = "sclk_fimg2d", "fimg2d";
};
- mdma1: mdma@fa200000 {
+ mdma1: dma-controller@fa200000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xfa200000 0x1000>;
interrupt-parent = <&vic0>;
@@ -536,8 +522,6 @@
clocks = <&clocks CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
};
rotator: rotator@fa300000 {
@@ -582,7 +566,7 @@
interrupts = <29>;
clocks = <&clocks CLK_CSIS>,
<&clocks SCLK_CSIS>;
- clock-names = "clk_csis",
+ clock-names = "csis",
"sclk_csis";
bus-width = <4>;
status = "disabled";
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
index 998629a3c34f..e67ede940071 100644
--- a/arch/arm/boot/dts/sam9x60.dtsi
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
/ {
@@ -169,6 +170,64 @@
#size-cells = <1>;
ranges = <0x0 0xf0000000 0x800>;
status = "disabled";
+
+ uart4: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(8))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(9))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ spi4: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(8))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(9))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(8))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(9))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx5: flexcom@f0004000 {
@@ -179,6 +238,65 @@
#size-cells = <1>;
ranges = <0x0 0xf0004000 0x800>;
status = "disabled";
+
+ uart5: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(10))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ spi5: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(10))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(10))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
dma0: dma-controller@f0008000 {
@@ -250,6 +368,45 @@
#size-cells = <1>;
ranges = <0x0 0xf0020000 0x800>;
status = "disabled";
+
+ uart11: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(22))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(23))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(22))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(23))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx12: flexcom@f0024000 {
@@ -260,6 +417,45 @@
#size-cells = <1>;
ranges = <0x0 0xf0024000 0x800>;
status = "disabled";
+
+ uart12: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(24))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(25))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(24))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(25))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
pit64b: timer@f0028000 {
@@ -378,6 +574,45 @@
#size-cells = <1>;
ranges = <0x0 0xf8010000 0x800>;
status = "disabled";
+
+ uart6: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(13))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(13))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx7: flexcom@f8014000 {
@@ -388,6 +623,45 @@
#size-cells = <1>;
ranges = <0x0 0xf8014000 0x800>;
status = "disabled";
+
+ uart7: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx8: flexcom@f8018000 {
@@ -398,6 +672,45 @@
#size-cells = <1>;
ranges = <0x0 0xf8018000 0x800>;
status = "disabled";
+
+ uart8: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(17))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(17))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx0: flexcom@f801c000 {
@@ -408,6 +721,64 @@
#size-cells = <1>;
ranges = <0x0 0xf801c000 0x800>;
status = "disabled";
+
+ uart0: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(0))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(1))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ spi0: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(0))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(1))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(0))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(1))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx1: flexcom@f8020000 {
@@ -418,6 +789,64 @@
#size-cells = <1>;
ranges = <0x0 0xf8020000 0x800>;
status = "disabled";
+
+ uart1: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(2))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(3))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ spi1: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(2))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(3))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(2))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(3))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx2: flexcom@f8024000 {
@@ -428,6 +857,64 @@
#size-cells = <1>;
ranges = <0x0 0xf8024000 0x800>;
status = "disabled";
+
+ uart2: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(4))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(5))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ spi2: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(4))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(5))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(4))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(5))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx3: flexcom@f8028000 {
@@ -438,6 +925,64 @@
#size-cells = <1>;
ranges = <0x0 0xf8028000 0x800>;
status = "disabled";
+
+ uart3: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(6))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(7))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ spi3: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(6))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(7))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(6))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(7))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
macb0: ethernet@f802c000 {
@@ -464,7 +1009,7 @@
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
#pwm-cells = <3>;
- status="disabled";
+ status = "disabled";
};
hlcdc: hlcdc@f8038000 {
@@ -503,6 +1048,45 @@
#size-cells = <1>;
ranges = <0x0 0xf8040000 0x800>;
status = "disabled";
+
+ uart9: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(18))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(19))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(18))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(19))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx10: flexcom@f8044000 {
@@ -513,6 +1097,45 @@
#size-cells = <1>;
ranges = <0x0 0xf8044000 0x800>;
status = "disabled";
+
+ uart10: serial@200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(20))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(21))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(20))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(21))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
isi: isi@f8048000 {
@@ -563,7 +1186,7 @@
mpddrc: mpddrc@ffffe800 {
compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
reg = <0xffffe800 0x200>;
- clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
clock-names = "ddrck", "mpddr";
};
@@ -583,6 +1206,7 @@
dbgu: serial@fffff200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
@@ -667,7 +1291,7 @@
clock-names = "td_slck", "md_slck", "main_xtal";
};
- reset_controller: rstc@fffffe00 {
+ reset_controller: reset-controller@fffffe00 {
compatible = "microchip,sam9x60-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k 0>;
@@ -684,7 +1308,7 @@
status = "disabled";
};
- rtt: rtt@fffffe20 {
+ rtt: rtc@fffffe20 {
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xfffffe20 0x20>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 89c71d419f82..14c35c12a115 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
/ {
@@ -99,6 +100,16 @@
ranges = <0 0x00200000 0x20000>;
};
+ resistive_touch: resistive-touch {
+ compatible = "resistive-adc-touch";
+ io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
+ <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
+ <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
+ io-channel-names = "x", "y", "pressure";
+ touchscreen-min-pressure = <50000>;
+ status = "disabled";
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -374,8 +385,6 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "hclk", "pclk";
status = "disabled";
@@ -433,6 +442,7 @@
uart0: serial@f801c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
@@ -449,6 +459,7 @@
uart1: serial@f8020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
@@ -465,6 +476,7 @@
uart2: serial@f8024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8024000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
@@ -522,6 +534,7 @@
uart5: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "usart";
@@ -592,6 +605,7 @@
uart6: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "usart";
@@ -660,7 +674,7 @@
ranges = <0 0xf8044000 0x1420>;
};
- reset_controller: rstc@f8048000 {
+ reset_controller: reset-controller@f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
clocks = <&clk32k>;
@@ -761,6 +775,7 @@
uart3: serial@fc008000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfc008000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
@@ -777,6 +792,7 @@
uart4: serial@fc00c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfc00c000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(43))>,
@@ -802,6 +818,7 @@
uart7: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "usart";
@@ -872,6 +889,7 @@
uart8: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usart";
@@ -943,6 +961,7 @@
uart9: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "usart";
@@ -1050,16 +1069,6 @@
status = "disabled";
};
- resistive_touch: resistive-touch {
- compatible = "resistive-adc-touch";
- io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
- <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
- <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
- io-channel-names = "x", "y", "pressure";
- touchscreen-min-pressure = <50000>;
- status = "disabled";
- };
-
pioA: pinctrl@fc038000 {
compatible = "atmel,sama5d2-pinctrl";
reg = <0xfc038000 0x600>;
@@ -1124,7 +1133,7 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
clock-names = "pclk", "gclk";
assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
- assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
+ assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 8fa423c52592..bde8e92d60bb 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@@ -194,6 +195,7 @@
usart0: serial@f001c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf001c000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
@@ -208,6 +210,7 @@
usart1: serial@f0020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf0020000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
<&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
@@ -222,6 +225,7 @@
uart0: serial@f0024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf0024000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
@@ -356,6 +360,7 @@
usart2: serial@f8020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
<&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
@@ -370,6 +375,7 @@
usart3: serial@f8024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8024000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
<&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
@@ -464,6 +470,7 @@
dbgu: serial@ffffee00 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xffffee00 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
<&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
@@ -1003,7 +1010,7 @@
clock-names = "slow_clk", "main_xtal";
};
- reset_controller: rstc@fffffe00 {
+ reset_controller: reset-controller@fffffe00 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 10fc80d6d30d..1f2dfb3127ab 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -40,7 +40,7 @@
};
leds {
- d3 {
+ led-d3 {
label = "d3";
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index 2335bf906f69..bffd61397cb5 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -50,7 +50,7 @@
};
leds {
- d3 {
+ led-d3 {
label = "d3";
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index a3eaba995cf4..44d1173f2ffb 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
aliases {
@@ -39,6 +40,7 @@
uart0: serial@f0024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf0024000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
@@ -50,6 +52,7 @@
uart1: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 384335635792..7d1d7859edb4 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -130,7 +130,7 @@
leds {
compatible = "gpio-leds";
- d2 {
+ led-d2 {
label = "d2";
gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
index 5579c955f141..830a0954ba1b 100644
--- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
@@ -184,7 +184,7 @@
leds {
compatible = "gpio-leds";
- d2 {
+ led-d2 {
label = "d2";
gpios = <&pioE 25 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index a499de8a7a64..3652c9e24124 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -26,7 +26,7 @@
spi0: spi@f0004000 {
dmas = <0>, <0>; /* Do not use DMA for spi0 */
- m25p80@0 {
+ flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
index fa9e5e2a745d..5d9e97fecf83 100644
--- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
@@ -25,7 +25,7 @@
spi0: spi@f0004000 {
dmas = <0>, <0>; /* Do not use DMA for spi0 */
- m25p80@0 {
+ flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 7b9242664875..af62157ae214 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
@@ -278,6 +279,7 @@
uart0: serial@f8004000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8004000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
@@ -437,6 +439,7 @@
usart0: serial@f802c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf802c000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
@@ -455,6 +458,7 @@
usart1: serial@f8030000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8030000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
@@ -490,6 +494,7 @@
uart1: serial@fc004000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfc004000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
@@ -508,6 +513,7 @@
usart2: serial@fc008000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfc008000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
@@ -526,6 +532,7 @@
usart3: serial@fc00c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfc00c000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
@@ -544,6 +551,7 @@
usart4: serial@fc010000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfc010000 0x100>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma1
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
@@ -726,7 +734,7 @@
};
};
- reset_controller: rstc@fc068600 {
+ reset_controller: reset-controller@fc068600 {
compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
reg = <0xfc068600 0x10>;
clocks = <&clk32k>;
@@ -770,6 +778,7 @@
dbgu: serial@fc069000 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfc069000 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h
index 4eb30445d205..a67a156e26ab 100644
--- a/arch/arm/boot/dts/sama7g5-pinfunc.h
+++ b/arch/arm/boot/dts/sama7g5-pinfunc.h
@@ -261,7 +261,7 @@
#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1)
#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1)
#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1)
-#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3)
+#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB3 35
#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0)
#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1)
@@ -673,7 +673,7 @@
#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0)
#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1)
#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1)
-#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2)
+#define PIN_PD8__A22_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2)
#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2)
#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5)
#define PIN_PD9 105
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 4decd3a91a76..929ba73702e9 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -9,11 +9,15 @@
*
*/
+#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Microchip SAMA7G5 family SoC";
@@ -33,6 +37,7 @@
clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
};
};
@@ -71,6 +76,46 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&thermal_sensor>;
+
+ trips {
+ cpu_normal: cpu-alert0 {
+ temperature = <90000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ cpu_hot: cpu-alert1 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ cpu_critical: cpu-critical {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_normal>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
clocks {
slow_xtal: slow_xtal {
compatible = "fixed-clock";
@@ -107,6 +152,13 @@
ranges;
};
+ thermal_sensor: thermal-sensor {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>;
+ io-channel-names = "sensor-channel";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -152,7 +204,7 @@
};
};
- securam: securam@e0000000 {
+ securam: sram@e0000000 {
compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
reg = <0xe0000000 0x4000>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
@@ -198,6 +250,13 @@
clock-names = "td_slck", "md_slck", "main_xtal";
};
+ reset_controller: reset-controller@e001d000 {
+ compatible = "microchip,sama7g5-rstc";
+ reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clk32k 0>;
+ };
+
shdwc: shdwc@e001d010 {
compatible = "microchip,sama7g5-shdwc", "syscon";
reg = <0xe001d010 0x10>;
@@ -209,7 +268,7 @@
status = "disabled";
};
- rtt: rtt@e001d020 {
+ rtt: rtc@e001d020 {
compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xe001d020 0x30>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -412,6 +471,9 @@
atmel,min-sample-rate-hz = <200000>;
atmel,max-sample-rate-hz = <20000000>;
atmel,startup-time-ms = <4>;
+ #io-channel-cells = <1>;
+ nvmem-cells = <&temperature_calib>;
+ nvmem-cell-names = "temperature_calib";
status = "disabled";
};
@@ -454,6 +516,57 @@
status = "disabled";
};
+ csi2dc: csi2dc@e1404000 {
+ compatible = "microchip,sama7g5-csi2dc";
+ reg = <0xe1404000 0x500>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>;
+ clock-names = "pclk", "scck";
+ assigned-clocks = <&xisc>;
+ assigned-clock-rates = <266000000>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csi2dc_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csi2dc_out: endpoint {
+ bus-width = <14>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ remote-endpoint = <&xisc_in>;
+ };
+ };
+ };
+ };
+
+ xisc: xisc@e1408000 {
+ compatible = "microchip,sama7g5-isc";
+ reg = <0xe1408000 0x2000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
+ clock-names = "hclock";
+ #clock-cells = <0>;
+ clock-output-names = "isc-mck";
+ status = "disabled";
+
+ port {
+ xisc_in: endpoint {
+ bus-type = <5>; /* Parallel */
+ bus-width = <14>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ remote-endpoint = <&csi2dc_out>;
+ };
+ };
+ };
+
pwm: pwm@e1604000 {
compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
reg = <0xe1604000 0x4000>;
@@ -463,6 +576,30 @@
status = "disabled";
};
+ pdmc0: sound@e1608000 {
+ compatible = "microchip,sama7g5-pdmc";
+ reg = <0xe1608000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ #sound-dai-cells = <0>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>;
+ dma-names = "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>;
+ clock-names = "pclk", "gclk";
+ status = "disabled";
+ };
+
+ pdmc1: sound@e160c000 {
+ compatible = "microchip,sama7g5-pdmc";
+ reg = <0xe160c000 0x1000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ #sound-dai-cells = <0>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>;
+ dma-names = "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>;
+ clock-names = "pclk", "gclk";
+ status = "disabled";
+ };
+
spdifrx: spdifrx@e1614000 {
#sound-dai-cells = <0>;
compatible = "microchip,sama7g5-spdifrx";
@@ -572,6 +709,7 @@
uart0: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
clock-names = "usart";
@@ -601,9 +739,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
atmel,fifo-size = <32>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
- <&dma0 AT91_XDMAC_DT_PERID(8)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
+ <&dma0 AT91_XDMAC_DT_PERID(7)>;
+ dma-names = "tx", "rx";
status = "disabled";
};
};
@@ -620,6 +758,7 @@
uart3: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "usart";
@@ -663,6 +802,7 @@
uart4: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
clock-names = "usart";
@@ -688,6 +828,7 @@
uart7: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
clock-names = "usart";
@@ -786,9 +927,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
atmel,fifo-size = <32>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
- <&dma0 AT91_XDMAC_DT_PERID(22)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
+ <&dma0 AT91_XDMAC_DT_PERID(21)>;
+ dma-names = "tx", "rx";
status = "disabled";
};
};
@@ -810,9 +951,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
atmel,fifo-size = <32>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,
- <&dma0 AT91_XDMAC_DT_PERID(24)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
+ <&dma0 AT91_XDMAC_DT_PERID(23)>;
+ dma-names = "tx", "rx";
status = "disabled";
};
};
@@ -835,9 +976,9 @@
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
- <&dma0 AT91_XDMAC_DT_PERID(28)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>,
+ <&dma0 AT91_XDMAC_DT_PERID(27)>;
+ dma-names = "tx", "rx";
status = "disabled";
};
};
@@ -852,12 +993,22 @@
reg = <0xe3804000 0x1000>;
};
+ otpc: efuse@e8c00000 {
+ compatible = "microchip,sama7g5-otpc", "syscon";
+ reg = <0xe8c00000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ temperature_calib: calib@1 {
+ reg = <OTP_PKT(1) 76>;
+ };
+ };
+
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- interrupt-parent;
reg = <0xe8c11000 0x1000>,
<0xe8c12000 0x2000>;
};
diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
index a61a078ea042..69381819e07b 100644
--- a/arch/arm/boot/dts/sd5203.dts
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -15,7 +15,7 @@
#size-cells = <1>;
chosen {
- bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
+ bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
};
aliases {
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 7c1d6423d7f8..4c1d140f40f8 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -46,7 +46,7 @@
<0xff113000 0x1000>;
};
- intc: intc@fffed000 {
+ intc: interrupt-controller@fffed000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
@@ -80,8 +80,6 @@
<0 110 4>,
<0 111 4>;
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
resets = <&rst DMA_RESET>;
@@ -455,7 +453,6 @@
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
clk-gate = <0xa0 8>;
- clk-phase = <0 135>;
};
sdmmc_clk_divided: sdmmc_clk_divided {
@@ -563,6 +560,12 @@
interrupts = <0 175 4>;
};
+ socfpga_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <0 0 0 0 16 0 0>;
+ };
+
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
@@ -578,6 +581,7 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -596,6 +600,7 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -744,12 +749,12 @@
arm,prefetch-offset = <7>;
};
- l3regs@0xff800000 {
+ l3regs@ff800000 {
compatible = "altr,l3regs", "syscon";
reg = <0xff800000 0x1000>;
};
- mmc: dwmmc0@ff704000 {
+ mmc: mmc@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <0 139 4>;
@@ -759,6 +764,7 @@
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
+ altr,sysmgr-syscon = <&sysmgr 0x108 3>;
status = "disabled";
};
@@ -899,7 +905,7 @@
reset-names = "timer";
};
- uart0: serial0@ffc02000 {
+ uart0: serial@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x1000>;
interrupts = <0 162 4>;
@@ -912,7 +918,7 @@
resets = <&rst UART0_RESET>;
};
- uart1: serial1@ffc03000 {
+ uart1: serial@ffc03000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc03000 0x1000>;
interrupts = <0 163 4>;
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 3ba431dfa8c9..72c55e5187ca 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -38,7 +38,7 @@
<0xff113000 0x1000>;
};
- intc: intc@ffffd000 {
+ intc: interrupt-controller@ffffd000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
@@ -73,8 +73,6 @@
<0 90 IRQ_TYPE_LEVEL_HIGH>,
<0 91 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
@@ -367,7 +365,6 @@
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&sdmmc_free_clk>;
clk-gate = <0xC8 5>;
- clk-phase = <0 135>;
};
qspi_clk: qspi_clk {
@@ -658,7 +655,7 @@
arm,shared-override;
};
- mmc: dwmmc0@ff808000 {
+ mmc: mmc@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
@@ -668,6 +665,7 @@
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
+ altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled";
};
@@ -738,6 +736,16 @@
<37 IRQ_TYPE_LEVEL_HIGH>;
};
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
@@ -837,7 +845,7 @@
reset-names = "timer";
};
- uart0: serial0@ffc02000 {
+ uart0: serial@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -848,7 +856,7 @@
status = "disabled";
};
- uart1: serial1@ffc02100 {
+ uart1: serial@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 000000000000..422d00cd4c74
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ model = "Google Chameleon V3";
+ compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ ssm2603: audio-codec@1a {
+ compatible = "adi,ssm2603";
+ reg = <0x1a>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ u80: gpio@21 {
+ compatible = "nxp,pca9535";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SOM_AUD_MUTE",
+ "DP1_OUT_CEC_EN",
+ "DP2_OUT_CEC_EN",
+ "DP1_SOM_PS8469_CAD",
+ "DPD_SOM_PS8469_CAD",
+ "DP_OUT_PWR_EN",
+ "STM32_RST_L",
+ "STM32_BOOT0",
+
+ "FPGA_PROT",
+ "STM32_FPGA_COMM0",
+ "TP119",
+ "TP120",
+ "TP121",
+ "TP122",
+ "TP123",
+ "TP124";
+ };
+};
+
+&mmc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index a75c059b6727..41f865c8c098 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
+/*
+ * Copyright 2022 Google LLC
+ */
#include "socfpga_arria10.dtsi"
@@ -11,8 +13,6 @@
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
};
memory@0 {
@@ -26,24 +26,11 @@
};
};
-&eccmgr {
- sdmmca-ecc@ff8c2c00 {
- compatible = "altr,socfpga-sdmmc-ecc";
- reg = <0xff8c2c00 0x400>;
- altr,ecc-parent = <&mmc>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <16 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>;
- };
-};
-
&gmac0 {
phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */
max-frame-size = <3800>;
- status = "okay";
phy-handle = <&phy3>;
@@ -69,22 +56,13 @@
};
};
-&gpio0 {
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gpio2 {
- status = "okay";
-};
-
&i2c1 {
- status = "okay";
+ atsha204a: crypto@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+
isl12022: isl12022@6f {
- status = "okay";
compatible = "isil,isl12022";
reg = <0x6f>;
};
@@ -92,21 +70,12 @@
/* Following mappings are taken from arria10 socdk dts */
&mmc {
- status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
clock-frequency = <33330000>;
};
-
-&uart1 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- dr_mode = "host";
-};
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts
new file mode 100644
index 000000000000..cf533f76a9fd
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2023 Steffen Trumtrar <kernel@pengutronix.de>
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ PE1";
+ compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
index 9aa897b79544..a662df319a84 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
@@ -16,11 +16,11 @@
partition@0 {
label = "Boot and fpga data";
- reg = <0x0 0x02000000>;
+ reg = <0x0 0x02500000>;
};
partition@1c00000 {
label = "Root Filesystem - JFFS2";
- reg = <0x02000000 0x06000000>;
+ reg = <0x02500000 0x05500000>;
};
};
};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
index 2a745522404d..11ccdc6c2dc6 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
@@ -9,7 +9,7 @@
&qspi {
status = "okay";
- flash0: n25q00@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,mt25qu02g", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
index 64dc0799f3d7..d3969367f4b5 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -12,6 +12,7 @@
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&eccmgr {
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 22dbf07afcff..40fecde65c54 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -18,11 +18,12 @@
};
};
- mmc0: dwmmc0@ff704000 {
+ mmc0: mmc@ff704000 {
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 7f5458d8fccc..c48385702a85 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -29,22 +29,22 @@
leds {
compatible = "gpio-leds";
- hps0 {
+ led-hps0 {
label = "hps_led0";
gpios = <&porta 0 1>;
};
- hps1 {
+ led-hps1 {
label = "hps_led1";
gpios = <&portb 11 1>;
};
- hps2 {
+ led-hps2 {
label = "hps_led2";
gpios = <&porta 17 1>;
};
- hps3 {
+ led-hps3 {
label = "hps_led3";
gpios = <&porta 18 1>;
};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 319a71e41ea4..305fe207b237 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -18,11 +18,12 @@
};
};
- mmc0: dwmmc0@ff704000 {
+ mmc0: mmc@ff704000 {
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts
index c8f051fb2bf6..bedf577cb056 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -33,7 +33,7 @@
leds {
compatible = "gpio-leds";
- hps0 {
+ led-hps0 {
label = "hps_led0";
gpios = <&portb 24 0>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
index bd92806ffc12..3b9daddf91cd 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
@@ -18,5 +18,6 @@
&mmc0 { /* On-SoM eMMC */
bus-width = <8>;
+ clk-phase-sd-hs = <0>, <135>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 253ef139181d..c7f5fa0ba0f2 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -29,22 +29,22 @@
leds {
compatible = "gpio-leds";
- hps0 {
+ led-hps0 {
label = "hps_led0";
gpios = <&portb 15 1>;
};
- hps1 {
+ led-hps1 {
label = "hps_led1";
gpios = <&portb 14 1>;
};
- hps2 {
+ led-hps2 {
label = "hps_led2";
gpios = <&portb 13 1>;
};
- hps3 {
+ led-hps3 {
label = "hps_led3";
gpios = <&portb 12 1>;
};
@@ -121,7 +121,7 @@
&qspi {
status = "okay";
- flash0: n25q00@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,mt25qu02g", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index b0003f350e65..2564671fc1c6 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -113,7 +113,7 @@
&qspi {
status = "okay";
- flash0: n25q512a@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q512a", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index 25874e1b9c82..e0630b0eed03 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -141,7 +141,7 @@
reg = <0x50>;
};
- i2cswitch@70 {
+ i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@@ -221,7 +221,7 @@
&qspi {
status = "okay";
- n25q128@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128", "jedec,spi-nor";
@@ -238,7 +238,7 @@
cdns,tslch-ns = <4>;
};
- n25q00@1 {
+ flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,mt25qu02g", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index a77846f73b34..845ab2cc5ce6 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -29,7 +29,7 @@
};
};
- dwmmc0@ff704000 {
+ mmc@ff704000 {
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
@@ -57,11 +57,11 @@
clock-frequency = <7000000>;
};
- serial0@ffc02000 {
+ serial@ffc02000 {
clock-frequency = <7372800>;
};
- serial1@ffc03000 {
+ serial@ffc03000 {
clock-frequency = <7372800>;
};
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index 4cbadcb41084..05408df38203 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -170,7 +170,7 @@
smi: flash@ea000000 {
status = "okay";
- clock-rate=<50000000>;
+ clock-rate = <50000000>;
flash@e6000000 {
#address-cells = <1>;
@@ -379,7 +379,7 @@
};
};
- m25p80@1 {
+ flash@1 {
compatible = "st,m25p80";
reg = <1>;
spi-max-frequency = <12000000>;
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index fd194ebeedc9..7700f2afc128 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -168,7 +168,7 @@
smi: flash@ea000000 {
status = "okay";
- clock-rate=<50000000>;
+ clock-rate = <50000000>;
flash@e6000000 {
#address-cells = <1>;
@@ -439,7 +439,7 @@
cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
<&gpiopinctrl 85 0>;
- m25p80@0 {
+ flash@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <12000000>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 13e1bdb3ddbf..818886e11713 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -88,7 +88,7 @@
};
pwm: pwm@e0180000 {
- compatible ="st,spear13xx-pwm";
+ compatible = "st,spear13xx-pwm";
reg = <0xe0180000 0x1000>;
#pwm-cells = <2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 2beb30ca2cba..303ef29fb805 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -80,7 +80,7 @@
smi: flash@fc000000 {
status = "okay";
- clock-rate=<50000000>;
+ clock-rate = <50000000>;
flash@f8000000 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index b39bd5a22627..f1135e887f7b 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -46,7 +46,7 @@
status = "disabled";
};
- shirq: interrupt-controller@0x50000000 {
+ shirq: interrupt-controller@50000000 {
compatible = "st,spear300-shirq";
reg = <0x50000000 0x1000>;
interrupts = <28>;
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index 1c41e4a40334..ea0b53036f7b 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -94,7 +94,7 @@
smi: flash@fc000000 {
status = "okay";
- clock-rate=<50000000>;
+ clock-rate = <50000000>;
flash@f8000000 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index 77570833d46b..ce08d8820940 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -34,7 +34,7 @@
status = "disabled";
};
- shirq: interrupt-controller@0xb4000000 {
+ shirq: interrupt-controller@b4000000 {
compatible = "st,spear310-shirq";
reg = <0xb4000000 0x1000>;
interrupts = <28 29 30 1>;
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index c322407a0ade..3c026d021c92 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -95,7 +95,7 @@
smi: flash@fc000000 {
status = "okay";
- clock-rate=<50000000>;
+ clock-rate = <50000000>;
flash@f8000000 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts
index b587e4ec11e5..721e5ee7b680 100644
--- a/arch/arm/boot/dts/spear320-hmi.dts
+++ b/arch/arm/boot/dts/spear320-hmi.dts
@@ -167,7 +167,7 @@
smi: flash@fc000000 {
status = "okay";
- clock-rate=<50000000>;
+ clock-rate = <50000000>;
flash@f8000000 {
#address-cells = <1>;
@@ -241,7 +241,7 @@
irq-trigger = <0x1>;
stmpegpio: stmpe-gpio {
- compatible = "stmpe,gpio";
+ compatible = "st,stmpe-gpio";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 47ac4474ed96..56f141297ea3 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -49,7 +49,7 @@
status = "disabled";
};
- shirq: interrupt-controller@0xb3000000 {
+ shirq: interrupt-controller@b3000000 {
compatible = "st,spear320-shirq";
reg = <0xb3000000 0x1000>;
interrupts = <30 28 29 1>;
@@ -78,7 +78,7 @@
};
pwm: pwm@a8000000 {
- compatible ="st,spear-pwm";
+ compatible = "st,spear-pwm";
reg = <0xa8000000 0x1000>;
#pwm-cells = <2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index fd41243a0b2c..6b67c0ceaed9 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -47,7 +47,7 @@
compatible = "arm,pl110", "arm,primecell";
reg = <0xfc200000 0x1000>;
interrupt-parent = <&vic1>;
- interrupts = <12>;
+ interrupts = <13>;
status = "disabled";
};
@@ -207,6 +207,36 @@
interrupts = <6>;
status = "disabled";
};
+
+ ssp1: spi@d0100000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0xd0100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&vic0>;
+ interrupts = <26>;
+ status = "disabled";
+ };
+
+ ssp2: spi@d0180000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0xd0180000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&vic0>;
+ interrupts = <27>;
+ status = "disabled";
+ };
+
+ ssp3: spi@d8180000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0xd8180000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&vic1>;
+ interrupts = <5>;
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi
index 35137c6e52ee..dd30d08ccb9b 100644
--- a/arch/arm/boot/dts/ste-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-ab8500.dtsi
@@ -195,7 +195,7 @@
"CH_WD_EXP",
"VBUS_CH_DROP_END";
monitored-battery = <&battery>;
- vddadc-supply = <&ab8500_ldo_tvout_reg>;
+ vddadc-supply = <&ab8500_ldo_tvout_reg>;
io-channels = <&gpadc 0x03>,
<&gpadc 0x0a>,
<&gpadc 0x09>,
@@ -207,8 +207,8 @@
};
ab8500_chargalg {
- compatible = "stericsson,ab8500-chargalg";
- monitored-battery = <&battery>;
+ compatible = "stericsson,ab8500-chargalg";
+ monitored-battery = <&battery>;
};
ab8500_usb: phy {
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index dc0bcc7020f1..fead7afd5517 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/ste-db8500-clkout.h>
#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
#include <dt-bindings/mfd/dbx500-prcmu.h>
#include <dt-bindings/arm/ux500_pm_domains.h>
@@ -312,6 +313,11 @@
smp_twd_clk: smp-twd-clock {
#clock-cells = <0>;
};
+
+ clkout_clk: clkout-clock {
+ /* Cell 1 id, cell 2 source, cell 3 div */
+ #clock-cells = <3>;
+ };
};
mtu@a03c6000 {
@@ -661,7 +667,6 @@
#address-cells = <1>;
#size-cells = <0>;
- v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
@@ -679,7 +684,6 @@
#address-cells = <1>;
#size-cells = <0>;
- v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
@@ -698,7 +702,6 @@
#address-cells = <1>;
#size-cells = <0>;
- v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
@@ -717,7 +720,6 @@
#address-cells = <1>;
#size-cells = <0>;
- v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
@@ -736,7 +738,6 @@
#address-cells = <1>;
#size-cells = <0>;
- v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
@@ -755,7 +756,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
<&dma 8 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
@@ -772,7 +773,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
<&dma 9 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
@@ -790,7 +791,7 @@
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
<&dma 0 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
@@ -807,7 +808,7 @@
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
<&dma 35 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
@@ -824,7 +825,7 @@
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
<&dma 33 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
@@ -841,7 +842,7 @@
#size-cells = <0>;
/* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
<&dma 40 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
@@ -1154,17 +1155,15 @@
compatible = "stericsson,ux500-cryp";
reg = <0xa03cb000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-
- v-ape-supply = <&db8500_vape_reg>;
clocks = <&prcc_pclk 6 1>;
+ power-domains = <&pm_domains DOMAIN_VAPE>;
};
hash@a03c2000 {
compatible = "stericsson,ux500-hash";
reg = <0xa03c2000 0x1000>;
-
- v-ape-supply = <&db8500_vape_reg>;
clocks = <&prcc_pclk 6 2>;
+ power-domains = <&pm_domains DOMAIN_VAPE>;
};
};
};
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index fbaa0ce46427..e716121a78ce 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -24,6 +24,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
@@ -84,20 +92,20 @@
clock-mode = /bits/ 8 <2>;
#address-cells = <1>;
#size-cells = <0>;
- chan@0 {
+ led@0 {
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
};
- chan@1 {
+ led@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
- chan@2 {
+ led@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
@@ -111,19 +119,19 @@
clock-mode = /bits/ 8 <2>;
#address-cells = <1>;
#size-cells = <0>;
- chan@0 {
+ led@0 {
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
- chan@1 {
+ led@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
- chan@2 {
+ led@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 8f504edefd3f..e66fa59c2de6 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -353,11 +353,11 @@
* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
*/
hrefv60_cfg1 {
- pins ="GPIO65_F1";
+ pins = "GPIO65_F1";
ste,config = <&gpio_out_hi>;
};
hrefv60_cfg2 {
- pins ="GPIO66_G3";
+ pins = "GPIO66_G3";
ste,config = <&gpio_out_lo>;
};
};
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
index 8142c017882c..4d741adc16cd 100644
--- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -210,8 +210,8 @@
* As we're dealing with 3wire SPI, we only define SCK
* and MOSI (in the spec MOSI is called "SDA").
*/
- gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 1c9094f24893..e2f0cdacba7d 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -28,6 +28,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts
new file mode 100644
index 000000000000..e036393d5415
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts
@@ -0,0 +1,793 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO,
+ * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively
+ * for T-Mobile in the United States.
+ *
+ * This phone is closely related to the Codina, but has:
+ * - No CPU speed cap, full ~1GHz rate
+ * - Different power management IC, AB8505
+ * - As AB8505 has a micro USB phy, no TI TSU6111
+ * - Different power routing such as the removal of the external LDO for the
+ * touchscreen in favor of using the AB8505
+ * - Using a regulator for the key backlight LED
+ * - Using the Samsung S6D27A1 panel by default
+ * - The panel is using one of the ordinary AB8505 regulators for 1.8V
+ * - WiFi/Bluetooth combi chip upgraded to BCM4334
+ * - GPIO for backlight control moved from 68 to 69
+ */
+
+/dts-v1/;
+#include "ste-db8500.dtsi"
+#include "ste-ab8505.dtsi"
+#include "ste-dbx5x0-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Samsung Galaxy Exhibit (SGH-T599)";
+ compatible = "samsung,codina-tmo", "st-ericsson,u8500";
+
+ chosen {
+ stdout-path = &serial2;
+ };
+
+ battery: battery {
+ compatible = "samsung,eb425161lu";
+ };
+
+ thermal-zones {
+ battery-thermal {
+ /* This zone will be polled by the battery temperature code */
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ bat_therm: thermistor {
+ compatible = "samsung,1404-001221";
+ io-channels = <&gpadc 0x02>; /* BatTemp */
+ pullup-uv = <1800000>;
+ pullup-ohm = <230000>;
+ pulldown-ohm = <0>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ /* TI TXS0206 level translator for 2.9 V */
+ sd_level_translator: regulator-gpio {
+ compatible = "regulator-fixed";
+
+ /* GPIO87 EN */
+ gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ regulator-name = "sd-level-translator";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+
+ startup-delay-us = <200>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_level_translator_default>;
+ };
+
+ /* External LDO MIC5366-3.3YMT for eMMC */
+ ldo_3v3_reg: regulator-gpio-ldo-3v3 {
+ compatible = "regulator-fixed";
+ /* Supplied in turn by VBAT */
+ regulator-name = "VMEM_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_ldo_en_default_mode>;
+ };
+
+ /*
+ * External Ricoh RP152L010B-TR LCD LDO regulator for the display.
+ * LCD_PWR_EN controls both the 3.0V output.
+ */
+ lcd_3v0_reg: regulator-gpio-lcd-3v0 {
+ compatible = "regulator-fixed";
+ /* Supplied in turn by VBAT */
+ regulator-name = "VREG_LCD_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ /* GPIO219 controls this regulator */
+ gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pwr_en_default_mode>;
+ };
+
+ /*
+ * This regulator is a GPIO line that drives the Broadcom WLAN
+ * line WL_REG_ON high and enables the internal regulators
+ * inside the chip. Unfortunatley it is erroneously named
+ * WLAN_RST_N on the schematic but it is not a reset line.
+ *
+ * The voltage specified here is only used to determine the OCR mask,
+ * the for the SDIO connector, the chip is actually connected
+ * directly to VBAT.
+ */
+ wl_reg: regulator-gpio-wlan {
+ compatible = "regulator-fixed";
+ regulator-name = "WL_REG_ON";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ startup-delay-us = <100000>;
+ /* GPIO215 (WLAN_RST_N to WL_REG_ON) */
+ gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_ldo_en_default>;
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ /* GPIO195 "MOT_EN" */
+ enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_default>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default_mode>;
+
+ button-home {
+ linux,code = <KEY_HOME>;
+ label = "HOME";
+ /* GPIO91 */
+ gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
+ };
+ button-volup {
+ linux,code = <KEY_VOLUMEUP>;
+ label = "VOL+";
+ /* GPIO67 */
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ };
+ button-voldown {
+ linux,code = <KEY_VOLUMEDOWN>;
+ label = "VOL-";
+ /* GPIO92 */
+ gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ led-touchkeys {
+ compatible = "regulator-led";
+ vled-supply = <&ab8500_ldo_aux4_reg>; // 3.3V
+ default-state = "on";
+ function = LED_FUNCTION_KBD_BACKLIGHT;
+ color = <LED_COLOR_ID_WHITE>;
+ };
+
+ ktd253: backlight {
+ compatible = "kinetic,ktd253";
+ /* GPIO69 is used on Codina R0.4 and Codina TMO */
+ enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ /* Default to 13/32 brightness */
+ default-brightness = <13>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ktd253_backlight_default_mode>;
+ };
+
+ /* Richtek RT8515GQW Flash LED Driver IC */
+ flash {
+ compatible = "richtek,rt8515";
+ /* GPIO 140 */
+ enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ /* GPIO 141 */
+ ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ /*
+ * RFS is 16 kOhm and RTS is 100 kOhm giving
+ * the flash max current 343mA and torch max
+ * current 55 mA.
+ */
+ richtek,rfs-ohms = <16000>;
+ richtek,rts-ohms = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_flash_default_mode>;
+
+ led {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ flash-max-timeout-us = <250000>;
+ flash-max-microamp = <343750>;
+ led-max-microamp = <55000>;
+ };
+ };
+
+ /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_gpio_0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* TODO: this should also be used by the SM5103 Camera power management unit */
+ };
+
+ /* Bit-banged I2C on GPIO151 and GPIO152 also called "COMP I2C" */
+ i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_gpio_1_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@c {
+ compatible = "alps,hscdtd008a";
+ reg = <0x0c>;
+ clock-frequency = <400000>;
+
+ avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V
+ dvdd-supply = <&ab8500_ldo_aux8_reg>; // 1.8V
+ };
+ };
+
+ spi {
+ compatible = "spi-gpio";
+ /* Clock on GPIO220, pin SCL */
+ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
+ /* MOSI on GPIO224, pin SDI "slave data in" */
+ mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ /* MISO on GPIO225, pin SDO "slave data out" */
+ miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+ /* Chip select on GPIO201 */
+ cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_gpio_0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "samsung,s6d27a1";
+ spi-max-frequency = <1200000>;
+ /* TYPE 3: inverse clock polarity and phase */
+ spi-cpha;
+ spi-cpol;
+
+ reg = <0>;
+ vci-supply = <&lcd_3v0_reg>;
+ vccio-supply = <&ab8500_ldo_aux6_reg>;
+
+ /* Reset on GPIO139 */
+ reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */
+ interrupt-parent = <&gpio2>;
+ interrupts = <29 IRQ_TYPE_EDGE_RISING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_default_mode>;
+ backlight = <&ktd253>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+ };
+
+ soc {
+ /* External Micro SD slot */
+ mmc@80126000 {
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ st,sig-pin-fbclk;
+ full-pwr-cycle;
+ /* MMC is powered by AUX3 1.2V .. 2.91V */
+ vmmc-supply = <&ab8500_ldo_aux3_reg>;
+ /* 2.9 V level translator is using AUX3 at 2.9 V as well */
+ vqmmc-supply = <&sd_level_translator>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc0_a_2_default>;
+ pinctrl-1 = <&mc0_a_2_sleep>;
+ cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
+ status = "okay";
+ };
+
+ /* WLAN SDIO channel */
+ mmc@80118000 {
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ non-removable;
+ cap-sd-highspeed;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc1_a_2_default>;
+ pinctrl-1 = <&mc1_a_2_sleep>;
+ /*
+ * GPIO-controlled voltage enablement: this drives
+ * the WL_REG_ON line high when we use this device.
+ * Represented as regulator to fill OCR mask.
+ */
+ vmmc-supply = <&wl_reg>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ /* GPIO216 WL_HOST_WAKE */
+ interrupt-parent = <&gpio6>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default_mode>;
+ };
+ };
+
+ /* eMMC */
+ mmc@80005000 {
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ no-sdio;
+ no-sd;
+ vmmc-supply = <&ldo_3v3_reg>;
+ pinctrl-names = "default", "sleep";
+ /*
+ * GPIO130 will be set to input no pull-up resulting in a resistor
+ * pulling the reset high and taking the memory out of reset.
+ */
+ pinctrl-0 = <&mc2_a_1_default>;
+ pinctrl-1 = <&mc2_a_1_sleep>;
+ status = "okay";
+ };
+
+ /* GBF (Bluetooth) UART */
+ uart@80120000 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
+ status = "okay";
+
+ bluetooth {
+ /* BCM4334B0 actually */
+ compatible = "brcm,bcm4330-bt";
+ /* GPIO222 rail BT_VREG_EN to BT_REG_ON */
+ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
+ /* BT_WAKE on GPIO199 */
+ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ /* BT_HOST_WAKE on GPIO97 */
+ /* FIXME: convert to interrupt */
+ host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+ /* BT_RST_N on GPIO209 */
+ reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bluetooth_default_mode>;
+ };
+ };
+
+ /* GPS UART */
+ uart@80121000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ /* CTS/RTS is not used, CTS is repurposed as GPIO */
+ pinctrl-0 = <&u1rxtx_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep>;
+ /* FIXME: add a device for the GPS here */
+ };
+
+ /* Debugging console UART connected to AB8505 */
+ uart@80007000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
+ };
+
+ prcmu@80157000 {
+ ab8505 {
+ phy {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
+ };
+
+ ab8500_fg {
+ line-impedance-micro-ohms = <36000>;
+ };
+
+ /* This is mostly identical to the Codina v0.4 regulators */
+ regulator {
+ ab8500_ldo_aux1 {
+ regulator-name = "v-sensors-vdd";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux2 {
+ regulator-name = "v-aux2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux3 {
+ regulator-name = "v-mmc-sd";
+ };
+
+ ab8500_ldo_aux4 {
+ regulator-name = "v-aux4";
+ /*
+ * Providing some span here makes the touchkey
+ * LEDs actually dimmable.
+ */
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux5 {
+ regulator-name = "v-aux5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ab8500_ldo_aux6 {
+ /* 1.8 V to the display */
+ regulator-name = "v-aux6";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ab8500_ldo_aux8 {
+ regulator-name = "v-sensors-vio";
+ };
+ };
+ };
+ };
+
+ /* I2C0 also known as "AGC I2C" */
+ i2c@80004000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c0_a_1_default>;
+ pinctrl-1 = <&i2c0_a_1_sleep>;
+
+ proximity@39 {
+ /* Codina has the Amstaos TMD2672 */
+ compatible = "amstaos,tmd2672";
+ clock-frequency = <400000>;
+ reg = <0x39>;
+
+ /* IRQ on GPIO146 "PS_INT" */
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&ab8500_ldo_aux8_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tmd2672_codina_default>;
+ };
+ };
+
+ /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */
+ i2c@80128000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+
+ /* Bosch BMA254 accelerometer */
+ accelerometer@18 {
+ compatible = "bosch,bma254";
+ reg = <0x18>;
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+ vddio-supply = <&ab8500_ldo_aux8_reg>; // 1.8V
+ vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V
+ };
+ };
+
+ /* I2C3 */
+ i2c@80110000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+
+ /* TODO: write bindings and driver for this touchscreen */
+
+ /* Zinitix BT404 ISP part */
+ isp@50 {
+ compatible = "zinitix,bt404-isp";
+ reg = <0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_default>;
+ };
+
+ /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */
+ touchscreen@20 {
+ compatible = "zinitix,bt404";
+ reg = <0x20>;
+ /* GPIO218 (TSP_INT_1V8) */
+ interrupt-parent = <&gpio6>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ vcca-supply = <&ab8500_ldo_aux2_reg>; // 3.3V
+ vdd-supply = <&ab8500_ldo_aux5_reg>; // 1.8V
+ zinitix,mode = <2>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_default>;
+ };
+ };
+
+ mcde@a0350000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dpi_default_mode>;
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+};
+
+&pinctrl {
+ /*
+ * This extends the MC0_A_2 default config to include
+ * the card detect GPIO217 line.
+ */
+ sdi0 {
+ mc0_a_2_default {
+ default_cfg4 {
+ pins = "GPIO217_AH12"; /* card detect */
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+ sdi2 {
+ /*
+ * GPIO130 should be set in GPIO mode and
+ * pulled down. (Not connected.)
+ */
+ mc2_a_1_default {
+ default_cfg2 {
+ pins = "GPIO130_C8"; /* FBCLK */
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+ /* GPIO that enables the 2.9V SD card level translator */
+ sd-level-translator {
+ sd_level_translator_default: sd_level_translator_default {
+ /* level shifter on GPIO87 */
+ codina_cfg1 {
+ pins = "GPIO87_B3";
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ /* GPIO that enables the LDO regulator for the eMMC */
+ emmc-ldo {
+ emmc_ldo_en_default_mode: emmc_ldo_default {
+ /* LDO enable on GPIO223 */
+ codina_cfg1 {
+ pins = "GPIO223_AH9";
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ /* GPIOs for panel control */
+ panel {
+ panel_default_mode: panel_default {
+ codina_cfg1 {
+ /* Reset line */
+ pins = "GPIO139_C9";
+ ste,config = <&gpio_out_lo>;
+ };
+ codina_cfg2 {
+ /* ESD IRQ line "LCD detect" */
+ pins = "GPIO93_B7";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ /* GPIO that enables the LDO regulator for the LCD display */
+ lcd-ldo {
+ lcd_pwr_en_default_mode: lcd_pwr_en_default {
+ /* LCD_PWR_EN on GPIO219 */
+ codina_cfg1 {
+ pins = "GPIO219_AG10";
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ /* GPIO that enables the WLAN internal LDO regulators */
+ wlan-ldo {
+ wlan_ldo_en_default: wlan_ldo_default {
+ /* GPIO215 named WLAN_RST_N */
+ codina_cfg1 {
+ pins = "GPIO215_AH13";
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ /* Backlight GPIO */
+ backlight {
+ ktd253_backlight_default_mode: backlight_default {
+ skomer_cfg1 {
+ pins = "GPIO69_E2"; /* LCD_BL_CTRL */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ /* Flash and torch */
+ flash {
+ gpio_flash_default_mode: flash_default {
+ codina_cfg1 {
+ pins = "GPIO140_B11", "GPIO141_C12";
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ /* GPIO keys */
+ gpio-keys {
+ gpio_keys_default_mode: gpio_keys_default {
+ skomer_cfg1 {
+ pins = "GPIO67_G2", /* VOL UP */
+ "GPIO91_B6", /* HOME */
+ "GPIO92_D6"; /* VOL DOWN */
+ ste,config = <&gpio_in_pu>;
+ };
+ };
+ };
+ /* Interrupt line for the Zinitix BT404 touchscreen */
+ tsp {
+ tsp_default: tsp_default {
+ codina_cfg1 {
+ pins = "GPIO218_AH11"; /* TSP_INT_1V8 */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ /* Interrupt line for light/proximity sensor TMD2672 */
+ tmd2672 {
+ tmd2672_codina_default: tmd2672_codina {
+ codina_cfg1 {
+ pins = "GPIO146_D13";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ /* GPIO-based I2C bus for subpmu */
+ i2c-gpio-0 {
+ i2c_gpio_0_default: i2c_gpio_0 {
+ codina_cfg1 {
+ pins = "GPIO143_D12", "GPIO144_B13";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ /* GPIO-based I2C bus for the NFC */
+ i2c-gpio-1 {
+ i2c_gpio_1_default: i2c_gpio_1 {
+ codina_cfg1 {
+ pins = "GPIO151_D17", "GPIO152_D16";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ /* GPIO-based SPI bus for the display */
+ spi-gpio-0 {
+ spi_gpio_0_default: spi_gpio_0_d {
+ codina_cfg1 {
+ pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9";
+ ste,config = <&gpio_out_hi>;
+ };
+ codina_cfg2 {
+ pins = "GPIO225_AG8";
+ /* Needs pull down, no pull down resistor on board */
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ spi_gpio_0_sleep: spi_gpio_0_s {
+ codina_cfg1 {
+ pins = "GPIO220_AH10", "GPIO201_AF24",
+ "GPIO224_AG9", "GPIO225_AG8";
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ wlan {
+ wlan_default_mode: wlan_default {
+ /* GPIO216 for WL_HOST_WAKE */
+ codina_cfg2 {
+ pins = "GPIO216_AG12";
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+ bluetooth {
+ bluetooth_default_mode: bluetooth_default {
+ /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */
+ codina_cfg1 {
+ pins = "GPIO199_AH23", "GPIO222_AJ9";
+ ste,config = <&gpio_out_lo>;
+ };
+ /* GPIO97 BT_HOST_WAKE */
+ codina_cfg2 {
+ pins = "GPIO97_D9";
+ ste,config = <&gpio_in_nopull>;
+ };
+ /* GPIO209 BT_RST_N */
+ codina_cfg3 {
+ pins = "GPIO209_AG15";
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ vibrator {
+ vibrator_default: vibrator_default {
+ codina_cfg1 {
+ pins = "GPIO195_AG28"; /* MOT_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ mcde {
+ dpi_default_mode: dpi_default {
+ default_mux1 {
+ /* Mux in all the data lines */
+ function = "lcd";
+ groups =
+ /* Data lines D0-D7 GPIO70..GPIO77 */
+ "lcd_d0_d7_a_1",
+ /* Data lines D8-D11 GPIO78..GPIO81 */
+ "lcd_d8_d11_a_1",
+ /* Data lines D12-D15 GPIO82..GPIO85 */
+ "lcd_d12_d15_a_1",
+ /* Data lines D16-D23 GPIO161..GPIO168 */
+ "lcd_d16_d23_b_1";
+ };
+ default_mux2 {
+ function = "lcda";
+ /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */
+ groups = "lcdaclk_b_1", "lcda_b_1";
+ };
+ /* Input, no pull-up is the default state for pins used for an alt function */
+ default_cfg1 {
+ pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23";
+ ste,config = <&in_nopull>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
index 1c1725d31c7c..1a6d24a7ccb8 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
@@ -9,9 +9,13 @@
* the boot loader.
*
* The Samsung tree further talks about GT-I8160P and GT-I8160chn (China).
- * The GT-I8160 plain is knonw as the "europe" variant.
- * The GT-I8160P appears to not use the ST Microelectronics accelerometer.
+ * The GT-I8160 plain is known as the "europe" variant.
+ * The GT-I8160P is the CDMA version and it appears to not use the ST
+ * Microelectronics accelerometer and reportedly has NFC mounted.
* The GT-I8160chn appears to be the same as the europe variant.
+ *
+ * There is also the Codina-TMO, Samsung SGH-T599, which has its own device
+ * tree.
*/
/dts-v1/;
@@ -53,6 +57,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
@@ -303,10 +315,25 @@
#address-cells = <1>;
#size-cells = <0>;
- /* TODO: add the NFC chip here */
+ nfc@2b {
+ /* NXP NFC circuit PN544 C1 marked NXP 44501 */
+ compatible = "nxp,pn544-i2c";
+ /* IF0, IF1 high, gives I2C address 0x2B */
+ reg = <0x2b>;
+ clock-frequency = <400000>;
+ /* NFC IRQ on GPIO32 */
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ /* GPIO 31 */
+ firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+ /* GPIO88 */
+ enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pn544_codina_default>;
+ };
};
- spi-gpio-0 {
+ spi {
compatible = "spi-gpio";
/* Clock on GPIO220, pin SCL */
sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
@@ -461,10 +488,20 @@
uart@80121000 {
status = "okay";
pinctrl-names = "default", "sleep";
- /* CTS/RTS is not used, CTS is repurposed as GPIO */
- pinctrl-0 = <&u1rxtx_a_1_default>;
- pinctrl-1 = <&u1rxtx_a_1_sleep>;
- /* FIXME: add a device for the GPS here */
+ pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>;
+
+ gnss {
+ compatible = "brcm,bcm4751";
+ /* GPS_RSTN on GPIO21 */
+ reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ /* GPS_ON_OFF on GPIO86 */
+ enable-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ /* GPS_1V8 (VSMPS2) */
+ vddio-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bcm4751_codina_default>;
+ };
};
/* Debugging console UART connected to TSU6111RSVR (FSA880) */
@@ -483,6 +520,10 @@
pinctrl-1 = <&usb_a_1_sleep>;
};
+ ab8500_fg {
+ line-impedance-micro-ohms = <36000>;
+ };
+
regulator {
ab8500_ldo_aux1 {
/* Used for VDD for sensors */
@@ -515,10 +556,9 @@
pinctrl-0 = <&i2c0_a_1_default>;
pinctrl-1 = <&i2c0_a_1_sleep>;
- /* TODO: write bindings and driver for this proximity sensor */
proximity@39 {
- /* Codina has the Mouser TMD2672 */
- compatible = "mouser,tmd2672";
+ /* Codina has the Amstaos TMD2672 */
+ compatible = "amstaos,tmd2672";
clock-frequency = <400000>;
reg = <0x39>;
@@ -566,8 +606,8 @@
reg = <0x19>;
vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V
vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V
- mount-matrix = "0", "-1", "0",
- "1", "0", "0",
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
"0", "0", "1";
};
};
@@ -847,6 +887,34 @@
};
};
};
+ nfc {
+ pn544_codina_default: pn544_codina {
+ /* Interrupt line */
+ codina_cfg1 {
+ pins = "GPIO32_V2";
+ ste,config = <&gpio_in_nopull>;
+ };
+ /* Enable and firmware GPIOs */
+ codina_cfg2 {
+ pins = "GPIO31_V3", "GPIO88_C4";
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ bcm4751 {
+ bcm4751_codina_default: bcm4751_codina {
+ /* Reset line, start out asserted */
+ codina_cfg1 {
+ pins = "GPIO21_AB3";
+ ste,config = <&gpio_out_lo>;
+ };
+ /* GPS_ON_OFF, start out deasserted (off) */
+ codina_cfg2 {
+ pins = "GPIO86_C6";
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
vibrator {
vibrator_default: vibrator_default {
codina_cfg1 {
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts
index fd170974765f..5b445fa4c8c0 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts
@@ -30,6 +30,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
@@ -269,7 +277,7 @@
/*
* TODO: See if we can use the PL023 for this instead.
*/
- spi-gpio-0 {
+ spi {
compatible = "spi-gpio";
/* Clock on GPIO220, pin SCL */
sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
@@ -456,6 +464,10 @@
pinctrl-1 = <&usb_a_1_sleep>;
};
+ ab8500_fg {
+ line-impedance-micro-ohms = <43000>;
+ };
+
regulator {
ab8500_ldo_aux1 {
/* Used for VDD for sensors */
@@ -523,8 +535,8 @@
accelerometer@18 {
compatible = "bosch,bma222e";
reg = <0x18>;
- mount-matrix = "0", "1", "0",
- "-1", "0", "0",
+ mount-matrix = "0", "-1", "0",
+ "1", "0", "0",
"0", "0", "1";
vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V
vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
index 290ab59e863d..9604695edf53 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
@@ -35,6 +35,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
@@ -304,6 +312,10 @@
pinctrl-1 = <&usb_a_1_sleep>;
};
+ ab8500_fg {
+ line-impedance-micro-ohms = <36000>;
+ };
+
regulator {
ab8500_ldo_aux1 {
regulator-name = "sensor_3v";
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
index 42762bfcd878..e901cb76b899 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
@@ -30,6 +30,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
@@ -263,7 +271,7 @@
* this derivative is 3wire support, so it cannot be used to drive
* this panel interface. We have to use GPIO bit-banging instead.
*/
- spi-gpio-0 {
+ spi {
compatible = "spi-gpio";
/* Clock on GPIO220 */
sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
@@ -365,9 +373,13 @@
#address-cells = <1>;
#size-cells = <0>;
- nfc@30 {
- compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
- reg = <0x30>;
+ /* This is only mounted on the GT-I9070P */
+ nfc@2b { /* 0x30? */
+ /* NXP NFC circuit PN544 C1 marked NXP 44501 */
+ compatible = "nxp,pn544-i2c";
+ /* IF0, IF1 high, gives I2C address 0x2B */
+ reg = <0x2b>;
+ clock-frequency = <400000>;
/* NFC IRQ on GPIO32 */
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
@@ -376,7 +388,7 @@
/* GPIO88 */
enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&pn547_janice_default>;
+ pinctrl-0 = <&pn544_janice_default>;
};
};
@@ -485,7 +497,26 @@
/* CTS/RTS is not used, CTS is repurposed as GPIO */
pinctrl-0 = <&u1rxtx_a_1_default>;
pinctrl-1 = <&u1rxtx_a_1_sleep>;
- /* FIXME: add a device for the GPS here */
+
+ gnss {
+ /*
+ * The Low Noise Amplifier (LNA) power and enablement is controlled
+ * autonomously by the GSD4t.
+ * Janice has a SiRFstarIV-based GSD4t
+ * Golden has a SiRFstarV 5t-based CSRG05TA03-ICJE-R.
+ */
+ compatible = "csr,gsd4t";
+ /* GPS_RSTN on GPIO21 */
+ reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ /* GPS_ON_OFF on GPIO96 */
+ sirf,onoff-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+ /* GPS_1V8 (VSMPS2) */
+ vcc-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsd4t_janice_default>;
+ /* According to /etc/sirfgps.conf */
+ current-speed = <460800>;
+ };
};
/* Debugging console UART connected to TSU6111RSVR (FSA880) */
@@ -504,6 +535,10 @@
pinctrl-1 = <&usb_a_1_sleep>;
};
+ ab8500_fg {
+ line-impedance-micro-ohms = <15000>;
+ };
+
regulator {
ab8500_ldo_aux1 {
/* Used for VDD for sensors */
@@ -610,8 +645,8 @@
accelerometer@8 {
compatible = "bosch,bma222";
reg = <0x08>;
- mount-matrix = "0", "1", "0",
- "-1", "0", "0",
+ mount-matrix = "0", "-1", "0",
+ "1", "0", "0",
"0", "0", "1";
vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V
vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V
@@ -928,7 +963,7 @@
};
};
nfc {
- pn547_janice_default: pn547_janice {
+ pn544_janice_default: pn544_janice {
/* Interrupt line */
janice_cfg1 {
pins = "GPIO32_V2";
@@ -941,4 +976,23 @@
};
};
};
+ gsd4t {
+ gsd4t_janice_default: gsd4t_janice {
+ /* Reset line, start out asserted */
+ janice_cfg1 {
+ pins = "GPIO21_AB3";
+ ste,config = <&gpio_out_lo>;
+ };
+ /* GPS_ON_OFF, start out deasserted (off) */
+ janice_cfg2 {
+ pins = "GPIO96_D8";
+ ste,config = <&gpio_out_lo>;
+ };
+ /* Unused power enablement line, used in R0.0 and R0.1 boards */
+ janice_cfg3 {
+ pins = "GPIO86_C6";
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts
index 2a5bf54137ce..45fab5283a9d 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts
@@ -34,6 +34,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
@@ -307,6 +315,21 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>;
pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>;
+
+ gnss {
+ /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */
+ compatible = "csr,csrg05ta03-icje-r";
+ /* GPS_RSTN on GPIO21 */
+ reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ /* GPS_ON_OFF on GPIO86 */
+ sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ /* GPS_1V8 (VSMPS2) */
+ vcc-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&g05ta03_kyle_default>;
+ /* According to /etc/sirfgps.conf */
+ current-speed = <460800>;
+ };
};
/* Debugging console UART connected to AB8505 USB */
@@ -325,6 +348,10 @@
pinctrl-1 = <&usb_a_1_sleep>;
};
+ ab8500_fg {
+ line-impedance-micro-ohms = <36000>;
+ };
+
regulator {
ab8500_ldo_aux1 {
/* Used for VDD for sensors */
@@ -662,6 +689,20 @@
};
};
};
+ g05ta03 {
+ g05ta03_kyle_default: g05ta03 {
+ /* Reset line, start out de-asserted */
+ kyle_cfg1 {
+ pins = "GPIO21_AB3";
+ ste,config = <&gpio_out_hi>;
+ };
+ /* GPS_ON_OFF, start out deasserted (off) */
+ kyle_cfg2 {
+ pins = "GPIO86_C6";
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
};
&ab8505_gpio {
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
index dcb03ce7cbd4..93e5f5ed888d 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
@@ -30,6 +30,14 @@
polling-delay = <0>;
polling-delay-passive = <0>;
thermal-sensors = <&bat_therm>;
+
+ trips {
+ battery-crit-hi {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
@@ -281,12 +289,27 @@
};
};
- /* GPF UART */
+ /* GPS UART */
uart@80121000 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>;
pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>;
+
+ gnss {
+ /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */
+ compatible = "csr,csrg05ta03-icje-r";
+ /* GPS_RSTN on GPIO209 */
+ reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>;
+ /* GPS_ON_OFF on GPIO86 */
+ sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ /* GPS_1V8 (VSMPS2) */
+ vcc-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&g05ta03_skomer_default>;
+ /* According to /etc/sirfgps.conf */
+ current-speed = <460800>;
+ };
};
/* Debugging console UART connected to AB8505 USB */
@@ -305,6 +328,10 @@
pinctrl-1 = <&usb_a_1_sleep>;
};
+ ab8500_fg {
+ line-impedance-micro-ohms = <16000>;
+ };
+
regulator {
ab8500_ldo_aux1 {
/* Used for VDD for sensors */
@@ -649,6 +676,20 @@
};
};
};
+ g05ta03 {
+ g05ta03_skomer_default: g05ta03 {
+ /* Reset line, start out de-asserted */
+ skomer_cfg1 {
+ pins = "GPIO209_AG15";
+ ste,config = <&gpio_out_hi>;
+ };
+ /* GPS_ON_OFF, start out deasserted (off) */
+ skomer_cfg2 {
+ pins = "GPIO86_C6";
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
};
&ab8505_gpio {
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 1713f7878117..5ebb77947fd9 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -137,8 +137,8 @@
};
irq-syscfg {
- compatible = "st,stih407-irq-syscfg";
- st,syscfg = <&syscfg_core>;
+ compatible = "st,stih407-irq-syscfg";
+ st,syscfg = <&syscfg_core>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
@@ -157,8 +157,8 @@
miphy28lp_phy: miphy28lp {
compatible = "st,miphy28lp-phy";
st,syscfg = <&syscfg_core>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
ranges;
phy_port0: port@9b22000 {
@@ -208,26 +208,26 @@
};
st231_gp0: st231-gp0 {
- compatible = "st,st231-rproc";
- memory-region = <&gp0_reserved>;
- resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x22c>;
+ compatible = "st,st231-rproc";
+ memory-region = <&gp0_reserved>;
+ resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x22c>;
#mbox-cells = <1>;
mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
};
st231_delta: st231-delta {
- compatible = "st,st231-rproc";
- memory-region = <&delta_reserved>;
- resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
- reset-names = "sw_reset";
- clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
- clock-frequency = <600000000>;
- st,syscfg = <&syscfg_core 0x224>;
+ compatible = "st,st231-rproc";
+ memory-region = <&delta_reserved>;
+ resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x224>;
#mbox-cells = <1>;
mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
@@ -710,78 +710,78 @@
st_dwc3: dwc3@8f94000 {
- compatible = "st,stih407-dwc3";
- reg = <0x08f94000 0x1000>, <0x110 0x4>;
- reg-names = "reg-glue", "syscfg-reg";
- st,syscfg = <&syscfg_core>;
- resets = <&powerdown STIH407_USB3_POWERDOWN>,
- <&softreset STIH407_MIPHY2_SOFTRESET>;
- reset-names = "powerdown", "softreset";
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
+ compatible = "st,stih407-dwc3";
+ reg = <0x08f94000 0x1000>, <0x110 0x4>;
+ reg-names = "reg-glue", "syscfg-reg";
+ st,syscfg = <&syscfg_core>;
+ resets = <&powerdown STIH407_USB3_POWERDOWN>,
+ <&softreset STIH407_MIPHY2_SOFTRESET>;
+ reset-names = "powerdown", "softreset";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
ranges;
status = "disabled";
- dwc3: dwc3@9900000 {
- compatible = "snps,dwc3";
- reg = <0x09900000 0x100000>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- phy-names = "usb2-phy", "usb3-phy";
- phys = <&usb2_picophy0>,
- <&phy_port2 PHY_TYPE_USB3>;
+ dwc3: usb@9900000 {
+ compatible = "snps,dwc3";
+ reg = <0x09900000 0x100000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ phy-names = "usb2-phy", "usb3-phy";
+ phys = <&usb2_picophy0>,
+ <&phy_port2 PHY_TYPE_USB3>;
snps,dis_u3_susphy_quirk;
};
};
/* COMMS PWM Module */
pwm0: pwm@9810000 {
- compatible = "st,sti-pwm";
- #pwm-cells = <2>;
- reg = <0x9810000 0x68>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
- clock-names = "pwm";
- clocks = <&clk_sysin>;
+ compatible = "st,sti-pwm";
+ #pwm-cells = <2>;
+ reg = <0x9810000 0x68>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
st,pwm-num-chan = <1>;
- status = "disabled";
+ status = "disabled";
};
/* SBC PWM Module */
pwm1: pwm@9510000 {
- compatible = "st,sti-pwm";
- #pwm-cells = <2>;
- reg = <0x9510000 0x68>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1_chan0_default
- &pinctrl_pwm1_chan1_default
- &pinctrl_pwm1_chan2_default
- &pinctrl_pwm1_chan3_default>;
- clock-names = "pwm";
- clocks = <&clk_sysin>;
+ compatible = "st,sti-pwm";
+ #pwm-cells = <2>;
+ reg = <0x9510000 0x68>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1_chan0_default
+ &pinctrl_pwm1_chan1_default
+ &pinctrl_pwm1_chan2_default
+ &pinctrl_pwm1_chan3_default>;
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
st,pwm-num-chan = <4>;
- status = "disabled";
+ status = "disabled";
};
rng10: rng@8a89000 {
- compatible = "st,rng";
- reg = <0x08a89000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
+ compatible = "st,rng";
+ reg = <0x08a89000 0x1000>;
+ clocks = <&clk_sysin>;
+ status = "okay";
};
rng11: rng@8a8a000 {
- compatible = "st,rng";
- reg = <0x08a8a000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
+ compatible = "st,rng";
+ reg = <0x08a8a000 0x1000>;
+ clocks = <&clk_sysin>;
+ status = "okay";
};
ethernet0: dwmac@9630000 {
@@ -812,36 +812,36 @@
};
mailbox0: mailbox@8f00000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f00000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- mbox-name = "a9";
- status = "okay";
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f00000 0x1000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ mbox-name = "a9";
+ status = "okay";
};
mailbox1: mailbox@8f01000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f01000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_gp_1";
- status = "okay";
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f01000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_gp_1";
+ status = "okay";
};
mailbox2: mailbox@8f02000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f02000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_gp_0";
- status = "okay";
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f02000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_gp_0";
+ status = "okay";
};
mailbox3: mailbox@8f03000 {
- compatible = "st,stih407-mailbox";
- reg = <0x8f03000 0x1000>;
- #mbox-cells = <2>;
- mbox-name = "st231_audio_video";
- status = "okay";
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f03000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_audio_video";
+ status = "okay";
};
/* fdma audio */
@@ -913,7 +913,7 @@
dmas = <&fdma0 2 0 1>;
dma-names = "tx";
- status = "disabled";
+ status = "disabled";
};
sti_uni_player1: sti-uni-player@8d81000 {
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 9e212b0af89d..aca43d2bdaad 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -13,7 +13,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0>;
- assigned-clocks = <&clk_s_d2_quadfs 0>,
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
@@ -106,7 +106,7 @@
reg-names = "hdmi-reg";
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq";
+ interrupt-names = "irq";
clock-names = "pix",
"tmds",
"phy",
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index 26d93f26f6d0..240b62040000 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -27,26 +27,26 @@
leds {
compatible = "gpio-leds";
- user_green_1 {
+ led-user-green-1 {
label = "User_green_1";
gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
- user_green_2 {
+ led-user-green-2 {
label = "User_green_2";
gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- user_green_3 {
+ led-user-green-3 {
label = "User_green_3";
gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- user_green_4 {
+ led-user-green-4 {
label = "User_green_4";
gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
default-state = "off";
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index ce2f62cf129b..29e95e9d3229 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -105,7 +105,7 @@
#size-cells = <1>;
reg = <0 0>;
- assigned-clocks = <&clk_s_d2_quadfs 0>,
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
@@ -198,7 +198,7 @@
reg-names = "hdmi-reg";
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq";
+ interrupt-names = "irq";
clock-names = "pix",
"tmds",
"phy",
@@ -272,7 +272,7 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
- sti-cec@94a087c {
+ cec@94a087c {
compatible = "st,stih-cec";
reg = <0x94a087c 0x64>;
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
index d21bcc7c1271..53ac6c2b7b7d 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -26,12 +26,12 @@
leds {
compatible = "gpio-leds";
- red {
+ led-red {
label = "Front Panel LED";
gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- green {
+ led-green {
gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
diff --git a/arch/arm/boot/dts/stih418-b2264.dts b/arch/arm/boot/dts/stih418-b2264.dts
index a99604bebf8c..fc32a03073b6 100644
--- a/arch/arm/boot/dts/stih418-b2264.dts
+++ b/arch/arm/boot/dts/stih418-b2264.dts
@@ -42,7 +42,7 @@
};
};
- cpu_opp_table: opp_table {
+ cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
@@ -76,7 +76,7 @@
soc {
leds {
compatible = "gpio-leds";
- green {
+ led-green {
gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 4c72dedcd1be..8d9a2dfa76f1 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -9,12 +9,12 @@
/ {
leds {
compatible = "gpio-leds";
- red {
+ led-red {
label = "Front Panel LED";
gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- green {
+ led-green {
gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
@@ -175,11 +175,11 @@
/* tsin0 is TSA on NIMA */
tsin0: port {
- tsin-num = <0>;
+ tsin-num = <0>;
serial-not-parallel;
- i2c-bus = <&ssc2>;
- reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>;
- dvb-card = <STV0367_TDA18212_NIMA_1>;
+ i2c-bus = <&ssc2>;
+ reset-gpios = <&pio15 4 GPIO_ACTIVE_LOW>;
+ dvb-card = <STV0367_TDA18212_NIMA_1>;
};
};
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 0d98aca01736..576235ec3c51 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -50,6 +50,7 @@
#include "stm32f429-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
/ {
model = "STMicroelectronics STM32429i-EVAL board";
@@ -186,7 +187,7 @@
port {
dcmi_0: endpoint {
remote-endpoint = <&ov2640_0>;
- bus-type = <5>;
+ bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
@@ -251,10 +252,10 @@
&mac {
status = "okay";
- pinctrl-0 = <&ethernet_mii>;
- pinctrl-names = "default";
- phy-mode = "mii";
- phy-handle = <&phy1>;
+ pinctrl-0 = <&ethernet_mii>;
+ pinctrl-names = "default";
+ phy-mode = "mii";
+ phy-handle = <&phy1>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index 155d9ffacc83..3bb812d6399e 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -45,13 +45,12 @@
/ {
soc {
- pinctrl: pin-controller@40020000 {
+ pinctrl: pinctrl@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
@@ -448,6 +447,36 @@
slew-rate = <2>;
};
};
+
+ can1_pins_a: can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
+ bias-pull-up;
+ };
+ };
+
+ can2_pins_a: can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
+ bias-pull-up;
+ };
+ };
+
+ can2_pins_b: can2-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
+ bias-pull-up;
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index c31ceb821231..c9e05e3540d6 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -362,6 +362,35 @@
status = "disabled";
};
+ can1: can@40006400 {
+ compatible = "st,stm32f4-bxcan";
+ reg = <0x40006400 0x200>;
+ interrupts = <19>, <20>, <21>, <22>;
+ interrupt-names = "tx", "rx0", "rx1", "sce";
+ resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
+ st,can-primary;
+ st,gcan = <&gcan>;
+ status = "disabled";
+ };
+
+ gcan: gcan@40006600 {
+ compatible = "st,stm32f4-gcan", "syscon";
+ reg = <0x40006600 0x200>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
+ };
+
+ can2: can@40006800 {
+ compatible = "st,stm32f4-bxcan";
+ reg = <0x40006800 0x200>;
+ interrupts = <63>, <64>, <65>, <66>;
+ interrupt-names = "tx", "rx0", "rx1", "sce";
+ resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
+ st,gcan = <&gcan>;
+ status = "disabled";
+ };
+
dac: dac@40007400 {
compatible = "st,stm32f4-dac-core";
reg = <0x40007400 0x400>;
diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
index 1cf8a23c2644..c8e6c52fb248 100644
--- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
@@ -9,13 +9,12 @@
/ {
soc {
- pinctrl: pin-controller@40020000 {
+ pinctrl: pinctrl@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 6e42ca2dada2..f30796f7adf3 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -375,7 +375,6 @@
arm,primecell-periphid = <0x10153180>;
reg = <0x52007000 0x1000>;
interrupts = <49>;
- interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
@@ -389,7 +388,6 @@
arm,primecell-periphid = <0x10153180>;
reg = <0x48022400 0x400>;
interrupts = <124>;
- interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
@@ -583,14 +581,13 @@
status = "disabled";
};
- pinctrl: pin-controller@58020000 {
+ pinctrl: pinctrl@58020000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
- pins-are-numbered;
gpioa: gpio@58020000 {
gpio-controller;
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 59e01ce10318..2b452883a708 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -77,10 +77,10 @@
&mac {
status = "disabled";
- pinctrl-0 = <&ethernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
+ pinctrl-0 = <&ethernet_rmii>;
+ pinctrl-names = "default";
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index 38cc7faf6884..5c5d8059bdc7 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -115,10 +115,10 @@
&mac {
status = "disabled";
- pinctrl-0 = <&ethernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
+ pinctrl-0 = <&ethernet_rmii>;
+ pinctrl-names = "default";
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts
index 9bb73bb61901..f3e70d3b65ac 100644
--- a/arch/arm/boot/dts/stm32h750i-art-pi.dts
+++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts
@@ -126,10 +126,10 @@
&mac {
status = "disabled";
- pinctrl-0 = <&ethernet_rmii>;
- pinctrl-names = "default";
- phy-mode = "rmii";
- phy-handle = <&phy0>;
+ pinctrl-0 = <&ethernet_rmii>;
+ pinctrl-names = "default";
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
index d2472cd8f1d0..27e0c3826789 100644
--- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,114 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+ <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
+ };
+ };
+
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_a: i2c1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c5_pins_a: i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_a: i2c5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
+ };
+ };
+
+ mcp23017_pins_a: mcp23017-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, GPIO)>;
+ bias-pull-up;
+ };
+ };
+
+ pwm3_pins_a: pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
+ };
+ };
+
+ pwm4_pins_a: pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
+ };
+ };
+
+ pwm8_pins_a: pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
+ };
+ };
+
+ pwm14_pins_a: pwm14-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm14_sleep_pins_a: pwm14-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -108,6 +216,36 @@
};
};
+ spi5_pins_a: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
+ <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ spi5_sleep_pins_a: spi5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
+ <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
+ <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
+ };
+ };
+
+ stm32g0_intn_pins_a: stm32g0-intn-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, GPIO)>;
+ bias-pull-up;
+ };
+ };
+
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
@@ -120,4 +258,133 @@
bias-disable;
};
};
+
+ uart4_idle_pins_a: uart4-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins_a: uart4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart8_pins_a: uart8-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_idle_pins_a: uart8-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart8_sleep_pins_a: uart8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
+ <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
+ };
+ };
+
+ usart1_pins_a: usart1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
+ <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_a: usart1-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_a: usart1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
+ <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
+ };
+ };
+
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
};
diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index 1708c79b5254..d163c267e34c 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -4,6 +4,8 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp13-clks.h>
+#include <dt-bindings/reset/stm32mp13-resets.h>
/ {
#address-cells = <1>;
@@ -27,53 +29,28 @@
interrupt-parent = <&intc>;
};
- clocks {
- clk_axi: clk-axi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <266500000>;
- };
-
- clk_hse: clk-hse {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
-
- clk_hsi: clk-hsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
-
- clk_lsi: clk-lsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- };
-
- clk_pclk3: clk-pclk3 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <104438965>;
+ firmware {
+ optee {
+ method = "smc";
+ compatible = "linaro,optee-tz";
};
- clk_pclk4: clk-pclk4 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <133250000>;
- };
+ scmi: scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+ shmem = <&scmi_shm>;
- clk_pll4_p: clk-pll4_p {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
- clk_pll4_r: clk-pll4_r {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <99000000>;
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
};
};
@@ -100,6 +77,28 @@
always-on;
};
+ /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
+ reg11: reg11 {
+ compatible = "regulator-fixed";
+ regulator-name = "reg11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ reg18: reg18 {
+ compatible = "regulator-fixed";
+ regulator-name = "reg18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ usb33: usb33 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -107,14 +106,610 @@
interrupt-parent = <&intc>;
ranges;
+ scmi_sram: sram@2ffff000 {
+ compatible = "mmio-sram";
+ reg = <0x2ffff000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2ffff000 0x1000>;
+
+ scmi_shm: scmi-sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0 0x80>;
+ };
+ };
+
+ timers2: timer@40000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40000000 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM2_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 18 0x400 0x1>,
+ <&dmamux1 19 0x400 0x1>,
+ <&dmamux1 20 0x400 0x1>,
+ <&dmamux1 21 0x400 0x1>,
+ <&dmamux1 22 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@1 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers3: timer@40001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40001000 0x400>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM3_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 23 0x400 0x1>,
+ <&dmamux1 24 0x400 0x1>,
+ <&dmamux1 25 0x400 0x1>,
+ <&dmamux1 26 0x400 0x1>,
+ <&dmamux1 27 0x400 0x1>,
+ <&dmamux1 28 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@2 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers4: timer@40002000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40002000 0x400>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM4_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 29 0x400 0x1>,
+ <&dmamux1 30 0x400 0x1>,
+ <&dmamux1 31 0x400 0x1>,
+ <&dmamux1 32 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@3 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers5: timer@40003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40003000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM5_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 55 0x400 0x1>,
+ <&dmamux1 56 0x400 0x1>,
+ <&dmamux1 57 0x400 0x1>,
+ <&dmamux1 58 0x400 0x1>,
+ <&dmamux1 59 0x400 0x1>,
+ <&dmamux1 60 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@4 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers6: timer@40004000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40004000 0x400>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM6_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 69 0x400 0x1>;
+ dma-names = "up";
+ status = "disabled";
+
+ timer@5 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <5>;
+ status = "disabled";
+ };
+ };
+
+ timers7: timer@40005000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40005000 0x400>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM7_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 70 0x400 0x1>;
+ dma-names = "up";
+ status = "disabled";
+
+ timer@6 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <6>;
+ status = "disabled";
+ };
+ };
+
+ lptimer1: timer@40009000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x40009000 0x400>;
+ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM1_K>;
+ clock-names = "mux";
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ i2s2: audio-controller@4000b000 {
+ compatible = "st,stm32h7-i2s";
+ reg = <0x4000b000 0x400>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi2: spi@4000b000 {
+ compatible = "st,stm32h7-spi";
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI2_K>;
+ resets = <&rcc SPI2_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s3: audio-controller@4000c000 {
+ compatible = "st,stm32h7-i2s";
+ reg = <0x4000c000 0x400>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi3: spi@4000c000 {
+ compatible = "st,stm32h7-spi";
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI3_K>;
+ resets = <&rcc SPI3_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spdifrx: audio-controller@4000d000 {
+ compatible = "st,stm32h7-spdifrx";
+ reg = <0x4000d000 0x400>;
+ #sound-dai-cells = <0>;
+ clocks = <&rcc SPDIF_K>;
+ clock-names = "kclk";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 93 0x400 0x01>,
+ <&dmamux1 94 0x400 0x01>;
+ dma-names = "rx", "rx-ctrl";
+ status = "disabled";
+ };
+
+ usart3: serial@4000f000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4000f000 0x400>;
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART3_K>;
+ resets = <&rcc USART3_R>;
+ wakeup-source;
+ dmas = <&dmamux1 45 0x400 0x5>,
+ <&dmamux1 46 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_hsi>;
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART4_K>;
+ resets = <&rcc UART4_R>;
+ wakeup-source;
+ dmas = <&dmamux1 63 0x400 0x5>,
+ <&dmamux1 64 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@40011000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40011000 0x400>;
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART5_K>;
+ resets = <&rcc UART5_R>;
+ wakeup-source;
+ dmas = <&dmamux1 65 0x400 0x5>,
+ <&dmamux1 66 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@40012000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x40012000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C1_K>;
+ resets = <&rcc I2C1_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 33 0x400 0x1>,
+ <&dmamux1 34 0x400 0x1>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
+ i2c-analog-filter;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40013000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x40013000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C2_K>;
+ resets = <&rcc I2C2_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 35 0x400 0x1>,
+ <&dmamux1 36 0x400 0x1>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ i2c-analog-filter;
+ status = "disabled";
+ };
+
+ uart7: serial@40018000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40018000 0x400>;
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART7_K>;
+ resets = <&rcc UART7_R>;
+ wakeup-source;
+ dmas = <&dmamux1 79 0x400 0x5>,
+ <&dmamux1 80 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart8: serial@40019000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40019000 0x400>;
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc UART8_K>;
+ resets = <&rcc UART8_R>;
+ wakeup-source;
+ dmas = <&dmamux1 81 0x400 0x5>,
+ <&dmamux1 82 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ timers1: timer@44000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x44000000 0x400>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "brk", "up", "trg-com", "cc";
+ clocks = <&rcc TIM1_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 11 0x400 0x1>,
+ <&dmamux1 12 0x400 0x1>,
+ <&dmamux1 13 0x400 0x1>,
+ <&dmamux1 14 0x400 0x1>,
+ <&dmamux1 15 0x400 0x1>,
+ <&dmamux1 16 0x400 0x1>,
+ <&dmamux1 17 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@0 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ timers8: timer@44001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x44001000 0x400>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "brk", "up", "trg-com", "cc";
+ clocks = <&rcc TIM8_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 47 0x400 0x1>,
+ <&dmamux1 48 0x400 0x1>,
+ <&dmamux1 49 0x400 0x1>,
+ <&dmamux1 50 0x400 0x1>,
+ <&dmamux1 51 0x400 0x1>,
+ <&dmamux1 52 0x400 0x1>,
+ <&dmamux1 53 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@7 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <7>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
+ };
+
+ usart6: serial@44003000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x44003000 0x400>;
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART6_K>;
+ resets = <&rcc USART6_R>;
+ wakeup-source;
+ dmas = <&dmamux1 71 0x400 0x5>,
+ <&dmamux1 72 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: audio-controller@44004000 {
+ compatible = "st,stm32h7-i2s";
+ reg = <0x44004000 0x400>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ spi1: spi@44004000 {
+ compatible = "st,stm32h7-spi";
+ reg = <0x44004000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI1_K>;
+ resets = <&rcc SPI1_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai1: sai@4400a000 {
+ compatible = "st,stm32h7-sai";
+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+ ranges = <0 0x4400a000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI1_R>;
+ status = "disabled";
+
+ sai1a: audio-controller@4400a004 {
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x20>;
+ #sound-dai-cells = <0>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 87 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai1b: audio-controller@4400a024 {
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x20>;
+ #sound-dai-cells = <0>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 88 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ sai2: sai@4400b000 {
+ compatible = "st,stm32h7-sai";
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+ ranges = <0 0x4400b000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI2_R>;
+ status = "disabled";
+
+ sai2a: audio-controller@4400b004 {
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x20>;
+ #sound-dai-cells = <0>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 89 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai2b: audio-controller@4400b024 {
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x20>;
+ #sound-dai-cells = <0>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 90 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ dfsdm: dfsdm@4400d000 {
+ compatible = "st,stm32mp1-dfsdm";
+ reg = <0x4400d000 0x800>;
+ clocks = <&rcc DFSDM_K>;
+ clock-names = "dfsdm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dfsdm0: filter@0 {
+ compatible = "st,stm32-dfsdm-adc";
+ reg = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 101 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ dfsdm1: filter@1 {
+ compatible = "st,stm32-dfsdm-adc";
+ reg = <1>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 102 0x400 0x01>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+ };
+
dma1: dma-controller@48000000 {
compatible = "st,stm32-dma";
reg = <0x48000000 0x400>;
@@ -126,7 +721,8 @@
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc DMA1>;
+ resets = <&rcc DMA1_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@@ -143,7 +739,8 @@
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc DMA2>;
+ resets = <&rcc DMA2_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@@ -152,13 +749,361 @@
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
reg = <0x48002000 0x40>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc DMAMUX1>;
+ resets = <&rcc DMAMUX1_R>;
#dma-cells = <3>;
dma-masters = <&dma1 &dma2>;
dma-requests = <128>;
dma-channels = <16>;
};
+ adc_2: adc@48004000 {
+ compatible = "st,stm32mp13-adc-core";
+ reg = <0x48004000 0x400>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+ clock-names = "bus", "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc2: adc@0 {
+ compatible = "st,stm32mp13-adc";
+ #io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_2>;
+ interrupts = <0>;
+ dmas = <&dmamux1 10 0x400 0x80000001>;
+ dma-names = "rx";
+ status = "disabled";
+
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ };
+ channel@16 {
+ reg = <16>;
+ label = "vddcpu";
+ };
+ channel@17 {
+ reg = <17>;
+ label = "vddq_ddr";
+ };
+ };
+ };
+
+ usbotg_hs: usb@49000000 {
+ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+ reg = <0x49000000 0x40000>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ resets = <&rcc USBO_R>;
+ reset-names = "dwc2";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+ dr_mode = "otg";
+ otg-rev = <0x200>;
+ usb33d-supply = <&usb33>;
+ status = "disabled";
+ };
+
+ usart1: serial@4c000000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c000000 0x400>;
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART1_K>;
+ resets = <&rcc USART1_R>;
+ wakeup-source;
+ dmas = <&dmamux1 41 0x400 0x5>,
+ <&dmamux1 42 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ usart2: serial@4c001000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c001000 0x400>;
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART2_K>;
+ resets = <&rcc USART2_R>;
+ wakeup-source;
+ dmas = <&dmamux1 43 0x400 0x5>,
+ <&dmamux1 44 0x400 0x1>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s4: audio-controller@4c002000 {
+ compatible = "st,stm32h7-i2s";
+ reg = <0x4c002000 0x400>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi4: spi@4c002000 {
+ compatible = "st,stm32h7-spi";
+ reg = <0x4c002000 0x400>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI4_K>;
+ resets = <&rcc SPI4_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi5: spi@4c003000 {
+ compatible = "st,stm32h7-spi";
+ reg = <0x4c003000 0x400>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SPI5_K>;
+ resets = <&rcc SPI5_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 85 0x400 0x01>,
+ <&dmamux1 86 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c3: i2c@4c004000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c004000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C3_K>;
+ resets = <&rcc I2C3_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 73 0x400 0x1>,
+ <&dmamux1 74 0x400 0x1>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
+ i2c-analog-filter;
+ status = "disabled";
+ };
+
+ i2c4: i2c@4c005000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c005000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C4_K>;
+ resets = <&rcc I2C4_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 75 0x400 0x1>,
+ <&dmamux1 76 0x400 0x1>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
+ i2c-analog-filter;
+ status = "disabled";
+ };
+
+ i2c5: i2c@4c006000 {
+ compatible = "st,stm32mp13-i2c";
+ reg = <0x4c006000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C5_K>;
+ resets = <&rcc I2C5_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dmamux1 115 0x400 0x1>,
+ <&dmamux1 116 0x400 0x1>;
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
+ i2c-analog-filter;
+ status = "disabled";
+ };
+
+ timers12: timer@4c007000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c007000 0x400>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@11 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <11>;
+ status = "disabled";
+ };
+ };
+
+ timers13: timer@4c008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c008000 0x400>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM13_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@12 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <12>;
+ status = "disabled";
+ };
+ };
+
+ timers14: timer@4c009000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c009000 0x400>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM14_K>;
+ clock-names = "int";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@13 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <13>;
+ status = "disabled";
+ };
+ };
+
+ timers15: timer@4c00a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00a000 0x400>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM15_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 105 0x400 0x1>,
+ <&dmamux1 106 0x400 0x1>,
+ <&dmamux1 107 0x400 0x1>,
+ <&dmamux1 108 0x400 0x1>;
+ dma-names = "ch1", "up", "trig", "com";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@14 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <14>;
+ status = "disabled";
+ };
+ };
+
+ timers16: timer@4c00b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00b000 0x400>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM16_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 109 0x400 0x1>,
+ <&dmamux1 110 0x400 0x1>;
+ dma-names = "ch1", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@15 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <15>;
+ status = "disabled";
+ };
+ };
+
+ timers17: timer@4c00c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x4c00c000 0x400>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
+ clocks = <&rcc TIM17_K>;
+ clock-names = "int";
+ dmas = <&dmamux1 111 0x400 0x1>,
+ <&dmamux1 112 0x400 0x1>;
+ dma-names = "ch1", "up";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@16 {
+ compatible = "st,stm32h7-timer-trigger";
+ reg = <16>;
+ status = "disabled";
+ };
+ };
+
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp13-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
@@ -169,27 +1114,180 @@
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
- clocks = <&clk_pclk3>;
+ clocks = <&rcc SYSCFG>;
+ };
+
+ lptimer2: timer@50021000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x50021000 0x400>;
+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM2_K>;
+ clock-names = "mux";
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@1 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer3: timer@50022000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x50022000 0x400>;
+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM3_K>;
+ clock-names = "mux";
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@2 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer4: timer@50023000 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x50023000 0x400>;
+ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM4_K>;
+ clock-names = "mux";
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
+ };
+
+ lptimer5: timer@50024000 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x50024000 0x400>;
+ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc LPTIM5_K>;
+ clock-names = "mux";
+ wakeup-source;
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32-lptimer-timer";
+ status = "disabled";
+ };
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc MDMA>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
};
+ fmc: memory-controller@58002000 {
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
+ status = "disabled";
+
+ nand-controller@4,0 {
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
+ <&mdma 24 0x2 0x12000a08 0x0 0x0>,
+ <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
+ };
+
+ qspi: spi@58003000 {
+ compatible = "st,stm32f469-qspi";
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
+ <&mdma 26 0x2 0x10100008 0x0 0x0>;
+ dma-names = "tx", "rx";
+ clocks = <&rcc QSPI_K>;
+ resets = <&rcc QSPI_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&clk_pll4_p>;
+ clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
+ resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
@@ -201,31 +1299,84 @@
arm,primecell-periphid = <0x20253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&clk_pll4_p>;
+ clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
status = "disabled";
};
+ usbh_ohci: usb@5800c000 {
+ compatible = "generic-ohci";
+ reg = <0x5800c000 0x1000>;
+ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usbh_ehci: usb@5800d000 {
+ compatible = "generic-ehci";
+ reg = <0x5800d000 0x1000>;
+ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ companion = <&usbh_ohci>;
+ status = "disabled";
+ };
+
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
- clocks = <&clk_pclk4>, <&clk_lsi>;
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
+ usbphyc: usbphyc@5a006000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc USBPHY_K>;
+ resets = <&rcc USBPHY_R>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>;
+ status = "disabled";
+
+ usbphyc_port0: usb-phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+ };
+
+ usbphyc_port1: usb-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ };
+ };
+
+ rtc: rtc@5c004000 {
+ compatible = "st,stm32mp1-rtc";
+ reg = <0x5c004000 0x400>;
+ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>,
+ <&scmi_clk CK_SCMI_RTC>;
+ clock-names = "pclk", "rtc_ck";
+ status = "disabled";
+ };
+
bsec: efuse@5c005000 {
- compatible = "st,stm32mp15-bsec";
+ compatible = "st,stm32mp13-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
part_number_otp: part_number_otp@4 {
reg = <0x4 0x2>;
+ bits = <0 12>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
@@ -239,12 +1390,13 @@
* Break node order to solve dependency probe issue between
* pinctrl and exti.
*/
- pinctrl: pin-controller@50002000 {
+ pinctrl: pinctrl@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp135-pinctrl";
ranges = <0 0x50002000 0x8400>;
- pins-are-numbered;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&exti 0x60 0xff>;
gpioa: gpio@50002000 {
gpio-controller;
@@ -252,7 +1404,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
@@ -264,7 +1416,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
@@ -276,7 +1428,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
@@ -288,7 +1440,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
@@ -300,7 +1452,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
@@ -312,7 +1464,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
@@ -324,7 +1476,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
@@ -336,7 +1488,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
ngpios = <15>;
gpio-ranges = <&pinctrl 0 112 15>;
@@ -348,7 +1500,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
- clocks = <&clk_pclk4>;
+ clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 128 8>;
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
index 0fb1386257cf..df451c3c2a26 100644
--- a/arch/arm/boot/dts/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -15,7 +15,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&clk_hse>, <&clk_pll4_r>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@@ -28,10 +28,41 @@
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
- clocks = <&clk_hse>, <&clk_pll4_r>;
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
+
+ adc_1: adc@48003000 {
+ compatible = "st,stm32mp13-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+ clock-names = "bus", "adc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32mp13-adc";
+ #io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_1>;
+ interrupts = <0>;
+ dmas = <&dmamux1 9 0x400 0x80000001>;
+ dma-names = "rx";
+ status = "disabled";
+
+ channel@18 {
+ reg = <18>;
+ label = "vrefint";
+ };
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts
index ee100d108ea2..f0900ca672b5 100644
--- a/arch/arm/boot/dts/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/stm32mp135f-dk.dts
@@ -6,6 +6,9 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-pinctrl.dtsi"
@@ -16,6 +19,13 @@
aliases {
serial0 = &uart4;
+ serial1 = &usart1;
+ serial2 = &uart8;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
};
memory@c0000000 {
@@ -23,6 +33,55 @@
reg = <0xc0000000 0x20000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ optee@dd000000 {
+ reg = <0xdd000000 0x3000000>;
+ no-map;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user {
+ label = "User-PA13";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ v3v3_sw: v3v3-sw {
+ compatible = "regulator-fixed";
+ regulator-name = "v3v3_sw";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_adc: vdd-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
vdd_sd: vdd-sd {
compatible = "regulator-fixed";
regulator-name = "vdd_sd";
@@ -30,6 +89,101 @@
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
+
+ vdd_usb: vdd-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&adc_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc1_usb_cc_pins_a>;
+ vdda-supply = <&vdd_adc>;
+ vref-supply = <&vdd_adc>;
+ status = "okay";
+ adc1: adc@0 {
+ status = "okay";
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+ * Use arbitrary margin here (e.g. 5us).
+ */
+ channel@6 {
+ reg = <6>;
+ st,min-sample-time-ns = <5000>;
+ };
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <1000000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ mcp23017: pinctrl@21 {
+ compatible = "microchip,mcp23017";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpiog>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcp23017_pins_a>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ microchip,irq-mirror;
+ };
+
+ typec@53 {
+ compatible = "st,stm32g0-typec";
+ reg = <0x53>;
+ /* Alert pin on PI2 */
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioi>;
+ /* Internal pull-up on PI2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&stm32g0_intn_pins_a>;
+ firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ con_usb_c_g0_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <170>;
+ i2c-scl-falling-time-ns = <5>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
};
&iwdg2 {
@@ -37,12 +191,16 @@
status = "okay";
};
+&rtc {
+ status = "okay";
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
+ cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
@@ -50,8 +208,163 @@
status = "okay";
};
+&spi5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi5_pins_a>;
+ pinctrl-1 = <&spi5_sleep_pins_a>;
+ status = "disabled";
+};
+
+&timers3 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm3_pins_a>;
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&timers4 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm4_pins_a>;
+ pinctrl-1 = <&pwm4_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@3 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers14 {
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm14_pins_a>;
+ pinctrl-1 = <&pwm14_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@13 {
+ status = "okay";
+ };
+};
+
&uart4 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "okay";
};
+
+&uart8 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart8_pins_a>;
+ pinctrl-1 = <&uart8_sleep_pins_a>;
+ pinctrl-2 = <&uart8_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
+&usart1 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-1 = <&usart1_sleep_pins_a>;
+ pinctrl-2 = <&usart1_idle_pins_a>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_sleep_pins_a>;
+ pinctrl-2 = <&usart2_idle_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* onboard HUB */
+ hub@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ vdd-supply = <&v3v3_sw>;
+ };
+};
+
+&usbotg_hs {
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb-role-switch;
+ status = "okay";
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usb_c_g0_ep>;
+ };
+ };
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+};
diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
index fa6889e30591..4d00e7592882 100644
--- a/arch/arm/boot/dts/stm32mp13xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -10,7 +10,8 @@
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_axi>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
index fa6889e30591..4d00e7592882 100644
--- a/arch/arm/boot/dts/stm32mp13xf.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -10,7 +10,8 @@
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_axi>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index f0d66d8c6e3b..e86d989dd351 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -151,6 +151,43 @@
};
};
+ dcmi_pins_c: dcmi-2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */
+ bias-pull-up;
+ };
+ };
+
+ dcmi_sleep_pins_c: dcmi-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@@ -379,6 +416,40 @@
};
};
+ ethernet0_rmii_pins_c: rmii-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
+ };
+ };
+
fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -889,6 +960,36 @@
};
};
+ mco1_pins_a: mco1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ mco1_sleep_pins_a: mco1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
+ };
+ };
+
+ mco2_pins_a: mco2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ mco2_sleep_pins_a: mco2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
+ };
+ };
+
m_can1_pins_a: m-can1-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
@@ -929,6 +1030,26 @@
};
};
+ m_can1_pins_c: m-can1-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_c: m_can1-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
@@ -1140,7 +1261,7 @@
};
qspi_bk1_pins_a: qspi-bk1-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
@@ -1149,12 +1270,6 @@
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
};
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
@@ -1162,13 +1277,12 @@
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
- <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
};
};
qspi_bk2_pins_a: qspi-bk2-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
@@ -1177,7 +1291,34 @@
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
+ };
+
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ qspi_cs2_pins_a: qspi-cs2-0 {
+ pins {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
@@ -1185,13 +1326,9 @@
};
};
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
- <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
};
};
@@ -1743,17 +1880,47 @@
};
};
+ spi1_pins_b: spi1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+
spi2_pins_a: spi2-0 {
pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
+ pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
+ <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
- pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
+ pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
+ bias-disable;
+ };
+ };
+
+ spi2_pins_b: spi2-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
+ <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
bias-disable;
};
};
@@ -1835,6 +2002,49 @@
};
};
+ uart4_pins_d: uart4-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_idle_pins_d: uart4-idle-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins_d: uart4-sleep-3 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart5_pins_a: uart5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */
+ bias-disable;
+ };
+ };
+
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
@@ -1968,7 +2178,7 @@
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -1986,7 +2196,7 @@
pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
@@ -2134,6 +2344,47 @@
};
};
+ usart3_pins_e: usart3-4 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
+ <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
+ bias-pull-up;
+ };
+ };
+
+ usart3_idle_pins_e: usart3-idle-4 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart3_sleep_pins_e: usart3-sleep-4 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
+ <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */
+ };
+ };
+
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
new file mode 100644
index 000000000000..543f24c2f4f6
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+ firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi: scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+ shmem = <&scmi_shm>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+
+ scmi_voltd: protocol@17 {
+ reg = <0x17>;
+
+ scmi_reguls: regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_reg11: reg11@0 {
+ reg = <0>;
+ regulator-name = "reg11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ scmi_reg18: reg18@1 {
+ voltd-name = "reg18";
+ reg = <1>;
+ regulator-name = "reg18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ scmi_usb33: usb33@2 {
+ reg = <2>;
+ regulator-name = "usb33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+ };
+ };
+
+ soc {
+ scmi_sram: sram@2ffff000 {
+ compatible = "mmio-sram";
+ reg = <0x2ffff000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2ffff000 0x1000>;
+
+ scmi_shm: scmi-sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0 0x80>;
+ };
+ };
+ };
+};
+
+&reg11 {
+ status = "disabled";
+};
+
+&reg18 {
+ status = "disabled";
+};
+
+&usb33 {
+ status = "disabled";
+};
+
+&usbotg_hs {
+ usb33d-supply = <&scmi_usb33>;
+};
+
+&usbphyc {
+ vdda1v1-supply = <&scmi_reg11>;
+ vdda1v8-supply = <&scmi_reg18>;
+};
+
+/delete-node/ &clk_hse;
+/delete-node/ &clk_hsi;
+/delete-node/ &clk_lse;
+/delete-node/ &clk_lsi;
+/delete-node/ &clk_csi;
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index f9aa9af31efd..63f4c78fcc1d 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -127,6 +127,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM2_K>;
clock-names = "int";
dmas = <&dmamux1 18 0x400 0x1>,
@@ -160,6 +162,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM3_K>;
clock-names = "int";
dmas = <&dmamux1 23 0x400 0x1>,
@@ -194,6 +198,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM4_K>;
clock-names = "int";
dmas = <&dmamux1 29 0x400 0x1>,
@@ -226,6 +232,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40003000 0x400>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM5_K>;
clock-names = "int";
dmas = <&dmamux1 55 0x400 0x1>,
@@ -260,6 +268,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40004000 0x400>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM6_K>;
clock-names = "int";
dmas = <&dmamux1 69 0x400 0x1>;
@@ -278,6 +288,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40005000 0x400>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM7_K>;
clock-names = "int";
dmas = <&dmamux1 70 0x400 0x1>;
@@ -296,6 +308,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40006000 0x400>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM12_K>;
clock-names = "int";
status = "disabled";
@@ -318,6 +332,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40007000 0x400>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM13_K>;
clock-names = "int";
status = "disabled";
@@ -340,6 +356,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40008000 0x400>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM14_K>;
clock-names = "int";
status = "disabled";
@@ -565,7 +583,7 @@
compatible = "st,stm32-cec";
reg = <0x40016000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CEC_K>, <&clk_lse>;
+ clocks = <&rcc CEC_K>, <&rcc CEC>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
@@ -623,6 +641,11 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44000000 0x400>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "brk", "up", "trg-com", "cc";
clocks = <&rcc TIM1_K>;
clock-names = "int";
dmas = <&dmamux1 11 0x400 0x1>,
@@ -659,6 +682,11 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44001000 0x400>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "brk", "up", "trg-com", "cc";
clocks = <&rcc TIM8_K>;
clock-names = "int";
dmas = <&dmamux1 47 0x400 0x1>,
@@ -746,6 +774,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44006000 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM15_K>;
clock-names = "int";
dmas = <&dmamux1 105 0x400 0x1>,
@@ -773,6 +803,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44007000 0x400>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM16_K>;
clock-names = "int";
dmas = <&dmamux1 109 0x400 0x1>,
@@ -797,6 +829,8 @@
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x44008000 0x400>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global";
clocks = <&rcc TIM17_K>;
clock-names = "int";
dmas = <&dmamux1 111 0x400 0x1>,
@@ -1084,7 +1118,6 @@
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC3_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC3_R>;
@@ -1097,8 +1130,8 @@
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
- clocks = <&rcc USBO_K>;
- clock-names = "otg";
+ clocks = <&rcc USBO_K>, <&usbphyc>;
+ clock-names = "otg", "utmi";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -1117,10 +1150,9 @@
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended =
- <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <&exti 61 1>;
- interrupt-names = "rx", "tx", "wakeup";
+ <&exti 61 1>,
+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
clocks = <&rcc IPCC>;
wakeup-source;
status = "disabled";
@@ -1406,7 +1438,6 @@
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
@@ -1421,7 +1452,6 @@
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
@@ -1474,7 +1504,7 @@
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
- clocks = <&rcc USBH>, <&usbphyc>;
+ clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1483,7 +1513,7 @@
usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
- clocks = <&rcc USBH>;
+ clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
@@ -1623,14 +1653,13 @@
* Break node order to solve dependency probe issue between
* pinctrl and exti.
*/
- pinctrl: pin-controller@50002000 {
+ pinctrl: pinctrl@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-pinctrl";
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
- pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
@@ -1754,12 +1783,11 @@
};
};
- pinctrl_z: pin-controller-z@54004000 {
+ pinctrl_z: pinctrl@54004000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
ranges = <0 0x54004000 0x400>;
- pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
diff --git a/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts b/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts
new file mode 100644
index 000000000000..e0f828ecc2fa
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+/dts-v1/;
+
+#include "stm32mp151.dtsi"
+#include "stm32mp15xx-dhcor-som.dtsi"
+#include "stm32mp15xx-dhcor-testbench.dtsi"
+
+/ {
+ model = "DH electronics STM32MP151A DHCOR Testbench";
+ compatible = "dh,stm32mp151a-dhcor-testbench",
+ "dh,stm32mp151a-dhcor-som",
+ "st,stm32mp151";
+};
diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts
new file mode 100644
index 000000000000..75874eafde11
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) Protonic Holland
+ * Author: David Jander <david@protonic.nl>
+ */
+/dts-v1/;
+
+#include "stm32mp151a-prtt1l.dtsi"
+
+/ {
+ model = "Protonic PRTT1A";
+ compatible = "prt,prtt1a", "st,stm32mp151";
+};
+
+&ethernet0 {
+ phy-handle = <&phy0>;
+};
+
+&mdio0 {
+ /* TI DP83TD510E */
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <0>;
+ interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <35>;
+ };
+};
+
+&pwm5_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */
+ };
+};
+
+&pwm5_sleep_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* TIM5_CH1 */
+ };
+};
+
+&timers5 {
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm5_pins_a>;
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts
new file mode 100644
index 000000000000..7ecf31263abc
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) Protonic Holland
+ * Author: David Jander <david@protonic.nl>
+ */
+/dts-v1/;
+
+#include "stm32mp151a-prtt1l.dtsi"
+
+/ {
+ model = "Protonic PRTT1C";
+ compatible = "prt,prtt1c", "st,stm32mp151";
+
+ clock_ksz9031: clock-ksz9031 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ clock_sja1105: clock-sja1105 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
+ &gpioa 2 GPIO_ACTIVE_HIGH>;
+
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ethernet0 {
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+&gpioa {
+ gpio-line-names =
+ "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "",
+ "", "", "", "", "", "", "", "SPI1_nSS";
+};
+
+&gpiod {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "WFM_RESET", "", "", "", "", "", "", "";
+};
+
+&gpioe {
+ gpio-line-names =
+ "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "",
+ "", "", "", "", "WFM_nIRQ", "", "", "";
+};
+
+&gpiog {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "PHY3_nINT",
+ "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET",
+ "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", "";
+};
+
+&mdio0 {
+ /* All this DP83TD510E PHYs can't be probed before switch@0 is
+ * probed so we need to use compatible with PHYid
+ */
+ /* TI DP83TD510E */
+ t1l0_phy: ethernet-phy@6 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <6>;
+ interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <35>;
+ };
+
+ /* TI DP83TD510E */
+ t1l1_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <7>;
+ interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <35>;
+ };
+
+ /* TI DP83TD510E */
+ t1l2_phy: ethernet-phy@10 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <10>;
+ interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <35>;
+ };
+
+ /* Micrel KSZ9031 */
+ rj45_phy: ethernet-phy@2 {
+ reg = <2>;
+ interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <1000>;
+
+ clocks = <&clock_ksz9031>;
+ };
+};
+
+&qspi {
+ status = "disabled";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ no-1-8-v;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&reg_3v3>;
+ vqmmc-supply = <&reg_3v3>;
+ status = "okay";
+};
+
+&sdmmc2_b4_od_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ };
+};
+
+&sdmmc2_b4_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ };
+};
+
+&sdmmc2_b4_sleep_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+};
+
+&sdmmc2_d47_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ };
+};
+
+&sdmmc2_d47_sleep_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
+ };
+};
+
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_b>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
+ non-removable;
+ no-1-8-v;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3v3>;
+ vqmmc-supply = <&reg_3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ mmc@1 {
+ compatible = "prt,prtt1c-wfm200", "silabs,wf200";
+ reg = <1>;
+ };
+};
+
+&sdmmc3_b4_od_pins_b {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
+ };
+};
+
+&sdmmc3_b4_pins_b {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
+ };
+};
+
+&sdmmc3_b4_sleep_pins_b {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
+ <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
+ };
+};
+
+&spi1 {
+ pinctrl-0 = <&spi1_pins_b>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ switch@0 {
+ compatible = "nxp,sja1105q";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ spi-rx-delay-us = <1>;
+ spi-tx-delay-us = <1>;
+ spi-cpha;
+
+ reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
+
+ clocks = <&clock_sja1105>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "t1l0";
+ phy-mode = "rmii";
+ phy-handle = <&t1l0_phy>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "t1l1";
+ phy-mode = "rmii";
+ phy-handle = <&t1l1_phy>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "t1l2";
+ phy-mode = "rmii";
+ phy-handle = <&t1l2_phy>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "rj45";
+ phy-handle = <&rj45_phy>;
+ phy-mode = "rgmii-id";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "cpu";
+ ethernet = <&ethernet0>;
+ phy-mode = "rmii";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi
new file mode 100644
index 000000000000..dd23de85100c
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) Protonic Holland
+ * Author: David Jander <david@protonic.nl>
+ */
+/dts-v1/;
+
+#include "stm32mp151.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxad-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ ethernet0 = &ethernet0;
+ mdio-gpio0 = &mdio0;
+ serial0 = &uart4;
+ };
+
+ led-controller-0 {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+
+ /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce
+ * stmmac MDC clock without reducing system bus rate, we need to use
+ * gpio based MDIO bus.
+ */
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
+ &gpioa 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&dts {
+ status = "okay";
+};
+
+&ethernet0 {
+ pinctrl-0 = <&ethernet0_rmii_pins_a>;
+ pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&ethernet0_rmii_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK input */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
+ };
+};
+
+&ethernet0_rmii_sleep_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
+ };
+};
+
+&iwdg2 {
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <104000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&qspi_bk1_pins_a {
+ pins1 {
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3v3>;
+ vqmmc-supply = <&reg_3v3>;
+ status = "okay";
+};
+
+&sdmmc1_b4_od_pins_a {
+ pins1 {
+ bias-pull-up;
+ };
+ pins2 {
+ bias-pull-up;
+ };
+};
+
+&sdmmc1_b4_pins_a {
+ pins1 {
+ bias-pull-up;
+ };
+ pins2 {
+ bias-pull-up;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart4_idle_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+};
+
+&uart4_pins_a {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+};
+
+&uart4_sleep_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
+ };
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&reg_3v3>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&reg_3v3>;
+};
diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts
new file mode 100644
index 000000000000..ad25929e64e6
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) Protonic Holland
+ * Author: David Jander <david@protonic.nl>
+ */
+/dts-v1/;
+
+#include "stm32mp151a-prtt1l.dtsi"
+
+/ {
+ model = "Protonic PRTT1S";
+ compatible = "prt,prtt1s", "st,stm32mp151";
+};
+
+&ethernet0 {
+ phy-handle = <&phy0>;
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ clock-frequency = <100000>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ humidity-sensor@40 {
+ compatible = "ti,hdc1080";
+ reg = <0x40>;
+ };
+
+ co2-sensor@62 {
+ compatible = "sensirion,scd41";
+ reg = <0x62>;
+ };
+};
+
+&i2c1_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */
+ };
+};
+
+&i2c1_sleep_pins_a {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('D', 13, ANALOG)>; /* I2C1_SDA */
+ };
+};
+
+&mdio0 {
+ /* TI DP83TD510E */
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id2000.0181";
+ reg = <0>;
+ interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <35>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts
new file mode 100644
index 000000000000..c8b9818499ea
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ *
+ * DHCOR STM32MP1 variant:
+ * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG
+ * DHCOR PCB number: 586-100 or newer
+ * DRC Compact PCB number: 627-100 or newer
+ */
+
+/dts-v1/;
+
+#include "stm32mp153.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15xx-dhcor-som.dtsi"
+#include "stm32mp15xx-dhcor-drc-compact.dtsi"
+
+/ {
+ model = "DH electronics STM32MP153C DHCOR DRC Compact";
+ compatible = "dh,stm32mp153c-dhcor-drc-compact",
+ "dh,stm32mp153c-dhcor-som",
+ "st,stm32mp153";
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_c>;
+ pinctrl-1 = <&m_can1_sleep_pins_c>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts
index 2e3c9fbb4eb3..275167f26fd9 100644
--- a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts
@@ -13,7 +13,6 @@
/dts-v1/;
#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
#include "stm32mp15xx-dhcor-avenger96.dtsi"
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
new file mode 100644
index 000000000000..e539cc80bef8
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157a-dk1.dts"
+#include "stm32mp15-scmi.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
+ compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
+
+ reserved-memory {
+ optee@de000000 {
+ reg = <0xde000000 0x2000000>;
+ no-map;
+ };
+ };
+};
+
+&cpu0 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cpu1 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&dsi {
+ clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
+&gpioz {
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
+};
+
+&hash1 {
+ clocks = <&scmi_clk CK_SCMI_HASH1>;
+ resets = <&scmi_reset RST_SCMI_HASH1>;
+};
+
+&i2c4 {
+ clocks = <&scmi_clk CK_SCMI_I2C4>;
+ resets = <&scmi_reset RST_SCMI_I2C4>;
+};
+
+&iwdg2 {
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+};
+
+&mdma1 {
+ resets = <&scmi_reset RST_SCMI_MDMA>;
+};
+
+&mlahb {
+ resets = <&scmi_reset RST_SCMI_MCU>;
+};
+
+&rcc {
+ compatible = "st,stm32mp1-rcc-secure", "syscon";
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+};
+
+&rng1 {
+ clocks = <&scmi_clk CK_SCMI_RNG1>;
+ resets = <&scmi_reset RST_SCMI_RNG1>;
+};
+
+&rtc {
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 4c8be9c8eb20..0da3667ab1e0 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -17,9 +17,6 @@
aliases {
ethernet0 = &ethernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
};
chosen {
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
index 2a2829283456..9a2a4bc7d079 100644
--- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
@@ -2,7 +2,7 @@
/*
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
* Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
+ * Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
index 1f75f1d45181..60ce4425a7fd 100644
--- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
@@ -2,7 +2,7 @@
/*
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
* Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
+ * Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
index ba92d7d8ed00..390ee8c05754 100644
--- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
@@ -2,7 +2,7 @@
/*
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
* Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
+ * Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
index 01166ccacf2b..9de893101b40 100644
--- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
+++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi
@@ -2,7 +2,7 @@
/*
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
* Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
+ * Copyright (c) 2020 Amarula Solutions(India)
*/
/ {
diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
index fae656edd820..0d7560ba2950 100644
--- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -2,7 +2,7 @@
/*
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
* Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
+ * Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
index b9d0d3d6ad15..d949559be020 100644
--- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
@@ -2,7 +2,7 @@
/*
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
* Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
+ * Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
index 0b85175f151e..fb4600a59869 100644
--- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
+++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi
@@ -2,7 +2,7 @@
/*
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
* Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons(India)
+ * Copyright (c) 2020 Amarula Solutions(India)
*/
/ {
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
new file mode 100644
index 000000000000..97e4f94b0a24
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-dk2.dts"
+#include "stm32mp15-scmi.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
+ compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
+
+ reserved-memory {
+ optee@de000000 {
+ reg = <0xde000000 0x2000000>;
+ no-map;
+ };
+ };
+};
+
+&cpu0 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cpu1 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cryp1 {
+ clocks = <&scmi_clk CK_SCMI_CRYP1>;
+ resets = <&scmi_reset RST_SCMI_CRYP1>;
+};
+
+&dsi {
+ phy-dsi-supply = <&scmi_reg18>;
+ clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
+&gpioz {
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
+};
+
+&hash1 {
+ clocks = <&scmi_clk CK_SCMI_HASH1>;
+ resets = <&scmi_reset RST_SCMI_HASH1>;
+};
+
+&i2c4 {
+ clocks = <&scmi_clk CK_SCMI_I2C4>;
+ resets = <&scmi_reset RST_SCMI_I2C4>;
+};
+
+&iwdg2 {
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+};
+
+&mdma1 {
+ resets = <&scmi_reset RST_SCMI_MDMA>;
+};
+
+&mlahb {
+ resets = <&scmi_reset RST_SCMI_MCU>;
+};
+
+&rcc {
+ compatible = "st,stm32mp1-rcc-secure", "syscon";
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+};
+
+&rng1 {
+ clocks = <&scmi_clk CK_SCMI_RNG1>;
+ resets = <&scmi_reset RST_SCMI_RNG1>;
+};
+
+&rtc {
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index 2bc92ef3aeb9..ab13e340f4ef 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -18,9 +18,6 @@
aliases {
ethernet0 = &ethernet0;
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
serial3 = &usart2;
};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
new file mode 100644
index 000000000000..9cf0a44d2f47
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-ed1.dts"
+#include "stm32mp15-scmi.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
+ compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ reserved-memory {
+ optee@fe000000 {
+ reg = <0xfe000000 0x2000000>;
+ no-map;
+ };
+ };
+};
+
+&cpu0 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cpu1 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cryp1 {
+ clocks = <&scmi_clk CK_SCMI_CRYP1>;
+ resets = <&scmi_reset RST_SCMI_CRYP1>;
+};
+
+&dsi {
+ clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
+&gpioz {
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
+};
+
+&hash1 {
+ clocks = <&scmi_clk CK_SCMI_HASH1>;
+ resets = <&scmi_reset RST_SCMI_HASH1>;
+};
+
+&i2c4 {
+ clocks = <&scmi_clk CK_SCMI_I2C4>;
+ resets = <&scmi_reset RST_SCMI_I2C4>;
+};
+
+&iwdg2 {
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+};
+
+&mdma1 {
+ resets = <&scmi_reset RST_SCMI_MDMA>;
+};
+
+&mlahb {
+ resets = <&scmi_reset RST_SCMI_MCU>;
+};
+
+&rcc {
+ compatible = "st,stm32mp1-rcc-secure", "syscon";
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+};
+
+&rng1 {
+ clocks = <&scmi_clk CK_SCMI_RNG1>;
+ resets = <&scmi_reset RST_SCMI_RNG1>;
+};
+
+&rtc {
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index b1eb688a278a..8beb901be506 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -16,6 +16,10 @@
model = "STMicroelectronics STM32MP157C eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+ aliases {
+ serial0 = &uart4;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -65,15 +69,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
-
- gpu_reserved: gpu@e8000000 {
- reg = <0xe8000000 0x8000000>;
- no-map;
- };
- };
-
- aliases {
- serial0 = &uart4;
};
sd_switch: regulator-sd_switch {
@@ -140,10 +135,6 @@
status = "okay";
};
-&gpu {
- contiguous-area = <&gpu_reserved>;
-};
-
&hash1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
index 33ae5e0590df..b01470a9a3d5 100644
--- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
@@ -68,11 +68,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
-
- gpu_reserved: gpu@dc000000 {
- reg = <0xdc000000 0x4000000>;
- no-map;
- };
};
led: gpio_leds {
@@ -173,7 +168,7 @@
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
@@ -183,10 +178,6 @@
};
};
-&gpu {
- contiguous-area = <&gpu_reserved>;
-};
-
&hash1 {
status = "okay";
};
@@ -391,14 +382,18 @@
&qspi {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
- flash0: is25lp016d@0 {
+ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <133000000>;
@@ -435,12 +430,6 @@
pinctrl-0 = <&spi1_pins_a>;
cs-gpios = <&gpioz 3 0>;
status = "disabled";
-
- spidev@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <100000>;
- };
};
&timers1 {
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
new file mode 100644
index 000000000000..3b9dd6f4ccc9
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-ev1.dts"
+#include "stm32mp15-scmi.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
+ compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
+ "st,stm32mp157";
+
+ reserved-memory {
+ optee@fe000000 {
+ reg = <0xfe000000 0x2000000>;
+ no-map;
+ };
+ };
+};
+
+&cpu0 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cpu1 {
+ clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cryp1 {
+ clocks = <&scmi_clk CK_SCMI_CRYP1>;
+ resets = <&scmi_reset RST_SCMI_CRYP1>;
+};
+
+&dsi {
+ phy-dsi-supply = <&scmi_reg18>;
+ clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
+&gpioz {
+ clocks = <&scmi_clk CK_SCMI_GPIOZ>;
+};
+
+&hash1 {
+ clocks = <&scmi_clk CK_SCMI_HASH1>;
+ resets = <&scmi_reset RST_SCMI_HASH1>;
+};
+
+&i2c4 {
+ clocks = <&scmi_clk CK_SCMI_I2C4>;
+ resets = <&scmi_reset RST_SCMI_I2C4>;
+};
+
+&iwdg2 {
+ clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+};
+
+&m_can1 {
+ clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
+};
+
+&mdma1 {
+ resets = <&scmi_reset RST_SCMI_MDMA>;
+};
+
+&mlahb {
+ resets = <&scmi_reset RST_SCMI_MCU>;
+};
+
+&rcc {
+ compatible = "st,stm32mp1-rcc-secure", "syscon";
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_CSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+};
+
+&rng1 {
+ clocks = <&scmi_clk CK_SCMI_RNG1>;
+ resets = <&scmi_reset RST_SCMI_RNG1>;
+};
+
+&rtc {
+ clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index e222d2d2cb44..ba8e9d9a42fa 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -8,21 +8,21 @@
#include "stm32mp157c-ed1.dts"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/media/video-interfaces.h>
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
aliases {
- serial0 = &uart4;
serial1 = &usart3;
ethernet0 = &ethernet0;
};
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
@@ -90,7 +90,7 @@
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
- bus-type = <5>;
+ bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
@@ -144,7 +144,7 @@
max-speed = <1000>;
phy-handle = <&phy0>;
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
@@ -255,14 +255,22 @@
&qspi {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a
+ &qspi_bk2_pins_a
+ &qspi_cs2_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a
+ &qspi_bk2_sleep_pins_a
+ &qspi_cs2_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
- flash0: mx66l51235l@0 {
+ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
@@ -271,7 +279,7 @@
#size-cells = <1>;
};
- flash1: mx66l51235l@1 {
+ flash1: flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-rx-bus-width = <4>;
@@ -362,6 +370,14 @@
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* onboard HUB */
+ hub@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ vdd-supply = <&v3v3>;
+ };
};
&usbotg_hs {
@@ -385,6 +401,11 @@
st,tune-squelch-level = <3>;
st,tune-hs-rx-offset = <2>;
st,no-lsfs-sc;
+
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vbus_sw>;
+ };
};
&usbphyc_port1 {
diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
index e8d2ec41d537..407ed3952f75 100644
--- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
@@ -73,7 +73,7 @@
};
panel: panel {
- compatible = "edt,etm0700g0edh6", "simple-panel";
+ compatible = "edt,etm0700g0edh6";
backlight = <&backlight>;
enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_3v3>;
@@ -112,7 +112,7 @@
phy-handle = <&ethphy>;
status = "okay";
- mdio0 {
+ mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
index 2d9461006810..e22871dc580c 100644
--- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
@@ -62,11 +62,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
-
- gpu_reserved: gpu@d4000000 {
- reg = <0xd4000000 0x4000000>;
- no-map;
- };
};
led {
@@ -80,11 +75,6 @@
};
};
-&gpu {
- contiguous-area = <&gpu_reserved>;
- status = "okay";
-};
-
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
index ed66d25b8bf3..a8b3f7a54703 100644
--- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
@@ -41,7 +41,7 @@
assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
st,eth-clk-sel;
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
index 5f586f024060..4709677151aa 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
@@ -242,7 +242,7 @@
sai2a_port: port {
sai2a_endpoint: endpoint {
remote-endpoint = <&sgtl5000_tx_endpoint>;
- format = "i2s";
+ dai-format = "i2s";
mclk-fs = <512>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
@@ -260,7 +260,7 @@
sai2b_port: port {
sai2b_endpoint: endpoint {
remote-endpoint = <&sgtl5000_rx_endpoint>;
- format = "i2s";
+ dai-format = "i2s";
mclk-fs = <512>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
index 83e2c87713f8..c06edd2eacb0 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
@@ -118,15 +118,14 @@
&ethernet0 {
status = "okay";
- pinctrl-0 = <&ethernet0_rmii_pins_a>;
- pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
+ pinctrl-0 = <&ethernet0_rmii_pins_c &mco2_pins_a>;
+ pinctrl-1 = <&ethernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
- st,eth-ref-clk-sel;
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
@@ -136,7 +135,7 @@
/* LAN8710Ai */
compatible = "ethernet-phy-id0007.c0f0",
"ethernet-phy-ieee802.3-c22";
- clocks = <&rcc ETHCK_K>;
+ clocks = <&rcc CK_MCO2>;
reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
reset-assert-us = <500>;
reset-deassert-us = <500>;
@@ -429,8 +428,12 @@
&qspi {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -446,6 +449,21 @@
};
};
+&rcc {
+ /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
+ clocks = <&rcc CK_MCO2>;
+ clock-names = "ETH_RX_CLK/ETH_REF_CLK";
+
+ /*
+ * Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
+ * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
+ * so that MCO2 behaves as a divider for the ETHRX clock here.
+ */
+ assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
+ assigned-clock-parents = <&rcc PLL4_P>;
+ assigned-clock-rates = <50000000>, <100000000>;
+};
+
&rng1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
index 61e17f44ce81..50af4a27d6be 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
@@ -66,7 +66,6 @@
led4 {
label = "green:user3";
gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
default-state = "off";
panic-indicator;
};
@@ -100,7 +99,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpioz 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@@ -126,6 +125,22 @@
};
};
+&dcmi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmi_pins_c>;
+ pinctrl-1 = <&dcmi_sleep_pins_c>;
+ status = "disabled";
+
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <&stmipi_2>;
+ bus-type = <5>;
+ bus-width = <8>;
+ pclk-sample = <0>;
+ };
+ };
+};
+
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_c>;
@@ -135,12 +150,13 @@
max-speed = <1000>;
phy-handle = <&phy0>;
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
+ reset-post-delay-us = <1000>;
phy0: ethernet-phy@7 {
reg = <7>;
@@ -218,6 +234,45 @@
};
&i2c4 {
+ stmipi: stmipi@14 {
+ compatible = "st,st-mipid02";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mco1_pins_a>;
+ pinctrl-1 = <&mco1_sleep_pins_a>;
+ reg = <0x14>;
+ clocks = <&rcc CK_MCO1>;
+ clock-names = "xclk";
+ assigned-clocks = <&rcc CK_MCO1>;
+ assigned-clock-parents = <&rcc CK_HSE>;
+ assigned-clock-rates = <24000000>;
+ VDDE-supply = <&v1v8>;
+ VDDIN-supply = <&v1v8>;
+ reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ stmipi_0: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ stmipi_2: endpoint {
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ remote-endpoint = <&dcmi_0>;
+ };
+ };
+ };
+ };
+
hdmi-transmitter@3d {
compatible = "adi,adv7513";
reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
@@ -303,7 +358,7 @@
sai2a_port: port {
sai2a_endpoint: endpoint {
remote-endpoint = <&adv7513_i2s0>;
- format = "i2s";
+ dai-format = "i2s";
mclk-fs = <256>;
};
};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi
new file mode 100644
index 000000000000..c32c160f97f2
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+/ {
+ aliases {
+ ethernet0 = &ethernet0;
+ ethernet1 = &ksz8851;
+ mmc0 = &sdmmc1;
+ rtc0 = &hwrtc;
+ rtc1 = &rtc;
+ serial0 = &uart4;
+ serial1 = &uart8;
+ serial2 = &usart3;
+ serial3 = &uart5;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ led {
+ compatible = "gpio-leds";
+ led1 {
+ label = "yellow:user0";
+ gpios = <&gpioz 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "red:user1";
+ gpios = <&gpioz 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ ethernet_vio: vioregulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpioh 2 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd>;
+ };
+};
+
+&adc { /* X11 ADC inputs */
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc12_ain_pins_b>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "okay";
+
+ adc1: adc@0 {
+ st,adc-channels = <0 1 6>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+
+ adc2: adc@100 {
+ st,adc-channels = <0 1 2>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+};
+
+&ethernet0 {
+ status = "okay";
+ pinctrl-0 = <&ethernet0_rgmii_pins_c>;
+ pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+ reset-post-delay-us = <1000>;
+
+ phy0: ethernet-phy@7 {
+ reg = <7>;
+
+ rxc-skew-ps = <1500>;
+ rxdv-skew-ps = <540>;
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+
+ txc-skew-ps = <1440>;
+ txen-skew-ps = <540>;
+ txd0-skew-ps = <420>;
+ txd1-skew-ps = <420>;
+ txd2-skew-ps = <420>;
+ txd3-skew-ps = <420>;
+ };
+ };
+};
+
+&fmc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&fmc_pins_b>;
+ pinctrl-1 = <&fmc_sleep_pins_b>;
+ status = "okay";
+
+ ksz8851: ethernet@1,0 {
+ compatible = "micrel,ks8851-mll";
+ reg = <1 0x0 0x2>, <1 0x2 0x20000>;
+ interrupt-parent = <&gpioc>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ bank-width = <2>;
+
+ /* Timing values are in nS */
+ st,fmc2-ebi-cs-mux-enable;
+ st,fmc2-ebi-cs-transaction-type = <4>;
+ st,fmc2-ebi-cs-buswidth = <16>;
+ st,fmc2-ebi-cs-address-setup-ns = <5>;
+ st,fmc2-ebi-cs-address-hold-ns = <5>;
+ st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
+ st,fmc2-ebi-cs-data-setup-ns = <45>;
+ st,fmc2-ebi-cs-data-hold-ns = <1>;
+ st,fmc2-ebi-cs-write-address-setup-ns = <5>;
+ st,fmc2-ebi-cs-write-address-hold-ns = <5>;
+ st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
+ st,fmc2-ebi-cs-write-data-setup-ns = <45>;
+ st,fmc2-ebi-cs-write-data-hold-ns = <1>;
+ };
+};
+
+&gpioa {
+ gpio-line-names = "", "", "", "",
+ "DRCC-VAR2", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpioe {
+ gpio-line-names = "", "", "", "",
+ "", "DRCC-GPIO0", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpiog {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "DRCC-GPIO5", "", "", "";
+};
+
+&gpioh {
+ gpio-line-names = "", "", "", "DRCC-HW2",
+ "DRCC-GPIO4", "", "", "",
+ "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1",
+ "DRCC-VAR0", "", "", "DRCC-GPIO6";
+};
+
+&gpioi {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "DRCC-GPIO2",
+ "", "DRCC-GPIO1", "", "",
+ "", "", "", "";
+};
+
+&i2c1 { /* X11 I2C1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_b>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c4 {
+ hwrtc: rtc@32 {
+ compatible = "microcrystal,rv8803";
+ reg = <0x32>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&sdmmc1 { /* MicroSD */
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&vdd>;
+ vqmmc-supply = <&vdd>;
+ status = "okay";
+};
+
+&sdmmc2 { /* eMMC */
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
+ status = "okay";
+};
+
+&sdmmc3 { /* SDIO Wi-Fi */
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ bus-width = <4>;
+ mmc-ddr-3_3v;
+ st,neg-edge;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&spi2 { /* X11 SPI */
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_b>;
+ cs-gpios = <&gpioi 0 0>;
+ status = "disabled";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&uart4 {
+ label = "UART0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_d>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart5 { /* X11 UART */
+ label = "X11-UART5";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pins_a>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart8 {
+ label = "RS485-1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
+ uart-has-rtscts;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&usart3 { /* RS485 or RS232 */
+ label = "RS485-2";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usart3_pins_e>;
+ pinctrl-1 = <&usart3_sleep_pins_e>;
+ uart-has-rtscts;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbh_ohci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "otg";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phy-names = "usb2-phy";
+ phys = <&usbphyc_port1 0>;
+ vbus-supply = <&vbus_otg>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vbus_sw>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
index 75172314d7af..9937b28548c2 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
@@ -18,6 +18,11 @@
};
};
+&vdd {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+};
+
&pwr_regulators {
vdd-supply = <&vdd_io>;
};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
index 6336c3ca0f0e..bb40fb46da81 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
@@ -119,8 +119,8 @@
vdd: buck3 {
regulator-name = "vdd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
@@ -247,8 +247,12 @@
&qspi {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi
new file mode 100644
index 000000000000..5fdb74b652ac
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+/ {
+ aliases {
+ ethernet0 = &ethernet0;
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ serial0 = &uart4;
+ serial1 = &uart7;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sd_switch: regulator-sd_switch {
+ compatible = "regulator-gpio";
+ regulator-name = "sd_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+ regulator-always-on;
+
+ gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1>,
+ <2900000 0x0>;
+ };
+};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc12_ain_pins_b>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "okay";
+
+ adc1: adc@0 {
+ st,adc-channels = <0 1 6>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+
+ adc2: adc@100 {
+ st,adc-channels = <0 1 2>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+};
+
+&ethernet0 {
+ status = "okay";
+ pinctrl-0 = <&ethernet0_rgmii_pins_c>;
+ pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+ reset-post-delay-us = <1000>;
+
+ phy0: ethernet-phy@7 {
+ reg = <7>;
+
+ rxc-skew-ps = <1500>;
+ rxdv-skew-ps = <540>;
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+
+ txc-skew-ps = <1440>;
+ txen-skew-ps = <540>;
+ txd0-skew-ps = <420>;
+ txd1-skew-ps = <420>;
+ txd2-skew-ps = <420>;
+ txd3-skew-ps = <420>;
+ };
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
+ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ vqmmc-supply = <&sd_switch>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_b>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ uart-has-rtscts;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbh_ohci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phy-names = "usb2-phy";
+ phys = <&usbphyc_port1 0>;
+ status = "okay";
+ vbus-supply = <&vbus_otg>;
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
index 333c2af97130..cefeeb00fc22 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -8,6 +8,12 @@
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
+ aliases {
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -53,11 +59,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
-
- gpu_reserved: gpu@d4000000 {
- reg = <0xd4000000 0x4000000>;
- no-map;
- };
};
led {
@@ -72,7 +73,7 @@
sound {
compatible = "audio-graph-card";
- label = "STM32MP1-DK";
+ label = "STM32MP15-DK";
routing =
"Playback" , "MCLK",
"Capture" , "MCLK",
@@ -141,7 +142,7 @@
max-speed = <1000>;
phy-handle = <&phy0>;
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
@@ -151,10 +152,6 @@
};
};
-&gpu {
- contiguous-area = <&gpu_reserved>;
-};
-
&hash1 {
status = "okay";
};
@@ -501,14 +498,12 @@
sai2a: audio-controller@4400b004 {
#clock-cells = <0>;
dma-names = "tx";
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
status = "okay";
sai2a_port: port {
sai2a_endpoint: endpoint {
remote-endpoint = <&cs42l51_tx_endpoint>;
- format = "i2s";
+ dai-format = "i2s";
mclk-fs = <256>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
@@ -526,7 +521,7 @@
sai2b_port: port {
sai2b_endpoint: endpoint {
remote-endpoint = <&cs42l51_rx_endpoint>;
- format = "i2s";
+ dai-format = "i2s";
mclk-fs = <256>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
@@ -677,6 +672,14 @@
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* onboard HUB */
+ hub@1 {
+ compatible = "usb424,2514";
+ reg = <1>;
+ vdd-supply = <&v3v3>;
+ };
};
&usbotg_hs {
diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
index 6706d8311a66..a43965c86fe8 100644
--- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
@@ -50,12 +50,6 @@
no-map;
};
};
-
- reg_sip_eeprom: regulator_eeprom {
- compatible = "regulator-fixed";
- regulator-name = "sip_eeprom";
- regulator-always-on;
- };
};
&i2c4 {
@@ -78,6 +72,7 @@
compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
ldo6-supply = <&v3v3>;
pwr_sw1-supply = <&bst_out>;
@@ -203,7 +198,7 @@
sip_eeprom: eeprom@50 {
compatible = "atmel,24c32";
- vcc-supply = <&reg_sip_eeprom>;
+ vcc-supply = <&vdd>;
reg = <0x50>;
};
};
@@ -215,8 +210,8 @@
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
index 0a562b2cc5bc..62e7aa587f89 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
@@ -63,7 +63,7 @@
compatible = "gpio-keys-polled";
poll-interval = <20>;
- left-joystick-left {
+ event-left-joystick-left {
label = "Left Joystick Left";
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
@@ -71,7 +71,7 @@
gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
};
- left-joystick-right {
+ event-left-joystick-right {
label = "Left Joystick Right";
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
@@ -79,7 +79,7 @@
gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
};
- left-joystick-up {
+ event-left-joystick-up {
label = "Left Joystick Up";
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
@@ -87,7 +87,7 @@
gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
};
- left-joystick-down {
+ event-left-joystick-down {
label = "Left Joystick Down";
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
@@ -95,7 +95,7 @@
gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
};
- right-joystick-left {
+ event-right-joystick-left {
label = "Right Joystick Left";
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
@@ -103,7 +103,7 @@
gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
};
- right-joystick-right {
+ event-right-joystick-right {
label = "Right Joystick Right";
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
@@ -111,7 +111,7 @@
gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
};
- right-joystick-up {
+ event-right-joystick-up {
label = "Right Joystick Up";
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
@@ -119,7 +119,7 @@
gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
};
- right-joystick-down {
+ event-right-joystick-down {
label = "Right Joystick Down";
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
@@ -127,7 +127,7 @@
gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
};
- dpad-left {
+ event-dpad-left {
label = "DPad Left";
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
@@ -135,7 +135,7 @@
gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
};
- dpad-right {
+ event-dpad-right {
label = "DPad Right";
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
@@ -143,7 +143,7 @@
gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
};
- dpad-up {
+ event-dpad-up {
label = "DPad Up";
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
@@ -151,7 +151,7 @@
gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
};
- dpad-down {
+ event-dpad-down {
label = "DPad Down";
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
@@ -159,49 +159,49 @@
gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
};
- x {
+ event-x {
label = "Button X";
linux,code = <BTN_X>;
gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
};
- y {
+ event-y {
label = "Button Y";
linux,code = <BTN_Y>;
gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
};
- a {
+ event-a {
label = "Button A";
linux,code = <BTN_A>;
gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
};
- b {
+ event-b {
label = "Button B";
linux,code = <BTN_B>;
gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
};
- select {
+ event-select {
label = "Select Button";
linux,code = <BTN_SELECT>;
gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
};
- start {
+ event-start {
label = "Start Button";
linux,code = <BTN_START>;
gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
};
- top-left {
+ event-top-left {
label = "Top Left Button";
linux,code = <BTN_TL>;
gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
};
- top-right {
+ event-top-right {
label = "Top Right Button";
linux,code = <BTN_TR>;
gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 1ac82376baef..a332d61fd561 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -77,19 +77,19 @@
gpio-keys {
compatible = "gpio-keys";
- back {
+ key-back {
label = "Key Back";
linux,code = <KEY_BACK>;
gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
};
- home {
+ key-home {
label = "Key Home";
linux,code = <KEY_HOME>;
gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
};
- menu {
+ key-menu {
label = "Key Menu";
linux,code = <KEY_MENU>;
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
index 2ce361f8fede..3a6c4bd0a44f 100644
--- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
+++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
@@ -67,18 +67,18 @@
compatible = "gpio-leds";
led-0 {
- label ="licheepi:red:usr";
+ label = "licheepi:red:usr";
gpios = <&pio 2 5 GPIO_ACTIVE_LOW>;
};
led-1 {
- label ="licheepi:green:usr";
+ label = "licheepi:green:usr";
gpios = <&pio 2 19 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-2 {
- label ="licheepi:blue:usr";
+ label = "licheepi:blue:usr";
gpios = <&pio 2 4 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
index a32cde3e32eb..5c3562b85a5b 100644
--- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -70,7 +70,7 @@
leds {
compatible = "gpio-leds";
- status {
+ led-0 {
label = "chip-pro:white:status";
gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index 4bf4943d4eb7..fd37bd1f3920 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -70,7 +70,7 @@
leds {
compatible = "gpio-leds";
- status {
+ led-0 {
label = "chip:white:status";
gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 715d74854449..5cce4918f84c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -46,6 +46,7 @@
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
/ {
@@ -598,7 +599,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun6i-a31-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&rtc 0>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -612,7 +613,8 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
+ clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
+ <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -820,7 +822,7 @@
clocks = <&ccu CLK_APB2_UART0>;
resets = <&ccu RST_APB2_UART0>;
dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -833,7 +835,7 @@
clocks = <&ccu CLK_APB2_UART1>;
resets = <&ccu RST_APB2_UART1>;
dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -846,7 +848,7 @@
clocks = <&ccu CLK_APB2_UART2>;
resets = <&ccu RST_APB2_UART2>;
dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -859,7 +861,7 @@
clocks = <&ccu CLK_APB2_UART3>;
resets = <&ccu RST_APB2_UART3>;
dmas = <&dma 9>, <&dma 9>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -872,7 +874,7 @@
clocks = <&ccu CLK_APB2_UART4>;
resets = <&ccu RST_APB2_UART4>;
dmas = <&dma 10>, <&dma 10>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -885,7 +887,7 @@
clocks = <&ccu CLK_APB2_UART5>;
resets = <&ccu RST_APB2_UART5>;
dmas = <&dma 22>, <&dma 22>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -1319,7 +1321,7 @@
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
- clocks = <&rtc 0>, <&osc24M>,
+ clocks = <&rtc CLK_OSC32K>, <&osc24M>,
<&ccu CLK_PLL_PERIPH>,
<&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
@@ -1354,7 +1356,7 @@
ir_clk: ir_clk {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
- clocks = <&rtc 0>, <&osc24M>;
+ clocks = <&rtc CLK_OSC32K>, <&osc24M>;
clock-output-names = "ir";
};
@@ -1385,9 +1387,8 @@
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
- resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index 0af48e143b66..56956352914d 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -67,7 +67,7 @@
leds {
compatible = "gpio-leds";
- status {
+ led-0 {
label = "sina31s:status:usr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 4f8d55d3ba79..928b86a95f34 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -78,19 +78,19 @@
gpio-keys {
compatible = "gpio-keys";
- back {
+ key-back {
label = "Key Back";
linux,code = <KEY_BACK>;
gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
};
- home {
+ key-home {
label = "Key Home";
linux,code = <KEY_HOME>;
gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
};
- menu {
+ key-menu {
label = "Key Menu";
linux,code = <KEY_MENU>;
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 4461d5098b20..4aa9d88c9ea3 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -44,6 +44,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
@@ -329,7 +330,7 @@
ccu: clock@1c20000 {
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&rtc 0>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -340,7 +341,8 @@
reg = <0x01c20800 0x400>;
interrupt-parent = <&r_intc>;
/* interrupts get set in SoC specific dtsi file */
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+ <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -488,7 +490,7 @@
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -501,7 +503,7 @@
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -514,7 +516,7 @@
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -527,7 +529,7 @@
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 9>, <&dma 9>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -540,7 +542,7 @@
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
dmas = <&dma 10>, <&dma 10>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -810,9 +812,8 @@
reg = <0x01f02c00 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
- resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index b3d1bdfb5118..30fdd2703b1f 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -278,6 +278,7 @@
dphy: d-phy@1ca1000 {
compatible = "allwinner,sun6i-a31-mipi-dphy";
reg = <0x01ca1000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_DSI_DPHY>;
clock-names = "bus", "mod";
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 5a7e1bd5f825..8d56b103f063 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -105,6 +105,21 @@
/* enables internal regulator and de-asserts reset */
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
};
+
+ /*
+ * Power supply for the SATA disk, behind a USB-SATA bridge.
+ * Since it is a USB device, there is no consumer in the DT, so we
+ * have to keep this always on.
+ */
+ regulator-sata-disk-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "sata-disk-pwr";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
+ };
};
&cpu0 {
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
index d5c7b7984d85..d729b7c705db 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -47,10 +47,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- sw4 {
+ switch-4 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@@ -106,7 +106,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@@ -181,7 +181,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <1500000>;
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index f19ed981da9d..3706216ffb40 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -169,7 +169,7 @@
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+ compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index cd9f655e4f92..a6d38ecee141 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -57,7 +57,7 @@
ethernet1 = &sdiowifi;
};
- cec-gpio {
+ cec {
compatible = "cec-gpio";
cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
hdmi-phandle = <&hdmi>;
@@ -93,10 +93,10 @@
};
};
- r-gpio-keys {
+ gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@@ -125,7 +125,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
index ff0a7a952e0c..f5c8ccc5b872 100644
--- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
+++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
@@ -39,16 +39,16 @@
};
};
- r_gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
};
- user {
+ key-user {
label = "user";
linux,code = <BTN_0>;
gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
index 8e7dfcffe1fb..343b02b97155 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
@@ -37,10 +37,10 @@
};
};
- r_gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- k1 {
+ key-0 {
label = "k1";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
@@ -57,7 +57,7 @@
regulator-ramp-delay = <50>; /* 4ms */
enable-active-high;
- enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
gpios-states = <0x1>;
states = <1100000 0>, <1300000 1>;
@@ -90,7 +90,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
@@ -151,7 +151,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
index cd3df12b6573..9e1a33f94cad 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -127,7 +127,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
index 26e2e6172e0d..42cd1131adf3 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
@@ -46,7 +46,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
@@ -147,7 +147,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
index fc45d5aaa67f..cf8413fba6c1 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -73,11 +73,10 @@
};
};
- r_gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- input-name = "k1";
- k1 {
+ key-0 {
label = "k1";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 9daffd90c12f..f1f9dbead32a 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -88,16 +88,16 @@
};
};
- r_gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- sw2 {
+ switch-2 {
label = "sw2";
linux,code = <BTN_1>;
gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
};
- sw4 {
+ switch-4 {
label = "sw4";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
index 6f9c97add54e..305b34a321f5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -87,10 +87,10 @@
};
};
- r_gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- sw4 {
+ switch-4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 4759ba3f2986..59f6f6d5e7ca 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -86,10 +86,10 @@
};
};
- r_gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- sw4 {
+ switch-4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 90f75fa85e68..b96e015f54ee 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -86,10 +86,10 @@
};
};
- r_gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- sw4 {
+ switch-4 {
label = "sw4";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index bf5b5e2f6168..bc394686fedb 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -91,7 +91,7 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@@ -283,7 +283,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_dldo1>;
vddio-supply = <&reg_aldo3>;
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index a6a1087a0c9b..28197bbcb1d5 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -43,6 +43,7 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
+#include "sun8i-r40-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -113,6 +114,10 @@
status = "okay";
};
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
&de {
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi
new file mode 100644
index 000000000000..649928b361af
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi
@@ -0,0 +1,52 @@
+/{
+ cpu0_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1000000 1000000 1300000>;
+ clock-latency-ns = <2000000>;
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <1100000 1100000 1300000>;
+ clock-latency-ns = <2000000>;
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1160000 1160000 1300000>;
+ clock-latency-ns = <2000000>;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1240000 1240000 1300000>;
+ clock-latency-ns = <2000000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1300000 1300000 1300000>;
+ clock-latency-ns = <2000000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu0_opp_table>;
+};
diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
index 265e0fa57a32..9f39b5a2bb35 100644
--- a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
@@ -5,6 +5,11 @@
// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
#include "sun8i-r40.dtsi"
+#include "sun8i-r40-cpu-opp.dtsi"
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 03d3e5f45a09..4ef26d8f5340 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -42,6 +42,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
@@ -84,24 +85,36 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
+ clocks = <&ccu CLK_CPU>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
+ clocks = <&ccu CLK_CPU>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
+ clocks = <&ccu CLK_CPU>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
+ clocks = <&ccu CLK_CPU>;
+ clock-names = "cpu";
+ #cooling-cells = <2>;
};
};
@@ -117,6 +130,30 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_hot_trip: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot_trip: cpu-very-hot {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu_hot_trip>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
gpu_thermal: gpu-thermal {
@@ -485,7 +522,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&rtc 0>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -504,7 +541,8 @@
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+ <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -1231,7 +1269,7 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
- <&ccu CLK_HDMI>, <&rtc 0>;
+ <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
diff --git a/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts
new file mode 100644
index 000000000000..94e24b5926dd
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Arm Ltd.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+
+#include "sun8i-t113s.dtsi"
+#include "sunxi-d1s-t113-mangopi-mq-r.dtsi"
+
+/ {
+ model = "MangoPi MQ-R-T113";
+ compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s";
+
+ aliases {
+ ethernet0 = &rtl8189ftv;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vcc_core>;
+};
+
+&cpu1 {
+ cpu-supply = <&reg_vcc_core>;
+};
+
+&mmc1 {
+ rtl8189ftv: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */
+ interrupt-names = "host-wake";
+ };
+};
diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/sun8i-t113s.dtsi
new file mode 100644
index 000000000000..804aa197a24f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-t113s.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Arm Ltd.
+
+#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <riscv/allwinner/sunxi-d1s-t113.dtsi>
+#include <riscv/allwinner/sunxi-d1-t113.dtsi>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
+ };
+ };
+
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+};
diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts
index 6931aaab2382..9f472521f4a4 100644
--- a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts
+++ b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts
@@ -45,6 +45,7 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
+#include "sun8i-r40-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -88,6 +89,10 @@
status = "okay";
};
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
&de {
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 084323d5c61c..b001251644f7 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -42,6 +42,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>
@@ -321,7 +322,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&rtc 0>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -342,7 +343,8 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+ <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@@ -477,7 +479,7 @@
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -490,7 +492,7 @@
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -503,7 +505,7 @@
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART2>;
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index 47954551f573..434871040aca 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -42,6 +42,7 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
+#include "sun8i-r40-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -107,6 +108,10 @@
status = "okay";
};
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
&de {
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index ce4fa6706d06..7d3f3300f431 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1218,7 +1218,6 @@
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
- resets = <&apbs_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6c7cb5..43896723a994 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,17 +6,54 @@
/dts-v1/;
#include "suniv-f1c100s.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
aliases {
+ mmc0 = &mmc0;
serial0 = &uart0;
+ spi0 = &spi0;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ status = "okay";
+ vmmc-supply = <&reg_vcc3v3>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pc_pins>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&otg_sram {
+ status = "okay";
};
&uart0 {
@@ -24,3 +61,13 @@
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 6100d3b75f61..3c61d59ab5f8 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
* Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
*/
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -26,9 +29,13 @@
};
cpus {
- cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0x0>;
};
};
@@ -62,6 +69,96 @@
};
};
+ spi0: spi@1c05000 {
+ compatible = "allwinner,suniv-f1c100s-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <10>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@1c06000 {
+ compatible = "allwinner,suniv-f1c100s-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <11>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <23>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <24>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>;
@@ -82,30 +179,119 @@
compatible = "allwinner,suniv-f1c100s-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <38>, <39>, <40>;
- clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ };
+
+ /omit-if-no-ref/
+ i2c0_pd_pins: i2c0-pd-pins {
+ pins = "PD0", "PD12";
+ function = "i2c0";
+ };
+
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
+
uart0_pe_pins: uart0-pe-pins {
pins = "PE0", "PE1";
function = "uart0";
};
+
+ /omit-if-no-ref/
+ uart1_pa_pins: uart1-pa-pins {
+ pins = "PA2", "PA3";
+ function = "uart1";
+ };
+ };
+
+ i2c0: i2c@1c27000 {
+ compatible = "allwinner,suniv-f1c100s-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c27000 0x400>;
+ interrupts = <7>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@1c27400 {
+ compatible = "allwinner,suniv-f1c100s-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c27400 0x400>;
+ interrupts = <8>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1c27800 {
+ compatible = "allwinner,suniv-f1c100s-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01c27800 0x400>;
+ interrupts = <9>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
timer@1c20c00 {
compatible = "allwinner,suniv-f1c100s-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <13>;
+ interrupts = <13>, <14>, <15>;
clocks = <&osc24M>;
};
wdt: watchdog@1c20ca0 {
compatible = "allwinner,suniv-f1c100s-wdt",
- "allwinner,sun4i-a10-wdt";
+ "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
+ interrupts = <16>;
+ clocks = <&osc32k>;
+ };
+
+ pwm: pwm@1c21000 {
+ compatible = "allwinner,suniv-f1c100s-pwm",
+ "allwinner,sun7i-a20-pwm";
+ reg = <0x01c21000 0x400>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir: ir@1c22c00 {
+ compatible = "allwinner,suniv-f1c100s-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01c22c00 0x400>;
+ clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&ccu RST_BUS_IR>;
+ interrupts = <6>;
+ status = "disabled";
+ };
+
+ lradc: lradc@1c23400 {
+ compatible = "allwinner,suniv-f1c100s-lradc",
+ "allwinner,sun8i-a83t-r-lradc";
+ reg = <0x01c23400 0x400>;
+ interrupts = <22>;
+ status = "disabled";
};
uart0: serial@1c25000 {
@@ -114,8 +300,8 @@
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 38>;
- resets = <&ccu 24>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -125,8 +311,8 @@
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 39>;
- resets = <&ccu 25>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -136,8 +322,8 @@
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&ccu 40>;
- resets = <&ccu 26>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
new file mode 100644
index 000000000000..2d2a3f026df3
--- /dev/null
+++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Arm Ltd,
+ * based on work:
+ * Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Lctech Pi F1C200s";
+ compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
+ "allwinner,suniv-f1c100s";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_vcc3v3>;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pc_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pa_pins>;
+ status = "okay";
+};
+
+/*
+ * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected
+ * to Vin, which supplies the board. Host mode works (if the board is powered
+ * otherwise), but peripheral is probably the intention.
+ */
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
new file mode 100644
index 000000000000..184c245041a6
--- /dev/null
+++ b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Popcorn Computer PopStick v1.1";
+ compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
+ "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_vcc3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_vcc3v3>;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pc_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pe_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi
new file mode 100644
index 000000000000..493d32357e4e
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Sunplus SP7021
+ *
+ * Copyright (C) 2021 Sunplus Technology Co.
+ */
+
+#include "sunplus-sp7021.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
+ model = "Sunplus SP7021 (CA7)";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <931000000>;
+ };
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clock-frequency = <931000000>;
+ };
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ clock-frequency = <931000000>;
+ };
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ clock-frequency = <931000000>;
+ };
+ };
+
+ gic: interrupt-controller@9f101000 {
+ compatible = "arm,cortex-a7-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x9f101000 0x1000>,
+ <0x9f102000 0x2000>,
+ <0x9f104000 0x2000>,
+ <0x9f106000 0x2000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <XTAL>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ soc@9c000000 {
+ intc: interrupt-controller@780 {
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts
new file mode 100644
index 000000000000..d5c5ffc20565
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Sunplus SP7021 Demo V3 SBC board
+ *
+ * Copyright (C) Sunplus Technology Co.
+ */
+
+/dts-v1/;
+
+#include "sunplus-sp7021-achip.dtsi"
+
+/ {
+ compatible = "sunplus,sp7021-demo-v3", "sunplus,sp7021";
+ model = "Sunplus SP7021/CA7/Demo_V3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus-sp7021.dtsi
new file mode 100644
index 000000000000..ae9bbe0320b8
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus-sp7021.dtsi
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Sunplus SP7021
+ *
+ * Copyright (C) 2021 Sunplus Technology Co.
+ */
+
+#include <dt-bindings/clock/sunplus,sp7021-clkc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sunplus,sp7021-reset.h>
+#include <dt-bindings/pinctrl/sppctl-sp7021.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define XTAL 27000000
+
+/ {
+ compatible = "sunplus,sp7021";
+ model = "Sunplus SP7021";
+
+ clocks {
+ extclk: osc0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <XTAL>;
+ clock-output-names = "extclk";
+ };
+ };
+
+ soc@9c000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x9c000000 0x400000>;
+ interrupt-parent = <&intc>;
+
+ clkc: clock-controller@4 {
+ compatible = "sunplus,sp7021-clkc";
+ reg = <0x4 0x28>,
+ <0x200 0x44>,
+ <0x268 0x04>;
+ clocks = <&extclk>;
+ #clock-cells = <1>;
+ };
+
+ intc: interrupt-controller@780 {
+ compatible = "sunplus,sp7021-intc";
+ reg = <0x780 0x80>, <0xa80 0x80>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ otp: otp@af00 {
+ compatible = "sunplus,sp7021-ocotp";
+ reg = <0xaf00 0x34>, <0xaf80 0x58>;
+ reg-names = "hb_gpio", "otprx";
+ clocks = <&clkc CLK_OTPRX>;
+ resets = <&rstc RST_OTPRX>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ therm_calib: thermal-calibration@14 {
+ reg = <0x14 0x3>;
+ };
+ disc_vol: disconnect-voltage@18 {
+ reg = <0x18 0x2>;
+ };
+ mac_addr0: mac-address0@34 {
+ reg = <0x34 0x6>;
+ };
+ mac_addr1: mac-address1@3a {
+ reg = <0x3a 0x6>;
+ };
+ };
+
+ pctl: pinctrl@100 {
+ compatible = "sunplus,sp7021-pctl";
+ reg = <0x100 0x100>,
+ <0x300 0x100>,
+ <0x32e4 0x1C>,
+ <0x80 0x20>;
+ reg-names = "moon2", "gpioxt", "first", "moon1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clkc CLK_GPIO>;
+ resets = <&rstc RST_GPIO>;
+
+ emac_pins: pinmux-emac-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
+ SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
+ SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
+ SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
+ SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
+ SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
+ SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
+ SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
+ SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
+ SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
+ SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
+ SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
+ SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
+ SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
+ SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
+ SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
+ SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
+ >;
+ sunplus,zerofunc = <
+ MUXF_L2SW_LED_FLASH0
+ MUXF_L2SW_LED_FLASH1
+ MUXF_L2SW_LED_ON0
+ MUXF_L2SW_LED_ON1
+ MUXF_DAISY_MODE
+ >;
+ };
+
+ emmc_pins: pinmux-emmc-pins {
+ function = "CARD0_EMMC";
+ groups = "CARD0_EMMC";
+ };
+
+ leds_pins: pinmux-leds-pins {
+ sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
+ };
+
+ sdcard_pins: pinmux-sdcard-pins {
+ function = "SD_CARD";
+ groups = "SD_CARD";
+ sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
+ };
+
+ spi0_pins: pinmux-spi0-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
+ SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0)
+ SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0)
+ SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0)
+ SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0)
+ >;
+ };
+
+ uart0_pins: pinmux-uart0-pins {
+ function = "UA0";
+ groups = "UA0";
+ };
+
+ uart1_pins: pinmux-uart1-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
+ SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
+ >;
+ };
+
+ uart2_pins: pinmux-uart2-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0)
+ SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0)
+ SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0)
+ SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0)
+ >;
+ };
+
+ uart4_pins: pinmux-uart4-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
+ SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
+ SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0)
+ SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0)
+ >;
+ };
+ };
+
+ rstc: reset@54 {
+ compatible = "sunplus,sp7021-reset";
+ reg = <0x54 0x28>;
+ #reset-cells = <1>;
+ };
+
+ rtc: rtc@3a00 {
+ compatible = "sunplus,sp7021-rtc";
+ reg = <0x3a00 0x80>;
+ reg-names = "rtc";
+ clocks = <&clkc CLK_RTC>;
+ resets = <&rstc RST_RTC>;
+ interrupts = <163 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ spi_controller0: spi@2d80 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0x2d80 0x80>, <0x2e00 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
+ <146 IRQ_TYPE_LEVEL_HIGH>,
+ <145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_0>;
+ resets = <&rstc RST_SPI_COMBO_0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>,
+ <&pctl 28 GPIO_ACTIVE_LOW>;
+ };
+
+ spi_controller1: spi@f480 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0xf480 0x80>, <0xf500 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <67 IRQ_TYPE_LEVEL_HIGH>,
+ <69 IRQ_TYPE_LEVEL_HIGH>,
+ <68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_1>;
+ resets = <&rstc RST_SPI_COMBO_1>;
+ status = "disabled";
+ };
+
+ spi_controller2: spi@f600 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0xf600 0x80>, <0xf680 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>,
+ <72 IRQ_TYPE_LEVEL_HIGH>,
+ <71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_2>;
+ resets = <&rstc RST_SPI_COMBO_2>;
+ status = "disabled";
+ };
+
+ spi_controller3: spi@f780 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0xf780 0x80>, <0xf800 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <73 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_3>;
+ resets = <&rstc RST_SPI_COMBO_3>;
+ status = "disabled";
+ };
+
+ uart0: serial@900 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x900 0x80>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA0>;
+ resets = <&rstc RST_UA0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ };
+
+ uart1: serial@980 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x980 0x80>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA1>;
+ resets = <&rstc RST_UA1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+ };
+
+ uart2: serial@800 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x800 0x80>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA2>;
+ resets = <&rstc RST_UA2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+ };
+
+ uart3: serial@880 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x880 0x80>;
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA3>;
+ resets = <&rstc RST_UA3>;
+ status = "disabled";
+ };
+
+ uart4: serial@8780 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x8780 0x80>;
+ interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA4>;
+ resets = <&rstc RST_UA4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ status = "disabled";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins>;
+ system-led {
+ label = "system-led";
+ gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
index d03f5853ef7b..1d1d127cf38f 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
@@ -77,10 +77,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- sw4 {
+ switch-4 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@@ -89,19 +89,19 @@
};
reg_gmac_3v3: gmac-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "gmac-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <100000>;
- enable-active-high;
- gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@@ -221,7 +221,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <1500000>;
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi
new file mode 100644
index 000000000000..e9bc749488bb
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Arm Ltd.
+/*
+ * Common peripherals and configurations for MangoPi MQ-R boards.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */
+ };
+ };
+
+ /* board wide 5V supply directly from the USB-C socket */
+ reg_vcc5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ /* SY8008 DC/DC regulator on the board */
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&reg_vcc5v>;
+ };
+
+ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
+ reg_vcc_core: regulator-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-core";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ vin-supply = <&reg_vcc5v>;
+ };
+
+ /* XC6206 LDO on the board */
+ reg_avdd2v8: regulator-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&reg_3v3>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ };
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&reg_3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&reg_3v3>;
+ non-removable;
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <&reg_3v3>;
+ vcc-pd-supply = <&reg_3v3>;
+ vcc-pe-supply = <&reg_avdd2v8>;
+ vcc-pf-supply = <&reg_3v3>;
+ vcc-pg-supply = <&reg_3v3>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pb_pins>;
+ status = "okay";
+};
+
+/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc5v>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
index fc67e30fe212..60804b0e6c56 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
@@ -22,7 +22,7 @@
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
post-power-on-delay-ms = <200>;
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@@ -124,7 +124,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
- clocks = <&rtc 1>;
+ clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d7e9f977f986..ade1cd50e445 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -40,6 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
@@ -301,6 +302,8 @@
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
status = "disabled";
};
@@ -311,6 +314,8 @@
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
status = "disabled";
};
@@ -386,7 +391,7 @@
ccu: clock@1c20000 {
/* compatible is in per SoC .dtsi file */
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&rtc 0>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -398,7 +403,8 @@
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+ <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@@ -704,7 +710,7 @@
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -717,7 +723,7 @@
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -730,7 +736,7 @@
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -743,7 +749,7 @@
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 9>, <&dma 9>;
- dma-names = "rx", "tx";
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -818,7 +824,7 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
- <&ccu CLK_HDMI>, <&rtc 0>;
+ <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
@@ -878,7 +884,7 @@
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-h3-r-ccu";
reg = <0x01f01400 0x100>;
- clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
@@ -931,7 +937,8 @@
reg = <0x01f02c00 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
+ <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
index 9e14fe5fdcde..89731bb34c6b 100644
--- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
@@ -42,10 +42,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts
index b791ce97424b..84a3eb38e71d 100644
--- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts
+++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts
@@ -25,6 +25,14 @@
serial2 = &uartb; /* GPS */
};
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <2>;
+ tlm,version-minor = <8>;
+ };
+ };
+
memory@80000000 {
reg = <0x80000000 0x80000000>;
};
@@ -80,7 +88,7 @@
};
pinmux@70000868 {
- asus_pad_ec_default: asus-pad-ec-default {
+ asus_pad_ec_default: pinmux-asus-pad-ec-default {
ec-interrupt {
nvidia,pins = "kb_col5_pq5";
nvidia,function = "kbc";
@@ -98,7 +106,7 @@
};
};
- backlight_default: backlight-default {
+ backlight_default: pinmux-backlight-default {
backlight-enable {
nvidia,pins = "gmi_ad10_ph2";
nvidia,function = "gmi";
@@ -108,7 +116,16 @@
};
};
- codec_default: codec-default {
+ codec_default: pinmux-codec-default {
+ interrupt {
+ nvidia,pins = "gpio_w2_aud_pw2",
+ "gpio_w3_aud_pw3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
ldo1-en {
nvidia,pins = "sdmmc1_wp_n_pv3";
nvidia,function = "sdmmc1";
@@ -116,18 +133,19 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
+ };
- interrupt {
- nvidia,pins = "gpio_w2_aud_pw2",
- "gpio_w3_aud_pw3";
- nvidia,function = "spi6";
+ gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default {
+ ulpi_data4_po5 {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: pinmux-gpio-keys-default {
power {
nvidia,pins = "kb_col0_pq0";
nvidia,function = "kbc";
@@ -146,17 +164,7 @@
};
};
- gpio_hall_sensor_default: gpio-hall-sensor-default {
- ulpi_data4_po5 {
- nvidia,pins = "ulpi_data4_po5";
- nvidia,function = "spi2";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- };
- };
-
- hp_det_default: hp-det-default {
+ hp_det_default: pinmux-hp-det-default {
gmi_iordy_pi5 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "rsvd2";
@@ -166,7 +174,7 @@
};
};
- imu_default: imu-default {
+ imu_default: pinmux-imu-default {
kb_row3_pr3 {
nvidia,pins = "kb_row3_pr3";
nvidia,function = "rsvd3";
@@ -176,7 +184,7 @@
};
};
- pwm_default: pwm-default {
+ pwm_default: pinmux-pwm-default {
gmi_ad9_ph1 {
nvidia,pins = "gmi_ad9_ph1";
nvidia,function = "pwm1";
@@ -187,7 +195,7 @@
};
/* XXX make this something more sensible */
- pwm_sleep: pwm-sleep {
+ pwm_sleep: pinmux-pwm-sleep {
gmi_ad9_ph1 {
nvidia,pins = "gmi_ad9_ph1";
nvidia,function = "pwm1";
@@ -197,7 +205,17 @@
};
};
- sdmmc3_default: sdmmc3-default {
+ sdmmc3_default: pinmux-sdmmc3-default {
+ drive_sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <22>;
+ nvidia,pull-up-strength = <36>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
@@ -221,19 +239,9 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
-
- drive_sdio3 {
- nvidia,pins = "drive_sdio3";
- nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
- nvidia,schmitt = <TEGRA_PIN_DISABLE>;
- nvidia,pull-down-strength = <22>;
- nvidia,pull-up-strength = <36>;
- nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
- nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
- };
};
- sdmmc3_vdd_default: sdmmc3-vdd-default {
+ sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default {
gmi_clk_pk1 {
nvidia,pins = "gmi_clk_pk1";
nvidia,function = "gmi";
@@ -243,7 +251,7 @@
};
};
- vdd_lcd_default: vdd-lcd-default {
+ vdd_lcd_default: pinmux-vdd-lcd-default {
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4";
nvidia,function = "sdmmc4";
@@ -298,6 +306,14 @@
pinctrl-0 = <&codec_default>;
};
+ temp_sensor: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+
motion-tracker@68 {
compatible = "invensense,mpu6500";
reg = <0x68>;
@@ -312,14 +328,6 @@
pinctrl-names = "default";
pinctrl-0 = <&imu_default>;
};
-
- temp_sensor: temperature-sensor@4c {
- compatible = "onnn,nct1008";
- reg = <0x4c>;
-
- vcc-supply = <&vdd_3v3_sys>;
- #thermal-sensor-cells = <1>;
- };
};
i2c@7000c400 {
@@ -368,6 +376,66 @@
#gpio-cells = <2>;
};
+ pinmux {
+ compatible = "ti,tps65913-pinctrl";
+ ti,palmas-enable-dvfs1;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&palmas_default>;
+
+ palmas_default: pinmux {
+ pin_gpio0 {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ pin_gpio1 {
+ pins = "gpio1";
+ function = "gpio";
+ };
+
+ pin_gpio2 {
+ pins = "gpio2";
+ function = "gpio";
+ };
+
+ pin_gpio3 {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ pin_gpio4 {
+ pins = "gpio4";
+ function = "gpio";
+ };
+
+ pin_gpio5 {
+ pins = "gpio5";
+ function = "gpio";
+ };
+
+ pin_gpio6 {
+ pins = "gpio6";
+ function = "gpio";
+ };
+
+ pin_gpio7 {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ pin_powergood {
+ pins = "powergood";
+ function = "powergood";
+ };
+
+ pin_vac {
+ pins = "vac";
+ function = "vac";
+ };
+ };
+ };
+
pmic {
compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
@@ -528,66 +596,6 @@
interrupt-parent = <&palmas>;
interrupts = <8 0>;
};
-
- pinmux {
- compatible = "ti,tps65913-pinctrl";
- ti,palmas-enable-dvfs1;
-
- pinctrl-names = "default";
- pinctrl-0 = <&palmas_default>;
-
- palmas_default: pinmux {
- pin_powergood {
- pins = "powergood";
- function = "powergood";
- };
-
- pin_vac {
- pins = "vac";
- function = "vac";
- };
-
- pin_gpio0 {
- pins = "gpio0";
- function = "gpio";
- };
-
- pin_gpio1 {
- pins = "gpio1";
- function = "gpio";
- };
-
- pin_gpio2 {
- pins = "gpio2";
- function = "gpio";
- };
-
- pin_gpio3 {
- pins = "gpio3";
- function = "gpio";
- };
-
- pin_gpio4 {
- pins = "gpio4";
- function = "gpio";
- };
-
- pin_gpio5 {
- pins = "gpio5";
- function = "gpio";
- };
-
- pin_gpio6 {
- pins = "gpio6";
- function = "gpio";
- };
-
- pin_gpio7 {
- pins = "gpio7";
- function = "gpio";
- };
- };
- };
};
};
@@ -668,11 +676,21 @@
clock-output-names = "pmic-oscillator";
};
- firmware {
- trusted-foundations {
- compatible = "tlm,trusted-foundations";
- tlm,version-major = <2>;
- tlm,version-minor = <8>;
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+
+ label = "GPIO Hall Effect Sensor";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_hall_sensor_default>;
+
+ switch-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ wakeup-source;
};
};
@@ -684,7 +702,7 @@
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_default>;
- power {
+ button-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -692,36 +710,18 @@
wakeup-source;
};
- volume-up {
- label = "Volume Up";
- gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <10>;
- };
-
- volume-down {
+ button-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <10>;
};
- };
- gpio-hall-sensor {
- compatible = "gpio-keys";
-
- label = "GPIO Hall Effect Sensor";
-
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_hall_sensor_default>;
-
- hall-sensor {
- label = "Hall Effect Sensor";
- gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_SW>;
- linux,code = <SW_LID>;
- linux,can-disable;
- wakeup-source;
+ button-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
};
};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 658edfb8d7fa..a685fcb129d0 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -909,6 +909,19 @@
#gpio-cells = <2>;
};
+ pinmux {
+ compatible = "ti,tps65913-pinctrl";
+ pinctrl-names = "default";
+ pinctrl-0 = <&palmas_default>;
+
+ palmas_default: pinmux {
+ pin_gpio6 {
+ pins = "gpio6";
+ function = "gpio";
+ };
+ };
+ };
+
pmic {
compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
smps1-in-supply = <&tps65090_dcdc3_reg>;
@@ -1065,19 +1078,6 @@
interrupt-parent = <&palmas>;
interrupts = <8 0>;
};
-
- pinmux {
- compatible = "ti,tps65913-pinctrl";
- pinctrl-names = "default";
- pinctrl-0 = <&palmas_default>;
-
- palmas_default: pinmux {
- pin_gpio6 {
- pins = "gpio6";
- function = "gpio";
- };
- };
- };
};
};
@@ -1161,26 +1161,26 @@
gpio-keys {
compatible = "gpio-keys";
- home {
+ key-home {
label = "Home";
gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- volume_down {
+ key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
- volume_up {
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 2498cf18fd39..b9d00009d1f4 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -1025,19 +1025,19 @@
gpio-keys {
compatible = "gpio-keys";
- back {
+ key-back {
label = "Back";
gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
- home {
+ key-home {
label = "Home";
gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
index ef8f722dd9cb..f02d8c79eee7 100644
--- a/arch/arm/boot/dts/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -282,20 +282,20 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- volume_down {
+ key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
- volume_up {
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
index 7143c6b2ec3e..970f33dd9101 100644
--- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
@@ -4,6 +4,8 @@
*
*/
+#include <dt-bindings/clock/tegra124-car.h>
+
/ {
clock@60006000 {
emc-timings-1 {
@@ -1474,12 +1476,12 @@
};
};
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-1200000000-1100;
-};
+ opp-table-actmon {
+ /delete-node/ opp-1200000000;
+ };
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-1200000000;
+ opp-table-emc {
+ /delete-node/ opp-1200000000-1100;
+ };
};
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index 3209554ec7e6..2df2d8a6b552 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -40,6 +40,16 @@
};
};
+ gpio: gpio@6000d000 {
+ /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+ pex-perst-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PEX_PERST_N";
+ };
+ };
+
/* Apalis UART1 */
serial@70006000 {
status = "okay";
@@ -191,7 +201,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "WAKE1_MICO";
gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -243,13 +253,3 @@
vin-supply = <&reg_5v0>;
};
};
-
-&gpio {
- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "PEX_PERST_N";
- };
-};
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
index 814257c79bf1..f4521fd15f6a 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
@@ -41,6 +41,16 @@
};
};
+ gpio@6000d000 {
+ /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+ pex-perst-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PEX_PERST_N";
+ };
+ };
+
/* Apalis UART1 */
serial@70006000 {
status = "okay";
@@ -193,7 +203,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "WAKE1_MICO";
gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -245,13 +255,3 @@
vin-supply = <&reg_5v0>;
};
};
-
-&gpio {
- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "PEX_PERST_N";
- };
-};
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index dbb0da08cb95..75cfe718737c 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -65,6 +65,24 @@
vdd-supply = <&reg_vdd_gpu>;
};
+ gpio@6000d000 {
+ /* I210 Gigabit Ethernet Controller Reset */
+ lan-reset-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LAN_RESET_N";
+ };
+
+ /* Control MXM3 pin 26 Reset Module Output Carrier Input */
+ reset-moci-ctrl-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RESET_MOCI_CTRL";
+ };
+ };
+
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@@ -1585,18 +1603,18 @@
pinctrl-0 = <&as3722_default>;
as3722_default: pinmux {
+ gpio0-1-3-4-5-6 {
+ pins = "gpio0", "gpio1", "gpio3",
+ "gpio4", "gpio5", "gpio6";
+ bias-high-impedance;
+ };
+
gpio2-7 {
pins = "gpio2", /* PWR_EN_+V3.3 */
"gpio7"; /* +V1.6_LPO */
function = "gpio";
bias-pull-up;
};
-
- gpio0-1-3-4-5-6 {
- pins = "gpio0", "gpio1", "gpio3",
- "gpio4", "gpio5", "gpio6";
- bias-high-impedance;
- };
};
regulators {
@@ -1943,18 +1961,18 @@
};
};
- clk32k_in: osc3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-
cpus {
cpu@0 {
vdd-cpu-supply = <&reg_vdd_cpu>;
};
};
+ clk32k_in: osc3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
compatible = "regulator-fixed";
regulator-name = "+V1.05_AVDD_HDMI_PLL";
@@ -2056,21 +2074,3 @@
};
};
};
-
-&gpio {
- /* I210 Gigabit Ethernet Controller Reset */
- lan-reset-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "LAN_RESET_N";
- };
-
- /* Control MXM3 pin 26 Reset Module Output Carrier Input */
- reset-moci-ctrl-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "RESET_MOCI_CTRL";
- };
-};
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index d3f16c117b0c..554c8089491c 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -64,6 +64,24 @@
vdd-supply = <&reg_vdd_gpu>;
};
+ gpio@6000d000 {
+ /* I210 Gigabit Ethernet Controller Reset */
+ lan-reset-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LAN_RESET_N";
+ };
+
+ /* Control MXM3 pin 26 Reset Module Output Carrier Input */
+ reset-moci-ctrl-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RESET_MOCI_CTRL";
+ };
+ };
+
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@@ -1578,18 +1596,18 @@
pinctrl-0 = <&as3722_default>;
as3722_default: pinmux {
+ gpio0-1-3-4-5-6 {
+ pins = "gpio0", "gpio1", "gpio3",
+ "gpio4", "gpio5", "gpio6";
+ bias-high-impedance;
+ };
+
gpio2-7 {
pins = "gpio2", /* PWR_EN_+V3.3 */
"gpio7"; /* +V1.6_LPO */
function = "gpio";
bias-pull-up;
};
-
- gpio0-1-3-4-5-6 {
- pins = "gpio0", "gpio1", "gpio3",
- "gpio4", "gpio5", "gpio6";
- bias-high-impedance;
- };
};
regulators {
@@ -1935,18 +1953,18 @@
};
};
- clk32k_in: osc3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-
cpus {
cpu@0 {
vdd-cpu-supply = <&reg_vdd_cpu>;
};
};
+ clk32k_in: osc3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
compatible = "regulator-fixed";
regulator-name = "+V1.05_AVDD_HDMI_PLL";
@@ -2048,21 +2066,3 @@
};
};
};
-
-&gpio {
- /* I210 Gigabit Ethernet Controller Reset */
- lan-reset-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "LAN_RESET_N";
- };
-
- /* Control MXM3 pin 26 Reset Module Output Carrier Input */
- reset-moci-ctrl-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "RESET_MOCI_CTRL";
- };
-};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
index 79e776db5f37..d10e5334a6c6 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
@@ -1,4 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/clock/tegra124-car.h>
+
/ {
clock@60006000 {
emc-timings-3 {
@@ -2429,12 +2432,12 @@
};
};
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-1200000000-1100;
-};
+ opp-table-actmon {
+ /delete-node/ opp-1200000000;
+ };
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-1200000000;
+ opp-table-emc {
+ /delete-node/ opp-1200000000-1100;
+ };
};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 28b889e4e33b..4196f2401c90 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -68,10 +68,6 @@
};
};
- cec@70015000 {
- status = "okay";
- };
-
gpu@57000000 {
/*
* Node left disabled on purpose - the bootloader will enable
@@ -1683,6 +1679,10 @@
};
};
+ cec@70015000 {
+ status = "okay";
+ };
+
/* Serial ATA */
sata@70020000 {
status = "okay";
@@ -1886,7 +1886,7 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
index 31b2e26c69d4..cadb1969f1cc 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
-/ {
- apbmisc@70000800 {
- nvidia,long-ram-code;
- };
+#include <dt-bindings/clock/tegra124-car.h>
+
+/ {
clock@60006000 {
emc-timings-1 {
nvidia,ram-code = <1>;
@@ -249,6 +248,10 @@
};
};
+ apbmisc@70000800 {
+ nvidia,long-ram-code;
+ };
+
memory-controller@70019000 {
emc-timings-1 {
nvidia,ram-code = <1>;
@@ -6678,14 +6681,14 @@
};
};
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-924000000-1100;
- /delete-node/ opp-1200000000-1100;
-};
+ opp-table-actmon {
+ /delete-node/ opp-924000000;
+ /delete-node/ opp-1200000000;
+ };
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-924000000;
- /delete-node/ opp-1200000000;
+ opp-table-emc {
+ /delete-node/ opp-924000000-1100;
+ /delete-node/ opp-1200000000-1100;
+ };
};
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index fdc1d64dfff9..8bca9599ad6e 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -18,28 +18,18 @@
aux-bus {
panel: panel {
compatible = "auo,b133xtn01";
+ power-supply = <&vdd_3v3_panel>;
backlight = <&backlight>;
};
};
};
};
- mmc@700b0400 { /* SD Card on this bus */
- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
- };
-
- sound {
- compatible = "nvidia,tegra-audio-max98090-nyan-big",
- "nvidia,tegra-audio-max98090-nyan",
- "nvidia,tegra-audio-max98090";
- nvidia,model = "GoogleNyanBig";
- };
-
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
- pinmux_default: common {
+ pinmux_default: pinmux {
clk_32k_out_pa0 {
nvidia,pins = "clk_32k_out_pa0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1344,4 +1334,15 @@
};
};
};
+
+ mmc@700b0400 { /* SD Card on this bus */
+ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-max98090-nyan-big",
+ "nvidia,tegra-audio-max98090-nyan",
+ "nvidia,tegra-audio-max98090";
+ nvidia,model = "GoogleNyanBig";
+ };
};
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
index 2ce1b12be44d..e8dcc4f51fc5 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
@@ -1,4 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/clock/tegra124-car.h>
+
/ {
clock@60006000 {
emc-timings-1 {
@@ -2055,14 +2058,14 @@
};
};
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-924000000-1100;
- /delete-node/ opp-1200000000-1100;
-};
+ opp-table-actmon {
+ /delete-node/ opp-924000000;
+ /delete-node/ opp-1200000000;
+ };
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-924000000;
- /delete-node/ opp-1200000000;
+ opp-table-emc {
+ /delete-node/ opp-924000000-1100;
+ /delete-node/ opp-1200000000-1100;
+ };
};
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
index abdf4456826f..432540c10065 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -20,24 +20,18 @@
aux-bus {
panel: panel {
compatible = "samsung,ltn140at29-301";
+ power-supply = <&vdd_3v3_panel>;
backlight = <&backlight>;
};
};
};
};
- sound {
- compatible = "nvidia,tegra-audio-max98090-nyan-blaze",
- "nvidia,tegra-audio-max98090-nyan",
- "nvidia,tegra-audio-max98090";
- nvidia,model = "GoogleNyanBlaze";
- };
-
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
- pinmux_default: common {
+ pinmux_default: pinmux {
clk_32k_out_pa0 {
nvidia,pins = "clk_32k_out_pa0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1342,4 +1336,11 @@
};
};
};
+
+ sound {
+ compatible = "nvidia,tegra-audio-max98090-nyan-blaze",
+ "nvidia,tegra-audio-max98090-nyan",
+ "nvidia,tegra-audio-max98090";
+ nvidia,model = "GoogleNyanBlaze";
+ };
};
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index a93cfb492ba1..56952333ae28 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -498,12 +498,6 @@
};
};
- sdhci0_pwrseq: sdhci0_pwrseq {
- compatible = "mmc-pwrseq-simple";
-
- reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
- };
-
mmc@700b0000 { /* WiFi/BT on this bus */
status = "okay";
bus-width = <4>;
@@ -595,15 +589,36 @@
};
cpus {
- cpu@0 {
+ cpu0: cpu@0 {
+ #cooling-cells = <2>;
vdd-cpu-supply = <&vdd_cpu>;
};
+
+ cpu1: cpu@1 {
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@2 {
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@3 {
+ #cooling-cells = <2>;
+ };
};
gpio-keys {
compatible = "gpio-keys";
- lid {
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <30>;
+ wakeup-source;
+ };
+
+ switch-lid {
label = "Lid";
gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
linux,input-type = <5>;
@@ -611,14 +626,18 @@
debounce-interval = <1>;
wakeup-source;
};
+ };
- power {
- label = "Power";
- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- debounce-interval = <30>;
- wakeup-source;
- };
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+
+ sdhci0_pwrseq: pwrseq-sdhci0 {
+ compatible = "mmc-pwrseq-simple";
+
+ reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
vdd_mux: regulator-mux {
@@ -785,30 +804,6 @@
<&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
};
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
- priority = <200>;
- };
-
- cpus {
- cpu0: cpu@0 {
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- #cooling-cells = <2>;
- };
- };
-
thermal-zones {
cpu-skin-thermal {
polling-delay-passive = <1000>; /* milliseconds */
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 6a9592ceb5f2..7e739879c00c 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -52,6 +52,7 @@
aux-bus {
panel: panel {
compatible = "lg,lp129qe";
+ power-supply = <&vdd_3v3_panel>;
backlight = <&backlight>;
};
};
@@ -70,7 +71,7 @@
pinctrl-names = "boot";
pinctrl-0 = <&pinmux_boot>;
- pinmux_boot: common {
+ pinmux_boot: pinmux {
dap_mclk1_pw4 {
nvidia,pins = "dap_mclk1_pw4";
nvidia,function = "extperiph1";
@@ -1078,7 +1079,7 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index a9ab548781e1..b3fbecf5c818 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -639,6 +639,16 @@
reset-names = "fuse";
};
+ cec@70015000 {
+ compatible = "nvidia,tegra124-cec";
+ reg = <0x0 0x70015000 0x0 0x00001000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_CEC>;
+ clock-names = "cec";
+ status = "disabled";
+ hdmi-phandle = <&hdmi>;
+ };
+
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
@@ -906,16 +916,6 @@
status = "disabled";
};
- cec@70015000 {
- compatible = "nvidia,tegra124-cec";
- reg = <0x0 0x70015000 0x0 0x00001000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_CEC>;
- clock-names = "cec";
- status = "disabled";
- hdmi-phandle = <&hdmi>;
- };
-
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra124-soctherm";
reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index a170a4ba36c1..08b42952f4de 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -342,36 +342,39 @@
};
};
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ state_i2cmux_ddc: pinmux-i2cmux-ddc {
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
};
+
pta {
nvidia,pins = "pta";
nvidia,function = "rsvd4";
};
};
- state_i2cmux_pta: pinmux_i2cmux_pta {
+ state_i2cmux_idle: pinmux-i2cmux-idle {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
+
pta {
nvidia,pins = "pta";
- nvidia,function = "i2c2";
+ nvidia,function = "rsvd4";
};
};
- state_i2cmux_idle: pinmux_i2cmux_idle {
+ state_i2cmux_pta: pinmux-i2cmux-pta {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
+
pta {
nvidia,pins = "pta";
- nvidia,function = "rsvd4";
+ nvidia,function = "i2c2";
};
};
};
@@ -417,7 +420,7 @@
vddio-supply = <&vdd_1v8_sys>;
device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
};
};
@@ -425,6 +428,10 @@
/* Docking station */
};
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
i2c@7000c000 {
clock-frequency = <400000>;
status = "okay";
@@ -512,45 +519,6 @@
status = "okay";
};
- i2cmux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-parent = <&{/i2c@7000c400}>;
-
- pinctrl-names = "ddc", "pta", "idle";
- pinctrl-0 = <&state_i2cmux_ddc>;
- pinctrl-1 = <&state_i2cmux_pta>;
- pinctrl-2 = <&state_i2cmux_idle>;
-
- hdmi_ddc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- panel_ddc: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- embedded-controller@58 {
- compatible = "acer,a500-iconia-ec", "ene,kb930";
- reg = <0x58>;
-
- system-power-controller;
-
- monitored-battery = <&bat1010>;
- power-supplies = <&mains>;
- };
- };
- };
-
- pwm: pwm@7000a000 {
- status = "okay";
- };
-
i2c@7000d000 {
clock-frequency = <100000>;
status = "okay";
@@ -729,396 +697,6 @@
core-supply = <&vdd_core>;
};
- usb@c5000000 {
- compatible = "nvidia,tegra20-udc";
- status = "okay";
- dr_mode = "peripheral";
- };
-
- usb-phy@c5000000 {
- status = "okay";
- dr_mode = "peripheral";
- nvidia,xcvr-setup-use-fuses;
- nvidia,xcvr-lsfslew = <2>;
- nvidia,xcvr-lsrslew = <2>;
- };
-
- usb@c5008000 {
- status = "okay";
- };
-
- usb-phy@c5008000 {
- status = "okay";
- nvidia,xcvr-setup-use-fuses;
- nvidia,xcvr-lsfslew = <2>;
- nvidia,xcvr-lsrslew = <2>;
- vbus-supply = <&vdd_5v0_sys>;
- };
-
- brcm_wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
-
- clocks = <&rtc_32k_wifi>;
- clock-names = "ext_clock";
-
- reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <300>;
- power-off-delay-us = <300>;
- };
-
- sdmmc1: mmc@c8000000 {
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
- assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
- assigned-clock-rates = <50000000>;
-
- max-frequency = <50000000>;
- keep-power-in-suspend;
- bus-width = <4>;
- non-removable;
-
- mmc-pwrseq = <&brcm_wifi_pwrseq>;
- vmmc-supply = <&vdd_3v3_sys>;
- vqmmc-supply = <&vdd_1v8_sys>;
-
- /* Azurewave AW-NH611 BCM4329 */
- wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- };
- };
-
- sdmmc3: mmc@c8000400 {
- status = "okay";
- bus-width = <4>;
- cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
- power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
- vmmc-supply = <&vdd_3v3_sys>;
- vqmmc-supply = <&vdd_3v3_sys>;
- };
-
- sdmmc4: mmc@c8000600 {
- status = "okay";
- bus-width = <8>;
- vmmc-supply = <&vcore_emmc>;
- vqmmc-supply = <&vdd_3v3_sys>;
- non-removable;
- };
-
- mains: ac-adapter-detect {
- compatible = "gpio-charger";
- charger-type = "mains";
- gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
-
- enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
- power-supply = <&vdd_3v3_sys>;
- pwms = <&pwm 2 41667>;
-
- brightness-levels = <7 255>;
- num-interpolated-steps = <248>;
- default-brightness-level = <20>;
- };
-
- bat1010: battery-2s1p {
- compatible = "simple-battery";
- charge-full-design-microamp-hours = <3260000>;
- energy-full-design-microwatt-hours = <24000000>;
- operating-range-celsius = <0 40>;
- };
-
- /* PMIC has a built-in 32KHz oscillator which is used by PMC */
- clk32k_in: clock-32k-in {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "tps658621-out32k";
- };
-
- /*
- * This standalone onboard fixed-clock always-ON 32KHz
- * oscillator is used as a reference clock-source by the
- * Azurewave WiFi/BT module.
- */
- rtc_32k_wifi: clock-32k-wifi {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "kk3270032";
- };
-
- cpus {
- cpu0: cpu@0 {
- cpu-supply = <&vdd_cpu>;
- operating-points-v2 = <&cpu0_opp_table>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- cpu-supply = <&vdd_cpu>;
- operating-points-v2 = <&cpu0_opp_table>;
- #cooling-cells = <2>;
- };
- };
-
- display-panel {
- compatible = "auo,b101ew05", "panel-lvds";
-
- ddc-i2c-bus = <&panel_ddc>;
- power-supply = <&vdd_pnl>;
- backlight = <&backlight>;
-
- width-mm = <218>;
- height-mm = <135>;
-
- data-mapping = "jeida-18";
-
- panel-timing {
- clock-frequency = <71200000>;
- hactive = <1280>;
- vactive = <800>;
- hfront-porch = <8>;
- hback-porch = <18>;
- hsync-len = <184>;
- vsync-len = <3>;
- vfront-porch = <4>;
- vback-porch = <8>;
- };
-
- port {
- panel_input: endpoint {
- remote-endpoint = <&lvds_encoder_output>;
- };
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- power {
- label = "Power";
- gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_POWER>;
- debounce-interval = <10>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
-
- rotation-lock {
- label = "Rotate-lock";
- gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
- linux,code = <SW_ROTATE_LOCK>;
- linux,input-type = <EV_SW>;
- debounce-interval = <10>;
- };
-
- volume-up {
- label = "Volume Up";
- gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <10>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
-
- volume-down {
- label = "Volume Down";
- gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <10>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
- };
-
- haptic-feedback {
- compatible = "gpio-vibrator";
- enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
- vcc-supply = <&vdd_3v3_sys>;
- };
-
- lvds-encoder {
- compatible = "ti,sn75lvds83", "lvds-encoder";
-
- powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
- power-supply = <&vdd_3v3_sys>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- lvds_encoder_input: endpoint {
- remote-endpoint = <&lcd_output>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lvds_encoder_output: endpoint {
- remote-endpoint = <&panel_input>;
- };
- };
- };
- };
-
- vdd_5v0_sys: regulator-5v0 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vdd_3v3_sys: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3_vs";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- vin-supply = <&vdd_5v0_sys>;
- };
-
- vdd_1v8_sys: regulator-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_1v8_vs";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- vin-supply = <&vdd_5v0_sys>;
- };
-
- vdd_pnl: regulator-panel {
- compatible = "regulator-fixed";
- regulator-name = "vdd_panel";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-enable-ramp-delay = <300000>;
- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
-
- sound {
- compatible = "nvidia,tegra-audio-wm8903-picasso",
- "nvidia,tegra-audio-wm8903";
- nvidia,model = "Acer Iconia Tab A500 WM8903";
-
- nvidia,audio-routing =
- "Headphone Jack", "HPOUTR",
- "Headphone Jack", "HPOUTL",
- "Int Spk", "LINEOUTL",
- "Int Spk", "LINEOUTR",
- "Mic Jack", "MICBIAS",
- "IN2L", "Mic Jack",
- "IN2R", "Mic Jack",
- "IN1L", "Int Mic",
- "IN1R", "Int Mic";
-
- nvidia,i2s-controller = <&tegra_i2s1>;
- nvidia,audio-codec = <&wm8903>;
-
- nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
- nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
- nvidia,headset;
-
- clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
- <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA20_CLK_CDEV1>;
- clock-names = "pll_a", "pll_a_out0", "mclk";
- };
-
- thermal-zones {
- /*
- * NCT1008 has two sensors:
- *
- * 0: internal that monitors ambient/skin temperature
- * 1: external that is connected to the CPU's diode
- *
- * Ideally we should use userspace thermal governor,
- * but it's a much more complex solution. The "skin"
- * zone is a simpler solution which prevents A500 from
- * getting too hot from a user's tactile perspective.
- * The CPU zone is intended to protect silicon from damage.
- */
-
- skin-thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- thermal-sensors = <&nct1008 0>;
-
- trips {
- trip0: skin-alert {
- /* start throttling at 60C */
- temperature = <60000>;
- hysteresis = <200>;
- type = "passive";
- };
-
- trip1: skin-crit {
- /* shut down at 70C */
- temperature = <70000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&trip0>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-
- cpu-thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- thermal-sensors = <&nct1008 1>;
-
- trips {
- trip2: cpu-alert {
- /* throttle at 85C until temperature drops to 84.8C */
- temperature = <85000>;
- hysteresis = <200>;
- type = "passive";
- };
-
- trip3: cpu-crit {
- /* shut down at 90C */
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map1 {
- trip = <&trip2>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
memory-controller@7000f400 {
nvidia,use-ram-code;
@@ -1514,9 +1092,434 @@
};
};
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-666000000;
- /delete-node/ opp-760000000;
+ usb@c5000000 {
+ compatible = "nvidia,tegra20-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5008000 {
+ status = "okay";
+ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ sdmmc1: mmc@c8000000 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+ assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
+ max-frequency = <50000000>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ non-removable;
+
+ mmc-pwrseq = <&brcm_wifi_pwrseq>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_1v8_sys>;
+
+ /* Azurewave AW-NH611 BCM4329 */
+ wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+ };
+
+ sdmmc3: mmc@c8000400 {
+ status = "okay";
+ bus-width = <4>;
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ };
+
+ sdmmc4: mmc@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ non-removable;
+ };
+
+ mains: ac-adapter-detect {
+ compatible = "gpio-charger";
+ charger-type = "mains";
+ gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_3v3_sys>;
+ pwms = <&pwm 2 41667>;
+
+ brightness-levels = <7 255>;
+ num-interpolated-steps = <248>;
+ default-brightness-level = <20>;
+ };
+
+ bat1010: battery-2s1p {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3260000>;
+ energy-full-design-microwatt-hours = <24000000>;
+ operating-range-celsius = <0 40>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k-in {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "tps658621-out32k";
+ };
+
+ /*
+ * This standalone onboard fixed-clock always-ON 32KHz
+ * oscillator is used as a reference clock-source by the
+ * Azurewave WiFi/BT module.
+ */
+ rtc_32k_wifi: clock-32k-wifi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "kk3270032";
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ display-panel {
+ compatible = "auo,b101ew05", "panel-lvds";
+
+ ddc-i2c-bus = <&panel_ddc>;
+ power-supply = <&vdd_pnl>;
+ backlight = <&backlight>;
+
+ width-mm = <218>;
+ height-mm = <135>;
+
+ data-mapping = "jeida-18";
+
+ panel-timing {
+ clock-frequency = <71200000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hfront-porch = <8>;
+ hback-porch = <18>;
+ hsync-len = <184>;
+ vsync-len = <3>;
+ vfront-porch = <4>;
+ vback-porch = <8>;
+ };
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&lvds_encoder_output>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-rotation-lock {
+ label = "Rotate-lock";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
+ linux,code = <SW_ROTATE_LOCK>;
+ linux,input-type = <EV_SW>;
+ debounce-interval = <10>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ haptic-feedback {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&vdd_3v3_sys>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ panel_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ embedded-controller@58 {
+ compatible = "acer,a500-iconia-ec", "ene,kb930";
+ reg = <0x58>;
+
+ system-power-controller;
+
+ monitored-battery = <&bat1010>;
+ power-supplies = <&mains>;
+ };
+ };
+ };
+
+ lvds-encoder {
+ compatible = "ti,sn75lvds83", "lvds-encoder";
+
+ powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+ power-supply = <&vdd_3v3_sys>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_encoder_input: endpoint {
+ remote-endpoint = <&lcd_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_encoder_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+
+ opp-table-emc {
+ /delete-node/ opp-666000000;
+ /delete-node/ opp-760000000;
+ };
+
+ vdd_5v0_sys: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_sys: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_vs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_1v8_sys: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8_vs";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_pnl: regulator-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <300000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8903-picasso",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Acer Iconia Tab A500 WM8903";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "LINEOUTL",
+ "Int Spk", "LINEOUTR",
+ "Mic Jack", "MICBIAS",
+ "IN2L", "Mic Jack",
+ "IN2R", "Mic Jack",
+ "IN1L", "Int Mic",
+ "IN1R", "Int Mic";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
+ nvidia,headset;
+
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+ };
+
+ thermal-zones {
+ /*
+ * NCT1008 has two sensors:
+ *
+ * 0: internal that monitors ambient/skin temperature
+ * 1: external that is connected to the CPU's diode
+ *
+ * Ideally we should use userspace thermal governor,
+ * but it's a much more complex solution. The "skin"
+ * zone is a simpler solution which prevents A500 from
+ * getting too hot from a user's tactile perspective.
+ * The CPU zone is intended to protect silicon from damage.
+ */
+
+ skin-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct1008 0>;
+
+ trips {
+ trip0: skin-alert {
+ /* start throttling at 60C */
+ temperature = <60000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip1: skin-crit {
+ /* shut down at 70C */
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct1008 1>;
+
+ trips {
+ trip2: cpu-alert {
+ /* throttle at 85C until temperature drops to 84.8C */
+ temperature = <85000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip3: cpu-crit {
+ /* shut down at 90C */
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&trip2>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ brcm_wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&rtc_32k_wifi>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
};
diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts
index a054d39db466..c2a9c3fb5b33 100644
--- a/arch/arm/boot/dts/tegra20-asus-tf101.dts
+++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts
@@ -399,7 +399,7 @@
};
};
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ state_i2cmux_ddc: pinmux-i2cmux-ddc {
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
@@ -411,7 +411,7 @@
};
};
- state_i2cmux_pta: pinmux_i2cmux_pta {
+ state_i2cmux_idle: pinmux-i2cmux-idle {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
@@ -419,11 +419,11 @@
pta {
nvidia,pins = "pta";
- nvidia,function = "i2c2";
+ nvidia,function = "rsvd4";
};
};
- state_i2cmux_idle: pinmux_i2cmux_idle {
+ state_i2cmux_pta: pinmux-i2cmux-pta {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
@@ -431,7 +431,7 @@
pta {
nvidia,pins = "pta";
- nvidia,function = "rsvd4";
+ nvidia,function = "i2c2";
};
};
};
@@ -477,7 +477,7 @@
vddio-supply = <&vdd_1v8_sys>;
device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
};
};
@@ -520,10 +520,10 @@
micdet-delay = <100>;
gpio-cfg = <
- 0xffffffff /* don't touch */
- 0xffffffff /* don't touch */
+ 0x00000600 /* DMIC_LR, output */
+ 0x00000680 /* DMIC_DAT, input */
0x00000000 /* Speaker-enable GPIO, output, low */
- 0x00000400 /* Mic bias current detect */
+ 0xffffffff /* don't touch */
0xffffffff /* don't touch */
>;
@@ -577,9 +577,9 @@
vdd-supply = <&vdd_1v8_sys>;
vddio-supply = <&vdd_1v8_sys>;
- mount-matrix = "1", "0", "0",
- "0", "1", "0",
- "0", "0", "1";
+ mount-matrix = "-1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
};
};
};
@@ -764,13 +764,6 @@
#address-cells = <1>;
#size-cells = <0>;
- lpddr2 {
- compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
- revision-id = <1 0>;
- density = <2048>;
- io-width = <16>;
- };
-
emc-table@25000 {
reg = <25000>;
compatible = "nvidia,tegra20-emc-table";
@@ -860,6 +853,13 @@
0x007e0010 0x00000000 0x00000000 0x0000001b
0x00000000 0x00000000 0x00000000 0x00000000>;
};
+
+ lpddr2 {
+ compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
+ revision-id = <1 0>;
+ density = <2048>;
+ io-width = <16>;
+ };
};
};
@@ -977,49 +977,8 @@
};
};
- gpio-keys {
- compatible = "gpio-keys";
-
- dock-hall-sensor {
- label = "Lid";
- gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_SW>;
- linux,code = <SW_LID>;
- debounce-interval = <500>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
-
- power {
- label = "Power";
- gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- debounce-interval = <10>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
-
- volume-up {
- label = "Volume Up";
- gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <10>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
-
- volume-down {
- label = "Volume Down";
- gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <10>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
- };
-
display-panel {
- compatible = "panel-lvds";
+ compatible = "auo,b101ew05", "panel-lvds";
/* AUO B101EW05 using custom timings */
@@ -1051,6 +1010,47 @@
};
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ switch-dock-hall-sensor {
+ label = "Lid";
+ gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <500>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
i2cmux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
@@ -1112,6 +1112,11 @@
};
};
+ opp-table-emc {
+ /delete-node/ opp-666000000;
+ /delete-node/ opp-760000000;
+ };
+
vdd_5v0_sys: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
@@ -1179,15 +1184,16 @@
"Int Spk", "RON",
"Int Spk", "LOP",
"Int Spk", "LON",
- "Mic Jack", "MICBIAS",
- "IN1L", "Mic Jack";
+ "IN2L", "Mic Jack",
+ "DMICDAT", "Int Mic";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
- nvidia,headset;
+ nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>;
+ nvidia,coupled-mic-hp-det;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
@@ -1283,8 +1289,3 @@
power-off-delay-us = <200>;
};
};
-
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-666000000;
- /delete-node/ opp-760000000;
-};
diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
index d2a3bf9d28bd..612f4e54cb20 100644
--- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
@@ -143,6 +143,24 @@
status = "okay";
};
+ /* SPI4: Colibri SSP */
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio>;
+ /* CAN_INT */
+ interrupts = <TEGRA_GPIO(A, 0) IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <&reg_3v3>;
+ xceiver-supply = <&reg_5v0>;
+ };
+ };
+
/* EHCI instance 0: USB1_DP/N -> USBC_P/N */
usb@c5000000 {
status = "okay";
@@ -164,24 +182,6 @@
vbus-supply = <&reg_usbh_vbus>;
};
- /* SPI4: Colibri SSP */
- spi@7000da00 {
- status = "okay";
- spi-max-frequency = <25000000>;
-
- can@0 {
- compatible = "microchip,mcp2515";
- reg = <0>;
- clocks = <&clk16m>;
- interrupt-parent = <&gpio>;
- /* CAN_INT */
- interrupts = <TEGRA_GPIO(A, 0) IRQ_TYPE_EDGE_FALLING>;
- spi-max-frequency = <10000000>;
- vdd-supply = <&reg_3v3>;
- xceiver-supply = <&reg_5v0>;
- };
- };
-
/* SD/MMC */
mmc@c8000600 {
status = "okay";
@@ -200,7 +200,7 @@
pwms = <&pwm 0 5000000>; /* PWM<A> */
};
- clk16m: osc3 {
+ clk16m: clock-osc3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
@@ -209,7 +209,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "SODIMM pin 45 wakeup";
gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 00ecbbd5e9e1..25a9f5dfe62d 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -143,6 +143,12 @@
status = "okay";
};
+ /* SPI4: Colibri SSP */
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
/* EHCI instance 0: USB1_DP/N -> USBC_P/N */
usb@c5000000 {
status = "okay";
@@ -164,12 +170,6 @@
vbus-supply = <&reg_usbh_vbus>;
};
- /* SPI4: Colibri SSP */
- spi@7000da00 {
- status = "okay";
- spi-max-frequency = <25000000>;
- };
-
/* SD/MMC */
mmc@c8000600 {
status = "okay";
@@ -191,7 +191,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "SODIMM pin 45 wakeup";
gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 8ebd8afc857d..0e03910abbe6 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -27,6 +27,31 @@
};
};
+ gpio@6000d000 {
+ lan-reset-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LAN_RESET#";
+ };
+
+ /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
+ npwe-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "Tri-state nPWE";
+ };
+
+ /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
+ rdnwr-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "Not tri-state RDnWR";
+ };
+ };
+
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@@ -705,12 +730,16 @@
vbus-supply = <&reg_lan_v_bus>;
};
- clk32k_in: xtal3 {
+ clk32k_in: clock-xtal3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
+ opp-table-emc {
+ /delete-node/ opp-760000000;
+ };
+
reg_lan_v_bus: regulator-lan-v-bus {
compatible = "regulator-fixed";
regulator-name = "LAN_V_BUS";
@@ -745,32 +774,3 @@
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
-
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-760000000;
-};
-
-&gpio {
- lan-reset-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "LAN_RESET#";
- };
-
- /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
- npwe-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "Tri-state nPWE";
- };
-
- /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
- rdnwr-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "Not tri-state RDnWR";
- };
-};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 79b6b79fab65..11f21aeba8e9 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -648,7 +648,7 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index f144487c5da3..8c657182fff3 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -15,10 +15,6 @@
stdout-path = "serial0:115200n8";
};
- pwm@7000a000 {
- status = "okay";
- };
-
host1x@50000000 {
dc@54200000 {
rgb {
@@ -28,6 +24,10 @@
};
};
+ pwm@7000a000 {
+ status = "okay";
+ };
+
i2c@7000c000 {
wm8903: wm8903@1a {
compatible = "wlf,wm8903";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 0fb4b1f5bc1c..e995f428dc2e 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -323,53 +323,6 @@
reset-names = "i2c";
};
- memory-controller@7000f400 {
- nvidia,use-ram-code;
-
- emc-tables@0 {
- nvidia,ram-code = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- emc-table@166500 {
- reg = <166500>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <166500>;
- nvidia,emc-registers = <0x0000000a 0x00000016
- 0x00000008 0x00000003 0x00000004 0x00000004
- 0x00000002 0x0000000c 0x00000003 0x00000003
- 0x00000002 0x00000001 0x00000004 0x00000005
- 0x00000004 0x00000009 0x0000000d 0x000004df
- 0x00000000 0x00000003 0x00000003 0x00000003
- 0x00000003 0x00000001 0x0000000a 0x000000c8
- 0x00000003 0x00000006 0x00000004 0x00000008
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0xe03b0323
- 0x007fe010 0x00001414 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
-
- emc-table@333000 {
- reg = <333000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = <333000>;
- nvidia,emc-registers = <0x00000018 0x00000033
- 0x00000012 0x00000004 0x00000004 0x00000005
- 0x00000003 0x0000000c 0x00000006 0x00000006
- 0x00000003 0x00000001 0x00000004 0x00000005
- 0x00000004 0x00000009 0x0000000d 0x00000bff
- 0x00000000 0x00000003 0x00000003 0x00000006
- 0x00000006 0x00000001 0x00000011 0x000000c8
- 0x00000003 0x0000000e 0x00000007 0x00000008
- 0x00000002 0x00000000 0x00000000 0x00000002
- 0x00000000 0x00000000 0x00000083 0xf0440303
- 0x007fe010 0x00001414 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000>;
- };
- };
- };
-
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
@@ -532,6 +485,53 @@
core-supply = <&core_vdd_reg>;
};
+ memory-controller@7000f400 {
+ nvidia,use-ram-code;
+
+ emc-tables@0 {
+ nvidia,ram-code = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ emc-table@166500 {
+ reg = <166500>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <166500>;
+ nvidia,emc-registers = <0x0000000a 0x00000016
+ 0x00000008 0x00000003 0x00000004 0x00000004
+ 0x00000002 0x0000000c 0x00000003 0x00000003
+ 0x00000002 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x000004df
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000003 0x00000001 0x0000000a 0x000000c8
+ 0x00000003 0x00000006 0x00000004 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xe03b0323
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000018 0x00000033
+ 0x00000012 0x00000004 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000bff
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xf0440303
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+ };
+
usb@c5000000 {
compatible = "nvidia,tegra20-udc";
status = "okay";
@@ -593,10 +593,24 @@
#clock-cells = <0>;
};
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&cpu_vdd_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ cpu-supply = <&cpu_vdd_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "Wakeup";
gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -614,6 +628,10 @@
};
};
+ opp-table-emc {
+ /delete-node/ opp-760000000;
+ };
+
panel: panel {
compatible = "samsung,ltn101nt05";
@@ -668,20 +686,6 @@
clock-names = "pll_a", "pll_a_out0", "mclk";
};
- cpus {
- cpu0: cpu@0 {
- cpu-supply = <&cpu_vdd_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- cpu-supply = <&cpu_vdd_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- #cooling-cells = <2>;
- };
- };
-
thermal-zones {
cpu-thermal {
polling-delay-passive = <500>; /* milliseconds */
@@ -715,7 +719,3 @@
};
};
};
-
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-760000000;
-};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index c4a6a6a94559..bd4ff8b40b20 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -285,7 +285,7 @@
};
};
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ state_i2cmux_ddc: pinmux-i2cmux-ddc {
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
@@ -296,25 +296,25 @@
};
};
- state_i2cmux_pta: pinmux_i2cmux_pta {
+ state_i2cmux_idle: pinmux-i2cmux-idle {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
- nvidia,function = "i2c2";
+ nvidia,function = "rsvd4";
};
};
- state_i2cmux_idle: pinmux_i2cmux_idle {
+ state_i2cmux_pta: pinmux-i2cmux-pta {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
- nvidia,function = "rsvd4";
+ nvidia,function = "i2c2";
};
};
};
@@ -370,38 +370,6 @@
clock-frequency = <100000>;
};
- i2cmux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-parent = <&{/i2c@7000c400}>;
-
- pinctrl-names = "ddc", "pta", "idle";
- pinctrl-0 = <&state_i2cmux_ddc>;
- pinctrl-1 = <&state_i2cmux_pta>;
- pinctrl-2 = <&state_i2cmux_idle>;
-
- hdmi_ddc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- lvds_ddc: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- smart-battery@b {
- compatible = "ti,bq20z75", "sbs,sbs-battery";
- reg = <0xb>;
- sbs,i2c-retry-count = <2>;
- sbs,poll-retry-count = <10>;
- };
- };
- };
-
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
@@ -800,14 +768,14 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
- lid {
+ switch-lid {
label = "Lid";
gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
linux,input-type = <5>; /* EV_SW */
@@ -817,6 +785,38 @@
};
};
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ lvds_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ smart-battery@b {
+ compatible = "ti,bq20z75", "sbs,sbs-battery";
+ reg = <0xb>;
+ sbs,i2c-retry-count = <2>;
+ sbs,poll-retry-count = <10>;
+ };
+ };
+ };
+
panel: panel {
compatible = "chunghwa,claa101wa01a";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 0e19bd0a847c..ddb84e4a9f8b 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -249,7 +249,7 @@
};
};
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ state_i2cmux_ddc: pinmux-i2cmux-ddc {
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
@@ -260,25 +260,25 @@
};
};
- state_i2cmux_pta: pinmux_i2cmux_pta {
+ state_i2cmux_idle: pinmux-i2cmux-idle {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
- nvidia,function = "i2c2";
+ nvidia,function = "rsvd4";
};
};
- state_i2cmux_idle: pinmux_i2cmux_idle {
+ state_i2cmux_pta: pinmux-i2cmux-pta {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
- nvidia,function = "rsvd4";
+ nvidia,function = "i2c2";
};
};
};
@@ -301,31 +301,6 @@
status = "okay";
};
- i2cmux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-parent = <&{/i2c@7000c400}>;
-
- pinctrl-names = "ddc", "pta", "idle";
- pinctrl-0 = <&state_i2cmux_ddc>;
- pinctrl-1 = <&state_i2cmux_pta>;
- pinctrl-2 = <&state_i2cmux_idle>;
-
- hdmi_ddc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
i2c@7000d000 {
clock-frequency = <400000>;
status = "okay";
@@ -509,6 +484,31 @@
#clock-cells = <0>;
};
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
pci_vdd_reg: regulator-1v05 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v05";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9d0c86711de2..1944121e2dd6 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -385,10 +385,20 @@
#clock-cells = <0>;
};
+ cpus {
+ cpu0: cpu@0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -462,14 +472,4 @@
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
-
- cpus {
- cpu0: cpu@0 {
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@1 {
- operating-points-v2 = <&cpu0_opp_table>;
- };
- };
};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index b0a00970b61c..433575a6ad38 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -284,7 +284,7 @@
};
};
- state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ state_i2cmux_ddc: pinmux-i2cmux-ddc {
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
@@ -295,25 +295,25 @@
};
};
- state_i2cmux_pta: pinmux_i2cmux_pta {
+ state_i2cmux_idle: pinmux-i2cmux-idle {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
- nvidia,function = "i2c2";
+ nvidia,function = "rsvd4";
};
};
- state_i2cmux_idle: pinmux_i2cmux_idle {
+ state_i2cmux_pta: pinmux-i2cmux-pta {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
- nvidia,function = "rsvd4";
+ nvidia,function = "i2c2";
};
};
};
@@ -362,31 +362,6 @@
clock-frequency = <100000>;
};
- i2cmux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-parent = <&{/i2c@7000c400}>;
-
- pinctrl-names = "ddc", "pta", "idle";
- pinctrl-0 = <&state_i2cmux_ddc>;
- pinctrl-1 = <&state_i2cmux_pta>;
- pinctrl-2 = <&state_i2cmux_idle>;
-
- hdmi_ddc: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- lvds_ddc: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
@@ -628,7 +603,7 @@
gpio-keys {
compatible = "gpio-keys";
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -636,6 +611,31 @@
};
};
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ lvds_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
panel: panel {
compatible = "chunghwa,claa101wa01a";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 62bf0b306472..4177d04265d8 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -356,12 +356,6 @@
operating-points-v2 = <&vde_dvfs_opp_table>;
};
- apbmisc@70000800 {
- compatible = "nvidia,tegra20-apbmisc";
- reg = <0x70000800 0x64>, /* Chip revision */
- <0x70000008 0x04>; /* Strapping options */
- };
-
pinmux: pinmux@70000014 {
compatible = "nvidia,tegra20-pinmux";
reg = <0x70000014 0x10>, /* Tri-state registers */
@@ -370,6 +364,12 @@
<0x70000868 0xa8>; /* Pad control registers */
};
+ apbmisc@70000800 {
+ compatible = "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64>, /* Chip revision */
+ <0x70000008 0x04>; /* Strapping options */
+ };
+
das@70000c00 {
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
@@ -542,13 +542,6 @@
status = "disabled";
};
- rtc@7000e000 {
- compatible = "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA20_CLK_RTC>;
- };
-
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
@@ -683,6 +676,13 @@
status = "disabled";
};
+ rtc@7000e000 {
+ compatible = "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA20_CLK_RTC>;
+ };
+
kbc@7000e200 {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
@@ -706,6 +706,16 @@
};
powergates {
+ pd_mpe: mpe {
+ clocks = <&tegra_car TEGRA20_CLK_MPE>;
+ resets = <&mc TEGRA20_MC_RESET_MPEA>,
+ <&mc TEGRA20_MC_RESET_MPEB>,
+ <&mc TEGRA20_MC_RESET_MPEC>,
+ <&tegra_car TEGRA20_CLK_MPE>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
pd_3d: td {
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&mc TEGRA20_MC_RESET_3D>,
@@ -714,6 +724,14 @@
#power-domain-cells = <0>;
};
+ pd_vde: vdec {
+ clocks = <&tegra_car TEGRA20_CLK_VDE>;
+ resets = <&mc TEGRA20_MC_RESET_VDE>,
+ <&tegra_car TEGRA20_CLK_VDE>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
pd_venc: venc {
clocks = <&tegra_car TEGRA20_CLK_ISP>,
<&tegra_car TEGRA20_CLK_VI>,
@@ -726,24 +744,6 @@
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
-
- pd_vde: vdec {
- clocks = <&tegra_car TEGRA20_CLK_VDE>;
- resets = <&mc TEGRA20_MC_RESET_VDE>,
- <&tegra_car TEGRA20_CLK_VDE>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_mpe: mpe {
- clocks = <&tegra_car TEGRA20_CLK_MPE>;
- resets = <&mc TEGRA20_MC_RESET_MPEA>,
- <&mc TEGRA20_MC_RESET_MPEB>,
- <&mc TEGRA20_MC_RESET_MPEC>,
- <&tegra_car TEGRA20_CLK_MPE>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
};
};
@@ -1049,13 +1049,13 @@
simple-audio-card,dai-link@0 {
reg = <0>;
- cpu {
- sound-dai = <&tegra_spdif>;
- };
-
codec {
sound-dai = <&tegra_hdmi>;
};
+
+ cpu {
+ sound-dai = <&tegra_spdif>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 93b83b3c5655..842b5faba285 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -47,6 +47,16 @@
};
};
+ gpio@6000d000 {
+ /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+ pex-perst-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PEX_PERST_N";
+ };
+ };
+
/* Apalis UART1 */
serial@70006000 {
status = "okay";
@@ -181,7 +191,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "WAKE1_MICO";
gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -236,13 +246,3 @@
vin-supply = <&reg_5v0>;
};
};
-
-&gpio {
- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "PEX_PERST_N";
- };
-};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
index fbfa75e53f32..ca277bf1df78 100644
--- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
@@ -48,6 +48,16 @@
};
};
+ gpio@6000d000 {
+ /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+ pex-perst-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PEX_PERST_N";
+ };
+ };
+
/* Apalis UART1 */
serial@70006000 {
status = "okay";
@@ -182,7 +192,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "WAKE1_MICO";
gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
@@ -254,13 +264,3 @@
vin-supply = <&vddio_sdmmc_1v8_reg>;
};
};
-
-&gpio {
- /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "PEX_PERST_N";
- };
-};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
index 380f22a35821..a4b7fe5c3d23 100644
--- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
@@ -993,7 +993,7 @@
touchscreen@41 {
compatible = "st,stmpe811";
reg = <0x41>;
- irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
+ irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
interrupt-controller;
id = <0>;
blocks = <0x5>;
@@ -1007,6 +1007,12 @@
/* ADC converstion time: 80 clocks */
st,sample-time = <4>;
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ /* forbid to use ADC channels 3-0 (touch) */
+ st,norequest-mask = <0x0F>;
+ };
+
stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
@@ -1023,12 +1029,6 @@
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- /* forbid to use ADC channels 3-0 (touch) */
- st,norequest-mask = <0x0F>;
- };
};
/*
@@ -1122,16 +1122,16 @@
mmc-ddr-1_8v;
};
- clk32k_in: xtal1 {
+ clk16m: clock-osc4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <32768>;
+ clock-frequency = <16000000>;
};
- clk16m: osc4 {
+ clk32k_in: clock-xtal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <16000000>;
+ clock-frequency = <32768>;
};
reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 9bdc4cb71449..d73103884000 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -976,7 +976,7 @@
touchscreen@41 {
compatible = "st,stmpe811";
reg = <0x41>;
- irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
+ irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
interrupt-controller;
id = <0>;
blocks = <0x5>;
@@ -990,6 +990,12 @@
/* ADC converstion time: 80 clocks */
st,sample-time = <4>;
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ /* forbid to use ADC channels 3-0 (touch) */
+ st,norequest-mask = <0x0F>;
+ };
+
stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
@@ -1006,12 +1012,6 @@
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- /* forbid to use ADC channels 3-0 (touch) */
- st,norequest-mask = <0x0F>;
- };
};
/*
@@ -1105,16 +1105,16 @@
mmc-ddr-1_8v;
};
- clk32k_in: xtal1 {
+ clk16m: clock-osc4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <32768>;
+ clock-frequency = <16000000>;
};
- clk16m: osc4 {
+ clk32k_in: clock-xtal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <16000000>;
+ clock-frequency = <32768>;
};
reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi
index a047abfa6369..bae09d82594d 100644
--- a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi
@@ -2,6 +2,8 @@
/* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */
+#include <dt-bindings/gpio/tegra-gpio.h>
+
/ {
host1x@50000000 {
lcd: dc@54200000 {
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 2c2ad2a38f04..c0062353c1f1 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -29,6 +29,14 @@
*/
chosen {};
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <0x0>;
+ tlm,version-minor = <0x0>;
+ };
+ };
+
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@@ -61,19 +69,19 @@
};
gpio@6000d000 {
+ init-low-power-mode-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+
init-mode-hog {
gpio-hog;
- gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
+ gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
output-low;
};
-
- init-low-power-mode-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
- input;
- };
};
pinmux@70000868 {
@@ -820,7 +828,7 @@
vddio-supply = <&vdd_1v8>;
device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
- shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
};
};
@@ -833,7 +841,7 @@
status = "okay";
touchscreen@10 {
- compatible ="elan,ektf3624";
+ compatible = "elan,ektf3624";
reg = <0x10>;
interrupt-parent = <&gpio>;
@@ -977,17 +985,6 @@
};
};
- brcm_wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
-
- clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
- clock-names = "ext_clock";
-
- reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <300>;
- power-off-delay-us = <300>;
- };
-
sdmmc3: mmc@78000400 {
status = "okay";
@@ -1113,28 +1110,10 @@
/delete-property/ ddc-i2c-bus;
};
- firmware {
- trusted-foundations {
- compatible = "tlm,trusted-foundations";
- tlm,version-major = <0x0>;
- tlm,version-minor = <0x0>;
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
- hall-sensor {
- label = "Lid";
- gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_SW>;
- linux,code = <SW_LID>;
- debounce-interval = <500>;
- wakeup-event-action = <EV_ACT_DEASSERTED>;
- wakeup-source;
- };
-
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -1143,7 +1122,16 @@
wakeup-source;
};
- volume-up {
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
@@ -1152,16 +1140,28 @@
wakeup-source;
};
- volume-down {
- label = "Volume Down";
- gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <10>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
+ switch-hall-sensor {
+ label = "Lid";
+ gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <500>;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
wakeup-source;
};
};
+ brcm_wifi_pwrseq: pwrseq-wifi {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
vdd_5v0_sys: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
index cd28e8782f7d..694c7fe37eb8 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
@@ -22,13 +22,6 @@
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
- max77620_default: pinmux {
- gpio4 {
- pins = "gpio4";
- function = "32k-out1";
- };
- };
-
cpu-pwr-req-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
@@ -49,6 +42,13 @@
};
};
+ max77620_default: pinmux {
+ gpio4 {
+ pins = "gpio4";
+ function = "32k-out1";
+ };
+ };
+
regulators {
in-sd0-supply = <&vdd_5v0_sys>;
in-sd1-supply = <&vdd_5v0_sys>;
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi
index 6c229e1d67e7..8944a4a5a8d7 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi
@@ -1562,16 +1562,16 @@
};
};
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-750000000-1300;
- /delete-node/ opp-800000000-1300;
- /delete-node/ opp-900000000-1350;
-};
+ opp-table-actmon {
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+ };
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-750000000;
- /delete-node/ opp-800000000;
- /delete-node/ opp-900000000;
+ opp-table-emc {
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
index 564cfcde21a9..c19a0419112a 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
@@ -6,20 +6,6 @@
/ {
compatible = "asus,grouper", "nvidia,tegra30";
- display-panel {
- panel-timing {
- clock-frequency = <68000000>;
- hactive = <800>;
- vactive = <1280>;
- hfront-porch = <24>;
- hback-porch = <32>;
- hsync-len = <24>;
- vsync-len = <1>;
- vfront-porch = <5>;
- vback-porch = <32>;
- };
- };
-
pinmux@70000868 {
state_default: pinmux {
lcd_dc1_pd2 {
@@ -145,4 +131,18 @@
firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
};
};
+
+ display-panel {
+ panel-timing {
+ clock-frequency = <68000000>;
+ hactive = <800>;
+ vactive = <1280>;
+ hfront-porch = <24>;
+ hback-porch = <32>;
+ hsync-len = <24>;
+ vsync-len = <1>;
+ vfront-porch = <5>;
+ vback-porch = <32>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
index cd63e0ef7445..94c80134574e 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
@@ -6,26 +6,10 @@
/ {
compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30";
- display-panel {
- enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>;
-
- panel-timing {
- clock-frequency = <81750000>;
- hactive = <800>;
- vactive = <1280>;
- hfront-porch = <64>;
- hback-porch = <128>;
- hsync-len = <64>;
- vsync-len = <1>;
- vfront-porch = <5>;
- vback-porch = <2>;
- };
- };
-
gpio@6000d000 {
init-mode-3g-hog {
gpio-hog;
- gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>,
+ gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
@@ -230,4 +214,20 @@
firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
};
};
+
+ display-panel {
+ enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>;
+
+ panel-timing {
+ clock-frequency = <81750000>;
+ hactive = <800>;
+ vactive = <1280>;
+ hfront-porch = <64>;
+ hback-porch = <128>;
+ hsync-len = <64>;
+ vsync-len = <1>;
+ vfront-porch = <5>;
+ vback-porch = <2>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts
index 315c6dc068c5..0406c5a69c12 100644
--- a/arch/arm/boot/dts/tegra30-asus-tf201.dts
+++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts
@@ -605,23 +605,40 @@
enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
vcc-supply = <&vdd_3v3_sys>;
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-533000000-1200;
- /delete-node/ opp-625000000-1200;
- /delete-node/ opp-625000000-1250;
- /delete-node/ opp-667000000-1200;
- /delete-node/ opp-750000000-1300;
- /delete-node/ opp-800000000-1300;
- /delete-node/ opp-900000000-1350;
-};
+ opp-table-actmon {
+ /delete-node/ opp-533000000;
+ /delete-node/ opp-625000000;
+ /delete-node/ opp-667000000;
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+ };
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-533000000;
- /delete-node/ opp-625000000;
- /delete-node/ opp-667000000;
- /delete-node/ opp-750000000;
- /delete-node/ opp-800000000;
- /delete-node/ opp-900000000;
+ opp-table-emc {
+ /delete-node/ opp-533000000-1200;
+ /delete-node/ opp-625000000-1200;
+ /delete-node/ opp-625000000-1250;
+ /delete-node/ opp-667000000-1200;
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+ };
+
+ sound {
+ compatible = "asus,tegra-audio-rt5631-tf201",
+ "nvidia,tegra-audio-rt5631";
+ nvidia,model = "Asus Transformer Prime TF201 RT5631";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR",
+ "Int Spk", "SPOL",
+ "Int Spk", "SPOR",
+ "MIC1", "MIC Bias1",
+ "MIC Bias1", "Mic Jack",
+ "DMIC", "Int Mic";
+
+ nvidia,audio-codec = <&rt5631>;
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts
index f47434871a5c..970a1f08dc8c 100644
--- a/arch/arm/boot/dts/tegra30-asus-tf300t.dts
+++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts
@@ -128,8 +128,8 @@
micdet-delay = <100>;
gpio-cfg = <
- 0xffffffff /* don't touch */
- 0xffffffff /* don't touch */
+ 0x00000600 /* DMIC_LR, output */
+ 0x00000680 /* DMIC_DAT, input */
0x00000000 /* Speaker-enable GPIO, output, low */
0xffffffff /* don't touch */
0xffffffff /* don't touch */
@@ -999,6 +999,18 @@
compatible = "innolux,g101ice-l01";
};
+ opp-table-emc {
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+ };
+
+ opp-table-actmon {
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+ };
+
sound {
compatible = "asus,tegra-audio-wm8903-tf300t",
"nvidia,tegra-audio-wm8903";
@@ -1011,24 +1023,10 @@
"Int Spk", "RON",
"Int Spk", "LOP",
"Int Spk", "LON",
- "IN1L", "Mic Jack",
"IN2L", "Mic Jack",
"DMICDAT", "Int Mic";
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,headset;
};
};
-
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-750000000-1300;
- /delete-node/ opp-800000000-1300;
- /delete-node/ opp-900000000-1350;
-};
-
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-750000000;
- /delete-node/ opp-800000000;
- /delete-node/ opp-900000000;
-};
diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts
index 96345f821c3d..4861db8e1e59 100644
--- a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts
+++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts
@@ -1072,16 +1072,33 @@
display-panel {
compatible = "innolux,g101ice-l01";
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-750000000-1300;
- /delete-node/ opp-800000000-1300;
- /delete-node/ opp-900000000-1350;
-};
+ opp-table-emc {
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+ };
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-750000000;
- /delete-node/ opp-800000000;
- /delete-node/ opp-900000000;
+ opp-table-actmon {
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+ };
+
+ sound {
+ compatible = "asus,tegra-audio-rt5631-tf300tg",
+ "nvidia,tegra-audio-rt5631";
+ nvidia,model = "Asus Transformer Pad TF300TG RT5631";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR",
+ "Int Spk", "SPOL",
+ "Int Spk", "SPOR",
+ "MIC1", "MIC Bias1",
+ "MIC Bias1", "Mic Jack",
+ "DMIC", "Int Mic";
+
+ nvidia,audio-codec = <&rt5631>;
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts
index 1a331dec3cfe..efde7dad718a 100644
--- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts
+++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts
@@ -758,6 +758,24 @@
vddio-supply = <&vdd_1v8_vio>;
vddmipi-supply = <&vdd_1v2_mipi>;
+ /*
+ * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
+ * LCD SuperIPS+ Full HD panel.
+ */
+ panel@1 {
+ compatible = "panasonic,vvx10f004b00";
+ reg = <1>;
+
+ power-supply = <&vdd_pnl>;
+ backlight = <&backlight>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -779,28 +797,18 @@
};
};
};
-
- /*
- * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
- * LCD SuperIPS+ Full HD panel.
- */
- panel@1 {
- compatible = "panasonic,vvx10f004b00";
- reg = <1>;
-
- power-supply = <&vdd_pnl>;
- backlight = <&backlight>;
-
- port {
- panel_input: endpoint {
- remote-endpoint = <&bridge_output>;
- };
- };
- };
};
};
};
+ opp-table-actmon {
+ /delete-node/ opp-900000000;
+ };
+
+ opp-table-emc {
+ /delete-node/ opp-900000000-1350;
+ };
+
vdd_1v2_mipi: regulator-mipi {
compatible = "regulator-fixed";
regulator-name = "tc358768_1v2_vdd";
@@ -812,12 +820,21 @@
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
-};
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-900000000-1350;
-};
-
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-900000000;
+ sound {
+ compatible = "asus,tegra-audio-rt5631-tf700t",
+ "nvidia,tegra-audio-rt5631";
+ nvidia,model = "Asus Transformer Infinity TF700T RT5631";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR",
+ "Int Spk", "SPOL",
+ "Int Spk", "SPOR",
+ "MIC1", "MIC Bias1",
+ "MIC Bias1", "Mic Jack",
+ "DMIC", "Int Mic";
+
+ nvidia,audio-codec = <&rt5631>;
+ };
};
diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi
index c662ab261ed5..bdb898ad6262 100644
--- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi
@@ -33,6 +33,14 @@
*/
chosen {};
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <2>;
+ tlm,version-minor = <8>;
+ };
+ };
+
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@@ -168,7 +176,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
/* SDMMC3 pinmux */
@@ -550,7 +558,7 @@
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- spi2_cs1_n_pw2 {
+ hp_detect {
nvidia,pins = "spi2_cs1_n_pw2";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -558,10 +566,10 @@
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
- spi2_sck_px2 {
+ mic_detect {
nvidia,pins = "spi2_sck_px2";
nvidia,function = "spi2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
@@ -711,7 +719,7 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
/* GPIO keys pinmux */
@@ -805,7 +813,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
vi_d10_pt2 {
@@ -937,7 +945,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
vi_mclk_pt1 {
@@ -1187,17 +1195,6 @@
status = "okay";
clock-frequency = <400000>;
- nct72: temperature-sensor@4c {
- compatible = "onnn,nct1008";
- reg = <0x4c>;
-
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
-
- vcc-supply = <&vdd_3v3_sys>;
- #thermal-sensor-cells = <1>;
- };
-
/* Texas Instruments TPS659110 PMIC */
pmic: pmic@2d {
compatible = "ti,tps65911";
@@ -1323,6 +1320,17 @@
};
};
+ nct72: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
+
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+
vdd_core: core-regulator@60 {
compatible = "ti,tps62361";
reg = <0x60>;
@@ -1509,9 +1517,8 @@
extcon-keys {
compatible = "gpio-keys";
- interrupt-parent = <&gpio>;
- dock-hall-sensor {
+ switch-dock-hall-sensor {
label = "Lid sensor";
gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
@@ -1521,7 +1528,7 @@
wakeup-source;
};
- lineout-detect {
+ switch-lineout-detect {
label = "Audio dock line-out detect";
gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
@@ -1532,19 +1539,10 @@
};
};
- firmware {
- trusted-foundations {
- compatible = "tlm,trusted-foundations";
- tlm,version-major = <2>;
- tlm,version-minor = <8>;
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
- interrupt-parent = <&gpio>;
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -1553,19 +1551,19 @@
wakeup-source;
};
- volume-up {
- label = "Volume Up";
- gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <10>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
- volume-down {
- label = "Volume Down";
- gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
debounce-interval = <10>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
@@ -1676,7 +1674,8 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
- nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
+ nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
+ nvidia,coupled-mic-hp-det;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 5ad62b567d32..51769d5132ae 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1974,6 +1974,28 @@
#clock-cells = <0>;
};
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@2 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@3 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
gpio-leds {
compatible = "gpio-leds";
@@ -2113,26 +2135,4 @@
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA30_CLK_EXTERN1>;
};
-
- cpus {
- cpu0: cpu@0 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@1 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@2 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
-
- cpu@3 {
- cpu-supply = <&vddctrl_reg>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
- };
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index ba257ed36d9c..37a9c5a0ca30 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -468,6 +468,33 @@
};
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ interrupt-parent = <&pmic>;
+ interrupts = <2 0>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <100>;
+ wakeup-source;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ };
+ };
+
panel: panel {
compatible = "chunghwa,claa101wb01";
ddc-i2c-bus = <&panelddc>;
@@ -681,31 +708,4 @@
};
};
};
-
- gpio-keys {
- compatible = "gpio-keys";
-
- power {
- label = "Power";
- interrupt-parent = <&pmic>;
- interrupts = <2 0>;
- linux,code = <KEY_POWER>;
- debounce-interval = <100>;
- wakeup-source;
- };
-
- volume-down {
- label = "Volume Down";
- gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <10>;
- };
-
- volume-up {
- label = "Volume Up";
- gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <10>;
- };
- };
};
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 7d4a6ca4936a..36615c5fda2c 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -136,7 +136,7 @@
pwms = <&pwm 0 5000000>; /* PWM<A> */
};
- clk16m: osc3 {
+ clk16m: clock-osc3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
@@ -145,7 +145,7 @@
gpio-keys {
compatible = "gpio-keys";
- wakeup {
+ key-wakeup {
label = "SODIMM pin 45 wakeup";
gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 22231d450b1b..ed6106f1bea1 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -20,6 +20,15 @@
};
};
+ gpio: gpio@6000d000 {
+ lan-reset-n-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LAN_RESET#";
+ };
+ };
+
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@@ -239,7 +248,7 @@
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
spdif-in-pk6 {
- nvidia,pins = "spdif_in_pk6";
+ nvidia,pins = "spdif_in_pk6";
nvidia,function = "hda";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -364,7 +373,7 @@
};
/* Multiplexed and therefore disabled */
cam-mclk-pcc0 {
- nvidia,pins = "cam_mclk_pcc0";
+ nvidia,pins = "cam_mclk_pcc0";
nvidia,function = "vi_alt3";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
@@ -511,7 +520,7 @@
/* Colibri USBC_DET */
spdif-out-pk5 {
- nvidia,pins = "spdif_out_pk5";
+ nvidia,pins = "spdif_out_pk5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -849,7 +858,7 @@
touchscreen@41 {
compatible = "st,stmpe811";
reg = <0x41>;
- irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
+ irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
interrupt-controller;
id = <0>;
blocks = <0x5>;
@@ -864,6 +873,11 @@
st,sample-time = <4>;
/* forbid to use ADC channels 3-0 (touch) */
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x0F>;
+ };
+
stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
@@ -880,11 +894,6 @@
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- st,norequest-mask = <0x0F>;
- };
};
/*
@@ -972,7 +981,7 @@
vbus-supply = <&reg_lan_v_bus>;
};
- clk32k_in: xtal1 {
+ clk32k_in: clock-xtal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -1053,12 +1062,3 @@
<&tegra_car TEGRA30_CLK_EXTERN1>;
};
};
-
-&gpio {
- lan-reset-n-hog {
- gpio-hog;
- gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "LAN_RESET#";
- };
-};
diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts
index e58dda4f9d2c..eef27c82987b 100644
--- a/arch/arm/boot/dts/tegra30-ouya.dts
+++ b/arch/arm/boot/dts/tegra30-ouya.dts
@@ -26,6 +26,14 @@
stdout-path = "serial0:115200n8";
};
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <0x0>;
+ tlm,version-minor = <0x0>;
+ };
+ };
+
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@@ -2037,17 +2045,6 @@
status = "okay";
clock-frequency = <400000>;
- cpu_temp: nct1008@4c {
- compatible = "onnn,nct1008";
- reg = <0x4c>;
- vcc-supply = <&sys_3v3_reg>;
-
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
-
- #thermal-sensor-cells = <1>;
- };
-
pmic: pmic@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
@@ -2161,6 +2158,17 @@
};
};
+ cpu_temp: nct1008@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+ vcc-supply = <&sys_3v3_reg>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
vdd_core: tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
@@ -4485,17 +4493,6 @@
status = "okay";
};
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
-
- clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
- clock-names = "ext_clock";
-
- reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <300>;
- power-off-delay-us = <300>;
- };
-
sdmmc3: mmc@78000400 {
status = "okay";
@@ -4608,15 +4605,7 @@
};
};
- firmware {
- trusted-foundations {
- compatible = "tlm,trusted-foundations";
- tlm,version-major = <0x0>;
- tlm,version-minor = <0x0>;
- };
- };
-
- fan: gpio_fan {
+ fan: fan {
compatible = "gpio-fan";
gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0
@@ -4624,50 +4613,50 @@
#cooling-cells = <2>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay = <5000>;
- polling-delay-passive = <5000>;
+ gpio-keys {
+ compatible = "gpio-keys";
- thermal-sensors = <&cpu_temp 1>;
+ key-power {
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ debounce-interval = <10>;
+ linux,code = <KEY_POWER>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
- trips {
- cpu_alert0: cpu-alert0 {
- temperature = <50000>;
- hysteresis = <10000>;
- type = "active";
- };
- cpu_alert1: cpu-alert1 {
- temperature = <70000>;
- hysteresis = <5000>;
- type = "passive";
- };
- cpu_crit: cpu-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
+ leds {
+ compatible = "gpio-leds";
- cooling-maps {
- map0 {
- trip = <&cpu_alert0>;
- cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu_alert1>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&actmon THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
+ led-power {
+ label = "power-led";
+ gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ retain-state-suspended;
};
};
- vdd_12v_in: vdd_12v_in {
+ opp-table-actmon {
+ /delete-node/ opp-900000000;
+ };
+
+ opp-table-emc {
+ /delete-node/ opp-900000000-1350;
+ };
+
+ wifi_pwrseq: pwrseq-wifi {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
+ vdd_12v_in: regulator-vdd-12v-in {
compatible = "regulator-fixed";
regulator-name = "vdd_12v_in";
regulator-min-microvolt = <12000000>;
@@ -4675,7 +4664,7 @@
regulator-always-on;
};
- sdmmc_3v3_reg: sdmmc_3v3_reg {
+ sdmmc_3v3_reg: regulator-sdmmc-3v3 {
compatible = "regulator-fixed";
regulator-name = "sdmmc_3v3";
regulator-min-microvolt = <3300000>;
@@ -4686,7 +4675,7 @@
vin-supply = <&sys_3v3_reg>;
};
- vdd_fuse_3v3_reg: vdd_fuse_3v3_reg {
+ vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_fuse_3v3";
regulator-min-microvolt = <3300000>;
@@ -4697,7 +4686,7 @@
regulator-always-on;
};
- vdd_vid_reg: vdd_vid_reg {
+ vdd_vid_reg: regulator-vdd-vid {
compatible = "regulator-fixed";
regulator-name = "vddio_vid";
regulator-min-microvolt = <5000000>;
@@ -4708,7 +4697,7 @@
regulator-boot-on;
};
- ddr_reg: ddr_reg {
+ ddr_reg: regulator-ddr {
compatible = "regulator-fixed";
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1500000>;
@@ -4720,7 +4709,7 @@
vin-supply = <&vdd_12v_in>;
};
- sys_3v3_reg: sys_3v3_reg {
+ sys_3v3_reg: regulator-sys-3v3 {
compatible = "regulator-fixed";
regulator-name = "sys_3v3";
regulator-min-microvolt = <3300000>;
@@ -4732,7 +4721,7 @@
vin-supply = <&vdd_12v_in>;
};
- vdd_5v0_reg: vdd_5v0_reg {
+ vdd_5v0_reg: regulator-vdd-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdd_5v0";
regulator-min-microvolt = <5000000>;
@@ -4744,14 +4733,14 @@
vin-supply = <&vdd_12v_in>;
};
- vdd_smsc: vdd_smsc {
+ vdd_smsc: regulator-vdd-smsc {
compatible = "regulator-fixed";
regulator-name = "vdd_smsc";
enable-active-high;
gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
};
- usb3_vbus_reg: usb3_vbus_reg {
+ usb3_vbus_reg: regulator-usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
@@ -4761,36 +4750,46 @@
vin-supply = <&vdd_5v0_reg>;
};
- gpio-keys {
- compatible = "gpio-keys";
-
- power {
- gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
- debounce-interval = <10>;
- linux,code = <KEY_POWER>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
- };
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay = <5000>;
+ polling-delay-passive = <5000>;
+ thermal-sensors = <&cpu_temp 1>;
- leds {
- compatible = "gpio-leds";
+ trips {
+ cpu_alert0: cpu-alert0 {
+ temperature = <50000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+ cpu_alert1: cpu-alert1 {
+ temperature = <70000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
- led-power {
- label = "power-led";
- gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- retain-state-suspended;
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
-
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-900000000-1350;
-};
-
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-900000000;
-};
diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts
index 8ce61035290b..8d10eb8b48b9 100644
--- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts
+++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts
@@ -37,6 +37,14 @@
*/
chosen {};
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <2>;
+ tlm,version-minor = <8>;
+ };
+ };
+
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@@ -134,7 +142,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
/* SDMMC3 pinmux */
@@ -150,7 +158,6 @@
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat3_pb4",
"sdmmc3_dat2_pb5",
- "sdmmc3_dat2_pb5",
"sdmmc3_dat1_pb6",
"sdmmc3_dat0_pb7",
"sdmmc3_dat5_pd0",
@@ -622,7 +629,7 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
pu1 {
@@ -689,7 +696,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
vi_d10_pt2 {
@@ -864,7 +871,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <0>;
- nvidia,ioreset = <0>;
+ nvidia,io-reset = <0>;
};
vi_mclk_pt1 {
@@ -1191,16 +1198,6 @@
status = "okay";
clock-frequency = <400000>;
- light-sensor@44 {
- compatible = "isil,isl29023";
- reg = <0x44>;
-
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>;
-
- vcc-supply = <&vdd_3v3_sen>;
- };
-
/* AsahiKASEI AK8975 magnetometer sensor */
magnetometer@c {
compatible = "asahi-kasei,ak8975";
@@ -1214,6 +1211,16 @@
"0", "0", "-1";
};
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+ vcc-supply = <&vdd_3v3_sen>;
+ };
+
gyroscope@68 {
compatible = "invensense,mpu3050";
reg = <0x68>;
@@ -1260,17 +1267,6 @@
status = "okay";
clock-frequency = <400000>;
- nct72: temperature-sensor@4c {
- compatible = "onnn,nct1008";
- reg = <0x4c>;
-
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>;
-
- vcc-supply = <&vdd_3v3_sys>;
- #thermal-sensor-cells = <1>;
- };
-
/* Texas Instruments TPS659110 PMIC */
pmic: pmic@2d {
compatible = "ti,tps65911";
@@ -1401,6 +1397,17 @@
};
};
+ nct72: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>;
+
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+
vdd_core: core-regulator@60 {
compatible = "ti,tps62361";
reg = <0x60>;
@@ -2507,17 +2514,6 @@
vqmmc-supply = <&vddio_usd>; /* ldo3 */
};
- brcm_wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
-
- clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
- clock-names = "ext_clock";
-
- reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
- post-power-on-delay-ms = <300>;
- power-off-delay-us = <300>;
- };
-
sdmmc3: mmc@78000400 {
status = "okay";
@@ -2653,9 +2649,8 @@
extcon-keys {
compatible = "gpio-keys";
- interrupt-parent = <&gpio>;
- dock-insert {
+ switch-dock-insert {
label = "Chagall Dock";
gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
@@ -2665,7 +2660,7 @@
wakeup-source;
};
- lineout-detect {
+ switch-lineout-detect {
label = "Audio dock line-out detect";
gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
@@ -2676,19 +2671,10 @@
};
};
- firmware {
- trusted-foundations {
- compatible = "tlm,trusted-foundations";
- tlm,version-major = <2>;
- tlm,version-minor = <8>;
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
- interrupt-parent = <&gpio>;
- power {
+ key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -2697,19 +2683,19 @@
wakeup-source;
};
- volume-up {
- label = "Volume Up";
- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <10>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
- volume-down {
- label = "Volume Down";
- gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
debounce-interval = <10>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
@@ -2722,6 +2708,34 @@
vcc-supply = <&vdd_3v3_sys>;
};
+ opp-table-actmon {
+ /delete-node/ opp-625000000;
+ /delete-node/ opp-667000000;
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-800000000;
+ /delete-node/ opp-900000000;
+ };
+
+ opp-table-emc {
+ /delete-node/ opp-625000000-1200;
+ /delete-node/ opp-625000000-1250;
+ /delete-node/ opp-667000000-1200;
+ /delete-node/ opp-750000000-1300;
+ /delete-node/ opp-800000000-1300;
+ /delete-node/ opp-900000000-1350;
+ };
+
+ brcm_wifi_pwrseq: pwrseq-wifi {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
sound {
compatible = "pegatron,tegra-audio-wm8903-chagall",
"nvidia,tegra-audio-wm8903";
@@ -2842,20 +2856,3 @@
};
};
};
-
-&emc_icc_dvfs_opp_table {
- /delete-node/ opp-625000000-1200;
- /delete-node/ opp-625000000-1250;
- /delete-node/ opp-667000000-1200;
- /delete-node/ opp-750000000-1300;
- /delete-node/ opp-800000000-1300;
- /delete-node/ opp-900000000-1350;
-};
-
-&emc_bw_dfs_opp_table {
- /delete-node/ opp-625000000;
- /delete-node/ opp-667000000;
- /delete-node/ opp-750000000;
- /delete-node/ opp-800000000;
- /delete-node/ opp-900000000;
-};
diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
index d100a1a8b705..a2d557155114 100644
--- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
+++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
@@ -210,6 +210,20 @@
opp-suspend;
};
+ opp-266500000-1000 {
+ opp-microvolt = <1000000 1000000 1350000>;
+ opp-hz = /bits/ 64 <266500000>;
+ opp-supported-hw = <0x0007>;
+ required-opps = <&core_opp_1000>;
+ };
+
+ opp-266500000-1250 {
+ opp-microvolt = <1250000 1250000 1350000>;
+ opp-hz = /bits/ 64 <266500000>;
+ opp-supported-hw = <0x0008>;
+ required-opps = <&core_opp_1250>;
+ };
+
opp-333500000-1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <333500000>;
@@ -424,6 +438,12 @@
opp-suspend;
};
+ opp-266500000 {
+ opp-hz = /bits/ 64 <266500000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <2132000>;
+ };
+
opp-333500000 {
opp-hz = /bits/ 64 <333500000>;
opp-supported-hw = <0x000F>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 9dab8d2c158a..9cba67b54111 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -397,13 +397,6 @@
#clock-cells = <1>;
#reset-cells = <1>;
- sclk {
- compatible = "nvidia,tegra30-sclk";
- clocks = <&tegra_car TEGRA30_CLK_SCLK>;
- power-domains = <&pd_core>;
- operating-points-v2 = <&sclk_dvfs_opp_table>;
- };
-
pll-c {
compatible = "nvidia,tegra30-pllc";
clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
@@ -424,6 +417,13 @@
power-domains = <&pd_core>;
operating-points-v2 = <&pll_m_dvfs_opp_table>;
};
+
+ sclk {
+ compatible = "nvidia,tegra30-sclk";
+ clocks = <&tegra_car TEGRA30_CLK_SCLK>;
+ power-domains = <&pd_core>;
+ operating-points-v2 = <&sclk_dvfs_opp_table>;
+ };
};
flow-controller@60007000 {
@@ -648,13 +648,6 @@
status = "disabled";
};
- rtc@7000e000 {
- compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA30_CLK_RTC>;
- };
-
i2c@7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
@@ -831,6 +824,13 @@
status = "disabled";
};
+ rtc@7000e000 {
+ compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_RTC>;
+ };
+
kbc@7000e200 {
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
@@ -854,6 +854,28 @@
};
powergates {
+ pd_heg: heg {
+ clocks = <&tegra_car TEGRA30_CLK_GR2D>,
+ <&tegra_car TEGRA30_CLK_EPP>,
+ <&tegra_car TEGRA30_CLK_HOST1X>;
+ resets = <&mc TEGRA30_MC_RESET_2D>,
+ <&mc TEGRA30_MC_RESET_EPP>,
+ <&mc TEGRA30_MC_RESET_HC>,
+ <&tegra_car TEGRA30_CLK_GR2D>,
+ <&tegra_car TEGRA30_CLK_EPP>,
+ <&tegra_car TEGRA30_CLK_HOST1X>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_mpe: mpe {
+ clocks = <&tegra_car TEGRA30_CLK_MPE>;
+ resets = <&mc TEGRA30_MC_RESET_MPE>,
+ <&tegra_car TEGRA30_CLK_MPE>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
pd_3d0: td {
clocks = <&tegra_car TEGRA30_CLK_GR3D>;
resets = <&mc TEGRA30_MC_RESET_3D>,
@@ -870,6 +892,14 @@
#power-domain-cells = <0>;
};
+ pd_vde: vdec {
+ clocks = <&tegra_car TEGRA30_CLK_VDE>;
+ resets = <&mc TEGRA30_MC_RESET_VDE>,
+ <&tegra_car TEGRA30_CLK_VDE>;
+ power-domains = <&pd_core>;
+ #power-domain-cells = <0>;
+ };
+
pd_venc: venc {
clocks = <&tegra_car TEGRA30_CLK_ISP>,
<&tegra_car TEGRA30_CLK_VI>,
@@ -882,36 +912,6 @@
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
-
- pd_vde: vdec {
- clocks = <&tegra_car TEGRA30_CLK_VDE>;
- resets = <&mc TEGRA30_MC_RESET_VDE>,
- <&tegra_car TEGRA30_CLK_VDE>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_mpe: mpe {
- clocks = <&tegra_car TEGRA30_CLK_MPE>;
- resets = <&mc TEGRA30_MC_RESET_MPE>,
- <&tegra_car TEGRA30_CLK_MPE>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
-
- pd_heg: heg {
- clocks = <&tegra_car TEGRA30_CLK_GR2D>,
- <&tegra_car TEGRA30_CLK_EPP>,
- <&tegra_car TEGRA30_CLK_HOST1X>;
- resets = <&mc TEGRA30_MC_RESET_2D>,
- <&mc TEGRA30_MC_RESET_EPP>,
- <&mc TEGRA30_MC_RESET_HC>,
- <&tegra_car TEGRA30_CLK_GR2D>,
- <&tegra_car TEGRA30_CLK_EPP>,
- <&tegra_car TEGRA30_CLK_HOST1X>;
- power-domains = <&pd_core>;
- #power-domain-cells = <0>;
- };
};
};
@@ -1283,10 +1283,7 @@
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&{/cpus/cpu@0}>,
- <&{/cpus/cpu@1}>,
- <&{/cpus/cpu@2}>,
- <&{/cpus/cpu@3}>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
thermal-zones {
diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts
index c46c2e8a10a7..e007db084787 100644
--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts
@@ -36,11 +36,11 @@
};
&ethsc {
- interrupts = <1 8>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <1 8>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -56,7 +56,7 @@
};
&gpio {
- xirq1 {
+ xirq1-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(1) 0>;
input;
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index b52957ccda0d..df2de7a40211 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-ld4";
@@ -55,7 +56,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
@@ -69,7 +71,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -80,7 +82,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -91,7 +93,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -102,7 +104,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -113,7 +115,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 29 4>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -140,7 +142,7 @@
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 1>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -154,7 +156,7 @@
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 1>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -168,7 +170,7 @@
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 1>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -182,7 +184,7 @@
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 1>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -205,33 +207,33 @@
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-ld4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-ld4-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-ld4-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-ld4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-ld4-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-ld4-peri-reset";
#reset-cells = <1>;
};
@@ -240,8 +242,13 @@
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
- <0 71 4>, <0 72 4>, <0 73 4>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
@@ -251,7 +258,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -271,7 +278,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
@@ -289,7 +296,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -303,7 +310,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -317,7 +324,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
@@ -327,7 +334,7 @@
has-transaction-translator;
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-ld4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -337,9 +344,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-ld4-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -358,14 +366,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -384,17 +394,17 @@
#interrupt-cells = <2>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-ld4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-ld4-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-ld4-reset";
#reset-cells = <1>;
};
@@ -407,7 +417,7 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
index 5bc7fe11b517..223a78b4a761 100644
--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
@@ -40,11 +40,11 @@
};
&ethsc {
- interrupts = <4 8>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <4 8>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -60,7 +60,7 @@
};
&gpio {
- xirq4 {
+ xirq4-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
input;
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index c0fd029b37e5..f909ec2e5333 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -196,11 +196,21 @@
function = "usb0";
};
+ pinctrl_usb0_device: usb0-device {
+ groups = "usb0_device";
+ function = "usb0";
+ };
+
pinctrl_usb1: usb1 {
groups = "usb1";
function = "usb1";
};
+ pinctrl_usb1_device: usb1-device {
+ groups = "usb1_device";
+ function = "usb1";
+ };
+
pinctrl_usb2: usb2 {
groups = "usb2";
function = "usb2";
diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts
index 27ff2b7b9d0e..6baee4410d9c 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts
@@ -99,3 +99,11 @@
&usb1 {
status = "okay";
};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts
index 3b9b61314d01..d2ce5c039865 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts
@@ -39,11 +39,11 @@
};
&ethsc {
- interrupts = <2 8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <2 8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -59,7 +59,7 @@
};
&gpio {
- xirq2 {
+ xirq2-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(2) 0>;
input;
@@ -108,3 +108,11 @@
reg = <0>;
};
};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index a53b73ee93e9..ba55af30e904 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-pro4";
@@ -63,7 +64,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(768 * 1024)>;
cache-sets = <256>;
@@ -77,7 +79,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -88,7 +90,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -99,7 +101,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -110,7 +112,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -121,7 +123,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -148,7 +150,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -162,7 +164,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -176,7 +178,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -190,7 +192,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -206,7 +208,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -218,7 +220,7 @@
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -239,33 +241,33 @@
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ mioctrl: syscon@59810000 {
compatible = "socionext,uniphier-pro4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-pro4-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-pro4-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pro4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pro4-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pro4-peri-reset";
#reset-cells = <1>;
};
@@ -274,8 +276,14 @@
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
- <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
@@ -285,7 +293,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -299,13 +307,14 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
@@ -323,7 +332,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a600000 0x200>;
- interrupts = <0 85 4>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1>;
clocks = <&mio_clk 2>;
@@ -339,7 +348,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -355,7 +364,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -367,7 +376,7 @@
has-transaction-translator;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pro4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -376,7 +385,7 @@
compatible = "socionext,uniphier-pro4-pinctrl";
};
- usb-phy {
+ usb-hub {
compatible = "socionext,uniphier-pro4-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
@@ -403,11 +412,17 @@
vbus-supply = <&usb1_vbus>;
};
};
+
+ sg_clk: clock-controller {
+ compatible = "socionext,uniphier-pro4-sg-clock";
+ #clock-cells = <1>;
+ };
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pro4-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -431,7 +446,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -446,14 +461,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -465,17 +482,17 @@
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pro4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pro4-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pro4-reset";
#reset-cells = <1>;
};
@@ -485,7 +502,7 @@
compatible = "socionext,uniphier-pro4-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "gio", "ether", "ether-gb", "ether-phy";
@@ -503,12 +520,107 @@
};
};
+ ahci0: sata@65600000 {
+ compatible = "socionext,uniphier-pro4-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65600000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 12>, <&sys_clk 28>;
+ resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
+ ports-implemented = <1>;
+ phys = <&ahci0_phy>;
+ assigned-clocks = <&sg_clk 0>;
+ assigned-clock-rates = <25000000>;
+ };
+
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs2-ahci-glue",
+ "simple-mfd";
+ reg = <0x65700000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ ahci0_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pro4-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 28>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ ahci0_phy: phy@10 {
+ compatible = "socionext,uniphier-pro4-ahci-phy";
+ reg = <0x10 0x40>;
+ clock-names = "link", "gio";
+ clocks = <&sys_clk 28>, <&sys_clk 12>;
+ reset-names = "link", "gio", "phy",
+ "pm", "tx", "rx";
+ resets = <&sys_rst 28>, <&sys_rst 12>,
+ <&sys_rst 30>,
+ <&ahci0_rst 0>, <&ahci0_rst 1>,
+ <&ahci0_rst 2>;
+ #phy-cells = <0>;
+ };
+ };
+
+ ahci1: sata@65800000 {
+ compatible = "socionext,uniphier-pro4-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65800000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 12>, <&sys_clk 29>;
+ resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
+ ports-implemented = <1>;
+ phys = <&ahci1_phy>;
+ assigned-clocks = <&sg_clk 0>;
+ assigned-clock-rates = <25000000>;
+ };
+
+ sata-controller@65900000 {
+ compatible = "socionext,uniphier-pro4-ahci-glue",
+ "simple-mfd";
+ reg = <0x65900000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65900000 0x100>;
+
+ ahci1_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pro4-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 29>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 29>;
+ #reset-cells = <1>;
+ };
+
+ ahci1_phy: phy@10 {
+ compatible = "socionext,uniphier-pro4-ahci-phy";
+ reg = <0x10 0x40>;
+ clock-names = "link", "gio";
+ clocks = <&sys_clk 29>, <&sys_clk 12>;
+ reset-names = "link", "gio", "phy",
+ "pm", "tx", "rx";
+ resets = <&sys_rst 29>, <&sys_rst 12>,
+ <&sys_rst 30>,
+ <&ahci1_rst 0>, <&ahci1_rst 1>,
+ <&ahci1_rst 2>;
+ #phy-cells = <0>;
+ };
+ };
+
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host", "peripheral";
- interrupts = <0 134 4>, <0 135 4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clock-names = "ref", "bus_early", "suspend";
@@ -518,9 +630,10 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x100>;
@@ -534,7 +647,7 @@
resets = <&sys_rst 12>, <&sys_rst 14>;
};
- usb0_ssphy: ss-phy@10 {
+ usb0_ssphy: phy@10 {
compatible = "socionext,uniphier-pro4-usb3-ssphy";
reg = <0x10 0x10>;
#phy-cells = <0>;
@@ -545,7 +658,7 @@
vbus-supply = <&usb0_vbus>;
};
- usb0_rst: reset@40 {
+ usb0_rst: reset-controller@40 {
compatible = "socionext,uniphier-pro4-usb3-reset";
reg = <0x40 0x4>;
#reset-cells = <1>;
@@ -561,7 +674,8 @@
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host", "peripheral";
- interrupts = <0 137 4>, <0 138 4>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clock-names = "ref", "bus_early", "suspend";
@@ -571,9 +685,10 @@
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x100>;
@@ -587,7 +702,7 @@
resets = <&sys_rst 12>, <&sys_rst 15>;
};
- usb1_rst: reset@40 {
+ usb1_rst: reset-controller@40 {
compatible = "socionext,uniphier-pro4-usb3-reset";
reg = <0x40 0x4>;
#reset-cells = <1>;
@@ -605,7 +720,7 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/boot/dts/uniphier-pro5-epcore.dts b/arch/arm/boot/dts/uniphier-pro5-epcore.dts
new file mode 100644
index 000000000000..ed759dcc3216
--- /dev/null
+++ b/arch/arm/boot/dts/uniphier-pro5-epcore.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE)
+ *
+ * Copyright (C) 2021 Socionext Inc.
+ * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ */
+
+/dts-v1/;
+#include "uniphier-pro5.dtsi"
+#include "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier Pro5 EP-CORE Board";
+ compatible = "socionext,uniphier-pro5-epcore", "socionext,uniphier-pro5";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&ethsc {
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&serialsc {
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+};
+
+&pcie_ep {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pro5-proex.dts b/arch/arm/boot/dts/uniphier-pro5-proex.dts
new file mode 100644
index 000000000000..2cfb84f73cc0
--- /dev/null
+++ b/arch/arm/boot/dts/uniphier-pro5-proex.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Source for UniPhier Pro5 ProEX Board
+ *
+ * Copyright (C) 2021 Socionext Inc.
+ * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ */
+
+/dts-v1/;
+#include "uniphier-pro5.dtsi"
+
+/ {
+ model = "UniPhier Pro5 ProEX Board";
+ compatible = "socionext,uniphier-pro5-proex", "socionext,uniphier-pro5";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ aliases {
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c3;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+};
+
+&pcie_ep {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 3525125832dd..2d8591cdddb8 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -5,6 +5,8 @@
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
/ {
compatible = "socionext,uniphier-pro5";
#address-cells = <1>;
@@ -135,7 +137,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
- interrupts = <0 190 4>, <0 191 4>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
@@ -148,7 +151,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
@@ -162,7 +166,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -175,7 +179,7 @@
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 11>; /* common with spi0 */
@@ -186,7 +190,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -197,7 +201,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -208,7 +212,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -219,7 +223,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -246,7 +250,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -260,7 +264,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -274,7 +278,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -288,7 +292,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -304,7 +308,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -316,7 +320,7 @@
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -337,39 +341,39 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pro5-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pro5-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pro5-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pro5-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pro5-peri-reset";
#reset-cells = <1>;
};
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-pro5-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -379,9 +383,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pro5-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -415,7 +420,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -430,14 +435,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -449,17 +456,17 @@
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pro5-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pro5-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pro5-reset";
#reset-cells = <1>;
};
@@ -470,7 +477,7 @@
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
- interrupts = <0 134 4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clock-names = "ref", "bus_early", "suspend";
@@ -480,14 +487,15 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -506,7 +514,7 @@
resets = <&sys_rst 12>, <&sys_rst 14>;
};
- usb0_hsphy0: hs-phy@280 {
+ usb0_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -517,7 +525,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy0: ss-phy@380 {
+ usb0_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
@@ -534,7 +542,7 @@
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host";
- interrupts = <0 137 4>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
@@ -544,14 +552,15 @@
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -579,7 +588,7 @@
resets = <&sys_rst 12>, <&sys_rst 15>;
};
- usb1_hsphy0: hs-phy@280 {
+ usb1_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -590,7 +599,7 @@
vbus-supply = <&usb1_vbus0>;
};
- usb1_hsphy1: hs-phy@290 {
+ usb1_hsphy1: phy@290 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x290 0x10>;
#phy-cells = <0>;
@@ -601,7 +610,7 @@
vbus-supply = <&usb1_vbus1>;
};
- usb1_ssphy0: ss-phy@380 {
+ usb1_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
@@ -614,8 +623,7 @@
};
pcie_ep: pcie-ep@66000000 {
- compatible = "socionext,uniphier-pro5-pcie-ep",
- "snps,dw-pcie-ep";
+ compatible = "socionext,uniphier-pro5-pcie-ep";
status = "disabled";
reg-names = "dbi", "dbi2", "link", "addr_space";
reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
@@ -650,7 +658,7 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
@@ -663,7 +671,7 @@
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68400000 0x800>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sd_clk 1>;
@@ -679,7 +687,7 @@
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68800000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -691,6 +699,7 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
index 759384b60663..5f18b926c50a 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
@@ -99,3 +99,7 @@
&usb1 {
status = "okay";
};
+
+&ahci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index e81e5937a60a..f97a57222101 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -161,7 +162,10 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(1280 * 1024)>;
cache-sets = <512>;
@@ -175,7 +179,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -188,7 +192,7 @@
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -199,7 +203,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -210,7 +214,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -221,7 +225,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -232,7 +236,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -259,7 +263,7 @@
audio@56000000 {
compatible = "socionext,uniphier-pxs2-aio";
reg = <0x56000000 0x80000>;
- interrupts = <0 144 4>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ain1>,
<&pinctrl_ain2>,
@@ -317,7 +321,7 @@
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -331,7 +335,7 @@
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -345,7 +349,7 @@
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -359,7 +363,7 @@
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -373,7 +377,7 @@
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 45 4>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 8>;
resets = <&peri_rst 8>;
clock-frequency = <400000>;
@@ -385,7 +389,7 @@
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -397,7 +401,7 @@
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -418,33 +422,33 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ sdctrl: syscon@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pxs2-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-peri-reset";
#reset-cells = <1>;
};
@@ -454,7 +458,7 @@
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a000000 0x800>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sd_clk 1>;
@@ -470,7 +474,7 @@
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -482,9 +486,10 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&sdctrl 0>;
};
- soc_glue: soc-glue@5f800000 {
+ soc_glue: syscon@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -494,9 +499,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -515,7 +521,7 @@
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -530,14 +536,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0xf04>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0xf04>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -549,24 +557,24 @@
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pxs2-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pxs2-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pxs2-reset";
#reset-cells = <1>;
};
- pvtctl: pvtctl {
+ pvtctl: thermal-sensor {
compatible = "socionext,uniphier-pxs2-thermal";
- interrupts = <0 3 4>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f86 0x6844>;
};
@@ -576,7 +584,7 @@
compatible = "socionext,uniphier-pxs2-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
@@ -593,12 +601,53 @@
};
};
+ ahci: sata@65600000 {
+ compatible = "socionext,uniphier-pxs2-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65600000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 28>;
+ resets = <&sys_rst 28>, <&ahci_rst 0>;
+ ports-implemented = <1>;
+ phys = <&ahci_phy>;
+ };
+
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs2-ahci-glue",
+ "simple-mfd";
+ reg = <0x65700000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ ahci_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pxs2-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link";
+ resets = <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ ahci_phy: phy@10 {
+ compatible = "socionext,uniphier-pxs2-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 28>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
+
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
- interrupt-names = "host", "peripheral";
- interrupts = <0 134 4>, <0 135 4>;
+ interrupt-names = "dwc_usb3";
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
@@ -609,14 +658,15 @@
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
+ reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -644,7 +694,7 @@
resets = <&sys_rst 14>;
};
- usb0_hsphy0: hs-phy@200 {
+ usb0_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -655,7 +705,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_hsphy1: hs-phy@210 {
+ usb0_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -666,7 +716,7 @@
vbus-supply = <&usb0_vbus1>;
};
- usb0_ssphy0: ss-phy@300 {
+ usb0_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -677,7 +727,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy1: ss-phy@310 {
+ usb0_ssphy1: phy@310 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x310 0x10>;
#phy-cells = <0>;
@@ -693,8 +743,8 @@
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65c00000 0xcd00>;
- interrupt-names = "host", "peripheral";
- interrupts = <0 137 4>, <0 138 4>;
+ interrupt-names = "dwc_usb3";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
clock-names = "ref", "bus_early", "suspend";
@@ -704,14 +754,15 @@
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
+ reg = <0x65d00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -739,7 +790,7 @@
resets = <&sys_rst 15>;
};
- usb1_hsphy0: hs-phy@200 {
+ usb1_hsphy0: phy@200 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
@@ -750,7 +801,7 @@
vbus-supply = <&usb1_vbus0>;
};
- usb1_hsphy1: hs-phy@210 {
+ usb1_hsphy1: phy@210 {
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
reg = <0x210 0x10>;
#phy-cells = <0>;
@@ -761,7 +812,7 @@
vbus-supply = <&usb1_vbus1>;
};
- usb1_ssphy0: ss-phy@300 {
+ usb1_ssphy0: phy@300 {
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
@@ -780,7 +831,7 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts
index 6db949ec7411..2446f9e15360 100644
--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts
@@ -36,11 +36,11 @@
};
&ethsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
@@ -56,7 +56,7 @@
};
&gpio {
- xirq0 {
+ xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index 96a766deb8d1..f876282760e9 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-sld8";
@@ -55,7 +56,8 @@
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(256 * 1024)>;
cache-sets = <256>;
@@ -69,7 +71,7 @@
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -80,7 +82,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -91,7 +93,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -102,7 +104,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -113,7 +115,7 @@
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 29 4>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -144,7 +146,7 @@
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 1>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -158,7 +160,7 @@
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 1>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -172,7 +174,7 @@
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 1>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -186,7 +188,7 @@
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 1>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -209,33 +211,33 @@
reg = <0x59801000 0x400>;
};
- mioctrl@59810000 {
+ mioctrl: syscon@59810000 {
compatible = "socionext,uniphier-sld8-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
- mio_clk: clock {
+ mio_clk: clock-controller {
compatible = "socionext,uniphier-sld8-mio-clock";
#clock-cells = <1>;
};
- mio_rst: reset {
+ mio_rst: reset-controller {
compatible = "socionext,uniphier-sld8-mio-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-sld8-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-sld8-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-sld8-peri-reset";
#reset-cells = <1>;
};
@@ -244,8 +246,13 @@
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
- <0 71 4>, <0 72 4>, <0 73 4>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
@@ -255,7 +262,7 @@
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -269,13 +276,14 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
+ socionext,syscon-uhs-mode = <&mioctrl 0>;
};
emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
@@ -293,7 +301,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 80 4>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -307,7 +315,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 81 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -321,7 +329,7 @@
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
- interrupts = <0 82 4>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
@@ -331,7 +339,7 @@
has-transaction-translator;
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-sld8-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -341,9 +349,10 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-sld8-soc-glue-debug",
- "simple-mfd";
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
@@ -362,14 +371,16 @@
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
@@ -388,17 +399,17 @@
#interrupt-cells = <2>;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-sld8-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-sld8-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-sld8-reset";
#reset-cells = <1>;
};
@@ -411,7 +422,7 @@
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi
index 444802fee9fb..97e7d5db8eb8 100644
--- a/arch/arm/boot/dts/uniphier-support-card.dtsi
+++ b/arch/arm/boot/dts/uniphier-support-card.dtsi
@@ -8,13 +8,13 @@
&system_bus {
status = "okay";
ranges = <1 0x00000000 0x42000000 0x02000000>;
- interrupt-parent = <&gpio>;
ethsc: ethernet@1,1f00000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <1 0x01f00000 0x1000>;
phy-mode = "mii";
reg-io-width = <4>;
+ interrupt-parent = <&gpio>;
};
serialsc: serial@1,1fb0000 {
@@ -22,5 +22,6 @@
reg = <1 0x01fb0000 0x20>;
clock-frequency = <12288000>;
reg-shift = <1>;
+ interrupt-parent = <&gpio>;
};
};
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 8a0cfbfd0c45..b6cb9cdf8197 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -60,7 +60,7 @@
spi0: spi@fffa4000 {
cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
status = "okay";
- mtd_dataflash@0 {
+ flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
reg = <0>;
spi-max-frequency = <15000000>;
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 79f7cc241282..f31dcf7e5862 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -237,7 +237,7 @@
clock-names = "apb_pclk";
};
- uart0: uart@101f1000 {
+ uart0: serial@101f1000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f1000 0x1000>;
interrupts = <12>;
@@ -245,7 +245,7 @@
clock-names = "uartclk", "apb_pclk";
};
- uart1: uart@101f2000 {
+ uart1: serial@101f2000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f2000 0x1000>;
interrupts = <13>;
@@ -253,7 +253,7 @@
clock-names = "uartclk", "apb_pclk";
};
- uart2: uart@101f3000 {
+ uart2: serial@101f3000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f3000 0x1000>;
interrupts = <14>;
@@ -391,7 +391,7 @@
reg = <0x101f4000 0x1000>;
interrupts = <11>;
clocks = <&xtal24mhz>, <&pclk>;
- clock-names = "SSPCLK", "apb_pclk";
+ clock-names = "sspclk", "apb_pclk";
};
fpga {
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index e7e751a858d8..fc21ce54b33a 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -85,7 +85,7 @@
*/
interrupts-extended = <&sic 22 &sic 23>;
};
- uart@9000 {
+ serial@9000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x9000 0x1000>;
interrupt-parent = <&sic>;
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index f434fe5cf4a1..c5e92f6d2fcd 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -216,7 +216,7 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
- v2m_serial0: uart@9000 {
+ v2m_serial0: serial@9000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x09000 0x1000>;
interrupts = <5>;
@@ -224,7 +224,7 @@
clock-names = "uartclk", "apb_pclk";
};
- v2m_serial1: uart@a000 {
+ v2m_serial1: serial@a000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a000 0x1000>;
interrupts = <6>;
@@ -232,7 +232,7 @@
clock-names = "uartclk", "apb_pclk";
};
- v2m_serial2: uart@b000 {
+ v2m_serial2: serial@b000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b000 0x1000>;
interrupts = <7>;
@@ -240,7 +240,7 @@
clock-names = "uartclk", "apb_pclk";
};
- v2m_serial3: uart@c000 {
+ v2m_serial3: serial@c000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c000 0x1000>;
interrupts = <8>;
@@ -383,49 +383,49 @@
leds {
compatible = "gpio-leds";
- user1 {
+ led-user1 {
label = "v2m:green:user1";
gpios = <&v2m_led_gpios 0 0>;
linux,default-trigger = "heartbeat";
};
- user2 {
+ led-user2 {
label = "v2m:green:user2";
gpios = <&v2m_led_gpios 1 0>;
linux,default-trigger = "mmc0";
};
- user3 {
+ led-user3 {
label = "v2m:green:user3";
gpios = <&v2m_led_gpios 2 0>;
linux,default-trigger = "cpu0";
};
- user4 {
+ led-user4 {
label = "v2m:green:user4";
gpios = <&v2m_led_gpios 3 0>;
linux,default-trigger = "cpu1";
};
- user5 {
+ led-user5 {
label = "v2m:green:user5";
gpios = <&v2m_led_gpios 4 0>;
linux,default-trigger = "cpu2";
};
- user6 {
+ led-user6 {
label = "v2m:green:user6";
gpios = <&v2m_led_gpios 5 0>;
linux,default-trigger = "cpu3";
};
- user7 {
+ led-user7 {
label = "v2m:green:user7";
gpios = <&v2m_led_gpios 6 0>;
linux,default-trigger = "cpu4";
};
- user8 {
+ led-user8 {
label = "v2m:green:user8";
gpios = <&v2m_led_gpios 7 0>;
linux,default-trigger = "cpu5";
diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts
index 830c85476b3d..e4f691d601cc 100644
--- a/arch/arm/boot/dts/vf610-bk4.dts
+++ b/arch/arm/boot/dts/vf610-bk4.dts
@@ -38,7 +38,7 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
/* LED D5 */
- led0: heartbeat {
+ led0: led-heartbeat {
label = "heartbeat";
gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -61,7 +61,7 @@
regulator-max-microvolt = <3300000>;
};
- spi-gpio {
+ spi {
compatible = "spi-gpio";
pinctrl-0 = <&pinctrl_gpio_spi>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h
index f1e5a7cf58a9..b7b7322a2d1b 100644
--- a/arch/arm/boot/dts/vf610-pinfunc.h
+++ b/arch/arm/boot/dts/vf610-pinfunc.h
@@ -420,7 +420,7 @@
#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
-#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
@@ -802,5 +802,55 @@
#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0
#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
+#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0
+#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0
+#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0
+#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0
+#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0
+#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0
#endif
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index dbb5ffcdcec4..6c246d5aa032 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -169,7 +169,7 @@
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&clks VF610_CLK_SAI2>;
- };
+ };
};
&iomuxc {
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index 1f9686c33a84..6280c5e86a12 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -288,7 +288,7 @@
};
};
- spi0 {
+ spi-0 {
compatible = "spi-gpio";
pinctrl-0 = <&pinctrl_gpio_spi0>;
pinctrl-names = "default";
@@ -345,7 +345,7 @@
};
&i2c2 {
- tca9548@70 {
+ i2c-mux@70 {
compatible = "nxp,pca9548";
pinctrl-0 = <&pinctrl_i2c_mux_reset>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
index de79dcfd32e6..c00d39562a10 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
@@ -259,7 +259,7 @@
xtal-trim = /bits/ 8 <0x06>;
sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
- reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio6 10 GPIO_ACTIVE_LOW>;
fsl,spi-cs-sck-delay = <180>;
fsl,spi-sck-cs-delay = <250>;
@@ -340,7 +340,7 @@
};
&i2c2 {
- tca9548@70 {
+ i2c-mux@70 {
compatible = "nxp,pca9548";
pinctrl-0 = <&pinctrl_i2c_mux_reset>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index f8299f33a692..ce5e52896b19 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -59,7 +59,7 @@
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
- debug {
+ led-debug {
label = "zii:green:debug1";
gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
index 040a1f8b6130..7b3276cd470f 100644
--- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
+++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
@@ -23,7 +23,7 @@
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
- debug {
+ led-debug {
label = "zii:green:debug1";
gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts
index 6c6ec46fd015..180acb0795b9 100644
--- a/arch/arm/boot/dts/vf610-zii-spb4.dts
+++ b/arch/arm/boot/dts/vf610-zii-spb4.dts
@@ -241,7 +241,7 @@
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
index fe600ab2e4bd..20beaa8433b6 100644
--- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
+++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
@@ -254,7 +254,7 @@
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
- rave-sp {
+ mcu {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 956182d08e74..2fba923821d0 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -2,7 +2,6 @@
//
// Copyright 2013 Freescale Semiconductor, Inc.
-
#include "vf500.dtsi"
&a5_cpu {
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index d53f9c9db8bf..ff4479994b60 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -191,9 +191,8 @@
<&clks VF610_CLK_SAI0_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 0 17>,
- <&edma0 0 16>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 0 16>, <&edma0 0 17>;
status = "disabled";
};
@@ -205,9 +204,8 @@
<&clks VF610_CLK_SAI1_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 0 19>,
- <&edma0 0 18>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 0 18>, <&edma0 0 19>;
status = "disabled";
};
@@ -219,9 +217,8 @@
<&clks VF610_CLK_SAI2_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 0 21>,
- <&edma0 0 20>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 0 20>, <&edma0 0 21>;
status = "disabled";
};
@@ -233,9 +230,8 @@
<&clks VF610_CLK_SAI3_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 9>,
- <&edma0 1 8>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 8>, <&edma0 1 9>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 47c2a4b14c06..cd9931f6bcbd 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -230,8 +230,20 @@
#size-cells = <0>;
};
+ qspi: spi@e000d000 {
+ compatible = "xlnx,zynq-qspi-1.0";
+ reg = <0xe000d000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 19 4>;
+ clocks = <&clkc 10>, <&clkc 43>;
+ clock-names = "ref_clk", "pclk";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gem0: ethernet@e000b000 {
- compatible = "cdns,zynq-gem", "cdns,gem";
+ compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
@@ -242,7 +254,7 @@
};
gem1: ethernet@e000c000 {
- compatible = "cdns,zynq-gem", "cdns,gem";
+ compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
@@ -331,20 +343,20 @@
};
};
- dmac_s: dmac@f8003000 {
+ dmac_s: dma-controller@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
- interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
- "dma4", "dma5", "dma6", "dma7";
+ /*
+ * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
+ * "dma4", "dma5", "dma6", "dma7";
+ */
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>;
#dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <4>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index cf70aff26c66..d23201ba8cd7 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -30,14 +30,14 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw14 {
+ switch-14 {
label = "sw14";
gpios = <&gpio0 12 0>;
linux,code = <108>; /* down */
wakeup-source;
autorepeat;
};
- sw13 {
+ switch-13 {
label = "sw13";
gpios = <&gpio0 14 0>;
linux,code = <103>; /* up */
diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi
index bf5d1c4568b0..dfb1fbafe3aa 100644
--- a/arch/arm/boot/dts/zynq-zturn-common.dtsi
+++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- K1 {
+ key {
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
diff --git a/arch/arm/boot/install.sh b/arch/arm/boot/install.sh
index 2a45092a40e3..9ec11fac7d8d 100644..100755
--- a/arch/arm/boot/install.sh
+++ b/arch/arm/boot/install.sh
@@ -1,7 +1,5 @@
#!/bin/sh
#
-# arch/arm/boot/install.sh
-#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
@@ -18,25 +16,6 @@
# $2 - kernel image file
# $3 - kernel map file
# $4 - default install path (blank if root directory)
-#
-
-verify () {
- if [ ! -f "$1" ]; then
- echo "" 1>&2
- echo " *** Missing file: $1" 1>&2
- echo ' *** You need to run "make" before "make install".' 1>&2
- echo "" 1>&2
- exit 1
- fi
-}
-
-# Make sure the files actually exist
-verify "$2"
-verify "$3"
-
-# User may have a custom install script
-if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
-if [ -x /sbin/${INSTALLKERNEL} ]; then exec /sbin/${INSTALLKERNEL} "$@"; fi
if [ "$(basename $2)" = "zImage" ]; then
# Compressed install
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index c8e198631d41..d2fdb1796f48 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,11 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
config SA1111
bool
- select DMABOUNCE if !ARCH_PXA
-
-config DMABOUNCE
- bool
- select ZONE_DMA
+ select ZONE_DMA if ARCH_SA1100
config KRAIT_L2_ACCESSORS
bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 8cd574be94cf..9733381074e0 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -6,7 +6,6 @@
obj-y += firmware.o
obj-$(CONFIG_SA1111) += sa1111.o
-obj-$(CONFIG_DMABOUNCE) += dmabounce.o
obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
@@ -14,7 +13,5 @@ obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
CFLAGS_REMOVE_mcpm_entry.o = -pg
-AFLAGS_mcpm_head.o := -march=armv7-a
-AFLAGS_vlock.o := -march=armv7-a
obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o
obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
deleted file mode 100644
index 7996c04393d5..000000000000
--- a/arch/arm/common/dmabounce.c
+++ /dev/null
@@ -1,582 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/common/dmabounce.c
- *
- * Special dma_{map/unmap/dma_sync}_* routines for systems that have
- * limited DMA windows. These functions utilize bounce buffers to
- * copy data to/from buffers located outside the DMA region. This
- * only works for systems in which DMA memory is at the bottom of
- * RAM, the remainder of memory is at the top and the DMA memory
- * can be marked as ZONE_DMA. Anything beyond that such as discontiguous
- * DMA windows will require custom implementations that reserve memory
- * areas at early bootup.
- *
- * Original version by Brad Parker (brad@heeltoe.com)
- * Re-written by Christopher Hoover <ch@murgatroid.com>
- * Made generic by Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Hewlett Packard Company.
- * Copyright (C) 2004 MontaVista Software, Inc.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/page-flags.h>
-#include <linux/device.h>
-#include <linux/dma-direct.h>
-#include <linux/dma-map-ops.h>
-#include <linux/dmapool.h>
-#include <linux/list.h>
-#include <linux/scatterlist.h>
-
-#include <asm/cacheflush.h>
-#include <asm/dma-iommu.h>
-
-#undef STATS
-
-#ifdef STATS
-#define DO_STATS(X) do { X ; } while (0)
-#else
-#define DO_STATS(X) do { } while (0)
-#endif
-
-/* ************************************************** */
-
-struct safe_buffer {
- struct list_head node;
-
- /* original request */
- void *ptr;
- size_t size;
- int direction;
-
- /* safe buffer info */
- struct dmabounce_pool *pool;
- void *safe;
- dma_addr_t safe_dma_addr;
-};
-
-struct dmabounce_pool {
- unsigned long size;
- struct dma_pool *pool;
-#ifdef STATS
- unsigned long allocs;
-#endif
-};
-
-struct dmabounce_device_info {
- struct device *dev;
- struct list_head safe_buffers;
-#ifdef STATS
- unsigned long total_allocs;
- unsigned long map_op_count;
- unsigned long bounce_count;
- int attr_res;
-#endif
- struct dmabounce_pool small;
- struct dmabounce_pool large;
-
- rwlock_t lock;
-
- int (*needs_bounce)(struct device *, dma_addr_t, size_t);
-};
-
-#ifdef STATS
-static ssize_t dmabounce_show(struct device *dev, struct device_attribute *attr,
- char *buf)
-{
- struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
- return sprintf(buf, "%lu %lu %lu %lu %lu %lu\n",
- device_info->small.allocs,
- device_info->large.allocs,
- device_info->total_allocs - device_info->small.allocs -
- device_info->large.allocs,
- device_info->total_allocs,
- device_info->map_op_count,
- device_info->bounce_count);
-}
-
-static DEVICE_ATTR(dmabounce_stats, 0400, dmabounce_show, NULL);
-#endif
-
-
-/* allocate a 'safe' buffer and keep track of it */
-static inline struct safe_buffer *
-alloc_safe_buffer(struct dmabounce_device_info *device_info, void *ptr,
- size_t size, enum dma_data_direction dir)
-{
- struct safe_buffer *buf;
- struct dmabounce_pool *pool;
- struct device *dev = device_info->dev;
- unsigned long flags;
-
- dev_dbg(dev, "%s(ptr=%p, size=%d, dir=%d)\n",
- __func__, ptr, size, dir);
-
- if (size <= device_info->small.size) {
- pool = &device_info->small;
- } else if (size <= device_info->large.size) {
- pool = &device_info->large;
- } else {
- pool = NULL;
- }
-
- buf = kmalloc(sizeof(struct safe_buffer), GFP_ATOMIC);
- if (buf == NULL) {
- dev_warn(dev, "%s: kmalloc failed\n", __func__);
- return NULL;
- }
-
- buf->ptr = ptr;
- buf->size = size;
- buf->direction = dir;
- buf->pool = pool;
-
- if (pool) {
- buf->safe = dma_pool_alloc(pool->pool, GFP_ATOMIC,
- &buf->safe_dma_addr);
- } else {
- buf->safe = dma_alloc_coherent(dev, size, &buf->safe_dma_addr,
- GFP_ATOMIC);
- }
-
- if (buf->safe == NULL) {
- dev_warn(dev,
- "%s: could not alloc dma memory (size=%d)\n",
- __func__, size);
- kfree(buf);
- return NULL;
- }
-
-#ifdef STATS
- if (pool)
- pool->allocs++;
- device_info->total_allocs++;
-#endif
-
- write_lock_irqsave(&device_info->lock, flags);
- list_add(&buf->node, &device_info->safe_buffers);
- write_unlock_irqrestore(&device_info->lock, flags);
-
- return buf;
-}
-
-/* determine if a buffer is from our "safe" pool */
-static inline struct safe_buffer *
-find_safe_buffer(struct dmabounce_device_info *device_info, dma_addr_t safe_dma_addr)
-{
- struct safe_buffer *b, *rb = NULL;
- unsigned long flags;
-
- read_lock_irqsave(&device_info->lock, flags);
-
- list_for_each_entry(b, &device_info->safe_buffers, node)
- if (b->safe_dma_addr <= safe_dma_addr &&
- b->safe_dma_addr + b->size > safe_dma_addr) {
- rb = b;
- break;
- }
-
- read_unlock_irqrestore(&device_info->lock, flags);
- return rb;
-}
-
-static inline void
-free_safe_buffer(struct dmabounce_device_info *device_info, struct safe_buffer *buf)
-{
- unsigned long flags;
-
- dev_dbg(device_info->dev, "%s(buf=%p)\n", __func__, buf);
-
- write_lock_irqsave(&device_info->lock, flags);
-
- list_del(&buf->node);
-
- write_unlock_irqrestore(&device_info->lock, flags);
-
- if (buf->pool)
- dma_pool_free(buf->pool->pool, buf->safe, buf->safe_dma_addr);
- else
- dma_free_coherent(device_info->dev, buf->size, buf->safe,
- buf->safe_dma_addr);
-
- kfree(buf);
-}
-
-/* ************************************************** */
-
-static struct safe_buffer *find_safe_buffer_dev(struct device *dev,
- dma_addr_t dma_addr, const char *where)
-{
- if (!dev || !dev->archdata.dmabounce)
- return NULL;
- if (dma_mapping_error(dev, dma_addr)) {
- dev_err(dev, "Trying to %s invalid mapping\n", where);
- return NULL;
- }
- return find_safe_buffer(dev->archdata.dmabounce, dma_addr);
-}
-
-static int needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
-{
- if (!dev || !dev->archdata.dmabounce)
- return 0;
-
- if (dev->dma_mask) {
- unsigned long limit, mask = *dev->dma_mask;
-
- limit = (mask + 1) & ~mask;
- if (limit && size > limit) {
- dev_err(dev, "DMA mapping too big (requested %#x "
- "mask %#Lx)\n", size, *dev->dma_mask);
- return -E2BIG;
- }
-
- /* Figure out if we need to bounce from the DMA mask. */
- if ((dma_addr | (dma_addr + size - 1)) & ~mask)
- return 1;
- }
-
- return !!dev->archdata.dmabounce->needs_bounce(dev, dma_addr, size);
-}
-
-static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
- enum dma_data_direction dir,
- unsigned long attrs)
-{
- struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
- struct safe_buffer *buf;
-
- if (device_info)
- DO_STATS ( device_info->map_op_count++ );
-
- buf = alloc_safe_buffer(device_info, ptr, size, dir);
- if (buf == NULL) {
- dev_err(dev, "%s: unable to map unsafe buffer %p!\n",
- __func__, ptr);
- return DMA_MAPPING_ERROR;
- }
-
- dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
- __func__, buf->ptr, virt_to_dma(dev, buf->ptr),
- buf->safe, buf->safe_dma_addr);
-
- if ((dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) &&
- !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
- dev_dbg(dev, "%s: copy unsafe %p to safe %p, size %d\n",
- __func__, ptr, buf->safe, size);
- memcpy(buf->safe, ptr, size);
- }
-
- return buf->safe_dma_addr;
-}
-
-static inline void unmap_single(struct device *dev, struct safe_buffer *buf,
- size_t size, enum dma_data_direction dir,
- unsigned long attrs)
-{
- BUG_ON(buf->size != size);
- BUG_ON(buf->direction != dir);
-
- dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
- __func__, buf->ptr, virt_to_dma(dev, buf->ptr),
- buf->safe, buf->safe_dma_addr);
-
- DO_STATS(dev->archdata.dmabounce->bounce_count++);
-
- if ((dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) &&
- !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
- void *ptr = buf->ptr;
-
- dev_dbg(dev, "%s: copy back safe %p to unsafe %p size %d\n",
- __func__, buf->safe, ptr, size);
- memcpy(ptr, buf->safe, size);
-
- /*
- * Since we may have written to a page cache page,
- * we need to ensure that the data will be coherent
- * with user mappings.
- */
- __cpuc_flush_dcache_area(ptr, size);
- }
- free_safe_buffer(dev->archdata.dmabounce, buf);
-}
-
-/* ************************************************** */
-
-/*
- * see if a buffer address is in an 'unsafe' range. if it is
- * allocate a 'safe' buffer and copy the unsafe buffer into it.
- * substitute the safe buffer for the unsafe one.
- * (basically move the buffer from an unsafe area to a safe one)
- */
-static dma_addr_t dmabounce_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction dir,
- unsigned long attrs)
-{
- dma_addr_t dma_addr;
- int ret;
-
- dev_dbg(dev, "%s(page=%p,off=%#lx,size=%zx,dir=%x)\n",
- __func__, page, offset, size, dir);
-
- dma_addr = pfn_to_dma(dev, page_to_pfn(page)) + offset;
-
- ret = needs_bounce(dev, dma_addr, size);
- if (ret < 0)
- return DMA_MAPPING_ERROR;
-
- if (ret == 0) {
- arm_dma_ops.sync_single_for_device(dev, dma_addr, size, dir);
- return dma_addr;
- }
-
- if (PageHighMem(page)) {
- dev_err(dev, "DMA buffer bouncing of HIGHMEM pages is not supported\n");
- return DMA_MAPPING_ERROR;
- }
-
- return map_single(dev, page_address(page) + offset, size, dir, attrs);
-}
-
-/*
- * see if a mapped address was really a "safe" buffer and if so, copy
- * the data from the safe buffer back to the unsafe buffer and free up
- * the safe buffer. (basically return things back to the way they
- * should be)
- */
-static void dmabounce_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
- enum dma_data_direction dir, unsigned long attrs)
-{
- struct safe_buffer *buf;
-
- dev_dbg(dev, "%s(dma=%#x,size=%d,dir=%x)\n",
- __func__, dma_addr, size, dir);
-
- buf = find_safe_buffer_dev(dev, dma_addr, __func__);
- if (!buf) {
- arm_dma_ops.sync_single_for_cpu(dev, dma_addr, size, dir);
- return;
- }
-
- unmap_single(dev, buf, size, dir, attrs);
-}
-
-static int __dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
- size_t sz, enum dma_data_direction dir)
-{
- struct safe_buffer *buf;
- unsigned long off;
-
- dev_dbg(dev, "%s(dma=%#x,sz=%zx,dir=%x)\n",
- __func__, addr, sz, dir);
-
- buf = find_safe_buffer_dev(dev, addr, __func__);
- if (!buf)
- return 1;
-
- off = addr - buf->safe_dma_addr;
-
- BUG_ON(buf->direction != dir);
-
- dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x off=%#lx) mapped to %p (dma=%#x)\n",
- __func__, buf->ptr, virt_to_dma(dev, buf->ptr), off,
- buf->safe, buf->safe_dma_addr);
-
- DO_STATS(dev->archdata.dmabounce->bounce_count++);
-
- if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
- dev_dbg(dev, "%s: copy back safe %p to unsafe %p size %d\n",
- __func__, buf->safe + off, buf->ptr + off, sz);
- memcpy(buf->ptr + off, buf->safe + off, sz);
- }
- return 0;
-}
-
-static void dmabounce_sync_for_cpu(struct device *dev,
- dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
- if (!__dmabounce_sync_for_cpu(dev, handle, size, dir))
- return;
-
- arm_dma_ops.sync_single_for_cpu(dev, handle, size, dir);
-}
-
-static int __dmabounce_sync_for_device(struct device *dev, dma_addr_t addr,
- size_t sz, enum dma_data_direction dir)
-{
- struct safe_buffer *buf;
- unsigned long off;
-
- dev_dbg(dev, "%s(dma=%#x,sz=%zx,dir=%x)\n",
- __func__, addr, sz, dir);
-
- buf = find_safe_buffer_dev(dev, addr, __func__);
- if (!buf)
- return 1;
-
- off = addr - buf->safe_dma_addr;
-
- BUG_ON(buf->direction != dir);
-
- dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x off=%#lx) mapped to %p (dma=%#x)\n",
- __func__, buf->ptr, virt_to_dma(dev, buf->ptr), off,
- buf->safe, buf->safe_dma_addr);
-
- DO_STATS(dev->archdata.dmabounce->bounce_count++);
-
- if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) {
- dev_dbg(dev, "%s: copy out unsafe %p to safe %p, size %d\n",
- __func__,buf->ptr + off, buf->safe + off, sz);
- memcpy(buf->safe + off, buf->ptr + off, sz);
- }
- return 0;
-}
-
-static void dmabounce_sync_for_device(struct device *dev,
- dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
- if (!__dmabounce_sync_for_device(dev, handle, size, dir))
- return;
-
- arm_dma_ops.sync_single_for_device(dev, handle, size, dir);
-}
-
-static int dmabounce_dma_supported(struct device *dev, u64 dma_mask)
-{
- if (dev->archdata.dmabounce)
- return 0;
-
- return arm_dma_ops.dma_supported(dev, dma_mask);
-}
-
-static const struct dma_map_ops dmabounce_ops = {
- .alloc = arm_dma_alloc,
- .free = arm_dma_free,
- .mmap = arm_dma_mmap,
- .get_sgtable = arm_dma_get_sgtable,
- .map_page = dmabounce_map_page,
- .unmap_page = dmabounce_unmap_page,
- .sync_single_for_cpu = dmabounce_sync_for_cpu,
- .sync_single_for_device = dmabounce_sync_for_device,
- .map_sg = arm_dma_map_sg,
- .unmap_sg = arm_dma_unmap_sg,
- .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
- .sync_sg_for_device = arm_dma_sync_sg_for_device,
- .dma_supported = dmabounce_dma_supported,
-};
-
-static int dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev,
- const char *name, unsigned long size)
-{
- pool->size = size;
- DO_STATS(pool->allocs = 0);
- pool->pool = dma_pool_create(name, dev, size,
- 0 /* byte alignment */,
- 0 /* no page-crossing issues */);
-
- return pool->pool ? 0 : -ENOMEM;
-}
-
-int dmabounce_register_dev(struct device *dev, unsigned long small_buffer_size,
- unsigned long large_buffer_size,
- int (*needs_bounce_fn)(struct device *, dma_addr_t, size_t))
-{
- struct dmabounce_device_info *device_info;
- int ret;
-
- device_info = kmalloc(sizeof(struct dmabounce_device_info), GFP_ATOMIC);
- if (!device_info) {
- dev_err(dev,
- "Could not allocated dmabounce_device_info\n");
- return -ENOMEM;
- }
-
- ret = dmabounce_init_pool(&device_info->small, dev,
- "small_dmabounce_pool", small_buffer_size);
- if (ret) {
- dev_err(dev,
- "dmabounce: could not allocate DMA pool for %ld byte objects\n",
- small_buffer_size);
- goto err_free;
- }
-
- if (large_buffer_size) {
- ret = dmabounce_init_pool(&device_info->large, dev,
- "large_dmabounce_pool",
- large_buffer_size);
- if (ret) {
- dev_err(dev,
- "dmabounce: could not allocate DMA pool for %ld byte objects\n",
- large_buffer_size);
- goto err_destroy;
- }
- }
-
- device_info->dev = dev;
- INIT_LIST_HEAD(&device_info->safe_buffers);
- rwlock_init(&device_info->lock);
- device_info->needs_bounce = needs_bounce_fn;
-
-#ifdef STATS
- device_info->total_allocs = 0;
- device_info->map_op_count = 0;
- device_info->bounce_count = 0;
- device_info->attr_res = device_create_file(dev, &dev_attr_dmabounce_stats);
-#endif
-
- dev->archdata.dmabounce = device_info;
- set_dma_ops(dev, &dmabounce_ops);
-
- dev_info(dev, "dmabounce: registered device\n");
-
- return 0;
-
- err_destroy:
- dma_pool_destroy(device_info->small.pool);
- err_free:
- kfree(device_info);
- return ret;
-}
-EXPORT_SYMBOL(dmabounce_register_dev);
-
-void dmabounce_unregister_dev(struct device *dev)
-{
- struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
-
- dev->archdata.dmabounce = NULL;
- set_dma_ops(dev, NULL);
-
- if (!device_info) {
- dev_warn(dev,
- "Never registered with dmabounce but attempting"
- "to unregister!\n");
- return;
- }
-
- if (!list_empty(&device_info->safe_buffers)) {
- dev_err(dev,
- "Removing from dmabounce with pending buffers!\n");
- BUG();
- }
-
- if (device_info->small.pool)
- dma_pool_destroy(device_info->small.pool);
- if (device_info->large.pool)
- dma_pool_destroy(device_info->large.pool);
-
-#ifdef STATS
- if (device_info->attr_res == 0)
- device_remove_file(dev, &dev_attr_dmabounce_stats);
-#endif
-
- kfree(device_info);
-
- dev_info(dev, "dmabounce: device unregistered\n");
-}
-EXPORT_SYMBOL(dmabounce_unregister_dev);
-
-MODULE_AUTHOR("Christopher Hoover <ch@hpl.hp.com>, Deepak Saxena <dsaxena@plexity.net>");
-MODULE_DESCRIPTION("Special dma_{map/unmap/dma_sync}_* routines for systems with limited DMA windows");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 24d21ba63030..309b74783468 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -23,7 +23,6 @@
#include <linux/spinlock.h>
#include <linux/io.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
@@ -495,7 +494,7 @@ static int locomo_probe(struct platform_device *dev)
return __locomo_probe(&dev->dev, mem, irq);
}
-static int locomo_remove(struct platform_device *dev)
+static void locomo_remove(struct platform_device *dev)
{
struct locomo *lchip = platform_get_drvdata(dev);
@@ -503,8 +502,6 @@ static int locomo_remove(struct platform_device *dev)
__locomo_remove(lchip);
platform_set_drvdata(dev, NULL);
}
-
- return 0;
}
/*
@@ -515,7 +512,7 @@ static int locomo_remove(struct platform_device *dev)
*/
static struct platform_driver locomo_device_driver = {
.probe = locomo_probe,
- .remove = locomo_remove,
+ .remove_new = locomo_remove,
#ifdef CONFIG_PM
.suspend = locomo_suspend,
.resume = locomo_resume,
diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
index 291d969bc719..299495c43dfd 100644
--- a/arch/arm/common/mcpm_head.S
+++ b/arch/arm/common/mcpm_head.S
@@ -15,6 +15,8 @@
#include "vlock.h"
+.arch armv7-a
+
.if MCPM_SYNC_CLUSTER_CPUS
.error "cpus must be the first member of struct mcpm_sync_struct"
.endif
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 5367f03beb46..aad6ba236f0f 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -26,13 +26,16 @@
#include <linux/clk.h>
#include <linux/io.h>
-#include <mach/hardware.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <linux/sizes.h>
#include <asm/hardware/sa1111.h>
+#ifdef CONFIG_ARCH_SA1100
+#include <mach/hardware.h>
+#endif
+
/* SA1111 IRQs */
#define IRQ_GPAIN0 (0)
#define IRQ_GPAIN1 (1)
@@ -1120,7 +1123,7 @@ static int sa1111_probe(struct platform_device *pdev)
return __sa1111_probe(&pdev->dev, mem, irq);
}
-static int sa1111_remove(struct platform_device *pdev)
+static void sa1111_remove(struct platform_device *pdev)
{
struct sa1111 *sachip = platform_get_drvdata(pdev);
@@ -1132,8 +1135,6 @@ static int sa1111_remove(struct platform_device *pdev)
__sa1111_remove(sachip);
platform_set_drvdata(pdev, NULL);
}
-
- return 0;
}
static struct dev_pm_ops sa1111_pm_ops = {
@@ -1152,7 +1153,7 @@ static struct dev_pm_ops sa1111_pm_ops = {
*/
static struct platform_driver sa1111_device_driver = {
.probe = sa1111_probe,
- .remove = sa1111_remove,
+ .remove_new = sa1111_remove,
.driver = {
.name = "sa1111",
.pm = &sa1111_pm_ops,
@@ -1386,70 +1387,9 @@ void sa1111_driver_unregister(struct sa1111_driver *driver)
}
EXPORT_SYMBOL(sa1111_driver_unregister);
-#ifdef CONFIG_DMABOUNCE
-/*
- * According to the "Intel StrongARM SA-1111 Microprocessor Companion
- * Chip Specification Update" (June 2000), erratum #7, there is a
- * significant bug in the SA1111 SDRAM shared memory controller. If
- * an access to a region of memory above 1MB relative to the bank base,
- * it is important that address bit 10 _NOT_ be asserted. Depending
- * on the configuration of the RAM, bit 10 may correspond to one
- * of several different (processor-relative) address bits.
- *
- * This routine only identifies whether or not a given DMA address
- * is susceptible to the bug.
- *
- * This should only get called for sa1111_device types due to the
- * way we configure our device dma_masks.
- */
-static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
-{
- /*
- * Section 4.6 of the "Intel StrongARM SA-1111 Development Module
- * User's Guide" mentions that jumpers R51 and R52 control the
- * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
- * SDRAM bank 1 on Neponset). The default configuration selects
- * Assabet, so any address in bank 1 is necessarily invalid.
- */
- return (machine_is_assabet() || machine_is_pfs168()) &&
- (addr >= 0xc8000000 || (addr + size) >= 0xc8000000);
-}
-
-static int sa1111_notifier_call(struct notifier_block *n, unsigned long action,
- void *data)
-{
- struct sa1111_dev *dev = to_sa1111_device(data);
-
- switch (action) {
- case BUS_NOTIFY_ADD_DEVICE:
- if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) {
- int ret = dmabounce_register_dev(&dev->dev, 1024, 4096,
- sa1111_needs_bounce);
- if (ret)
- dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret);
- }
- break;
-
- case BUS_NOTIFY_DEL_DEVICE:
- if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL)
- dmabounce_unregister_dev(&dev->dev);
- break;
- }
- return NOTIFY_OK;
-}
-
-static struct notifier_block sa1111_bus_notifier = {
- .notifier_call = sa1111_notifier_call,
-};
-#endif
-
static int __init sa1111_init(void)
{
int ret = bus_register(&sa1111_bus_type);
-#ifdef CONFIG_DMABOUNCE
- if (ret == 0)
- bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
-#endif
if (ret == 0)
platform_driver_register(&sa1111_device_driver);
return ret;
@@ -1458,9 +1398,6 @@ static int __init sa1111_init(void)
static void __exit sa1111_exit(void)
{
platform_driver_unregister(&sa1111_device_driver);
-#ifdef CONFIG_DMABOUNCE
- bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
-#endif
bus_unregister(&sa1111_bus_type);
}
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index e74c5bfdc6d3..9018c7240166 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -236,7 +236,7 @@ err_ioremap:
return ret;
}
-static int scoop_remove(struct platform_device *pdev)
+static void scoop_remove(struct platform_device *pdev)
{
struct scoop_dev *sdev = platform_get_drvdata(pdev);
@@ -246,13 +246,11 @@ static int scoop_remove(struct platform_device *pdev)
platform_set_drvdata(pdev, NULL);
iounmap(sdev->base);
kfree(sdev);
-
- return 0;
}
static struct platform_driver scoop_driver = {
.probe = scoop_probe,
- .remove = scoop_remove,
+ .remove_new = scoop_remove,
.suspend = scoop_suspend,
.resume = scoop_resume,
.driver = {
diff --git a/arch/arm/common/vlock.S b/arch/arm/common/vlock.S
index f1c7fd44f1b1..1fa09c4697ed 100644
--- a/arch/arm/common/vlock.S
+++ b/arch/arm/common/vlock.S
@@ -12,6 +12,8 @@
#include <linux/linkage.h>
#include "vlock.h"
+.arch armv7-a
+
/* Select different code if voting flags can fit in a single word. */
#if VLOCK_VOTING_SIZE > 4
#define FEW(x...)
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
index 4e49d6cb2f62..3f633eaf9770 100644
--- a/arch/arm/configs/am200epdkit_defconfig
+++ b/arch/arm/configs/am200epdkit_defconfig
@@ -1,24 +1,22 @@
CONFIG_LOCALVERSION="gum"
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_PREEMPT=y
CONFIG_EXPERT=y
# CONFIG_EPOLL is not set
# CONFIG_SHMEM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_PXA=y
CONFIG_ARCH_GUMSTIX=y
-CONFIG_PCCARD=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_SWAP is not set
+CONFIG_SLAB=y
+# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=m
CONFIG_UNIX=y
@@ -34,6 +32,7 @@ CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_H4=y
+CONFIG_PCCARD=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
@@ -47,14 +46,15 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PXA2XX=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_SD=m
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=m
CONFIG_PATA_PCMCIA=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_SMC91X=m
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
@@ -83,16 +83,15 @@ CONFIG_VFAT_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_RUBIN=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_USER=y
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_ARC4=m
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig
index 5d20057bdc43..a5c65d28ca63 100644
--- a/arch/arm/configs/aspeed_g4_defconfig
+++ b/arch/arm/configs/aspeed_g4_defconfig
@@ -1,5 +1,4 @@
CONFIG_KERNEL_XZ=y
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
@@ -8,6 +7,7 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZO is not set
@@ -17,9 +17,6 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_ASPEED=y
CONFIG_MACH_ASPEED_G4=y
@@ -27,17 +24,17 @@ CONFIG_VMSPLIT_2G=y
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
# CONFIG_ATAGS is not set
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_KEXEC=y
-CONFIG_FIRMWARE_MEMMAP=y
CONFIG_JUMP_LABEL=y
CONFIG_STRICT_KERNEL_RWX=y
-# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEBUG_FS is not set
# CONFIG_MQ_IOSCHED_DEADLINE is not set
# CONFIG_MQ_IOSCHED_KYBER is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLAB_FREELIST_HARDENED=y
+# CONFIG_COMPAT_BRK is not set
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
@@ -48,7 +45,11 @@ CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_DIAG is not set
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_VLAN_8021Q=y
@@ -57,16 +58,17 @@ CONFIG_NET_NCSI=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FIRMWARE_MEMMAP=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_PARTITIONED_MASTER=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_ASPEED_SMC=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=y
CONFIG_EEPROM_AT24=y
CONFIG_NETDEVICES=y
CONFIG_NETCONSOLE=y
@@ -88,9 +90,9 @@ CONFIG_FTGMAC100=y
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
-# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
@@ -134,6 +136,7 @@ CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_ASPEED=y
CONFIG_I2C_FSI=y
CONFIG_SPI=y
+CONFIG_SPI_ASPEED_SMC=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_ASPEED=y
@@ -145,6 +148,7 @@ CONFIG_SENSORS_ASPEED=y
CONFIG_SENSORS_IIO_HWMON=y
CONFIG_SENSORS_LM75=y
CONFIG_SENSORS_NCT7904=y
+CONFIG_SENSORS_OCC_P8_I2C=y
CONFIG_PMBUS=y
CONFIG_SENSORS_ADM1275=y
CONFIG_SENSORS_IBM_CFFPS=y
@@ -244,9 +248,8 @@ CONFIG_CRYPTO_USER_API_HASH=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_GDB_SCRIPTS=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig
index ae4f3c56ae6b..c7c11cbaa39d 100644
--- a/arch/arm/configs/aspeed_g5_defconfig
+++ b/arch/arm/configs/aspeed_g5_defconfig
@@ -1,5 +1,4 @@
CONFIG_KERNEL_XZ=y
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
@@ -8,6 +7,7 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZO is not set
@@ -17,9 +17,6 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_ASPEED=y
CONFIG_MACH_ASPEED_G5=y
@@ -36,13 +33,15 @@ CONFIG_KEXEC=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
-CONFIG_FIRMWARE_MEMMAP=y
CONFIG_JUMP_LABEL=y
-# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEBUG_FS is not set
# CONFIG_MQ_IOSCHED_DEADLINE is not set
# CONFIG_MQ_IOSCHED_KYBER is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLAB_FREELIST_HARDENED=y
+# CONFIG_COMPAT_BRK is not set
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
@@ -66,16 +65,17 @@ CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_VLAN_8021Q=y
CONFIG_NET_NCSI=y
+CONFIG_MCTP=y
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FIRMWARE_MEMMAP=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_PARTITIONED_MASTER=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_ASPEED_SMC=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_BLOCK=y
@@ -83,6 +83,8 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_NETCONSOLE=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
@@ -103,9 +105,9 @@ CONFIG_FTGMAC100=y
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
-# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
@@ -120,6 +122,8 @@ CONFIG_FTGMAC100=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_BROADCOM_PHY=y
CONFIG_REALTEK_PHY=y
+CONFIG_MCTP_SERIAL=y
+CONFIG_MCTP_TRANSPORT_I2C=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
@@ -147,6 +151,8 @@ CONFIG_IPMI_KCS_BMC_CDEV_IPMI=y
CONFIG_IPMI_KCS_BMC_SERIO=y
CONFIG_ASPEED_BT_IPMI_BMC=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX_GPIO=y
@@ -156,6 +162,7 @@ CONFIG_I2C_ASPEED=y
CONFIG_I2C_FSI=y
CONFIG_I2C_SLAVE=y
CONFIG_SPI=y
+CONFIG_SPI_ASPEED_SMC=y
CONFIG_SPI_FSI=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
@@ -180,6 +187,7 @@ CONFIG_SENSORS_IR38064=y
CONFIG_SENSORS_ISL68137=y
CONFIG_SENSORS_LM25066=y
CONFIG_SENSORS_MAX31785=y
+CONFIG_SENSORS_MP5023=y
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=y
CONFIG_SENSORS_SBTSI=y
@@ -200,6 +208,9 @@ CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_GADGET=y
CONFIG_USB_ASPEED_VHUB=y
CONFIG_USB_CONFIGFS=y
@@ -243,9 +254,13 @@ CONFIG_FSI_MASTER_ASPEED=y
CONFIG_FSI_SCOM=y
CONFIG_FSI_SBEFIFO=y
CONFIG_FSI_OCC=y
+CONFIG_PECI=y
+CONFIG_PECI_CPU=y
+CONFIG_PECI_ASPEED=y
CONFIG_EXT4_FS=y
CONFIG_FANOTIFY=y
CONFIG_OVERLAY_FS=y
+CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
# CONFIG_JFFS2_FS_WRITEBUFFER is not set
@@ -261,6 +276,9 @@ CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_FTRACE=y
CONFIG_PSTORE_RAM=y
# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_SECURITYFS is not set
CONFIG_HARDENED_USERCOPY=y
CONFIG_FORTIFY_SOURCE=y
CONFIG_CRYPTO_HMAC=y
@@ -273,9 +291,8 @@ CONFIG_CRYPTO_USER_API_HASH=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_DEBUG_INFO_REDUCED=y
CONFIG_GDB_SCRIPTS=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig
index 04c86ff558da..8ba8eb7a4adf 100644
--- a/arch/arm/configs/assabet_defconfig
+++ b/arch/arm/configs/assabet_defconfig
@@ -1,25 +1,21 @@
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_ASSABET=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttySA0,38400n8 initrd=0xc0800000,3M root=/dev/ram"
CONFIG_FPE_NWFPE=y
CONFIG_PM=y
+CONFIG_MODULES=y
+CONFIG_PARTITION_ADVANCED=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_SA1100_FIR=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_SA1100=y
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -46,11 +42,14 @@ CONFIG_FB=y
CONFIG_FB_SA1100=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_SOUND=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 549d01be0b47..82bcf4dc7f54 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -1,14 +1,13 @@
# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set
@@ -26,8 +25,9 @@ CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 r
CONFIG_KEXEC=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -40,7 +40,6 @@ CONFIG_IP_PNP_RARP=y
# CONFIG_INET_DIAG is not set
CONFIG_IPV6_SIT_6RD=y
CONFIG_CAN=y
-CONFIG_CAN_AT91=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_DEVTMPFS=y
@@ -50,13 +49,13 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_BLOCK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
@@ -65,6 +64,7 @@ CONFIG_ATMEL_SSC=y
CONFIG_EEPROM_AT24=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
@@ -80,6 +80,7 @@ CONFIG_DM9000=y
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_DAVICOM_PHY=y
CONFIG_MICREL_PHY=y
+CONFIG_CAN_AT91=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
@@ -138,9 +139,9 @@ CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ATMEL_ISI=y
+CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_MT9V032=m
CONFIG_DRM=y
CONFIG_DRM_ATMEL_HLCDC=y
CONFIG_DRM_PANEL_SIMPLE=y
@@ -195,7 +196,6 @@ CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y
CONFIG_AT_XDMAC=y
-CONFIG_MICROCHIP_PIT64B=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y
CONFIG_AT91_ADC=y
@@ -206,6 +206,7 @@ CONFIG_PWM_ATMEL_HLCDC_PWM=y
CONFIG_PWM_ATMEL_TCB=y
CONFIG_EXT4_FS=y
CONFIG_FANOTIFY=y
+CONFIG_AUTOFS_FS=m
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
@@ -216,6 +217,7 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_OFB=y
@@ -223,7 +225,6 @@ CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_DEV_ATMEL_AES=y
diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig
index 46075216ee6d..bfbaa2df3be5 100644
--- a/arch/arm/configs/axm55xx_defconfig
+++ b/arch/arm/configs/axm55xx_defconfig
@@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_FHANDLE=y
CONFIG_AUDIT=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
@@ -21,12 +22,8 @@ CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
-# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_AXXIA=y
-CONFIG_GPIO_PCA953X=y
CONFIG_ARM_LPAE=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_430973=y
@@ -37,26 +34,24 @@ CONFIG_ARM_ERRATA_754327=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_ARM_ERRATA_798181=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
CONFIG_PCIE_AXXIA=y
CONFIG_SMP=y
CONFIG_NR_CPUS=16
CONFIG_HOTPLUG_CPU=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_HIGHMEM=y
-CONFIG_KSM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_VFP=y
CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_MISC=y
-# CONFIG_SUSPEND is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_KSM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -76,6 +71,8 @@ CONFIG_INET_IPCOMP=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_BRIDGE=y
# CONFIG_WIRELESS is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
@@ -142,9 +139,10 @@ CONFIG_DP83640_PHY=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
-CONFIG_POWER_SUPPLY=y
+CONFIG_GPIO_PCA953X=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_AXXIA=y
+CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_ADT7475=y
CONFIG_SENSORS_JC42=y
CONFIG_SENSORS_LM75=y
@@ -224,8 +222,9 @@ CONFIG_NFS_FSCACHE=y
CONFIG_SUNRPC_DEBUG=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_XCBC=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
@@ -233,6 +232,5 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
deleted file mode 100644
index d9119da65f48..000000000000
--- a/arch/arm/configs/badge4_defconfig
+++ /dev/null
@@ -1,110 +0,0 @@
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_MODULES=y
-CONFIG_MODVERSIONS=y
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_BADGE4=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="init=/linuxrc root=/dev/mtdblock3"
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=y
-CONFIG_IRLAN=y
-CONFIG_IRCOMM=y
-CONFIG_IRDA_ULTRA=y
-CONFIG_SA1100_FIR=y
-CONFIG_BT=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIVHCI=m
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_SA1100=y
-CONFIG_PARPORT=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=y
-CONFIG_NETDEVICES=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_ELEKTOR=m
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_SA1100_WATCHDOG=m
-CONFIG_SOUND=y
-CONFIG_SOUND_PRIME=y
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=m
-CONFIG_MINIX_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index a9ed79b7f871..ce092abcd323 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -1,7 +1,8 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_LOG_BUF_SHIFT=18
@@ -19,19 +20,12 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
-# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
-CONFIG_JUMP_LABEL=y
CONFIG_CC_STACKPROTECTOR_REGULAR=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM2835=y
-CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
-CONFIG_KSM=y
-CONFIG_CMA=y
CONFIG_SECCOMP=y
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
@@ -44,9 +38,15 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPUFREQ_DT=y
CONFIG_ARM_RASPBERRYPI_CPUFREQ=y
CONFIG_VFP=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_SUSPEND is not set
CONFIG_PM=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_KSM=y
+CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -63,8 +63,7 @@ CONFIG_MAC80211=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
-CONFIG_DMA_CMA=y
-CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_CONSTANTS=y
@@ -106,8 +105,10 @@ CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_DRM=y
+CONFIG_DRM_V3D=y
CONFIG_DRM_VC4=y
-CONFIG_FB_SIMPLE=y
+CONFIG_DRM_SIMPLEDRM=y
+CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
@@ -151,7 +152,6 @@ CONFIG_BCM2835_MBOX=y
CONFIG_RASPBERRYPI_POWER=y
CONFIG_PWM=y
CONFIG_PWM_BCM2835=y
-CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
@@ -170,20 +170,22 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_LOCKUP_DETECTOR=y
-CONFIG_SCHED_TRACER=y
-CONFIG_STACK_TRACER=y
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_TEST_KSTRTOX=y
CONFIG_DEBUG_FS=y
CONFIG_KGDB=y
CONFIG_KGDB_KDB=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FUNCTION_PROFILER=y
+CONFIG_STACK_TRACER=y
+CONFIG_SCHED_TRACER=y
CONFIG_STRICT_DEVMEM=y
-# CONFIG_XZ_DEC_ARM is not set
-# CONFIG_XZ_DEC_ARMTHUMB is not set
+CONFIG_TEST_KSTRTOX=y
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig
deleted file mode 100644
index 3f910bbf1bfd..000000000000
--- a/arch/arm/configs/cerfcube_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_CERF=y
-CONFIG_SA1100_CERF_FLASH_16MB=y
-CONFIG_PCCARD=m
-CONFIG_PCMCIA_SA1100=m
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySA0,38400 root=/dev/mtdblock3 rootfstype=jffs2 rw mem=32M init=/linuxrc"
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_FPE_FASTFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_WATCHDOG=y
-CONFIG_SA1100_WATCHDOG=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_SMB_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 63a153f5cf68..adcee238822a 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -4,7 +4,6 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_LZMA=y
CONFIG_EMBEDDED=y
-CONFIG_SLOB=y
CONFIG_JUMP_LABEL=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_CLPS711X=y
@@ -14,16 +13,14 @@ CONFIG_ARCH_CLEP7312=y
CONFIG_ARCH_EDB7211=y
CONFIG_ARCH_P720T=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_COREDUMP is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_TINY=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
-CONFIG_IRDA=y
-CONFIG_IRTTY_SIR=y
# CONFIG_WIRELESS is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
deleted file mode 100644
index 45769d0ddd4e..000000000000
--- a/arch/arm/configs/cm_x300_defconfig
+++ /dev/null
@@ -1,163 +0,0 @@
-CONFIG_LOCALVERSION="-cm-x300"
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_MACH_CM_X300=y
-CONFIG_NO_HZ=y
-CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=ubifs console=ttyS2,38400"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_FPE_NWFPE=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_LIB80211=m
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_MARVELL=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=0
-CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_PXA27x=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_DA9034 is not set
-CONFIG_TOUCHSCREEN_WM97XX=m
-# CONFIG_TOUCHSCREEN_WM9705 is not set
-# CONFIG_TOUCHSCREEN_WM9713 is not set
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_GPIO=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_PMIC_DA903X=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DA903X=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_TDO24M=y
-CONFIG_BACKLIGHT_DA903X=m
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_PXA2XX_SOC_EM_X270=m
-CONFIG_HID_DRAGONRISE=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=m
-CONFIG_MMC_PXA=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_V3020=y
-CONFIG_RTC_DRV_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_UBIFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_T10DIF=y
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
deleted file mode 100644
index 63fa2eb21b75..000000000000
--- a/arch/arm/configs/cns3420vb_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_PERF_EVENTS is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_IOSCHED_BFQ=m
-CONFIG_ARCH_MULTI_V6=y
-#CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_CNS3XXX=y
-CONFIG_MACH_CNS3420VB=y
-CONFIG_DEBUG_CNS3XXX=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=20000
-CONFIG_BLK_DEV_SD=y
-CONFIG_ATA=y
-# CONFIG_SATA_PMP is not set
-# CONFIG_ATA_SFF is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FSCACHE=y
-CONFIG_TMPFS=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_ARM_UNWIND is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig
deleted file mode 100644
index 52bad9a544a0..000000000000
--- a/arch/arm/configs/colibri_pxa270_defconfig
+++ /dev/null
@@ -1,162 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_COLIBRI=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_VLAN_8021Q=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_CFG80211=y
-CONFIG_CONNECTOR=y
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_LE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_DISKONCHIP=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_ONENAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=8
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-CONFIG_HOSTAP=y
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_ATKBD=m
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_MOUSE_SERIAL=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_PXA=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_SERIAL=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_MMC=y
-CONFIG_NEW_LEDS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=1
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V4=y
-CONFIG_NLS_DEFAULT="iso8859-15"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=m
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_KEYS=y
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig
deleted file mode 100644
index 26e5a67f8e2d..000000000000
--- a/arch/arm/configs/colibri_pxa300_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_COLIBRI300=y
-CONFIG_AEABI=y
-CONFIG_CMDLINE="console=ttyS0,115200 rw"
-CONFIG_CPU_IDLE=y
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_SYN_COOKIES=y
-CONFIG_IPV6=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_AX88796=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_DEBUG_GPIO=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_PXA=y
-CONFIG_EXT3_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index 36384fd575f8..69341c33e0cc 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -1,4 +1,3 @@
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
@@ -6,22 +5,24 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_BASE_FULL is not set
# CONFIG_EPOLL is not set
-CONFIG_SLOB=y
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_COLLIE=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_PCMCIA_DEBUG=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="noinitrd root=/dev/mtdblock2 rootfstype=jffs2 fbcon=rotate:1"
CONFIG_FPE_NWFPE=y
CONFIG_PM=y
+# CONFIG_SWAP is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_TINY=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_SA1100=y
+CONFIG_PCMCIA_DEBUG=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
@@ -48,12 +49,12 @@ CONFIG_KEYBOARD_LOCOMO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_SERIO_SERPORT is not set
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CS=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
# CONFIG_HWMON is not set
CONFIG_MCP_SA11X0=y
CONFIG_MCP_UCB1200=y
@@ -64,8 +65,6 @@ CONFIG_FB_SA1100=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_LOCOMO=y
@@ -80,9 +79,11 @@ CONFIG_ROMFS_FS=y
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
+CONFIG_CRC_CCITT=y
+CONFIG_FONTS=y
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
deleted file mode 100644
index 15b749f6996d..000000000000
--- a/arch/arm/configs/corgi_defconfig
+++ /dev/null
@@ -1,253 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_PXA_SHARPSL=y
-CONFIG_MACH_POODLE=y
-CONFIG_MACH_CORGI=y
-CONFIG_MACH_SHEPHERD=y
-CONFIG_MACH_HUSKY=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_PXA2XX=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2 debug"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_INET=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_PXA_FICP=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIBTUART=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_SHARPSL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_ATA=y
-CONFIG_PATA_PCMCIA=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_PXA2XX=y
-CONFIG_FB=y
-CONFIG_FB_W100=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_CORGI=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_SOUND=y
-CONFIG_SOUND_PRIME=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SONY=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_USB=m
-CONFIG_USB_MON=m
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=y
-CONFIG_MMC_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=m
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index b58d45a03607..821d966c95a5 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -1,8 +1,8 @@
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -10,34 +10,16 @@ CONFIG_CGROUPS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V7=n
CONFIG_ARCH_MULTI_V5=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_DAVINCI=y
-CONFIG_ARCH_DAVINCI_DM644x=y
-CONFIG_ARCH_DAVINCI_DM355=y
-CONFIG_ARCH_DAVINCI_DM646x=y
CONFIG_ARCH_DAVINCI_DA830=y
CONFIG_ARCH_DAVINCI_DA850=y
-CONFIG_ARCH_DAVINCI_DM365=y
-CONFIG_MACH_SFFSDR=y
-CONFIG_MACH_NEUROS_OSD2=y
-CONFIG_MACH_DM355_LEOPARD=y
-CONFIG_MACH_MITYOMAPL138=y
-CONFIG_MACH_OMAPL138_HAWKBOARD=y
CONFIG_DAVINCI_MUX_DEBUG=y
CONFIG_DAVINCI_MUX_WARNINGS=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
-CONFIG_CMA=y
CONFIG_SECCOMP=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_AUTO_ZRELADDR=y
@@ -48,6 +30,13 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPUFREQ_DT=m
CONFIG_CPU_IDLE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_SWAP is not set
+CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -65,7 +54,6 @@ CONFIG_BT_HCIUART_LL=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_FW_LOADER=m
-CONFIG_DMA_CMA=y
CONFIG_DA8XX_MSTPRI=y
CONFIG_MTD=m
CONFIG_MTD_TESTS=m
@@ -95,8 +83,8 @@ CONFIG_NETCONSOLE=y
CONFIG_TUN=m
CONFIG_DM9000=y
CONFIG_TI_DAVINCI_EMAC=y
-CONFIG_LSI_ET1011C_PHY=y
CONFIG_LXT_PHY=y
+CONFIG_LSI_ET1011C_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_PPP=m
CONFIG_PPP_DEFLATE=m
@@ -113,7 +101,6 @@ CONFIG_KEYBOARD_XTKBD=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_DM355EVM=m
CONFIG_SERIO_LIBPS2=y
# CONFIG_VT_CONSOLE is not set
CONFIG_SERIAL_8250=y
@@ -141,7 +128,6 @@ CONFIG_SYSCON_REBOOT_MODE=m
CONFIG_BATTERY_LEGO_EV3=m
CONFIG_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=y
-CONFIG_MFD_DM355EVM_MSP=y
CONFIG_TPS6507X=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -262,10 +248,11 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=m
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_T10DIF=m
+CONFIG_DMA_CMA=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_USER=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_T10DIF=m
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 33074fdab2ea..c8d559f38f48 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -1,27 +1,23 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ARCH_MULTI_V6 is not set
+CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_DOVE=y
CONFIG_MACH_DOVE_DB=y
CONFIG_MACH_CM_A510=y
CONFIG_MACH_DOVE_DT=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MVEBU=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_VFP=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -31,6 +27,9 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MVEBU=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
@@ -51,6 +50,7 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_SATA_MV=y
@@ -115,15 +115,11 @@ CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SCHED_DEBUG is not set
CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
@@ -131,12 +127,16 @@ CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 88d5ecc2121e..3154125321c5 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -5,14 +5,9 @@ CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_MULTI_V4T=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_EP93XX=y
-CONFIG_MACH_ADSSPHERE=y
CONFIG_MACH_EDB9301=y
CONFIG_MACH_EDB9302=y
CONFIG_MACH_EDB9302A=y
@@ -21,19 +16,15 @@ CONFIG_MACH_EDB9307A=y
CONFIG_MACH_EDB9312=y
CONFIG_MACH_EDB9315=y
CONFIG_MACH_EDB9315A=y
-CONFIG_MACH_GESBC9312=y
-CONFIG_MACH_MICRO9H=y
-CONFIG_MACH_MICRO9M=y
-CONFIG_MACH_MICRO9L=y
-CONFIG_MACH_MICRO9S=y
-CONFIG_MACH_SIM_ONE=y
-CONFIG_MACH_SNAPPER_CL15=y
CONFIG_MACH_TS72XX=y
CONFIG_MACH_VISION_EP9307=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/nfs ip=bootp"
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -50,8 +41,8 @@ CONFIG_IPV6=y
# CONFIG_IPV6_SIT is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -66,6 +57,7 @@ CONFIG_EEPROM_LEGACY=y
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_NETDEVICES=y
CONFIG_EP93XX_ETH=y
CONFIG_USB_RTL8150=y
@@ -122,6 +114,7 @@ CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
+CONFIG_LIBCRC32C=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_SLAB=y
CONFIG_DEBUG_SPINLOCK=y
@@ -129,4 +122,3 @@ CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
deleted file mode 100644
index 046f4dc2e18e..000000000000
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ /dev/null
@@ -1,105 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_ARCH_PXA_ESERIES=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_IWMMXT=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_KEXEC=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=y
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_PXA_FICP=y
-CONFIG_CFG80211=m
-CONFIG_MAC80211=m
-CONFIG_MAC80211_RC_PID=y
-# CONFIG_MAC80211_RC_MINSTREL is not set
-# CONFIG_STANDALONE is not set
-CONFIG_MTD=m
-CONFIG_MTD_RAW_NAND=m
-CONFIG_MTD_NAND_TMIO=m
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=m
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_PCMCIA=m
-CONFIG_NETDEVICES=y
-CONFIG_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_NET_PCMCIA=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_WM97XX=m
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_PXA=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_MFD_T7L66XB=y
-CONFIG_MFD_TC6387XB=y
-CONFIG_MFD_TC6393XB=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_FB_W100=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_SOUND=y
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-# CONFIG_SND_PCMCIA is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_PXA2XX_SOC_E800=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_TMIO=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index aa061074db78..b0f0baa3a6c4 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_CGROUPS=y
@@ -13,12 +13,9 @@ CONFIG_BIG_LITTLE=y
CONFIG_NR_CPUS=8
CONFIG_HIGHMEM=y
CONFIG_SECCOMP=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
-CONFIG_ENERGY_MODEL=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
@@ -34,12 +31,7 @@ CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA256_ARM=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_ENERGY_MODEL=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
@@ -170,8 +162,6 @@ CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_MFD_CROS_EC_DEV=y
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CROS_EC=y
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77686=y
CONFIG_MFD_MAX77693=y
@@ -207,19 +197,19 @@ CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m
CONFIG_VIDEO_S5P_FIMC=m
CONFIG_VIDEO_S5P_MIPI_CSIS=m
CONFIG_VIDEO_EXYNOS_FIMC_LITE=m
CONFIG_VIDEO_EXYNOS4_FIMC_IS=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
-CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIVID=m
-CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5C73M3=m
+CONFIG_VIDEO_S5K6A3=m
CONFIG_DRM=y
CONFIG_DRM_EXYNOS=y
CONFIG_DRM_EXYNOS_FIMD=y
@@ -295,11 +285,11 @@ CONFIG_MMC_DW_EXYNOS=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
-CONFIG_LEDS_AAT1290=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
-CONFIG_LEDS_MAX77693=y
CONFIG_LEDS_MAX8997=y
+CONFIG_LEDS_AAT1290=y
+CONFIG_LEDS_MAX77693=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MAX8998=y
@@ -309,6 +299,8 @@ CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_S3C=y
CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_SPI=y
CONFIG_COMMON_CLK_MAX77686=y
@@ -319,12 +311,12 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
-CONFIG_EXYNOS5422_DMC=y
CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y
CONFIG_EXTCON=y
CONFIG_EXTCON_MAX14577=y
CONFIG_EXTCON_MAX77693=y
CONFIG_EXTCON_MAX8997=y
+CONFIG_EXYNOS5422_DMC=y
CONFIG_IIO=y
CONFIG_EXYNOS_ADC=y
CONFIG_STMPE_ADC=y
@@ -367,6 +359,11 @@ CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA256_ARM=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_DEV_EXYNOS_RNG=y
CONFIG_CRYPTO_DEV_S5P=y
CONFIG_CRC_CCITT=y
@@ -376,10 +373,10 @@ CONFIG_FONTS=y
CONFIG_FONT_7x14=y
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_DETECT_HUNG_TASK is not set
CONFIG_PROVE_LOCKING=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
deleted file mode 100644
index 0788a892e160..000000000000
--- a/arch/arm/configs/ezx_defconfig
+++ /dev/null
@@ -1,390 +0,0 @@
-CONFIG_LOCALVERSION="-ezx200910312315"
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_PXA_EZX=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
-CONFIG_KEXEC=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_CPU_IDLE=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_BRIDGE=m
-CONFIG_BT=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-# CONFIG_WIRELESS is not set
-CONFIG_FW_LOADER=m
-CONFIG_CONNECTOR=m
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_OTP=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-# CONFIG_WLAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_PXA27x=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_PCAP=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_INPUT_PCAP=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=8
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_PXA2XX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_EZX_PCAP=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_PCAP=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_MEDIA_TUNER_CUSTOMISE=y
-# CONFIG_MEDIA_TUNER_SIMPLE is not set
-# CONFIG_MEDIA_TUNER_TDA8290 is not set
-# CONFIG_MEDIA_TUNER_TDA827X is not set
-# CONFIG_MEDIA_TUNER_TDA18271 is not set
-# CONFIG_MEDIA_TUNER_TDA9887 is not set
-# CONFIG_MEDIA_TUNER_TEA5761 is not set
-# CONFIG_MEDIA_TUNER_TEA5767 is not set
-# CONFIG_MEDIA_TUNER_MT20XX is not set
-# CONFIG_MEDIA_TUNER_MT2060 is not set
-# CONFIG_MEDIA_TUNER_MT2266 is not set
-# CONFIG_MEDIA_TUNER_MT2131 is not set
-# CONFIG_MEDIA_TUNER_QT1010 is not set
-# CONFIG_MEDIA_TUNER_XC2028 is not set
-# CONFIG_MEDIA_TUNER_XC5000 is not set
-# CONFIG_MEDIA_TUNER_MXL5005S is not set
-# CONFIG_MEDIA_TUNER_MXL5007T is not set
-# CONFIG_MEDIA_TUNER_MC44S803 is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-CONFIG_VIDEO_PXA27x=y
-# CONFIG_V4L_USB_DRIVERS is not set
-CONFIG_RADIO_TEA5764=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_OVERLAY=y
-CONFIG_FB_PXA_PARAMETERS=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_PXA2XX_SOC=y
-# CONFIG_USB_HID is not set
-CONFIG_HID_APPLE=m
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_PXA27X=y
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_MMC=y
-CONFIG_SDIO_UART=m
-CONFIG_MMC_PXA=y
-CONFIG_MMC_SPI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_LP3944=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PCAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=m
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_XFS_FS=m
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_ROMFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_PROVE_LOCKING=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig
index 7a32de51f0fa..87c489337d0e 100644
--- a/arch/arm/configs/footbridge_defconfig
+++ b/arch/arm/configs/footbridge_defconfig
@@ -4,18 +4,17 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_HOTPLUG is not set
-CONFIG_MODULES=y
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_FOOTBRIDGE=y
-CONFIG_ARCH_CATS=y
CONFIG_ARCH_EBSA285_HOST=y
CONFIG_ARCH_NETWINDER=y
-CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
-CONFIG_BINFMT_AOUT=y
+CONFIG_MODULES=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ACORN_PARTITION=y
+CONFIG_ACORN_PARTITION_ADFS=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -26,15 +25,6 @@ CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
CONFIG_ATM=y
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_IRDA_DEBUG=y
-CONFIG_WINBOND_FIR=m
CONFIG_PARPORT=y
CONFIG_PARPORT_PC=y
CONFIG_PARPORT_PC_FIFO=y
@@ -71,17 +61,17 @@ CONFIG_VORTEX=y
CONFIG_NET_PCI=y
CONFIG_NE2K_PCI=y
CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
CONFIG_PPPOE=m
+CONFIG_PPP_ASYNC=m
CONFIG_SLIP=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_21285=y
CONFIG_SERIAL_21285_CONSOLE=y
+CONFIG_SERIAL_NONSTANDARD=y
CONFIG_PRINTER=m
CONFIG_DS1620=y
CONFIG_NWBUTTON=y
@@ -99,6 +89,10 @@ CONFIG_SOUND=m
CONFIG_USB=m
CONFIG_USB_MON=m
CONFIG_USB_PRINTER=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_EXT2_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_ISO9660_FS=m
@@ -109,9 +103,6 @@ CONFIG_ADFS_FS=m
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ADFS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_850=m
diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig
index a7acfee11ffc..592a6e6024d4 100644
--- a/arch/arm/configs/gemini_defconfig
+++ b/arch/arm/configs/gemini_defconfig
@@ -49,11 +49,13 @@ CONFIG_ATA=y
CONFIG_PATA_FTIDE010=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
+CONFIG_NET_DSA_REALTEK=y
CONFIG_NET_DSA_REALTEK_SMI=y
+CONFIG_NET_DSA_REALTEK_RTL8366RB=y
CONFIG_GEMINI_ETHERNET=y
+CONFIG_MARVELL_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
-CONFIG_MARVELL_PHY=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@@ -66,6 +68,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
+CONFIG_SENSORS_DRIVETEMP=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_LM75=y
CONFIG_THERMAL=y
@@ -80,9 +83,9 @@ CONFIG_LOGO=y
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_FOTG210_HCD=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_FOTG210_HCD=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index c02b3e409610..4e272875c797 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -1,28 +1,23 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_H3600=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_CPU_FREQ_STAT is not set
CONFIG_FPE_NWFPE=y
+CONFIG_MODULES=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
# CONFIG_WIRELESS is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_SA1100=y
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -36,6 +31,7 @@ CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
CONFIG_PATA_PCMCIA=y
CONFIG_NETDEVICES=y
diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig
deleted file mode 100644
index f5a338fefda8..000000000000
--- a/arch/arm/configs/h5000_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_H5000=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="keepinitrd"
-CONFIG_KEXEC=y
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=32
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_SA1100=y
-CONFIG_EXT2_FS=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
deleted file mode 100644
index 742d18cdabde..000000000000
--- a/arch/arm/configs/hackkit_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_HACKKIT=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySA0,115200 root=/dev/ram0 initrd=0xc0400000,8M init=/rootshell"
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=3
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 74d611e41e02..0376a65e8bc1 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -1,24 +1,25 @@
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_LZMA=y
CONFIG_ARCH_HISI=y
CONFIG_ARCH_HI3xxx=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_ARCH_HIX5HD2=y
CONFIG_ARCH_HIP01=y
CONFIG_ARCH_HIP04=y
+CONFIG_ARCH_HIX5HD2=y
CONFIG_SMP=y
CONFIG_NR_CPUS=16
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
CONFIG_PM=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -39,20 +40,20 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_PINCTRL_SINGLE=y
-CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIOLIB=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_REGULATOR_GPIO=y
+CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_DWAPB=y
CONFIG_MFD_SYSCON=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_DRM=y
CONFIG_FB_SIMPLE=y
@@ -66,13 +67,13 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_MMC=y
-CONFIG_RTC_CLASS=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
+CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_DMADEVICES=y
-CONFIG_DW_DMAC=y
CONFIG_PL330_DMA=y
+CONFIG_DW_DMAC=y
CONFIG_PWM=y
CONFIG_PHY_HIX5HD2_SATA=y
CONFIG_EXT4_FS=y
@@ -81,11 +82,10 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_KERNEL=y
CONFIG_LOCKUP_DETECTOR=y
-CONFIG_VFP=y
CONFIG_VFPv3=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
deleted file mode 100644
index 015b7ef237de..000000000000
--- a/arch/arm/configs/imote2_defconfig
+++ /dev/null
@@ -1,365 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_INTELMOTE2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS2,115200 mem=32M"
-CONFIG_KEXEC=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_BRIDGE=m
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-CONFIG_IEEE802154=y
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_FW_LOADER=m
-CONFIG_CONNECTOR=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
-CONFIG_MTD_AR7_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_OTP=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-# CONFIG_WLAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_PXA27x=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=8
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_PXA2XX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_HWMON is not set
-CONFIG_PMIC_DA903X=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_DA903X=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_MEDIA_TUNER_CUSTOMISE=y
-# CONFIG_MEDIA_TUNER_SIMPLE is not set
-# CONFIG_MEDIA_TUNER_TDA8290 is not set
-# CONFIG_MEDIA_TUNER_TDA827X is not set
-# CONFIG_MEDIA_TUNER_TDA18271 is not set
-# CONFIG_MEDIA_TUNER_TDA9887 is not set
-# CONFIG_MEDIA_TUNER_TEA5761 is not set
-# CONFIG_MEDIA_TUNER_TEA5767 is not set
-# CONFIG_MEDIA_TUNER_MT20XX is not set
-# CONFIG_MEDIA_TUNER_MT2060 is not set
-# CONFIG_MEDIA_TUNER_MT2266 is not set
-# CONFIG_MEDIA_TUNER_MT2131 is not set
-# CONFIG_MEDIA_TUNER_QT1010 is not set
-# CONFIG_MEDIA_TUNER_XC2028 is not set
-# CONFIG_MEDIA_TUNER_XC5000 is not set
-# CONFIG_MEDIA_TUNER_MXL5005S is not set
-# CONFIG_MEDIA_TUNER_MXL5007T is not set
-# CONFIG_MEDIA_TUNER_MC44S803 is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-CONFIG_VIDEO_PXA27x=y
-# CONFIG_V4L_USB_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_OVERLAY=y
-CONFIG_FB_PXA_PARAMETERS=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_PXA2XX_SOC=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_PXA27X=y
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_MMC=y
-CONFIG_SDIO_UART=m
-CONFIG_MMC_PXA=y
-CONFIG_MMC_SPI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_LP3944=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=m
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_ROMFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_PROVE_LOCKING=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC16=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 1d9fa77bbafc..c9a602aee715 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -1,15 +1,12 @@
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y
@@ -24,13 +21,13 @@ CONFIG_SOC_IMX1=y
CONFIG_SOC_IMX25=y
CONFIG_SOC_IMX27=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_PM_DEBUG=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB=y
+# CONFIG_COMPAT_BRK is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -63,6 +60,7 @@ CONFIG_MTD_UBI=y
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
CONFIG_PATA_IMX=y
CONFIG_NETDEVICES=y
@@ -162,7 +160,7 @@ CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
CONFIG_DMADEVICES=y
CONFIG_IMX_DMA=y
-CONFIG_IMX_SDMA=y
+CONFIG_IMX_SDMA=m
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y
CONFIG_FSL_MX25_ADC=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f7498df08dfe..4de293da4789 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -1,6 +1,6 @@
CONFIG_KERNEL_LZO=y
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BPF_SYSCALL=y
CONFIG_PREEMPT_VOLUNTARY=y
@@ -13,8 +13,6 @@ CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX31=y
@@ -33,7 +31,7 @@ CONFIG_SOC_VF610=y
CONFIG_SMP=y
CONFIG_ARM_PSCI=y
CONFIG_HIGHMEM=y
-CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_ARCH_FORCE_MAX_ORDER=13
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_KEXEC=y
CONFIG_CPU_FREQ=y
@@ -58,6 +56,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_BINFMT_MISC=m
+# CONFIG_COMPAT_BRK is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -66,7 +65,6 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_NETFILTER=y
CONFIG_CAN=y
-CONFIG_CAN_FLEXCAN=y
CONFIG_BT=y
CONFIG_BT_BNEP=m
CONFIG_BT_HCIUART=y
@@ -78,7 +76,7 @@ CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
-CONFIG_PCI_IMX6=y
+CONFIG_PCI_IMX6_HOST=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
@@ -130,6 +128,7 @@ CONFIG_CS89x0_PLATFORM=y
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_QCA7000_SPI=m
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_SMC91X=y
CONFIG_SMC911X=y
@@ -137,6 +136,7 @@ CONFIG_SMSC911X=y
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_MICREL_PHY=y
CONFIG_AT803X_PHY=y
+CONFIG_CAN_FLEXCAN=y
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=y
@@ -167,6 +167,7 @@ CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_TOUCHSCREEN_AD7879=y
CONFIG_TOUCHSCREEN_AD7879_I2C=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_CYTTSP5=y
CONFIG_TOUCHSCREEN_DA9052=y
CONFIG_TOUCHSCREEN_EGALAX=y
CONFIG_TOUCHSCREEN_GOODIX=y
@@ -213,8 +214,12 @@ CONFIG_GPIO_SIOX=m
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_BD71815=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_74X164=y
+CONFIG_W1=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_SLAVE_THERM=m
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
@@ -223,6 +228,8 @@ CONFIG_RN5T618_POWER=m
CONFIG_SENSORS_MC13783_ADC=y
CONFIG_SENSORS_GPIO_FAN=y
CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_PWM_FAN=y
+CONFIG_SENSORS_SY7636A=y
CONFIG_THERMAL_STATISTICS=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_CPU_THERMAL=y
@@ -238,10 +245,13 @@ CONFIG_MFD_DA9062=y
CONFIG_MFD_DA9063=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_MFD_MC13XXX_I2C=y
+CONFIG_MFD_SY7636A=y
CONFIG_MFD_RN5T618=y
CONFIG_MFD_STMPE=y
+CONFIG_MFD_ROHM_BD71828=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_BD71815=y
CONFIG_REGULATOR_DA9052=y
CONFIG_REGULATOR_DA9062=y
CONFIG_REGULATOR_DA9063=y
@@ -251,6 +261,7 @@ CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_REGULATOR_RN5T618=y
+CONFIG_REGULATOR_SY7636A=y
CONFIG_RC_CORE=y
CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=y
@@ -258,16 +269,17 @@ CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_MUX=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_MUX=y
CONFIG_VIDEO_CODA=m
CONFIG_VIDEO_IMX_PXP=y
-CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
+CONFIG_VIDEO_ADV7180=m
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
+CONFIG_DRM_I2C_NXP_TDA998X=y
CONFIG_DRM_MSM=y
CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y
@@ -377,6 +389,7 @@ CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_PCF8523=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_M41T80=y
+CONFIG_RTC_DRV_BD70528=y
CONFIG_RTC_DRV_RC5T619=y
CONFIG_RTC_DRV_RV3029C2=y
CONFIG_RTC_DRV_DA9063=y
@@ -393,15 +406,19 @@ CONFIG_STAGING=y
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_IMX_MEDIA=y
CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_BD718XX=y
CONFIG_CLK_IMX8MM=y
CONFIG_CLK_IMX8MN=y
CONFIG_CLK_IMX8MP=y
CONFIG_CLK_IMX8MQ=y
CONFIG_SOC_IMX8M=y
+CONFIG_EXTCON_USB_GPIO=y
CONFIG_IIO=y
+CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_MMA8452=y
CONFIG_IMX7D_ADC=y
CONFIG_RN5T618_ADC=y
+CONFIG_STMPE_ADC=y
CONFIG_VF610_ADC=y
CONFIG_SENSORS_ISL29018=y
CONFIG_MAG3110=y
@@ -411,8 +428,8 @@ CONFIG_PWM_FSL_FTM=y
CONFIG_PWM_IMX27=y
CONFIG_PWM_IMX_TPM=y
CONFIG_NVMEM_IMX_OCOTP=y
-CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_NVMEM_SNVS_LPGPR=y
+CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MUX_MMIO=y
@@ -467,6 +484,6 @@ CONFIG_PRINTK_TIME=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
+# CONFIG_SLUB_DEBUG is not set
# CONFIG_SCHED_DEBUG is not set
-CONFIG_PROVE_LOCKING=y
# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 5b485722ccf9..61711d4bbf74 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
@@ -81,5 +81,5 @@ CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
deleted file mode 100644
index de2cc6759cae..000000000000
--- a/arch/arm/configs/iop32x_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_IOP32X=y
-CONFIG_MACH_GLANTANK=y
-CONFIG_ARCH_IQ80321=y
-CONFIG_ARCH_IQ31244=y
-CONFIG_MACH_N2100=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IPV6=y
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-# CONFIG_IPV6_SIT is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_ATA=y
-CONFIG_SATA_SIL=y
-CONFIG_SATA_VITESSE=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_RAID0=y
-CONFIG_MD_RAID1=y
-CONFIG_MD_RAID10=y
-CONFIG_MD_RAID456=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-CONFIG_E100=y
-CONFIG_E1000=y
-CONFIG_R8169=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IOP3XX=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_RS5C372=y
-CONFIG_DMADEVICES=y
-CONFIG_INTEL_IOP_ADMA=y
-CONFIG_NET_DMA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_TMPFS=y
-CONFIG_ECRYPT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_UART_8250=y
-CONFIG_KEYS=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_LRW=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ANUBIS=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_CAST5=y
-CONFIG_CRYPTO_CAST6=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_KHAZAD=y
-CONFIG_CRYPTO_SERPENT=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index 9a7667383df9..3cb995b9616a 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -1,36 +1,21 @@
+CONFIG_KERNEL_XZ=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_COMPRESSION_XZ=y
CONFIG_EXPERT=y
-CONFIG_MODULES=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_IXP4XX=y
-CONFIG_MACH_NSLU2=y
-CONFIG_MACH_AVILA=y
-CONFIG_MACH_LOFT=y
-CONFIG_ARCH_ADI_COYOTE=y
-CONFIG_MACH_GATEWAY7001=y
-CONFIG_MACH_WG302V2=y
-CONFIG_ARCH_IXDP425=y
-CONFIG_MACH_IXDPG425=y
-CONFIG_MACH_IXDP465=y
-CONFIG_MACH_KIXRP435=y
-CONFIG_ARCH_PRPMC1100=y
-CONFIG_MACH_NAS100D=y
-CONFIG_MACH_DSMG600=y
-CONFIG_MACH_FSG=y
-CONFIG_MACH_GTWX5715=y
-CONFIG_IXP4XX_QMGR=y
-CONFIG_IXP4XX_NPE=y
-# CONFIG_ARM_THUMB is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp root=/dev/nfs"
-CONFIG_FPE_NWFPE=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_MODULES=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -43,8 +28,6 @@ CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
@@ -65,7 +48,6 @@ CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
@@ -76,14 +58,12 @@ CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
-CONFIG_IPX=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_X25=m
CONFIG_LAPB=m
-CONFIG_WAN_ROUTER=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
@@ -104,91 +84,92 @@ CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_PKTGEN=m
+CONFIG_DEVTMPFS=y
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_IXP4XX=y
+CONFIG_MTD_PHYSMAP_IXP4XX=y
CONFIG_MTD_RAW_NAND=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_EEPROM_LEGACY=y
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
-CONFIG_SATA_VIA=y
-CONFIG_PATA_ARTOP=y
-CONFIG_PATA_CMD64X=y
-CONFIG_PATA_HPT366=y
-CONFIG_PATA_HPT37X=y
-CONFIG_PATA_HPT3X2N=y
-CONFIG_PATA_PDC2027X=y
CONFIG_PATA_IXP4XX_CF=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
+CONFIG_ATM_TCP=m
CONFIG_IXP4XX_ETH=y
-CONFIG_NET_PCI=y
CONFIG_WAN=y
-CONFIG_HDLC=m
+CONFIG_HDLC=y
CONFIG_HDLC_RAW=m
CONFIG_HDLC_CISCO=m
CONFIG_HDLC_FR=m
CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_WAN_ROUTER_DRIVERS=m
-CONFIG_ATM_TCP=m
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_IXP4XX_HSS=m
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_MISC=y
-CONFIG_INPUT_IXP4XX_BEEPER=y
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_I2C=y
+CONFIG_HW_RANDOM=y
CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_GPIO_GW_PLD=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_SENSORS_AD7418=y
CONFIG_SENSORS_W83781D=y
CONFIG_WATCHDOG=y
CONFIG_IXP4XX_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_UHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_FSG=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1672=y
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_X1205=y
CONFIG_RTC_DRV_PCF8563=y
+CONFIG_IXP4XX_QMGR=y
+CONFIG_IXP4XX_NPE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_OVERLAY_FS=y
CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
CONFIG_JFFS2_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
+CONFIG_CRYPTO_DEV_IXP4XX=y
CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_FS=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_UART_8250=y
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index 069f60ffdcd8..91bdcc095884 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -1,18 +1,14 @@
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_JORNADA720=y
CONFIG_SA1100_JORNADA720_SSP=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
CONFIG_PM=y
+CONFIG_MODULES=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -20,13 +16,12 @@ CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_SA1100_FIR=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_SA1100=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
CONFIG_PATA_PCMCIA=y
CONFIG_NETDEVICES=y
@@ -40,9 +35,9 @@ CONFIG_KEYBOARD_HP7XX=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_HP7XX=y
+CONFIG_LEGACY_PTY_COUNT=32
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=32
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_S1D13XXX=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index b1bcb858216b..d7a0bca641eb 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -1,43 +1,41 @@
-# CONFIG_SWAP is not set
CONFIG_POSIX_MQUEUE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_BLK_CGROUP=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_ALL=y
# CONFIG_ELF_CORE is not set
# CONFIG_BASE_FULL is not set
+CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARM_LPAE=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
CONFIG_PCI_KEYSTONE=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_ARM_PSCI=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_CMA=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_SUSPEND is not set
CONFIG_PM=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_SWAP is not set
+CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -111,11 +109,11 @@ CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP_SCTP=y
CONFIG_VLAN_8021Q=y
CONFIG_CAN=m
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_CMA=y
+CONFIG_TI_SCI_PROTOCOL=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -131,10 +129,17 @@ CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
+CONFIG_TI_CPTS=y
CONFIG_TI_KEYSTONE_NETCP=y
CONFIG_TI_KEYSTONE_NETCP_ETHSS=y
-CONFIG_TI_CPTS=y
CONFIG_MARVELL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_DP83867_PHY=y
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_GPIO_DECODER=m
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
@@ -144,17 +149,18 @@ CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DAVINCI=y
CONFIG_SPI=y
+CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_SPI_DAVINCI=y
CONFIG_SPI_SPIDEV=y
-CONFIG_PTP_1588_CLOCK=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DAVINCI=y
CONFIG_GPIO_SYSCON=y
-CONFIG_POWER_SUPPLY=y
+CONFIG_GPIO_PCA953X=m
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_KEYSTONE=y
+CONFIG_POWER_SUPPLY=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=y
@@ -166,8 +172,8 @@ CONFIG_USB_MON=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
-CONFIG_NOP_USB_XCEIV=y
CONFIG_KEYSTONE_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
@@ -180,6 +186,8 @@ CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y
@@ -196,7 +204,6 @@ CONFIG_PWM_TIECAP=m
CONFIG_KEYSTONE_IRQ=y
CONFIG_RESET_TI_SCI=m
CONFIG_RESET_TI_SYSCON=m
-CONFIG_TI_SCI_PROTOCOL=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_FANOTIFY=y
@@ -216,25 +223,17 @@ CONFIG_NFSD=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
-CONFIG_SPI_CADENCE_QUADSPI=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_GPIO_PCA953X=m
-CONFIG_LEDS_TRIGGER_ACTIVITY=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_MICREL_PHY=y
-CONFIG_DP83867_PHY=y
+CONFIG_DMA_CMA=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig
deleted file mode 100644
index 2dfa33d7dca3..000000000000
--- a/arch/arm/configs/lart_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_LART=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySA0,9600 root=/dev/ram"
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_DEBUG=y
-CONFIG_SA1100_FIR=m
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_LART=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=m
-CONFIG_REISERFS_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=1
-CONFIG_CRAMFS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFSD=m
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_USER=y
-CONFIG_CRC32=m
diff --git a/arch/arm/configs/lpae.config b/arch/arm/configs/lpae.config
new file mode 100644
index 000000000000..a6d6f7ab3c01
--- /dev/null
+++ b/arch/arm/configs/lpae.config
@@ -0,0 +1,2 @@
+CONFIG_ARM_LPAE=y
+CONFIG_VMSPLIT_2G=y
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
index be882ea0eee4..56eae6a0a311 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -15,8 +15,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
# CONFIG_MMU is not set
CONFIG_ARCH_LPC18XX=y
CONFIG_SET_MEM_PARAM=y
@@ -24,14 +22,11 @@ CONFIG_DRAM_BASE=0x28000000
CONFIG_DRAM_SIZE=0x02000000
CONFIG_FLASH_MEM_BASE=0x1b000000
CONFIG_FLASH_SIZE=0x00080000
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
# CONFIG_COREDUMP is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -61,6 +56,7 @@ CONFIG_SRAM=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
@@ -93,11 +89,11 @@ CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_LPC2K=y
CONFIG_SPI=y
@@ -154,11 +150,12 @@ CONFIG_JFFS2_FS=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_FS=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SLUB_DEBUG is not set
# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 6c3e4a141963..fabb66a53350 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
@@ -10,12 +10,9 @@ CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_LPC32XX=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
@@ -24,9 +21,9 @@ CONFIG_VFP=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -60,6 +57,7 @@ CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
@@ -93,11 +91,11 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PNX=y
-CONFIG_GPIO_LPC32XX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_LPC32XX=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCF857X=y
CONFIG_SENSORS_DS620=y
@@ -187,10 +185,10 @@ CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRC_CCITT=y
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_GDB_SCRIPTS=y
-CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=5
# CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
deleted file mode 100644
index 3a4d0e64cd6e..000000000000
--- a/arch/arm/configs/lpd270_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_LOGICPD_PXA270=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IPV6=y
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-# CONFIG_IPV6_SIT is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_PXA2XX_AC97=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
deleted file mode 100644
index 4ce2da2e76fa..000000000000
--- a/arch/arm/configs/lubbock_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
-CONFIG_ARCH_LUBBOCK=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_PXA2XX=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_SA1111=y
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_G_SERIAL=m
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
deleted file mode 100644
index abde1fb23b20..000000000000
--- a/arch/arm/configs/magician_defconfig
+++ /dev/null
@@ -1,160 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_H4700=y
-CONFIG_MACH_MAGICIAN=y
-CONFIG_NO_HZ=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="keepinitrd"
-CONFIG_KEXEC=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_IRDA_DEBUG=y
-CONFIG_IRTTY_SIR=m
-CONFIG_PXA_FICP=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NETDEVICES=y
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_PXA=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_PXA=y
-CONFIG_W1_MASTER_DS1WM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PDA_POWER=y
-CONFIG_BATTERY_DS2760=y
-# CONFIG_HWMON is not set
-CONFIG_MFD_ASIC3=y
-CONFIG_HTC_EGPIO=y
-CONFIG_HTC_PASIC3=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_OVERLAY=y
-CONFIG_FB_W100=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_SOUND=y
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_USB=y
-CONFIG_USB_MON=m
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_USB_PXA27X=y
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_MMC=y
-CONFIG_SDIO_UART=m
-CONFIG_MMC_PXA=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DEBUG=y
-CONFIG_RTC_DRV_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
deleted file mode 100644
index 26499b697f9f..000000000000
--- a/arch/arm/configs/mainstone_defconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_MAINSTONE=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig
index 7c07f9893a0f..385ad0f391a8 100644
--- a/arch/arm/configs/milbeaut_m10v_defconfig
+++ b/arch/arm/configs/milbeaut_m10v_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
@@ -26,7 +26,7 @@ CONFIG_THUMB2_KERNEL=y
# CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 is not set
# CONFIG_ARM_PATCH_IDIV is not set
CONFIG_HIGHMEM=y
-CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_ARCH_FORCE_MAX_ORDER=11
CONFIG_SECCOMP=y
CONFIG_KEXEC=y
CONFIG_EFI=y
@@ -44,19 +44,6 @@ CONFIG_ARM_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
-CONFIG_EFI_VARS=m
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA1_ARM_CE=m
-CONFIG_CRYPTO_SHA2_ARM_CE=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_AES_ARM_CE=m
-CONFIG_CRYPTO_GHASH_ARM_CE=m
-CONFIG_CRYPTO_CRC32_ARM_CE=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
@@ -64,8 +51,7 @@ CONFIG_CMDLINE_PARTITION=y
CONFIG_CMA=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_CMA=y
-CONFIG_CMA_SIZE_MBYTES=64
+CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_OF_OVERLAY=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -109,11 +95,23 @@ CONFIG_NLS_UTF8=y
CONFIG_KEYS=y
CONFIG_CRYPTO_MANAGER=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
-CONFIG_CRYPTO_SEQIV=m
# CONFIG_CRYPTO_ECHAINIV is not set
CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA1_ARM_CE=m
+CONFIG_CRYPTO_SHA2_ARM_CE=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_AES_ARM_CE=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_CRC32_ARM_CE=m
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC_ITU_T=m
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=64
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
deleted file mode 100644
index 898490aaa39e..000000000000
--- a/arch/arm/configs/mini2440_defconfig
+++ /dev/null
@@ -1,334 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_ARCH_S3C24XX=y
-CONFIG_S3C_ADC=y
-CONFIG_S3C24XX_PWM=y
-# CONFIG_CPU_S3C2410 is not set
-CONFIG_CPU_S3C2440=y
-CONFIG_MACH_MINI2440=y
-CONFIG_AEABI=y
-CONFIG_KEXEC=y
-CONFIG_CPU_IDLE=y
-CONFIG_APM_EMULATION=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_BINFMT_MISC=m
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_NET_KEY=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_DIAG=m
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_NET_PKTGEN=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_CFG80211=m
-CONFIG_MAC80211=m
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-CONFIG_CONNECTOR=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_FTL=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=y
-CONFIG_RFD_FTL=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_S3C2410=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_MTD_LPDDR=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=m
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_SG=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_TUN=m
-CONFIG_DM9000=y
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_ZD1211RW=m
-CONFIG_ZD1211RW_DEBUG=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_SERIO_RAW=y
-CONFIG_LEGACY_PTY_COUNT=128
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_S3C2410=y
-CONFIG_I2C_SIMTEC=y
-CONFIG_SPI=y
-CONFIG_SPI_S3C24XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_SENSORS_LM75=y
-CONFIG_THERMAL=y
-CONFIG_WATCHDOG=y
-CONFIG_S3C2410_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_S3C2410=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_SOC=y
-CONFIG_HIDRAW=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=m
-CONFIG_USB_WDM=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_GADGET=y
-CONFIG_USB_S3C2410=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_MMC=y
-CONFIG_SDIO_UART=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SPI=y
-CONFIG_MMC_S3C=y
-CONFIG_LEDS_S3C24XX=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_S3C=y
-CONFIG_DMADEVICES=y
-CONFIG_S3C24XX_DMAC=y
-CONFIG_EXT2_FS=m
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_CTS=m
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SALSA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_LZO=m
-CONFIG_LIBCRC32C=m
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index a5e8d2235a1a..7984640e994e 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -1,22 +1,18 @@
CONFIG_SYSVIPC=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MMP=y
-CONFIG_MACH_BROWNSTONE=y
-CONFIG_MACH_FLINT=y
-CONFIG_MACH_MARVELL_JASPER=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_MACH_MMP2_DT=y
CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255 earlyprintk"
CONFIG_VFP=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -28,9 +24,9 @@ CONFIG_IP_PNP=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_GENERIC=y
+CONFIG_MTD_RAW_NAND=y
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
@@ -39,9 +35,9 @@ CONFIG_SMC91X=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_PXA=y
@@ -55,17 +51,18 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_MAX8925=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MAX8925=y
-CONFIG_MMC=y
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_RESET_CONTROLLER is not set
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_EXT4_FS=y
+# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
@@ -73,16 +70,16 @@ CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
+CONFIG_CRC_CCITT=y
CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_INFO=y
# CONFIG_DYNAMIC_DEBUG is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_MMP_UART3=y
CONFIG_EARLY_PRINTK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig
index eacc089d86c5..ea31f116d577 100644
--- a/arch/arm/configs/moxart_defconfig
+++ b/arch/arm/configs/moxart_defconfig
@@ -1,7 +1,7 @@
# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_ELF_CORE is not set
@@ -11,18 +11,17 @@ CONFIG_IKCONFIG_PROC=y
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MULTI_V4=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MOXART=y
CONFIG_MACH_UC7112LX=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_ATAGS is not set
CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_SWAP is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -118,10 +117,15 @@ CONFIG_EXT3_FS=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
+CONFIG_KEYS=y
+CONFIG_CRC32_BIT=y
+CONFIG_DMA_API_DEBUG=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_KGDB=y
CONFIG_DEBUG_PAGEALLOC=y
+# CONFIG_SLUB_DEBUG is not set
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_STACK_USAGE=y
@@ -131,12 +135,8 @@ CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_PROVE_LOCKING=y
-CONFIG_DMA_API_DEBUG=y
-CONFIG_KGDB=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_UART_8250=y
CONFIG_DEBUG_UART_PHYS=0x98200000
CONFIG_DEBUG_UART_VIRT=0xf9820000
CONFIG_EARLY_PRINTK=y
-CONFIG_KEYS=y
-CONFIG_CRC32_BIT=y
diff --git a/arch/arm/configs/mps2_defconfig b/arch/arm/configs/mps2_defconfig
index 89f4a6ff30bd..3ed73f184d83 100644
--- a/arch/arm/configs/mps2_defconfig
+++ b/arch/arm/configs/mps2_defconfig
@@ -1,5 +1,6 @@
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EXPERT=y
@@ -10,22 +11,17 @@ CONFIG_EXPERT=y
# CONFIG_SIGNALFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_BLOCK is not set
# CONFIG_MMU is not set
CONFIG_ARCH_MPS2=y
CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x21000000
CONFIG_DRAM_SIZE=0x1000000
-CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_ATAGS is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_SUSPEND is not set
+# CONFIG_BLOCK is not set
CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
# CONFIG_COREDUMP is not set
-# CONFIG_SUSPEND is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -68,9 +64,9 @@ CONFIG_SMSC911X=y
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_MPS2_UART_CONSOLE=y
CONFIG_SERIAL_MPS2_UART=y
+CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
@@ -98,9 +94,10 @@ CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_NLS=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_DEBUG_FS=y
+# CONFIG_SLUB_DEBUG is not set
# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_MEMTEST=y
diff --git a/arch/arm/configs/multi_v4t_defconfig b/arch/arm/configs/multi_v4t_defconfig
index e530107be412..b60000a89aff 100644
--- a/arch/arm/configs/multi_v4t_defconfig
+++ b/arch/arm/configs/multi_v4t_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
-CONFIG_SLOB=y
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_AT91=y
@@ -11,23 +10,23 @@ CONFIG_SOC_AT91RM9200=y
CONFIG_ARCH_CLPS711X=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX1=y
+CONFIG_ARCH_NSPIRE=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_INTEGRATOR_IMPD1=y
CONFIG_INTEGRATOR_CM720T=y
CONFIG_INTEGRATOR_CM920T=y
CONFIG_INTEGRATOR_CM922T_XA10=y
-CONFIG_ARCH_NSPIRE=y
CONFIG_AEABI=y
# CONFIG_ATAGS is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_CLPS711X_CPUIDLE=y
CONFIG_JUMP_LABEL=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_COREDUMP is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_TINY=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -73,8 +72,6 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_WATCHDOG=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_AT91RM9200_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_FB=y
CONFIG_FB_CLPS711X=y
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 70241ad2b550..52bb1a5e25fc 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=19
@@ -12,17 +12,8 @@ CONFIG_MACH_ASPEED_G4=y
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91SAM9=y
CONFIG_ARCH_DAVINCI=y
-CONFIG_ARCH_DAVINCI_DM644x=y
-CONFIG_ARCH_DAVINCI_DM355=y
-CONFIG_ARCH_DAVINCI_DM646x=y
CONFIG_ARCH_DAVINCI_DA830=y
CONFIG_ARCH_DAVINCI_DA850=y
-CONFIG_ARCH_DAVINCI_DM365=y
-CONFIG_MACH_SFFSDR=y
-CONFIG_MACH_NEUROS_OSD2=y
-CONFIG_MACH_DM355_LEOPARD=y
-CONFIG_MACH_MITYOMAPL138=y
-CONFIG_MACH_OMAPL138_HAWKBOARD=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX25=y
CONFIG_SOC_IMX27=y
@@ -31,8 +22,6 @@ CONFIG_MACH_KIRKWOOD=y
CONFIG_ARCH_NPCM=y
CONFIG_ARCH_WPCM450=y
CONFIG_ARCH_ORION5X=y
-CONFIG_MACH_DB88F5281=y
-CONFIG_MACH_RD88F5182=y
CONFIG_MACH_RD88F5182_DT=y
CONFIG_MACH_KUROBOX_PRO=y
CONFIG_MACH_DNS323=y
@@ -40,19 +29,14 @@ CONFIG_MACH_TS209=y
CONFIG_MACH_TERASTATION_PRO2=y
CONFIG_MACH_LINKSTATION_PRO=y
CONFIG_MACH_LINKSTATION_MINI=y
-CONFIG_MACH_LINKSTATION_LS_HGL=y
CONFIG_MACH_TS409=y
-CONFIG_MACH_WRT350N_V2=y
CONFIG_MACH_TS78XX=y
CONFIG_MACH_MV2120=y
CONFIG_MACH_D2NET_DT=y
CONFIG_MACH_NET2BIG=y
CONFIG_MACH_MSS2_DT=y
-CONFIG_MACH_WNR854T=y
-CONFIG_MACH_RD88F5181L_GE=y
-CONFIG_MACH_RD88F5181L_FXO=y
-CONFIG_MACH_RD88F6183AP_GE=y
CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_VERSATILE=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_ARM_APPENDED_DTB=y
@@ -65,6 +49,7 @@ CONFIG_ARM_KIRKWOOD_CPUIDLE=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
+CONFIG_IOSCHED_BFQ=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -78,7 +63,6 @@ CONFIG_NET_PKTGEN=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_PCI_MVEBU=y
-CONFIG_ARCH_VERSATILE=y
CONFIG_PCI_VERSATILE=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
@@ -98,17 +82,14 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_ORION=y
CONFIG_MTD_SPI_NOR=y
-CONFIG_SPI_ASPEED_SMC=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
CONFIG_ATMEL_SSC=m
CONFIG_EEPROM_AT24=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_BLK=y
CONFIG_CHR_DEV_SG=m
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
@@ -158,9 +139,11 @@ CONFIG_HW_RANDOM_TIMERIOMEM=m
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_ASPEED=m
CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=m
CONFIG_I2C_IMX=y
CONFIG_I2C_MV64XXX=y
CONFIG_SPI=y
+CONFIG_SPI_ASPEED_SMC=y
CONFIG_SPI_ATMEL=y
CONFIG_SPI_IMX=y
CONFIG_SPI_ORION=y
@@ -168,7 +151,6 @@ CONFIG_SPI_SUN6I=y
CONFIG_GPIO_ASPEED=m
CONFIG_GPIO_ASPEED_SGPIO=y
CONFIG_GPIO_MXC=y
-CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_QNAP=y
CONFIG_SENSORS_ADT7475=y
@@ -211,7 +193,8 @@ CONFIG_SND_ATMEL_SOC_WM8904=m
CONFIG_SND_AT91_SOC_SAM9X5_WM8731=m
CONFIG_SND_KIRKWOOD_SOC=y
CONFIG_SND_SOC_ALC5623=y
-CONFIG_SND_SOC_WM8731=y
+CONFIG_SND_SOC_WM8731_I2C=y
+CONFIG_SND_SOC_WM8731_SPI=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_HID_DRAGONRISE=y
CONFIG_HID_GYRATION=y
@@ -272,6 +255,8 @@ CONFIG_RTC_DRV_ASPEED=m
CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y
CONFIG_MV_XOR=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_MMIO=y
CONFIG_STAGING=y
CONFIG_ASPEED_LPC_CTRL=m
CONFIG_ASPEED_LPC_SNOOP=m
@@ -306,10 +291,10 @@ CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 6e0c8c19b35c..871fffe92187 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1,11 +1,12 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_ARCH_VIRT=y
+CONFIG_ARCH_AIROHA=y
CONFIG_ARCH_ACTIONS=y
CONFIG_ARCH_ALPINE=y
CONFIG_ARCH_ARTPEC=y
@@ -17,6 +18,7 @@ CONFIG_SOC_SAMA5D2=y
CONFIG_SOC_SAMA5D3=y
CONFIG_SOC_SAMA5D4=y
CONFIG_SOC_SAMA7G5=y
+CONFIG_SOC_LAN966=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_CYGNUS=y
CONFIG_ARCH_BCM_HR2=y
@@ -27,14 +29,16 @@ CONFIG_ARCH_BCM_21664=y
CONFIG_ARCH_BCM_23550=y
CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_BCM_53573=y
-CONFIG_ARCH_BCM_63XX=y
CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_ARCH_BCMBCA_CORTEXA7=y
+CONFIG_ARCH_BCMBCA_CORTEXA9=y
+CONFIG_ARCH_BCMBCA_BRAHMAB15=y
CONFIG_ARCH_BERLIN=y
CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
CONFIG_MACH_BERLIN_BG2Q=y
CONFIG_ARCH_DIGICOLOR=y
-CONFIG_ARCH_AIROHA=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HISI=y
@@ -42,6 +46,8 @@ CONFIG_ARCH_HI3xxx=y
CONFIG_ARCH_HIP01=y
CONFIG_ARCH_HIP04=y
CONFIG_ARCH_HIX5HD2=y
+CONFIG_ARCH_HPE=y
+CONFIG_ARCH_HPE_GXP=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
@@ -90,6 +96,7 @@ CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
CONFIG_ARCH_STI=y
CONFIG_ARCH_STM32=y
+CONFIG_ARCH_SUNPLUS=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_UNIPHIER=y
@@ -125,27 +132,11 @@ CONFIG_ARM_EXYNOS_CPUIDLE=y
CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_ARM_QCOM_SPM_CPUIDLE=y
CONFIG_KERNEL_MODE_NEON=y
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_TRUSTED_FOUNDATIONS=y
-CONFIG_BCM47XX_NVRAM=y
-CONFIG_BCM47XX_SPROM=y
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA1_ARM_CE=m
-CONFIG_CRYPTO_SHA2_ARM_CE=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_AES_ARM_CE=m
-CONFIG_CRYPTO_GHASH_ARM_CE=m
-CONFIG_CRYPTO_CRC32_ARM_CE=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_CMDLINE_PARTITION=y
+CONFIG_IOSCHED_BFQ=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -166,12 +157,6 @@ CONFIG_NET_DSA=m
CONFIG_QRTR=m
CONFIG_QRTR_SMD=m
CONFIG_CAN=y
-CONFIG_CAN_AT91=m
-CONFIG_CAN_FLEXCAN=m
-CONFIG_CAN_SUN4I=y
-CONFIG_CAN_XILINXCAN=y
-CONFIG_CAN_RCAR=m
-CONFIG_CAN_MCP251X=y
CONFIG_BT=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_BCM=y
@@ -197,12 +182,19 @@ CONFIG_PCI_TEGRA=y
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PCIE_RCAR_HOST=y
CONFIG_PCI_DRA7XX_EP=y
+CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_TEST=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_OMAP_OCP2SCP=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_TRUSTED_FOUNDATIONS=y
+CONFIG_BCM47XX_NVRAM=y
+CONFIG_BCM47XX_SPROM=y
+CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -223,7 +215,6 @@ CONFIG_MTD_NAND_DAVINCI=y
CONFIG_MTD_NAND_STM32_FMC2=y
CONFIG_MTD_NAND_PL35X=y
CONFIG_MTD_SPI_NOR=y
-CONFIG_SPI_ASPEED_SMC=m
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -250,18 +241,19 @@ CONFIG_AHCI_ST=y
CONFIG_AHCI_IMX=y
CONFIG_AHCI_SUNXI=y
CONFIG_AHCI_TEGRA=y
+CONFIG_AHCI_QORIQ=y
CONFIG_SATA_HIGHBANK=y
CONFIG_SATA_MV=y
CONFIG_SATA_RCAR=y
CONFIG_NETDEVICES=y
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
CONFIG_VIRTIO_NET=y
CONFIG_B53_SPI_DRIVER=m
CONFIG_B53_MDIO_DRIVER=m
CONFIG_B53_MMAP_DRIVER=m
CONFIG_NET_DSA_BCM_SF2=m
+CONFIG_NET_DSA_RZN1_A5PSW=m
CONFIG_SUN4I_EMAC=y
+CONFIG_SPI_AX88796C=m
CONFIG_BCMGENET=m
CONFIG_BGMAC_BCMA=y
CONFIG_SYSTEMPORT=m
@@ -276,6 +268,7 @@ CONFIG_MV643XX_ETH=y
CONFIG_MVNETA=y
CONFIG_PXA168_ETH=m
CONFIG_KS8851=y
+CONFIG_LAN966X_SWITCH=m
CONFIG_R8169=y
CONFIG_SH_ETH=y
CONFIG_SMSC911X=y
@@ -286,13 +279,20 @@ CONFIG_TI_CPSW=y
CONFIG_TI_CPSW_SWITCHDEV=y
CONFIG_TI_CPTS=y
CONFIG_XILINX_EMACLITE=y
+CONFIG_SFP=m
CONFIG_BROADCOM_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_AT803X_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_DP83867_PHY=y
-CONFIG_USB_BRCMSTB=m
+CONFIG_CAN_AT91=m
+CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_SUN4I=y
+CONFIG_CAN_XILINXCAN=y
+CONFIG_CAN_RCAR=m
+CONFIG_CAN_MCP251X=y
+CONFIG_MDIO_MSCC_MIIM=m
CONFIG_USB_PEGASUS=y
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
@@ -323,6 +323,7 @@ CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_MMS114=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMPE=y
@@ -370,8 +371,6 @@ CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SERIAL_VT8500=y
CONFIG_SERIAL_VT8500_CONSOLE=y
-CONFIG_SERIAL_OMAP=y
-CONFIG_SERIAL_OMAP_CONSOLE=y
CONFIG_SERIAL_BCM63XX=y
CONFIG_SERIAL_BCM63XX_CONSOLE=y
CONFIG_SERIAL_XILINX_PS_UART=y
@@ -428,12 +427,15 @@ CONFIG_I2C_RCAR=y
CONFIG_I2C_CROS_EC_TUNNEL=m
CONFIG_I2C_SLAVE_EEPROM=y
CONFIG_SPI=y
+CONFIG_SPI_ASPEED_SMC=m
CONFIG_SPI_ATMEL=m
+CONFIG_SPI_ATMEL_QUADSPI=m
CONFIG_SPI_BCM2835=y
CONFIG_SPI_BCM2835AUX=y
CONFIG_SPI_CADENCE=y
CONFIG_SPI_DAVINCI=y
CONFIG_SPI_FSL_QUADSPI=m
+CONFIG_SPI_GXP=m
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_DSPI=m
CONFIG_SPI_OMAP24XX=y
@@ -455,10 +457,11 @@ CONFIG_SPI_TEGRA20_SLINK=y
CONFIG_SPI_XILINX=y
CONFIG_SPI_SPIDEV=y
CONFIG_SPMI=y
-CONFIG_PTP_1588_CLOCK=y
CONFIG_PINCTRL_AS3722=y
-CONFIG_PINCTRL_STMFX=y
+CONFIG_PINCTRL_MICROCHIP_SGPIO=y
+CONFIG_PINCTRL_OCELOT=y
CONFIG_PINCTRL_PALMAS=y
+CONFIG_PINCTRL_STMFX=y
CONFIG_PINCTRL_OWL=y
CONFIG_PINCTRL_S500=y
CONFIG_PINCTRL_MSM=y
@@ -472,10 +475,12 @@ CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_QCOM_SSBI_PMIC=y
CONFIG_PINCTRL_RZA2=y
+CONFIG_PINCTRL_RZN1=y
CONFIG_GPIO_ASPEED_SGPIO=y
CONFIG_GPIO_DAVINCI=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_EM=y
+CONFIG_GPIO_MPC8XXX=y
CONFIG_GPIO_MXC=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_SYSCON=y
@@ -486,6 +491,7 @@ CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
CONFIG_GPIO_TWL4030=y
@@ -501,7 +507,6 @@ CONFIG_BATTERY_ACT8945A=y
CONFIG_BATTERY_CPCAP=m
CONFIG_BATTERY_SBS=y
CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_ACER_A500=m
CONFIG_AXP20X_POWER=m
CONFIG_BATTERY_MAX17040=m
CONFIG_BATTERY_MAX17042=m
@@ -513,18 +518,22 @@ CONFIG_CHARGER_MAX8997=m
CONFIG_CHARGER_MAX8998=m
CONFIG_CHARGER_SMB347=m
CONFIG_CHARGER_TPS65090=y
+CONFIG_BATTERY_ACER_A500=m
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ASPEED=m
CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_LAN966X=m
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM95245=y
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_PWM_FAN=m
CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_GXP_FAN_CTRL=m
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_IMX_THERMAL=y
+CONFIG_QORIQ_THERMAL=m
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_ARMADA_THERMAL=y
@@ -556,16 +565,17 @@ CONFIG_MESON_WATCHDOG=y
CONFIG_DIGICOLOR_WATCHDOG=y
CONFIG_RENESAS_WDT=m
CONFIG_RENESAS_RZAWDT=m
+CONFIG_RENESAS_RZN1WDT=m
CONFIG_STPMIC1_WATCHDOG=y
CONFIG_PM8916_WATCHDOG=m
CONFIG_BCM47XX_WDT=y
CONFIG_BCM2835_WDT=y
CONFIG_BCM_KONA_WDT=y
CONFIG_BCM7038_WDT=m
+CONFIG_GXP_WATCHDOG=y
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
-CONFIG_MFD_ACER_A500_EC=m
CONFIG_MFD_ACT8945A=y
CONFIG_MFD_AS3711=y
CONFIG_MFD_AS3722=y
@@ -598,6 +608,7 @@ CONFIG_MFD_TPS6586X=y
CONFIG_MFD_TPS65910=y
CONFIG_MFD_STM32_LPTIMER=m
CONFIG_MFD_STPMIC1=y
+CONFIG_MFD_ACER_A500_EC=m
CONFIG_REGULATOR_ACT8865=y
CONFIG_REGULATOR_ACT8945A=y
CONFIG_REGULATOR_ANATOP=y
@@ -652,27 +663,31 @@ CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_MMP_CAMERA=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_ASPEED=m
-CONFIG_VIDEO_STM32_DCMI=m
+CONFIG_VIDEO_ATMEL_ISI=m
+CONFIG_VIDEO_MMP_CAMERA=m
+CONFIG_VIDEO_MICROCHIP_ISC=m
+CONFIG_VIDEO_MICROCHIP_XISC=m
+CONFIG_VIDEO_MICROCHIP_CSI2DC=m
+CONFIG_VIDEO_TEGRA_VDE=m
CONFIG_VIDEO_RENESAS_CEU=m
+CONFIG_VIDEO_RCAR_VIN=m
+CONFIG_VIDEO_RENESAS_FDP1=m
+CONFIG_VIDEO_RENESAS_JPU=m
+CONFIG_VIDEO_RENESAS_VSP1=m
+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m
CONFIG_VIDEO_S5P_FIMC=m
CONFIG_VIDEO_S5P_MIPI_CSIS=m
CONFIG_VIDEO_EXYNOS_FIMC_LITE=m
CONFIG_VIDEO_EXYNOS4_FIMC_IS=m
-CONFIG_VIDEO_RCAR_VIN=m
-CONFIG_VIDEO_ATMEL_ISI=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
-CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_STI_BDISP=m
-CONFIG_VIDEO_STI_HVA=m
CONFIG_VIDEO_STI_DELTA=m
-CONFIG_VIDEO_RENESAS_FDP1=m
-CONFIG_VIDEO_RENESAS_JPU=m
-CONFIG_VIDEO_RENESAS_VSP1=m
+CONFIG_VIDEO_STI_HVA=m
+CONFIG_VIDEO_STM32_DCMI=m
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIVID=m
CONFIG_VIDEO_ADV7180=m
@@ -683,6 +698,7 @@ CONFIG_IMX_IPUV3_CORE=m
CONFIG_DRM=y
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
+CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_NOUVEAU=m
CONFIG_DRM_EXYNOS=m
CONFIG_DRM_EXYNOS_FIMD=y
@@ -697,7 +713,6 @@ CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_DRM_ATMEL_HLCDC=m
CONFIG_DRM_RCAR_DU=m
-CONFIG_DRM_RCAR_LVDS=y
CONFIG_DRM_SUN4I=m
CONFIG_DRM_MSM=m
CONFIG_DRM_FSL_DCU=m
@@ -708,13 +723,13 @@ CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
-CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
-CONFIG_DRM_LVDS_CODEC=m
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_LVDS_CODEC=m
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
CONFIG_DRM_SII902X=m
@@ -730,6 +745,7 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=m
CONFIG_DRM_IMX_TVE=m
CONFIG_DRM_IMX_LDB=m
CONFIG_DRM_IMX_HDMI=m
+CONFIG_DRM_V3D=m
CONFIG_DRM_VC4=m
CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_MXSFB=m
@@ -761,7 +777,8 @@ CONFIG_SND_ATMEL_SOC_WM8904=m
CONFIG_SND_ATMEL_SOC_PDMIC=m
CONFIG_SND_ATMEL_SOC_I2S=m
CONFIG_SND_BCM2835_SOC_I2S=m
-CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_IMX_SOC=m
+CONFIG_SND_SOC_FSL_ASOC_CARD=m
CONFIG_SND_PXA_SOC_SSP=m
CONFIG_SND_MMP_SOC_SSPA=m
CONFIG_SND_PXA910_SOC=m
@@ -797,6 +814,8 @@ CONFIG_SND_SOC_TEGRA_WM9712=m
CONFIG_SND_SOC_TEGRA_TRIMSLICE=m
CONFIG_SND_SOC_TEGRA_ALC5632=m
CONFIG_SND_SOC_TEGRA_MAX98090=m
+CONFIG_SND_SOC_DAVINCI_MCASP=m
+CONFIG_SND_SOC_AC97_CODEC=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_CPCAP=m
CONFIG_SND_SOC_CS42L51_I2C=m
@@ -804,6 +823,10 @@ CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_STI_SAS=m
+CONFIG_SND_SOC_TLV320AIC32X4=m
+CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
+CONFIG_SND_SOC_WM8960=m
+CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_USB=y
@@ -811,7 +834,9 @@ CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_XHCI_TEGRA=m
+CONFIG_USB_BRCMSTB=m
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_STI=y
CONFIG_USB_EHCI_EXYNOS=m
CONFIG_USB_EHCI_MV=m
@@ -840,6 +865,7 @@ CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_ISP1760=y
CONFIG_USB_HSIC_USB3503=y
+CONFIG_USB_ONBOARD_HUB=m
CONFIG_AB8500_USB=y
CONFIG_KEYSTONE_USB_PHY=m
CONFIG_NOP_USB_XCEIV=y
@@ -849,8 +875,8 @@ CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ISP1301=y
CONFIG_USB_MXS_PHY=y
CONFIG_USB_GADGET=y
-CONFIG_USB_FSL_USB2=y
CONFIG_USB_RENESAS_USBHS_UDC=m
+CONFIG_USB_RENESAS_USBF=m
CONFIG_USB_ASPEED_VHUB=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
@@ -873,6 +899,8 @@ CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_ETH=m
CONFIG_TYPEC=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_UCSI_STM32G0=m
CONFIG_TYPEC_STUSB160X=m
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
@@ -913,12 +941,14 @@ CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
CONFIG_LEDS_CPCAP=m
+CONFIG_LEDS_PCA9532=m
+CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
-CONFIG_LEDS_MAX77693=m
CONFIG_LEDS_MAX8997=m
CONFIG_LEDS_ACER_A500=m
CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_MAX77693=m
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
@@ -929,6 +959,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_EDAC=y
+CONFIG_EDAC_LAYERSCAPE=y
CONFIG_EDAC_HIGHBANK_MC=y
CONFIG_EDAC_HIGHBANK_L2=y
CONFIG_RTC_CLASS=y
@@ -942,6 +973,7 @@ CONFIG_RTC_DRV_MAX8997=m
CONFIG_RTC_DRV_MAX77686=y
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_RS5C372=m
+CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_TWL4030=y
@@ -961,6 +993,7 @@ CONFIG_RTC_DRV_SH=m
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_AT91RM9200=m
CONFIG_RTC_DRV_AT91SAM9=m
+CONFIG_RTC_DRV_RZN1=m
CONFIG_RTC_DRV_VT8500=y
CONFIG_RTC_DRV_SUNXI=y
CONFIG_RTC_DRV_MV=y
@@ -992,6 +1025,7 @@ CONFIG_UNIPHIER_MDMAC=y
CONFIG_XILINX_DMA=y
CONFIG_QCOM_BAM_DMA=y
CONFIG_DW_DMAC=y
+CONFIG_RZN1_DMAMUX=m
CONFIG_RCAR_DMAC=y
CONFIG_RENESAS_USB_DMAC=m
CONFIG_VIRTIO_PCI=y
@@ -1010,6 +1044,7 @@ CONFIG_CROS_EC_SPI=m
CONFIG_COMMON_CLK_MAX77686=y
CONFIG_COMMON_CLK_RK808=m
CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_LAN966X=y
CONFIG_COMMON_CLK_S2MPS11=m
CONFIG_CLK_RASPBERRYPI=y
CONFIG_COMMON_CLK_QCOM=y
@@ -1024,7 +1059,6 @@ CONFIG_MSM_MMCC_8960=y
CONFIG_MSM_MMCC_8974=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_MICROCHIP_PIT64B=y
CONFIG_BCM2835_MBOX=y
CONFIG_QCOM_APCS_IPC=y
CONFIG_QCOM_IPCC=y
@@ -1044,9 +1078,13 @@ CONFIG_ASPEED_LPC_CTRL=m
CONFIG_ASPEED_LPC_SNOOP=m
CONFIG_ASPEED_P2A_CTRL=m
CONFIG_RASPBERRYPI_POWER=y
+CONFIG_QCOM_COMMAND_DB=m
CONFIG_QCOM_CPR=y
CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_OCMEM=m
CONFIG_QCOM_RMTFS_MEM=m
+CONFIG_QCOM_RPMH=y
+CONFIG_QCOM_RPMHPD=y
CONFIG_QCOM_RPMPD=y
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMD_RPM=y
@@ -1137,13 +1175,15 @@ CONFIG_PWM_SUN4I=y
CONFIG_PWM_TEGRA=y
CONFIG_PWM_VT8500=y
CONFIG_KEYSTONE_IRQ=y
+CONFIG_RESET_MCHP_SPARX5=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN9I_USB=y
+CONFIG_PHY_BRCM_USB=m
CONFIG_PHY_HIX5HD2_SATA=y
CONFIG_PHY_BERLIN_SATA=y
CONFIG_PHY_BERLIN_USB=y
-CONFIG_PHY_BRCM_USB=m
CONFIG_PHY_MMP3_USB=m
+CONFIG_PHY_LAN966X_SERDES=m
CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_QCOM_APQ8064_SATA=m
CONFIG_PHY_QCOM_USB_HS=y
@@ -1164,12 +1204,13 @@ CONFIG_TI_PIPE3=y
CONFIG_TWL4030_USB=m
CONFIG_RAS=y
CONFIG_NVMEM_IMX_OCOTP=y
-CONFIG_QCOM_QFPROM=y
-CONFIG_ROCKCHIP_EFUSE=m
+CONFIG_NVMEM_MESON_MX_EFUSE=m
+CONFIG_NVMEM_QCOM_QFPROM=y
+CONFIG_NVMEM_RMEM=m
+CONFIG_NVMEM_ROCKCHIP_EFUSE=m
+CONFIG_NVMEM_STM32_ROMEM=m
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_VF610_OCOTP=y
-CONFIG_MESON_MX_EFUSE=m
-CONFIG_NVMEM_RMEM=m
CONFIG_FSI=m
CONFIG_FSI_MASTER_GPIO=m
CONFIG_FSI_MASTER_HUB=m
@@ -1177,6 +1218,8 @@ CONFIG_FSI_MASTER_ASPEED=m
CONFIG_FSI_SCOM=m
CONFIG_FSI_SBEFIFO=m
CONFIG_FSI_OCC=m
+CONFIG_TEE=y
+CONFIG_OPTEE=y
CONFIG_INTERCONNECT_QCOM=y
CONFIG_INTERCONNECT_QCOM_MSM8916=y
CONFIG_COUNTER=m
@@ -1210,6 +1253,16 @@ CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA1_ARM_CE=m
+CONFIG_CRYPTO_SHA2_ARM_CE=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_AES_ARM_CE=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_CRC32_ARM_CE=m
CONFIG_CRYPTO_DEV_SUN4I_SS=m
CONFIG_CRYPTO_DEV_FSL_CAAM=m
CONFIG_CRYPTO_DEV_EXYNOS_RNG=m
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index cd703c15798f..4ed6e8c8e164 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -1,30 +1,26 @@
CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
-# CONFIG_SLUB_DEBUG is not set
CONFIG_PROFILING=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V6 is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MV78XX0=y
-CONFIG_MACH_DB78X00_BP=y
-CONFIG_MACH_RD78X00_MASA=y
CONFIG_MACH_TERASTATION_WXL=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_VFP=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -52,25 +48,26 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
CONFIG_SATA_MV=y
CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_NET_PCI=y
CONFIG_MV643XX_ETH=y
# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_MARVELL_PHY=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
+CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -110,21 +107,20 @@ CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
+# CONFIG_SLUB_DEBUG is not set
CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
index d57ff30dabff..2467afd32146 100644
--- a/arch/arm/configs/mvebu_v5_defconfig
+++ b/arch/arm/configs/mvebu_v5_defconfig
@@ -1,19 +1,14 @@
CONFIG_SYSVIPC=y
CONFIG_FHANDLE=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_PROFILING=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_KIRKWOOD=y
CONFIG_ARCH_ORION5X=y
-CONFIG_MACH_DB88F5281=y
-CONFIG_MACH_RD88F5182=y
CONFIG_MACH_RD88F5182_DT=y
CONFIG_MACH_KUROBOX_PRO=y
CONFIG_MACH_DNS323=y
@@ -22,24 +17,14 @@ CONFIG_MACH_TERASTATION_PRO2=y
CONFIG_MACH_LINKSTATION_PRO=y
CONFIG_MACH_LINKSTATION_LSCHL=y
CONFIG_MACH_LINKSTATION_MINI=y
-CONFIG_MACH_LINKSTATION_LS_HGL=y
CONFIG_MACH_TS409=y
-CONFIG_MACH_WRT350N_V2=y
CONFIG_MACH_TS78XX=y
CONFIG_MACH_MV2120=y
CONFIG_MACH_D2NET_DT=y
CONFIG_MACH_NET2BIG=y
CONFIG_MACH_MSS2_DT=y
-CONFIG_MACH_WNR854T=y
-CONFIG_MACH_RD88F5181L_GE=y
-CONFIG_MACH_RD88F5181L_FXO=y
-CONFIG_MACH_RD88F6183AP_GE=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
@@ -47,6 +32,9 @@ CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_KIRKWOOD_CPUIDLE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -61,6 +49,7 @@ CONFIG_NET_SWITCHDEV=y
CONFIG_NET_PKTGEN=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
+CONFIG_PCI_MVEBU=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
@@ -84,6 +73,7 @@ CONFIG_EEPROM_AT24=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_MV=y
@@ -93,9 +83,9 @@ CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_MV643XX_ETH=y
CONFIG_R8169=y
CONFIG_MARVELL_PHY=y
-CONFIG_MWL8K=m
CONFIG_LIBERTAS=y
CONFIG_LIBERTAS_SDIO=y
+CONFIG_MWL8K=m
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@@ -194,16 +184,16 @@ CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_FS=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_DEV_MARVELL_CESA=y
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index 7b713c083a2a..68a18264f31b 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -4,7 +4,6 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_375=y
@@ -24,6 +23,7 @@ CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
+CONFIG_SLAB=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
@@ -147,7 +147,7 @@ CONFIG_NLS_UTF8=y
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_PRINTK_TIME=y
# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ca32446b187f..feb38a94c1a7 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_TASKSTATS=y
@@ -15,7 +15,6 @@ CONFIG_CGROUPS=y
# CONFIG_NET_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_PERF_EVENTS=y
-# CONFIG_COMPAT_BRK is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MXS=y
CONFIG_AEABI=y
@@ -25,6 +24,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_COMPAT_BRK is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -38,7 +38,6 @@ CONFIG_SYN_COOKIES=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_CAN=m
-CONFIG_CAN_FLEXCAN=m
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
@@ -62,6 +61,7 @@ CONFIG_ICPLUS_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_SMSC_PHY=y
+CONFIG_CAN_FLEXCAN=m
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC95XX=y
# CONFIG_WLAN is not set
@@ -93,6 +93,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
CONFIG_DRM_MXSFB=y
+CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -162,10 +163,10 @@ CONFIG_CRC_ITU_T=m
CONFIG_CRC7=m
CONFIG_FONTS=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_FRAME_WARN=2048
CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_PROVE_LOCKING=y
CONFIG_BLK_DEV_IO_TRACE=y
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index 018a1092d0e7..c333406ce5e3 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -1,31 +1,32 @@
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_ASSABET=y
CONFIG_ASSABET_NEPONSET=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_PCMCIA_SA1111=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x80000
CONFIG_ZBOOT_ROM_BSS=0xc1000000
CONFIG_ZBOOT_ROM=y
CONFIG_CMDLINE="console=ttySA0,38400n8 cpufreq=221200 rw root=/dev/mtdblock2 mtdparts=sa1100:512K(boot),1M(kernel),2560K(initrd),4M(root) load_ramdisk=1 prompt_ramdisk=0 mem=32M noinitrd initrd=0xc0800000,3M"
CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
CONFIG_PM=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_MSDOS_PARTITION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_SA1100=y
+CONFIG_PCMCIA_SA1111=y
CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -39,20 +40,20 @@ CONFIG_BLK_DEV_SD=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_NET_VENDOR_SMC=y
+CONFIG_PCMCIA_PCNET=y
CONFIG_SMC9194=y
CONFIG_SMC91X=y
CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_SA1111=y
-CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_LEGACY_PTY_COUNT=64
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CS=y
CONFIG_SERIAL_SA1100=y
CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=64
+CONFIG_SERIAL_NONSTANDARD=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_WATCHDOG=y
@@ -68,17 +69,19 @@ CONFIG_USB=m
CONFIG_USB_MON=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_STORAGE=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ISO8859_1=m
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
index c3c171cec91b..30ff6fbce5a3 100644
--- a/arch/arm/configs/netwinder_defconfig
+++ b/arch/arm/configs/netwinder_defconfig
@@ -1,15 +1,13 @@
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_FOOTBRIDGE=y
CONFIG_ARCH_NETWINDER=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
CONFIG_DEPRECATED_PARAM_STRUCT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=0x801"
CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
+CONFIG_PARTITION_ADVANCED=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -51,9 +49,6 @@ CONFIG_977_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_CYBER2000=y
CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SOUND_PRIME=y
@@ -62,6 +57,10 @@ CONFIG_SOUND_TRACEINIT=y
CONFIG_SOUND_DMAP=y
CONFIG_SOUND_YM3812=y
CONFIG_SOUND_WAVEARTIST=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_EXT2_FS=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
@@ -72,7 +71,6 @@ CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_SMB_FS=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
@@ -80,6 +78,9 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 907d6512821a..4171dafddc0a 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -1,5 +1,4 @@
# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
@@ -10,14 +9,14 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
-CONFIG_SLAB=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_NOMADIK=y
CONFIG_MACH_NOMADIK_8815NHK=y
CONFIG_AEABI=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -59,6 +58,7 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
@@ -131,11 +131,11 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=y
+CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_DES=y
# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 3148567b66b6..53dd0717cea5 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -1,61 +1,48 @@
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
# CONFIG_ELF_CORE is not set
# CONFIG_BASE_FULL is not set
# CONFIG_SHMEM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLOB=y
+# CONFIG_KALLSYMS is not set
CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MULTI_V4T=y
+CONFIG_ARCH_MULTI_V5=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_DM_TIMER=y
-CONFIG_ARCH_OMAP730=y
-CONFIG_ARCH_OMAP850=y
CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_INNOVATOR=y
-CONFIG_MACH_OMAP_H2=y
-CONFIG_MACH_OMAP_H3=y
-CONFIG_MACH_HERALD=y
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_MACH_OMAP_OSK=y
-CONFIG_MACH_OMAP_PERSEUS2=y
-CONFIG_MACH_OMAP_FSAMPLE=y
-CONFIG_MACH_VOICEBLUE=y
CONFIG_MACH_OMAP_PALMTE=y
-CONFIG_MACH_OMAP_PALMZ71=y
-CONFIG_MACH_OMAP_PALMTT=y
CONFIG_MACH_SX1=y
CONFIG_MACH_NOKIA770=y
CONFIG_MACH_AMS_DELTA=y
CONFIG_MACH_OMAP_GENERIC=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_OMAP_CF=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=1f03 rootfstype=jffs2"
CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
# CONFIG_SUSPEND is not set
+CONFIG_PM=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_SWAP is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_TINY=y
+# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -76,6 +63,8 @@ CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
+CONFIG_PCCARD=y
+CONFIG_OMAP_CF=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_CONNECTOR=y
@@ -96,12 +85,21 @@ CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=m
CONFIG_PATA_PCMCIA=m
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_PHYLIB=y
CONFIG_SMC91X=y
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_ASYNC=y
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
CONFIG_USB_CATC=y
CONFIG_USB_KAWETH=y
CONFIG_USB_PEGASUS=y
@@ -109,14 +107,6 @@ CONFIG_USB_RTL8150=y
CONFIG_USB_USBNET=y
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_SLIP=y
-CONFIG_SLIP_COMPRESSED=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=y
@@ -127,11 +117,11 @@ CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-# CONFIG_LEGACY_PTYS is not set
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -153,11 +143,6 @@ CONFIG_FB_OMAP_LCD_MIPID=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_6x11=y
-CONFIG_FONT_MINI_4x6=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
@@ -219,7 +204,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
@@ -232,13 +216,7 @@ CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_UTF8=y
# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_PCBC=y
@@ -246,3 +224,14 @@ CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_LIBCRC32C=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_6x11=y
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index d933b787d934..c4216c552100 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -2,7 +2,7 @@ CONFIG_KERNEL_LZMA=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_AUDIT=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
@@ -22,11 +22,8 @@ CONFIG_CGROUP_PERF=y
CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
-CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_ARCH_MULTI_V6=y
-CONFIG_POWER_AVS_OMAP=y
-CONFIG_POWER_AVS_OMAP_CLASS3=y
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_ARCH_OMAP2=y
CONFIG_ARCH_OMAP3=y
@@ -35,6 +32,8 @@ CONFIG_SOC_OMAP5=y
CONFIG_SOC_AM33XX=y
CONFIG_SOC_AM43XX=y
CONFIG_SOC_DRA7XX=y
+CONFIG_POWER_AVS_OMAP=y
+CONFIG_POWER_AVS_OMAP_CLASS3=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_SMP=y
@@ -54,14 +53,6 @@ CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_PM_DEBUG=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA256_ARM=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_GHASH_ARM_CE=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
@@ -69,9 +60,9 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_BINFMT_MISC=y
+CONFIG_SLAB=y
CONFIG_CMA=y
CONFIG_ZSMALLOC=m
CONFIG_NET=y
@@ -250,8 +241,6 @@ CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_NET_SWITCHDEV=y
CONFIG_CAN=m
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
@@ -316,6 +305,7 @@ CONFIG_PCI_ENDPOINT_TEST=m
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_ATA=y
CONFIG_SATA_AHCI_PLATFORM=y
@@ -350,6 +340,8 @@ CONFIG_AT803X_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_DP83848_PHY=y
CONFIG_DP83867_PHY=y
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
@@ -419,8 +411,6 @@ CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_OMAP=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_OMAP=y
-CONFIG_SERIAL_OMAP_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
@@ -430,7 +420,6 @@ CONFIG_SPI_TI_QSPI=m
CONFIG_HSI=m
CONFIG_OMAP_SSI=m
CONFIG_SSI_PROTOCOL=m
-CONFIG_PTP_1588_CLOCK=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
@@ -494,15 +483,15 @@ CONFIG_REGULATOR_TWL4030=y
CONFIG_RC_CORE=m
CONFIG_LIRC=y
CONFIG_RC_DEVICES=y
-CONFIG_IR_SPI=m
-CONFIG_IR_RX51=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_PWM_TX=m
+CONFIG_IR_RX51=m
+CONFIG_IR_SPI=m
CONFIG_MEDIA_SUPPORT=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_OMAP3=m
-CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_MT9P031=m
+CONFIG_VIDEO_TVP5150=m
CONFIG_DRM=m
CONFIG_DRM_OMAP=m
CONFIG_OMAP5_DSS_HDMI=y
@@ -553,6 +542,8 @@ CONFIG_SND_SOC_OMAP_ABE_TWL6040=m
CONFIG_SND_SOC_OMAP_HDMI=m
CONFIG_SND_SOC_CPCAP=m
CONFIG_SND_SOC_TLV320AIC23_I2C=m
+CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_HID_GENERIC=m
@@ -576,6 +567,7 @@ CONFIG_USB_INVENTRA_DMA=y
CONFIG_USB_TI_CPPI41_DMA=y
CONFIG_USB_TUSB_OMAP_DMA=y
CONFIG_USB_DWC3=m
+CONFIG_USB_ISP1760=m
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
@@ -708,6 +700,13 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA256_ARM=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_DEV_OMAP=m
CONFIG_CRYPTO_DEV_OMAP_SHAM=m
CONFIG_CRYPTO_DEV_OMAP_AES=m
@@ -723,9 +722,8 @@ CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_PRINTK_TIME=y
# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_INFO_SPLIT=y
CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_DEBUG_INFO_SPLIT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_SCHEDSTATS=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index b9e3b647e732..0629b088a584 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -1,23 +1,14 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
-# CONFIG_SLUB_DEBUG is not set
CONFIG_PROFILING=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V6 is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_ORION5X=y
-CONFIG_ARCH_ORION5X_DT=y
-CONFIG_MACH_DB88F5281=y
-CONFIG_MACH_RD88F5182=y
CONFIG_MACH_RD88F5182_DT=y
CONFIG_MACH_KUROBOX_PRO=y
CONFIG_MACH_DNS323=y
@@ -25,28 +16,20 @@ CONFIG_MACH_TS209=y
CONFIG_MACH_TERASTATION_PRO2=y
CONFIG_MACH_LINKSTATION_PRO=y
CONFIG_MACH_LINKSTATION_MINI=y
-CONFIG_MACH_LINKSTATION_LS_HGL=y
CONFIG_MACH_TS409=y
-CONFIG_MACH_WRT350N_V2=y
CONFIG_MACH_TS78XX=y
CONFIG_MACH_MV2120=y
-CONFIG_MACH_EDMINI_V2_DT=y
-CONFIG_MACH_D2NET=y
-CONFIG_MACH_BIGDISK=y
CONFIG_MACH_NET2BIG=y
-CONFIG_MACH_MSS2=y
-CONFIG_MACH_WNR854T=y
-CONFIG_MACH_RD88F5181L_GE=y
-CONFIG_MACH_RD88F5181L_FXO=y
-CONFIG_MACH_RD88F6183AP_GE=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_FPE_NWFPE=y
CONFIG_VFP=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -58,6 +41,7 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_NET_DSA=y
CONFIG_NET_PKTGEN=m
+# CONFIG_VGA_ARB is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -69,13 +53,14 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_ORION=y
+CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
CONFIG_SATA_MV=y
CONFIG_NETDEVICES=y
@@ -103,7 +88,6 @@ CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MV64XXX=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_LM75=y
-# CONFIG_VGA_ARB is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
@@ -148,17 +132,18 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_DEV_MARVELL_CESA=y
+CONFIG_CRC_T10DIF=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
+# CONFIG_SLUB_DEBUG is not set
CONFIG_LATENCYTOP=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRC_T10DIF=y
diff --git a/arch/arm/configs/oxnas_v6_defconfig b/arch/arm/configs/oxnas_v6_defconfig
deleted file mode 100644
index de37f7e90999..000000000000
--- a/arch/arm/configs/oxnas_v6_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CGROUPS=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-CONFIG_PERF_EVENTS=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_OXNAS=y
-CONFIG_MACH_OX820=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_CMA=y
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_SECCOMP=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_KEXEC=y
-CONFIG_EFI=y
-CONFIG_CPU_IDLE=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_VFP=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_CMA=y
-CONFIG_CMA_SIZE_MBYTES=64
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_OXNAS=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_NETDEVICES=y
-CONFIG_STMMAC_ETH=y
-CONFIG_REALTEK_PHY=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_EXT4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_UBIFS_FS=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig
deleted file mode 100644
index b47c8abe85bc..000000000000
--- a/arch/arm/configs/palmz72_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_ARCH_PXA_PALM=y
-# CONFIG_MACH_PALMTX is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=tty root=/dev/mmcblk0"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_PXA27x=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PDA_POWER=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_PXA=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_TMPFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_USER=y
-CONFIG_CRC_T10DIF=y
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
deleted file mode 100644
index e97a158081fc..000000000000
--- a/arch/arm/configs/pcm027_defconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_PCM027=y
-CONFIG_MACH_PCM990_BASEBOARD=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_BLK_DEV is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PXA=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PXA2XX_AC97=y
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_PXA=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PXA=m
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_DEFAULT="iso8859-15"
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
deleted file mode 100644
index 2170148b975c..000000000000
--- a/arch/arm/configs/pleb_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_SHMEM is not set
-CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_PLEB=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySA0,9600 mem=16M@0xc0000000 mem=16M@0xc8000000 root=/dev/ram initrd=0xc0400000,4M"
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig
index 0947f022954d..8422ddc9bab2 100644
--- a/arch/arm/configs/pxa168_defconfig
+++ b/arch/arm/configs/pxa168_defconfig
@@ -1,23 +1,18 @@
CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MMP=y
-CONFIG_MACH_ASPENITE=y
-CONFIG_MACH_ZYLONITE2=y
-CONFIG_MACH_AVENGERS_LITE=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_ARCH_MMP=y
CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M"
CONFIG_FPE_NWFPE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -34,9 +29,9 @@ CONFIG_SMC91X=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
@@ -49,12 +44,12 @@ CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
+CONFIG_CRC_CCITT=y
CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
deleted file mode 100644
index 4a383afa5e87..000000000000
--- a/arch/arm/configs/pxa255-idp_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
-CONFIG_ARCH_PXA_IDP=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=dhcp console=ttyS0,115200 mem=64M"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index f0c34017f2aa..d1e83b52e03a 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -1,21 +1,18 @@
CONFIG_SYSVIPC=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=18
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_KALLSYMS_ALL=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_PXA=y
-CONFIG_MACH_LITTLETON=y
-CONFIG_MACH_TAVOREVB=y
-CONFIG_MACH_SAAR=y
-CONFIG_PREEMPT=y
+CONFIG_MACH_PXA3XX_DT=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=64M debug"
CONFIG_FPE_NWFPE=y
+CONFIG_MODULES=y
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -30,11 +27,11 @@ CONFIG_IP_PNP=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_MARVELL=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
@@ -44,12 +41,10 @@ CONFIG_SMC91X=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_PXA27x=y
-CONFIG_KEYBOARD_PXA930_ROTARY=y
-CONFIG_MOUSE_PXA930_TRKBALL=y
CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_HELPER_AUTO is not set
@@ -60,7 +55,6 @@ CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_MAX7301=y
-CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
CONFIG_PDA_POWER=y
CONFIG_BATTERY_DA9030=y
@@ -78,8 +72,6 @@ CONFIG_BACKLIGHT_DA903X=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
CONFIG_LOGO=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
@@ -105,9 +97,11 @@ CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NLS=y
+CONFIG_FONTS=y
+CONFIG_FONT_6x11=y
CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
# CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index b21196372158..48e41ca582af 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -1,23 +1,19 @@
CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
+CONFIG_ARCH_MMP=y
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M earlyprintk"
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MMP=y
-CONFIG_MACH_TAVOREVB=y
-CONFIG_MACH_TTC_DKB=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M earlyprintk"
CONFIG_FPE_NWFPE=y
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -34,9 +30,12 @@ CONFIG_SMC91X=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
+# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_MMP_DISP=y
CONFIG_MMP_DISP_CONTROLLER=y
@@ -44,9 +43,6 @@ CONFIG_MMP_SPI=y
CONFIG_MMP_PANEL_TPOHVGA=y
CONFIG_MMP_FB=y
CONFIG_LOGO=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_TMPFS=y
@@ -57,14 +53,14 @@ CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
+CONFIG_CRC_CCITT=y
CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_MMP_UART2=y
CONFIG_EARLY_PRINTK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig
index 29b1f192afbb..b46e39369dbb 100644
--- a/arch/arm/configs/pxa_defconfig
+++ b/arch/arm/configs/pxa_defconfig
@@ -1,8 +1,9 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_FHANDLE=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
@@ -11,80 +12,15 @@ CONFIG_LOG_BUF_SHIFT=13
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
-CONFIG_SLOB=y
CONFIG_PROFILING=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_LDM_PARTITION=y
-CONFIG_CMDLINE_PARTITION=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_PXA=y
-CONFIG_ARCH_LUBBOCK=y
-CONFIG_MACH_MAINSTONE=y
-CONFIG_MACH_ZYLONITE300=y
-CONFIG_MACH_ZYLONITE320=y
-CONFIG_MACH_LITTLETON=y
-CONFIG_MACH_TAVOREVB=y
-CONFIG_MACH_SAAR=y
-CONFIG_ARCH_PXA_IDP=y
-CONFIG_ARCH_VIPER=y
-CONFIG_MACH_ARCOM_ZEUS=y
-CONFIG_MACH_BALLOON3=y
-CONFIG_MACH_CSB726=y
-CONFIG_CSB726_CSB701=y
-CONFIG_MACH_EXEDA=y
-CONFIG_MACH_CM_X300=y
-CONFIG_MACH_CAPC7117=y
CONFIG_ARCH_GUMSTIX=y
-CONFIG_MACH_XCEP=y
-CONFIG_TRIZEPS_PXA=y
-CONFIG_MACH_TRIZEPS4WL=y
-CONFIG_MACH_LOGICPD_PXA270=y
-CONFIG_MACH_PCM027=y
-CONFIG_MACH_PCM990_BASEBOARD=y
-CONFIG_MACH_COLIBRI=y
-CONFIG_MACH_COLIBRI_PXA270_INCOME=y
-CONFIG_MACH_COLIBRI300=y
-CONFIG_MACH_COLIBRI320=y
-CONFIG_MACH_COLIBRI_EVALBOARD=y
-CONFIG_MACH_VPAC270=y
-CONFIG_MACH_H4700=y
-CONFIG_MACH_H5000=y
-CONFIG_MACH_HIMALAYA=y
-CONFIG_MACH_MAGICIAN=y
-CONFIG_MACH_MIOA701=y
-CONFIG_PXA_EZX=y
-CONFIG_MACH_MP900C=y
-CONFIG_ARCH_PXA_PALM=y
CONFIG_PXA_SHARPSL=y
-CONFIG_MACH_POODLE=y
-CONFIG_MACH_CORGI=y
-CONFIG_MACH_SHEPHERD=y
-CONFIG_MACH_HUSKY=y
CONFIG_MACH_AKITA=y
CONFIG_MACH_BORZOI=y
-CONFIG_MACH_TOSA=y
-CONFIG_TOSA_BT=m
-CONFIG_TOSA_USE_EXT_KEYCODES=y
-CONFIG_MACH_ICONTROL=y
-CONFIG_ARCH_PXA_ESERIES=y
-CONFIG_MACH_ZIPIT2=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCCARD=m
-CONFIG_YENTA=m
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
-# CONFIG_COMPACTION is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARCH_FORCE_MAX_ORDER=8
CONFIG_CMDLINE="root=/dev/ram0 ro"
CONFIG_KEXEC=y
CONFIG_CPU_FREQ=y
@@ -97,7 +33,20 @@ CONFIG_CPUFREQ_DT=m
CONFIG_ARM_PXA2xx_CPUFREQ=m
CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_LDM_PARTITION=y
+CONFIG_CMDLINE_PARTITION=y
CONFIG_BINFMT_MISC=y
+CONFIG_SLUB=y
+CONFIG_SLUB_TINY=y
+# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -115,16 +64,6 @@ CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_IEEE802154=y
CONFIG_DNS_RESOLVER=y
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_IRDA_DEBUG=y
-CONFIG_IRTTY_SIR=m
-CONFIG_PXA_FICP=m
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
@@ -151,51 +90,60 @@ CONFIG_MAC80211=m
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_MSI=y
+CONFIG_PCCARD=m
+CONFIG_YENTA=m
+CONFIG_PCMCIA_PXA2XX=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_AR7_PARTS=m
+CONFIG_MTD_CMDLINE_PARTS=m
+CONFIG_MTD_OF_PARTS=m
+CONFIG_MTD_AFS_PARTS=m
CONFIG_MTD_REDBOOT_PARTS=m
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=0
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_AFS_PARTS=m
-CONFIG_MTD_OF_PARTS=m
-CONFIG_MTD_AR7_PARTS=m
CONFIG_MTD_BLOCK=m
CONFIG_NFTL=m
CONFIG_NFTL_RW=y
+CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_LE_BYTE_SWAP=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_OTP=y
+CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_CFI_STAA=m
CONFIG_MTD_RAM=m
CONFIG_MTD_ROM=m
CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=m
CONFIG_MTD_M25P80=m
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_DOCG3=m
+CONFIG_MTD_ONENAND=m
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_ONENAND_GENERIC=m
CONFIG_MTD_RAW_NAND=m
-CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_SHARPSL=m
+CONFIG_MTD_NAND_TMIO=m
+CONFIG_MTD_NAND_BRCMNAND=m
CONFIG_MTD_NAND_GPIO=m
+CONFIG_MTD_NAND_PLATFORM=m
CONFIG_MTD_NAND_DISKONCHIP=m
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_NAND_SHARPSL=m
-CONFIG_MTD_NAND_MARVELL=m
CONFIG_MTD_NAND_CM_X270=m
-CONFIG_MTD_NAND_TMIO=m
-CONFIG_MTD_NAND_BRCMNAND=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
+CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_BLOCK=y
@@ -209,8 +157,6 @@ CONFIG_AD525X_DPOT_I2C=m
CONFIG_ICS932S401=m
CONFIG_APDS9802ALS=m
CONFIG_ISL29003=m
-CONFIG_IIO=m
-CONFIG_AD5446=m
CONFIG_EEPROM_AT24=m
CONFIG_SENSORS_LIS3_SPI=m
CONFIG_SCSI=y
@@ -241,13 +187,13 @@ CONFIG_SMC91X=m
CONFIG_SMSC911X=m
CONFIG_STMMAC_ETH=m
CONFIG_PHYLIB=y
-CONFIG_AT803X_PHY=m
-CONFIG_MARVELL_PHY=m
CONFIG_SMSC_PHY=m
CONFIG_BROADCOM_PHY=y
CONFIG_ICPLUS_PHY=m
CONFIG_MICREL_PHY=m
CONFIG_FIXED_PHY=m
+CONFIG_MARVELL_PHY=m
+CONFIG_AT803X_PHY=m
CONFIG_MDIO_BITBANG=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
@@ -271,16 +217,16 @@ CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
CONFIG_HOSTAP_CS=m
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_SDIO=m
CONFIG_HERMES=m
CONFIG_PCMCIA_HERMES=m
CONFIG_PCMCIA_SPECTRUM=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
CONFIG_RT2X00=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
CONFIG_INPUT_FF_MEMLESS=m
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_MOUSEDEV=m
@@ -293,14 +239,12 @@ CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_GPIO=m
CONFIG_KEYBOARD_PXA27x=m
-CONFIG_KEYBOARD_PXA930_ROTARY=m
CONFIG_KEYBOARD_CROS_EC=m
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_PXA930_TRKBALL=m
CONFIG_MOUSE_NAVPOINT_PXA27x=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
@@ -311,12 +255,9 @@ CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_HTCPEN=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_PCAP=m
CONFIG_TOUCHSCREEN_ST1232=m
@@ -327,7 +268,6 @@ CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
CONFIG_INPUT_PCAP=m
CONFIG_INPUT_ADXL34X=m
CONFIG_SERIO=m
-CONFIG_SERIO_SA1111=m
CONFIG_LEGACY_PTY_COUNT=8
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_8250_CS=m
@@ -340,6 +280,7 @@ CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_DESIGNWARE_PLATFORM=m
+CONFIG_I2C_GPIO=y
CONFIG_I2C_PXA_SLAVE=y
CONFIG_I2C_XILINX=m
CONFIG_I2C_CROS_EC_TUNNEL=m
@@ -353,16 +294,17 @@ CONFIG_SPI_XILINX=m
CONFIG_SPI_SPIDEV=m
CONFIG_PPS=y
CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=m
CONFIG_GPIO_GENERIC_PLATFORM=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
CONFIG_GPIO_PCF857X=m
+CONFIG_HTC_EGPIO=y
CONFIG_GPIO_PALMAS=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY_DEBUG=y
CONFIG_PDA_POWER=m
CONFIG_BATTERY_SBS=m
@@ -386,13 +328,8 @@ CONFIG_MFD_AS3711=y
CONFIG_MFD_BCM590XX=m
CONFIG_MFD_AXP20X=y
CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_SPI=m
CONFIG_MFD_ASIC3=y
CONFIG_PMIC_DA903X=y
-CONFIG_HTC_EGPIO=y
CONFIG_HTC_PASIC3=m
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77693=y
@@ -440,11 +377,13 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_PXA27x=m
CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_PXA27x=m
CONFIG_DRM=m
+CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_PXA=y
CONFIG_FB_PXA_OVERLAY=y
CONFIG_FB_PXA_PARAMETERS=y
CONFIG_PXA3XX_GCU=m
@@ -453,39 +392,26 @@ CONFIG_FB_VIRTUAL=m
CONFIG_FB_SIMPLE=y
CONFIG_LCD_CORGI=m
CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_TOSA=m
CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_TOSA=m
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_DEBUG=y
+CONFIG_SND_SEQUENCER=m
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=m
CONFIG_SND_ATMEL_SOC=m
CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_PXA2XX_SOC_CORGI=m
+CONFIG_SND_PXA_SOC_SSP=m
CONFIG_SND_PXA2XX_SOC_SPITZ=m
-CONFIG_SND_PXA2XX_SOC_Z2=m
-CONFIG_SND_PXA2XX_SOC_POODLE=m
-CONFIG_SND_PXA2XX_SOC_TOSA=m
-CONFIG_SND_PXA2XX_SOC_E740=m
-CONFIG_SND_PXA2XX_SOC_E750=m
-CONFIG_SND_PXA2XX_SOC_E800=m
-CONFIG_SND_PXA2XX_SOC_EM_X270=m
-CONFIG_SND_PXA2XX_SOC_PALM27X=y
-CONFIG_SND_SOC_ZYLONITE=m
-CONFIG_SND_PXA2XX_SOC_HX4700=m
-CONFIG_SND_PXA2XX_SOC_MAGICIAN=m
-CONFIG_SND_PXA2XX_SOC_MIOA701=m
CONFIG_SND_SOC_AK4642=m
+CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SOUND_PRIME=m
@@ -574,6 +500,7 @@ CONFIG_USB_LCD=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_GPIO_VBUS=y
+CONFIG_USB_GPIO_VBUS=m
CONFIG_USB_ISP1301=m
CONFIG_USB_GADGET=m
CONFIG_USB_GADGET_VBUS_DRAW=500
@@ -620,9 +547,9 @@ CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_MAX8907=m
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_PALMAS=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_PCF8583=m
+CONFIG_RTC_DRV_PALMAS=m
CONFIG_RTC_DRV_TPS6586X=m
CONFIG_RTC_DRV_TPS65910=m
CONFIG_RTC_DRV_S35390A=m
@@ -637,10 +564,16 @@ CONFIG_PXA_DMA=y
CONFIG_DW_DMAC=m
CONFIG_UIO=y
CONFIG_CROS_EC_CHARDEV=m
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=m
+CONFIG_CROS_EC_I2C=m
+CONFIG_CROS_EC_SPI=m
CONFIG_COMMON_CLK_S2MPS11=m
CONFIG_PM_DEVFREQ=y
CONFIG_EXTCON=y
CONFIG_MEMORY=y
+CONFIG_IIO=m
+CONFIG_AD5446=m
CONFIG_PWM=y
CONFIG_PWM_PXA=m
CONFIG_PHY_SAMSUNG_USB2=m
@@ -706,31 +639,12 @@ CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_UTF8=m
-CONFIG_PRINTK_TIME=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
-CONFIG_FRAME_WARN=0
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_SHIRQ=y
CONFIG_TIMER_STATS=y
-CONFIG_FUNCTION_TRACER=y
-CONFIG_FTRACE_SYSCALLS=y
-CONFIG_DEBUG_USER=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
@@ -740,9 +654,17 @@ CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
-CONFIG_ARM_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM=m
CONFIG_CRYPTO_SHA256_ARM=m
CONFIG_CRYPTO_SHA512_ARM=m
@@ -754,3 +676,12 @@ CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_FONT_6x11=y
CONFIG_FONT_MINI_4x6=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_FRAME_WARN=0
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_FTRACE_SYSCALLS=y
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 9981566f2096..ab686b9c2ad8 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -1,39 +1,38 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_MSM8X60=y
CONFIG_ARCH_MSM8960=y
CONFIG_ARCH_MSM8974=y
CONFIG_ARCH_MDM9615=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCIE_QCOM=y
CONFIG_SMP=y
-CONFIG_PREEMPT=y
+CONFIG_ARM_PSCI=y
CONFIG_HIGHMEM=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPUFREQ_DT=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_COMPAT_BRK is not set
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -56,15 +55,18 @@ CONFIG_BT_HCIUART_BCM=y
CONFIG_CFG80211=m
CONFIG_MAC80211=m
CONFIG_RFKILL=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_QCOM=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
+CONFIG_MTD_QCOMSMEM_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_QCOMSMEM_PARTS=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -129,14 +131,19 @@ CONFIG_PINCTRL_APQ8064=y
CONFIG_PINCTRL_APQ8084=y
CONFIG_PINCTRL_IPQ4019=y
CONFIG_PINCTRL_IPQ8064=y
+CONFIG_PINCTRL_MSM8226=y
CONFIG_PINCTRL_MSM8660=y
CONFIG_PINCTRL_MSM8960=y
+CONFIG_PINCTRL_MDM9607=y
CONFIG_PINCTRL_MDM9615=y
CONFIG_PINCTRL_MSM8X74=y
-CONFIG_PINCTRL_SDX55=y
+CONFIG_PINCTRL_MSM8909=y
+CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_QCOM_SSBI_PMIC=y
CONFIG_GPIOLIB=y
+CONFIG_PINCTRL_SDX55=y
+CONFIG_PINCTRL_SDX65=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
@@ -144,15 +151,17 @@ CONFIG_CHARGER_QCOM_SMBB=y
CONFIG_CHARGER_BQ24190=m
CONFIG_THERMAL=y
CONFIG_QCOM_TSENS=y
+CONFIG_WATCHDOG=y
+CONFIG_QCOM_WDT=y
CONFIG_MFD_PM8XXX=y
CONFIG_MFD_QCOM_RPM=y
CONFIG_MFD_SPMI_PMIC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_QCOM_RPM=y
+CONFIG_REGULATOR_QCOM_RPMH=y
CONFIG_REGULATOR_QCOM_SMD_RPM=y
CONFIG_REGULATOR_QCOM_SPMI=y
-CONFIG_REGULATOR_QCOM_RPMH=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_DRM=y
CONFIG_DRM_MSM=m
@@ -160,11 +169,11 @@ CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
CONFIG_DRM_ANALOGIX_ANX78XX=m
CONFIG_FB=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_LM3630A=y
CONFIG_BACKLIGHT_LP855X=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_DYNAMIC_MINORS=y
@@ -180,6 +189,7 @@ CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MSM=y
CONFIG_USB_ACM=y
+CONFIG_USB_DWC3=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
@@ -196,7 +206,6 @@ CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_ETH=m
-CONFIG_USB_DWC3=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_ARMMMCI=y
@@ -218,8 +227,8 @@ CONFIG_COMMON_CLK_QCOM=y
CONFIG_QCOM_A7PLL=y
CONFIG_QCOM_CLK_APCS_SDX55=y
CONFIG_QCOM_CLK_RPM=y
-CONFIG_QCOM_CLK_RPMH=y
CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_QCOM_CLK_RPMH=y
CONFIG_APQ_MMCC_8084=y
CONFIG_IPQ_GCC_4019=y
CONFIG_IPQ_LCC_806X=y
@@ -229,30 +238,35 @@ CONFIG_MDM_LCC_9615=y
CONFIG_MSM_MMCC_8960=y
CONFIG_MSM_MMCC_8974=y
CONFIG_SDX_GCC_55=y
-CONFIG_MSM_IOMMU=y
-CONFIG_ARM_SMMU=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_MAILBOX=y
CONFIG_QCOM_APCS_IPC=y
+CONFIG_MSM_IOMMU=y
+CONFIG_ARM_SMMU=y
CONFIG_REMOTEPROC=y
CONFIG_QCOM_ADSP_PIL=y
CONFIG_QCOM_Q6V5_PAS=y
CONFIG_QCOM_Q6V5_PIL=y
CONFIG_QCOM_WCNSS_PIL=y
CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_QCOM_GLINK_SMEM=y
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_QCOM_COMMAND_DB=y
CONFIG_QCOM_GSBI=y
CONFIG_QCOM_OCMEM=y
CONFIG_QCOM_PM=y
+CONFIG_QCOM_RMTFS_MEM=y
+CONFIG_QCOM_RPMH=y
+CONFIG_QCOM_RPMHPD=y
+CONFIG_QCOM_RPMPD=y
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMD_RPM=y
CONFIG_QCOM_SMP2P=y
CONFIG_QCOM_SMSM=y
-CONFIG_QCOM_RPMH=y
-CONFIG_QCOM_RPMHPD=y
+CONFIG_QCOM_SOCINFO=y
+CONFIG_QCOM_STATS=y
CONFIG_QCOM_WCNSS_CTRL=y
CONFIG_EXTCON_QCOM_SPMI_MISC=y
CONFIG_IIO=y
@@ -270,11 +284,11 @@ CONFIG_BMP280=y
CONFIG_PWM=y
CONFIG_PHY_QCOM_APQ8064_SATA=y
CONFIG_PHY_QCOM_IPQ806X_SATA=y
-CONFIG_PHY_QCOM_USB_HS=y
-CONFIG_PHY_QCOM_USB_HSIC=y
CONFIG_PHY_QCOM_QMP=y
+CONFIG_PHY_QCOM_USB_HS=y
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
-CONFIG_QCOM_QFPROM=y
+CONFIG_PHY_QCOM_USB_HSIC=y
+CONFIG_NVMEM_QCOM_QFPROM=y
CONFIG_INTERCONNECT=y
CONFIG_INTERCONNECT_QCOM=y
CONFIG_INTERCONNECT_QCOM_MSM8974=m
@@ -295,15 +309,19 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_DEV_QCOM_RNG=m
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SLUB_DEBUG is not set
# CONFIG_SCHED_DEBUG is not set
-CONFIG_WATCHDOG=y
-CONFIG_QCOM_WDT=y
-CONFIG_ARM_PSCI=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPUFREQ_DT=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 3ef3521c19db..92f803c2805c 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -1,10 +1,8 @@
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_FULL=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_REALVIEW=y
CONFIG_MACH_REALVIEW_EB=y
@@ -21,7 +19,8 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=tt
CONFIG_VFP=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -43,6 +42,7 @@ CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_NETDEVICES=y
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
@@ -95,9 +95,9 @@ CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_KERNEL=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index c090643b1ecb..210974364d61 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -2,16 +2,16 @@
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_RPC=y
CONFIG_CPU_SA110=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -33,6 +33,7 @@ CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_ARXESCSI=m
@@ -55,12 +56,12 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_MOUSE_PS2 is not set
CONFIG_MOUSE_RISCPC=y
# CONFIG_SERIO_SERPORT is not set
+CONFIG_LEGACY_PTY_COUNT=64
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=16
CONFIG_SERIAL_8250_RUNTIME_UARTS=8
CONFIG_SERIAL_8250_ACORN=y
-CONFIG_LEGACY_PTY_COUNT=64
CONFIG_PRINTER=m
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
@@ -69,9 +70,6 @@ CONFIG_I2C_CHARDEV=y
CONFIG_FB=y
CONFIG_FB_ACORN=y
CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_ACORN_8x8=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SOUND_PRIME=m
@@ -89,10 +87,8 @@ CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_ADFS_FS=y
CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION_CUMANA is not set
# CONFIG_ACORN_PARTITION_EESOX is not set
-CONFIG_BSD_DISKLABEL=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
@@ -120,8 +116,11 @@ CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_KOI8_R=m
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_ACORN_8x8=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_UART_8250=y
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
deleted file mode 100644
index 153009130dab..000000000000
--- a/arch/arm/configs/s3c2410_defconfig
+++ /dev/null
@@ -1,433 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=m
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_ARCH_S3C24XX=y
-CONFIG_S3C_ADC=y
-CONFIG_CPU_S3C2412=y
-CONFIG_CPU_S3C2416=y
-CONFIG_CPU_S3C2440=y
-CONFIG_CPU_S3C2442=y
-CONFIG_CPU_S3C2443=y
-CONFIG_MACH_AML_M5900=y
-CONFIG_ARCH_BAST=y
-CONFIG_ARCH_H1940=y
-CONFIG_MACH_N30=y
-CONFIG_MACH_OTOM=y
-CONFIG_MACH_QT2410=y
-CONFIG_ARCH_SMDK2410=y
-CONFIG_MACH_TCT_HAMMER=y
-CONFIG_MACH_VR1000=y
-CONFIG_MACH_JIVE=y
-CONFIG_MACH_SMDK2412=y
-CONFIG_MACH_VSTMS=y
-CONFIG_MACH_SMDK2416=y
-CONFIG_MACH_ANUBIS=y
-CONFIG_MACH_AT2440EVB=y
-CONFIG_MACH_MINI2440=y
-CONFIG_MACH_NEXCODER_2440=y
-CONFIG_MACH_OSIRIS=y
-CONFIG_MACH_OSIRIS_DVS=m
-CONFIG_MACH_RX3715=y
-CONFIG_ARCH_S3C2440=y
-CONFIG_MACH_NEO1973_GTA02=y
-CONFIG_MACH_RX1950=y
-CONFIG_MACH_SMDK2443=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-CONFIG_APM_EMULATION=m
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_NET_KEY=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPIP=m
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_IP_VS=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_CFG80211=m
-CONFIG_MAC80211=m
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_S3C2410=y
-CONFIG_PARPORT=y
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_EEPROM_AT24=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_ATA=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_NETDEVICES=y
-CONFIG_DM9000=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=m
-CONFIG_PRINTER=y
-CONFIG_PPDEV=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_S3C2410=y
-CONFIG_I2C_SIMTEC=y
-CONFIG_SPI=y
-CONFIG_SPI_GPIO=m
-CONFIG_SPI_S3C24XX=m
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_TLE62X0=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM85=m
-CONFIG_WATCHDOG=y
-CONFIG_S3C2410_WATCHDOG=y
-CONFIG_MFD_SM501=y
-CONFIG_TPS65010=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_S3C2410=y
-CONFIG_FB_SM501=y
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_SEQUENCER=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_SOC=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_MMC=y
-CONFIG_SDIO_UART=m
-CONFIG_MMC_TEST=m
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SPI=m
-CONFIG_MMC_S3C=y
-CONFIG_LEDS_S3C24XX=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_PCA955X=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_S3C=y
-CONFIG_DMADEVICES=y
-CONFIG_S3C24XX_DMAC=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CONFIGFS_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=y
-CONFIG_SQUASHFS=m
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_CIFS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_INFO=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index 59a258d504aa..93258d5b57ff 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -5,15 +5,6 @@ CONFIG_KALLSYMS_ALL=y
CONFIG_ARCH_MULTI_V6=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_S3C64XX=y
-CONFIG_MACH_SMDK6400=y
-CONFIG_MACH_ANW6410=y
-CONFIG_MACH_MINI6410=y
-CONFIG_MACH_REAL6410=y
-CONFIG_MACH_SMDK6410=y
-CONFIG_MACH_NCP=y
-CONFIG_MACH_HMT=y
-CONFIG_MACH_SMARTQ5=y
-CONFIG_MACH_SMARTQ7=y
CONFIG_MACH_WLF_CRAGG_6410=y
CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x51000000,6M ramdisk_size=6144"
CONFIG_VFP=y
@@ -71,9 +62,9 @@ CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index 70919716f815..4c1e480b5bbd 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_CGROUPS=y
@@ -21,7 +21,6 @@ CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
@@ -48,6 +47,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_NETDEVICES=y
CONFIG_BRCMFMAC=m
CONFIG_INPUT_EVDEV=y
@@ -115,9 +115,9 @@ CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_CRC_CCITT=y
-CONFIG_DEBUG_INFO=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 03dd80c2a19e..c6aff6fb084d 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -1,5 +1,4 @@
# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
@@ -7,7 +6,6 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
CONFIG_ARCH_AT91=y
CONFIG_SOC_SAMA5D2=y
CONFIG_SOC_SAMA5D3=y
@@ -26,8 +24,9 @@ CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -44,9 +43,6 @@ CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_NET_DSA=m
CONFIG_VLAN_8021Q=m
CONFIG_CAN=y
-CONFIG_CAN_AT91=y
-CONFIG_CAN_M_CAN=y
-CONFIG_CAN_M_CAN_PLATFORM=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_MAC80211_LEDS=y
@@ -57,13 +53,13 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_BLOCK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
@@ -72,6 +68,7 @@ CONFIG_ATMEL_SSC=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
@@ -90,6 +87,9 @@ CONFIG_MACB=y
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MICREL_PHY=y
+CONFIG_CAN_AT91=y
+CONFIG_CAN_M_CAN=y
+CONFIG_CAN_M_CAN_PLATFORM=y
CONFIG_USB_LAN78XX=m
CONFIG_LIBERTAS_THINFIRM=m
CONFIG_LIBERTAS_THINFIRM_USB=m
@@ -150,13 +150,13 @@ CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_ATMEL_ISC=y
CONFIG_VIDEO_ATMEL_ISI=y
+CONFIG_VIDEO_MICROCHIP_ISC=y
+CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_MT9V032=m
CONFIG_DRM=y
CONFIG_DRM_ATMEL_HLCDC=y
CONFIG_DRM_PANEL_SIMPLE=y
@@ -222,6 +222,7 @@ CONFIG_PWM_ATMEL_HLCDC_PWM=y
CONFIG_PWM_ATMEL_TCB=y
CONFIG_EXT4_FS=y
CONFIG_FANOTIFY=y
+CONFIG_AUTOFS_FS=m
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
@@ -232,6 +233,7 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_OFB=y
@@ -239,7 +241,6 @@ CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_DEV_ATMEL_AES=y
diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig
index 07b0494ef743..954112041403 100644
--- a/arch/arm/configs/sama7_defconfig
+++ b/arch/arm/configs/sama7_defconfig
@@ -1,5 +1,4 @@
# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
@@ -14,15 +13,13 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_IO_URING is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLAB=y
CONFIG_ARCH_AT91=y
CONFIG_SOC_SAMA7G5=y
CONFIG_ATMEL_CLOCKSOURCE_TCB=y
# CONFIG_CACHE_L2X0 is not set
# CONFIG_ARM_PATCH_IDIV is not set
# CONFIG_CPU_SW_DOMAIN_PAN is not set
-CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_ARCH_FORCE_MAX_ORDER=14
CONFIG_UACCESS_WITH_MEMCPY=y
# CONFIG_ATAGS is not set
CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel"
@@ -43,8 +40,11 @@ CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_EFI_PARTITION is not set
# CONFIG_COREDUMP is not set
+# CONFIG_SWAP is not set
+CONFIG_SLAB=y
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
+# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -59,8 +59,6 @@ CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_NET_DSA=m
CONFIG_VLAN_8021Q=m
CONFIG_CAN=y
-CONFIG_CAN_M_CAN=y
-CONFIG_CAN_M_CAN_PLATFORM=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
@@ -94,6 +92,8 @@ CONFIG_MTD_NAND_ATMEL=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_BLOCK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
@@ -105,6 +105,8 @@ CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_MACB=y
CONFIG_MICREL_PHY=y
+CONFIG_CAN_M_CAN=y
+CONFIG_CAN_M_CAN_PLATFORM=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@@ -126,6 +128,10 @@ CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_AT91_RESET=y
CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_GENERIC_ADC_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_SAMA5D4_WATCHDOG=y
CONFIG_MFD_ATMEL_FLEXCOM=y
@@ -138,6 +144,8 @@ CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MICROCHIP_XISC=y
+CONFIG_VIDEO_MICROCHIP_CSI2DC=y
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_OV5647=m
@@ -149,6 +157,8 @@ CONFIG_SND_SOC_MIKROE_PROTO=m
CONFIG_SND_MCHP_SOC_I2S_MCC=y
CONFIG_SND_MCHP_SOC_SPDIFTX=y
CONFIG_SND_MCHP_SOC_SPDIFRX=y
+CONFIG_SND_MCHP_SOC_PDMC=y
+CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_PCM5102A=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SIMPLE_CARD=y
@@ -182,7 +192,6 @@ CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_DMADEVICES=y
CONFIG_AT_XDMAC=y
CONFIG_STAGING=y
-CONFIG_MICROCHIP_PIT64B=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y
CONFIG_IIO_SW_TRIGGER=y
@@ -190,9 +199,12 @@ CONFIG_AT91_SAMA5D2_ADC=y
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_MCHP_EIC=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_NVMEM_MICROCHIP_OTPC=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_FANOTIFY=y
+CONFIG_AUTOFS_FS=m
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
@@ -204,13 +216,13 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_LSM="N"
CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_DEV_ATMEL_AES=y
@@ -221,9 +233,9 @@ CONFIG_CRC_ITU_T=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_CMA_ALIGNMENT=9
+# CONFIG_DEBUG_MISC is not set
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_DEBUG_FS=y
-# CONFIG_DEBUG_MISC is not set
# CONFIG_SCHED_DEBUG is not set
CONFIG_STACKTRACE=y
# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig
deleted file mode 100644
index de33abdeb6fa..000000000000
--- a/arch/arm/configs/shannon_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_SHANNON=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySA0,9600 console=tty1 root=/dev/mtdblock2 init=/linuxrc"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=y
-CONFIG_PCMCIA_SMC91C92=y
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_WATCHDOG=y
-CONFIG_SA1100_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_SA1100=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index db8df8a3a7b1..0b21c0a47582 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -1,12 +1,11 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
CONFIG_ARCH_RENESAS=y
CONFIG_PL310_ERRATA_588369=y
CONFIG_SMP=y
@@ -25,6 +24,7 @@ CONFIG_CPUFREQ_DT=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_SLAB=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -32,8 +32,8 @@ CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_DSA=y
CONFIG_CAN=y
-CONFIG_CAN_RCAR=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_RCAR_GEN2=y
@@ -52,11 +52,14 @@ CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_RCAR=y
CONFIG_NETDEVICES=y
+CONFIG_NET_DSA_RZN1_A5PSW=y
CONFIG_SH_ETH=y
CONFIG_RAVB=y
CONFIG_SMSC911X=y
+CONFIG_STMMAC_ETH=y
CONFIG_MICREL_PHY=y
CONFIG_SMSC_PHY=y
+CONFIG_CAN_RCAR=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@@ -73,6 +76,7 @@ CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_EM=y
# CONFIG_SERIAL_8250_PERICOM is not set
@@ -91,6 +95,7 @@ CONFIG_SPI_SH_MSIOF=y
CONFIG_SPI_SH_HSPI=y
CONFIG_PINCTRL_RZA1=y
CONFIG_PINCTRL_RZA2=y
+CONFIG_PINCTRL_RZN1=y
CONFIG_GPIO_EM=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_PCA953X=y
@@ -106,6 +111,7 @@ CONFIG_WATCHDOG=y
CONFIG_DA9063_WATCHDOG=y
CONFIG_RENESAS_WDT=y
CONFIG_RENESAS_RZAWDT=y
+CONFIG_RENESAS_RZN1WDT=y
CONFIG_MFD_AS3711=y
CONFIG_MFD_DA9063=y
CONFIG_MFD_STMPE=y
@@ -119,9 +125,9 @@ CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_RENESAS_CEU=y
CONFIG_VIDEO_RCAR_VIN=y
-CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_RENESAS_FDP1=y
CONFIG_VIDEO_RENESAS_JPU=y
CONFIG_VIDEO_RENESAS_VSP1=y
@@ -131,6 +137,7 @@ CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ML86V7667=y
CONFIG_DRM=y
CONFIG_DRM_RCAR_DU=y
+# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
@@ -162,6 +169,7 @@ CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_USB_RENESAS_USBF=y
CONFIG_USB_ETH=y
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
@@ -177,7 +185,10 @@ CONFIG_RTC_DRV_S35390A=y
CONFIG_RTC_DRV_RX8581=y
CONFIG_RTC_DRV_DA9063=y
CONFIG_RTC_DRV_SH=y
+CONFIG_RTC_DRV_RZN1=y
CONFIG_DMADEVICES=y
+CONFIG_DW_DMAC=y
+CONFIG_RZN1_DMAMUX=y
CONFIG_RCAR_DMAC=y
CONFIG_RENESAS_USB_DMAC=y
CONFIG_STAGING=y
@@ -224,5 +235,5 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig
deleted file mode 100644
index 28d99d8895f9..000000000000
--- a/arch/arm/configs/simpad_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_LOCALVERSION="oe1"
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
-CONFIG_SA1100_SIMPAD=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_SA1100=y
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mtdparts=sa1100:512k(boot),1m(kernel),-(root) console=ttySA0 root=1f02 noinitrd mem=64M jffs2_orphaned_inodes=delete rootfstype=jffs2"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_SA1100_FIR=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_SA1100=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPPOE=m
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=600
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIO=m
-CONFIG_SERIAL_SA1100=y
-CONFIG_SERIAL_SA1100_CONSOLE=y
-CONFIG_FB=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 2d9404ea52c6..70739e09d0f4 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -14,13 +14,10 @@ CONFIG_ARM_THUMBEE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_HIGHMEM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -36,9 +33,6 @@ CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_VLAN_8021Q=y
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_CAN=y
-CONFIG_CAN_C_CAN=y
-CONFIG_CAN_C_CAN_PLATFORM=y
-CONFIG_CAN_DEBUG_DEVICES=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCIE_ALTERA=y
@@ -52,7 +46,6 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_OF_OVERLAY=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -64,6 +57,7 @@ CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_ALTERA_TSE=m
@@ -73,6 +67,9 @@ CONFIG_IXGBE=m
CONFIG_STMMAC_ETH=y
CONFIG_MARVELL_PHY=y
CONFIG_MICREL_PHY=y
+CONFIG_CAN_C_CAN=y
+CONFIG_CAN_C_CAN_PLATFORM=y
+CONFIG_CAN_DEBUG_DEVICES=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_STMPE=y
@@ -88,6 +85,7 @@ CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
+CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_SPIDEV=y
@@ -154,7 +152,7 @@ CONFIG_NFSD_V4=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
diff --git a/arch/arm/configs/sp7021_defconfig b/arch/arm/configs/sp7021_defconfig
new file mode 100644
index 000000000000..c6448ac860b6
--- /dev/null
+++ b/arch/arm/configs/sp7021_defconfig
@@ -0,0 +1,59 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PERF_EVENTS=y
+CONFIG_ARCH_SUNPLUS=y
+# CONFIG_VDSO is not set
+CONFIG_SMP=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_SLAB=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_EXT4_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FANOTIFY=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_EXFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 065553326b39..bfde0c86cdc5 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -1,18 +1,11 @@
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
# CONFIG_SWP_EMULATE is not set
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCIE_SPEAR13XX=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
@@ -20,6 +13,10 @@ CONFIG_AEABI=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_VFP=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_UNIX=y
@@ -28,6 +25,9 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_NET_IPIP=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -97,8 +97,8 @@ CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index afca722d6605..a96ed5cf778e 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -1,16 +1,16 @@
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PARTITION_ADVANCED=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR3XX=y
CONFIG_MACH_SPEAR300=y
CONFIG_MACH_SPEAR310=y
CONFIG_MACH_SPEAR320=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_MTD=y
@@ -77,8 +77,8 @@ CONFIG_JFFS2_FS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index bc32c02cb86b..3e2c2abae5ba 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -1,17 +1,16 @@
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BLK_DEV_INITRD=y
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR6XX=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR6XX=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_MTD=y
-CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y
@@ -28,23 +27,21 @@ CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_STMMAC_ETH=y
# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_RAW_DRIVER=y
CONFIG_I2C=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
-CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_DRM=y
+CONFIG_DRM_PL111=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
@@ -66,8 +63,8 @@ CONFIG_JFFS2_FS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index f42c7a502b6e..10108b4a978e 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -1,26 +1,22 @@
CONFIG_SYSVIPC=y
+CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_PXA=y
CONFIG_PXA_SHARPSL=y
CONFIG_MACH_AKITA=y
CONFIG_MACH_BORZOI=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_PXA2XX=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2 debug"
CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
CONFIG_BINFMT_MISC=m
CONFIG_PM=y
CONFIG_NET=y
@@ -54,11 +50,6 @@ CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_PXA_FICP=m
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
@@ -77,6 +68,8 @@ CONFIG_BT_HCIBT3C=m
CONFIG_BT_HCIBLUECARD=m
CONFIG_BT_HCIBTUART=m
CONFIG_BT_HCIVHCI=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_PXA2XX=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -90,10 +83,15 @@ CONFIG_CHR_DEV_ST=m
CONFIG_CHR_DEV_OSST=m
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_ATA=y
CONFIG_PATA_PCMCIA=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
+CONFIG_PCMCIA_PCNET=m
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_ASYNC=m
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
@@ -101,10 +99,6 @@ CONFIG_USB_RTL8150=m
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_CDC_SUBSET is not set
CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_BSDCOMP=m
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
@@ -115,11 +109,11 @@ CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=m
# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_8250_CS=m
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
CONFIG_SPI=y
CONFIG_SPI_PXA2XX=y
CONFIG_FB=y
@@ -130,11 +124,6 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
CONFIG_HID_A4TECH=m
CONFIG_HID_APPLE=m
CONFIG_HID_BELKIN=m
@@ -151,6 +140,8 @@ CONFIG_HID_PETALYNX=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=m
CONFIG_HID_SUNPLUS=m
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
CONFIG_USB=m
CONFIG_USB_MON=m
CONFIG_USB_OHCI_HCD=m
@@ -219,25 +210,16 @@ CONFIG_NFS_V3=y
CONFIG_NFS_V4=y
CONFIG_SMB_FS=m
CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_PARTITION_ADVANCED=y
+CONFIG_NFS_V4=m
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_LL=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
@@ -249,5 +231,16 @@ CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_WP512=m
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=m
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 551db328009d..dc1a32f50b7e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -1,5 +1,6 @@
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -11,8 +12,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_MMU is not set
CONFIG_ARCH_STM32=y
@@ -21,15 +20,12 @@ CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x90000000
CONFIG_FLASH_MEM_BASE=0x08000000
CONFIG_FLASH_SIZE=0x00200000
-CONFIG_PREEMPT=y
# CONFIG_ATAGS is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_XIP_KERNEL=y
CONFIG_XIP_PHYS_ADDR=0x08008000
CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
# CONFIG_COREDUMP is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER is not set
@@ -39,9 +35,9 @@ CONFIG_KEYBOARD_GPIO=y
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
+CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -75,12 +71,13 @@ CONFIG_EXT3_FS=y
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_NLS=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SLUB_DEBUG is not set
# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_CRYPTO=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 8ba7935bd039..bddc82f78942 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -1,4 +1,4 @@
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
@@ -26,7 +26,6 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_CAN=y
-CONFIG_CAN_SUN4I=y
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
@@ -52,6 +51,7 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MICREL_PHY=y
CONFIG_REALTEK_PHY=y
+CONFIG_CAN_SUN4I=y
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_SUN4I_LRADC=y
@@ -97,9 +97,9 @@ CONFIG_IR_SUNXI=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_SUN4I_CSI=y
CONFIG_VIDEO_SUN6I_CSI=y
-CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_SUN8I_DEINTERLACE=y
CONFIG_VIDEO_SUN8I_ROTATE=y
CONFIG_DRM=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
deleted file mode 100644
index 3a9503fe84cb..000000000000
--- a/arch/arm/configs/tct_hammer_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_SHMEM is not set
-CONFIG_SLOB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S3C24XX=y
-CONFIG_MACH_TCT_HAMMER=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=10240
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT_CONSOLE is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_S3C2410=y
-CONFIG_USB_ETH=m
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-# CONFIG_PROC_SYSCTL is not set
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 289d022acc4b..f32047e24b63 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -1,5 +1,5 @@
CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
@@ -16,7 +16,6 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_ELF_CORE is not set
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
CONFIG_ARCH_TEGRA=y
CONFIG_SMP=y
CONFIG_HIGHMEM=y
@@ -29,12 +28,11 @@ CONFIG_CPU_IDLE=y
CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
-CONFIG_TRUSTED_FOUNDATIONS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
+CONFIG_SLAB=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -56,7 +54,6 @@ CONFIG_IPV6_MIP6=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_CAN=y
-CONFIG_CAN_MCP251X=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_BNEP=y
@@ -80,6 +77,7 @@ CONFIG_PCI_TEGRA=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_TEGRA_GMI=y
+CONFIG_TRUSTED_FOUNDATIONS=y
CONFIG_MTD=y
CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_LOOP=y
@@ -91,6 +89,7 @@ CONFIG_ISL29003=y
CONFIG_EEPROM_AT24=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
@@ -99,6 +98,7 @@ CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_IGB=y
CONFIG_R8169=y
+CONFIG_CAN_MCP251X=y
CONFIG_USB_PEGASUS=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC75XX=y
@@ -114,9 +114,9 @@ CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_TEGRA=y
CONFIG_KEYBOARD_CROS_EC=y
CONFIG_KEYBOARD_CAP11XX=y
+CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_ELAN=y
@@ -139,6 +139,7 @@ CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_TEGRA=y
+CONFIG_I2C_CROS_EC_TUNNEL=m
CONFIG_SPI=y
CONFIG_SPI_TEGRA114=y
CONFIG_SPI_TEGRA20_SFLASH=y
@@ -158,9 +159,9 @@ CONFIG_POWER_RESET_AS3722=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_BATTERY_SBS=y
-CONFIG_CHARGER_BQ24735=y
CONFIG_BATTERY_BQ27XXX=y
CONFIG_CHARGER_GPIO=y
+CONFIG_CHARGER_BQ24735=y
CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65090=y
CONFIG_BATTERY_ACER_A500=y
@@ -198,8 +199,10 @@ CONFIG_REGULATOR_TPS6586X=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_GSPCA=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_TEGRA_VDE=y
CONFIG_DRM=y
CONFIG_DRM_NOUVEAU=m
CONFIG_DRM_TEGRA=y
@@ -286,12 +289,10 @@ CONFIG_SERIO_NVEC_PS2=y
CONFIG_NVEC_POWER=y
CONFIG_NVEC_PAZ00=y
CONFIG_STAGING_MEDIA=y
-CONFIG_TEGRA_VDE=y
CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=m
CONFIG_CROS_EC_SPI=m
-CONFIG_I2C_CROS_EC_TUNNEL=m
CONFIG_TEGRA_IOMMU_GART=y
CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARCH_TEGRA_2x_SOC=y
@@ -342,7 +343,7 @@ CONFIG_CRYPTO_TWOFISH=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_SLAB=y
CONFIG_DEBUG_VM=y
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
deleted file mode 100644
index d66f0c287d41..000000000000
--- a/arch/arm/configs/trizeps4_defconfig
+++ /dev/null
@@ -1,213 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PXA=y
-CONFIG_TRIZEPS_PXA=y
-CONFIG_MACH_TRIZEPS4=y
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_LOAD_CIS is not set
-CONFIG_PCMCIA_PXA2XX=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_CMDLINE="root=fe01 console=ttyS0,38400n8 loglevel=5"
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_VLAN_8021Q=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_CFG80211=y
-CONFIG_CONNECTOR=y
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_LE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_DOC2000=y
-CONFIG_MTD_DOC2001=y
-CONFIG_MTD_DOC2001PLUS=y
-CONFIG_MTD_DOCPROBE_ADVANCED=y
-CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
-CONFIG_MTD_DOCPROBE_HIGH=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_DISKONCHIP=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_ONENAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=8
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_ATA=m
-CONFIG_PATA_PCMCIA=m
-CONFIG_PATA_PLATFORM=m
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-CONFIG_HOSTAP=y
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_CS=y
-CONFIG_HERMES=y
-CONFIG_PCMCIA_HERMES=y
-CONFIG_PCMCIA_SPECTRUM=y
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_ATKBD=m
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_MOUSE_SERIAL=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PXA=y
-CONFIG_I2C_PXA_SLAVE=y
-CONFIG_WATCHDOG=y
-CONFIG_SA1100_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_PXA=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_PXA2XX_AC97=y
-CONFIG_SND_USB_AUDIO=m
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_MMC=y
-CONFIG_MMC_PXA=y
-CONFIG_NEW_LEDS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V4=y
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_LDM_PARTITION=y
-CONFIG_NLS_DEFAULT="iso8859-15"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_USER=y
-CONFIG_KEYS=y
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 3b30913d7d8d..0f55815eecb3 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -1,4 +1,3 @@
-# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
@@ -20,8 +19,8 @@ CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
+# CONFIG_SWAP is not set
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -39,8 +38,14 @@ CONFIG_CFG80211_DEBUGFS=y
CONFIG_MAC80211=y
CONFIG_MAC80211_LEDS=y
CONFIG_CAIF=y
+CONFIG_NFC=m
+CONFIG_NFC_HCI=m
+CONFIG_NFC_SHDLC=m
+CONFIG_NFC_PN544_I2C=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_GNSS=y
+CONFIG_GNSS_SIRF_SERIAL=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_NETDEVICES=y
@@ -83,6 +88,8 @@ CONFIG_SPI_GPIO=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TC3589X=y
+CONFIG_BATTERY_SAMSUNG_SDI=y
+CONFIG_AB8500_BM=y
CONFIG_SENSORS_IIO_HWMON=y
CONFIG_SENSORS_NTC_THERMISTOR=y
CONFIG_THERMAL=y
@@ -98,10 +105,13 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_V4L2_FLASH_LED_CLASS=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_NOVATEK_NT35510=y
+CONFIG_DRM_PANEL_NOVATEK_NT35560=y
+CONFIG_DRM_PANEL_SAMSUNG_DB7430=y
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
+CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y
-CONFIG_DRM_PANEL_SONY_ACX424AKP=y
+CONFIG_DRM_PANEL_WIDECHIPS_WS2401=y
CONFIG_DRM_LIMA=y
CONFIG_DRM_MCDE=y
CONFIG_FB=y
@@ -129,6 +139,7 @@ CONFIG_LEDS_LM3530=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=y
+CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_RT8515=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
@@ -144,17 +155,22 @@ CONFIG_IIO_SW_TRIGGER=y
CONFIG_BMA180=y
CONFIG_BMC150_ACCEL=y
CONFIG_IIO_ST_ACCEL_3AXIS=y
+# CONFIG_IIO_ST_ACCEL_SPI_3AXIS is not set
CONFIG_IIO_RESCALE=y
CONFIG_MPU3050_I2C=y
CONFIG_IIO_ST_GYRO_3AXIS=y
+# CONFIG_IIO_ST_GYRO_SPI_3AXIS is not set
CONFIG_INV_MPU6050_I2C=y
CONFIG_BH1780=y
CONFIG_GP2AP002=y
+CONFIG_TSL2772=y
CONFIG_AK8974=y
CONFIG_IIO_ST_MAGN_3AXIS=y
+# CONFIG_IIO_ST_MAGN_SPI_3AXIS is not set
CONFIG_YAMAHA_YAS530=y
CONFIG_IIO_HRTIMER_TRIGGER=y
CONFIG_IIO_ST_PRESS=y
+# CONFIG_IIO_ST_PRESS_SPI is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
@@ -168,15 +184,12 @@ CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-CONFIG_CRYPTO_DEV_UX500=y
-CONFIG_CRYPTO_DEV_UX500_CRYP=y
-CONFIG_CRYPTO_DEV_UX500_HASH=y
-CONFIG_CRYPTO_DEV_UX500_DEBUG=y
+CONFIG_CRYPTO_DEV_STM32_HASH=y
+CONFIG_CRYPTO_DEV_STM32_CRYP=y
CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index c2d79a67f81f..67e3f9138306 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -4,7 +4,6 @@ CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_VERSATILE=y
CONFIG_AEABI=y
@@ -15,6 +14,7 @@ CONFIG_VFP=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
+CONFIG_SLAB=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -88,8 +88,8 @@ CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_ISO8859_1=m
+CONFIG_DEBUG_KERNEL=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index 947987730eb7..96ad442089bd 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -1,5 +1,7 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_FULL=y
+CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -20,15 +22,12 @@ CONFIG_MCPM=y
CONFIG_VMSPLIT_2G=y
CONFIG_NR_CPUS=8
CONFIG_ARM_PSCI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAMA0"
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_CMA=y
CONFIG_NET=y
@@ -45,6 +44,7 @@ CONFIG_NET_9P_VIRTIO=y
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
@@ -56,6 +56,7 @@ CONFIG_MTD_UBI=y
CONFIG_VIRTIO_BLK=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
CONFIG_SCSI_VIRTIO=y
CONFIG_ATA=y
CONFIG_NETDEVICES=y
@@ -135,9 +136,8 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_CRYPTO_HW is not set
CONFIG_DMA_CMA=y
-CONFIG_DEBUG_INFO=y
-CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_MAGIC_SYSRQ=y
CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/vf610m4_defconfig b/arch/arm/configs/vf610m4_defconfig
index a89f035c3b01..2e47cc57a928 100644
--- a/arch/arm/configs/vf610m4_defconfig
+++ b/arch/arm/configs/vf610m4_defconfig
@@ -16,10 +16,9 @@ CONFIG_FLASH_SIZE=0x01000000
CONFIG_CMDLINE="console=/dev/ttyLP2"
CONFIG_XIP_KERNEL=y
CONFIG_XIP_PHYS_ADDR=0x0f000080
+# CONFIG_SUSPEND is not set
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-# CONFIG_SUSPEND is not set
# CONFIG_UEVENT_HELPER is not set
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
deleted file mode 100644
index c28539bfd128..000000000000
--- a/arch/arm/configs/viper_defconfig
+++ /dev/null
@@ -1,160 +0,0 @@
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=13
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_SHMEM is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_ARCH_VIPER=y
-CONFIG_IWMMXT=y
-CONFIG_PCCARD=m
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_FPE_FASTFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_IPV6 is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=0
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=m
-CONFIG_ATA=m
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_PCMCIA=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_NET_PCMCIA=y
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_INPUT_MOUSEDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_HTCPEN=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_VT_CONSOLE is not set
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_8250_NR_UARTS=5
-CONFIG_SERIAL_8250_RUNTIME_UARTS=5
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_PXA=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_PXA=m
-CONFIG_FB_PXA_PARAMETERS=y
-CONFIG_BACKLIGHT_PWM=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PXA2XX_AC97=m
-CONFIG_USB=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=m
-CONFIG_RTC_DRV_SA1100=m
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRC_T10DIF=m
diff --git a/arch/arm/configs/vt8500_v6_v7_defconfig b/arch/arm/configs/vt8500_v6_v7_defconfig
index 9b85326ba287..41607a84abc8 100644
--- a/arch/arm/configs/vt8500_v6_v7_defconfig
+++ b/arch/arm/configs/vt8500_v6_v7_defconfig
@@ -1,4 +1,4 @@
-CONFIG_NO_HZ=y
+CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_ARCH_MULTI_V6=y
@@ -50,8 +50,8 @@ CONFIG_I2C_WMT=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_WM8750=y
CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
CONFIG_MFD_SYSCON=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
diff --git a/arch/arm/configs/wpcm450_defconfig b/arch/arm/configs/wpcm450_defconfig
new file mode 100644
index 000000000000..45483deab034
--- /dev/null
+++ b/arch/arm/configs/wpcm450_defconfig
@@ -0,0 +1,211 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PROFILING=y
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_NPCM=y
+CONFIG_ARCH_WPCM450=y
+CONFIG_CPU_DCACHE_WRITETHROUGH=y
+CONFIG_AEABI=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+# CONFIG_ATAGS is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_DSA=y
+CONFIG_NET_DSA_TAG_EDSA=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_PKTGEN=m
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SRAM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_QT1070=m
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_LEGACY_TIOCSTI is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_NPCM7XX_KCS_IPMI_BMC=y
+CONFIG_IPMI_KCS_BMC_CDEV_IPMI=y
+CONFIG_IPMI_KCS_BMC_SERIO=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_NPCM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_NPCM=y
+CONFIG_SPI=y
+CONFIG_SPI_WPCM_FIU=y
+CONFIG_SPI_NPCM_PSPI=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_WPCM450=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_NPCM7XX=y
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_NPCM7XX_WATCHDOG=y
+CONFIG_MFD_SYSCON=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_HID is not set
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_DMADEVICES=y
+CONFIG_SYNC_FILE=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VHOST_MENU is not set
+CONFIG_STAGING=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_GENERIC_PHY=y
+CONFIG_PECI=y
+CONFIG_PECI_CPU=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_UTF8=y
+CONFIG_KEYS=y
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_FORTIFY_SOURCE=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_PKCS7_MESSAGE_PARSER=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=m
+CONFIG_LIBCRC32C=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_IO_STRICT_DEVMEM=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0xb8000000
+CONFIG_DEBUG_UART_VIRT=0x0ff000000
+CONFIG_DEBUG_UART_8250_WORD=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig
deleted file mode 100644
index 4d8e7f2eaef7..000000000000
--- a/arch/arm/configs/xcep_defconfig
+++ /dev/null
@@ -1,89 +0,0 @@
-CONFIG_LOCALVERSION=".xcep-itech"
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SHMEM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLOB=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLOCK is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_XCEP=y
-CONFIG_IWMMXT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=mtd4 rootfstype=jffs2 ro console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_PXA=m
-CONFIG_HWMON=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_MAX6650=m
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_SA1100=m
-CONFIG_DMADEVICES=y
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS=m
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_UTF8=m
-CONFIG_PRINTK_TIME=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
-# CONFIG_ARM_UNWIND is not set
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_LIBCRC32C=m
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
deleted file mode 100644
index 25bb6995f105..000000000000
--- a/arch/arm/configs/zeus_defconfig
+++ /dev/null
@@ -1,173 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_TINY_RCU=y
-CONFIG_LOG_BUF_SHIFT=13
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_ARCOM_ZEUS=y
-CONFIG_PCCARD=m
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_IPV6 is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_CFG80211=m
-CONFIG_LIB80211=m
-CONFIG_MAC80211=m
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_EEPROM_AT24=m
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=m
-CONFIG_ATA=m
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_PCMCIA=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-CONFIG_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_RT2X00=m
-CONFIG_RT73USB=m
-CONFIG_NET_PCMCIA=y
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_HTCPEN=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=7
-CONFIG_SERIAL_8250_RUNTIME_UARTS=7
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_PXA2XX=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_SENSORS_LM75=m
-CONFIG_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_PXA=m
-CONFIG_FB_PXA_PARAMETERS=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_PXA2XX_AC97=m
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_PCMCIA is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_USB=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_PXA27X=y
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=y
-CONFIG_MMC_PXA=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_PXA=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_T10DIF=m
diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig
index e4dba5461cb3..847b7a003356 100644
--- a/arch/arm/crypto/Kconfig
+++ b/arch/arm/crypto/Kconfig
@@ -1,92 +1,158 @@
# SPDX-License-Identifier: GPL-2.0
-menuconfig ARM_CRYPTO
- bool "ARM Accelerated Cryptographic Algorithms"
- depends on ARM
+menu "Accelerated Cryptographic Algorithms for CPU (arm)"
+
+config CRYPTO_CURVE25519_NEON
+ tristate "Public key crypto: Curve25519 (NEON)"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_LIB_CURVE25519_GENERIC
+ select CRYPTO_ARCH_HAVE_LIB_CURVE25519
+ help
+ Curve25519 algorithm
+
+ Architecture: arm with
+ - NEON (Advanced SIMD) extensions
+
+config CRYPTO_GHASH_ARM_CE
+ tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_AEAD
+ select CRYPTO_HASH
+ select CRYPTO_CRYPTD
+ select CRYPTO_LIB_AES
+ select CRYPTO_LIB_GF128MUL
+ help
+ GCM GHASH function (NIST SP800-38D)
+
+ Architecture: arm using
+ - PMULL (Polynomial Multiply Long) instructions
+ - NEON (Advanced SIMD) extensions
+ - ARMv8 Crypto Extensions
+
+ Use an implementation of GHASH (used by the GCM AEAD chaining mode)
+ that uses the 64x64 to 128 bit polynomial multiplication (vmull.p64)
+ that is part of the ARMv8 Crypto Extensions, or a slower variant that
+ uses the vmull.p8 instruction that is part of the basic NEON ISA.
+
+config CRYPTO_NHPOLY1305_NEON
+ tristate "Hash functions: NHPoly1305 (NEON)"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_NHPOLY1305
help
- Say Y here to choose from a selection of cryptographic algorithms
- implemented using ARM specific CPU features or instructions.
+ NHPoly1305 hash function (Adiantum)
-if ARM_CRYPTO
+ Architecture: arm using:
+ - NEON (Advanced SIMD) extensions
+
+config CRYPTO_POLY1305_ARM
+ tristate "Hash functions: Poly1305 (NEON)"
+ select CRYPTO_HASH
+ select CRYPTO_ARCH_HAVE_LIB_POLY1305
+ help
+ Poly1305 authenticator algorithm (RFC7539)
+
+ Architecture: arm optionally using
+ - NEON (Advanced SIMD) extensions
+
+config CRYPTO_BLAKE2S_ARM
+ bool "Hash functions: BLAKE2s"
+ select CRYPTO_ARCH_HAVE_LIB_BLAKE2S
+ help
+ BLAKE2s cryptographic hash function (RFC 7693)
+
+ Architecture: arm
+
+ This is faster than the generic implementations of BLAKE2s and
+ BLAKE2b, but slower than the NEON implementation of BLAKE2b.
+ There is no NEON implementation of BLAKE2s, since NEON doesn't
+ really help with it.
+
+config CRYPTO_BLAKE2B_NEON
+ tristate "Hash functions: BLAKE2b (NEON)"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_BLAKE2B
+ help
+ BLAKE2b cryptographic hash function (RFC 7693)
+
+ Architecture: arm using
+ - NEON (Advanced SIMD) extensions
+
+ BLAKE2b digest algorithm optimized with ARM NEON instructions.
+ On ARM processors that have NEON support but not the ARMv8
+ Crypto Extensions, typically this BLAKE2b implementation is
+ much faster than the SHA-2 family and slightly faster than
+ SHA-1.
config CRYPTO_SHA1_ARM
- tristate "SHA1 digest algorithm (ARM-asm)"
+ tristate "Hash functions: SHA-1"
select CRYPTO_SHA1
select CRYPTO_HASH
help
- SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
- using optimized ARM assembler.
+ SHA-1 secure hash algorithm (FIPS 180)
+
+ Architecture: arm
config CRYPTO_SHA1_ARM_NEON
- tristate "SHA1 digest algorithm (ARM NEON)"
+ tristate "Hash functions: SHA-1 (NEON)"
depends on KERNEL_MODE_NEON
select CRYPTO_SHA1_ARM
select CRYPTO_SHA1
select CRYPTO_HASH
help
- SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
- using optimized ARM NEON assembly, when NEON instructions are
- available.
+ SHA-1 secure hash algorithm (FIPS 180)
+
+ Architecture: arm using
+ - NEON (Advanced SIMD) extensions
config CRYPTO_SHA1_ARM_CE
- tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)"
+ tristate "Hash functions: SHA-1 (ARMv8 Crypto Extensions)"
depends on KERNEL_MODE_NEON
select CRYPTO_SHA1_ARM
select CRYPTO_HASH
help
- SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
- using special ARMv8 Crypto Extensions.
+ SHA-1 secure hash algorithm (FIPS 180)
+
+ Architecture: arm using ARMv8 Crypto Extensions
config CRYPTO_SHA2_ARM_CE
- tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
+ tristate "Hash functions: SHA-224 and SHA-256 (ARMv8 Crypto Extensions)"
depends on KERNEL_MODE_NEON
select CRYPTO_SHA256_ARM
select CRYPTO_HASH
help
- SHA-256 secure hash standard (DFIPS 180-2) implemented
- using special ARMv8 Crypto Extensions.
+ SHA-224 and SHA-256 secure hash algorithms (FIPS 180)
+
+ Architecture: arm using
+ - ARMv8 Crypto Extensions
config CRYPTO_SHA256_ARM
- tristate "SHA-224/256 digest algorithm (ARM-asm and NEON)"
+ tristate "Hash functions: SHA-224 and SHA-256 (NEON)"
select CRYPTO_HASH
depends on !CPU_V7M
help
- SHA-256 secure hash standard (DFIPS 180-2) implemented
- using optimized ARM assembler and NEON, when available.
+ SHA-224 and SHA-256 secure hash algorithms (FIPS 180)
+
+ Architecture: arm using
+ - NEON (Advanced SIMD) extensions
config CRYPTO_SHA512_ARM
- tristate "SHA-384/512 digest algorithm (ARM-asm and NEON)"
+ tristate "Hash functions: SHA-384 and SHA-512 (NEON)"
select CRYPTO_HASH
depends on !CPU_V7M
help
- SHA-512 secure hash standard (DFIPS 180-2) implemented
- using optimized ARM assembler and NEON, when available.
-
-config CRYPTO_BLAKE2S_ARM
- tristate "BLAKE2s digest algorithm (ARM)"
- select CRYPTO_ARCH_HAVE_LIB_BLAKE2S
- help
- BLAKE2s digest algorithm optimized with ARM scalar instructions. This
- is faster than the generic implementations of BLAKE2s and BLAKE2b, but
- slower than the NEON implementation of BLAKE2b. (There is no NEON
- implementation of BLAKE2s, since NEON doesn't really help with it.)
+ SHA-384 and SHA-512 secure hash algorithms (FIPS 180)
-config CRYPTO_BLAKE2B_NEON
- tristate "BLAKE2b digest algorithm (ARM NEON)"
- depends on KERNEL_MODE_NEON
- select CRYPTO_BLAKE2B
- help
- BLAKE2b digest algorithm optimized with ARM NEON instructions.
- On ARM processors that have NEON support but not the ARMv8
- Crypto Extensions, typically this BLAKE2b implementation is
- much faster than SHA-2 and slightly faster than SHA-1.
+ Architecture: arm using
+ - NEON (Advanced SIMD) extensions
config CRYPTO_AES_ARM
- tristate "Scalar AES cipher for ARM"
+ tristate "Ciphers: AES"
select CRYPTO_ALGAPI
select CRYPTO_AES
help
- Use optimized AES assembler routines for ARM platforms.
+ Block ciphers: AES cipher algorithms (FIPS-197)
+
+ Architecture: arm
On ARM processors without the Crypto Extensions, this is the
fastest AES implementation for single blocks. For multiple
@@ -98,7 +164,7 @@ config CRYPTO_AES_ARM
such attacks very difficult.
config CRYPTO_AES_ARM_BS
- tristate "Bit sliced AES using NEON instructions"
+ tristate "Ciphers: AES, modes: ECB/CBC/CTR/XTS (bit-sliced NEON)"
depends on KERNEL_MODE_NEON
select CRYPTO_SKCIPHER
select CRYPTO_LIB_AES
@@ -106,8 +172,13 @@ config CRYPTO_AES_ARM_BS
select CRYPTO_CBC
select CRYPTO_SIMD
help
- Use a faster and more secure NEON based implementation of AES in CBC,
- CTR and XTS modes
+ Length-preserving ciphers: AES cipher algorithms (FIPS-197)
+ with block cipher modes:
+ - ECB (Electronic Codebook) mode (NIST SP800-38A)
+ - CBC (Cipher Block Chaining) mode (NIST SP800-38A)
+ - CTR (Counter) mode (NIST SP800-38A)
+ - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E
+ and IEEE 1619)
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
@@ -116,58 +187,59 @@ config CRYPTO_AES_ARM_BS
believed to be invulnerable to cache timing attacks.
config CRYPTO_AES_ARM_CE
- tristate "Accelerated AES using ARMv8 Crypto Extensions"
+ tristate "Ciphers: AES, modes: ECB/CBC/CTS/CTR/XTS (ARMv8 Crypto Extensions)"
depends on KERNEL_MODE_NEON
select CRYPTO_SKCIPHER
select CRYPTO_LIB_AES
select CRYPTO_SIMD
help
- Use an implementation of AES in CBC, CTR and XTS modes that uses
- ARMv8 Crypto Extensions
+ Length-preserving ciphers: AES cipher algorithms (FIPS-197)
+ with block cipher modes:
+ - ECB (Electronic Codebook) mode (NIST SP800-38A)
+ - CBC (Cipher Block Chaining) mode (NIST SP800-38A)
+ - CTR (Counter) mode (NIST SP800-38A)
+ - CTS (Cipher Text Stealing) mode (NIST SP800-38A)
+ - XTS (XOR Encrypt XOR with ciphertext stealing) mode (NIST SP800-38E
+ and IEEE 1619)
+
+ Architecture: arm using:
+ - ARMv8 Crypto Extensions
-config CRYPTO_GHASH_ARM_CE
- tristate "PMULL-accelerated GHASH using NEON/ARMv8 Crypto Extensions"
- depends on KERNEL_MODE_NEON
- select CRYPTO_HASH
- select CRYPTO_CRYPTD
- select CRYPTO_GF128MUL
+config CRYPTO_CHACHA20_NEON
+ tristate "Ciphers: ChaCha20, XChaCha20, XChaCha12 (NEON)"
+ select CRYPTO_SKCIPHER
+ select CRYPTO_ARCH_HAVE_LIB_CHACHA
help
- Use an implementation of GHASH (used by the GCM AEAD chaining mode)
- that uses the 64x64 to 128 bit polynomial multiplication (vmull.p64)
- that is part of the ARMv8 Crypto Extensions, or a slower variant that
- uses the vmull.p8 instruction that is part of the basic NEON ISA.
+ Length-preserving ciphers: ChaCha20, XChaCha20, and XChaCha12
+ stream cipher algorithms
-config CRYPTO_CRCT10DIF_ARM_CE
- tristate "CRCT10DIF digest algorithm using PMULL instructions"
- depends on KERNEL_MODE_NEON
- depends on CRC_T10DIF
- select CRYPTO_HASH
+ Architecture: arm using:
+ - NEON (Advanced SIMD) extensions
config CRYPTO_CRC32_ARM_CE
- tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
+ tristate "CRC32C and CRC32"
depends on KERNEL_MODE_NEON
depends on CRC32
select CRYPTO_HASH
+ help
+ CRC32c CRC algorithm with the iSCSI polynomial (RFC 3385 and RFC 3720)
+ and CRC32 CRC algorithm (IEEE 802.3)
-config CRYPTO_CHACHA20_NEON
- tristate "NEON and scalar accelerated ChaCha stream cipher algorithms"
- select CRYPTO_SKCIPHER
- select CRYPTO_ARCH_HAVE_LIB_CHACHA
+ Architecture: arm using:
+ - CRC and/or PMULL instructions
-config CRYPTO_POLY1305_ARM
- tristate "Accelerated scalar and SIMD Poly1305 hash implementations"
- select CRYPTO_HASH
- select CRYPTO_ARCH_HAVE_LIB_POLY1305
+ Drivers: crc32-arm-ce and crc32c-arm-ce
-config CRYPTO_NHPOLY1305_NEON
- tristate "NEON accelerated NHPoly1305 hash function (for Adiantum)"
+config CRYPTO_CRCT10DIF_ARM_CE
+ tristate "CRCT10DIF"
depends on KERNEL_MODE_NEON
- select CRYPTO_NHPOLY1305
+ depends on CRC_T10DIF
+ select CRYPTO_HASH
+ help
+ CRC16 CRC algorithm used for the T10 (SCSI) Data Integrity Field (DIF)
-config CRYPTO_CURVE25519_NEON
- tristate "NEON accelerated Curve25519 scalar multiplication library"
- depends on KERNEL_MODE_NEON
- select CRYPTO_LIB_CURVE25519_GENERIC
- select CRYPTO_ARCH_HAVE_LIB_CURVE25519
+ Architecture: arm using:
+ - PMULL (Polynomial Multiply Long) instructions
+
+endmenu
-endif
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
index 0274f81cc8ea..13e62c7c25dc 100644
--- a/arch/arm/crypto/Makefile
+++ b/arch/arm/crypto/Makefile
@@ -9,8 +9,7 @@ obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o
obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o
obj-$(CONFIG_CRYPTO_SHA256_ARM) += sha256-arm.o
obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o
-obj-$(CONFIG_CRYPTO_BLAKE2S_ARM) += blake2s-arm.o
-obj-$(if $(CONFIG_CRYPTO_BLAKE2S_ARM),y) += libblake2s-arm.o
+obj-$(CONFIG_CRYPTO_BLAKE2S_ARM) += libblake2s-arm.o
obj-$(CONFIG_CRYPTO_BLAKE2B_NEON) += blake2b-neon.o
obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o
obj-$(CONFIG_CRYPTO_POLY1305_ARM) += poly1305-arm.o
@@ -32,7 +31,6 @@ sha256-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha256_neon_glue.o
sha256-arm-y := sha256-core.o sha256_glue.o $(sha256-arm-neon-y)
sha512-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha512-neon-glue.o
sha512-arm-y := sha512-core.o sha512-glue.o $(sha512-arm-neon-y)
-blake2s-arm-y := blake2s-shash.o
libblake2s-arm-y:= blake2s-core.o blake2s-glue.o
blake2b-neon-y := blake2b-neon-core.o blake2b-neon-glue.o
sha1-arm-ce-y := sha1-ce-core.o sha1-ce-glue.o
@@ -55,7 +53,12 @@ $(obj)/%-core.S: $(src)/%-armv4.pl
clean-files += poly1305-core.S sha256-core.S sha512-core.S
+aflags-thumb2-$(CONFIG_THUMB2_KERNEL) := -U__thumb2__ -D__thumb2__=1
+
+AFLAGS_sha256-core.o += $(aflags-thumb2-y)
+AFLAGS_sha512-core.o += $(aflags-thumb2-y)
+
# massage the perlasm code a bit so we only get the NEON routine if we need it
poly1305-aflags-$(CONFIG_CPU_V7) := -U__LINUX_ARM_ARCH__ -D__LINUX_ARM_ARCH__=5
poly1305-aflags-$(CONFIG_KERNEL_MODE_NEON) := -U__LINUX_ARM_ARCH__ -D__LINUX_ARM_ARCH__=7
-AFLAGS_poly1305-core.o += $(poly1305-aflags-y)
+AFLAGS_poly1305-core.o += $(poly1305-aflags-y) $(aflags-thumb2-y)
diff --git a/arch/arm/crypto/aes-cipher-glue.c b/arch/arm/crypto/aes-cipher-glue.c
index 8cd00f56800e..6dfaef2d8f91 100644
--- a/arch/arm/crypto/aes-cipher-glue.c
+++ b/arch/arm/crypto/aes-cipher-glue.c
@@ -7,7 +7,7 @@
*/
#include <crypto/aes.h>
-#include <linux/crypto.h>
+#include <crypto/algapi.h>
#include <linux/module.h>
asmlinkage void __aes_arm_encrypt(u32 *rk, int rounds, const u8 *in, u8 *out);
diff --git a/arch/arm/crypto/blake2s-shash.c b/arch/arm/crypto/blake2s-shash.c
deleted file mode 100644
index 763c73beea2d..000000000000
--- a/arch/arm/crypto/blake2s-shash.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * BLAKE2s digest algorithm, ARM scalar implementation
- *
- * Copyright 2020 Google LLC
- */
-
-#include <crypto/internal/blake2s.h>
-#include <crypto/internal/hash.h>
-
-#include <linux/module.h>
-
-static int crypto_blake2s_update_arm(struct shash_desc *desc,
- const u8 *in, unsigned int inlen)
-{
- return crypto_blake2s_update(desc, in, inlen, false);
-}
-
-static int crypto_blake2s_final_arm(struct shash_desc *desc, u8 *out)
-{
- return crypto_blake2s_final(desc, out, false);
-}
-
-#define BLAKE2S_ALG(name, driver_name, digest_size) \
- { \
- .base.cra_name = name, \
- .base.cra_driver_name = driver_name, \
- .base.cra_priority = 200, \
- .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, \
- .base.cra_blocksize = BLAKE2S_BLOCK_SIZE, \
- .base.cra_ctxsize = sizeof(struct blake2s_tfm_ctx), \
- .base.cra_module = THIS_MODULE, \
- .digestsize = digest_size, \
- .setkey = crypto_blake2s_setkey, \
- .init = crypto_blake2s_init, \
- .update = crypto_blake2s_update_arm, \
- .final = crypto_blake2s_final_arm, \
- .descsize = sizeof(struct blake2s_state), \
- }
-
-static struct shash_alg blake2s_arm_algs[] = {
- BLAKE2S_ALG("blake2s-128", "blake2s-128-arm", BLAKE2S_128_HASH_SIZE),
- BLAKE2S_ALG("blake2s-160", "blake2s-160-arm", BLAKE2S_160_HASH_SIZE),
- BLAKE2S_ALG("blake2s-224", "blake2s-224-arm", BLAKE2S_224_HASH_SIZE),
- BLAKE2S_ALG("blake2s-256", "blake2s-256-arm", BLAKE2S_256_HASH_SIZE),
-};
-
-static int __init blake2s_arm_mod_init(void)
-{
- return IS_REACHABLE(CONFIG_CRYPTO_HASH) ?
- crypto_register_shashes(blake2s_arm_algs,
- ARRAY_SIZE(blake2s_arm_algs)) : 0;
-}
-
-static void __exit blake2s_arm_mod_exit(void)
-{
- if (IS_REACHABLE(CONFIG_CRYPTO_HASH))
- crypto_unregister_shashes(blake2s_arm_algs,
- ARRAY_SIZE(blake2s_arm_algs));
-}
-
-module_init(blake2s_arm_mod_init);
-module_exit(blake2s_arm_mod_exit);
-
-MODULE_DESCRIPTION("BLAKE2s digest algorithm, ARM scalar implementation");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Eric Biggers <ebiggers@google.com>");
-MODULE_ALIAS_CRYPTO("blake2s-128");
-MODULE_ALIAS_CRYPTO("blake2s-128-arm");
-MODULE_ALIAS_CRYPTO("blake2s-160");
-MODULE_ALIAS_CRYPTO("blake2s-160-arm");
-MODULE_ALIAS_CRYPTO("blake2s-224");
-MODULE_ALIAS_CRYPTO("blake2s-224-arm");
-MODULE_ALIAS_CRYPTO("blake2s-256");
-MODULE_ALIAS_CRYPTO("blake2s-256-arm");
diff --git a/arch/arm/crypto/ghash-ce-core.S b/arch/arm/crypto/ghash-ce-core.S
index 9f51e3fa4526..858c0d66798b 100644
--- a/arch/arm/crypto/ghash-ce-core.S
+++ b/arch/arm/crypto/ghash-ce-core.S
@@ -2,7 +2,8 @@
/*
* Accelerated GHASH implementation with NEON/ARMv8 vmull.p8/64 instructions.
*
- * Copyright (C) 2015 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ * Copyright (C) 2015 - 2017 Linaro Ltd.
+ * Copyright (C) 2023 Google LLC. <ardb@google.com>
*/
#include <linux/linkage.h>
@@ -44,7 +45,7 @@
t2q .req q7
t3q .req q8
t4q .req q9
- T2 .req q9
+ XH2 .req q9
s1l .req d20
s1h .req d21
@@ -80,7 +81,7 @@
XL2 .req q5
XM2 .req q6
- XH2 .req q7
+ T2 .req q7
T3 .req q8
XL2_L .req d10
@@ -192,9 +193,10 @@
vshr.u64 XL, XL, #1
.endm
- .macro ghash_update, pn
+ .macro ghash_update, pn, enc, aggregate=1, head=1
vld1.64 {XL}, [r1]
+ .if \head
/* do the head block first, if supplied */
ldr ip, [sp]
teq ip, #0
@@ -202,13 +204,32 @@
vld1.64 {T1}, [ip]
teq r0, #0
b 3f
+ .endif
0: .ifc \pn, p64
+ .if \aggregate
tst r0, #3 // skip until #blocks is a
bne 2f // round multiple of 4
vld1.8 {XL2-XM2}, [r2]!
-1: vld1.8 {T3-T2}, [r2]!
+1: vld1.8 {T2-T3}, [r2]!
+
+ .ifnb \enc
+ \enc\()_4x XL2, XM2, T2, T3
+
+ add ip, r3, #16
+ vld1.64 {HH}, [ip, :128]!
+ vld1.64 {HH3-HH4}, [ip, :128]
+
+ veor SHASH2_p64, SHASH_L, SHASH_H
+ veor SHASH2_H, HH_L, HH_H
+ veor HH34_L, HH3_L, HH3_H
+ veor HH34_H, HH4_L, HH4_H
+
+ vmov.i8 MASK, #0xe1
+ vshl.u64 MASK, MASK, #57
+ .endif
+
vrev64.8 XL2, XL2
vrev64.8 XM2, XM2
@@ -218,8 +239,8 @@
veor XL2_H, XL2_H, XL_L
veor XL, XL, T1
- vrev64.8 T3, T3
- vrev64.8 T1, T2
+ vrev64.8 T1, T3
+ vrev64.8 T3, T2
vmull.p64 XH, HH4_H, XL_H // a1 * b1
veor XL2_H, XL2_H, XL_H
@@ -267,14 +288,22 @@
b 1b
.endif
+ .endif
+
+2: vld1.8 {T1}, [r2]!
+
+ .ifnb \enc
+ \enc\()_1x T1
+ veor SHASH2_p64, SHASH_L, SHASH_H
+ vmov.i8 MASK, #0xe1
+ vshl.u64 MASK, MASK, #57
+ .endif
-2: vld1.64 {T1}, [r2]!
subs r0, r0, #1
3: /* multiply XL by SHASH in GF(2^128) */
-#ifndef CONFIG_CPU_BIG_ENDIAN
vrev64.8 T1, T1
-#endif
+
vext.8 IN1, T1, T1, #8
veor T1_L, T1_L, XL_H
veor XL, XL, IN1
@@ -293,9 +322,6 @@
veor XL, XL, T1
bne 0b
-
- vst1.64 {XL}, [r1]
- bx lr
.endm
/*
@@ -316,6 +342,9 @@ ENTRY(pmull_ghash_update_p64)
vshl.u64 MASK, MASK, #57
ghash_update p64
+ vst1.64 {XL}, [r1]
+
+ bx lr
ENDPROC(pmull_ghash_update_p64)
ENTRY(pmull_ghash_update_p8)
@@ -336,4 +365,331 @@ ENTRY(pmull_ghash_update_p8)
vmov.i64 k48, #0xffffffffffff
ghash_update p8
+ vst1.64 {XL}, [r1]
+
+ bx lr
ENDPROC(pmull_ghash_update_p8)
+
+ e0 .req q9
+ e1 .req q10
+ e2 .req q11
+ e3 .req q12
+ e0l .req d18
+ e0h .req d19
+ e2l .req d22
+ e2h .req d23
+ e3l .req d24
+ e3h .req d25
+ ctr .req q13
+ ctr0 .req d26
+ ctr1 .req d27
+
+ ek0 .req q14
+ ek1 .req q15
+
+ .macro round, rk:req, regs:vararg
+ .irp r, \regs
+ aese.8 \r, \rk
+ aesmc.8 \r, \r
+ .endr
+ .endm
+
+ .macro aes_encrypt, rkp, rounds, regs:vararg
+ vld1.8 {ek0-ek1}, [\rkp, :128]!
+ cmp \rounds, #12
+ blt .L\@ // AES-128
+
+ round ek0, \regs
+ vld1.8 {ek0}, [\rkp, :128]!
+ round ek1, \regs
+ vld1.8 {ek1}, [\rkp, :128]!
+
+ beq .L\@ // AES-192
+
+ round ek0, \regs
+ vld1.8 {ek0}, [\rkp, :128]!
+ round ek1, \regs
+ vld1.8 {ek1}, [\rkp, :128]!
+
+.L\@: .rept 4
+ round ek0, \regs
+ vld1.8 {ek0}, [\rkp, :128]!
+ round ek1, \regs
+ vld1.8 {ek1}, [\rkp, :128]!
+ .endr
+
+ round ek0, \regs
+ vld1.8 {ek0}, [\rkp, :128]
+
+ .irp r, \regs
+ aese.8 \r, ek1
+ .endr
+ .irp r, \regs
+ veor \r, \r, ek0
+ .endr
+ .endm
+
+pmull_aes_encrypt:
+ add ip, r5, #4
+ vld1.8 {ctr0}, [r5] // load 12 byte IV
+ vld1.8 {ctr1}, [ip]
+ rev r8, r7
+ vext.8 ctr1, ctr1, ctr1, #4
+ add r7, r7, #1
+ vmov.32 ctr1[1], r8
+ vmov e0, ctr
+
+ add ip, r3, #64
+ aes_encrypt ip, r6, e0
+ bx lr
+ENDPROC(pmull_aes_encrypt)
+
+pmull_aes_encrypt_4x:
+ add ip, r5, #4
+ vld1.8 {ctr0}, [r5]
+ vld1.8 {ctr1}, [ip]
+ rev r8, r7
+ vext.8 ctr1, ctr1, ctr1, #4
+ add r7, r7, #1
+ vmov.32 ctr1[1], r8
+ rev ip, r7
+ vmov e0, ctr
+ add r7, r7, #1
+ vmov.32 ctr1[1], ip
+ rev r8, r7
+ vmov e1, ctr
+ add r7, r7, #1
+ vmov.32 ctr1[1], r8
+ rev ip, r7
+ vmov e2, ctr
+ add r7, r7, #1
+ vmov.32 ctr1[1], ip
+ vmov e3, ctr
+
+ add ip, r3, #64
+ aes_encrypt ip, r6, e0, e1, e2, e3
+ bx lr
+ENDPROC(pmull_aes_encrypt_4x)
+
+pmull_aes_encrypt_final:
+ add ip, r5, #4
+ vld1.8 {ctr0}, [r5]
+ vld1.8 {ctr1}, [ip]
+ rev r8, r7
+ vext.8 ctr1, ctr1, ctr1, #4
+ mov r7, #1 << 24 // BE #1 for the tag
+ vmov.32 ctr1[1], r8
+ vmov e0, ctr
+ vmov.32 ctr1[1], r7
+ vmov e1, ctr
+
+ add ip, r3, #64
+ aes_encrypt ip, r6, e0, e1
+ bx lr
+ENDPROC(pmull_aes_encrypt_final)
+
+ .macro enc_1x, in0
+ bl pmull_aes_encrypt
+ veor \in0, \in0, e0
+ vst1.8 {\in0}, [r4]!
+ .endm
+
+ .macro dec_1x, in0
+ bl pmull_aes_encrypt
+ veor e0, e0, \in0
+ vst1.8 {e0}, [r4]!
+ .endm
+
+ .macro enc_4x, in0, in1, in2, in3
+ bl pmull_aes_encrypt_4x
+
+ veor \in0, \in0, e0
+ veor \in1, \in1, e1
+ veor \in2, \in2, e2
+ veor \in3, \in3, e3
+
+ vst1.8 {\in0-\in1}, [r4]!
+ vst1.8 {\in2-\in3}, [r4]!
+ .endm
+
+ .macro dec_4x, in0, in1, in2, in3
+ bl pmull_aes_encrypt_4x
+
+ veor e0, e0, \in0
+ veor e1, e1, \in1
+ veor e2, e2, \in2
+ veor e3, e3, \in3
+
+ vst1.8 {e0-e1}, [r4]!
+ vst1.8 {e2-e3}, [r4]!
+ .endm
+
+ /*
+ * void pmull_gcm_encrypt(int blocks, u64 dg[], const char *src,
+ * struct gcm_key const *k, char *dst,
+ * char *iv, int rounds, u32 counter)
+ */
+ENTRY(pmull_gcm_encrypt)
+ push {r4-r8, lr}
+ ldrd r4, r5, [sp, #24]
+ ldrd r6, r7, [sp, #32]
+
+ vld1.64 {SHASH}, [r3]
+
+ ghash_update p64, enc, head=0
+ vst1.64 {XL}, [r1]
+
+ pop {r4-r8, pc}
+ENDPROC(pmull_gcm_encrypt)
+
+ /*
+ * void pmull_gcm_decrypt(int blocks, u64 dg[], const char *src,
+ * struct gcm_key const *k, char *dst,
+ * char *iv, int rounds, u32 counter)
+ */
+ENTRY(pmull_gcm_decrypt)
+ push {r4-r8, lr}
+ ldrd r4, r5, [sp, #24]
+ ldrd r6, r7, [sp, #32]
+
+ vld1.64 {SHASH}, [r3]
+
+ ghash_update p64, dec, head=0
+ vst1.64 {XL}, [r1]
+
+ pop {r4-r8, pc}
+ENDPROC(pmull_gcm_decrypt)
+
+ /*
+ * void pmull_gcm_enc_final(int bytes, u64 dg[], char *tag,
+ * struct gcm_key const *k, char *head,
+ * char *iv, int rounds, u32 counter)
+ */
+ENTRY(pmull_gcm_enc_final)
+ push {r4-r8, lr}
+ ldrd r4, r5, [sp, #24]
+ ldrd r6, r7, [sp, #32]
+
+ bl pmull_aes_encrypt_final
+
+ cmp r0, #0
+ beq .Lenc_final
+
+ mov_l ip, .Lpermute
+ sub r4, r4, #16
+ add r8, ip, r0
+ add ip, ip, #32
+ add r4, r4, r0
+ sub ip, ip, r0
+
+ vld1.8 {e3}, [r8] // permute vector for key stream
+ vld1.8 {e2}, [ip] // permute vector for ghash input
+
+ vtbl.8 e3l, {e0}, e3l
+ vtbl.8 e3h, {e0}, e3h
+
+ vld1.8 {e0}, [r4] // encrypt tail block
+ veor e0, e0, e3
+ vst1.8 {e0}, [r4]
+
+ vtbl.8 T1_L, {e0}, e2l
+ vtbl.8 T1_H, {e0}, e2h
+
+ vld1.64 {XL}, [r1]
+.Lenc_final:
+ vld1.64 {SHASH}, [r3, :128]
+ vmov.i8 MASK, #0xe1
+ veor SHASH2_p64, SHASH_L, SHASH_H
+ vshl.u64 MASK, MASK, #57
+ mov r0, #1
+ bne 3f // process head block first
+ ghash_update p64, aggregate=0, head=0
+
+ vrev64.8 XL, XL
+ vext.8 XL, XL, XL, #8
+ veor XL, XL, e1
+
+ sub r2, r2, #16 // rewind src pointer
+ vst1.8 {XL}, [r2] // store tag
+
+ pop {r4-r8, pc}
+ENDPROC(pmull_gcm_enc_final)
+
+ /*
+ * int pmull_gcm_dec_final(int bytes, u64 dg[], char *tag,
+ * struct gcm_key const *k, char *head,
+ * char *iv, int rounds, u32 counter,
+ * const char *otag, int authsize)
+ */
+ENTRY(pmull_gcm_dec_final)
+ push {r4-r8, lr}
+ ldrd r4, r5, [sp, #24]
+ ldrd r6, r7, [sp, #32]
+
+ bl pmull_aes_encrypt_final
+
+ cmp r0, #0
+ beq .Ldec_final
+
+ mov_l ip, .Lpermute
+ sub r4, r4, #16
+ add r8, ip, r0
+ add ip, ip, #32
+ add r4, r4, r0
+ sub ip, ip, r0
+
+ vld1.8 {e3}, [r8] // permute vector for key stream
+ vld1.8 {e2}, [ip] // permute vector for ghash input
+
+ vtbl.8 e3l, {e0}, e3l
+ vtbl.8 e3h, {e0}, e3h
+
+ vld1.8 {e0}, [r4]
+
+ vtbl.8 T1_L, {e0}, e2l
+ vtbl.8 T1_H, {e0}, e2h
+
+ veor e0, e0, e3
+ vst1.8 {e0}, [r4]
+
+ vld1.64 {XL}, [r1]
+.Ldec_final:
+ vld1.64 {SHASH}, [r3]
+ vmov.i8 MASK, #0xe1
+ veor SHASH2_p64, SHASH_L, SHASH_H
+ vshl.u64 MASK, MASK, #57
+ mov r0, #1
+ bne 3f // process head block first
+ ghash_update p64, aggregate=0, head=0
+
+ vrev64.8 XL, XL
+ vext.8 XL, XL, XL, #8
+ veor XL, XL, e1
+
+ mov_l ip, .Lpermute
+ ldrd r2, r3, [sp, #40] // otag and authsize
+ vld1.8 {T1}, [r2]
+ add ip, ip, r3
+ vceq.i8 T1, T1, XL // compare tags
+ vmvn T1, T1 // 0 for eq, -1 for ne
+
+ vld1.8 {e0}, [ip]
+ vtbl.8 XL_L, {T1}, e0l // keep authsize bytes only
+ vtbl.8 XL_H, {T1}, e0h
+
+ vpmin.s8 XL_L, XL_L, XL_H // take the minimum s8 across the vector
+ vpmin.s8 XL_L, XL_L, XL_L
+ vmov.32 r0, XL_L[0] // fail if != 0x0
+
+ pop {r4-r8, pc}
+ENDPROC(pmull_gcm_dec_final)
+
+ .section ".rodata", "a", %progbits
+ .align 5
+.Lpermute:
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
+ .byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
diff --git a/arch/arm/crypto/ghash-ce-glue.c b/arch/arm/crypto/ghash-ce-glue.c
index f13401f3e669..3ddf05b4234d 100644
--- a/arch/arm/crypto/ghash-ce-glue.c
+++ b/arch/arm/crypto/ghash-ce-glue.c
@@ -2,36 +2,53 @@
/*
* Accelerated GHASH implementation with ARMv8 vmull.p64 instructions.
*
- * Copyright (C) 2015 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ * Copyright (C) 2015 - 2018 Linaro Ltd.
+ * Copyright (C) 2023 Google LLC.
*/
#include <asm/hwcap.h>
#include <asm/neon.h>
#include <asm/simd.h>
#include <asm/unaligned.h>
+#include <crypto/aes.h>
+#include <crypto/gcm.h>
#include <crypto/b128ops.h>
#include <crypto/cryptd.h>
+#include <crypto/internal/aead.h>
#include <crypto/internal/hash.h>
#include <crypto/internal/simd.h>
+#include <crypto/internal/skcipher.h>
#include <crypto/gf128mul.h>
+#include <crypto/scatterwalk.h>
#include <linux/cpufeature.h>
#include <linux/crypto.h>
#include <linux/jump_label.h>
#include <linux/module.h>
MODULE_DESCRIPTION("GHASH hash function using ARMv8 Crypto Extensions");
-MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
-MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Ard Biesheuvel <ardb@kernel.org>");
+MODULE_LICENSE("GPL");
MODULE_ALIAS_CRYPTO("ghash");
+MODULE_ALIAS_CRYPTO("gcm(aes)");
+MODULE_ALIAS_CRYPTO("rfc4106(gcm(aes))");
#define GHASH_BLOCK_SIZE 16
#define GHASH_DIGEST_SIZE 16
+#define RFC4106_NONCE_SIZE 4
+
struct ghash_key {
be128 k;
u64 h[][2];
};
+struct gcm_key {
+ u64 h[4][2];
+ u32 rk[AES_MAX_KEYLENGTH_U32];
+ int rounds;
+ u8 nonce[]; // for RFC4106 nonce
+};
+
struct ghash_desc_ctx {
u64 digest[GHASH_DIGEST_SIZE/sizeof(u64)];
u8 buf[GHASH_BLOCK_SIZE];
@@ -344,6 +361,393 @@ static struct ahash_alg ghash_async_alg = {
},
};
+
+void pmull_gcm_encrypt(int blocks, u64 dg[], const char *src,
+ struct gcm_key const *k, char *dst,
+ const char *iv, int rounds, u32 counter);
+
+void pmull_gcm_enc_final(int blocks, u64 dg[], char *tag,
+ struct gcm_key const *k, char *head,
+ const char *iv, int rounds, u32 counter);
+
+void pmull_gcm_decrypt(int bytes, u64 dg[], const char *src,
+ struct gcm_key const *k, char *dst,
+ const char *iv, int rounds, u32 counter);
+
+int pmull_gcm_dec_final(int bytes, u64 dg[], char *tag,
+ struct gcm_key const *k, char *head,
+ const char *iv, int rounds, u32 counter,
+ const char *otag, int authsize);
+
+static int gcm_aes_setkey(struct crypto_aead *tfm, const u8 *inkey,
+ unsigned int keylen)
+{
+ struct gcm_key *ctx = crypto_aead_ctx(tfm);
+ struct crypto_aes_ctx aes_ctx;
+ be128 h, k;
+ int ret;
+
+ ret = aes_expandkey(&aes_ctx, inkey, keylen);
+ if (ret)
+ return -EINVAL;
+
+ aes_encrypt(&aes_ctx, (u8 *)&k, (u8[AES_BLOCK_SIZE]){});
+
+ memcpy(ctx->rk, aes_ctx.key_enc, sizeof(ctx->rk));
+ ctx->rounds = 6 + keylen / 4;
+
+ memzero_explicit(&aes_ctx, sizeof(aes_ctx));
+
+ ghash_reflect(ctx->h[0], &k);
+
+ h = k;
+ gf128mul_lle(&h, &k);
+ ghash_reflect(ctx->h[1], &h);
+
+ gf128mul_lle(&h, &k);
+ ghash_reflect(ctx->h[2], &h);
+
+ gf128mul_lle(&h, &k);
+ ghash_reflect(ctx->h[3], &h);
+
+ return 0;
+}
+
+static int gcm_aes_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
+{
+ return crypto_gcm_check_authsize(authsize);
+}
+
+static void gcm_update_mac(u64 dg[], const u8 *src, int count, u8 buf[],
+ int *buf_count, struct gcm_key *ctx)
+{
+ if (*buf_count > 0) {
+ int buf_added = min(count, GHASH_BLOCK_SIZE - *buf_count);
+
+ memcpy(&buf[*buf_count], src, buf_added);
+
+ *buf_count += buf_added;
+ src += buf_added;
+ count -= buf_added;
+ }
+
+ if (count >= GHASH_BLOCK_SIZE || *buf_count == GHASH_BLOCK_SIZE) {
+ int blocks = count / GHASH_BLOCK_SIZE;
+
+ pmull_ghash_update_p64(blocks, dg, src, ctx->h,
+ *buf_count ? buf : NULL);
+
+ src += blocks * GHASH_BLOCK_SIZE;
+ count %= GHASH_BLOCK_SIZE;
+ *buf_count = 0;
+ }
+
+ if (count > 0) {
+ memcpy(buf, src, count);
+ *buf_count = count;
+ }
+}
+
+static void gcm_calculate_auth_mac(struct aead_request *req, u64 dg[], u32 len)
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(req);
+ struct gcm_key *ctx = crypto_aead_ctx(aead);
+ u8 buf[GHASH_BLOCK_SIZE];
+ struct scatter_walk walk;
+ int buf_count = 0;
+
+ scatterwalk_start(&walk, req->src);
+
+ do {
+ u32 n = scatterwalk_clamp(&walk, len);
+ u8 *p;
+
+ if (!n) {
+ scatterwalk_start(&walk, sg_next(walk.sg));
+ n = scatterwalk_clamp(&walk, len);
+ }
+
+ p = scatterwalk_map(&walk);
+ gcm_update_mac(dg, p, n, buf, &buf_count, ctx);
+ scatterwalk_unmap(p);
+
+ if (unlikely(len / SZ_4K > (len - n) / SZ_4K)) {
+ kernel_neon_end();
+ kernel_neon_begin();
+ }
+
+ len -= n;
+ scatterwalk_advance(&walk, n);
+ scatterwalk_done(&walk, 0, len);
+ } while (len);
+
+ if (buf_count) {
+ memset(&buf[buf_count], 0, GHASH_BLOCK_SIZE - buf_count);
+ pmull_ghash_update_p64(1, dg, buf, ctx->h, NULL);
+ }
+}
+
+static int gcm_encrypt(struct aead_request *req, const u8 *iv, u32 assoclen)
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(req);
+ struct gcm_key *ctx = crypto_aead_ctx(aead);
+ struct skcipher_walk walk;
+ u8 buf[AES_BLOCK_SIZE];
+ u32 counter = 2;
+ u64 dg[2] = {};
+ be128 lengths;
+ const u8 *src;
+ u8 *tag, *dst;
+ int tail, err;
+
+ if (WARN_ON_ONCE(!may_use_simd()))
+ return -EBUSY;
+
+ err = skcipher_walk_aead_encrypt(&walk, req, false);
+
+ kernel_neon_begin();
+
+ if (assoclen)
+ gcm_calculate_auth_mac(req, dg, assoclen);
+
+ src = walk.src.virt.addr;
+ dst = walk.dst.virt.addr;
+
+ while (walk.nbytes >= AES_BLOCK_SIZE) {
+ int nblocks = walk.nbytes / AES_BLOCK_SIZE;
+
+ pmull_gcm_encrypt(nblocks, dg, src, ctx, dst, iv,
+ ctx->rounds, counter);
+ counter += nblocks;
+
+ if (walk.nbytes == walk.total) {
+ src += nblocks * AES_BLOCK_SIZE;
+ dst += nblocks * AES_BLOCK_SIZE;
+ break;
+ }
+
+ kernel_neon_end();
+
+ err = skcipher_walk_done(&walk,
+ walk.nbytes % AES_BLOCK_SIZE);
+ if (err)
+ return err;
+
+ src = walk.src.virt.addr;
+ dst = walk.dst.virt.addr;
+
+ kernel_neon_begin();
+ }
+
+
+ lengths.a = cpu_to_be64(assoclen * 8);
+ lengths.b = cpu_to_be64(req->cryptlen * 8);
+
+ tag = (u8 *)&lengths;
+ tail = walk.nbytes % AES_BLOCK_SIZE;
+
+ /*
+ * Bounce via a buffer unless we are encrypting in place and src/dst
+ * are not pointing to the start of the walk buffer. In that case, we
+ * can do a NEON load/xor/store sequence in place as long as we move
+ * the plain/ciphertext and keystream to the start of the register. If
+ * not, do a memcpy() to the end of the buffer so we can reuse the same
+ * logic.
+ */
+ if (unlikely(tail && (tail == walk.nbytes || src != dst)))
+ src = memcpy(buf + sizeof(buf) - tail, src, tail);
+
+ pmull_gcm_enc_final(tail, dg, tag, ctx, (u8 *)src, iv,
+ ctx->rounds, counter);
+ kernel_neon_end();
+
+ if (unlikely(tail && src != dst))
+ memcpy(dst, src, tail);
+
+ if (walk.nbytes) {
+ err = skcipher_walk_done(&walk, 0);
+ if (err)
+ return err;
+ }
+
+ /* copy authtag to end of dst */
+ scatterwalk_map_and_copy(tag, req->dst, req->assoclen + req->cryptlen,
+ crypto_aead_authsize(aead), 1);
+
+ return 0;
+}
+
+static int gcm_decrypt(struct aead_request *req, const u8 *iv, u32 assoclen)
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(req);
+ struct gcm_key *ctx = crypto_aead_ctx(aead);
+ int authsize = crypto_aead_authsize(aead);
+ struct skcipher_walk walk;
+ u8 otag[AES_BLOCK_SIZE];
+ u8 buf[AES_BLOCK_SIZE];
+ u32 counter = 2;
+ u64 dg[2] = {};
+ be128 lengths;
+ const u8 *src;
+ u8 *tag, *dst;
+ int tail, err, ret;
+
+ if (WARN_ON_ONCE(!may_use_simd()))
+ return -EBUSY;
+
+ scatterwalk_map_and_copy(otag, req->src,
+ req->assoclen + req->cryptlen - authsize,
+ authsize, 0);
+
+ err = skcipher_walk_aead_decrypt(&walk, req, false);
+
+ kernel_neon_begin();
+
+ if (assoclen)
+ gcm_calculate_auth_mac(req, dg, assoclen);
+
+ src = walk.src.virt.addr;
+ dst = walk.dst.virt.addr;
+
+ while (walk.nbytes >= AES_BLOCK_SIZE) {
+ int nblocks = walk.nbytes / AES_BLOCK_SIZE;
+
+ pmull_gcm_decrypt(nblocks, dg, src, ctx, dst, iv,
+ ctx->rounds, counter);
+ counter += nblocks;
+
+ if (walk.nbytes == walk.total) {
+ src += nblocks * AES_BLOCK_SIZE;
+ dst += nblocks * AES_BLOCK_SIZE;
+ break;
+ }
+
+ kernel_neon_end();
+
+ err = skcipher_walk_done(&walk,
+ walk.nbytes % AES_BLOCK_SIZE);
+ if (err)
+ return err;
+
+ src = walk.src.virt.addr;
+ dst = walk.dst.virt.addr;
+
+ kernel_neon_begin();
+ }
+
+ lengths.a = cpu_to_be64(assoclen * 8);
+ lengths.b = cpu_to_be64((req->cryptlen - authsize) * 8);
+
+ tag = (u8 *)&lengths;
+ tail = walk.nbytes % AES_BLOCK_SIZE;
+
+ if (unlikely(tail && (tail == walk.nbytes || src != dst)))
+ src = memcpy(buf + sizeof(buf) - tail, src, tail);
+
+ ret = pmull_gcm_dec_final(tail, dg, tag, ctx, (u8 *)src, iv,
+ ctx->rounds, counter, otag, authsize);
+ kernel_neon_end();
+
+ if (unlikely(tail && src != dst))
+ memcpy(dst, src, tail);
+
+ if (walk.nbytes) {
+ err = skcipher_walk_done(&walk, 0);
+ if (err)
+ return err;
+ }
+
+ return ret ? -EBADMSG : 0;
+}
+
+static int gcm_aes_encrypt(struct aead_request *req)
+{
+ return gcm_encrypt(req, req->iv, req->assoclen);
+}
+
+static int gcm_aes_decrypt(struct aead_request *req)
+{
+ return gcm_decrypt(req, req->iv, req->assoclen);
+}
+
+static int rfc4106_setkey(struct crypto_aead *tfm, const u8 *inkey,
+ unsigned int keylen)
+{
+ struct gcm_key *ctx = crypto_aead_ctx(tfm);
+ int err;
+
+ keylen -= RFC4106_NONCE_SIZE;
+ err = gcm_aes_setkey(tfm, inkey, keylen);
+ if (err)
+ return err;
+
+ memcpy(ctx->nonce, inkey + keylen, RFC4106_NONCE_SIZE);
+ return 0;
+}
+
+static int rfc4106_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
+{
+ return crypto_rfc4106_check_authsize(authsize);
+}
+
+static int rfc4106_encrypt(struct aead_request *req)
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(req);
+ struct gcm_key *ctx = crypto_aead_ctx(aead);
+ u8 iv[GCM_AES_IV_SIZE];
+
+ memcpy(iv, ctx->nonce, RFC4106_NONCE_SIZE);
+ memcpy(iv + RFC4106_NONCE_SIZE, req->iv, GCM_RFC4106_IV_SIZE);
+
+ return crypto_ipsec_check_assoclen(req->assoclen) ?:
+ gcm_encrypt(req, iv, req->assoclen - GCM_RFC4106_IV_SIZE);
+}
+
+static int rfc4106_decrypt(struct aead_request *req)
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(req);
+ struct gcm_key *ctx = crypto_aead_ctx(aead);
+ u8 iv[GCM_AES_IV_SIZE];
+
+ memcpy(iv, ctx->nonce, RFC4106_NONCE_SIZE);
+ memcpy(iv + RFC4106_NONCE_SIZE, req->iv, GCM_RFC4106_IV_SIZE);
+
+ return crypto_ipsec_check_assoclen(req->assoclen) ?:
+ gcm_decrypt(req, iv, req->assoclen - GCM_RFC4106_IV_SIZE);
+}
+
+static struct aead_alg gcm_aes_algs[] = {{
+ .ivsize = GCM_AES_IV_SIZE,
+ .chunksize = AES_BLOCK_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ .setkey = gcm_aes_setkey,
+ .setauthsize = gcm_aes_setauthsize,
+ .encrypt = gcm_aes_encrypt,
+ .decrypt = gcm_aes_decrypt,
+
+ .base.cra_name = "gcm(aes)",
+ .base.cra_driver_name = "gcm-aes-ce",
+ .base.cra_priority = 400,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct gcm_key),
+ .base.cra_module = THIS_MODULE,
+}, {
+ .ivsize = GCM_RFC4106_IV_SIZE,
+ .chunksize = AES_BLOCK_SIZE,
+ .maxauthsize = AES_BLOCK_SIZE,
+ .setkey = rfc4106_setkey,
+ .setauthsize = rfc4106_setauthsize,
+ .encrypt = rfc4106_encrypt,
+ .decrypt = rfc4106_decrypt,
+
+ .base.cra_name = "rfc4106(gcm(aes))",
+ .base.cra_driver_name = "rfc4106-gcm-aes-ce",
+ .base.cra_priority = 400,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct gcm_key) + RFC4106_NONCE_SIZE,
+ .base.cra_module = THIS_MODULE,
+}};
+
static int __init ghash_ce_mod_init(void)
{
int err;
@@ -352,13 +756,17 @@ static int __init ghash_ce_mod_init(void)
return -ENODEV;
if (elf_hwcap2 & HWCAP2_PMULL) {
+ err = crypto_register_aeads(gcm_aes_algs,
+ ARRAY_SIZE(gcm_aes_algs));
+ if (err)
+ return err;
ghash_alg.base.cra_ctxsize += 3 * sizeof(u64[2]);
static_branch_enable(&use_p64);
}
err = crypto_register_shash(&ghash_alg);
if (err)
- return err;
+ goto err_aead;
err = crypto_register_ahash(&ghash_async_alg);
if (err)
goto err_shash;
@@ -367,6 +775,10 @@ static int __init ghash_ce_mod_init(void)
err_shash:
crypto_unregister_shash(&ghash_alg);
+err_aead:
+ if (elf_hwcap2 & HWCAP2_PMULL)
+ crypto_unregister_aeads(gcm_aes_algs,
+ ARRAY_SIZE(gcm_aes_algs));
return err;
}
@@ -374,6 +786,9 @@ static void __exit ghash_ce_mod_exit(void)
{
crypto_unregister_ahash(&ghash_async_alg);
crypto_unregister_shash(&ghash_alg);
+ if (elf_hwcap2 & HWCAP2_PMULL)
+ crypto_unregister_aeads(gcm_aes_algs,
+ ARRAY_SIZE(gcm_aes_algs));
}
module_init(ghash_ce_mod_init);
diff --git a/arch/arm/crypto/nh-neon-core.S b/arch/arm/crypto/nh-neon-core.S
index 434d80ab531c..01620a0782ca 100644
--- a/arch/arm/crypto/nh-neon-core.S
+++ b/arch/arm/crypto/nh-neon-core.S
@@ -69,7 +69,7 @@
/*
* void nh_neon(const u32 *key, const u8 *message, size_t message_len,
- * u8 hash[NH_HASH_BYTES])
+ * __le64 hash[NH_NUM_PASSES])
*
* It's guaranteed that message_len % 16 == 0.
*/
diff --git a/arch/arm/crypto/nhpoly1305-neon-glue.c b/arch/arm/crypto/nhpoly1305-neon-glue.c
index ffa8d73fe722..e93e41ff2656 100644
--- a/arch/arm/crypto/nhpoly1305-neon-glue.c
+++ b/arch/arm/crypto/nhpoly1305-neon-glue.c
@@ -14,14 +14,7 @@
#include <linux/module.h>
asmlinkage void nh_neon(const u32 *key, const u8 *message, size_t message_len,
- u8 hash[NH_HASH_BYTES]);
-
-/* wrapper to avoid indirect call to assembly, which doesn't work with CFI */
-static void _nh_neon(const u32 *key, const u8 *message, size_t message_len,
- __le64 hash[NH_NUM_PASSES])
-{
- nh_neon(key, message, message_len, (u8 *)hash);
-}
+ __le64 hash[NH_NUM_PASSES]);
static int nhpoly1305_neon_update(struct shash_desc *desc,
const u8 *src, unsigned int srclen)
@@ -33,7 +26,7 @@ static int nhpoly1305_neon_update(struct shash_desc *desc,
unsigned int n = min_t(unsigned int, srclen, SZ_4K);
kernel_neon_begin();
- crypto_nhpoly1305_update_helper(desc, src, n, _nh_neon);
+ crypto_nhpoly1305_update_helper(desc, src, n, nh_neon);
kernel_neon_end();
src += n;
srclen -= n;
diff --git a/arch/arm/crypto/sha1_glue.c b/arch/arm/crypto/sha1_glue.c
index 6c2b849e459d..95a727bcd664 100644
--- a/arch/arm/crypto/sha1_glue.c
+++ b/arch/arm/crypto/sha1_glue.c
@@ -21,31 +21,29 @@
#include "sha1.h"
-asmlinkage void sha1_block_data_order(u32 *digest,
- const unsigned char *data, unsigned int rounds);
+asmlinkage void sha1_block_data_order(struct sha1_state *digest,
+ const u8 *data, int rounds);
int sha1_update_arm(struct shash_desc *desc, const u8 *data,
unsigned int len)
{
- /* make sure casting to sha1_block_fn() is safe */
+ /* make sure signature matches sha1_block_fn() */
BUILD_BUG_ON(offsetof(struct sha1_state, state) != 0);
- return sha1_base_do_update(desc, data, len,
- (sha1_block_fn *)sha1_block_data_order);
+ return sha1_base_do_update(desc, data, len, sha1_block_data_order);
}
EXPORT_SYMBOL_GPL(sha1_update_arm);
static int sha1_final(struct shash_desc *desc, u8 *out)
{
- sha1_base_do_finalize(desc, (sha1_block_fn *)sha1_block_data_order);
+ sha1_base_do_finalize(desc, sha1_block_data_order);
return sha1_base_finish(desc, out);
}
int sha1_finup_arm(struct shash_desc *desc, const u8 *data,
unsigned int len, u8 *out)
{
- sha1_base_do_update(desc, data, len,
- (sha1_block_fn *)sha1_block_data_order);
+ sha1_base_do_update(desc, data, len, sha1_block_data_order);
return sha1_final(desc, out);
}
EXPORT_SYMBOL_GPL(sha1_finup_arm);
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 413abfb42989..311e83038bdb 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -48,6 +48,7 @@ static inline u32 read_ ## a64(void) \
return read_sysreg(a32); \
} \
+CPUIF_MAP(ICC_EOIR1, ICC_EOIR1_EL1)
CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
@@ -63,12 +64,6 @@ CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
/* Low-level accessors */
-static inline void gic_write_eoir(u32 irq)
-{
- write_sysreg(irq, ICC_EOIR1);
- isb();
-}
-
static inline void gic_write_dir(u32 val)
{
write_sysreg(val, ICC_DIR);
@@ -257,5 +252,10 @@ static inline void gic_arch_enable_irqs(void)
WARN_ON_ONCE(true);
}
+static inline bool gic_has_relaxed_pmr_sync(void)
+{
+ return false;
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* !__ASM_ARCH_GICV3_H */
diff --git a/arch/arm/include/asm/archrandom.h b/arch/arm/include/asm/archrandom.h
index a8e84ca5c2ee..cc4714eb1a75 100644
--- a/arch/arm/include/asm/archrandom.h
+++ b/arch/arm/include/asm/archrandom.h
@@ -7,4 +7,6 @@ static inline bool __init smccc_probe_trng(void)
return false;
}
+#include <asm-generic/archrandom.h>
+
#endif /* _ASM_ARCHRANDOM_H */
diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h
new file mode 100644
index 000000000000..78d3d4b82c6c
--- /dev/null
+++ b/arch/arm/include/asm/arm_pmuv3.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ */
+
+#ifndef __ASM_PMUV3_H
+#define __ASM_PMUV3_H
+
+#include <asm/cp15.h>
+#include <asm/cputype.h>
+
+#define PMCCNTR __ACCESS_CP15_64(0, c9)
+
+#define PMCR __ACCESS_CP15(c9, 0, c12, 0)
+#define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1)
+#define PMCNTENCLR __ACCESS_CP15(c9, 0, c12, 2)
+#define PMOVSR __ACCESS_CP15(c9, 0, c12, 3)
+#define PMSELR __ACCESS_CP15(c9, 0, c12, 5)
+#define PMCEID0 __ACCESS_CP15(c9, 0, c12, 6)
+#define PMCEID1 __ACCESS_CP15(c9, 0, c12, 7)
+#define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1)
+#define PMXEVCNTR __ACCESS_CP15(c9, 0, c13, 2)
+#define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0)
+#define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1)
+#define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2)
+#define PMMIR __ACCESS_CP15(c9, 0, c14, 6)
+#define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7)
+
+#define PMEVCNTR0 __ACCESS_CP15(c14, 0, c8, 0)
+#define PMEVCNTR1 __ACCESS_CP15(c14, 0, c8, 1)
+#define PMEVCNTR2 __ACCESS_CP15(c14, 0, c8, 2)
+#define PMEVCNTR3 __ACCESS_CP15(c14, 0, c8, 3)
+#define PMEVCNTR4 __ACCESS_CP15(c14, 0, c8, 4)
+#define PMEVCNTR5 __ACCESS_CP15(c14, 0, c8, 5)
+#define PMEVCNTR6 __ACCESS_CP15(c14, 0, c8, 6)
+#define PMEVCNTR7 __ACCESS_CP15(c14, 0, c8, 7)
+#define PMEVCNTR8 __ACCESS_CP15(c14, 0, c9, 0)
+#define PMEVCNTR9 __ACCESS_CP15(c14, 0, c9, 1)
+#define PMEVCNTR10 __ACCESS_CP15(c14, 0, c9, 2)
+#define PMEVCNTR11 __ACCESS_CP15(c14, 0, c9, 3)
+#define PMEVCNTR12 __ACCESS_CP15(c14, 0, c9, 4)
+#define PMEVCNTR13 __ACCESS_CP15(c14, 0, c9, 5)
+#define PMEVCNTR14 __ACCESS_CP15(c14, 0, c9, 6)
+#define PMEVCNTR15 __ACCESS_CP15(c14, 0, c9, 7)
+#define PMEVCNTR16 __ACCESS_CP15(c14, 0, c10, 0)
+#define PMEVCNTR17 __ACCESS_CP15(c14, 0, c10, 1)
+#define PMEVCNTR18 __ACCESS_CP15(c14, 0, c10, 2)
+#define PMEVCNTR19 __ACCESS_CP15(c14, 0, c10, 3)
+#define PMEVCNTR20 __ACCESS_CP15(c14, 0, c10, 4)
+#define PMEVCNTR21 __ACCESS_CP15(c14, 0, c10, 5)
+#define PMEVCNTR22 __ACCESS_CP15(c14, 0, c10, 6)
+#define PMEVCNTR23 __ACCESS_CP15(c14, 0, c10, 7)
+#define PMEVCNTR24 __ACCESS_CP15(c14, 0, c11, 0)
+#define PMEVCNTR25 __ACCESS_CP15(c14, 0, c11, 1)
+#define PMEVCNTR26 __ACCESS_CP15(c14, 0, c11, 2)
+#define PMEVCNTR27 __ACCESS_CP15(c14, 0, c11, 3)
+#define PMEVCNTR28 __ACCESS_CP15(c14, 0, c11, 4)
+#define PMEVCNTR29 __ACCESS_CP15(c14, 0, c11, 5)
+#define PMEVCNTR30 __ACCESS_CP15(c14, 0, c11, 6)
+
+#define PMEVTYPER0 __ACCESS_CP15(c14, 0, c12, 0)
+#define PMEVTYPER1 __ACCESS_CP15(c14, 0, c12, 1)
+#define PMEVTYPER2 __ACCESS_CP15(c14, 0, c12, 2)
+#define PMEVTYPER3 __ACCESS_CP15(c14, 0, c12, 3)
+#define PMEVTYPER4 __ACCESS_CP15(c14, 0, c12, 4)
+#define PMEVTYPER5 __ACCESS_CP15(c14, 0, c12, 5)
+#define PMEVTYPER6 __ACCESS_CP15(c14, 0, c12, 6)
+#define PMEVTYPER7 __ACCESS_CP15(c14, 0, c12, 7)
+#define PMEVTYPER8 __ACCESS_CP15(c14, 0, c13, 0)
+#define PMEVTYPER9 __ACCESS_CP15(c14, 0, c13, 1)
+#define PMEVTYPER10 __ACCESS_CP15(c14, 0, c13, 2)
+#define PMEVTYPER11 __ACCESS_CP15(c14, 0, c13, 3)
+#define PMEVTYPER12 __ACCESS_CP15(c14, 0, c13, 4)
+#define PMEVTYPER13 __ACCESS_CP15(c14, 0, c13, 5)
+#define PMEVTYPER14 __ACCESS_CP15(c14, 0, c13, 6)
+#define PMEVTYPER15 __ACCESS_CP15(c14, 0, c13, 7)
+#define PMEVTYPER16 __ACCESS_CP15(c14, 0, c14, 0)
+#define PMEVTYPER17 __ACCESS_CP15(c14, 0, c14, 1)
+#define PMEVTYPER18 __ACCESS_CP15(c14, 0, c14, 2)
+#define PMEVTYPER19 __ACCESS_CP15(c14, 0, c14, 3)
+#define PMEVTYPER20 __ACCESS_CP15(c14, 0, c14, 4)
+#define PMEVTYPER21 __ACCESS_CP15(c14, 0, c14, 5)
+#define PMEVTYPER22 __ACCESS_CP15(c14, 0, c14, 6)
+#define PMEVTYPER23 __ACCESS_CP15(c14, 0, c14, 7)
+#define PMEVTYPER24 __ACCESS_CP15(c14, 0, c15, 0)
+#define PMEVTYPER25 __ACCESS_CP15(c14, 0, c15, 1)
+#define PMEVTYPER26 __ACCESS_CP15(c14, 0, c15, 2)
+#define PMEVTYPER27 __ACCESS_CP15(c14, 0, c15, 3)
+#define PMEVTYPER28 __ACCESS_CP15(c14, 0, c15, 4)
+#define PMEVTYPER29 __ACCESS_CP15(c14, 0, c15, 5)
+#define PMEVTYPER30 __ACCESS_CP15(c14, 0, c15, 6)
+
+#define RETURN_READ_PMEVCNTRN(n) \
+ return read_sysreg(PMEVCNTR##n)
+static unsigned long read_pmevcntrn(int n)
+{
+ PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
+ return 0;
+}
+
+#define WRITE_PMEVCNTRN(n) \
+ write_sysreg(val, PMEVCNTR##n)
+static void write_pmevcntrn(int n, unsigned long val)
+{
+ PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
+}
+
+#define WRITE_PMEVTYPERN(n) \
+ write_sysreg(val, PMEVTYPER##n)
+static void write_pmevtypern(int n, unsigned long val)
+{
+ PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
+}
+
+static inline unsigned long read_pmmir(void)
+{
+ return read_sysreg(PMMIR);
+}
+
+static inline u32 read_pmuver(void)
+{
+ /* PMUVers is not a signed field */
+ u32 dfr0 = read_cpuid_ext(CPUID_EXT_DFR0);
+
+ return (dfr0 >> 24) & 0xf;
+}
+
+static inline void write_pmcr(u32 val)
+{
+ write_sysreg(val, PMCR);
+}
+
+static inline u32 read_pmcr(void)
+{
+ return read_sysreg(PMCR);
+}
+
+static inline void write_pmselr(u32 val)
+{
+ write_sysreg(val, PMSELR);
+}
+
+static inline void write_pmccntr(u64 val)
+{
+ write_sysreg(val, PMCCNTR);
+}
+
+static inline u64 read_pmccntr(void)
+{
+ return read_sysreg(PMCCNTR);
+}
+
+static inline void write_pmxevcntr(u32 val)
+{
+ write_sysreg(val, PMXEVCNTR);
+}
+
+static inline u32 read_pmxevcntr(void)
+{
+ return read_sysreg(PMXEVCNTR);
+}
+
+static inline void write_pmxevtyper(u32 val)
+{
+ write_sysreg(val, PMXEVTYPER);
+}
+
+static inline void write_pmcntenset(u32 val)
+{
+ write_sysreg(val, PMCNTENSET);
+}
+
+static inline void write_pmcntenclr(u32 val)
+{
+ write_sysreg(val, PMCNTENCLR);
+}
+
+static inline void write_pmintenset(u32 val)
+{
+ write_sysreg(val, PMINTENSET);
+}
+
+static inline void write_pmintenclr(u32 val)
+{
+ write_sysreg(val, PMINTENCLR);
+}
+
+static inline void write_pmccfiltr(u32 val)
+{
+ write_sysreg(val, PMCCFILTR);
+}
+
+static inline void write_pmovsclr(u32 val)
+{
+ write_sysreg(val, PMOVSR);
+}
+
+static inline u32 read_pmovsclr(void)
+{
+ return read_sysreg(PMOVSR);
+}
+
+static inline void write_pmuserenr(u32 val)
+{
+ write_sysreg(val, PMUSERENR);
+}
+
+static inline u32 read_pmceid0(void)
+{
+ return read_sysreg(PMCEID0);
+}
+
+static inline u32 read_pmceid1(void)
+{
+ return read_sysreg(PMCEID1);
+}
+
+static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
+static inline void kvm_clr_pmu_events(u32 clr) {}
+static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
+{
+ return false;
+}
+
+/* PMU Version in DFR Register */
+#define ARMV8_PMU_DFR_VER_NI 0
+#define ARMV8_PMU_DFR_VER_V3P4 0x5
+#define ARMV8_PMU_DFR_VER_V3P5 0x6
+#define ARMV8_PMU_DFR_VER_IMP_DEF 0xF
+
+static inline bool pmuv3_implemented(int pmuver)
+{
+ return !(pmuver == ARMV8_PMU_DFR_VER_IMP_DEF ||
+ pmuver == ARMV8_PMU_DFR_VER_NI);
+}
+
+static inline bool is_pmuv3p4(int pmuver)
+{
+ return pmuver >= ARMV8_PMU_DFR_VER_V3P4;
+}
+
+static inline bool is_pmuv3p5(int pmuver)
+{
+ return pmuver >= ARMV8_PMU_DFR_VER_V3P5;
+}
+
+#endif
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 34fe8d2dd5d1..505a306e0271 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -236,20 +236,12 @@ THUMB( fpreg .req r7 )
sub \tmp, \tmp, #1 @ decrement it
str \tmp, [\ti, #TI_PREEMPT]
.endm
-
- .macro dec_preempt_count_ti, ti, tmp
- get_thread_info \ti
- dec_preempt_count \ti, \tmp
- .endm
#else
.macro inc_preempt_count, ti, tmp
.endm
.macro dec_preempt_count, ti, tmp
.endm
-
- .macro dec_preempt_count_ti, ti, tmp
- .endm
#endif
#define USERL(l, x...) \
@@ -666,12 +658,11 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
__adldst_l str, \src, \sym, \tmp, \cond
.endm
- .macro __ldst_va, op, reg, tmp, sym, cond
+ .macro __ldst_va, op, reg, tmp, sym, cond, offset
#if __LINUX_ARM_ARCH__ >= 7 || \
!defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
mov_l \tmp, \sym, \cond
- \op\cond \reg, [\tmp]
#else
/*
* Avoid a literal load, by emitting a sequence of ADD/LDR instructions
@@ -683,24 +674,29 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
.reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
.reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
.reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
-.L0_\@: sub\cond \tmp, pc, #8
-.L1_\@: sub\cond \tmp, \tmp, #4
-.L2_\@: \op\cond \reg, [\tmp, #0]
+.L0_\@: sub\cond \tmp, pc, #8 - \offset
+.L1_\@: sub\cond \tmp, \tmp, #4 - \offset
+.L2_\@:
#endif
+ \op\cond \reg, [\tmp, #\offset]
.endm
/*
* ldr_va - load a 32-bit word from the virtual address of \sym
*/
- .macro ldr_va, rd:req, sym:req, cond
- __ldst_va ldr, \rd, \rd, \sym, \cond
+ .macro ldr_va, rd:req, sym:req, cond, tmp, offset=0
+ .ifnb \tmp
+ __ldst_va ldr, \rd, \tmp, \sym, \cond, \offset
+ .else
+ __ldst_va ldr, \rd, \rd, \sym, \cond, \offset
+ .endif
.endm
/*
* str_va - store a 32-bit word to the virtual address of \sym
*/
.macro str_va, rn:req, sym:req, tmp:req, cond
- __ldst_va str, \rn, \tmp, \sym, \cond
+ __ldst_va str, \rn, \tmp, \sym, \cond, 0
.endm
/*
@@ -727,9 +723,11 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
* are permitted to overlap with 'rd' if != sp
*/
.macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
-#if __LINUX_ARM_ARCH__ >= 7 || \
- !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
- (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
+#ifndef CONFIG_SMP
+ ldr_va \rd, \sym, tmp=\t1
+#elif __LINUX_ARM_ARCH__ >= 7 || \
+ !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
+ (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
this_cpu_offset \t1
mov_l \t2, \sym
ldr \rd, [\t1, \t2]
@@ -755,6 +753,12 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
.endif
.endm
+ .if __LINUX_ARM_ARCH__ < 6
+ .set .Lrev_l_uses_tmp, 1
+ .else
+ .set .Lrev_l_uses_tmp, 0
+ .endif
+
/*
* bl_r - branch and link to register
*
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 8e94fe7ab5eb..714440fa2fc6 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -160,18 +160,20 @@ extern int _test_and_change_bit(int nr, volatile unsigned long * p);
/*
* Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
*/
-extern int _find_first_zero_bit_le(const unsigned long *p, unsigned size);
-extern int _find_next_zero_bit_le(const unsigned long *p, int size, int offset);
-extern int _find_first_bit_le(const unsigned long *p, unsigned size);
-extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
+unsigned long _find_first_zero_bit_le(const unsigned long *p, unsigned long size);
+unsigned long _find_next_zero_bit_le(const unsigned long *p,
+ unsigned long size, unsigned long offset);
+unsigned long _find_first_bit_le(const unsigned long *p, unsigned long size);
+unsigned long _find_next_bit_le(const unsigned long *p, unsigned long size, unsigned long offset);
/*
* Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
*/
-extern int _find_first_zero_bit_be(const unsigned long *p, unsigned size);
-extern int _find_next_zero_bit_be(const unsigned long *p, int size, int offset);
-extern int _find_first_bit_be(const unsigned long *p, unsigned size);
-extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
+unsigned long _find_first_zero_bit_be(const unsigned long *p, unsigned long size);
+unsigned long _find_next_zero_bit_be(const unsigned long *p,
+ unsigned long size, unsigned long offset);
+unsigned long _find_first_bit_be(const unsigned long *p, unsigned long size);
+unsigned long _find_next_bit_be(const unsigned long *p, unsigned long size, unsigned long offset);
#ifndef CONFIG_SMP
/*
diff --git a/arch/arm/include/asm/checksum.h b/arch/arm/include/asm/checksum.h
index f0f54aef3724..d8a13959bff0 100644
--- a/arch/arm/include/asm/checksum.h
+++ b/arch/arm/include/asm/checksum.h
@@ -11,6 +11,7 @@
#define __ASM_ARM_CHECKSUM_H
#include <linux/in6.h>
+#include <linux/uaccess.h>
/*
* computes the checksum of a memory block at buff, length len,
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 4dfe538dfc68..44667bdb4707 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -25,7 +25,8 @@
#define swp_is_buggy
#endif
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+static inline unsigned long
+__arch_xchg(unsigned long x, volatile void *ptr, int size)
{
extern void __bad_xchg(volatile void *, int);
unsigned long ret;
@@ -115,8 +116,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
}
#define arch_xchg_relaxed(ptr, x) ({ \
- (__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), \
- sizeof(*(ptr))); \
+ (__typeof__(*(ptr)))__arch_xchg((unsigned long)(x), (ptr), \
+ sizeof(*(ptr))); \
})
#include <asm-generic/cmpxchg-local.h>
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 775cac3c02bb..0163c3e78a67 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -25,6 +25,8 @@
#define CPUID_EXT_ISAR3 0x6c
#define CPUID_EXT_ISAR4 0x70
#define CPUID_EXT_ISAR5 0x74
+#define CPUID_EXT_ISAR6 0x7c
+#define CPUID_EXT_PFR2 0x90
#else
#define CPUID_EXT_PFR0 "c1, 0"
#define CPUID_EXT_PFR1 "c1, 1"
@@ -40,6 +42,8 @@
#define CPUID_EXT_ISAR3 "c2, 3"
#define CPUID_EXT_ISAR4 "c2, 4"
#define CPUID_EXT_ISAR5 "c2, 5"
+#define CPUID_EXT_ISAR6 "c2, 7"
+#define CPUID_EXT_PFR2 "c3, 4"
#endif
#define MPIDR_SMP_BITMASK (0x3 << 30)
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index be666f58bf7a..c6beb1708c64 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -6,13 +6,9 @@
#define ASMARM_DEVICE_H
struct dev_archdata {
-#ifdef CONFIG_DMABOUNCE
- struct dmabounce_device_info *dmabounce;
-#endif
#ifdef CONFIG_ARM_DMA_USE_IOMMU
struct dma_iommu_mapping *mapping;
#endif
- unsigned int dma_coherent:1;
unsigned int dma_ops_setup:1;
};
diff --git a/arch/arm/include/asm/dma-direct.h b/arch/arm/include/asm/dma-direct.h
deleted file mode 100644
index 77fcb7ee5ec9..000000000000
--- a/arch/arm/include/asm/dma-direct.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef ASM_ARM_DMA_DIRECT_H
-#define ASM_ARM_DMA_DIRECT_H 1
-
-#include <asm/memory.h>
-
-/*
- * dma_to_pfn/pfn_to_dma/virt_to_dma are architecture private
- * functions used internally by the DMA-mapping API to provide DMA
- * addresses. They must not be used by drivers.
- */
-static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
-{
- if (dev && dev->dma_range_map)
- pfn = PFN_DOWN(translate_phys_to_dma(dev, PFN_PHYS(pfn)));
- return (dma_addr_t)__pfn_to_bus(pfn);
-}
-
-static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
-{
- unsigned long pfn = __bus_to_pfn(addr);
-
- if (dev && dev->dma_range_map)
- pfn = PFN_DOWN(translate_dma_to_phys(dev, PFN_PHYS(pfn)));
- return pfn;
-}
-
-static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
-{
- if (dev)
- return pfn_to_dma(dev, virt_to_pfn(addr));
-
- return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
-}
-
-static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
-{
- unsigned int offset = paddr & ~PAGE_MASK;
- return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset;
-}
-
-static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
-{
- unsigned int offset = dev_addr & ~PAGE_MASK;
- return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset;
-}
-
-#endif /* ASM_ARM_DMA_DIRECT_H */
diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
index fe9ef6f79e9c..82ec1ccf1fee 100644
--- a/arch/arm/include/asm/dma-iommu.h
+++ b/arch/arm/include/asm/dma-iommu.h
@@ -24,7 +24,7 @@ struct dma_iommu_mapping {
};
struct dma_iommu_mapping *
-arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size);
+arm_iommu_create_mapping(const struct bus_type *bus, dma_addr_t base, u64 size);
void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
deleted file mode 100644
index 77082246a5e1..000000000000
--- a/arch/arm/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef ASMARM_DMA_MAPPING_H
-#define ASMARM_DMA_MAPPING_H
-
-#ifdef __KERNEL__
-
-#include <linux/mm_types.h>
-#include <linux/scatterlist.h>
-
-#include <xen/xen.h>
-#include <asm/xen/hypervisor.h>
-
-extern const struct dma_map_ops arm_dma_ops;
-extern const struct dma_map_ops arm_coherent_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- if (IS_ENABLED(CONFIG_MMU) && !IS_ENABLED(CONFIG_ARM_LPAE))
- return &arm_dma_ops;
- return NULL;
-}
-
-/**
- * arm_dma_alloc - allocate consistent memory for DMA
- * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
- * @size: required memory size
- * @handle: bus-specific DMA address
- * @attrs: optinal attributes that specific mapping properties
- *
- * Allocate some memory for a device for performing DMA. This function
- * allocates pages, and will return the CPU-viewed address, and sets @handle
- * to be the device-viewed address.
- */
-extern void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
- gfp_t gfp, unsigned long attrs);
-
-/**
- * arm_dma_free - free memory allocated by arm_dma_alloc
- * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
- * @size: size of memory originally requested in dma_alloc_coherent
- * @cpu_addr: CPU-view address returned from dma_alloc_coherent
- * @handle: device-view address returned from dma_alloc_coherent
- * @attrs: optinal attributes that specific mapping properties
- *
- * Free (and unmap) a DMA buffer previously allocated by
- * arm_dma_alloc().
- *
- * References to memory and mappings associated with cpu_addr/handle
- * during and after this call executing are illegal.
- */
-extern void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
- dma_addr_t handle, unsigned long attrs);
-
-/**
- * arm_dma_mmap - map a coherent DMA allocation into user space
- * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
- * @vma: vm_area_struct describing requested user mapping
- * @cpu_addr: kernel CPU-view address returned from dma_alloc_coherent
- * @handle: device-view address returned from dma_alloc_coherent
- * @size: size of memory originally requested in dma_alloc_coherent
- * @attrs: optinal attributes that specific mapping properties
- *
- * Map a coherent DMA buffer previously allocated by dma_alloc_coherent
- * into user space. The coherent DMA buffer must not be freed by the
- * driver until the user space mapping has been released.
- */
-extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
- void *cpu_addr, dma_addr_t dma_addr, size_t size,
- unsigned long attrs);
-
-/*
- * For SA-1111, IXP425, and ADI systems the dma-mapping functions are "magic"
- * and utilize bounce buffers as needed to work around limited DMA windows.
- *
- * On the SA-1111, a bug limits DMA to only certain regions of RAM.
- * On the IXP425, the PCI inbound window is 64MB (256MB total RAM)
- * On some ADI engineering systems, PCI inbound window is 32MB (12MB total RAM)
- *
- * The following are helper functions used by the dmabounce subystem
- *
- */
-
-/**
- * dmabounce_register_dev
- *
- * @dev: valid struct device pointer
- * @small_buf_size: size of buffers to use with small buffer pool
- * @large_buf_size: size of buffers to use with large buffer pool (can be 0)
- * @needs_bounce_fn: called to determine whether buffer needs bouncing
- *
- * This function should be called by low-level platform code to register
- * a device as requireing DMA buffer bouncing. The function will allocate
- * appropriate DMA pools for the device.
- */
-extern int dmabounce_register_dev(struct device *, unsigned long,
- unsigned long, int (*)(struct device *, dma_addr_t, size_t));
-
-/**
- * dmabounce_unregister_dev
- *
- * @dev: valid struct device pointer
- *
- * This function should be called by low-level platform code when device
- * that was previously registered with dmabounce_register_dev is removed
- * from the system.
- *
- */
-extern void dmabounce_unregister_dev(struct device *);
-
-
-
-/*
- * The scatter list versions of the above methods.
- */
-extern int arm_dma_map_sg(struct device *, struct scatterlist *, int,
- enum dma_data_direction, unsigned long attrs);
-extern void arm_dma_unmap_sg(struct device *, struct scatterlist *, int,
- enum dma_data_direction, unsigned long attrs);
-extern void arm_dma_sync_sg_for_cpu(struct device *, struct scatterlist *, int,
- enum dma_data_direction);
-extern void arm_dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
- enum dma_data_direction);
-extern int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
- void *cpu_addr, dma_addr_t dma_addr, size_t size,
- unsigned long attrs);
-
-#endif /* __KERNEL__ */
-#endif
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index a81dda65c576..c6aded1b069c 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -10,7 +10,7 @@
#else
#define MAX_DMA_ADDRESS ({ \
extern phys_addr_t arm_dma_zone_size; \
- arm_dma_zone_size && arm_dma_zone_size < (0x10000000 - PAGE_OFFSET) ? \
+ arm_dma_zone_size && arm_dma_zone_size < (0x100000000ULL - PAGE_OFFSET) ? \
(PAGE_OFFSET + arm_dma_zone_size) : 0xffffffffUL; })
#endif
@@ -106,7 +106,7 @@ extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
*/
extern void __set_dma_addr(unsigned int chan, void *addr);
#define set_dma_addr(chan, addr) \
- __set_dma_addr(chan, (void *)__bus_to_virt(addr))
+ __set_dma_addr(chan, (void *)isa_bus_to_virt(addr))
/* Set the DMA byte count for this channel
*
@@ -143,10 +143,4 @@ extern int get_dma_residue(unsigned int chan);
#endif /* CONFIG_ISA_DMA_API */
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
#endif /* __ASM_ARM_DMA_H */
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index f1d0a7807cd0..41536feb4392 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -112,19 +112,6 @@ static __always_inline void set_domain(unsigned int val)
}
#endif
-#ifdef CONFIG_CPU_USE_DOMAINS
-#define modify_domain(dom,type) \
- do { \
- unsigned int domain = get_domain(); \
- domain &= ~domain_mask(dom); \
- domain = domain | domain_val(dom, type); \
- set_domain(domain); \
- } while (0)
-
-#else
-static inline void modify_domain(unsigned dom, unsigned type) { }
-#endif
-
/*
* Generate the T (user) versions of the LDR/STR and related
* instructions (inline assembly)
diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h
index 27218eabbf9a..78282ced5038 100644
--- a/arch/arm/include/asm/efi.h
+++ b/arch/arm/include/asm/efi.h
@@ -17,20 +17,14 @@
#ifdef CONFIG_EFI
void efi_init(void);
+void arm_efi_init(void);
int efi_create_mapping(struct mm_struct *mm, efi_memory_desc_t *md);
-int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md);
+int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md, bool);
#define arch_efi_call_virt_setup() efi_virtmap_load()
#define arch_efi_call_virt_teardown() efi_virtmap_unload()
-#define arch_efi_call_virt(p, f, args...) \
-({ \
- efi_##f##_t *__f; \
- __f = p->f; \
- __f(args); \
-})
-
#define ARCH_EFI_IRQ_FLAGS_MASK \
(PSR_J_BIT | PSR_E_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | \
PSR_T_BIT | MODE_MASK)
@@ -44,14 +38,11 @@ void efi_virtmap_load(void);
void efi_virtmap_unload(void);
#else
-#define efi_init()
+#define arm_efi_init()
#endif /* CONFIG_EFI */
/* arch specific definitions used by the stub code */
-struct screen_info *alloc_screen_info(void);
-void free_screen_info(struct screen_info *si);
-
/*
* A reasonable upper bound for the uncompressed kernel size is 32 MBytes,
* so we will reserve that amount of memory. We have no easy way to tell what
diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h
index ca42fd9ae0b3..e29d9c7a5238 100644
--- a/arch/arm/include/asm/fpstate.h
+++ b/arch/arm/include/asm/fpstate.h
@@ -46,9 +46,6 @@ union vfp_state {
struct vfp_hard_struct hard;
};
-extern void vfp_flush_thread(union vfp_state *);
-extern void vfp_release_thread(union vfp_state *);
-
#define FP_HARD_SIZE 35
struct fp_hard_struct {
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
deleted file mode 100644
index f3bb8a2bf788..000000000000
--- a/arch/arm/include/asm/gpio.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ARCH_ARM_GPIO_H
-#define _ARCH_ARM_GPIO_H
-
-/* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */
-#include <asm-generic/gpio.h>
-
-/* The trivial gpiolib dispatchers */
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-#define gpio_cansleep __gpio_cansleep
-
-/*
- * Provide a default gpio_to_irq() which should satisfy every case.
- * However, some platforms want to do this differently, so allow them
- * to override it.
- */
-#ifndef gpio_to_irq
-#define gpio_to_irq __gpio_to_irq
-#endif
-
-#endif /* _ARCH_ARM_GPIO_H */
diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
index 39769ffa0051..9694808ee97c 100644
--- a/arch/arm/include/asm/hardware/cache-aurora-l2.h
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AURORA shared L2 cache controller support
*
@@ -5,10 +6,6 @@
*
* Yehuda Yitschak <yehuday@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
index 12e1588dc4f1..eb2e7b7f70a8 100644
--- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h
+++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
@@ -1,13 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/cache-feroceon-l2.h
*
* Copyright (C) 2008 Marvell Semiconductor
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
extern void __init feroceon_l2_init(int l2_wt_override);
extern int __init feroceon_of_init(void);
-
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
index 295e2e40151b..4e493facaa31 100644
--- a/arch/arm/include/asm/hardware/cache-tauros2.h
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/cache-tauros2.h
*
* Copyright (C) 2008 Marvell Semiconductor
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#define CACHE_TAUROS2_PREFETCH_ON (1 << 0)
diff --git a/arch/arm/include/asm/hardware/dec21285.h b/arch/arm/include/asm/hardware/dec21285.h
index 3f18a56a025d..894f2a635cbb 100644
--- a/arch/arm/include/asm/hardware/dec21285.h
+++ b/arch/arm/include/asm/hardware/dec21285.h
@@ -22,6 +22,13 @@
#define DC21285_IO(x) (x)
#endif
+/*
+ * The footbridge is programmed to expose the system RAM at 0xe0000000.
+ * The requirement is that the RAM isn't placed at bus address 0, which
+ * would clash with VGA cards.
+ */
+#define BUS_OFFSET 0xe0000000
+
#define CSR_PCICMD DC21285_IO(0x0004)
#define CSR_CLASSREV DC21285_IO(0x0008)
#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
@@ -81,19 +88,6 @@
#define SA110_CNTL_XCSDIR(x) ((x)<<28)
#define SA110_CNTL_PCICFN (1 << 31)
-/*
- * footbridge_cfn_mode() is used when we want
- * to check whether we are the central function
- */
-#define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
-#if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
-#define footbridge_cfn_mode() __footbridge_cfn_mode()
-#elif defined(CONFIG_FOOTBRIDGE_HOST)
-#define footbridge_cfn_mode() (1)
-#else
-#define footbridge_cfn_mode() (0)
-#endif
-
#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h
index 2e70db6f22ea..d8c6f8a99dfa 100644
--- a/arch/arm/include/asm/hardware/sa1111.h
+++ b/arch/arm/include/asm/hardware/sa1111.h
@@ -13,8 +13,6 @@
#ifndef _ASM_ARCH_SA1111
#define _ASM_ARCH_SA1111
-#include <mach/bitfield.h>
-
/*
* Don't ask the (SAC) DMA engines to move less than this amount.
*/
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 0c70eb688a00..7fcdc785366c 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -139,11 +139,9 @@ extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
void __arm_iomem_set_ro(void __iomem *ptr, size_t size);
-extern void __iounmap(volatile void __iomem *addr);
extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
unsigned int, void *);
-extern void (*arch_iounmap)(volatile void __iomem *);
/*
* Bad read/write accesses...
@@ -174,7 +172,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
#define PCI_IO_VIRT_BASE 0xfee00000
#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) || IS_ENABLED(CONFIG_PCMCIA)
void pci_ioremap_set_mem_type(int mem_type);
#else
static inline void pci_ioremap_set_mem_type(int mem_type) {}
@@ -200,32 +198,13 @@ void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
*/
#ifdef CONFIG_NEED_MACH_IO_H
#include <mach/io.h>
-#elif defined(CONFIG_PCI)
-#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
-#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
#else
-#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
-#endif
-
-/*
- * This is the limit of PC card/PCI/ISA IO space, which is by default
- * 64K if we have PC card, PCI or ISA support. Otherwise, default to
- * zero to prevent ISA/PCI drivers claiming IO space (and potentially
- * oopsing.)
- *
- * Only set this larger if you really need inb() et.al. to operate over
- * a larger address space. Note that SOC_COMMON ioremaps each sockets
- * IO space area, and so inb() et.al. must be defined to operate as per
- * readb() et.al. on such platforms.
- */
-#ifndef IO_SPACE_LIMIT
-#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
-#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
-#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
-#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
+#if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
+#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
#else
#define IO_SPACE_LIMIT ((resource_size_t)0)
#endif
+#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
#endif
/*
@@ -399,7 +378,7 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
#define ioremap_wc ioremap_wc
#define ioremap_wt ioremap_wc
-void iounmap(volatile void __iomem *iomem_cookie);
+void iounmap(volatile void __iomem *io_addr);
#define iounmap iounmap
void *arch_memremap_wb(phys_addr_t phys_addr, size_t size);
@@ -440,6 +419,9 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
+ unsigned long flags);
+#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
#endif
/*
diff --git a/arch/arm/include/asm/irq_work.h b/arch/arm/include/asm/irq_work.h
index 8895999834cc..3149e4dc1b54 100644
--- a/arch/arm/include/asm/irq_work.h
+++ b/arch/arm/include/asm/irq_work.h
@@ -9,4 +9,6 @@ static inline bool arch_irq_work_has_interrupt(void)
return is_smp();
}
+extern void arch_irq_work_raise(void);
+
#endif /* _ASM_ARM_IRQ_WORK_H */
diff --git a/arch/arm/include/asm/mach/dma.h b/arch/arm/include/asm/mach/dma.h
index 1506422af383..5ec11d7f0d04 100644
--- a/arch/arm/include/asm/mach/dma.h
+++ b/arch/arm/include/asm/mach/dma.h
@@ -44,8 +44,3 @@ struct dma_struct {
* isa_dma_add - add an ISA-style DMA channel
*/
extern int isa_dma_add(unsigned int, dma_t *dma);
-
-/*
- * Add the ISA DMA controller. Always takes channels 0-7.
- */
-extern void isa_init_dma(void);
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 92282558caf7..2b8970d8e5a2 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -27,6 +27,7 @@ enum {
MT_HIGH_VECTORS,
MT_MEMORY_RWX,
MT_MEMORY_RW,
+ MT_MEMORY_RO,
MT_ROM,
MT_MEMORY_RWX_NONCACHED,
MT_MEMORY_RW_DTCM,
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index f673e13e0f94..62e9df024445 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -370,19 +370,6 @@ static inline unsigned long __virt_to_idmap(unsigned long x)
#define virt_to_idmap(x) __virt_to_idmap((unsigned long)(x))
/*
- * Virtual <-> DMA view memory address translations
- * Again, these are *only* valid on the kernel direct mapped RAM
- * memory. Use of these is *deprecated* (and that doesn't mean
- * use the __ prefixed forms instead.) See dma-mapping.h.
- */
-#ifndef __virt_to_bus
-#define __virt_to_bus __virt_to_phys
-#define __bus_to_virt __phys_to_virt
-#define __pfn_to_bus(x) __pfn_to_phys(x)
-#define __bus_to_pfn(x) __phys_to_pfn(x)
-#endif
-
-/*
* Conversion between a struct page and a physical address.
*
* page_to_pfn(page) convert a struct page * to a PFN number
@@ -399,6 +386,4 @@ static inline unsigned long __virt_to_idmap(unsigned long x)
#endif
-#include <asm-generic/memory_model.h>
-
#endif
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index cfffae67c04e..07c51a34f77d 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -3,20 +3,10 @@
#define _ASM_ARM_MODULE_H
#include <asm-generic/module.h>
-
-struct unwind_table;
+#include <asm/unwind.h>
#ifdef CONFIG_ARM_UNWIND
-enum {
- ARM_SEC_INIT,
- ARM_SEC_DEVINIT,
- ARM_SEC_CORE,
- ARM_SEC_EXIT,
- ARM_SEC_DEVEXIT,
- ARM_SEC_HOT,
- ARM_SEC_UNLIKELY,
- ARM_SEC_MAX,
-};
+#define ELF_SECTION_UNWIND 0x70000001
#endif
#define PLT_ENT_STRIDE L1_CACHE_BYTES
@@ -36,7 +26,8 @@ struct mod_plt_sec {
struct mod_arch_specific {
#ifdef CONFIG_ARM_UNWIND
- struct unwind_table *unwind[ARM_SEC_MAX];
+ struct list_head unwind_list;
+ struct unwind_table *init_table;
#endif
#ifdef CONFIG_ARM_MODULE_PLTS
struct mod_plt_sec core;
@@ -46,6 +37,11 @@ struct mod_arch_specific {
struct module;
u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val);
+#ifdef CONFIG_ARM_MODULE_PLTS
+bool in_module_plt(unsigned long loc);
+#else
+static inline bool in_module_plt(unsigned long loc) { return false; }
+#endif
#ifdef CONFIG_THUMB2_KERNEL
#define HAVE_ARCH_KALLSYMS_SYMBOL_VALUE
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 5fcc8a600e36..74bb5947b387 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -158,6 +158,7 @@ typedef struct page *pgtable_t;
#ifdef CONFIG_HAVE_ARCH_PFN_VALID
extern int pfn_valid(unsigned long);
+#define pfn_valid pfn_valid
#endif
#include <asm/memory.h>
@@ -167,5 +168,6 @@ extern int pfn_valid(unsigned long);
#define VM_DATA_DEFAULT_FLAGS VM_DATA_FLAGS_TSK_EXEC
#include <asm-generic/getorder.h>
+#include <asm-generic/memory_model.h>
#endif
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 68e6f25784a4..5916b88d4c94 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -22,11 +22,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
#define HAVE_PCI_MMAP
#define ARCH_GENERIC_PCI_MMAP_RESOURCE
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
- return channel ? 15 : 14;
-}
-
extern void pcibios_report_status(unsigned int status_mask, int warn);
#endif /* __KERNEL__ */
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index fe87397c3d8c..bdbc1e590891 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -17,7 +17,7 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_arch_fetch_caller_regs(regs, __ip) { \
(regs)->ARM_pc = (__ip); \
- (regs)->ARM_fp = (unsigned long) __builtin_frame_address(0); \
+ frame_pointer((regs)) = (unsigned long) __builtin_frame_address(0); \
(regs)->ARM_sp = current_stack_pointer; \
(regs)->ARM_cpsr = SVC_MODE; \
}
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 92abd4cd8ca2..ce543cd9380c 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -126,6 +126,9 @@
#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */
#define L_PTE_NONE (_AT(pteval_t, 1) << 11)
+/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
+#define L_PTE_SWP_EXCLUSIVE L_PTE_RDONLY
+
/*
* These are the memory types, defined to be compatible with
* pre-ARMv6 CPUs cacheable and bufferable bits: n/a,n/a,C,B
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index eabe72ff7381..106049791500 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -76,6 +76,9 @@
#define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
#define L_PTE_RDONLY (_AT(pteval_t, 1) << 58) /* READ ONLY */
+/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
+#define L_PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 7)
+
#define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
#define L_PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
#define L_PMD_SECT_NONE (_AT(pmdval_t, 1) << 57)
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index d16aba48fa0a..61480d096054 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -21,8 +21,6 @@
#define pgd_none(pgd) (0)
#define pgd_bad(pgd) (0)
#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-/* FIXME */
/*
* PMD_SHIFT determines the size of the area a second-level page table can map
* PGDIR_SHIFT determines what a third-level page table entry can map
@@ -45,12 +43,6 @@
typedef pte_t *pte_addr_t;
/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr) (virt_to_page(0))
-
-/*
* Mark the prot value as uncacheable and unbufferable.
*/
#define pgprot_noncached(prot) (prot)
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index cd1f84bb40ae..a58ccbb406ad 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -10,6 +10,15 @@
#include <linux/const.h>
#include <asm/proc-fns.h>
+#ifndef __ASSEMBLY__
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern struct page *empty_zero_page;
+#define ZERO_PAGE(vaddr) (empty_zero_page)
+#endif
+
#ifndef CONFIG_MMU
#include <asm-generic/pgtable-nopud.h>
@@ -137,32 +146,8 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
* 2) If we could do execute protection, then read is implied
* 3) write implies read permissions
*/
-#define __P000 __PAGE_NONE
-#define __P001 __PAGE_READONLY
-#define __P010 __PAGE_COPY
-#define __P011 __PAGE_COPY
-#define __P100 __PAGE_READONLY_EXEC
-#define __P101 __PAGE_READONLY_EXEC
-#define __P110 __PAGE_COPY_EXEC
-#define __P111 __PAGE_COPY_EXEC
-
-#define __S000 __PAGE_NONE
-#define __S001 __PAGE_READONLY
-#define __S010 __PAGE_SHARED
-#define __S011 __PAGE_SHARED
-#define __S100 __PAGE_READONLY_EXEC
-#define __S101 __PAGE_READONLY_EXEC
-#define __S110 __PAGE_SHARED_EXEC
-#define __S111 __PAGE_SHARED_EXEC
#ifndef __ASSEMBLY__
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern struct page *empty_zero_page;
-#define ZERO_PAGE(vaddr) (empty_zero_page)
-
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
@@ -286,27 +271,47 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
}
/*
- * Encode and decode a swap entry. Swap entries are stored in the Linux
- * page tables as follows:
+ * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
+ * are !pte_none() && !pte_present().
+ *
+ * Format of swap PTEs:
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * <--------------- offset ------------------------> < type -> 0 0
+ * <------------------- offset ------------------> E < type -> 0 0
+ *
+ * E is the exclusive marker that is not stored in swap entries.
*
- * This gives us up to 31 swap files and 128GB per swap file. Note that
+ * This gives us up to 31 swap files and 64GB per swap file. Note that
* the offset field is always non-zero.
*/
#define __SWP_TYPE_SHIFT 2
#define __SWP_TYPE_BITS 5
#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
-#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
+#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
-#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
+#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
+ ((offset) << __SWP_OFFSET_SHIFT) })
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(swp) __pte((swp).val | PTE_TYPE_FAULT)
+#define __swp_entry_to_pte(swp) __pte((swp).val)
+
+static inline int pte_swp_exclusive(pte_t pte)
+{
+ return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
+}
+
+static inline pte_t pte_swp_mkexclusive(pte_t pte)
+{
+ return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
+}
+
+static inline pte_t pte_swp_clear_exclusive(pte_t pte)
+{
+ return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
+}
/*
* It is an error for the kernel to have more swap files than we can
@@ -315,10 +320,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
*/
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-/* FIXME: this is not correct */
-#define kern_addr_valid(addr) (1)
-
/*
* We provide our own arch_get_unmapped_area to cope with VIPT caches.
*/
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index bdc35c0e8dfb..326864f79d18 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -81,9 +81,6 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
/* Forward declaration, a strange C thing */
struct task_struct;
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
unsigned long __get_wchan(struct task_struct *p);
#define task_pt_regs(p) \
diff --git a/arch/arm/include/asm/ptdump.h b/arch/arm/include/asm/ptdump.h
index 0c2d3d0d4cc6..aad1d034136c 100644
--- a/arch/arm/include/asm/ptdump.h
+++ b/arch/arm/include/asm/ptdump.h
@@ -21,6 +21,7 @@ struct ptdump_info {
void ptdump_walk_pgd(struct seq_file *s, struct ptdump_info *info);
#ifdef CONFIG_ARM_PTDUMP_DEBUGFS
+#define EFI_RUNTIME_MAP_END SZ_1G
void ptdump_debugfs_register(struct ptdump_info *info, const char *name);
#else
static inline void ptdump_debugfs_register(struct ptdump_info *info,
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 93051e2f402c..483b8ddfcb82 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -163,5 +163,35 @@ static inline unsigned long user_stack_pointer(struct pt_regs *regs)
((current_stack_pointer | (THREAD_SIZE - 1)) - 7) - 1; \
})
+static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
+{
+ regs->ARM_r0 = rc;
+}
+
+/*
+ * Update ITSTATE after normal execution of an IT block instruction.
+ *
+ * The 8 IT state bits are split into two parts in CPSR:
+ * ITSTATE<1:0> are in CPSR<26:25>
+ * ITSTATE<7:2> are in CPSR<15:10>
+ */
+static inline unsigned long it_advance(unsigned long cpsr)
+{
+ if ((cpsr & 0x06000400) == 0) {
+ /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */
+ cpsr &= ~PSR_IT_MASK;
+ } else {
+ /* We need to shift left ITSTATE<4:0> */
+ const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */
+ unsigned long it = cpsr & mask;
+ it <<= 1;
+ it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */
+ it &= mask;
+ cpsr &= ~mask;
+ cpsr |= it;
+ }
+ return cpsr;
+}
+
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/semihost.h b/arch/arm/include/asm/semihost.h
new file mode 100644
index 000000000000..f365787e7c23
--- /dev/null
+++ b/arch/arm/include/asm/semihost.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Adapted for ARM and earlycon:
+ * Copyright (C) 2014 Linaro Ltd.
+ * Author: Rob Herring <robh@kernel.org>
+ */
+
+#ifndef _ARM_SEMIHOST_H_
+#define _ARM_SEMIHOST_H_
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define SEMIHOST_SWI "0xab"
+#else
+#define SEMIHOST_SWI "0x123456"
+#endif
+
+struct uart_port;
+
+static inline void smh_putc(struct uart_port *port, unsigned char c)
+{
+ asm volatile("mov r1, %0\n"
+ "mov r0, #3\n"
+ "svc " SEMIHOST_SWI "\n"
+ : : "r" (&c) : "r0", "r1", "memory");
+}
+
+#endif /* _ARM_SEMIHOST_H_ */
diff --git a/arch/arm/include/asm/simd.h b/arch/arm/include/asm/simd.h
new file mode 100644
index 000000000000..82191dbd7e78
--- /dev/null
+++ b/arch/arm/include/asm/simd.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <linux/hardirq.h>
+
+static __must_check inline bool may_use_simd(void)
+{
+ return IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && !in_hardirq();
+}
diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
index 088d03161be5..0bd4979759f1 100644
--- a/arch/arm/include/asm/stackprotector.h
+++ b/arch/arm/include/asm/stackprotector.h
@@ -15,9 +15,6 @@
#ifndef _ASM_STACKPROTECTOR_H
#define _ASM_STACKPROTECTOR_H 1
-#include <linux/random.h>
-#include <linux/version.h>
-
#include <asm/thread_info.h>
extern unsigned long __stack_chk_guard;
@@ -30,11 +27,7 @@ extern unsigned long __stack_chk_guard;
*/
static __always_inline void boot_init_stack_canary(void)
{
- unsigned long canary;
-
- /* Try to get a semi random initial value. */
- get_random_bytes(&canary, sizeof(canary));
- canary ^= LINUX_VERSION_CODE;
+ unsigned long canary = get_random_canary();
current->stack_canary = canary;
#ifndef CONFIG_STACKPROTECTOR_PER_TASK
diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h
index 3e78f921b8b2..360f0d2406bf 100644
--- a/arch/arm/include/asm/stacktrace.h
+++ b/arch/arm/include/asm/stacktrace.h
@@ -21,6 +21,9 @@ struct stackframe {
struct llist_node *kr_cur;
struct task_struct *tsk;
#endif
+#ifdef CONFIG_UNWINDER_FRAME_POINTER
+ bool ex_frame;
+#endif
};
static __always_inline
@@ -34,12 +37,17 @@ void arm_get_current_stackframe(struct pt_regs *regs, struct stackframe *frame)
frame->kr_cur = NULL;
frame->tsk = current;
#endif
+#ifdef CONFIG_UNWINDER_FRAME_POINTER
+ frame->ex_frame = in_entry_text(frame->pc);
+#endif
}
extern int unwind_frame(struct stackframe *frame);
extern void walk_stackframe(struct stackframe *frame,
- int (*fn)(struct stackframe *, void *), void *data);
+ bool (*fn)(void *, unsigned long), void *data);
extern void dump_mem(const char *lvl, const char *str, unsigned long bottom,
unsigned long top);
+extern void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
+ const char *loglvl);
#endif /* __ASM_STACKTRACE_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index aecc403b2880..943ffcf069d2 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -40,6 +40,7 @@ struct task_struct;
DECLARE_PER_CPU(struct task_struct *, __entry_task);
#include <asm/types.h>
+#include <asm/traps.h>
struct cpu_context_save {
__u32 r4;
@@ -66,7 +67,6 @@ struct thread_info {
__u32 cpu_domain; /* cpu domain */
struct cpu_context_save cpu_context; /* cpu context */
__u32 abi_syscall; /* ABI type and syscall nr */
- __u8 used_cp[16]; /* thread used copro */
unsigned long tp_value[2]; /* TLS registers */
union fp_state fpstate __attribute__((aligned(8)));
union vfp_state vfpstate;
@@ -105,6 +105,21 @@ extern void iwmmxt_task_restore(struct thread_info *, void *);
extern void iwmmxt_task_release(struct thread_info *);
extern void iwmmxt_task_switch(struct thread_info *);
+extern int iwmmxt_undef_handler(struct pt_regs *, u32);
+
+static inline void register_iwmmxt_undef_handler(void)
+{
+ static struct undef_hook iwmmxt_undef_hook = {
+ .instr_mask = 0x0c000e00,
+ .instr_val = 0x0c000000,
+ .cpsr_mask = MODE_MASK | PSR_T_BIT,
+ .cpsr_val = USR_MODE,
+ .fn = iwmmxt_undef_handler,
+ };
+
+ register_undef_hook(&iwmmxt_undef_hook);
+}
+
extern void vfp_sync_hwstate(struct thread_info *);
extern void vfp_flush_hwstate(struct thread_info *);
@@ -128,15 +143,16 @@ extern int vfp_restore_user_hwstate(struct user_vfp *,
#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */
#define TIF_UPROBE 3 /* breakpointed or singlestepping */
-#define TIF_SYSCALL_TRACE 4 /* syscall trace active */
-#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
-#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */
-#define TIF_SECCOMP 7 /* seccomp syscall filtering active */
-#define TIF_NOTIFY_SIGNAL 8 /* signal notifications exist */
+#define TIF_NOTIFY_SIGNAL 4 /* signal notifications exist */
#define TIF_USING_IWMMXT 17
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
-#define TIF_RESTORE_SIGMASK 20
+#define TIF_RESTORE_SIGMASK 19
+#define TIF_SYSCALL_TRACE 20 /* syscall trace active */
+#define TIF_SYSCALL_AUDIT 21 /* syscall auditing active */
+#define TIF_SYSCALL_TRACEPOINT 22 /* syscall tracepoint instrumentation */
+#define TIF_SECCOMP 23 /* seccomp syscall filtering active */
+
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index 7c3b3671d6c2..6d1337c169cd 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -11,5 +11,6 @@
typedef unsigned long cycles_t;
#define get_cycles() ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
+#define random_get_entropy() (((unsigned long)get_cycles()) ?: random_get_entropy_fallback())
#endif
diff --git a/arch/arm/include/asm/unwind.h b/arch/arm/include/asm/unwind.h
index 0f8a3439902d..b51f85417f58 100644
--- a/arch/arm/include/asm/unwind.h
+++ b/arch/arm/include/asm/unwind.h
@@ -24,6 +24,7 @@ struct unwind_idx {
struct unwind_table {
struct list_head list;
+ struct list_head mod_list;
const struct unwind_idx *start;
const struct unwind_idx *origin;
const struct unwind_idx *stop;
diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h
index 19928bfb4f9c..157ea3426158 100644
--- a/arch/arm/include/asm/vfp.h
+++ b/arch/arm/include/asm/vfp.h
@@ -87,6 +87,12 @@
#define MVFR0_DP_BIT (8)
#define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT)
+/* MVFR1 bits */
+#define MVFR1_ASIMDHP_BIT (20)
+#define MVFR1_ASIMDHP_MASK (0xf << MVFR1_ASIMDHP_BIT)
+#define MVFR1_FPHP_BIT (24)
+#define MVFR1_FPHP_MASK (0xf << MVFR1_FPHP_BIT)
+
/* Bit patterns for decoding the packaged operation descriptors */
#define VFPOPDESC_LENGTH_BIT (9)
#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
diff --git a/arch/arm/include/asm/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h
index fad45c884e98..4c8632d5c432 100644
--- a/arch/arm/include/asm/vmlinux.lds.h
+++ b/arch/arm/include/asm/vmlinux.lds.h
@@ -96,7 +96,6 @@
SOFTIRQENTRY_TEXT \
TEXT_TEXT \
SCHED_TEXT \
- CPUIDLE_TEXT \
LOCK_TEXT \
KPROBES_TEXT \
ARM_STUBS_TEXT \
diff --git a/arch/arm/include/asm/xen/page-coherent.h b/arch/arm/include/asm/xen/xen-ops.h
index 27e984977402..7ebb7eb0bd93 100644
--- a/arch/arm/include/asm/xen/page-coherent.h
+++ b/arch/arm/include/asm/xen/xen-ops.h
@@ -1,2 +1,2 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#include <xen/arm/page-coherent.h>
+#include <xen/arm/xen-ops.h>
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h
index 669cad5194d3..934b549905f5 100644
--- a/arch/arm/include/asm/xor.h
+++ b/arch/arm/include/asm/xor.h
@@ -51,7 +51,7 @@ xor_arm4regs_2(unsigned long bytes, unsigned long * __restrict p1,
register unsigned int a1 __asm__("r4");
register unsigned int a2 __asm__("r5");
register unsigned int a3 __asm__("r6");
- register unsigned int a4 __asm__("r7");
+ register unsigned int a4 __asm__("r10");
register unsigned int b1 __asm__("r8");
register unsigned int b2 __asm__("r9");
register unsigned int b3 __asm__("ip");
@@ -73,7 +73,7 @@ xor_arm4regs_3(unsigned long bytes, unsigned long * __restrict p1,
register unsigned int a1 __asm__("r4");
register unsigned int a2 __asm__("r5");
register unsigned int a3 __asm__("r6");
- register unsigned int a4 __asm__("r7");
+ register unsigned int a4 __asm__("r10");
register unsigned int b1 __asm__("r8");
register unsigned int b2 __asm__("r9");
register unsigned int b3 __asm__("ip");
diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S
index f684e3a815f6..f6175e6e28cd 100644
--- a/arch/arm/include/debug/brcmstb.S
+++ b/arch/arm/include/debug/brcmstb.S
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2016 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2016 Broadcom */
#include <linux/serial_reg.h>
#include <asm/cputype.h>
diff --git a/arch/arm/include/debug/s3c24xx.S b/arch/arm/include/debug/s3c24xx.S
index af873b526677..7ab5e577cd42 100644
--- a/arch/arm/include/debug/s3c24xx.S
+++ b/arch/arm/include/debug/s3c24xx.S
@@ -28,16 +28,6 @@
and \rd, \rd, #S3C2410_UFSTAT_TXMASK
.endm
-/* Select the correct implementation depending on the configuration. The
- * S3C2440 will get selected by default, as these are the most widely
- * used variants of these
-*/
-
-#if defined(CONFIG_DEBUG_S3C2410_UART)
-#define fifo_full fifo_full_s3c2410
-#define fifo_level fifo_level_s3c2410
-#endif
-
/* include the reset of the code which will do the work */
#include <debug/samsung.S>
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 990199d8b7c6..6b2023e39b6f 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -28,6 +28,12 @@
#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
#define HWCAP_LPAE (1 << 20)
#define HWCAP_EVTSTRM (1 << 21)
+#define HWCAP_FPHP (1 << 22)
+#define HWCAP_ASIMDHP (1 << 23)
+#define HWCAP_ASIMDDP (1 << 24)
+#define HWCAP_ASIMDFHM (1 << 25)
+#define HWCAP_ASIMDBF16 (1 << 26)
+#define HWCAP_I8MM (1 << 27)
/*
* HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
@@ -37,5 +43,7 @@
#define HWCAP2_SHA1 (1 << 2)
#define HWCAP2_SHA2 (1 << 3)
#define HWCAP2_CRC32 (1 << 4)
+#define HWCAP2_SB (1 << 5)
+#define HWCAP2_SSBS (1 << 6)
#endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 553866751e1a..d53f56d6f840 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -45,7 +45,6 @@ obj-$(CONFIG_ISA_DMA_API) += dma.o
obj-$(CONFIG_FIQ) += fiq.o fiqasm.o
obj-$(CONFIG_MODULES) += armksyms.o module.o
obj-$(CONFIG_ARM_MODULE_PLTS) += module-plts.o
-obj-$(CONFIG_ISA_DMA) += dma-isa.o
obj-$(CONFIG_PCI) += bios32.o isa.o
obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o
obj-$(CONFIG_HIBERNATION) += hibernate.o
@@ -71,7 +70,6 @@ obj-$(CONFIG_HAVE_TCM) += tcm.o
obj-$(CONFIG_OF) += devtree.o
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_SWP_EMULATE) += swp_emulate.o
-CFLAGS_swp_emulate.o := -Wa,-march=armv7-a
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
@@ -89,7 +87,7 @@ obj-$(CONFIG_VDSO) += vdso.o
obj-$(CONFIG_EFI) += efi.o
obj-$(CONFIG_PARAVIRT) += paravirt.o
-head-y := head$(MMUEXT).o
+obj-y += head$(MMUEXT).o
obj-$(CONFIG_DEBUG_LL) += debug.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_ARM_PATCH_PHYS_VIRT) += phys2virt.o
@@ -100,7 +98,6 @@ CFLAGS_head-inflate-data.o := $(call cc-option,-Wframe-larger-than=10240)
obj-$(CONFIG_XIP_DEFLATED_DATA) += head-inflate-data.o
obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o
-AFLAGS_hyp-stub.o :=-Wa,-march=armv7-a
ifeq ($(CONFIG_ARM_PSCI),y)
obj-$(CONFIG_SMP) += psci_smp.o
endif
@@ -109,4 +106,4 @@ obj-$(CONFIG_HAVE_ARM_SMCCC) += smccc-call.o
obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += spectre.o
-extra-y := $(head-y) vmlinux.lds
+extra-y := vmlinux.lds
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 2c8d76fd7c66..f9c7111c1d65 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -47,7 +47,6 @@ int main(void)
DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain));
DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context));
DEFINE(TI_ABI_SYSCALL, offsetof(struct thread_info, abi_syscall));
- DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp));
DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
#ifdef CONFIG_VFP
@@ -56,6 +55,7 @@ int main(void)
DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu));
#endif
#endif
+ DEFINE(SOFTIRQ_DISABLE_OFFSET,SOFTIRQ_DISABLE_OFFSET);
#ifdef CONFIG_ARM_THUMBEE
DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state));
#endif
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index e7ef2b5bea9c..d334c7fb672b 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -142,15 +142,15 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F,
*/
static void pci_fixup_dec21285(struct pci_dev *dev)
{
- int i;
-
if (dev->devfn == 0) {
+ struct resource *r;
+
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
+ pci_dev_for_each_resource(dev, r) {
+ r->start = 0;
+ r->end = 0;
+ r->flags = 0;
}
}
}
@@ -162,13 +162,11 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_d
static void pci_fixup_ide_bases(struct pci_dev *dev)
{
struct resource *r;
- int i;
if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
return;
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- r = dev->resource + i;
+ pci_dev_for_each_resource(dev, r) {
if ((r->start & ~0x80) == 0x374) {
r->start |= 2;
r->end = r->start;
diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c
index e1684623e1b2..fba1f8bb03b5 100644
--- a/arch/arm/kernel/cpuidle.c
+++ b/arch/arm/kernel/cpuidle.c
@@ -5,7 +5,6 @@
#include <linux/cpuidle.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <asm/cpuidle.h>
extern struct of_cpuidle_method __cpuidle_method_of_table[];
@@ -26,8 +25,8 @@ static struct cpuidle_ops cpuidle_ops[NR_CPUS] __ro_after_init;
*
* Returns the index passed as parameter
*/
-int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+__cpuidle int arm_cpuidle_simple_enter(struct cpuidle_device *dev, struct
+ cpuidle_driver *drv, int index)
{
cpu_do_idle();
diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
index 53cb92435392..938bd932df9a 100644
--- a/arch/arm/kernel/crash_dump.c
+++ b/arch/arm/kernel/crash_dump.c
@@ -14,22 +14,10 @@
#include <linux/crash_dump.h>
#include <linux/uaccess.h>
#include <linux/io.h>
+#include <linux/uio.h>
-/**
- * copy_oldmem_page() - copy one page from old kernel memory
- * @pfn: page frame number to be copied
- * @buf: buffer where the copied page is placed
- * @csize: number of bytes to copy
- * @offset: offset in bytes into the page
- * @userbuf: if set, @buf is int he user address space
- *
- * This function copies one page from old kernel memory into buffer pointed by
- * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
- * copied or negative error in case of failure.
- */
-ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
- size_t csize, unsigned long offset,
- int userbuf)
+ssize_t copy_oldmem_page(struct iov_iter *iter, unsigned long pfn,
+ size_t csize, unsigned long offset)
{
void *vaddr;
@@ -40,14 +28,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
if (!vaddr)
return -ENOMEM;
- if (userbuf) {
- if (copy_to_user(buf, vaddr + offset, csize)) {
- iounmap(vaddr);
- return -EFAULT;
- }
- } else {
- memcpy(buf, vaddr + offset, csize);
- }
+ csize = copy_to_iter(vaddr + offset, csize, iter);
iounmap(vaddr);
return csize;
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 02839d8b6202..264827281113 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -194,14 +194,12 @@ const struct machine_desc * __init setup_machine_fdt(void *dt_virt)
{
const struct machine_desc *mdesc, *mdesc_best = NULL;
-#if defined(CONFIG_ARCH_MULTIPLATFORM) || defined(CONFIG_ARM_SINGLE_ARMV7M)
DT_MACHINE_START(GENERIC_DT, "Generic DT based system")
.l2c_aux_val = 0x0,
.l2c_aux_mask = ~0x0,
MACHINE_END
mdesc_best = &__mach_desc_GENERIC_DT;
-#endif
if (!dt_virt || !early_init_dt_verify(dt_virt))
return NULL;
diff --git a/arch/arm/kernel/efi.c b/arch/arm/kernel/efi.c
index e57dbcc89123..e2b9d2618c67 100644
--- a/arch/arm/kernel/efi.c
+++ b/arch/arm/kernel/efi.c
@@ -4,6 +4,7 @@
*/
#include <linux/efi.h>
+#include <linux/memblock.h>
#include <asm/efi.h>
#include <asm/mach/map.h>
#include <asm/mmu_context.h>
@@ -22,7 +23,8 @@ static int __init set_permissions(pte_t *ptep, unsigned long addr, void *data)
}
int __init efi_set_mapping_permissions(struct mm_struct *mm,
- efi_memory_desc_t *md)
+ efi_memory_desc_t *md,
+ bool ignored)
{
unsigned long base, size;
@@ -70,6 +72,63 @@ int __init efi_create_mapping(struct mm_struct *mm, efi_memory_desc_t *md)
* If stricter permissions were specified, apply them now.
*/
if (md->attribute & (EFI_MEMORY_RO | EFI_MEMORY_XP))
- return efi_set_mapping_permissions(mm, md);
+ return efi_set_mapping_permissions(mm, md, false);
return 0;
}
+
+static unsigned long __initdata cpu_state_table = EFI_INVALID_TABLE_ADDR;
+
+const efi_config_table_type_t efi_arch_tables[] __initconst = {
+ {LINUX_EFI_ARM_CPU_STATE_TABLE_GUID, &cpu_state_table},
+ {}
+};
+
+static void __init load_cpu_state_table(void)
+{
+ if (cpu_state_table != EFI_INVALID_TABLE_ADDR) {
+ struct efi_arm_entry_state *state;
+ bool dump_state = true;
+
+ state = early_memremap_ro(cpu_state_table,
+ sizeof(struct efi_arm_entry_state));
+ if (state == NULL) {
+ pr_warn("Unable to map CPU entry state table.\n");
+ return;
+ }
+
+ if ((state->sctlr_before_ebs & 1) == 0)
+ pr_warn(FW_BUG "EFI stub was entered with MMU and Dcache disabled, please fix your firmware!\n");
+ else if ((state->sctlr_after_ebs & 1) == 0)
+ pr_warn(FW_BUG "ExitBootServices() returned with MMU and Dcache disabled, please fix your firmware!\n");
+ else
+ dump_state = false;
+
+ if (dump_state || efi_enabled(EFI_DBG)) {
+ pr_info("CPSR at EFI stub entry : 0x%08x\n",
+ state->cpsr_before_ebs);
+ pr_info("SCTLR at EFI stub entry : 0x%08x\n",
+ state->sctlr_before_ebs);
+ pr_info("CPSR after ExitBootServices() : 0x%08x\n",
+ state->cpsr_after_ebs);
+ pr_info("SCTLR after ExitBootServices(): 0x%08x\n",
+ state->sctlr_after_ebs);
+ }
+ early_memunmap(state, sizeof(struct efi_arm_entry_state));
+ }
+}
+
+void __init arm_efi_init(void)
+{
+ efi_init();
+
+ if (screen_info.orig_video_isVGA == VIDEO_TYPE_EFI) {
+ /* dummycon on ARM needs non-zero values for columns/lines */
+ screen_info.orig_video_cols = 80;
+ screen_info.orig_video_lines = 25;
+ }
+
+ /* ARM does not permit early mappings to persist across paging_init() */
+ efi_memmap_unmap();
+
+ load_cpu_state_table();
+}
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 06508698abb8..682e92664b07 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -61,9 +61,8 @@
.macro pabt_helper
@ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
#ifdef MULTI_PABORT
- ldr ip, .LCprocfns
- mov lr, pc
- ldr pc, [ip, #PROCESSOR_PABT_FUNC]
+ ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC
+ bl_r ip
#else
bl CPU_PABORT_HANDLER
#endif
@@ -82,9 +81,8 @@
@ the fault status register in r1. r9 must be preserved.
@
#ifdef MULTI_DABORT
- ldr ip, .LCprocfns
- mov lr, pc
- ldr pc, [ip, #PROCESSOR_DABT_FUNC]
+ ldr_va ip, processor, offset=PROCESSOR_DABT_FUNC
+ bl_r ip
#else
bl CPU_DABORT_HANDLER
#endif
@@ -302,16 +300,6 @@ __fiq_svc:
UNWIND(.fnend )
ENDPROC(__fiq_svc)
- .align 5
-.LCcralign:
- .word cr_alignment
-#ifdef MULTI_DABORT
-.LCprocfns:
- .word processor
-#endif
-.LCfp:
- .word fp_enter
-
/*
* Abort mode handlers
*/
@@ -370,7 +358,7 @@ ENDPROC(__fiq_abt)
THUMB( stmia sp, {r0 - r12} )
ATRAP( mrc p15, 0, r7, c1, c0, 0)
- ATRAP( ldr r8, .LCcralign)
+ ATRAP( ldr_va r8, cr_alignment)
ldmia r0, {r3 - r5}
add r0, sp, #S_PC @ here for interlock avoidance
@@ -379,8 +367,6 @@ ENDPROC(__fiq_abt)
str r3, [sp] @ save the "real" r0 copied
@ from the exception stack
- ATRAP( ldr r8, [r8, #0])
-
@
@ We are now ready to fill in the remaining blanks on the stack:
@
@@ -460,267 +446,26 @@ ENDPROC(__irq_usr)
__und_usr:
usr_entry uaccess=0
- mov r2, r4
- mov r3, r5
-
- @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
- @ faulting instruction depending on Thumb mode.
- @ r3 = regs->ARM_cpsr
- @
- @ The emulation code returns using r9 if it has emulated the
- @ instruction, or the more conventional lr if we are to treat
- @ this as a real undefined instruction
- @
- badr r9, ret_from_exception
-
@ IRQs must be enabled before attempting to read the instruction from
@ user space since that could cause a page/translation fault if the
@ page table was modified by another CPU.
enable_irq
- tst r3, #PSR_T_BIT @ Thumb mode?
- bne __und_usr_thumb
- sub r4, r2, #4 @ ARM instr at LR - 4
-1: ldrt r0, [r4]
- ARM_BE8(rev r0, r0) @ little endian instruction
-
- uaccess_disable ip
-
- @ r0 = 32-bit ARM instruction which caused the exception
- @ r2 = PC value for the following instruction (:= regs->ARM_pc)
- @ r4 = PC value for the faulting instruction
- @ lr = 32-bit undefined instruction function
- badr lr, __und_usr_fault_32
- b call_fpe
-
-__und_usr_thumb:
- @ Thumb instruction
- sub r4, r2, #2 @ First half of thumb instr at LR - 2
-#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
-/*
- * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
- * can never be supported in a single kernel, this code is not applicable at
- * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
- * made about .arch directives.
- */
-#if __LINUX_ARM_ARCH__ < 7
-/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
-#define NEED_CPU_ARCHITECTURE
- ldr r5, .LCcpu_architecture
- ldr r5, [r5]
- cmp r5, #CPU_ARCH_ARMv7
- blo __und_usr_fault_16 @ 16bit undefined instruction
-/*
- * The following code won't get run unless the running CPU really is v7, so
- * coding round the lack of ldrht on older arches is pointless. Temporarily
- * override the assembler target arch with the minimum required instead:
- */
- .arch armv6t2
+ tst r5, #PSR_T_BIT @ Thumb mode?
+ mov r1, #2 @ set insn size to 2 for Thumb
+ bne 0f @ handle as Thumb undef exception
+#ifdef CONFIG_FPE_NWFPE
+ adr r9, ret_from_exception
+ bl call_fpe @ returns via R9 on success
#endif
-2: ldrht r5, [r4]
-ARM_BE8(rev16 r5, r5) @ little endian instruction
- cmp r5, #0xe800 @ 32bit instruction if xx != 0
- blo __und_usr_fault_16_pan @ 16bit undefined instruction
-3: ldrht r0, [r2]
-ARM_BE8(rev16 r0, r0) @ little endian instruction
+ mov r1, #4 @ set insn size to 4 for ARM
+0: mov r0, sp
uaccess_disable ip
- add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
- str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
- orr r0, r0, r5, lsl #16
- badr lr, __und_usr_fault_32
- @ r0 = the two 16-bit Thumb instructions which caused the exception
- @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
- @ r4 = PC value for the first 16-bit Thumb instruction
- @ lr = 32bit undefined instruction function
-
-#if __LINUX_ARM_ARCH__ < 7
-/* If the target arch was overridden, change it back: */
-#ifdef CONFIG_CPU_32v6K
- .arch armv6k
-#else
- .arch armv6
-#endif
-#endif /* __LINUX_ARM_ARCH__ < 7 */
-#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
- b __und_usr_fault_16
-#endif
+ bl __und_fault
+ b ret_from_exception
UNWIND(.fnend)
ENDPROC(__und_usr)
-/*
- * The out of line fixup for the ldrt instructions above.
- */
- .pushsection .text.fixup, "ax"
- .align 2
-4: str r4, [sp, #S_PC] @ retry current instruction
- ret r9
- .popsection
- .pushsection __ex_table,"a"
- .long 1b, 4b
-#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
- .long 2b, 4b
- .long 3b, 4b
-#endif
- .popsection
-
-/*
- * Check whether the instruction is a co-processor instruction.
- * If yes, we need to call the relevant co-processor handler.
- *
- * Note that we don't do a full check here for the co-processor
- * instructions; all instructions with bit 27 set are well
- * defined. The only instructions that should fault are the
- * co-processor instructions. However, we have to watch out
- * for the ARM6/ARM7 SWI bug.
- *
- * NEON is a special case that has to be handled here. Not all
- * NEON instructions are co-processor instructions, so we have
- * to make a special case of checking for them. Plus, there's
- * five groups of them, so we have a table of mask/opcode pairs
- * to check against, and if any match then we branch off into the
- * NEON handler code.
- *
- * Emulators may wish to make use of the following registers:
- * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
- * r2 = PC value to resume execution after successful emulation
- * r9 = normal "successful" return address
- * r10 = this threads thread_info structure
- * lr = unrecognised instruction return address
- * IRQs enabled, FIQs enabled.
- */
- @
- @ Fall-through from Thumb-2 __und_usr
- @
-#ifdef CONFIG_NEON
- get_thread_info r10 @ get current thread
- adr r6, .LCneon_thumb_opcodes
- b 2f
-#endif
-call_fpe:
- get_thread_info r10 @ get current thread
-#ifdef CONFIG_NEON
- adr r6, .LCneon_arm_opcodes
-2: ldr r5, [r6], #4 @ mask value
- ldr r7, [r6], #4 @ opcode bits matching in mask
- cmp r5, #0 @ end mask?
- beq 1f
- and r8, r0, r5
- cmp r8, r7 @ NEON instruction?
- bne 2b
- mov r7, #1
- strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
- strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
- b do_vfp @ let VFP handler handle this
-1:
-#endif
- tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
- tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
- reteq lr
- and r8, r0, #0x00000f00 @ mask out CP number
- mov r7, #1
- add r6, r10, r8, lsr #8 @ add used_cp[] array offset first
- strb r7, [r6, #TI_USED_CP] @ set appropriate used_cp[]
-#ifdef CONFIG_IWMMXT
- @ Test if we need to give access to iWMMXt coprocessors
- ldr r5, [r10, #TI_FLAGS]
- rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
- movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1)
- bcs iwmmxt_task_enable
-#endif
- ARM( add pc, pc, r8, lsr #6 )
- THUMB( lsr r8, r8, #6 )
- THUMB( add pc, r8 )
- nop
-
- ret.w lr @ CP#0
- W(b) do_fpe @ CP#1 (FPE)
- W(b) do_fpe @ CP#2 (FPE)
- ret.w lr @ CP#3
- ret.w lr @ CP#4
- ret.w lr @ CP#5
- ret.w lr @ CP#6
- ret.w lr @ CP#7
- ret.w lr @ CP#8
- ret.w lr @ CP#9
-#ifdef CONFIG_VFP
- W(b) do_vfp @ CP#10 (VFP)
- W(b) do_vfp @ CP#11 (VFP)
-#else
- ret.w lr @ CP#10 (VFP)
- ret.w lr @ CP#11 (VFP)
-#endif
- ret.w lr @ CP#12
- ret.w lr @ CP#13
- ret.w lr @ CP#14 (Debug)
- ret.w lr @ CP#15 (Control)
-
-#ifdef NEED_CPU_ARCHITECTURE
- .align 2
-.LCcpu_architecture:
- .word __cpu_architecture
-#endif
-
-#ifdef CONFIG_NEON
- .align 6
-
-.LCneon_arm_opcodes:
- .word 0xfe000000 @ mask
- .word 0xf2000000 @ opcode
-
- .word 0xff100000 @ mask
- .word 0xf4000000 @ opcode
-
- .word 0x00000000 @ mask
- .word 0x00000000 @ opcode
-
-.LCneon_thumb_opcodes:
- .word 0xef000000 @ mask
- .word 0xef000000 @ opcode
-
- .word 0xff100000 @ mask
- .word 0xf9000000 @ opcode
-
- .word 0x00000000 @ mask
- .word 0x00000000 @ opcode
-#endif
-
-do_fpe:
- ldr r4, .LCfp
- add r10, r10, #TI_FPSTATE @ r10 = workspace
- ldr pc, [r4] @ Call FP module USR entry point
-
-/*
- * The FP module is called with these registers set:
- * r0 = instruction
- * r2 = PC+4
- * r9 = normal "successful" return address
- * r10 = FP workspace
- * lr = unrecognised FP instruction return address
- */
-
- .pushsection .data
- .align 2
-ENTRY(fp_enter)
- .word no_fp
- .popsection
-
-ENTRY(no_fp)
- ret lr
-ENDPROC(no_fp)
-
-__und_usr_fault_32:
- mov r1, #4
- b 1f
-__und_usr_fault_16_pan:
- uaccess_disable ip
-__und_usr_fault_16:
- mov r1, #2
-1: mov r0, sp
- badr lr, ret_from_exception
- b __und_fault
-ENDPROC(__und_usr_fault_32)
-ENDPROC(__und_usr_fault_16)
-
.align 5
__pabt_usr:
usr_entry
@@ -1101,6 +846,12 @@ __kuser_helper_end:
*/
.macro vector_stub, name, mode, correction=0
.align 5
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+vector_bhb_bpiall_\name:
+ mcr p15, 0, r0, c7, c5, 6 @ BPIALL
+ @ isb not needed due to "movs pc, lr" in the vector stub
+ @ which gives a "context synchronisation".
+#endif
vector_\name:
.if \correction
@@ -1111,7 +862,8 @@ vector_\name:
stmia sp, {r0, lr} @ save r0, lr
@ Save spsr_<exception> (parent CPSR)
-2: mrs lr, spsr
+.Lvec_\name:
+ mrs lr, spsr
str lr, [sp, #8] @ save spsr
@
@@ -1145,28 +897,14 @@ vector_bhb_loop8_\name:
@ bhb workaround
mov r0, #8
-3: b . + 4
+3: W(b) . + 4
subs r0, r0, #1
bne 3b
- dsb
- isb
- b 2b
-ENDPROC(vector_bhb_loop8_\name)
-
-vector_bhb_bpiall_\name:
- .if \correction
- sub lr, lr, #\correction
- .endif
-
- @ Save r0, lr_<exception> (parent PC)
- stmia sp, {r0, lr}
-
- @ bhb workaround
- mcr p15, 0, r0, c7, c5, 6 @ BPIALL
+ dsb nsh
@ isb not needed due to "movs pc, lr" in the vector stub
@ which gives a "context synchronisation".
- b 2b
-ENDPROC(vector_bhb_bpiall_\name)
+ b .Lvec_\name
+ENDPROC(vector_bhb_loop8_\name)
.previous
#endif
@@ -1176,10 +914,15 @@ ENDPROC(vector_bhb_bpiall_\name)
.endm
.section .stubs, "ax", %progbits
- @ This must be the first word
+ @ These need to remain at the start of the section so that
+ @ they are in range of the 'SWI' entries in the vector tables
+ @ located 4k down.
+.L__vector_swi:
.word vector_swi
#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+.L__vector_bhb_loop8_swi:
.word vector_bhb_loop8_swi
+.L__vector_bhb_bpiall_swi:
.word vector_bhb_bpiall_swi
#endif
@@ -1322,10 +1065,11 @@ vector_addrexcptn:
.globl vector_fiq
.section .vectors, "ax", %progbits
-.L__vectors_start:
W(b) vector_rst
W(b) vector_und
- W(ldr) pc, .L__vectors_start + 0x1000
+ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi )
+THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi )
+ W(ldr) pc, .
W(b) vector_pabt
W(b) vector_dabt
W(b) vector_addrexcptn
@@ -1334,10 +1078,11 @@ vector_addrexcptn:
#ifdef CONFIG_HARDEN_BRANCH_HISTORY
.section .vectors.bhb.loop8, "ax", %progbits
-.L__vectors_bhb_loop8_start:
W(b) vector_rst
W(b) vector_bhb_loop8_und
- W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004
+ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi )
+THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi )
+ W(ldr) pc, .
W(b) vector_bhb_loop8_pabt
W(b) vector_bhb_loop8_dabt
W(b) vector_addrexcptn
@@ -1345,10 +1090,11 @@ vector_addrexcptn:
W(b) vector_bhb_loop8_fiq
.section .vectors.bhb.bpiall, "ax", %progbits
-.L__vectors_bhb_bpiall_start:
W(b) vector_rst
W(b) vector_bhb_bpiall_und
- W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008
+ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi )
+THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_bpiall_swi )
+ W(ldr) pc, .
W(b) vector_bhb_bpiall_pabt
W(b) vector_bhb_bpiall_dabt
W(b) vector_addrexcptn
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 90d40f4d56cf..03d4c5578c5c 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -16,19 +16,10 @@
.equ NR_syscalls, __NR_syscalls
- .macro arch_ret_to_user, tmp
-#ifdef CONFIG_ARCH_IOP32X
- mrc p15, 0, \tmp, c15, c1, 0
- tst \tmp, #(1 << 6)
- bicne \tmp, \tmp, #(1 << 6)
- mcrne p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access
-#endif
- .endm
-
#include "entry-header.S"
saved_psr .req r8
-#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
+#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING_USER)
saved_pc .req r9
#define TRACE(x...) x
#else
@@ -38,7 +29,7 @@ saved_pc .req lr
.section .entry.text,"ax",%progbits
.align 5
-#if !(IS_ENABLED(CONFIG_TRACE_IRQFLAGS) || IS_ENABLED(CONFIG_CONTEXT_TRACKING) || \
+#if !(IS_ENABLED(CONFIG_TRACE_IRQFLAGS) || IS_ENABLED(CONFIG_CONTEXT_TRACKING_USER) || \
IS_ENABLED(CONFIG_DEBUG_RSEQ))
/*
* This is the fast syscall return path. We do as little as possible here,
@@ -55,10 +46,6 @@ __ret_fast_syscall:
movs r1, r1, lsl #16
bne fast_work_pending
-
- /* perform architecture specific actions before user return */
- arch_ret_to_user r1
-
restore_user_regs fast = 1, offset = S_OFF
UNWIND(.fnend )
ENDPROC(ret_fast_syscall)
@@ -129,8 +116,6 @@ ENTRY(ret_to_user_from_irq)
no_work_pending:
asm_trace_hardirqs_on save = 0
- /* perform architecture specific actions before user return */
- arch_ret_to_user r1
ct_user_enter save = 0
restore_user_regs fast = 0, offset = 0
@@ -164,7 +149,7 @@ ENTRY(vector_bhb_loop8_swi)
1: b 2f
2: subs r8, r8, #1
bne 1b
- dsb
+ dsb nsh
isb
b 3f
ENDPROC(vector_bhb_loop8_swi)
@@ -198,7 +183,7 @@ ENTRY(vector_swi)
#endif
reload_current r10, ip
zero_fp
- alignment_trap r10, ip, __cr_alignment
+ alignment_trap r10, ip, cr_alignment
asm_trace_hardirqs_on save=0
enable_irq_notrace
ct_user_exit save=0
@@ -302,6 +287,7 @@ local_restart:
b ret_fast_syscall
#endif
ENDPROC(vector_swi)
+ .ltorg
/*
* This is the really slow path. We're going to be doing
@@ -328,14 +314,6 @@ __sys_trace_return:
bl syscall_trace_exit
b ret_slow_syscall
- .align 5
-#ifdef CONFIG_ALIGNMENT_TRAP
- .type __cr_alignment, #object
-__cr_alignment:
- .word cr_alignment
-#endif
- .ltorg
-
.macro syscall_table_start, sym
.equ __sys_nr, 0
.type \sym, #object
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 9a1dc142f782..99411fa91350 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -48,8 +48,7 @@
.macro alignment_trap, rtmp1, rtmp2, label
#ifdef CONFIG_ALIGNMENT_TRAP
mrc p15, 0, \rtmp2, c1, c0, 0
- ldr \rtmp1, \label
- ldr \rtmp1, [\rtmp1]
+ ldr_va \rtmp1, \label
teq \rtmp1, \rtmp2
mcrne p15, 0, \rtmp1, c1, c0, 0
#endif
@@ -367,25 +366,25 @@ ALT_UP_B(.L1_\@)
* between user and kernel mode.
*/
.macro ct_user_exit, save = 1
-#ifdef CONFIG_CONTEXT_TRACKING
+#ifdef CONFIG_CONTEXT_TRACKING_USER
.if \save
stmdb sp!, {r0-r3, ip, lr}
- bl context_tracking_user_exit
+ bl user_exit_callable
ldmia sp!, {r0-r3, ip, lr}
.else
- bl context_tracking_user_exit
+ bl user_exit_callable
.endif
#endif
.endm
.macro ct_user_enter, save = 1
-#ifdef CONFIG_CONTEXT_TRACKING
+#ifdef CONFIG_CONTEXT_TRACKING_USER
.if \save
stmdb sp!, {r0-r3, ip, lr}
- bl context_tracking_user_enter
+ bl user_enter_callable
ldmia sp!, {r0-r3, ip, lr}
.else
- bl context_tracking_user_enter
+ bl user_enter_callable
.endif
#endif
.endm
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index 83cc068586bc..a0b6d1e3812f 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -79,16 +79,14 @@ static unsigned long __ref adjust_address(struct dyn_ftrace *rec,
return (unsigned long)&ftrace_regs_caller_from_init;
}
-int ftrace_arch_code_modify_prepare(void)
+void ftrace_arch_code_modify_prepare(void)
{
- return 0;
}
-int ftrace_arch_code_modify_post_process(void)
+void ftrace_arch_code_modify_post_process(void)
{
/* Make sure any TLB misses during machine stop are cleared. */
flush_tlb_all();
- return 0;
}
static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr,
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 500612d3da2e..656991055bc1 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -38,10 +38,10 @@
#ifdef CONFIG_ARM_LPAE
/* LPAE requires an additional page for the PGD */
#define PG_DIR_SIZE 0x5000
-#define PMD_ORDER 3
+#define PMD_ENTRY_ORDER 3 /* PMD entry size is 2^PMD_ENTRY_ORDER */
#else
#define PG_DIR_SIZE 0x4000
-#define PMD_ORDER 2
+#define PMD_ENTRY_ORDER 2
#endif
.globl swapper_pg_dir
@@ -240,7 +240,7 @@ __create_page_tables:
mov r6, r6, lsr #SECTION_SHIFT
1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
- str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
+ str r3, [r4, r5, lsl #PMD_ENTRY_ORDER] @ identity mapping
cmp r5, r6
addlo r5, r5, #1 @ next section
blo 1b
@@ -250,7 +250,7 @@ __create_page_tables:
* set two variables to indicate the physical start and end of the
* kernel.
*/
- add r0, r4, #KERNEL_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
+ add r0, r4, #KERNEL_OFFSET >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
ldr r6, =(_end - 1)
adr_l r5, kernel_sec_start @ _pa(kernel_sec_start)
#if defined CONFIG_CPU_ENDIAN_BE8 || defined CONFIG_CPU_ENDIAN_BE32
@@ -259,8 +259,8 @@ __create_page_tables:
str r8, [r5] @ Save physical start of kernel (LE)
#endif
orr r3, r8, r7 @ Add the MMU flags
- add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
-1: str r3, [r0], #1 << PMD_ORDER
+ add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ENTRY_ORDER)
+1: str r3, [r0], #1 << PMD_ENTRY_ORDER
add r3, r3, #1 << SECTION_SHIFT
cmp r0, r6
bls 1b
@@ -280,14 +280,14 @@ __create_page_tables:
mov r3, pc
mov r3, r3, lsr #SECTION_SHIFT
orr r3, r7, r3, lsl #SECTION_SHIFT
- add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
- str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
+ add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
+ str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ENTRY_ORDER]!
ldr r6, =(_edata_loc - 1)
- add r0, r0, #1 << PMD_ORDER
- add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
+ add r0, r0, #1 << PMD_ENTRY_ORDER
+ add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ENTRY_ORDER)
1: cmp r0, r6
add r3, r3, #1 << SECTION_SHIFT
- strls r3, [r0], #1 << PMD_ORDER
+ strls r3, [r0], #1 << PMD_ENTRY_ORDER
bls 1b
#endif
@@ -297,10 +297,10 @@ __create_page_tables:
*/
mov r0, r2, lsr #SECTION_SHIFT
cmp r2, #0
- ldrne r3, =FDT_FIXED_BASE >> (SECTION_SHIFT - PMD_ORDER)
+ ldrne r3, =FDT_FIXED_BASE >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
addne r3, r3, r4
orrne r6, r7, r0, lsl #SECTION_SHIFT
- strne r6, [r3], #1 << PMD_ORDER
+ strne r6, [r3], #1 << PMD_ENTRY_ORDER
addne r6, r6, #1 << SECTION_SHIFT
strne r6, [r3]
@@ -319,7 +319,7 @@ __create_page_tables:
addruart r7, r3, r0
mov r3, r3, lsr #SECTION_SHIFT
- mov r3, r3, lsl #PMD_ORDER
+ mov r3, r3, lsl #PMD_ENTRY_ORDER
add r0, r4, r3
mov r3, r7, lsr #SECTION_SHIFT
@@ -344,12 +344,12 @@ __create_page_tables:
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
#endif
-#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
+#if defined(CONFIG_ARCH_NETWINDER)
/*
* If we're using the NetWinder or CATS, we also need to map
* in the 16550-type serial port for the debug messages
*/
- add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
+ add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
orr r3, r7, #0x7c000000
str r3, [r0]
#endif
@@ -359,10 +359,10 @@ __create_page_tables:
* Similar reasons here - for debug. This is
* only for Acorn RiscPC architectures.
*/
- add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
+ add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
orr r3, r7, #0x02000000
str r3, [r0]
- add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
+ add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
str r3, [r0]
#endif
#endif
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index b1423fb130ea..054e9199f30d 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -941,6 +941,23 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
return ret;
}
+#ifdef CONFIG_ARM_ERRATA_764319
+static int oslsr_fault;
+
+static int debug_oslsr_trap(struct pt_regs *regs, unsigned int instr)
+{
+ oslsr_fault = 1;
+ instruction_pointer(regs) += 4;
+ return 0;
+}
+
+static struct undef_hook debug_oslsr_hook = {
+ .instr_mask = 0xffffffff,
+ .instr_val = 0xee115e91,
+ .fn = debug_oslsr_trap,
+};
+#endif
+
/*
* One-time initialisation.
*/
@@ -974,7 +991,16 @@ static bool core_has_os_save_restore(void)
case ARM_DEBUG_ARCH_V7_1:
return true;
case ARM_DEBUG_ARCH_V7_ECP14:
+#ifdef CONFIG_ARM_ERRATA_764319
+ oslsr_fault = 0;
+ register_undef_hook(&debug_oslsr_hook);
ARM_DBG_READ(c1, c1, 4, oslsr);
+ unregister_undef_hook(&debug_oslsr_hook);
+ if (oslsr_fault)
+ return false;
+#else
+ ARM_DBG_READ(c1, c1, 4, oslsr);
+#endif
if (oslsr & ARM_OSLSR_OSLM0)
return true;
fallthrough;
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index b699b22a4db1..3a506b9095a5 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -9,6 +9,8 @@
#include <asm/assembler.h>
#include <asm/virt.h>
+.arch armv7-a
+
#ifndef ZIMAGE
/*
* For the kernel proper, we need to find out the CPU boot mode long after
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 5c6f8d11a3ce..fe28fc1f759d 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -70,6 +70,7 @@ static void __init init_irq_stacks(void)
}
}
+#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
static void ____do_softirq(void *arg)
{
__do_softirq();
@@ -80,7 +81,7 @@ void do_softirq_own_stack(void)
call_with_stack(____do_softirq, NULL,
__this_cpu_read(irq_stack_ptr));
}
-
+#endif
#endif
int arch_show_interrupts(struct seq_file *p, int prec)
diff --git a/arch/arm/kernel/isa.c b/arch/arm/kernel/isa.c
index d8a509c5d5bd..20218876bef2 100644
--- a/arch/arm/kernel/isa.c
+++ b/arch/arm/kernel/isa.c
@@ -40,27 +40,11 @@ static struct ctl_table ctl_isa_vars[4] = {
static struct ctl_table_header *isa_sysctl_header;
-static struct ctl_table ctl_isa[2] = {
- {
- .procname = "isa",
- .mode = 0555,
- .child = ctl_isa_vars,
- }, {}
-};
-
-static struct ctl_table ctl_bus[2] = {
- {
- .procname = "bus",
- .mode = 0555,
- .child = ctl_isa,
- }, {}
-};
-
void __init
register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift)
{
isa_membase = membase;
isa_portbase = portbase;
isa_portshift = portshift;
- isa_sysctl_header = register_sysctl_table(ctl_bus);
+ isa_sysctl_header = register_sysctl("bus/isa", ctl_isa_vars);
}
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index d2b4ac06e4ed..a0218c4867b9 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -58,9 +58,19 @@
.text
.arm
+ENTRY(iwmmxt_undef_handler)
+ push {r9, r10, lr}
+ get_thread_info r10
+ mov r9, pc
+ b iwmmxt_task_enable
+ mov r0, #0
+ pop {r9, r10, pc}
+ENDPROC(iwmmxt_undef_handler)
+
/*
* Lazy switching of Concan coprocessor context
*
+ * r0 = struct pt_regs pointer
* r10 = struct thread_info pointer
* r9 = ret_from_exception
* lr = undefined instr exit
@@ -84,12 +94,12 @@ ENTRY(iwmmxt_task_enable)
PJ4(mcr p15, 0, r2, c1, c0, 2)
ldr r3, =concan_owner
- add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
- ldr r2, [sp, #60] @ current task pc value
+ ldr r2, [r0, #S_PC] @ current task pc value
ldr r1, [r3] @ get current Concan owner
- str r0, [r3] @ this task now owns Concan regs
sub r2, r2, #4 @ adjust pc back
- str r2, [sp, #60]
+ str r2, [r0, #S_PC]
+ add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
+ str r0, [r3] @ this task now owns Concan regs
mrc p15, 0, r2, c2, c0, 0
mov r2, r2 @ cpwait
diff --git a/arch/arm/kernel/jump_label.c b/arch/arm/kernel/jump_label.c
index 303b3ab87f7e..eb9c24b6e8e2 100644
--- a/arch/arm/kernel/jump_label.c
+++ b/arch/arm/kernel/jump_label.c
@@ -27,9 +27,3 @@ void arch_jump_label_transform(struct jump_entry *entry,
{
__arch_jump_label_transform(entry, type, false);
}
-
-void arch_jump_label_transform_static(struct jump_entry *entry,
- enum jump_label_type type)
-{
- __arch_jump_label_transform(entry, type, true);
-}
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index f567032a09c0..46364b699cc3 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -73,10 +73,12 @@ void machine_kexec_cleanup(struct kimage *image)
{
}
-void machine_crash_nonpanic_core(void *unused)
+static void machine_crash_nonpanic_core(void *unused)
{
struct pt_regs regs;
+ local_fiq_disable();
+
crash_setup_regs(&regs, get_irq_regs());
printk(KERN_DEBUG "CPU %u will stop doing anything useful since another CPU has crashed\n",
smp_processor_id());
diff --git a/arch/arm/kernel/module-plts.c b/arch/arm/kernel/module-plts.c
index 1fc309b41f94..f5a43fd8c163 100644
--- a/arch/arm/kernel/module-plts.c
+++ b/arch/arm/kernel/module-plts.c
@@ -28,11 +28,6 @@ static const u32 fixed_plts[] = {
#endif
};
-static bool in_init(const struct module *mod, unsigned long loc)
-{
- return loc - (u32)mod->init_layout.base < mod->init_layout.size;
-}
-
static void prealloc_fixed(struct mod_plt_sec *pltsec, struct plt_entries *plt)
{
int i;
@@ -50,8 +45,8 @@ static void prealloc_fixed(struct mod_plt_sec *pltsec, struct plt_entries *plt)
u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val)
{
- struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
- &mod->arch.init;
+ struct mod_plt_sec *pltsec = !within_module_init(loc, mod) ?
+ &mod->arch.core : &mod->arch.init;
struct plt_entries *plt;
int idx;
@@ -284,3 +279,17 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
mod->arch.core.plt->sh_size, mod->arch.init.plt->sh_size);
return 0;
}
+
+bool in_module_plt(unsigned long loc)
+{
+ struct module *mod;
+ bool ret;
+
+ preempt_disable();
+ mod = __module_text_address(loc);
+ ret = mod && (loc - (u32)mod->arch.core.plt_ent < mod->arch.core.plt_count * PLT_ENT_SIZE ||
+ loc - (u32)mod->arch.init.plt_ent < mod->arch.init.plt_count * PLT_ENT_SIZE);
+ preempt_enable();
+
+ return ret;
+}
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 549abcedf795..d59c36dc0494 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -459,46 +459,40 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
#ifdef CONFIG_ARM_UNWIND
const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
const Elf_Shdr *sechdrs_end = sechdrs + hdr->e_shnum;
- struct mod_unwind_map maps[ARM_SEC_MAX];
- int i;
+ struct list_head *unwind_list = &mod->arch.unwind_list;
- memset(maps, 0, sizeof(maps));
+ INIT_LIST_HEAD(unwind_list);
+ mod->arch.init_table = NULL;
for (s = sechdrs; s < sechdrs_end; s++) {
const char *secname = secstrs + s->sh_name;
+ const char *txtname;
+ const Elf_Shdr *txt_sec;
- if (!(s->sh_flags & SHF_ALLOC))
+ if (!(s->sh_flags & SHF_ALLOC) ||
+ s->sh_type != ELF_SECTION_UNWIND)
continue;
- if (strcmp(".ARM.exidx.init.text", secname) == 0)
- maps[ARM_SEC_INIT].unw_sec = s;
- else if (strcmp(".ARM.exidx", secname) == 0)
- maps[ARM_SEC_CORE].unw_sec = s;
- else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
- maps[ARM_SEC_EXIT].unw_sec = s;
- else if (strcmp(".ARM.exidx.text.unlikely", secname) == 0)
- maps[ARM_SEC_UNLIKELY].unw_sec = s;
- else if (strcmp(".ARM.exidx.text.hot", secname) == 0)
- maps[ARM_SEC_HOT].unw_sec = s;
- else if (strcmp(".init.text", secname) == 0)
- maps[ARM_SEC_INIT].txt_sec = s;
- else if (strcmp(".text", secname) == 0)
- maps[ARM_SEC_CORE].txt_sec = s;
- else if (strcmp(".exit.text", secname) == 0)
- maps[ARM_SEC_EXIT].txt_sec = s;
- else if (strcmp(".text.unlikely", secname) == 0)
- maps[ARM_SEC_UNLIKELY].txt_sec = s;
- else if (strcmp(".text.hot", secname) == 0)
- maps[ARM_SEC_HOT].txt_sec = s;
- }
+ if (!strcmp(".ARM.exidx", secname))
+ txtname = ".text";
+ else
+ txtname = secname + strlen(".ARM.exidx");
+ txt_sec = find_mod_section(hdr, sechdrs, txtname);
+
+ if (txt_sec) {
+ struct unwind_table *table =
+ unwind_table_add(s->sh_addr,
+ s->sh_size,
+ txt_sec->sh_addr,
+ txt_sec->sh_size);
- for (i = 0; i < ARM_SEC_MAX; i++)
- if (maps[i].unw_sec && maps[i].txt_sec)
- mod->arch.unwind[i] =
- unwind_table_add(maps[i].unw_sec->sh_addr,
- maps[i].unw_sec->sh_size,
- maps[i].txt_sec->sh_addr,
- maps[i].txt_sec->sh_size);
+ list_add(&table->mod_list, unwind_list);
+
+ /* save init table for module_arch_freeing_init */
+ if (strcmp(".ARM.exidx.init.text", secname) == 0)
+ mod->arch.init_table = table;
+ }
+ }
#endif
#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
s = find_mod_section(hdr, sechdrs, ".pv_table");
@@ -519,19 +513,27 @@ void
module_arch_cleanup(struct module *mod)
{
#ifdef CONFIG_ARM_UNWIND
- int i;
+ struct unwind_table *tmp;
+ struct unwind_table *n;
- for (i = 0; i < ARM_SEC_MAX; i++) {
- unwind_table_del(mod->arch.unwind[i]);
- mod->arch.unwind[i] = NULL;
+ list_for_each_entry_safe(tmp, n,
+ &mod->arch.unwind_list, mod_list) {
+ list_del(&tmp->mod_list);
+ unwind_table_del(tmp);
}
+ mod->arch.init_table = NULL;
#endif
}
void __weak module_arch_freeing_init(struct module *mod)
{
#ifdef CONFIG_ARM_UNWIND
- unwind_table_del(mod->arch.unwind[ARM_SEC_INIT]);
- mod->arch.unwind[ARM_SEC_INIT] = NULL;
+ struct unwind_table *init = mod->arch.init_table;
+
+ if (init) {
+ mod->arch.init_table = NULL;
+ list_del(&init->mod_list);
+ unwind_table_del(init);
+ }
#endif
}
diff --git a/arch/arm/kernel/perf_callchain.c b/arch/arm/kernel/perf_callchain.c
index bc6b246ab55e..7147edbe56c6 100644
--- a/arch/arm/kernel/perf_callchain.c
+++ b/arch/arm/kernel/perf_callchain.c
@@ -81,13 +81,12 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs
* whist unwinding the stackframe and is like a subroutine return so we use
* the PC.
*/
-static int
-callchain_trace(struct stackframe *fr,
- void *data)
+static bool
+callchain_trace(void *data, unsigned long pc)
{
struct perf_callchain_entry_ctx *entry = data;
- perf_callchain_store(entry, fr->pc);
- return 0;
+ perf_callchain_store(entry, pc);
+ return true;
}
void
diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index 1d1fb22f44f3..4bca8098c4ff 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -126,6 +126,7 @@ static int __init pj4_cp0_init(void)
pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
elf_hwcap |= HWCAP_IWMMXT;
thread_register_notifier(&iwmmxt_notifier_block);
+ register_iwmmxt_undef_handler();
#endif
return 0;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 0617af11377f..e16ed102960c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -78,7 +78,6 @@ void arch_cpu_idle(void)
arm_pm_idle();
else
cpu_do_idle();
- raw_local_irq_enable();
}
void arch_cpu_idle_prepare(void)
@@ -201,7 +200,7 @@ void __show_regs(struct pt_regs *regs)
void show_regs(struct pt_regs * regs)
{
__show_regs(regs);
- dump_stack();
+ dump_backtrace(regs, NULL, KERN_DEFAULT);
}
ATOMIC_NOTIFIER_HEAD(thread_notify_head);
@@ -223,7 +222,6 @@ void flush_thread(void)
flush_ptrace_hw_breakpoint(tsk);
- memset(thread->used_cp, 0, sizeof(thread->used_cp));
memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
memset(&thread->fpstate, 0, sizeof(union fp_state));
@@ -232,15 +230,13 @@ void flush_thread(void)
thread_notify(THREAD_NOTIFY_FLUSH, thread);
}
-void release_thread(struct task_struct *dead_task)
-{
-}
-
asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
-int copy_thread(unsigned long clone_flags, unsigned long stack_start,
- unsigned long stk_sz, struct task_struct *p, unsigned long tls)
+int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
{
+ unsigned long clone_flags = args->flags;
+ unsigned long stack_start = args->stack;
+ unsigned long tls = args->tls;
struct thread_info *thread = task_thread_info(p);
struct pt_regs *childregs = task_pt_regs(p);
@@ -256,15 +252,15 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
thread->cpu_domain = get_domain();
#endif
- if (likely(!(p->flags & (PF_KTHREAD | PF_IO_WORKER)))) {
+ if (likely(!args->fn)) {
*childregs = *current_pt_regs();
childregs->ARM_r0 = 0;
if (stack_start)
childregs->ARM_sp = stack_start;
} else {
memset(childregs, 0, sizeof(struct pt_regs));
- thread->cpu_context.r4 = stk_sz;
- thread->cpu_context.r5 = stack_start;
+ thread->cpu_context.r4 = (unsigned long)args->fn_arg;
+ thread->cpu_context.r5 = (unsigned long)args->fn;
childregs->ARM_cpsr = SVC_MODE;
}
thread->cpu_context.pc = (unsigned long)ret_from_fork;
@@ -318,7 +314,7 @@ static int __init gate_vma_init(void)
gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
gate_vma.vm_start = 0xffff0000;
gate_vma.vm_end = 0xffff0000 + PAGE_SIZE;
- gate_vma.vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC;
+ vm_flags_init(&gate_vma, VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC);
return 0;
}
arch_initcall(gate_vma_init);
@@ -373,7 +369,7 @@ static unsigned long sigpage_addr(const struct mm_struct *mm,
slots = ((last - first) >> PAGE_SHIFT) + 1;
- offset = get_random_int() % slots;
+ offset = get_random_u32_below(slots);
addr = first + (offset << PAGE_SHIFT);
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index bfe88c6e60d5..2b945b9bd366 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -584,8 +584,6 @@ static int fpa_set(struct task_struct *target,
{
struct thread_info *thread = task_thread_info(target);
- thread->used_cp[1] = thread->used_cp[2] = 1;
-
return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
&thread->fpstate,
0, sizeof(struct user_fp));
@@ -651,11 +649,9 @@ static int vfp_set(struct task_struct *target,
if (ret)
return ret;
- ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- user_fpregs_offset + sizeof(new_vfp.fpregs),
- user_fpscr_offset);
- if (ret)
- return ret;
+ user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
+ user_fpregs_offset + sizeof(new_vfp.fpregs),
+ user_fpscr_offset);
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
&new_vfp.fpscr,
diff --git a/arch/arm/kernel/reboot.c b/arch/arm/kernel/reboot.c
index 3044fcb8d073..3f0d5c3dae11 100644
--- a/arch/arm/kernel/reboot.c
+++ b/arch/arm/kernel/reboot.c
@@ -10,6 +10,7 @@
#include <asm/cacheflush.h>
#include <asm/idmap.h>
#include <asm/virt.h>
+#include <asm/system_misc.h>
#include "reboot.h"
@@ -116,9 +117,7 @@ void machine_power_off(void)
{
local_irq_disable();
smp_send_stop();
-
- if (pm_power_off)
- pm_power_off();
+ do_kernel_power_off();
}
/*
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c
index 8aac1e10b117..ac15db66df4c 100644
--- a/arch/arm/kernel/return_address.c
+++ b/arch/arm/kernel/return_address.c
@@ -16,17 +16,17 @@ struct return_address_data {
void *addr;
};
-static int save_return_addr(struct stackframe *frame, void *d)
+static bool save_return_addr(void *d, unsigned long pc)
{
struct return_address_data *data = d;
if (!data->level) {
- data->addr = (void *)frame->pc;
+ data->addr = (void *)pc;
- return 1;
+ return false;
} else {
--data->level;
- return 0;
+ return true;
}
}
@@ -47,6 +47,7 @@ here:
frame.kr_cur = NULL;
frame.tsk = current;
#endif
+ frame.ex_frame = false;
walk_stackframe(&frame, save_return_addr, &data);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1e8a50a97edf..75cd4699e7b3 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -450,6 +450,8 @@ static void __init cpuid_init_hwcaps(void)
{
int block;
u32 isar5;
+ u32 isar6;
+ u32 pfr2;
if (cpu_architecture() < CPU_ARCH_ARMv7)
return;
@@ -485,6 +487,18 @@ static void __init cpuid_init_hwcaps(void)
block = cpuid_feature_extract_field(isar5, 16);
if (block >= 1)
elf_hwcap2 |= HWCAP2_CRC32;
+
+ /* Check for Speculation barrier instruction */
+ isar6 = read_cpuid_ext(CPUID_EXT_ISAR6);
+ block = cpuid_feature_extract_field(isar6, 12);
+ if (block >= 1)
+ elf_hwcap2 |= HWCAP2_SB;
+
+ /* Check for Speculative Store Bypassing control */
+ pfr2 = read_cpuid_ext(CPUID_EXT_PFR2);
+ block = cpuid_feature_extract_field(pfr2, 4);
+ if (block >= 1)
+ elf_hwcap2 |= HWCAP2_SSBS;
}
static void __init elf_hwcap_fixup(void)
@@ -1141,7 +1155,7 @@ void __init setup_arch(char **cmdline_p)
#endif
setup_dma_zone(mdesc);
xen_early_init();
- efi_init();
+ arm_efi_init();
/*
* Make sure the calculation for lowmem/highmem is set appropriately
* before reserving/allocating any memory
@@ -1249,6 +1263,12 @@ static const char *hwcap_str[] = {
"vfpd32",
"lpae",
"evtstrm",
+ "fphp",
+ "asimdhp",
+ "asimddp",
+ "asimdfhm",
+ "asimdbf16",
+ "i8mm",
NULL
};
@@ -1258,6 +1278,8 @@ static const char *hwcap2_str[] = {
"sha1",
"sha2",
"crc32",
+ "sb",
+ "ssbs",
NULL
};
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 459abc5d1819..e07f359254c3 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -655,7 +655,7 @@ struct page *get_signal_page(void)
PAGE_SIZE / sizeof(u32));
/* Give the signal return code some randomness */
- offset = 0x200 + (get_random_int() & 0x7fc);
+ offset = 0x200 + (get_random_u16() & 0x7fc);
signal_return_offset = offset;
/* Copy signal return handlers into the page */
@@ -708,6 +708,7 @@ static_assert(offsetof(siginfo_t, si_upper) == 0x18);
static_assert(offsetof(siginfo_t, si_pkey) == 0x14);
static_assert(offsetof(siginfo_t, si_perf_data) == 0x10);
static_assert(offsetof(siginfo_t, si_perf_type) == 0x14);
+static_assert(offsetof(siginfo_t, si_perf_flags) == 0x18);
static_assert(offsetof(siginfo_t, si_band) == 0x0c);
static_assert(offsetof(siginfo_t, si_fd) == 0x10);
static_assert(offsetof(siginfo_t, si_call_addr) == 0x0c);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 73fc645fc4c7..87f8d0e5e314 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -48,7 +48,6 @@
#include <asm/mach/arch.h>
#include <asm/mpu.h>
-#define CREATE_TRACE_POINTS
#include <trace/events/ipi.h>
/*
@@ -320,7 +319,7 @@ void __cpu_die(unsigned int cpu)
* of the other hotplug-cpu capable cores, so presumably coming
* out of idle fixes this.
*/
-void arch_cpu_idle_dead(void)
+void __noreturn arch_cpu_idle_dead(void)
{
unsigned int cpu = smp_processor_id();
@@ -382,6 +381,8 @@ void arch_cpu_idle_dead(void)
: "r" (task_stack_page(current) + THREAD_SIZE - 8),
"r" (current)
: "r0");
+
+ unreachable();
}
#endif /* CONFIG_HOTPLUG_CPU */
@@ -600,6 +601,8 @@ static DEFINE_RAW_SPINLOCK(stop_lock);
*/
static void ipi_cpu_stop(unsigned int cpu)
{
+ local_fiq_disable();
+
if (system_state <= SYSTEM_RUNNING) {
raw_spin_lock(&stop_lock);
pr_crit("CPU%u: stopping\n", cpu);
@@ -609,9 +612,6 @@ static void ipi_cpu_stop(unsigned int cpu)
set_cpu_online(cpu, false);
- local_fiq_disable();
- local_irq_disable();
-
while (1) {
cpu_relax();
wfe();
@@ -639,7 +639,7 @@ static void do_handle_IPI(int ipinr)
unsigned int cpu = smp_processor_id();
if ((unsigned)ipinr < NR_IPI)
- trace_ipi_entry_rcuidle(ipi_types[ipinr]);
+ trace_ipi_entry(ipi_types[ipinr]);
switch (ipinr) {
case IPI_WAKEUP:
@@ -686,7 +686,7 @@ static void do_handle_IPI(int ipinr)
}
if ((unsigned)ipinr < NR_IPI)
- trace_ipi_exit_rcuidle(ipi_types[ipinr]);
+ trace_ipi_exit(ipi_types[ipinr]);
}
/* Legacy version, should go away once all irqchips have been converted */
@@ -709,7 +709,7 @@ static irqreturn_t ipi_handler(int irq, void *data)
static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
{
- trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
+ trace_ipi_raise(target, ipi_types[ipinr]);
__ipi_send_mask(ipi_desc[ipinr], target);
}
@@ -748,7 +748,7 @@ void __init set_smp_ipi_range(int ipi_base, int n)
ipi_setup(smp_processor_id());
}
-void smp_send_reschedule(int cpu)
+void arch_smp_send_reschedule(int cpu)
{
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
}
@@ -778,7 +778,7 @@ void smp_send_stop(void)
* kdump fails. So split out the panic_smp_self_stop() and add
* set_cpu_online(smp_processor_id(), false).
*/
-void panic_smp_self_stop(void)
+void __noreturn panic_smp_self_stop(void)
{
pr_debug("CPU %u will stop doing anything useful since another CPU has paniced\n",
smp_processor_id());
@@ -787,14 +787,6 @@ void panic_smp_self_stop(void)
cpu_relax();
}
-/*
- * not supported here
- */
-int setup_profiling_timer(unsigned int multiplier)
-{
- return -EINVAL;
-}
-
#ifdef CONFIG_CPU_FREQ
static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index d0fa2037460a..620aa82e3bdd 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -9,6 +9,8 @@
#include <asm/stacktrace.h>
#include <asm/traps.h>
+#include "reboot.h"
+
#if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND)
/*
* Unwind the current stack frame and store the new register values in the
@@ -39,29 +41,74 @@
* Note that with framepointer enabled, even the leaf functions have the same
* prologue and epilogue, therefore we can ignore the LR value in this case.
*/
-int notrace unwind_frame(struct stackframe *frame)
+
+extern unsigned long call_with_stack_end;
+
+static int frame_pointer_check(struct stackframe *frame)
{
unsigned long high, low;
unsigned long fp = frame->fp;
+ unsigned long pc = frame->pc;
+
+ /*
+ * call_with_stack() is the only place we allow SP to jump from one
+ * stack to another, with FP and SP pointing to different stacks,
+ * skipping the FP boundary check at this point.
+ */
+ if (pc >= (unsigned long)&call_with_stack &&
+ pc < (unsigned long)&call_with_stack_end)
+ return 0;
/* only go to a higher address on the stack */
low = frame->sp;
high = ALIGN(low, THREAD_SIZE);
-#ifdef CONFIG_CC_IS_CLANG
/* check current frame pointer is within bounds */
+#ifdef CONFIG_CC_IS_CLANG
if (fp < low + 4 || fp > high - 4)
return -EINVAL;
-
- frame->sp = frame->fp;
- frame->fp = READ_ONCE_NOCHECK(*(unsigned long *)(fp));
- frame->pc = READ_ONCE_NOCHECK(*(unsigned long *)(fp + 4));
#else
- /* check current frame pointer is within bounds */
if (fp < low + 12 || fp > high - 4)
return -EINVAL;
+#endif
+
+ return 0;
+}
+
+int notrace unwind_frame(struct stackframe *frame)
+{
+ unsigned long fp = frame->fp;
+
+ if (frame_pointer_check(frame))
+ return -EINVAL;
+
+ /*
+ * When we unwind through an exception stack, include the saved PC
+ * value into the stack trace.
+ */
+ if (frame->ex_frame) {
+ struct pt_regs *regs = (struct pt_regs *)frame->sp;
+
+ /*
+ * We check that 'regs + sizeof(struct pt_regs)' (that is,
+ * &regs[1]) does not exceed the bottom of the stack to avoid
+ * accessing data outside the task's stack. This may happen
+ * when frame->ex_frame is a false positive.
+ */
+ if ((unsigned long)&regs[1] > ALIGN(frame->sp, THREAD_SIZE))
+ return -EINVAL;
+
+ frame->pc = regs->ARM_pc;
+ frame->ex_frame = false;
+ return 0;
+ }
/* restore the registers from the stack frame */
+#ifdef CONFIG_CC_IS_CLANG
+ frame->sp = frame->fp;
+ frame->fp = READ_ONCE_NOCHECK(*(unsigned long *)(fp));
+ frame->pc = READ_ONCE_NOCHECK(*(unsigned long *)(fp + 4));
+#else
frame->fp = READ_ONCE_NOCHECK(*(unsigned long *)(fp - 12));
frame->sp = READ_ONCE_NOCHECK(*(unsigned long *)(fp - 8));
frame->pc = READ_ONCE_NOCHECK(*(unsigned long *)(fp - 4));
@@ -72,17 +119,20 @@ int notrace unwind_frame(struct stackframe *frame)
(void *)frame->fp, &frame->kr_cur);
#endif
+ if (in_entry_text(frame->pc))
+ frame->ex_frame = true;
+
return 0;
}
#endif
void notrace walk_stackframe(struct stackframe *frame,
- int (*fn)(struct stackframe *, void *), void *data)
+ bool (*fn)(void *, unsigned long), void *data)
{
while (1) {
int ret;
- if (fn(frame, data))
+ if (!fn(data, frame->pc))
break;
ret = unwind_frame(frame);
if (ret < 0)
@@ -92,55 +142,32 @@ void notrace walk_stackframe(struct stackframe *frame,
EXPORT_SYMBOL(walk_stackframe);
#ifdef CONFIG_STACKTRACE
-struct stack_trace_data {
- struct stack_trace *trace;
- unsigned int no_sched_functions;
- unsigned int skip;
-};
-
-static int save_trace(struct stackframe *frame, void *d)
+static void start_stack_trace(struct stackframe *frame, struct task_struct *task,
+ unsigned long fp, unsigned long sp,
+ unsigned long lr, unsigned long pc)
{
- struct stack_trace_data *data = d;
- struct stack_trace *trace = data->trace;
- struct pt_regs *regs;
- unsigned long addr = frame->pc;
-
- if (data->no_sched_functions && in_sched_functions(addr))
- return 0;
- if (data->skip) {
- data->skip--;
- return 0;
- }
-
- trace->entries[trace->nr_entries++] = addr;
-
- if (trace->nr_entries >= trace->max_entries)
- return 1;
-
- if (!in_entry_text(frame->pc))
- return 0;
-
- regs = (struct pt_regs *)frame->sp;
- if ((unsigned long)&regs[1] > ALIGN(frame->sp, THREAD_SIZE))
- return 0;
-
- trace->entries[trace->nr_entries++] = regs->ARM_pc;
-
- return trace->nr_entries >= trace->max_entries;
+ frame->fp = fp;
+ frame->sp = sp;
+ frame->lr = lr;
+ frame->pc = pc;
+#ifdef CONFIG_KRETPROBES
+ frame->kr_cur = NULL;
+ frame->tsk = task;
+#endif
+#ifdef CONFIG_UNWINDER_FRAME_POINTER
+ frame->ex_frame = in_entry_text(frame->pc);
+#endif
}
-/* This must be noinline to so that our skip calculation works correctly */
-static noinline void __save_stack_trace(struct task_struct *tsk,
- struct stack_trace *trace, unsigned int nosched)
+void arch_stack_walk(stack_trace_consume_fn consume_entry, void *cookie,
+ struct task_struct *task, struct pt_regs *regs)
{
- struct stack_trace_data data;
struct stackframe frame;
- data.trace = trace;
- data.skip = trace->skip;
- data.no_sched_functions = nosched;
-
- if (tsk != current) {
+ if (regs) {
+ start_stack_trace(&frame, NULL, regs->ARM_fp, regs->ARM_sp,
+ regs->ARM_lr, regs->ARM_pc);
+ } else if (task != current) {
#ifdef CONFIG_SMP
/*
* What guarantees do we have here that 'tsk' is not
@@ -149,58 +176,22 @@ static noinline void __save_stack_trace(struct task_struct *tsk,
*/
return;
#else
- frame.fp = thread_saved_fp(tsk);
- frame.sp = thread_saved_sp(tsk);
- frame.lr = 0; /* recovered from the stack */
- frame.pc = thread_saved_pc(tsk);
+ start_stack_trace(&frame, task, thread_saved_fp(task),
+ thread_saved_sp(task), 0,
+ thread_saved_pc(task));
#endif
} else {
- /* We don't want this function nor the caller */
- data.skip += 2;
- frame.fp = (unsigned long)__builtin_frame_address(0);
- frame.sp = current_stack_pointer;
- frame.lr = (unsigned long)__builtin_return_address(0);
here:
- frame.pc = (unsigned long)&&here;
+ start_stack_trace(&frame, task,
+ (unsigned long)__builtin_frame_address(0),
+ current_stack_pointer,
+ (unsigned long)__builtin_return_address(0),
+ (unsigned long)&&here);
+ /* skip this function */
+ if (unwind_frame(&frame))
+ return;
}
-#ifdef CONFIG_KRETPROBES
- frame.kr_cur = NULL;
- frame.tsk = tsk;
-#endif
- walk_stackframe(&frame, save_trace, &data);
-}
-
-void save_stack_trace_regs(struct pt_regs *regs, struct stack_trace *trace)
-{
- struct stack_trace_data data;
- struct stackframe frame;
-
- data.trace = trace;
- data.skip = trace->skip;
- data.no_sched_functions = 0;
-
- frame.fp = regs->ARM_fp;
- frame.sp = regs->ARM_sp;
- frame.lr = regs->ARM_lr;
- frame.pc = regs->ARM_pc;
-#ifdef CONFIG_KRETPROBES
- frame.kr_cur = NULL;
- frame.tsk = current;
-#endif
-
- walk_stackframe(&frame, save_trace, &data);
-}
-
-void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
-{
- __save_stack_trace(tsk, trace, 1);
-}
-EXPORT_SYMBOL(save_stack_trace_tsk);
-
-void save_stack_trace(struct stack_trace *trace)
-{
- __save_stack_trace(current, trace, 0);
+ walk_stackframe(&frame, consume_entry, cookie);
}
-EXPORT_SYMBOL_GPL(save_stack_trace);
#endif
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index b74bfcf94fb1..fdce83c95acb 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -34,6 +34,7 @@
*/
#define __user_swpX_asm(data, addr, res, temp, B) \
__asm__ __volatile__( \
+ ".arch armv7-a\n" \
"0: ldrex"B" %2, [%3]\n" \
"1: strex"B" %0, %1, [%3]\n" \
" cmp %0, #0\n" \
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index 68112c172025..006163195d67 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -73,6 +73,7 @@
#include <linux/syscalls.h>
#include <linux/errno.h>
#include <linux/fs.h>
+#include <linux/filelock.h>
#include <linux/cred.h>
#include <linux/fcntl.h>
#include <linux/eventpoll.h>
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 9283dc65be31..40c7c807d67f 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -178,19 +178,22 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
for (i = -4; i < 1 + !!thumb; i++) {
unsigned int val, bad;
- if (!user_mode(regs)) {
- if (thumb) {
- u16 val16;
- bad = get_kernel_nofault(val16, &((u16 *)addr)[i]);
- val = val16;
- } else {
- bad = get_kernel_nofault(val, &((u32 *)addr)[i]);
- }
+ if (thumb) {
+ u16 tmp;
+
+ if (user_mode(regs))
+ bad = get_user(tmp, &((u16 __user *)addr)[i]);
+ else
+ bad = get_kernel_nofault(tmp, &((u16 *)addr)[i]);
+
+ val = __mem_to_opcode_thumb16(tmp);
} else {
- if (thumb)
- bad = get_user(val, &((u16 *)addr)[i]);
+ if (user_mode(regs))
+ bad = get_user(val, &((u32 __user *)addr)[i]);
else
- bad = get_user(val, &((u32 *)addr)[i]);
+ bad = get_kernel_nofault(val, &((u32 *)addr)[i]);
+
+ val = __mem_to_opcode_arm(val);
}
if (!bad)
@@ -205,14 +208,14 @@ static void dump_instr(const char *lvl, struct pt_regs *regs)
}
#ifdef CONFIG_ARM_UNWIND
-static inline void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
- const char *loglvl)
+void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
+ const char *loglvl)
{
unwind_backtrace(regs, tsk, loglvl);
}
#else
-static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
- const char *loglvl)
+void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
+ const char *loglvl)
{
unsigned int fp, mode;
int ok = 1;
@@ -487,7 +490,7 @@ asmlinkage void do_undefinstr(struct pt_regs *regs)
die_sig:
#ifdef CONFIG_DEBUG_USER
if (user_debug & UDBG_UNDEFINED) {
- pr_info("%s (%d): undefined instruction: pc=%p\n",
+ pr_info("%s (%d): undefined instruction: pc=%px\n",
current->comm, task_pid_nr(current), pc);
__show_regs(regs);
dump_instr(KERN_INFO, regs);
@@ -920,9 +923,9 @@ asmlinkage void handle_bad_stack(struct pt_regs *regs)
{
unsigned long tsk_stk = (unsigned long)current->stack;
#ifdef CONFIG_IRQSTACKS
- unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
+ unsigned long irq_stk = (unsigned long)raw_cpu_read(irq_stack_ptr);
#endif
- unsigned long ovf_stk = (unsigned long)this_cpu_read(overflow_stack_ptr);
+ unsigned long ovf_stk = (unsigned long)raw_cpu_read(overflow_stack_ptr);
console_verbose();
pr_emerg("Insufficient stack space to handle exception!");
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index a37ea6c772cd..9d2192156087 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -28,6 +28,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/list.h>
+#include <linux/module.h>
#include <asm/stacktrace.h>
#include <asm/traps.h>
@@ -307,6 +308,29 @@ static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl,
return URC_OK;
}
+static unsigned long unwind_decode_uleb128(struct unwind_ctrl_block *ctrl)
+{
+ unsigned long bytes = 0;
+ unsigned long insn;
+ unsigned long result = 0;
+
+ /*
+ * unwind_get_byte() will advance `ctrl` one instruction at a time, so
+ * loop until we get an instruction byte where bit 7 is not set.
+ *
+ * Note: This decodes a maximum of 4 bytes to output 28 bits data where
+ * max is 0xfffffff: that will cover a vsp increment of 1073742336, hence
+ * it is sufficient for unwinding the stack.
+ */
+ do {
+ insn = unwind_get_byte(ctrl);
+ result |= (insn & 0x7f) << (bytes * 7);
+ bytes++;
+ } while (!!(insn & 0x80) && (bytes != sizeof(result)));
+
+ return result;
+}
+
/*
* Execute the current unwind instruction.
*/
@@ -360,7 +384,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
if (ret)
goto error;
} else if (insn == 0xb2) {
- unsigned long uleb128 = unwind_get_byte(ctrl);
+ unsigned long uleb128 = unwind_decode_uleb128(ctrl);
ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
} else {
@@ -395,8 +419,18 @@ int unwind_frame(struct stackframe *frame)
idx = unwind_find_idx(frame->pc);
if (!idx) {
- if (frame->pc && kernel_text_address(frame->pc))
+ if (frame->pc && kernel_text_address(frame->pc)) {
+ if (in_module_plt(frame->pc) && frame->pc != frame->lr) {
+ /*
+ * Quoting Ard: Veneers only set PC using a
+ * PC+immediate LDR, and so they don't affect
+ * the state of the stack or the register file
+ */
+ frame->pc = frame->lr;
+ return URC_OK;
+ }
pr_warn("unwind: Index not found %08lx\n", frame->pc);
+ }
return -URC_FAILURE;
}
diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c
index ed4f6e77616d..00d00d3aae97 100644
--- a/arch/arm/kernel/xscale-cp0.c
+++ b/arch/arm/kernel/xscale-cp0.c
@@ -166,6 +166,7 @@ static int __init xscale_cp0_init(void)
pr_info("XScale iWMMXt coprocessor detected.\n");
elf_hwcap |= HWCAP_IWMMXT;
thread_register_notifier(&iwmmxt_notifier_block);
+ register_iwmmxt_undef_handler();
#endif
} else {
pr_info("XScale DSP coprocessor detected.\n");
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 6d2ba454f25b..650404be6768 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -36,10 +36,6 @@ else
lib-y += io-readsw-armv4.o io-writesw-armv4.o
endif
-ifeq ($(CONFIG_ARCH_RPC),y)
- AFLAGS_delay-loop.o += -march=armv4
-endif
-
$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S
@@ -48,3 +44,5 @@ ifeq ($(CONFIG_KERNEL_MODE_NEON),y)
CFLAGS_xor-neon.o += $(NEON_FLAGS)
obj-$(CONFIG_XOR_BLOCKS) += xor-neon.o
endif
+
+obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o
diff --git a/arch/arm/lib/call_with_stack.S b/arch/arm/lib/call_with_stack.S
index 0a268a6c513c..5030d4e8d126 100644
--- a/arch/arm/lib/call_with_stack.S
+++ b/arch/arm/lib/call_with_stack.S
@@ -46,4 +46,6 @@ UNWIND( .setfp fpreg, sp )
pop {fpreg, pc}
UNWIND( .fnend )
#endif
+ .globl call_with_stack_end
+call_with_stack_end:
ENDPROC(call_with_stack)
diff --git a/arch/arm/lib/delay-loop.S b/arch/arm/lib/delay-loop.S
index 3ccade0f8130..3ac05177d097 100644
--- a/arch/arm/lib/delay-loop.S
+++ b/arch/arm/lib/delay-loop.S
@@ -8,6 +8,10 @@
#include <asm/assembler.h>
#include <asm/delay.h>
+#ifdef CONFIG_ARCH_RPC
+ .arch armv4
+#endif
+
.text
.LC0: .word loops_per_jiffy
diff --git a/arch/arm/lib/error-inject.c b/arch/arm/lib/error-inject.c
new file mode 100644
index 000000000000..5a5b405792ba
--- /dev/null
+++ b/arch/arm/lib/error-inject.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/error-injection.h>
+#include <linux/kprobes.h>
+
+void override_function_with_return(struct pt_regs *regs)
+{
+ instruction_pointer_set(regs, regs->ARM_lr);
+}
+NOKPROBE_SYMBOL(override_function_with_return);
diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S
index b5e8b9ae4c7d..b7ac2d3c0748 100644
--- a/arch/arm/lib/findbit.S
+++ b/arch/arm/lib/findbit.S
@@ -12,182 +12,128 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <asm/unwind.h>
.text
-/*
- * Purpose : Find a 'zero' bit
- * Prototype: int find_first_zero_bit(void *addr, unsigned int maxbit);
- */
-ENTRY(_find_first_zero_bit_le)
- teq r1, #0
- beq 3f
- mov r2, #0
-1:
- ARM( ldrb r3, [r0, r2, lsr #3] )
- THUMB( lsr r3, r2, #3 )
- THUMB( ldrb r3, [r0, r3] )
- eors r3, r3, #0xff @ invert bits
- bne .L_found @ any now set - found zero bit
- add r2, r2, #8 @ next bit pointer
-2: cmp r2, r1 @ any more?
- blo 1b
-3: mov r0, r1 @ no free bits
- ret lr
-ENDPROC(_find_first_zero_bit_le)
+#ifdef __ARMEB__
+#define SWAB_ENDIAN le
+#else
+#define SWAB_ENDIAN be
+#endif
-/*
- * Purpose : Find next 'zero' bit
- * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit, int offset)
- */
-ENTRY(_find_next_zero_bit_le)
+ .macro find_first, endian, set, name
+ENTRY(_find_first_\name\()bit_\endian)
+ UNWIND( .fnstart)
teq r1, #0
- beq 3b
- ands ip, r2, #7
- beq 1b @ If new byte, goto old routine
- ARM( ldrb r3, [r0, r2, lsr #3] )
- THUMB( lsr r3, r2, #3 )
- THUMB( ldrb r3, [r0, r3] )
- eor r3, r3, #0xff @ now looking for a 1 bit
- movs r3, r3, lsr ip @ shift off unused bits
- bne .L_found
- orr r2, r2, #7 @ if zero, then no bits here
- add r2, r2, #1 @ align bit pointer
- b 2b @ loop for next bit
-ENDPROC(_find_next_zero_bit_le)
-
-/*
- * Purpose : Find a 'one' bit
- * Prototype: int find_first_bit(const unsigned long *addr, unsigned int maxbit);
- */
-ENTRY(_find_first_bit_le)
- teq r1, #0
beq 3f
mov r2, #0
-1:
- ARM( ldrb r3, [r0, r2, lsr #3] )
- THUMB( lsr r3, r2, #3 )
- THUMB( ldrb r3, [r0, r3] )
- movs r3, r3
- bne .L_found @ any now set - found zero bit
- add r2, r2, #8 @ next bit pointer
+1: ldr r3, [r0], #4
+ .ifeq \set
+ mvns r3, r3 @ invert/test bits
+ .else
+ movs r3, r3 @ test bits
+ .endif
+ .ifc \endian, SWAB_ENDIAN
+ bne .L_found_swab
+ .else
+ bne .L_found @ found the bit?
+ .endif
+ add r2, r2, #32 @ next index
2: cmp r2, r1 @ any more?
blo 1b
-3: mov r0, r1 @ no free bits
+3: mov r0, r1 @ no more bits
ret lr
-ENDPROC(_find_first_bit_le)
+ UNWIND( .fnend)
+ENDPROC(_find_first_\name\()bit_\endian)
+ .endm
-/*
- * Purpose : Find next 'one' bit
- * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit, int offset)
- */
-ENTRY(_find_next_bit_le)
- teq r1, #0
- beq 3b
- ands ip, r2, #7
- beq 1b @ If new byte, goto old routine
- ARM( ldrb r3, [r0, r2, lsr #3] )
- THUMB( lsr r3, r2, #3 )
- THUMB( ldrb r3, [r0, r3] )
+ .macro find_next, endian, set, name
+ENTRY(_find_next_\name\()bit_\endian)
+ UNWIND( .fnstart)
+ cmp r2, r1
+ bhs 3b
+ mov ip, r2, lsr #5 @ word index
+ add r0, r0, ip, lsl #2
+ ands ip, r2, #31 @ bit position
+ beq 1b
+ ldr r3, [r0], #4
+ .ifeq \set
+ mvn r3, r3 @ invert bits
+ .endif
+ .ifc \endian, SWAB_ENDIAN
+ rev_l r3, ip
+ .if .Lrev_l_uses_tmp
+ @ we need to recompute ip because rev_l will have overwritten
+ @ it.
+ and ip, r2, #31 @ bit position
+ .endif
+ .endif
movs r3, r3, lsr ip @ shift off unused bits
bne .L_found
- orr r2, r2, #7 @ if zero, then no bits here
+ orr r2, r2, #31 @ no zero bits
add r2, r2, #1 @ align bit pointer
b 2b @ loop for next bit
-ENDPROC(_find_next_bit_le)
+ UNWIND( .fnend)
+ENDPROC(_find_next_\name\()bit_\endian)
+ .endm
-#ifdef __ARMEB__
+ .macro find_bit, endian, set, name
+ find_first \endian, \set, \name
+ find_next \endian, \set, \name
+ .endm
-ENTRY(_find_first_zero_bit_be)
- teq r1, #0
- beq 3f
- mov r2, #0
-1: eor r3, r2, #0x18 @ big endian byte ordering
- ARM( ldrb r3, [r0, r3, lsr #3] )
- THUMB( lsr r3, #3 )
- THUMB( ldrb r3, [r0, r3] )
- eors r3, r3, #0xff @ invert bits
- bne .L_found @ any now set - found zero bit
- add r2, r2, #8 @ next bit pointer
-2: cmp r2, r1 @ any more?
- blo 1b
-3: mov r0, r1 @ no free bits
- ret lr
-ENDPROC(_find_first_zero_bit_be)
+/* _find_first_zero_bit_le and _find_next_zero_bit_le */
+ find_bit le, 0, zero_
-ENTRY(_find_next_zero_bit_be)
- teq r1, #0
- beq 3b
- ands ip, r2, #7
- beq 1b @ If new byte, goto old routine
- eor r3, r2, #0x18 @ big endian byte ordering
- ARM( ldrb r3, [r0, r3, lsr #3] )
- THUMB( lsr r3, #3 )
- THUMB( ldrb r3, [r0, r3] )
- eor r3, r3, #0xff @ now looking for a 1 bit
- movs r3, r3, lsr ip @ shift off unused bits
- bne .L_found
- orr r2, r2, #7 @ if zero, then no bits here
- add r2, r2, #1 @ align bit pointer
- b 2b @ loop for next bit
-ENDPROC(_find_next_zero_bit_be)
+/* _find_first_bit_le and _find_next_bit_le */
+ find_bit le, 1
-ENTRY(_find_first_bit_be)
- teq r1, #0
- beq 3f
- mov r2, #0
-1: eor r3, r2, #0x18 @ big endian byte ordering
- ARM( ldrb r3, [r0, r3, lsr #3] )
- THUMB( lsr r3, #3 )
- THUMB( ldrb r3, [r0, r3] )
- movs r3, r3
- bne .L_found @ any now set - found zero bit
- add r2, r2, #8 @ next bit pointer
-2: cmp r2, r1 @ any more?
- blo 1b
-3: mov r0, r1 @ no free bits
- ret lr
-ENDPROC(_find_first_bit_be)
+#ifdef __ARMEB__
-ENTRY(_find_next_bit_be)
- teq r1, #0
- beq 3b
- ands ip, r2, #7
- beq 1b @ If new byte, goto old routine
- eor r3, r2, #0x18 @ big endian byte ordering
- ARM( ldrb r3, [r0, r3, lsr #3] )
- THUMB( lsr r3, #3 )
- THUMB( ldrb r3, [r0, r3] )
- movs r3, r3, lsr ip @ shift off unused bits
- bne .L_found
- orr r2, r2, #7 @ if zero, then no bits here
- add r2, r2, #1 @ align bit pointer
- b 2b @ loop for next bit
-ENDPROC(_find_next_bit_be)
+/* _find_first_zero_bit_be and _find_next_zero_bit_be */
+ find_bit be, 0, zero_
+
+/* _find_first_bit_be and _find_next_bit_be */
+ find_bit be, 1
#endif
/*
* One or more bits in the LSB of r3 are assumed to be set.
*/
+.L_found_swab:
+ UNWIND( .fnstart)
+ rev_l r3, ip
.L_found:
-#if __LINUX_ARM_ARCH__ >= 5
+#if __LINUX_ARM_ARCH__ >= 7
+ rbit r3, r3 @ reverse bits
+ clz r3, r3 @ count high zero bits
+ add r0, r2, r3 @ add offset of first set bit
+#elif __LINUX_ARM_ARCH__ >= 5
rsb r0, r3, #0
- and r3, r3, r0
- clz r3, r3
- rsb r3, r3, #31
- add r0, r2, r3
+ and r3, r3, r0 @ mask out lowest bit set
+ clz r3, r3 @ count high zero bits
+ rsb r3, r3, #31 @ offset of first set bit
+ add r0, r2, r3 @ add offset of first set bit
#else
- tst r3, #0x0f
+ mov ip, #~0
+ tst r3, ip, lsr #16 @ test bits 0-15
+ addeq r2, r2, #16
+ moveq r3, r3, lsr #16
+ tst r3, #0x00ff
+ addeq r2, r2, #8
+ moveq r3, r3, lsr #8
+ tst r3, #0x000f
addeq r2, r2, #4
- movne r3, r3, lsl #4
- tst r3, #0x30
+ moveq r3, r3, lsr #4
+ tst r3, #0x0003
addeq r2, r2, #2
- movne r3, r3, lsl #2
- tst r3, #0x40
+ moveq r3, r3, lsr #2
+ tst r3, #0x0001
addeq r2, r2, #1
mov r0, r2
#endif
cmp r1, r0 @ Clamp to maxbit
movlo r0, r1
ret lr
-
+ UNWIND( .fnend)
diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c
index c30b689bec2e..e4c2677cc1e9 100644
--- a/arch/arm/lib/uaccess_with_memcpy.c
+++ b/arch/arm/lib/uaccess_with_memcpy.c
@@ -116,7 +116,7 @@ __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n)
tocopy = n;
ua_flags = uaccess_save_and_enable();
- memcpy((void *)to, from, tocopy);
+ __memcpy((void *)to, from, tocopy);
uaccess_restore(ua_flags);
to += tocopy;
from += tocopy;
@@ -178,7 +178,7 @@ __clear_user_memset(void __user *addr, unsigned long n)
tocopy = n;
ua_flags = uaccess_save_and_enable();
- memset((void *)addr, 0, tocopy);
+ __memset((void *)addr, 0, tocopy);
uaccess_restore(ua_flags);
addr += tocopy;
n -= tocopy;
@@ -237,7 +237,7 @@ static int __init test_size_treshold(void)
if (!dst_page)
goto no_dst;
kernel_ptr = page_address(src_page);
- user_ptr = vmap(&dst_page, 1, VM_IOREMAP, __pgprot(__P010));
+ user_ptr = vmap(&dst_page, 1, VM_IOREMAP, __pgprot(__PAGE_COPY));
if (!user_ptr)
goto no_vmap;
diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c
index f26618b43514..7b208e96fbb6 100644
--- a/arch/arm/mach-actions/platsmp.c
+++ b/arch/arm/mach-actions/platsmp.c
@@ -20,6 +20,8 @@
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
+#include <trace/events/ipi.h>
+
#define OWL_CPU1_ADDR 0x50
#define OWL_CPU1_FLAG 0x5c
diff --git a/arch/arm/mach-asm9260/Kconfig b/arch/arm/mach-asm9260/Kconfig
index a2e1d0aaf252..74e0f61c74c8 100644
--- a/arch/arm/mach-asm9260/Kconfig
+++ b/arch/arm/mach-asm9260/Kconfig
@@ -2,6 +2,7 @@
config MACH_ASM9260
bool "Alphascale ASM9260"
depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select ASM9260_TIMER
help
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index ea96d11b8502..080019aa6fcd 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_ASPEED
bool "Aspeed BMC architectures"
- depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7
+ depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V6 || ARCH_MULTI_V7
select SRAM
select WATCHDOG
select ASPEED_WATCHDOG
@@ -19,9 +19,9 @@ config MACH_ASPEED_G4
select PINCTRL_ASPEED_G4
select FTTMR010_TIMER
help
- Say yes if you intend to run on an Aspeed ast2400 or similar
- fourth generation BMCs, such as those used by OpenPower Power8
- systems.
+ Say yes if you intend to run on an Aspeed ast2400 or similar
+ fourth generation BMCs, such as those used by OpenPower Power8
+ systems.
config MACH_ASPEED_G5
bool "Aspeed SoC 5th Generation"
@@ -29,8 +29,8 @@ config MACH_ASPEED_G5
select PINCTRL_ASPEED_G5
select FTTMR010_TIMER
help
- Say yes if you intend to run on an Aspeed ast2500 or similar
- fifth generation Aspeed BMCs.
+ Say yes if you intend to run on an Aspeed ast2500 or similar
+ fifth generation Aspeed BMCs.
config MACH_ASPEED_G6
bool "Aspeed SoC 6th Generation"
@@ -40,7 +40,7 @@ config MACH_ASPEED_G6
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
help
- Say yes if you intend to run on an Aspeed ast2600 or similar
- sixth generation Aspeed BMCs.
+ Say yes if you intend to run on an Aspeed ast2600 or similar
+ sixth generation Aspeed BMCs.
endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 279810381256..3dd9e718661b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_AT91
bool "AT91/Microchip SoCs"
- depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+ depends on (CPU_LITTLE_ENDIAN && (ARCH_MULTI_V4T || ARCH_MULTI_V5)) || \
+ ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7
select COMMON_CLK_AT91
select GPIOLIB
@@ -165,6 +166,15 @@ config ATMEL_CLOCKSOURCE_TCB
to make a single 32-bit timer.
It can also be used as a clock event device supporting oneshot mode.
+config MICROCHIP_CLOCKSOURCE_PIT64B
+ bool "64-bit Periodic Interval Timer (PIT64B) support"
+ default SOC_SAM9X60 || SOC_SAMA7
+ select MICROCHIP_PIT64B
+ help
+ Select this to get a high resolution clockevent (SAM9X60) or
+ clocksource and clockevent (SAMA7G5) based on Microchip 64-bit
+ Periodic Interval Timer.
+
config HAVE_AT91_UTMI
bool
@@ -211,6 +221,15 @@ config SOC_SAMA5
config ATMEL_PM
bool
+config ATMEL_SECURE_PM
+ bool "Atmel Secure PM support"
+ depends on SOC_SAMA5D2 && ATMEL_PM
+ select ARM_PSCI
+ help
+ When running under a TEE, the suspend mode must be requested to be set
+ at TEE level. When enable, this option will use secure monitor calls
+ to set the suspend level. PSCI is then used to enter suspend.
+
config SOC_SAMA7
bool
select ARM_GIC
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 522b680b6446..794bd12ab0a8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,16 +7,13 @@
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
-obj-$(CONFIG_SOC_SAMA5) += sama5.o
+obj-$(CONFIG_SOC_SAMA5) += sama5.o sam_secure.o
obj-$(CONFIG_SOC_SAMA7) += sama7.o
obj-$(CONFIG_SOC_SAMV7) += samv7.o
# Power Management
obj-$(CONFIG_ATMEL_PM) += pm.o pm_suspend.o
-ifeq ($(CONFIG_CPU_V7),y)
-AFLAGS_pm_suspend.o := -march=armv7-a
-endif
ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
endif
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
deleted file mode 100644
index 5dde7328a7a9..000000000000
--- a/arch/arm/mach-at91/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-# Empty file waiting for deletion once Makefile.boot isn't needed any more.
-# Patch waits for application at
-# https://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 0fd609e26615..60dc56d8acfb 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -15,11 +15,10 @@
#include <linux/parser.h>
#include <linux/suspend.h>
+#include <linux/clk.h>
#include <linux/clk/at91_pmc.h>
#include <linux/platform_data/atmel.h>
-#include <soc/at91/pm.h>
-
#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/system_misc.h>
@@ -27,6 +26,7 @@
#include "generic.h"
#include "pm.h"
+#include "sam_secure.h"
#define BACKUP_DDR_PHY_CALIBRATION (9)
@@ -47,8 +47,8 @@ struct at91_pm_bu {
unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
};
-/*
- * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU
+/**
+ * struct at91_pm_sfrbu_regs - registers mapping for SFRBU
* @pswbu: power switch BU control registers
*/
struct at91_pm_sfrbu_regs {
@@ -61,13 +61,64 @@ struct at91_pm_sfrbu_regs {
};
/**
+ * enum at91_pm_eth_clk - Ethernet clock indexes
+ * @AT91_PM_ETH_PCLK: pclk index
+ * @AT91_PM_ETH_HCLK: hclk index
+ * @AT91_PM_ETH_MAX_CLK: max index
+ */
+enum at91_pm_eth_clk {
+ AT91_PM_ETH_PCLK,
+ AT91_PM_ETH_HCLK,
+ AT91_PM_ETH_MAX_CLK,
+};
+
+/**
+ * enum at91_pm_eth - Ethernet controller indexes
+ * @AT91_PM_G_ETH: gigabit Ethernet controller index
+ * @AT91_PM_E_ETH: megabit Ethernet controller index
+ * @AT91_PM_MAX_ETH: max index
+ */
+enum at91_pm_eth {
+ AT91_PM_G_ETH,
+ AT91_PM_E_ETH,
+ AT91_PM_MAX_ETH,
+};
+
+/**
+ * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks
+ * @dev: Ethernet device
+ * @np: Ethernet device node
+ * @clks: Ethernet clocks
+ * @modes: power management mode that this quirk applies to
+ * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured
+ * as wakeup source but buggy and no other wakeup source is
+ * available
+ */
+struct at91_pm_quirk_eth {
+ struct device *dev;
+ struct device_node *np;
+ struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK];
+ u32 modes;
+ u32 dns_modes;
+};
+
+/**
+ * struct at91_pm_quirks - AT91 PM quirks
+ * @eth: Ethernet quirks
+ */
+struct at91_pm_quirks {
+ struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH];
+};
+
+/**
* struct at91_soc_pm - AT91 SoC power management data structure
* @config_shdwc_ws: wakeup sources configuration function for SHDWC
* @config_pmc_ws: wakeup srouces configuration function for PMC
* @ws_ids: wakup sources of_device_id array
+ * @bu: backup unit mapped data (for backup mode)
+ * @quirks: PM quirks
* @data: PM data to be used on last phase of suspend
* @sfrbu_regs: SFRBU registers mapping
- * @bu: backup unit mapped data (for backup mode)
* @memcs: memory chip select
*/
struct at91_soc_pm {
@@ -75,19 +126,22 @@ struct at91_soc_pm {
int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
const struct of_device_id *ws_ids;
struct at91_pm_bu *bu;
+ struct at91_pm_quirks quirks;
struct at91_pm_data data;
struct at91_pm_sfrbu_regs sfrbu_regs;
void *memcs;
};
/**
- * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
+ * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes
* @AT91_PM_IOMAP_SHDWC: SHDWC controller
* @AT91_PM_IOMAP_SFRBU: SFRBU controller
+ * @AT91_PM_IOMAP_ETHC: Ethernet controller
*/
enum at91_pm_iomaps {
AT91_PM_IOMAP_SHDWC,
AT91_PM_IOMAP_SFRBU,
+ AT91_PM_IOMAP_ETHC,
};
#define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
@@ -146,7 +200,7 @@ static const struct wakeup_source_info ws_info[] = {
static const struct of_device_id sama5d2_ws_ids[] = {
{ .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
- { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
+ { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
{ .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
@@ -157,24 +211,24 @@ static const struct of_device_id sama5d2_ws_ids[] = {
};
static const struct of_device_id sam9x60_ws_ids[] = {
- { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
+ { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
- { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
+ { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
{ .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
{ /* sentinel */ }
};
static const struct of_device_id sama7g5_ws_ids[] = {
- { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
+ { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
{ .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
- { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
+ { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
{ /* sentinel */ }
};
@@ -263,6 +317,141 @@ static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
return 0;
}
+static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth)
+{
+ struct platform_device *pdev;
+
+ /* Interface NA in DT. */
+ if (!eth->np)
+ return false;
+
+ /* No quirks for this interface and current suspend mode. */
+ if (!(eth->modes & BIT(soc_pm.data.mode)))
+ return false;
+
+ if (!eth->dev) {
+ /* Driver not probed. */
+ pdev = of_find_device_by_node(eth->np);
+ if (!pdev)
+ return false;
+ eth->dev = &pdev->dev;
+ }
+
+ /* No quirks if device isn't a wakeup source. */
+ if (!device_may_wakeup(eth->dev)) {
+ put_device(eth->dev);
+ return false;
+ }
+
+ /* put_device(eth->dev) is called at the end of suspend. */
+ return true;
+}
+
+static int at91_pm_config_quirks(bool suspend)
+{
+ struct at91_pm_quirk_eth *eth;
+ int i, j, ret, tmp;
+
+ /*
+ * Ethernet IPs who's device_node pointers are stored into
+ * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1
+ * or both due to a hardware bug. If they receive WoL packets while in
+ * ULP0 or ULP1 IPs could stop working or the whole system could stop
+ * working. We cannot handle this scenario in the ethernet driver itself
+ * as the driver is common to multiple vendors and also we only know
+ * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle
+ * these scenarios here, as quirks.
+ */
+ for (i = 0; i < AT91_PM_MAX_ETH; i++) {
+ eth = &soc_pm.quirks.eth[i];
+
+ if (!at91_pm_eth_quirk_is_valid(eth))
+ continue;
+
+ /*
+ * For modes in dns_modes mask the system blocks if quirk is not
+ * applied but if applied the interface doesn't act at WoL
+ * events. Thus take care to avoid suspending if this interface
+ * is the only configured wakeup source.
+ */
+ if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
+ int ws_count = 0;
+#ifdef CONFIG_PM_SLEEP
+ struct wakeup_source *ws;
+
+ for_each_wakeup_source(ws) {
+ if (ws->dev == eth->dev)
+ continue;
+
+ ws_count++;
+ break;
+ }
+#endif
+
+ /*
+ * Checking !ws is good for all platforms with issues
+ * even when both G_ETH and E_ETH are available as dns_modes
+ * is populated only on G_ETH interface.
+ */
+ if (!ws_count) {
+ pr_err("AT91: PM: Ethernet cannot resume from WoL!");
+ ret = -EPERM;
+ put_device(eth->dev);
+ eth->dev = NULL;
+ /* No need to revert clock settings for this eth. */
+ i--;
+ goto clk_unconfigure;
+ }
+ }
+
+ if (suspend) {
+ clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks);
+ } else {
+ ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK,
+ eth->clks);
+ if (ret)
+ goto clk_unconfigure;
+ /*
+ * Release the reference to eth->dev taken in
+ * at91_pm_eth_quirk_is_valid().
+ */
+ put_device(eth->dev);
+ eth->dev = NULL;
+ }
+ }
+
+ return 0;
+
+clk_unconfigure:
+ /*
+ * In case of resume we reach this point if clk_prepare_enable() failed.
+ * we don't want to revert the previous clk_prepare_enable() for the
+ * other IP.
+ */
+ for (j = i; j >= 0; j--) {
+ eth = &soc_pm.quirks.eth[j];
+ if (suspend) {
+ if (!at91_pm_eth_quirk_is_valid(eth))
+ continue;
+
+ tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks);
+ if (tmp) {
+ pr_err("AT91: PM: failed to enable %s clocks\n",
+ j == AT91_PM_G_ETH ? "geth" : "eth");
+ }
+ } else {
+ /*
+ * Release the reference to eth->dev taken in
+ * at91_pm_eth_quirk_is_valid().
+ */
+ put_device(eth->dev);
+ eth->dev = NULL;
+ }
+ }
+
+ return ret;
+}
+
/*
* Called after processes are frozen, but before we shutdown devices.
*/
@@ -350,10 +539,42 @@ extern u32 at91_pm_suspend_in_sram_sz;
static int at91_suspend_finish(unsigned long val)
{
+ unsigned char modified_gray_code[] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
+ 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
+ 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
+ 0x10, 0x11,
+ };
+ unsigned int tmp, index;
int i;
if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
/*
+ * Bootloader will perform DDR recalibration and will try to
+ * restore the ZQ0SR0 with the value saved here. But the
+ * calibration is buggy and restoring some values from ZQ0SR0
+ * is forbidden and risky thus we need to provide processed
+ * values for these (modified gray code values).
+ */
+ tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
+
+ /* Store pull-down output impedance select. */
+ index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
+ soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
+
+ /* Store pull-up output impedance select. */
+ index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+
+ /* Store pull-down on-die termination impedance select. */
+ index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+
+ /* Store pull-up on-die termination impedance select. */
+ index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+
+ /*
* The 1st 8 words of memory might get corrupted in the process
* of DDR PHY recalibration; it is saved here in securam and it
* will be restored later, after recalibration, by bootloader
@@ -427,15 +648,11 @@ static void at91_pm_suspend(suspend_state_t state)
*/
static int at91_pm_enter(suspend_state_t state)
{
-#ifdef CONFIG_PINCTRL_AT91
- /*
- * FIXME: this is needed to communicate between the pinctrl driver and
- * the PM implementation in the machine. Possibly part of the PM
- * implementation should be moved down into the pinctrl driver and get
- * called as part of the generic suspend/resume path.
- */
- at91_pinctrl_gpio_suspend();
-#endif
+ int ret;
+
+ ret = at91_pm_config_quirks(true);
+ if (ret)
+ return ret;
switch (state) {
case PM_SUSPEND_MEM:
@@ -461,9 +678,7 @@ static int at91_pm_enter(suspend_state_t state)
}
error:
-#ifdef CONFIG_PINCTRL_AT91
- at91_pinctrl_gpio_resume();
-#endif
+ at91_pm_config_quirks(false);
return 0;
}
@@ -868,10 +1083,6 @@ static int __init at91_pm_backup_init(void)
of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
if (!located)
goto securam_fail;
-
- /* DDR3PHY_ZQ0SR0 */
- soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
- 0x188);
}
return 0;
@@ -881,6 +1092,35 @@ securam_fail:
return ret;
}
+static void __init at91_pm_secure_init(void)
+{
+ int suspend_mode;
+ struct arm_smccc_res res;
+
+ suspend_mode = soc_pm.data.suspend_mode;
+
+ res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE,
+ suspend_mode, 0);
+ if (res.a0 == 0) {
+ pr_info("AT91: Secure PM: suspend mode set to %s\n",
+ pm_modes[suspend_mode].pattern);
+ return;
+ }
+
+ pr_warn("AT91: Secure PM: %s mode not supported !\n",
+ pm_modes[suspend_mode].pattern);
+
+ res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
+ if (res.a0 == 0) {
+ pr_warn("AT91: Secure PM: failed to get default mode\n");
+ return;
+ }
+
+ pr_info("AT91: Secure PM: using default suspend mode %s\n",
+ pm_modes[suspend_mode].pattern);
+
+ soc_pm.data.suspend_mode = res.a1;
+}
static const struct of_device_id atmel_shdwc_ids[] = {
{ .compatible = "atmel,sama5d2-shdwc" },
{ .compatible = "microchip,sam9x60-shdwc" },
@@ -888,10 +1128,99 @@ static const struct of_device_id atmel_shdwc_ids[] = {
{ /* sentinel. */ }
};
+static const struct of_device_id gmac_ids[] __initconst = {
+ { .compatible = "atmel,sama5d3-gem" },
+ { .compatible = "atmel,sama5d2-gem" },
+ { .compatible = "atmel,sama5d29-gem" },
+ { .compatible = "microchip,sama7g5-gem" },
+ { },
+};
+
+static const struct of_device_id emac_ids[] __initconst = {
+ { .compatible = "atmel,sama5d3-macb" },
+ { .compatible = "microchip,sama7g5-emac" },
+ { },
+};
+
+/*
+ * Replaces _mode_to_replace with a supported mode that doesn't depend
+ * on controller pointed by _map_bitmask
+ * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91
+ * PM mode
+ * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on
+ * controller represented by _map_bitmask, _mode_to_replace needs to be
+ * updated
+ * @_mode_to_replace: standby_mode or suspend_mode that need to be
+ * updated
+ * @_mode_to_check: standby_mode or suspend_mode; this is needed here
+ * to avoid having standby_mode and suspend_mode set with the same AT91
+ * PM mode
+ */
+#define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \
+ _mode_to_check) \
+ do { \
+ if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \
+ int _mode_to_use, _mode_complementary; \
+ /* Use ULP0 if it doesn't need _map_bitmask. */ \
+ if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\
+ _mode_to_use = AT91_PM_ULP0; \
+ _mode_complementary = AT91_PM_STANDBY; \
+ } else { \
+ _mode_to_use = AT91_PM_STANDBY; \
+ _mode_complementary = AT91_PM_STANDBY; \
+ } \
+ \
+ if ((_mode_to_check) != _mode_to_use) \
+ (_mode_to_replace) = _mode_to_use; \
+ else \
+ (_mode_to_replace) = _mode_complementary;\
+ } \
+ } while (0)
+
+/*
+ * Replaces standby and suspend modes with default supported modes:
+ * ULP0 and STANDBY.
+ * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP()
+ * flags
+ * @_map: controller specific name; standby and suspend mode need to be
+ * replaced in order to not depend on this controller
+ */
+#define AT91_PM_REPLACE_MODES(_maps, _map) \
+ do { \
+ AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
+ (soc_pm.data.standby_mode), \
+ (soc_pm.data.suspend_mode)); \
+ AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
+ (soc_pm.data.suspend_mode), \
+ (soc_pm.data.standby_mode)); \
+ } while (0)
+
+static int __init at91_pm_get_eth_clks(struct device_node *np,
+ struct clk_bulk_data *clks)
+{
+ clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk");
+ if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk))
+ return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk);
+
+ clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk");
+ if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk))
+ return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk);
+
+ return 0;
+}
+
+static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks)
+{
+ return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) ||
+ IS_ERR(clks[AT91_PM_ETH_HCLK].clk);
+}
+
static void __init at91_pm_modes_init(const u32 *maps, int len)
{
+ struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH];
+ struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH];
struct device_node *np;
- int ret, mode;
+ int ret;
ret = at91_pm_backup_init();
if (ret) {
@@ -906,17 +1235,7 @@ static void __init at91_pm_modes_init(const u32 *maps, int len)
np = of_find_matching_node(NULL, atmel_shdwc_ids);
if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__);
-
- /* Use ULP0 if it doesn't needs SHDWC.*/
- if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
- mode = AT91_PM_ULP0;
- else
- mode = AT91_PM_STANDBY;
-
- if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
- soc_pm.data.standby_mode = mode;
- if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
- soc_pm.data.suspend_mode = mode;
+ AT91_PM_REPLACE_MODES(maps, SHDWC);
} else {
soc_pm.data.shdwc = of_iomap(np, 0);
of_node_put(np);
@@ -928,27 +1247,48 @@ static void __init at91_pm_modes_init(const u32 *maps, int len)
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
if (!np) {
pr_warn("%s: failed to find sfrbu!\n", __func__);
-
- /*
- * Use ULP0 if it doesn't need SHDWC or if SHDWC
- * was already located.
- */
- if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
- soc_pm.data.shdwc)
- mode = AT91_PM_ULP0;
- else
- mode = AT91_PM_STANDBY;
-
- if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
- soc_pm.data.standby_mode = mode;
- if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
- soc_pm.data.suspend_mode = mode;
+ AT91_PM_REPLACE_MODES(maps, SFRBU);
} else {
soc_pm.data.sfrbu = of_iomap(np, 0);
of_node_put(np);
}
}
+ if ((at91_is_pm_mode_active(AT91_PM_ULP1) ||
+ at91_is_pm_mode_active(AT91_PM_ULP0) ||
+ at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) &&
+ (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
+ np = of_find_matching_node(NULL, gmac_ids);
+ if (!np) {
+ np = of_find_matching_node(NULL, emac_ids);
+ if (np)
+ goto get_emac_clks;
+ AT91_PM_REPLACE_MODES(maps, ETHC);
+ goto unmap_unused_nodes;
+ } else {
+ gmac->np = np;
+ at91_pm_get_eth_clks(np, gmac->clks);
+ }
+
+ np = of_find_matching_node(NULL, emac_ids);
+ if (!np) {
+ if (at91_pm_eth_clks_empty(gmac->clks))
+ AT91_PM_REPLACE_MODES(maps, ETHC);
+ } else {
+get_emac_clks:
+ emac->np = np;
+ ret = at91_pm_get_eth_clks(np, emac->clks);
+ if (ret && at91_pm_eth_clks_empty(gmac->clks)) {
+ of_node_put(gmac->np);
+ of_node_put(emac->np);
+ gmac->np = NULL;
+ emac->np = NULL;
+ }
+ }
+ }
+
+unmap_unused_nodes:
/* Unmap all unnecessary. */
if (soc_pm.data.shdwc &&
!(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
@@ -1184,17 +1524,30 @@ void __init sama5_pm_init(void)
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
};
+ static const u32 iomaps[] __initconst = {
+ [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
+ [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
+ };
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAMA5))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
ret = at91_dt_ramc(false);
if (ret)
return;
at91_pm_init(NULL);
+
+ /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */
+ soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
+ BIT(AT91_PM_ULP0_FAST) |
+ BIT(AT91_PM_ULP1);
+ /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */
+ soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
+ BIT(AT91_PM_ULP0_FAST);
}
void __init sama5d2_pm_init(void)
@@ -1204,7 +1557,10 @@ void __init sama5d2_pm_init(void)
AT91_PM_BACKUP,
};
static const u32 iomaps[] __initconst = {
- [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
+ [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
+ [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
+ [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) |
+ AT91_PM_IOMAP(ETHC),
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
AT91_PM_IOMAP(SFRBU),
};
@@ -1213,6 +1569,12 @@ void __init sama5d2_pm_init(void)
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
return;
+ if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) {
+ pr_warn("AT91: Secure PM: ignoring standby mode\n");
+ at91_pm_secure_init();
+ return;
+ }
+
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
ret = at91_dt_ramc(false);
@@ -1229,6 +1591,17 @@ void __init sama5d2_pm_init(void)
soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
soc_pm.sfrbu_regs.pswbu.state = BIT(3);
+
+ /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */
+ soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
+ BIT(AT91_PM_ULP0_FAST) |
+ BIT(AT91_PM_ULP1);
+ /*
+ * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup
+ * source.
+ */
+ soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
+ BIT(AT91_PM_ULP0_FAST);
}
void __init sama7_pm_init(void)
@@ -1239,7 +1612,8 @@ void __init sama7_pm_init(void)
static const u32 iomaps[] __initconst = {
[AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
[AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
- AT91_PM_IOMAP(SHDWC),
+ AT91_PM_IOMAP(SHDWC) |
+ AT91_PM_IOMAP(ETHC),
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC),
};
@@ -1264,6 +1638,10 @@ void __init sama7_pm_init(void)
soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
soc_pm.sfrbu_regs.pswbu.state = BIT(2);
+
+ /* Quirks applies to ULP1 for both Ethernet interfaces. */
+ soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1);
+ soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1);
}
static int __init at91_pm_modes_select(char *str)
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index abe4ced33eda..e5869cca5e79 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -12,6 +12,10 @@
#include "pm.h"
#include "pm_data-offsets.h"
+#ifdef CONFIG_CPU_V7
+.arch armv7-a
+#endif
+
#define SRAMC_SELF_FRESH_ACTIVE 0x01
#define SRAMC_SELF_FRESH_EXIT 0x00
@@ -169,12 +173,23 @@ sr_ena_2:
cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
bne sr_ena_2
- /* Put DDR PHY's DLL in bypass mode for non-backup modes. */
+ /* Disable DX DLLs for non-backup modes. */
cmp r7, #AT91_PM_BACKUP
beq sr_ena_3
- ldr tmp1, [r3, #DDR3PHY_PIR]
- orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
- str tmp1, [r3, #DDR3PHY_PIR]
+
+ /* Do not soft reset the AC DLL. */
+ ldr tmp1, [r3, DDR3PHY_ACDLLCR]
+ bic tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
+ str tmp1, [r3, DDR3PHY_ACDLLCR]
+
+ /* Disable DX DLLs. */
+ ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
+ orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+ str tmp1, [r3, #DDR3PHY_DX0DLLCR]
+
+ ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
+ orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+ str tmp1, [r3, #DDR3PHY_DX1DLLCR]
sr_ena_3:
/* Power down DDR PHY data receivers. */
@@ -221,10 +236,14 @@ sr_ena_3:
bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
str tmp1, [r3, #DDR3PHY_DSGCR]
- /* Take DDR PHY's DLL out of bypass mode. */
- ldr tmp1, [r3, #DDR3PHY_PIR]
- bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
- str tmp1, [r3, #DDR3PHY_PIR]
+ /* Enable DX DLLs. */
+ ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
+ bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+ str tmp1, [r3, #DDR3PHY_DX0DLLCR]
+
+ ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
+ bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
+ str tmp1, [r3, #DDR3PHY_DX1DLLCR]
/* Enable quasi-dynamic programming. */
mov tmp1, #0
diff --git a/arch/arm/mach-at91/sam_secure.c b/arch/arm/mach-at91/sam_secure.c
new file mode 100644
index 000000000000..f7789cbe289f
--- /dev/null
+++ b/arch/arm/mach-at91/sam_secure.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2022, Microchip
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/of.h>
+
+#include "sam_secure.h"
+
+static bool optee_available;
+
+#define SAM_SIP_SMC_STD_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1)
+{
+ struct arm_smccc_res res = {.a0 = -1};
+
+ if (WARN_ON(!optee_available))
+ return res;
+
+ arm_smccc_smc(SAM_SIP_SMC_STD_CALL_VAL(fn), arg0, arg1, 0, 0, 0, 0, 0,
+ &res);
+
+ return res;
+}
+
+bool sam_linux_is_optee_available(void)
+{
+ /* If optee has been detected, then we are running in normal world */
+ return optee_available;
+}
+
+void __init sam_secure_init(void)
+{
+ struct device_node *np;
+
+ /*
+ * We only check that the OP-TEE node is present and available. The
+ * OP-TEE kernel driver is not needed for the type of interaction made
+ * with OP-TEE here so the driver's status is not checked.
+ */
+ np = of_find_node_by_path("/firmware/optee");
+ if (np && of_device_is_available(np))
+ optee_available = true;
+ of_node_put(np);
+
+ if (optee_available)
+ pr_info("Running under OP-TEE firmware\n");
+}
diff --git a/arch/arm/mach-at91/sam_secure.h b/arch/arm/mach-at91/sam_secure.h
new file mode 100644
index 000000000000..1a0b5ebbfc39
--- /dev/null
+++ b/arch/arm/mach-at91/sam_secure.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Microchip
+ */
+
+#ifndef SAM_SECURE_H
+#define SAM_SECURE_H
+
+#include <linux/arm-smccc.h>
+
+/* Secure Monitor mode APIs */
+#define SAMA5_SMC_SIP_SET_SUSPEND_MODE 0x400
+#define SAMA5_SMC_SIP_GET_SUSPEND_MODE 0x401
+
+void __init sam_secure_init(void);
+struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1);
+bool sam_linux_is_optee_available(void);
+
+#endif /* SAM_SECURE_H */
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index 89dab7cf01e8..bf2b5c6a18c6 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -9,11 +9,26 @@
#include <linux/of.h>
#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/outercache.h>
#include <asm/system_misc.h>
#include "generic.h"
+#include "sam_secure.h"
+
+static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
+{
+ /* OP-TEE configures the L2 cache and does not allow modifying it yet */
+}
+
+static void __init sama5_secure_cache_init(void)
+{
+ sam_secure_init();
+ if (IS_ENABLED(CONFIG_OUTER_CACHE) && sam_linux_is_optee_available())
+ outer_cache.write_sec = sama5_l2c310_write_sec;
+}
static void __init sama5_dt_device_init(void)
{
@@ -58,6 +73,7 @@ static const char *const sama5d2_compat[] __initconst = {
DT_MACHINE_START(sama5d2, "Atmel SAMA5")
/* Maintainer: Atmel */
.init_machine = sama5d2_init,
+ .init_early = sama5_secure_cache_init,
.dt_compat = sama5d2_compat,
.l2c_aux_mask = ~0UL,
MACHINE_END
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
index 512943eae30a..2e203626eda5 100644
--- a/arch/arm/mach-axxia/platsmp.c
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -39,6 +39,7 @@ static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
return -ENOENT;
syscon = of_iomap(syscon_np, 0);
+ of_node_put(syscon_np);
if (!syscon)
return -ENOMEM;
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 8db655c3e321..8789d93a7c04 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,8 +54,6 @@ config ARCH_BCM_NSP
select ARM_ERRATA_775420
select ARM_ERRATA_764369 if SMP
select ARM_TIMER_SP804
- select THERMAL
- select THERMAL_OF
help
Support for Broadcom Northstar Plus SoC.
Broadcom Northstar Plus family of SoCs are used for switching control
@@ -182,23 +180,6 @@ config ARCH_BCM_53573
The base chip is BCM53573 and there are some packaging modifications
like BCM47189 and BCM47452.
-config ARCH_BCM_63XX
- bool "Broadcom BCM63xx DSL SoC"
- depends on ARCH_MULTI_V7
- select ARCH_HAS_RESET_CONTROLLER
- select ARM_ERRATA_754322
- select ARM_ERRATA_764369 if SMP
- select ARM_GIC
- select ARM_GLOBAL_TIMER
- select CACHE_L2X0
- select HAVE_ARM_ARCH_TIMER
- select HAVE_ARM_TWD if SMP
- select HAVE_ARM_SCU if SMP
- help
- This enables support for systems based on Broadcom DSL SoCs.
- It currently supports the 'BCM63XX' ARM-based family, which includes
- the BCM63138 variant.
-
config ARCH_BRCMSTB
bool "Broadcom BCM7XXX based boards"
depends on ARCH_MULTI_V7
@@ -218,4 +199,58 @@ config ARCH_BRCMSTB
This enables support for Broadcom ARM-based set-top box chipsets,
including the 7445 family of chips.
+menuconfig ARCH_BCMBCA
+ bool "Broadcom Broadband Carrier Access (BCA) origin SoC"
+ depends on ARCH_MULTI_V7
+ select ARM_AMBA
+ select ARM_GIC
+ select HAVE_ARM_ARCH_TIMER
+ help
+ Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
+ BCA chipset.
+
+ This enables support for Broadcom BCA ARM-based broadband chipsets,
+ including the DSL, PON and Wireless family of chips.
+
+comment "BCMBCA sub platforms"
+
+if ARCH_BCMBCA
+
+config ARCH_BCMBCA_CORTEXA7
+ bool "Cortex-A7 SoCs"
+ help
+ Say Y if you intend to run the kernel on a Broadcom Broadband ARM A7
+ based chipset.
+
+ This enables support for Broadcom BCA ARM A7 broadband chipsets,
+ including various DSL, PON and Wireless family of chips.
+
+config ARCH_BCMBCA_CORTEXA9
+ bool "Cortex-A9 SoCS"
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369 if SMP
+ select ARCH_HAS_RESET_CONTROLLER
+ select ARM_GLOBAL_TIMER
+ select CACHE_L2X0
+ select HAVE_ARM_TWD if SMP
+ select HAVE_ARM_SCU if SMP
+ help
+ Say Y if you intend to run the kernel on a Broadcom Broadband ARM A9
+ based BCA chipset.
+
+ This enables support for Broadcom BCA ARM A9 broadband chipset. Currently
+ only DSL chip BCM63138.
+
+config ARCH_BCMBCA_BRAHMAB15
+ bool "Brahma-B15 SoCs"
+ select ARM_ERRATA_798181 if SMP
+ help
+ Say Y if you intend to run the kernel on a Broadcom Broadband ARM B15
+ based BCA chipset.
+
+ This enables support for Broadcom BCA ARM B15 broadband chipset. Currently
+ only DSL chip BCM63148.
+
+endif
+
endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index b2394ddb0558..2e523f29ec3b 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -1,14 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2012-2015 Broadcom Corporation
#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation version 2.
-#
-# This program is distributed "as is" WITHOUT ANY WARRANTY of any
-# kind, whether express or implied; without even the implied warranty
-# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
# Cygnus
obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
@@ -57,14 +50,13 @@ ifeq ($(CONFIG_ARCH_BCM_5301X),y)
obj-$(CONFIG_SMP) += platsmp.o
endif
-# BCM63XXx
-ifeq ($(CONFIG_ARCH_BCM_63XX),y)
-obj-y += bcm63xx.o
-obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_pmb.o
-endif
-
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
CFLAGS_platsmp-brcmstb.o += -march=armv7-a
obj-y += brcmstb.o
obj-$(CONFIG_SMP) += platsmp-brcmstb.o
endif
+
+# BCMBCA
+ifeq ($(CONFIG_ARCH_BCMBCA),y)
+obj-$(CONFIG_SMP) += bcm63xx_smp.o bcm63xx_pmb.o
+endif
diff --git a/arch/arm/mach-bcm/bcm63xx.c b/arch/arm/mach-bcm/bcm63xx.c
deleted file mode 100644
index c4c66ae51308..000000000000
--- a/arch/arm/mach-bcm/bcm63xx.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/of_platform.h>
-
-#include <asm/mach/arch.h>
-
-static const char * const bcm63xx_dt_compat[] = {
- "brcm,bcm63138",
- NULL
-};
-
-DT_MACHINE_START(BCM63XXX_DT, "BCM63xx DSL SoC")
- .dt_compat = bcm63xx_dt_compat,
- .l2c_aux_val = 0,
- .l2c_aux_mask = ~0,
-MACHINE_END
diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c
index 641e1f8fcf5e..18d0ffc621aa 100644
--- a/arch/arm/mach-bcm/bcm63xx_smp.c
+++ b/arch/arm/mach-bcm/bcm63xx_smp.c
@@ -142,8 +142,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
*/
ret = bcm63xx_pmb_power_on_cpu(dn);
of_node_put(dn);
- if (ret)
- goto out;
+
out:
iounmap(bootlut_base);
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
index 7ae894c7849b..2469b66cc59e 100644
--- a/arch/arm/mach-bcm/bcm_cygnus.c
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-bcm/bcm_hr2.c b/arch/arm/mach-bcm/bcm_hr2.c
index c104f28995d7..a19cc206ec76 100644
--- a/arch/arm/mach-bcm/bcm_hr2.c
+++ b/arch/arm/mach-bcm/bcm_hr2.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2017 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2017 Broadcom
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
index 43829e49ad93..f236e12d7a59 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.c
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013 Broadcom Corporation
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/ioport.h>
@@ -41,33 +31,23 @@ static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
int __init bcm_kona_smc_init(void)
{
struct device_node *node;
- const __be32 *prop_val;
- u64 prop_size = 0;
- unsigned long buffer_size;
- u32 buffer_phys;
+ struct resource res;
+ int ret;
/* Read buffer addr and size from the device tree node */
node = of_find_matching_node(NULL, bcm_kona_smc_ids);
if (!node)
return -ENODEV;
- prop_val = of_get_address(node, 0, &prop_size, NULL);
- if (!prop_val)
- return -EINVAL;
-
- /* We assume space for four 32-bit arguments */
- if (prop_size < 4 * sizeof(u32) || prop_size > (u64)ULONG_MAX)
- return -EINVAL;
- buffer_size = (unsigned long)prop_size;
-
- buffer_phys = be32_to_cpup(prop_val);
- if (!buffer_phys)
+ ret = of_address_to_resource(node, 0, &res);
+ of_node_put(node);
+ if (ret)
return -EINVAL;
- bcm_smc_buffer = ioremap(buffer_phys, buffer_size);
+ bcm_smc_buffer = ioremap(res.start, resource_size(&res));
if (!bcm_smc_buffer)
return -ENOMEM;
- bcm_smc_buffer_phys = buffer_phys;
+ bcm_smc_buffer_phys = res.start;
pr_info("Kona Secure API initialized\n");
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h
index 2e29ec67e414..17f3811fa543 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.h
+++ b/arch/arm/mach-bcm/bcm_kona_smc.h
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2013 Broadcom Corporation */
#ifndef BCM_KONA_SMC_H
#define BCM_KONA_SMC_H
diff --git a/arch/arm/mach-bcm/bcm_nsp.c b/arch/arm/mach-bcm/bcm_nsp.c
index a1101a3d318e..65ed9f8a518a 100644
--- a/arch/arm/mach-bcm/bcm_nsp.c
+++ b/arch/arm/mach-bcm/bcm_nsp.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2015 Broadcom Corporation
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c
index c5bf01641172..9ce9ed092b09 100644
--- a/arch/arm/mach-bcm/board_bcm21664.c
+++ b/arch/arm/mach-bcm/board_bcm21664.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-bcm/board_bcm23550.c b/arch/arm/mach-bcm/board_bcm23550.c
index 0ac01debd077..dd6e9cb785e0 100644
--- a/arch/arm/mach-bcm/board_bcm23550.c
+++ b/arch/arm/mach-bcm/board_bcm23550.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2016 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2016 Broadcom
#include <linux/of_platform.h>
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c
index 1238ac801530..91f6d633ee8e 100644
--- a/arch/arm/mach-bcm/board_bcm281xx.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012-2014 Broadcom Corporation
#include <linux/clocksource.h>
#include <linux/of_address.h>
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
index 5f127d5f1045..2e3385ced82a 100644
--- a/arch/arm/mach-bcm/brcmstb.c
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013-2014 Broadcom Corporation
#include <linux/init.h>
#include <linux/irqchip.h>
diff --git a/arch/arm/mach-bcm/kona_l2_cache.c b/arch/arm/mach-bcm/kona_l2_cache.c
index 59ad86304092..457c66e1d7ae 100644
--- a/arch/arm/mach-bcm/kona_l2_cache.c
+++ b/arch/arm/mach-bcm/kona_l2_cache.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012-2014 Broadcom Corporation
#include <linux/init.h>
diff --git a/arch/arm/mach-bcm/kona_l2_cache.h b/arch/arm/mach-bcm/kona_l2_cache.h
index 46f84a95ab1c..77c5dc033910 100644
--- a/arch/arm/mach-bcm/kona_l2_cache.h
+++ b/arch/arm/mach-bcm/kona_l2_cache.h
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2012-2014 Broadcom Corporation */
#ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE
void kona_l2_cache_init(void);
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index 4555f21e7077..8989299ebdd6 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Broadcom STB CPU SMP and hotplug support for ARM
*
* Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/delay.h>
@@ -59,7 +51,7 @@ static u32 hif_cont_reg;
/*
* We must quiesce a dying CPU before it can be killed by the boot CPU. Because
* one or more cache may be disabled, we must flush to ensure coherency. We
- * cannot use traditionl completion structures or spinlocks as they rely on
+ * cannot use traditional completion structures or spinlocks as they rely on
* coherency.
*/
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 314de9477b84..fd32e576ecd0 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -2,6 +2,7 @@
menuconfig ARCH_CLPS711X
bool "Cirrus Logic EP721x/EP731x-based"
depends on ARCH_MULTI_V4T
+ depends on CPU_LITTLE_ENDIAN
select CLPS711X_TIMER
select CPU_ARM720T
select GPIOLIB
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
deleted file mode 100644
index 1ecf5466931e..000000000000
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menuconfig ARCH_CNS3XXX
- bool "Cavium Networks CNS3XXX family"
- depends on ARCH_MULTI_V6
- select ARM_GIC
- help
- Support for Cavium Networks CNS3XXX platform.
-
-if ARCH_CNS3XXX
-
-config MACH_CNS3420VB
- bool "Support for CNS3420 Validation Board"
- depends on ATAGS
- help
- Include support for the Cavium Networks CNS3420 MPCore Platform
- Baseboard.
- This is a platform with an on-board ARM11 MPCore and has support
- for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
-
-endif
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
deleted file mode 100644
index 52ca6ed62304..000000000000
--- a/arch/arm/mach-cns3xxx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
-cns3xxx-y += core.o pm.o
-cns3xxx-$(CONFIG_ATAGS) += devices.o
-cns3xxx-$(CONFIG_PCI) += pcie.o
-cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
deleted file mode 100644
index 9099560aa462..000000000000
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ /dev/null
@@ -1,252 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Cavium Networks CNS3420 Validation Board
- *
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2008 ARM Limited
- * Copyright 2008 Cavium Networks
- * Scott Shu
- * Copyright 2010 MontaVista Software, LLC.
- * Anton Vorontsov <avorontsov@mvista.com>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/io.h>
-#include <linux/dma-mapping.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include "cns3xxx.h"
-#include "pm.h"
-#include "core.h"
-#include "devices.h"
-
-/*
- * NOR Flash
- */
-static struct mtd_partition cns3420_nor_partitions[] = {
- {
- .name = "uboot",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "kernel",
- .size = 0x004C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "filesystem",
- .size = 0x7000000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "filesystem2",
- .size = 0x0AE0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "ubootenv",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data cns3420_nor_pdata = {
- .width = 2,
- .parts = cns3420_nor_partitions,
- .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
-};
-
-static struct resource cns3420_nor_res = {
- .start = CNS3XXX_FLASH_BASE,
- .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-};
-
-static struct platform_device cns3420_nor_pdev = {
- .name = "physmap-flash",
- .id = 0,
- .resource = &cns3420_nor_res,
- .num_resources = 1,
- .dev = {
- .platform_data = &cns3420_nor_pdata,
- },
-};
-
-/*
- * UART
- */
-static void __init cns3420_early_serial_setup(void)
-{
-#ifdef CONFIG_SERIAL_8250_CONSOLE
- static struct uart_port cns3420_serial_port = {
- .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
- .mapbase = CNS3XXX_UART0_BASE,
- .irq = IRQ_CNS3XXX_UART0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
- .regshift = 2,
- .uartclk = 24000000,
- .line = 0,
- .type = PORT_16550A,
- .fifosize = 16,
- };
-
- early_serial_setup(&cns3420_serial_port);
-#endif
-}
-
-/*
- * USB
- */
-static struct resource cns3xxx_usb_ehci_resources[] = {
- [0] = {
- .start = CNS3XXX_USB_BASE,
- .end = CNS3XXX_USB_BASE + SZ_16M - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_CNS3XXX_USB_EHCI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
-
-static int csn3xxx_usb_power_on(struct platform_device *pdev)
-{
- /*
- * EHCI and OHCI share the same clock and power,
- * resetting twice would cause the 1st controller been reset.
- * Therefore only do power up at the first up device, and
- * power down at the last down device.
- *
- * Set USB AHB INCR length to 16
- */
- if (atomic_inc_return(&usb_pwr_ref) == 1) {
- cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
- cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
- cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
- __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
- MISC_CHIP_CONFIG_REG);
- }
-
- return 0;
-}
-
-static void csn3xxx_usb_power_off(struct platform_device *pdev)
-{
- /*
- * EHCI and OHCI share the same clock and power,
- * resetting twice would cause the 1st controller been reset.
- * Therefore only do power up at the first up device, and
- * power down at the last down device.
- */
- if (atomic_dec_return(&usb_pwr_ref) == 0)
- cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
-}
-
-static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
- .power_on = csn3xxx_usb_power_on,
- .power_off = csn3xxx_usb_power_off,
-};
-
-static struct platform_device cns3xxx_usb_ehci_device = {
- .name = "ehci-platform",
- .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
- .resource = cns3xxx_usb_ehci_resources,
- .dev = {
- .dma_mask = &cns3xxx_usb_ehci_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &cns3xxx_usb_ehci_pdata,
- },
-};
-
-static struct resource cns3xxx_usb_ohci_resources[] = {
- [0] = {
- .start = CNS3XXX_USB_OHCI_BASE,
- .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_CNS3XXX_USB_OHCI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
-
-static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
- .num_ports = 1,
- .power_on = csn3xxx_usb_power_on,
- .power_off = csn3xxx_usb_power_off,
-};
-
-static struct platform_device cns3xxx_usb_ohci_device = {
- .name = "ohci-platform",
- .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
- .resource = cns3xxx_usb_ohci_resources,
- .dev = {
- .dma_mask = &cns3xxx_usb_ohci_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &cns3xxx_usb_ohci_pdata,
- },
-};
-
-/*
- * Initialization
- */
-static struct platform_device *cns3420_pdevs[] __initdata = {
- &cns3420_nor_pdev,
- &cns3xxx_usb_ehci_device,
- &cns3xxx_usb_ohci_device,
-};
-
-static void __init cns3420_init(void)
-{
- cns3xxx_l2x0_init();
-
- platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
-
- cns3xxx_ahci_init();
- cns3xxx_sdhci_init();
-
- pm_power_off = cns3xxx_power_off;
-}
-
-static struct map_desc cns3420_io_desc[] __initdata = {
- {
- .virtual = CNS3XXX_UART0_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-};
-
-static void __init cns3420_map_io(void)
-{
- cns3xxx_map_io();
- iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
-
- cns3420_early_serial_setup();
-}
-
-MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
- .atag_offset = 0x100,
- .map_io = cns3420_map_io,
- .init_irq = cns3xxx_init_irq,
- .init_time = cns3xxx_timer_init,
- .init_machine = cns3420_init,
- .init_late = cns3xxx_pcie_init_late,
- .restart = cns3xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h
deleted file mode 100644
index cbb105a74f90..000000000000
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
+++ /dev/null
@@ -1,593 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2008 Cavium Networks
- */
-
-#ifndef __MACH_BOARD_CNS3XXXH
-#define __MACH_BOARD_CNS3XXXH
-
-/*
- * Memory map
- */
-#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
-#define CNS3XXX_FLASH_SIZE SZ_256M
-
-#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
-
-#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
-
-#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
-
-#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
-
-#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
-
-#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
-
-#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
-
-#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
-
-#define SMC_MEMC_STATUS_OFFSET 0x000
-#define SMC_MEMIF_CFG_OFFSET 0x004
-#define SMC_MEMC_CFG_SET_OFFSET 0x008
-#define SMC_MEMC_CFG_CLR_OFFSET 0x00C
-#define SMC_DIRECT_CMD_OFFSET 0x010
-#define SMC_SET_CYCLES_OFFSET 0x014
-#define SMC_SET_OPMODE_OFFSET 0x018
-#define SMC_REFRESH_PERIOD_0_OFFSET 0x020
-#define SMC_REFRESH_PERIOD_1_OFFSET 0x024
-#define SMC_SRAM_CYCLES0_0_OFFSET 0x100
-#define SMC_NAND_CYCLES0_0_OFFSET 0x100
-#define SMC_OPMODE0_0_OFFSET 0x104
-#define SMC_SRAM_CYCLES0_1_OFFSET 0x120
-#define SMC_NAND_CYCLES0_1_OFFSET 0x120
-#define SMC_OPMODE0_1_OFFSET 0x124
-#define SMC_USER_STATUS_OFFSET 0x200
-#define SMC_USER_CONFIG_OFFSET 0x204
-#define SMC_ECC_STATUS_OFFSET 0x300
-#define SMC_ECC_MEMCFG_OFFSET 0x304
-#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
-#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
-#define SMC_ECC_ADDR0_OFFSET 0x310
-#define SMC_ECC_ADDR1_OFFSET 0x314
-#define SMC_ECC_VALUE0_OFFSET 0x318
-#define SMC_ECC_VALUE1_OFFSET 0x31C
-#define SMC_ECC_VALUE2_OFFSET 0x320
-#define SMC_ECC_VALUE3_OFFSET 0x324
-#define SMC_PERIPH_ID_0_OFFSET 0xFE0
-#define SMC_PERIPH_ID_1_OFFSET 0xFE4
-#define SMC_PERIPH_ID_2_OFFSET 0xFE8
-#define SMC_PERIPH_ID_3_OFFSET 0xFEC
-#define SMC_PCELL_ID_0_OFFSET 0xFF0
-#define SMC_PCELL_ID_1_OFFSET 0xFF4
-#define SMC_PCELL_ID_2_OFFSET 0xFF8
-#define SMC_PCELL_ID_3_OFFSET 0xFFC
-
-#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
-
-#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
-
-#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
-
-#define RTC_SEC_OFFSET 0x00
-#define RTC_MIN_OFFSET 0x04
-#define RTC_HOUR_OFFSET 0x08
-#define RTC_DAY_OFFSET 0x0C
-#define RTC_SEC_ALM_OFFSET 0x10
-#define RTC_MIN_ALM_OFFSET 0x14
-#define RTC_HOUR_ALM_OFFSET 0x18
-#define RTC_REC_OFFSET 0x1C
-#define RTC_CTRL_OFFSET 0x20
-#define RTC_INTR_STS_OFFSET 0x34
-
-#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
-#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
-
-#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
-#define CNS3XXX_PM_BASE_VIRT 0xFB001000
-
-#define PM_CLK_GATE_OFFSET 0x00
-#define PM_SOFT_RST_OFFSET 0x04
-#define PM_HS_CFG_OFFSET 0x08
-#define PM_CACTIVE_STA_OFFSET 0x0C
-#define PM_PWR_STA_OFFSET 0x10
-#define PM_SYS_CLK_CTRL_OFFSET 0x14
-#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
-#define PM_PLL_HM_PD_OFFSET 0x1C
-
-#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
-#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
-
-#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
-
-#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
-
-#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
-
-#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
-
-#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
-
-#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
-
-#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
-#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
-
-#define TIMER1_COUNTER_OFFSET 0x00
-#define TIMER1_AUTO_RELOAD_OFFSET 0x04
-#define TIMER1_MATCH_V1_OFFSET 0x08
-#define TIMER1_MATCH_V2_OFFSET 0x0C
-
-#define TIMER2_COUNTER_OFFSET 0x10
-#define TIMER2_AUTO_RELOAD_OFFSET 0x14
-#define TIMER2_MATCH_V1_OFFSET 0x18
-#define TIMER2_MATCH_V2_OFFSET 0x1C
-
-#define TIMER1_2_CONTROL_OFFSET 0x30
-#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
-#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
-
-#define TIMER_FREERUN_OFFSET 0x40
-#define TIMER_FREERUN_CONTROL_OFFSET 0x44
-
-#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
-
-#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
-
-#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
-
-#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
-
-#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
-
-#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
-
-#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
-#define CNS3XXX_SATA2_SIZE SZ_16M
-
-#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
-
-#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
-
-#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
-
-#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
-
-#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
-
-#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
-
-#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
-
-#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
-#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
-
-#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
-
-#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
-#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
-
-#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
-#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
-
-#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
-
-#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
-
-#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
-#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
-
-#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
-
-#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
-#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
-
-#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
-#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
-
-#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
-
-/*
- * Testchip peripheral and fpga gic regions
- */
-#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
-#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
-
-#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
-#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
-
-#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
-#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
-
-#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
-#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
-
-#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
-
-/*
- * Misc block
- */
-#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-
-#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
-#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
-#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
-#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
-#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
-#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
-#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
-#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
-
-#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
-
-#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
-#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
-#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
-#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
-#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
-#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
-
-#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
-#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
-#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
-#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
-#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
-#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
-#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
-#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
-#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
-#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
-#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
-#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
-#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
-#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
-#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
-#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
-#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
-
-/*
- * Power management and clock control
- */
-#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
-
-#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
-#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
-#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
-#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
-#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
-#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
-#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
-#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
-#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
-#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
-#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
-#define PM_CSR_REG PMU_MEM_MAP(0x030)
-
-/* PM_CLK_GATE_REG */
-#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
-#define PM_CLK_GATE_REG_OFFSET_GPU (24)
-#define PM_CLK_GATE_REG_OFFSET_CIM (23)
-#define PM_CLK_GATE_REG_OFFSET_LCDC (22)
-#define PM_CLK_GATE_REG_OFFSET_I2S (21)
-#define PM_CLK_GATE_REG_OFFSET_RAID (20)
-#define PM_CLK_GATE_REG_OFFSET_SATA (19)
-#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
-#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
-#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
-#define PM_CLK_GATE_REG_OFFSET_TIMER (14)
-#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
-#define PM_CLK_GATE_REG_OFFSET_HCIE (12)
-#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
-#define PM_CLK_GATE_REG_OFFSET_GPIO (10)
-#define PM_CLK_GATE_REG_OFFSET_UART3 (9)
-#define PM_CLK_GATE_REG_OFFSET_UART2 (8)
-#define PM_CLK_GATE_REG_OFFSET_UART1 (7)
-#define PM_CLK_GATE_REG_OFFSET_RTC (5)
-#define PM_CLK_GATE_REG_OFFSET_GDMA (4)
-#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
-#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
-#define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
-
-/* PM_SOFT_RST_REG */
-#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
-#define PM_SOFT_RST_REG_OFFST_CPU1 (29)
-#define PM_SOFT_RST_REG_OFFST_CPU0 (28)
-#define PM_SOFT_RST_REG_OFFST_SDIO (25)
-#define PM_SOFT_RST_REG_OFFST_GPU (24)
-#define PM_SOFT_RST_REG_OFFST_CIM (23)
-#define PM_SOFT_RST_REG_OFFST_LCDC (22)
-#define PM_SOFT_RST_REG_OFFST_I2S (21)
-#define PM_SOFT_RST_REG_OFFST_RAID (20)
-#define PM_SOFT_RST_REG_OFFST_SATA (19)
-#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))
-#define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
-#define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
-#define PM_SOFT_RST_REG_OFFST_TIMER (14)
-#define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
-#define PM_SOFT_RST_REG_OFFST_HCIE (12)
-#define PM_SOFT_RST_REG_OFFST_SWITCH (11)
-#define PM_SOFT_RST_REG_OFFST_GPIO (10)
-#define PM_SOFT_RST_REG_OFFST_UART3 (9)
-#define PM_SOFT_RST_REG_OFFST_UART2 (8)
-#define PM_SOFT_RST_REG_OFFST_UART1 (7)
-#define PM_SOFT_RST_REG_OFFST_RTC (5)
-#define PM_SOFT_RST_REG_OFFST_GDMA (4)
-#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
-#define PM_SOFT_RST_REG_OFFST_DMC (2)
-#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
-#define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
-#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
-
-/* PMHS_CFG_REG */
-#define PM_HS_CFG_REG_OFFSET_SDIO (25)
-#define PM_HS_CFG_REG_OFFSET_GPU (24)
-#define PM_HS_CFG_REG_OFFSET_CIM (23)
-#define PM_HS_CFG_REG_OFFSET_LCDC (22)
-#define PM_HS_CFG_REG_OFFSET_I2S (21)
-#define PM_HS_CFG_REG_OFFSET_RAID (20)
-#define PM_HS_CFG_REG_OFFSET_SATA (19)
-#define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
-#define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
-#define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
-#define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
-#define PM_HS_CFG_REG_OFFSET_TIMER (14)
-#define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
-#define PM_HS_CFG_REG_OFFSET_HCIE (12)
-#define PM_HS_CFG_REG_OFFSET_SWITCH (11)
-#define PM_HS_CFG_REG_OFFSET_GPIO (10)
-#define PM_HS_CFG_REG_OFFSET_UART3 (9)
-#define PM_HS_CFG_REG_OFFSET_UART2 (8)
-#define PM_HS_CFG_REG_OFFSET_UART1 (7)
-#define PM_HS_CFG_REG_OFFSET_RTC (5)
-#define PM_HS_CFG_REG_OFFSET_GDMA (4)
-#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
-#define PM_HS_CFG_REG_OFFSET_DMC (2)
-#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
-#define PM_HS_CFG_REG_MASK (0x03FFFFBE)
-#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
-
-/* PM_CACTIVE_STA_REG */
-#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
-#define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
-#define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
-#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
-#define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
-#define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
-#define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
-#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
-#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
-#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
-#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
-#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
-#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
-#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
-#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
-#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
-#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
-#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
-#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
-#define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
-#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
-#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
-#define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
-#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
-#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
-
-/* PM_PWR_STA_REG */
-#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
-#define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
-#define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
-#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
-#define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
-#define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
-#define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
-#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
-#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
-#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
-#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
-#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
-#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
-#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
-#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
-#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
-#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
-#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
-#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
-#define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
-#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
-#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
-#define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
-#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
-#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
-
-/* PM_CLK_CTRL_REG */
-#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
-#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
-#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
-#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
-#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
-#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
-#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
-#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
-#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
-#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
-#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
-#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
-#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
-#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
-#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
-#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
-
-#define PM_CPU_CLK_DIV(DIV) { \
- PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
- PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
-}
-
-#define PM_PLL_CPU_SEL(CPU) { \
- PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
- PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
-}
-
-/* PM_PLL_LCD_I2S_CTRL_REG */
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
-
-/* PM_PLL_HM_PD_CTRL_REG */
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
-#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
-
-/* PM_WDT_CTRL_REG */
-#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
-
-/* PM_CSR_REG - Clock Scaling Register*/
-#define PM_CSR_REG_OFFSET_CSR_EN (30)
-#define PM_CSR_REG_OFFSET_CSR_NUM (0)
-
-#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
-
-/* Software reset*/
-#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
-
-/*
- * CNS3XXX support several power saving mode as following,
- * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
- */
-#define CNS3XXX_PWR_CPU_MODE_DFS (0)
-#define CNS3XXX_PWR_CPU_MODE_IDLE (1)
-#define CNS3XXX_PWR_CPU_MODE_HALT (2)
-#define CNS3XXX_PWR_CPU_MODE_DOZE (3)
-#define CNS3XXX_PWR_CPU_MODE_SLEEP (4)
-#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)
-
-#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
-#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK
-
-/* Change CPU frequency and divider */
-#define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
-#define CNS3XXX_PWR_PLL_CPU_333MHZ (1)
-#define CNS3XXX_PWR_PLL_CPU_366MHZ (2)
-#define CNS3XXX_PWR_PLL_CPU_400MHZ (3)
-#define CNS3XXX_PWR_PLL_CPU_433MHZ (4)
-#define CNS3XXX_PWR_PLL_CPU_466MHZ (5)
-#define CNS3XXX_PWR_PLL_CPU_500MHZ (6)
-#define CNS3XXX_PWR_PLL_CPU_533MHZ (7)
-#define CNS3XXX_PWR_PLL_CPU_566MHZ (8)
-#define CNS3XXX_PWR_PLL_CPU_600MHZ (9)
-#define CNS3XXX_PWR_PLL_CPU_633MHZ (10)
-#define CNS3XXX_PWR_PLL_CPU_666MHZ (11)
-#define CNS3XXX_PWR_PLL_CPU_700MHZ (12)
-
-#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
-#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)
-#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)
-
-/* Change DDR2 frequency */
-#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
-#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)
-#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)
-#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)
-
-void cns3xxx_pwr_soft_rst(unsigned int block);
-void cns3xxx_pwr_clk_en(unsigned int block);
-int cns3xxx_cpu_clock(void);
-
-/*
- * ARM11 MPCore interrupt sources (primary GIC)
- */
-#define IRQ_TC11MP_GIC_START 32
-
-#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
-#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
-#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
-#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)
-#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)
-#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)
-#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)
-#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)
-#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)
-#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)
-#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)
-#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)
-#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)
-#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)
-#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)
-#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)
-#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)
-
-#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)
-#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)
-#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)
-#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)
-#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)
-#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)
-#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)
-#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)
-#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)
-#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)
-
-#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)
-#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)
-#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)
-#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)
-#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)
-#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)
-#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)
-#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)
-#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)
-
-#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)
-#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)
-#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)
-#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)
-#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)
-#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)
-#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)
-#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)
-#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)
-#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)
-#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)
-#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)
-#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)
-#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)
-#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)
-#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)
-#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)
-#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)
-#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)
-
-#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)
-#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)
-#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)
-#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)
-#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)
-#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)
-#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)
-#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)
-#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)
-
-#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
-
-#endif /* __MACH_BOARD_CNS3XXX_H */
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
deleted file mode 100644
index e4f4b20b83a2..000000000000
--- a/arch/arm/mach-cns3xxx/core.c
+++ /dev/null
@@ -1,408 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright 1999 - 2003 ARM Limited
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2008 Cavium Networks
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/clockchips.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/of_platform.h>
-#include <linux/platform_device.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/mach/irq.h>
-#include <asm/hardware/cache-l2x0.h>
-#include "cns3xxx.h"
-#include "core.h"
-#include "pm.h"
-
-static struct map_desc cns3xxx_io_desc[] __initdata = {
- {
- .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
- .length = SZ_8K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_MISC_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_PM_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
-#ifdef CONFIG_PCI
- }, {
- .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
- .length = SZ_64K, /* really 4 KiB at offset 32 KiB */
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
- .length = SZ_16M,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
- .length = SZ_64K, /* really 4 KiB at offset 32 KiB */
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
- .length = SZ_16M,
- .type = MT_DEVICE,
-#endif
- },
-};
-
-void __init cns3xxx_map_io(void)
-{
- iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
-}
-
-/* used by entry-macro.S */
-void __init cns3xxx_init_irq(void)
-{
- gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
- IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
-}
-
-void cns3xxx_power_off(void)
-{
- u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
- u32 clkctrl;
-
- printk(KERN_INFO "powering system down...\n");
-
- clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
- clkctrl &= 0xfffff1ff;
- clkctrl |= (0x5 << 9); /* Hibernate */
- writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
-
-}
-
-/*
- * Timer
- */
-static void __iomem *cns3xxx_tmr1;
-
-static int cns3xxx_shutdown(struct clock_event_device *clk)
-{
- writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- return 0;
-}
-
-static int cns3xxx_set_oneshot(struct clock_event_device *clk)
-{
- unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- /* period set, and timer enabled in 'next_event' hook */
- ctrl |= (1 << 2) | (1 << 9);
- writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- return 0;
-}
-
-static int cns3xxx_set_periodic(struct clock_event_device *clk)
-{
- unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- int pclk = cns3xxx_cpu_clock() / 8;
- int reload;
-
- reload = pclk * 20 / (3 * HZ) * 0x25000;
- writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
- writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- return 0;
-}
-
-static int cns3xxx_timer_set_next_event(unsigned long evt,
- struct clock_event_device *unused)
-{
- unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- return 0;
-}
-
-static struct clock_event_device cns3xxx_tmr1_clockevent = {
- .name = "cns3xxx timer1",
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .set_state_shutdown = cns3xxx_shutdown,
- .set_state_periodic = cns3xxx_set_periodic,
- .set_state_oneshot = cns3xxx_set_oneshot,
- .tick_resume = cns3xxx_shutdown,
- .set_next_event = cns3xxx_timer_set_next_event,
- .rating = 350,
- .cpumask = cpu_all_mask,
-};
-
-static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
-{
- cns3xxx_tmr1_clockevent.irq = timer_irq;
- clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
- (cns3xxx_cpu_clock() >> 3) * 1000000,
- 0xf, 0xffffffff);
-}
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
- u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
- u32 val;
-
- /* Clear the interrupt */
- val = readl(stat);
- writel(val & ~(1 << 2), stat);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-/*
- * Set up the clock source and clock events devices
- */
-static void __init __cns3xxx_timer_init(unsigned int timer_irq)
-{
- u32 val;
- u32 irq_mask;
-
- /*
- * Initialise to a known state (all timers off)
- */
-
- /* disable timer1 and timer2 */
- writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- /* stop free running timer3 */
- writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-
- /* timer1 */
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
-
- writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
- writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
-
- /* mask irq, non-mask timer1 overflow */
- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
- irq_mask &= ~(1 << 2);
- irq_mask |= 0x03;
- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-
- /* down counter */
- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- val |= (1 << 9);
- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- /* timer2 */
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
-
- /* mask irq */
- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-
- /* down counter */
- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- val |= (1 << 10);
- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- /* Make irqs happen for the system timer */
- if (request_irq(timer_irq, cns3xxx_timer_interrupt,
- IRQF_TIMER | IRQF_IRQPOLL, "timer", NULL))
- pr_err("Failed to request irq %d (timer)\n", timer_irq);
-
- cns3xxx_clockevents_init(timer_irq);
-}
-
-void __init cns3xxx_timer_init(void)
-{
- cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
-
- __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
-}
-
-#ifdef CONFIG_CACHE_L2X0
-
-void __init cns3xxx_l2x0_init(void)
-{
- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
- u32 val;
-
- if (WARN_ON(!base))
- return;
-
- /*
- * Tag RAM Control register
- *
- * bit[10:8] - 1 cycle of write accesses latency
- * bit[6:4] - 1 cycle of read accesses latency
- * bit[3:0] - 1 cycle of setup latency
- *
- * 1 cycle of latency for setup, read and write accesses
- */
- val = readl(base + L310_TAG_LATENCY_CTRL);
- val &= 0xfffff888;
- writel(val, base + L310_TAG_LATENCY_CTRL);
-
- /*
- * Data RAM Control register
- *
- * bit[10:8] - 1 cycles of write accesses latency
- * bit[6:4] - 1 cycles of read accesses latency
- * bit[3:0] - 1 cycle of setup latency
- *
- * 1 cycle of latency for setup, read and write accesses
- */
- val = readl(base + L310_DATA_LATENCY_CTRL);
- val &= 0xfffff888;
- writel(val, base + L310_DATA_LATENCY_CTRL);
-
- /* 32 KiB, 8-way, parity disable */
- l2x0_init(base, 0x00500000, 0xfe0f0fff);
-}
-
-#endif /* CONFIG_CACHE_L2X0 */
-
-static int csn3xxx_usb_power_on(struct platform_device *pdev)
-{
- /*
- * EHCI and OHCI share the same clock and power,
- * resetting twice would cause the 1st controller been reset.
- * Therefore only do power up at the first up device, and
- * power down at the last down device.
- *
- * Set USB AHB INCR length to 16
- */
- if (atomic_inc_return(&usb_pwr_ref) == 1) {
- cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
- cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
- cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
- __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
- MISC_CHIP_CONFIG_REG);
- }
-
- return 0;
-}
-
-static void csn3xxx_usb_power_off(struct platform_device *pdev)
-{
- /*
- * EHCI and OHCI share the same clock and power,
- * resetting twice would cause the 1st controller been reset.
- * Therefore only do power up at the first up device, and
- * power down at the last down device.
- */
- if (atomic_dec_return(&usb_pwr_ref) == 0)
- cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
-}
-
-static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
- .power_on = csn3xxx_usb_power_on,
- .power_off = csn3xxx_usb_power_off,
-};
-
-static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
- .num_ports = 1,
- .power_on = csn3xxx_usb_power_on,
- .power_off = csn3xxx_usb_power_off,
-};
-
-static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
- { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
- { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
- { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
- { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
- {},
-};
-
-static void __init cns3xxx_init(void)
-{
- struct device_node *dn;
-
- cns3xxx_l2x0_init();
-
- dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
- if (of_device_is_available(dn)) {
- u32 tmp;
-
- tmp = __raw_readl(MISC_SATA_POWER_MODE);
- tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
- tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
- __raw_writel(tmp, MISC_SATA_POWER_MODE);
-
- /* Enable SATA PHY */
- cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
- cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
-
- /* Enable SATA Clock */
- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
-
- /* De-Asscer SATA Reset */
- cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
- }
-
- dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
- if (of_device_is_available(dn)) {
- u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
- u32 gpioa_pins = __raw_readl(gpioa);
-
- /* MMC/SD pins share with GPIOA */
- gpioa_pins |= 0x1fff0004;
- __raw_writel(gpioa_pins, gpioa);
-
- cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
- cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
- }
-
- pm_power_off = cns3xxx_power_off;
-
- of_platform_default_populate(NULL, cns3xxx_auxdata, NULL);
-}
-
-static const char *const cns3xxx_dt_compat[] __initconst = {
- "cavium,cns3410",
- "cavium,cns3420",
- NULL,
-};
-
-DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
- .dt_compat = cns3xxx_dt_compat,
- .map_io = cns3xxx_map_io,
- .init_irq = cns3xxx_init_irq,
- .init_time = cns3xxx_timer_init,
- .init_machine = cns3xxx_init,
- .init_late = cns3xxx_pcie_init_late,
- .restart = cns3xxx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
deleted file mode 100644
index a96eabaea301..000000000000
--- a/arch/arm/mach-cns3xxx/core.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2004 ARM Limited
- * Copyright 2008 Cavium Networks
- */
-
-#ifndef __CNS3XXX_CORE_H
-#define __CNS3XXX_CORE_H
-
-#include <linux/reboot.h>
-
-extern void cns3xxx_timer_init(void);
-
-#ifdef CONFIG_CACHE_L2X0
-void __init cns3xxx_l2x0_init(void);
-#else
-static inline void cns3xxx_l2x0_init(void) {}
-#endif /* CONFIG_CACHE_L2X0 */
-
-#ifdef CONFIG_PCI
-extern void __init cns3xxx_pcie_init_late(void);
-#else
-static inline void __init cns3xxx_pcie_init_late(void) {}
-#endif
-
-void __init cns3xxx_map_io(void);
-void __init cns3xxx_init_irq(void);
-void cns3xxx_power_off(void);
-void cns3xxx_restart(enum reboot_mode, const char *);
-
-#endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
deleted file mode 100644
index 0f1ba8a0377d..000000000000
--- a/arch/arm/mach-cns3xxx/devices.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * CNS3xxx common devices
- *
- * Copyright 2008 Cavium Networks
- * Scott Shu
- * Copyright 2010 MontaVista Software, LLC.
- * Anton Vorontsov <avorontsov@mvista.com>
- */
-
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/compiler.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include "cns3xxx.h"
-#include "pm.h"
-#include "core.h"
-#include "devices.h"
-
-/*
- * AHCI
- */
-static struct resource cns3xxx_ahci_resource[] = {
- [0] = {
- .start = CNS3XXX_SATA2_BASE,
- .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_CNS3XXX_SATA,
- .end = IRQ_CNS3XXX_SATA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device cns3xxx_ahci_pdev = {
- .name = "ahci",
- .id = 0,
- .resource = cns3xxx_ahci_resource,
- .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
- .dev = {
- .dma_mask = &cns3xxx_ahci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init cns3xxx_ahci_init(void)
-{
- u32 tmp;
-
- tmp = __raw_readl(MISC_SATA_POWER_MODE);
- tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
- tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
- __raw_writel(tmp, MISC_SATA_POWER_MODE);
-
- /* Enable SATA PHY */
- cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
- cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
-
- /* Enable SATA Clock */
- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
-
- /* De-Asscer SATA Reset */
- cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
-
- platform_device_register(&cns3xxx_ahci_pdev);
-}
-
-/*
- * SDHCI
- */
-static struct resource cns3xxx_sdhci_resources[] = {
- [0] = {
- .start = CNS3XXX_SDIO_BASE,
- .end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_CNS3XXX_SDIO,
- .end = IRQ_CNS3XXX_SDIO,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device cns3xxx_sdhci_pdev = {
- .name = "sdhci-cns3xxx",
- .id = 0,
- .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
- .resource = cns3xxx_sdhci_resources,
-};
-
-void __init cns3xxx_sdhci_init(void)
-{
- u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
- u32 gpioa_pins = __raw_readl(gpioa);
-
- /* MMC/SD pins share with GPIOA */
- gpioa_pins |= 0x1fff0004;
- __raw_writel(gpioa_pins, gpioa);
-
- cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
- cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
-
- platform_device_register(&cns3xxx_sdhci_pdev);
-}
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
deleted file mode 100644
index ab16530d0116..000000000000
--- a/arch/arm/mach-cns3xxx/devices.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * CNS3xxx common devices
- *
- * Copyright 2008 Cavium Networks
- * Scott Shu
- * Copyright 2010 MontaVista Software, LLC.
- * Anton Vorontsov <avorontsov@mvista.com>
- */
-
-#ifndef __CNS3XXX_DEVICES_H_
-#define __CNS3XXX_DEVICES_H_
-
-void __init cns3xxx_ahci_init(void);
-void __init cns3xxx_sdhci_init(void);
-
-#endif /* __CNS3XXX_DEVICES_H_ */
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
deleted file mode 100644
index e92fbd679dfb..000000000000
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ /dev/null
@@ -1,290 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * PCI-E support for CNS3xxx
- *
- * Copyright 2008 Cavium Networks
- * Richard Liu <richard.liu@caviumnetworks.com>
- * Copyright 2010 MontaVista Software, LLC.
- * Anton Vorontsov <avorontsov@mvista.com>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/bug.h>
-#include <linux/pci.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/ptrace.h>
-#include <asm/mach/map.h>
-#include "cns3xxx.h"
-#include "core.h"
-
-struct cns3xxx_pcie {
- void __iomem *host_regs; /* PCI config registers for host bridge */
- void __iomem *cfg0_regs; /* PCI Type 0 config registers */
- void __iomem *cfg1_regs; /* PCI Type 1 config registers */
- unsigned int irqs[2];
- struct resource res_io;
- struct resource res_mem;
- int port;
- bool linked;
-};
-
-static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
-{
- struct pci_sys_data *root = sysdata;
-
- return root->private_data;
-}
-
-static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
-{
- return sysdata_to_cnspci(dev->sysdata);
-}
-
-static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
-{
- return sysdata_to_cnspci(bus->sysdata);
-}
-
-static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
- unsigned int devfn, int where)
-{
- struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
- int busno = bus->number;
- int slot = PCI_SLOT(devfn);
- void __iomem *base;
-
- /* If there is no link, just show the CNS PCI bridge. */
- if (!cnspci->linked && busno > 0)
- return NULL;
-
- /*
- * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
- * we still want to access it.
- * We place the host bridge on bus 0, and the directly connected
- * device on bus 1, slot 0.
- */
- if (busno == 0) { /* internal PCIe bus, host bridge device */
- if (devfn == 0) /* device# and function# are ignored by hw */
- base = cnspci->host_regs;
- else
- return NULL; /* no such device */
-
- } else if (busno == 1) { /* directly connected PCIe device */
- if (slot == 0) /* device# is ignored by hw */
- base = cnspci->cfg0_regs;
- else
- return NULL; /* no such device */
- } else /* remote PCI bus */
- base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
-
- return base + where + (devfn << 12);
-}
-
-static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- int ret;
- u32 mask = (0x1ull << (size * 8)) - 1;
- int shift = (where % 4) * 8;
-
- ret = pci_generic_config_read(bus, devfn, where, size, val);
-
- if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
- (where & 0xffc) == PCI_CLASS_REVISION)
- /*
- * RC's class is 0xb, but Linux PCI driver needs 0x604
- * for a PCIe bridge. So we must fixup the class code
- * to 0x604 here.
- */
- *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;
-
- return ret;
-}
-
-static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
-{
- struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
- struct resource *res_io = &cnspci->res_io;
- struct resource *res_mem = &cnspci->res_mem;
-
- BUG_ON(request_resource(&iomem_resource, res_io) ||
- request_resource(&iomem_resource, res_mem));
-
- pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
- pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
-
- return 1;
-}
-
-static struct pci_ops cns3xxx_pcie_ops = {
- .map_bus = cns3xxx_pci_map_bus,
- .read = cns3xxx_pci_read_config,
- .write = pci_generic_config_write,
-};
-
-static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
- int irq = cnspci->irqs[!!dev->bus->number];
-
- pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
- pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
- PCI_FUNC(dev->devfn), slot, pin, irq);
-
- return irq;
-}
-
-static struct cns3xxx_pcie cns3xxx_pcie[] = {
- [0] = {
- .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
- .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
- .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
- .res_io = {
- .name = "PCIe0 I/O space",
- .start = CNS3XXX_PCIE0_IO_BASE,
- .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
- .flags = IORESOURCE_IO,
- },
- .res_mem = {
- .name = "PCIe0 non-prefetchable",
- .start = CNS3XXX_PCIE0_MEM_BASE,
- .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
- .flags = IORESOURCE_MEM,
- },
- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
- .port = 0,
- },
- [1] = {
- .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
- .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
- .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
- .res_io = {
- .name = "PCIe1 I/O space",
- .start = CNS3XXX_PCIE1_IO_BASE,
- .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
- .flags = IORESOURCE_IO,
- },
- .res_mem = {
- .name = "PCIe1 non-prefetchable",
- .start = CNS3XXX_PCIE1_MEM_BASE,
- .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
- .flags = IORESOURCE_MEM,
- },
- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
- .port = 1,
- },
-};
-
-static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
-{
- int port = cnspci->port;
- u32 reg;
- unsigned long time;
-
- reg = __raw_readl(MISC_PCIE_CTRL(port));
- /*
- * Enable Application Request to 1, it will exit L1 automatically,
- * but when chip back, it will use another clock, still can use 0x1.
- */
- reg |= 0x3;
- __raw_writel(reg, MISC_PCIE_CTRL(port));
-
- pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
- pr_info("PCIe: Port[%d] Check data link layer...", port);
-
- time = jiffies;
- while (1) {
- reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
- if (reg & 0x1) {
- pr_info("Link up.\n");
- cnspci->linked = 1;
- break;
- } else if (time_after(jiffies, time + 50)) {
- pr_info("Device not found.\n");
- break;
- }
- }
-}
-
-static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
- int where, int size, u32 val)
-{
- void __iomem *base = cnspci->host_regs + (where & 0xffc);
- u32 v;
- u32 mask = (0x1ull << (size * 8)) - 1;
- int shift = (where % 4) * 8;
-
- v = readl_relaxed(base);
-
- v &= ~(mask << shift);
- v |= (val & mask) << shift;
-
- writel_relaxed(v, base);
- readl_relaxed(base);
-}
-
-static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
-{
- u16 mem_base = cnspci->res_mem.start >> 16;
- u16 mem_limit = cnspci->res_mem.end >> 16;
- u16 io_base = cnspci->res_io.start >> 16;
- u16 io_limit = cnspci->res_io.end >> 16;
-
- cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
- cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
- cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
- cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
- cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
- cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
- cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);
-
- if (!cnspci->linked)
- return;
-
- /* Set Device Max_Read_Request_Size to 128 byte */
- pcie_bus_config = PCIE_BUS_PEER2PEER;
-
- /* Disable PCIe0 Interrupt Mask INTA to INTD */
- __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));
-}
-
-static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
- struct pt_regs *regs)
-{
- if (fsr & (1 << 10))
- regs->ARM_pc += 4;
- return 0;
-}
-
-void __init cns3xxx_pcie_init_late(void)
-{
- int i;
- void *private_data;
- struct hw_pci hw_pci = {
- .nr_controllers = 1,
- .ops = &cns3xxx_pcie_ops,
- .setup = cns3xxx_pci_setup,
- .map_irq = cns3xxx_pcie_map_irq,
- .private_data = &private_data,
- };
-
- pcibios_min_io = 0;
- pcibios_min_mem = 0;
-
- hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
- "imprecise external abort");
-
- for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
- cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
- private_data = &cns3xxx_pcie[i];
- pci_common_init(&hw_pci);
- }
-
- pci_assign_unassigned_resources();
-}
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
deleted file mode 100644
index 72e8a7ec7a38..000000000000
--- a/arch/arm/mach-cns3xxx/pm.c
+++ /dev/null
@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright 2008 Cavium Networks
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/atomic.h>
-#include "cns3xxx.h"
-#include "pm.h"
-#include "core.h"
-
-void cns3xxx_pwr_clk_en(unsigned int block)
-{
- u32 reg = __raw_readl(PM_CLK_GATE_REG);
-
- reg |= (block & PM_CLK_GATE_REG_MASK);
- __raw_writel(reg, PM_CLK_GATE_REG);
-}
-EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
-
-void cns3xxx_pwr_clk_dis(unsigned int block)
-{
- u32 reg = __raw_readl(PM_CLK_GATE_REG);
-
- reg &= ~(block & PM_CLK_GATE_REG_MASK);
- __raw_writel(reg, PM_CLK_GATE_REG);
-}
-EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
-
-void cns3xxx_pwr_power_up(unsigned int block)
-{
- u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
-
- reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
- __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
-
- /* Wait for 300us for the PLL output clock locked. */
- udelay(300);
-};
-EXPORT_SYMBOL(cns3xxx_pwr_power_up);
-
-void cns3xxx_pwr_power_down(unsigned int block)
-{
- u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
-
- /* write '1' to power down */
- reg |= (block & CNS3XXX_PWR_PLL_ALL);
- __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
-};
-EXPORT_SYMBOL(cns3xxx_pwr_power_down);
-
-static void cns3xxx_pwr_soft_rst_force(unsigned int block)
-{
- u32 reg = __raw_readl(PM_SOFT_RST_REG);
-
- /*
- * bit 0, 28, 29 => program low to reset,
- * the other else program low and then high
- */
- if (block & 0x30000001) {
- reg &= ~(block & PM_SOFT_RST_REG_MASK);
- } else {
- reg &= ~(block & PM_SOFT_RST_REG_MASK);
- __raw_writel(reg, PM_SOFT_RST_REG);
- reg |= (block & PM_SOFT_RST_REG_MASK);
- }
-
- __raw_writel(reg, PM_SOFT_RST_REG);
-}
-
-void cns3xxx_pwr_soft_rst(unsigned int block)
-{
- static unsigned int soft_reset;
-
- if (soft_reset & block) {
- /* SPI/I2C/GPIO use the same block, reset once. */
- return;
- } else {
- soft_reset |= block;
- }
- cns3xxx_pwr_soft_rst_force(block);
-}
-EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
-
-void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
-{
- /*
- * To reset, we hit the on-board reset register
- * in the system FPGA.
- */
- cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
-}
-
-/*
- * cns3xxx_cpu_clock - return CPU/L2 clock
- * aclk: cpu clock/2
- * hclk: cpu clock/4
- * pclk: cpu clock/8
- */
-int cns3xxx_cpu_clock(void)
-{
- u32 reg = __raw_readl(PM_CLK_CTRL_REG);
- int cpu;
- int cpu_sel;
- int div_sel;
-
- cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
- div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
-
- cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
-
- return cpu;
-}
-EXPORT_SYMBOL(cns3xxx_cpu_clock);
-
-atomic_t usb_pwr_ref = ATOMIC_INIT(0);
-EXPORT_SYMBOL(usb_pwr_ref);
diff --git a/arch/arm/mach-cns3xxx/pm.h b/arch/arm/mach-cns3xxx/pm.h
deleted file mode 100644
index 61b73e59f0ff..000000000000
--- a/arch/arm/mach-cns3xxx/pm.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2004 ARM Limited
- * Copyright 2008 Cavium Networks
- */
-
-#ifndef __CNS3XXX_PM_H
-#define __CNS3XXX_PM_H
-
-#include <linux/atomic.h>
-
-void cns3xxx_pwr_clk_en(unsigned int block);
-void cns3xxx_pwr_clk_dis(unsigned int block);
-void cns3xxx_pwr_power_up(unsigned int block);
-void cns3xxx_pwr_power_down(unsigned int block);
-
-extern atomic_t usb_pwr_ref;
-
-#endif /* __CNS3XXX_PM_H */
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 1d3aef84287d..4316e1370627 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -3,6 +3,7 @@
menuconfig ARCH_DAVINCI
bool "TI DaVinci"
depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
select DAVINCI_TIMER
select ZONE_DMA
select PM_GENERIC_DOMAINS if PM
@@ -13,29 +14,10 @@ menuconfig ARCH_DAVINCI
if ARCH_DAVINCI
-config ARCH_DAVINCI_DMx
- bool
-
comment "DaVinci Core Type"
-config ARCH_DAVINCI_DM644x
- bool "DaVinci 644x based system"
- select DAVINCI_AINTC
- select ARCH_DAVINCI_DMx
-
-config ARCH_DAVINCI_DM355
- bool "DaVinci 355 based system"
- select DAVINCI_AINTC
- select ARCH_DAVINCI_DMx
-
-config ARCH_DAVINCI_DM646x
- bool "DaVinci 646x based system"
- select DAVINCI_AINTC
- select ARCH_DAVINCI_DMx
-
config ARCH_DAVINCI_DA830
bool "DA830/OMAP-L137/AM17x based system"
- depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
select ARCH_DAVINCI_DA8XX
# needed on silicon revs 1.0, 1.1:
select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
@@ -43,170 +25,11 @@ config ARCH_DAVINCI_DA830
config ARCH_DAVINCI_DA850
bool "DA850/OMAP-L138/AM18x based system"
- depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
- select ARCH_DAVINCI_DA8XX
select DAVINCI_CP_INTC
config ARCH_DAVINCI_DA8XX
bool
-config ARCH_DAVINCI_DM365
- bool "DaVinci 365 based system"
- select DAVINCI_AINTC
- select ARCH_DAVINCI_DMx
-
-comment "DaVinci Board Type"
-
-config MACH_DA8XX_DT
- bool "Support DA8XX platforms using device tree"
- default y
- depends on ARCH_DAVINCI_DA850
- select PINCTRL
- help
- Say y here to include support for TI DaVinci DA850 based using
- Flattened Device Tree. More information at Documentation/devicetree
-
-config MACH_DAVINCI_EVM
- bool "TI DM644x EVM"
- default ARCH_DAVINCI_DM644x
- depends on ARCH_DAVINCI_DM644x
- help
- Configure this option to specify the whether the board used
- for development is a DM644x EVM
-
-config MACH_SFFSDR
- bool "Lyrtech SFFSDR"
- depends on ARCH_DAVINCI_DM644x
- help
- Say Y here to select the Lyrtech Small Form Factor
- Software Defined Radio (SFFSDR) board.
-
-config MACH_NEUROS_OSD2
- bool "Neuros OSD2 Open Television Set Top Box"
- depends on ARCH_DAVINCI_DM644x
- help
- Configure this option to specify the whether the board used
- for development is a Neuros OSD2 Open Set Top Box.
-
-config MACH_DAVINCI_DM355_EVM
- bool "TI DM355 EVM"
- default ARCH_DAVINCI_DM355
- depends on ARCH_DAVINCI_DM355
- help
- Configure this option to specify the whether the board used
- for development is a DM355 EVM
-
-config MACH_DM355_LEOPARD
- bool "DM355 Leopard board"
- depends on ARCH_DAVINCI_DM355
- help
- Configure this option to specify the whether the board used
- for development is a DM355 Leopard board.
-
-config MACH_DAVINCI_DM6467_EVM
- bool "TI DM6467 EVM"
- default ARCH_DAVINCI_DM646x
- depends on ARCH_DAVINCI_DM646x
- select MACH_DAVINCI_DM6467TEVM
- help
- Configure this option to specify the whether the board used
- for development is a DM6467 EVM
-
-config MACH_DAVINCI_DM6467TEVM
- bool
-
-config MACH_DAVINCI_DM365_EVM
- bool "TI DM365 EVM"
- default ARCH_DAVINCI_DM365
- depends on ARCH_DAVINCI_DM365
- help
- Configure this option to specify whether the board used
- for development is a DM365 EVM
-
-config MACH_DAVINCI_DA830_EVM
- bool "TI DA830/OMAP-L137/AM17x Reference Platform"
- default ARCH_DAVINCI_DA830
- depends on ARCH_DAVINCI_DA830
- select GPIO_PCF857X if I2C
- help
- Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
-
-choice
- prompt "Select DA830/OMAP-L137/AM17x UI board peripheral"
- depends on MACH_DAVINCI_DA830_EVM
- help
- The presence of UI card on the DA830/OMAP-L137/AM17x EVM is
- detected automatically based on successful probe of the I2C
- based GPIO expander on that board. This option selected in this
- menu has an effect only in case of a successful UI card detection.
-
-config DA830_UI_LCD
- bool "LCD"
- help
- Say Y here to use the LCD as a framebuffer or simple character
- display.
-
-config DA830_UI_NAND
- bool "NAND flash"
- help
- Say Y here to use the NAND flash. Do not forget to setup
- the switch correctly.
-endchoice
-
-config MACH_DAVINCI_DA850_EVM
- bool "TI DA850/OMAP-L138/AM18x Reference Platform"
- default ARCH_DAVINCI_DA850
- depends on ARCH_DAVINCI_DA850
- help
- Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.
-
-choice
- prompt "Select peripherals connected to expander on UI board"
- depends on MACH_DAVINCI_DA850_EVM
- help
- The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x
- EVM is detected automatically based on successful probe of the I2C
- based GPIO expander on that card. This option selected in this
- menu has an effect only in case of a successful UI card detection.
-
-config DA850_UI_NONE
- bool "No peripheral is enabled"
- help
- Say Y if you do not want to enable any of the peripherals connected
- to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card
-
-config DA850_UI_RMII
- bool "RMII Ethernet PHY"
- help
- Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x
- EVM. This PHY is found on the UI daughter card that is supplied with
- the EVM.
- NOTE: Please take care while choosing this option, MII PHY will
- not be functional if RMII mode is selected.
-
-config DA850_UI_SD_VIDEO_PORT
- bool "Video Port Interface"
- help
- Say Y if you want to use Video Port Interface (VPIF) on the
- DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
- UI daughter card that is supplied with the EVM.
-
-endchoice
-
-config MACH_MITYOMAPL138
- bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
- depends on ARCH_DAVINCI_DA850
- help
- Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
- System on Module. Information on this SoM may be found at
- https://www.mitydsp.com
-
-config MACH_OMAPL138_HAWKBOARD
- bool "TI AM1808 / OMAPL-138 Hawkboard platform"
- depends on ARCH_DAVINCI_DA850
- help
- Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform .
-
config DAVINCI_MUX
bool "DAVINCI multiplexing support"
depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 58838a9de651..450883ea0e73 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -3,35 +3,17 @@
# Makefile for the linux kernel.
#
#
-
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-
+#
# Common objects
-obj-y := serial.o usb.o common.o sram.o
+obj-y := common.o sram.o devices-da8xx.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
# Chip specific
-obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o
-obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o
+obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o pdata-quirks.o
-# Board specific
-obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
-obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
-obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
-obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
-obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
-obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
-obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
-obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
-obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
-obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
-obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o
-obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
+obj-y += da8xx-dt.o
# Power Management
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot
deleted file mode 100644
index d36b251f325b..000000000000
--- a/arch/arm/mach-davinci/Makefile.boot
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX) += 0xc0008000
-params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0000100
-initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0800000
-
-zreladdr-$(CONFIG_ARCH_DAVINCI_DMx) += 0x80008000
-params_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80000100
-initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80800000
diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
deleted file mode 100644
index d0ecd1d0f084..000000000000
--- a/arch/arm/mach-davinci/asp.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * TI DaVinci Audio definitions
- */
-#ifndef __ASM_ARCH_DAVINCI_ASP_H
-#define __ASM_ARCH_DAVINCI_ASP_H
-
-/* Bases of dm644x and dm355 register banks */
-#define DAVINCI_ASP0_BASE 0x01E02000
-#define DAVINCI_ASP1_BASE 0x01E04000
-
-/* Bases of dm365 register banks */
-#define DAVINCI_DM365_ASP0_BASE 0x01D02000
-
-/* Bases of dm646x register banks */
-#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
-#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
-
-/* Bases of da850/da830 McASP0 register banks */
-#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
-
-/* Bases of da830 McASP1 register banks */
-#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
-
-/* Bases of da830 McASP2 register banks */
-#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000
-
-/* EDMA channels of dm644x and dm355 */
-#define DAVINCI_DMA_ASP0_TX 2
-#define DAVINCI_DMA_ASP0_RX 3
-#define DAVINCI_DMA_ASP1_TX 8
-#define DAVINCI_DMA_ASP1_RX 9
-
-/* EDMA channels of dm646x */
-#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
-#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
-#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
-
-/* EDMA channels of da850/da830 McASP0 */
-#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
-#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
-
-/* EDMA channels of da830 McASP1 */
-#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
-#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
-
-/* EDMA channels of da830 McASP2 */
-#define DAVINCI_DA830_DMA_MCASP2_AREVT 4
-#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
-
-/* Interrupts */
-#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
-#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
-#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
-#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
-
-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
deleted file mode 100644
index 823c9cc98f18..000000000000
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ /dev/null
@@ -1,694 +0,0 @@
-/*
- * TI DA830/OMAP L137 EVM board
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c
- *
- * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/pcf857x.h>
-#include <linux/property.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/nvmem-provider.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/mux.h>
-#include <mach/da8xx.h>
-
-#include "irqs.h"
-
-#define DA830_EVM_PHY_ID ""
-/*
- * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
- */
-#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15)
-#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4)
-
-static const short da830_evm_usb11_pins[] = {
- DA830_GPIO1_15, DA830_GPIO2_4,
- -1
-};
-
-static struct regulator_consumer_supply da830_evm_usb_supplies[] = {
- REGULATOR_SUPPLY("vbus", NULL),
-};
-
-static struct regulator_init_data da830_evm_usb_vbus_data = {
- .consumer_supplies = da830_evm_usb_supplies,
- .num_consumer_supplies = ARRAY_SIZE(da830_evm_usb_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config da830_evm_usb_vbus = {
- .supply_name = "vbus",
- .microvolts = 33000000,
- .init_data = &da830_evm_usb_vbus_data,
-};
-
-static struct platform_device da830_evm_usb_vbus_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &da830_evm_usb_vbus,
- },
-};
-
-static struct gpiod_lookup_table da830_evm_usb_oc_gpio_lookup = {
- .dev_id = "ohci-da8xx",
- .table = {
- GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table da830_evm_usb_vbus_gpio_lookup = {
- .dev_id = "reg-fixed-voltage.0",
- .table = {
- GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, NULL, 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table *da830_evm_usb_gpio_lookups[] = {
- &da830_evm_usb_oc_gpio_lookup,
- &da830_evm_usb_vbus_gpio_lookup,
-};
-
-static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
- /* TPS2065 switch @ 5V */
- .potpgt = (3 + 1) / 2, /* 3 ms max */
-};
-
-static __init void da830_evm_usb_init(void)
-{
- int ret;
-
- ret = da8xx_register_usb_phy_clocks();
- if (ret)
- pr_warn("%s: USB PHY CLK registration failed: %d\n",
- __func__, ret);
-
- gpiod_add_lookup_tables(da830_evm_usb_gpio_lookups,
- ARRAY_SIZE(da830_evm_usb_gpio_lookups));
-
- ret = da8xx_register_usb_phy();
- if (ret)
- pr_warn("%s: USB PHY registration failed: %d\n",
- __func__, ret);
-
- ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
- if (ret)
- pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret);
- else {
- /*
- * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
- * with the power on to power good time of 3 ms.
- */
- ret = da8xx_register_usb20(1000, 3);
- if (ret)
- pr_warn("%s: USB 2.0 registration failed: %d\n",
- __func__, ret);
- }
-
- ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
- if (ret) {
- pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
- return;
- }
-
- ret = platform_device_register(&da830_evm_usb_vbus_device);
- if (ret) {
- pr_warn("%s: Unable to register the vbus supply\n", __func__);
- return;
- }
-
- ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
- if (ret)
- pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
-}
-
-static const short da830_evm_mcasp1_pins[] = {
- DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
- DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
- DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10,
- DA830_AXR1_11,
- -1
-};
-
-static u8 da830_iis_serializer_direction[] = {
- RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
-};
-
-static struct snd_platform_data da830_evm_snd_data = {
- .tx_dma_offset = 0x2000,
- .rx_dma_offset = 0x2000,
- .op_mode = DAVINCI_MCASP_IIS_MODE,
- .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction),
- .tdm_slots = 2,
- .serial_dir = da830_iis_serializer_direction,
- .asp_chan_q = EVENTQ_0,
- .version = MCASP_VERSION_2,
- .txnumevt = 1,
- .rxnumevt = 1,
-};
-
-/*
- * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS.
- */
-static const short da830_evm_mmc_sd_pins[] = {
- DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
- DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
- DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
- DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2,
- -1
-};
-
-#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
-#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
-
-static struct gpiod_lookup_table mmc_gpios_table = {
- .dev_id = "da830-mmc.0",
- .table = {
- /* gpio chip 1 contains gpio range 32-63 */
- GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd",
- GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp",
- GPIO_ACTIVE_LOW),
- { }
- },
-};
-
-static struct davinci_mmc_config da830_evm_mmc_config = {
- .wires = 8,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static inline void da830_evm_init_mmc(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
- if (ret) {
- pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret);
- return;
- }
-
- gpiod_add_lookup_table(&mmc_gpios_table);
-
- ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
- if (ret) {
- pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret);
- gpiod_remove_lookup_table(&mmc_gpios_table);
- }
-}
-
-#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
-
-#ifdef CONFIG_DA830_UI_NAND
-static struct mtd_partition da830_evm_nand_partitions[] = {
- /* bootloader (U-Boot, etc) in first sector */
- [0] = {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next sector */
- [1] = {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* kernel */
- [2] = {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0,
- },
- /* file system */
- [3] = {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
-};
-
-/* flash bbt descriptors */
-static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' };
-static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' };
-
-static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
- NAND_BBT_WRITE | NAND_BBT_2BIT |
- NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 2,
- .len = 4,
- .veroffs = 16,
- .maxblocks = 4,
- .pattern = da830_evm_nand_bbt_pattern
-};
-
-static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
- NAND_BBT_WRITE | NAND_BBT_2BIT |
- NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 2,
- .len = 4,
- .veroffs = 16,
- .maxblocks = 4,
- .pattern = da830_evm_nand_mirror_pattern
-};
-
-static struct davinci_aemif_timing da830_evm_nandflash_timing = {
- .wsetup = 24,
- .wstrobe = 21,
- .whold = 14,
- .rsetup = 19,
- .rstrobe = 50,
- .rhold = 0,
- .ta = 20,
-};
-
-static struct davinci_nand_pdata da830_evm_nand_pdata = {
- .core_chipsel = 1,
- .parts = da830_evm_nand_partitions,
- .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
- .bbt_td = &da830_evm_nand_bbt_main_descr,
- .bbt_md = &da830_evm_nand_bbt_mirror_descr,
- .timing = &da830_evm_nandflash_timing,
-};
-
-static struct resource da830_evm_nand_resources[] = {
- [0] = { /* First memory resource is NAND I/O window */
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* Second memory resource is AEMIF control registers */
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da830_evm_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 1,
- .dev = {
- .platform_data = &da830_evm_nand_pdata,
- },
- .num_resources = ARRAY_SIZE(da830_evm_nand_resources),
- .resource = da830_evm_nand_resources,
- },
-};
-
-static struct resource da830_evm_aemif_resource[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data da830_evm_aemif_abus_data[] = {
- {
- .cs = 3,
- },
-};
-
-static struct aemif_platform_data da830_evm_aemif_pdata = {
- .abus_data = da830_evm_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(da830_evm_aemif_abus_data),
- .sub_devices = da830_evm_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(da830_evm_aemif_devices),
- .cs_offset = 2,
-};
-
-static struct platform_device da830_evm_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &da830_evm_aemif_pdata,
- },
- .resource = da830_evm_aemif_resource,
- .num_resources = ARRAY_SIZE(da830_evm_aemif_resource),
-};
-
-/*
- * UI board NAND/NOR flashes only use 8-bit data bus.
- */
-static const short da830_evm_emif25_pins[] = {
- DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
- DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
- DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
- DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
- DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
- DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
- DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
- -1
-};
-
-static inline void da830_evm_init_nand(int mux_mode)
-{
- int ret;
-
- if (HAS_MMC) {
- pr_warn("WARNING: both MMC/SD and NAND are enabled, but they share AEMIF pins\n"
- "\tDisable MMC/SD for NAND support\n");
- return;
- }
-
- ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
- if (ret)
- pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret);
-
- ret = platform_device_register(&da830_evm_aemif_device);
- if (ret)
- pr_warn("%s: AEMIF device not registered\n", __func__);
-
- gpio_direction_output(mux_mode, 1);
-}
-#else
-static inline void da830_evm_init_nand(int mux_mode) { }
-#endif
-
-#ifdef CONFIG_DA830_UI_LCD
-static inline void da830_evm_init_lcdc(int mux_mode)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
- if (ret)
- pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata);
- if (ret)
- pr_warn("%s: lcd setup failed: %d\n", __func__, ret);
-
- gpio_direction_output(mux_mode, 0);
-}
-#else
-static inline void da830_evm_init_lcdc(int mux_mode) { }
-#endif
-
-static struct nvmem_cell_info da830_evm_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x7f00,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table da830_evm_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = da830_evm_nvmem_cells,
- .ncells = ARRAY_SIZE(da830_evm_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry da830_evm_i2c_eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 64),
- { }
-};
-
-static const struct software_node da830_evm_i2c_eeprom_node = {
- .properties = da830_evm_i2c_eeprom_properties,
-};
-
-static int __init da830_evm_ui_expander_setup(struct i2c_client *client,
- int gpio, unsigned ngpio, void *context)
-{
- gpio_request(gpio + 6, "UI MUX_MODE");
-
- /* Drive mux mode low to match the default without UI card */
- gpio_direction_output(gpio + 6, 0);
-
- da830_evm_init_lcdc(gpio + 6);
-
- da830_evm_init_nand(gpio + 6);
-
- return 0;
-}
-
-static int da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio,
- unsigned ngpio, void *context)
-{
- gpio_free(gpio + 6);
- return 0;
-}
-
-static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = {
- .gpio_base = DAVINCI_N_GPIO,
- .setup = da830_evm_ui_expander_setup,
- .teardown = da830_evm_ui_expander_teardown,
-};
-
-static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
- {
- I2C_BOARD_INFO("24c256", 0x50),
- .swnode = &da830_evm_i2c_eeprom_node,
- },
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- },
- {
- I2C_BOARD_INFO("pcf8574", 0x3f),
- .platform_data = &da830_evm_ui_expander_info,
- },
-};
-
-static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
- .bus_freq = 100, /* kHz */
- .bus_delay = 0, /* usec */
-};
-
-/*
- * The following EDMA channels/slots are not being used by drivers (for
- * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence
- * they are being reserved for codecs on the DSP side.
- */
-static const s16 da830_dma_rsv_chans[][2] = {
- /* (offset, number) */
- { 8, 2},
- {12, 2},
- {24, 4},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da830_dma_rsv_slots[][2] = {
- /* (offset, number) */
- { 8, 2},
- {12, 2},
- {24, 4},
- {30, 26},
- {-1, -1}
-};
-
-static struct edma_rsv_info da830_edma_rsv[] = {
- {
- .rsv_chans = da830_dma_rsv_chans,
- .rsv_slots = da830_dma_rsv_slots,
- },
-};
-
-static struct mtd_partition da830evm_spiflash_part[] = {
- [0] = {
- .name = "DSP-UBL",
- .offset = 0,
- .size = SZ_8K,
- .mask_flags = MTD_WRITEABLE,
- },
- [1] = {
- .name = "ARM-UBL",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_16K + SZ_8K,
- .mask_flags = MTD_WRITEABLE,
- },
- [2] = {
- .name = "U-Boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_256K - SZ_32K,
- .mask_flags = MTD_WRITEABLE,
- },
- [3] = {
- .name = "U-Boot-Environment",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_16K,
- .mask_flags = 0,
- },
- [4] = {
- .name = "Kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct flash_platform_data da830evm_spiflash_data = {
- .name = "m25p80",
- .parts = da830evm_spiflash_part,
- .nr_parts = ARRAY_SIZE(da830evm_spiflash_part),
- .type = "w25x32",
-};
-
-static struct davinci_spi_config da830evm_spiflash_cfg = {
- .io_type = SPI_IO_TYPE_DMA,
- .c2tdelay = 8,
- .t2cdelay = 8,
-};
-
-static struct spi_board_info da830evm_spi_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &da830evm_spiflash_data,
- .controller_data = &da830evm_spiflash_cfg,
- .mode = SPI_MODE_0,
- .max_speed_hz = 30000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static __init void da830_evm_init(void)
-{
- struct davinci_soc_info *soc_info = &davinci_soc_info;
- int ret;
-
- da830_register_clocks();
-
- ret = da830_register_gpio();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- ret = da830_register_edma(da830_edma_rsv);
- if (ret)
- pr_warn("%s: edma registration failed: %d\n", __func__, ret);
-
- ret = davinci_cfg_reg_list(da830_i2c0_pins);
- if (ret)
- pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata);
- if (ret)
- pr_warn("%s: i2c0 registration failed: %d\n", __func__, ret);
-
- da830_evm_usb_init();
-
- soc_info->emac_pdata->rmii_en = 1;
- soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID;
-
- ret = davinci_cfg_reg_list(da830_cpgmac_pins);
- if (ret)
- pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("%s: emac registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("%s: watchdog registration failed: %d\n",
- __func__, ret);
-
- davinci_serial_init(da8xx_serial_device);
-
- nvmem_add_cell_table(&da830_evm_nvmem_cell_table);
- nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1);
-
- i2c_register_board_info(1, da830_evm_i2c_devices,
- ARRAY_SIZE(da830_evm_i2c_devices));
-
- ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
- if (ret)
- pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret);
-
- da8xx_register_mcasp(1, &da830_evm_snd_data);
-
- da830_evm_init_mmc();
-
- ret = da8xx_register_rtc();
- if (ret)
- pr_warn("%s: rtc setup failed: %d\n", __func__, ret);
-
- ret = spi_register_board_info(da830evm_spi_info,
- ARRAY_SIZE(da830evm_spi_info));
- if (ret)
- pr_warn("%s: spi info registration failed: %d\n",
- __func__, ret);
-
- ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
- if (ret)
- pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret);
-
- regulator_has_full_constraints();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init da830_evm_console_init(void)
-{
- if (!machine_is_davinci_da830_evm())
- return 0;
-
- return add_preferred_console("ttyS", 2, "115200");
-}
-console_initcall(da830_evm_console_init);
-#endif
-
-static void __init da830_evm_map_io(void)
-{
- da830_init();
-}
-
-MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
- .atag_offset = 0x100,
- .map_io = da830_evm_map_io,
- .init_irq = da830_init_irq,
- .init_time = da830_init_time,
- .init_machine = da830_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
deleted file mode 100644
index 428012687a80..000000000000
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ /dev/null
@@ -1,1555 +0,0 @@
-/*
- * TI DA850/OMAP-L138 EVM board
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Derived from: arch/arm/mach-davinci/board-da830-evm.c
- * Original Copyrights follow:
- *
- * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio/machine.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/leds.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/input.h>
-#include <linux/input/tps6507x-ts.h>
-#include <linux/mfd/tps6507x.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/nvmem-provider.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_data/uio_pruss.h>
-#include <linux/property.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/tps6507x.h>
-#include <linux/regulator/fixed.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <mach/common.h>
-#include <mach/da8xx.h>
-#include <mach/mux.h>
-
-#include "irqs.h"
-#include "sram.h"
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/system_info.h>
-
-#include <media/i2c/tvp514x.h>
-#include <media/i2c/adv7343.h>
-
-#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
-#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
-#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
-
-#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
-
-static struct mtd_partition da850evm_spiflash_part[] = {
- [0] = {
- .name = "UBL",
- .offset = 0,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [1] = {
- .name = "U-Boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- [2] = {
- .name = "U-Boot-Env",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [3] = {
- .name = "Kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M + SZ_512K,
- .mask_flags = 0,
- },
- [4] = {
- .name = "Filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- },
- [5] = {
- .name = "MAC-Address",
- .offset = SZ_8M - SZ_64K,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
-};
-
-static struct nvmem_cell_info da850evm_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x0,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table da850evm_nvmem_cell_table = {
- /*
- * The nvmem name differs from the partition name because of the
- * internal works of the nvmem framework.
- */
- .nvmem_name = "MAC-Address0",
- .cells = da850evm_nvmem_cells,
- .ncells = ARRAY_SIZE(da850evm_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = {
- .nvmem_name = "MAC-Address0",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static struct flash_platform_data da850evm_spiflash_data = {
- .name = "m25p80",
- .parts = da850evm_spiflash_part,
- .nr_parts = ARRAY_SIZE(da850evm_spiflash_part),
- .type = "m25p64",
-};
-
-static struct davinci_spi_config da850evm_spiflash_cfg = {
- .io_type = SPI_IO_TYPE_DMA,
- .c2tdelay = 8,
- .t2cdelay = 8,
-};
-
-static struct spi_board_info da850evm_spi_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &da850evm_spiflash_data,
- .controller_data = &da850evm_spiflash_cfg,
- .mode = SPI_MODE_0,
- .max_speed_hz = 30000000,
- .bus_num = 1,
- .chip_select = 0,
- },
-};
-
-static struct mtd_partition da850_evm_norflash_partition[] = {
- {
- .name = "bootloaders + env",
- .offset = 0,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0,
- },
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct physmap_flash_data da850_evm_norflash_data = {
- .width = 2,
- .parts = da850_evm_norflash_partition,
- .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
-};
-
-static struct resource da850_evm_norflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS2_BASE,
- .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
- * (128K blocks). It may be used instead of the (default) SPI flash
- * to boot, using TI's tools to install the secondary boot loader
- * (UBL) and U-Boot.
- */
-static struct mtd_partition da850_evm_nandflash_partition[] = {
- {
- .name = "u-boot env",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "UBL",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "kernel",
- .offset = 0x200000,
- .size = SZ_2M,
- .mask_flags = 0,
- },
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct davinci_aemif_timing da850_evm_nandflash_timing = {
- .wsetup = 24,
- .wstrobe = 21,
- .whold = 14,
- .rsetup = 19,
- .rstrobe = 50,
- .rhold = 0,
- .ta = 20,
-};
-
-static struct davinci_nand_pdata da850_evm_nandflash_data = {
- .core_chipsel = 1,
- .parts = da850_evm_nandflash_partition,
- .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
- .timing = &da850_evm_nandflash_timing,
-};
-
-static struct resource da850_evm_nandflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource da850_evm_aemif_resource[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
- {
- .cs = 3,
- }
-};
-
-static struct platform_device da850_evm_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 1,
- .dev = {
- .platform_data = &da850_evm_nandflash_data,
- },
- .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
- .resource = da850_evm_nandflash_resource,
- },
- {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &da850_evm_norflash_data,
- },
- .num_resources = 1,
- .resource = da850_evm_norflash_resource,
- }
-};
-
-static struct aemif_platform_data da850_evm_aemif_pdata = {
- .cs_offset = 2,
- .abus_data = da850_evm_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
- .sub_devices = da850_evm_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices),
-};
-
-static struct platform_device da850_evm_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &da850_evm_aemif_pdata,
- },
- .resource = da850_evm_aemif_resource,
- .num_resources = ARRAY_SIZE(da850_evm_aemif_resource),
-};
-
-static const short da850_evm_nand_pins[] = {
- DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
- DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
- DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
- DA850_NEMA_WE, DA850_NEMA_OE,
- -1
-};
-
-static const short da850_evm_nor_pins[] = {
- DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
- DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
- DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
- DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
- DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
- DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
- DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
- DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
- DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
- DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
- DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
- DA850_EMA_A_22, DA850_EMA_A_23,
- -1
-};
-
-#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
-
-static inline void da850_evm_setup_nor_nand(void)
-{
- int ret = 0;
-
- if (!HAS_MMC) {
- ret = davinci_cfg_reg_list(da850_evm_nand_pins);
- if (ret)
- pr_warn("%s: NAND mux setup failed: %d\n",
- __func__, ret);
-
- ret = davinci_cfg_reg_list(da850_evm_nor_pins);
- if (ret)
- pr_warn("%s: NOR mux setup failed: %d\n",
- __func__, ret);
-
- ret = platform_device_register(&da850_evm_aemif_device);
- if (ret)
- pr_warn("%s: registering aemif failed: %d\n",
- __func__, ret);
- }
-}
-
-#ifdef CONFIG_DA850_UI_RMII
-static inline void da850_evm_setup_emac_rmii(int rmii_sel)
-{
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- soc_info->emac_pdata->rmii_en = 1;
- gpio_set_value_cansleep(rmii_sel, 0);
-}
-#else
-static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
-#endif
-
-
-#define DA850_KEYS_DEBOUNCE_MS 10
-/*
- * At 200ms polling interval it is possible to miss an
- * event by tapping very lightly on the push button but most
- * pushes do result in an event; longer intervals require the
- * user to hold the button whereas shorter intervals require
- * more CPU time for polling.
- */
-#define DA850_GPIO_KEYS_POLL_MS 200
-
-enum da850_evm_ui_exp_pins {
- DA850_EVM_UI_EXP_SEL_C = 5,
- DA850_EVM_UI_EXP_SEL_B,
- DA850_EVM_UI_EXP_SEL_A,
- DA850_EVM_UI_EXP_PB8,
- DA850_EVM_UI_EXP_PB7,
- DA850_EVM_UI_EXP_PB6,
- DA850_EVM_UI_EXP_PB5,
- DA850_EVM_UI_EXP_PB4,
- DA850_EVM_UI_EXP_PB3,
- DA850_EVM_UI_EXP_PB2,
- DA850_EVM_UI_EXP_PB1,
-};
-
-static const char * const da850_evm_ui_exp[] = {
- [DA850_EVM_UI_EXP_SEL_C] = "sel_c",
- [DA850_EVM_UI_EXP_SEL_B] = "sel_b",
- [DA850_EVM_UI_EXP_SEL_A] = "sel_a",
- [DA850_EVM_UI_EXP_PB8] = "pb8",
- [DA850_EVM_UI_EXP_PB7] = "pb7",
- [DA850_EVM_UI_EXP_PB6] = "pb6",
- [DA850_EVM_UI_EXP_PB5] = "pb5",
- [DA850_EVM_UI_EXP_PB4] = "pb4",
- [DA850_EVM_UI_EXP_PB3] = "pb3",
- [DA850_EVM_UI_EXP_PB2] = "pb2",
- [DA850_EVM_UI_EXP_PB1] = "pb1",
-};
-
-#define DA850_N_UI_PB 8
-
-static struct gpio_keys_button da850_evm_ui_keys[] = {
- [0 ... DA850_N_UI_PB - 1] = {
- .type = EV_KEY,
- .active_low = 1,
- .wakeup = 0,
- .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
- .code = -1, /* assigned at runtime */
- .gpio = -1, /* assigned at runtime */
- .desc = NULL, /* assigned at runtime */
- },
-};
-
-static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
- .buttons = da850_evm_ui_keys,
- .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
- .poll_interval = DA850_GPIO_KEYS_POLL_MS,
-};
-
-static struct platform_device da850_evm_ui_keys_device = {
- .name = "gpio-keys-polled",
- .id = 0,
- .dev = {
- .platform_data = &da850_evm_ui_keys_pdata
- },
-};
-
-static void da850_evm_ui_keys_init(unsigned gpio)
-{
- int i;
- struct gpio_keys_button *button;
-
- for (i = 0; i < DA850_N_UI_PB; i++) {
- button = &da850_evm_ui_keys[i];
- button->code = KEY_F8 - i;
- button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
- button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
- }
-}
-
-#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
-static inline void da850_evm_setup_video_port(int video_sel)
-{
- gpio_set_value_cansleep(video_sel, 0);
-}
-#else
-static inline void da850_evm_setup_video_port(int video_sel) { }
-#endif
-
-static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
- unsigned ngpio, void *c)
-{
- int sel_a, sel_b, sel_c, ret;
-
- sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
- sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
- sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
-
- ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
- if (ret) {
- pr_warn("Cannot open UI expander pin %d\n", sel_a);
- goto exp_setup_sela_fail;
- }
-
- ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
- if (ret) {
- pr_warn("Cannot open UI expander pin %d\n", sel_b);
- goto exp_setup_selb_fail;
- }
-
- ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
- if (ret) {
- pr_warn("Cannot open UI expander pin %d\n", sel_c);
- goto exp_setup_selc_fail;
- }
-
- /* deselect all functionalities */
- gpio_direction_output(sel_a, 1);
- gpio_direction_output(sel_b, 1);
- gpio_direction_output(sel_c, 1);
-
- da850_evm_ui_keys_init(gpio);
- ret = platform_device_register(&da850_evm_ui_keys_device);
- if (ret) {
- pr_warn("Could not register UI GPIO expander push-buttons");
- goto exp_setup_keys_fail;
- }
-
- pr_info("DA850/OMAP-L138 EVM UI card detected\n");
-
- da850_evm_setup_nor_nand();
-
- da850_evm_setup_emac_rmii(sel_a);
-
- da850_evm_setup_video_port(sel_c);
-
- return 0;
-
-exp_setup_keys_fail:
- gpio_free(sel_c);
-exp_setup_selc_fail:
- gpio_free(sel_b);
-exp_setup_selb_fail:
- gpio_free(sel_a);
-exp_setup_sela_fail:
- return ret;
-}
-
-static int da850_evm_ui_expander_teardown(struct i2c_client *client,
- unsigned gpio, unsigned ngpio, void *c)
-{
- platform_device_unregister(&da850_evm_ui_keys_device);
-
- /* deselect all functionalities */
- gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
- gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
- gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
-
- gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
- gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
- gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
-
- return 0;
-}
-
-/* assign the baseboard expander's GPIOs after the UI board's */
-#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
-#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
-
-enum da850_evm_bb_exp_pins {
- DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
- DA850_EVM_BB_EXP_SW_RST,
- DA850_EVM_BB_EXP_TP_23,
- DA850_EVM_BB_EXP_TP_22,
- DA850_EVM_BB_EXP_TP_21,
- DA850_EVM_BB_EXP_USER_PB1,
- DA850_EVM_BB_EXP_USER_LED2,
- DA850_EVM_BB_EXP_USER_LED1,
- DA850_EVM_BB_EXP_USER_SW1,
- DA850_EVM_BB_EXP_USER_SW2,
- DA850_EVM_BB_EXP_USER_SW3,
- DA850_EVM_BB_EXP_USER_SW4,
- DA850_EVM_BB_EXP_USER_SW5,
- DA850_EVM_BB_EXP_USER_SW6,
- DA850_EVM_BB_EXP_USER_SW7,
- DA850_EVM_BB_EXP_USER_SW8
-};
-
-static const char * const da850_evm_bb_exp[] = {
- [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en",
- [DA850_EVM_BB_EXP_SW_RST] = "sw_rst",
- [DA850_EVM_BB_EXP_TP_23] = "tp_23",
- [DA850_EVM_BB_EXP_TP_22] = "tp_22",
- [DA850_EVM_BB_EXP_TP_21] = "tp_21",
- [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1",
- [DA850_EVM_BB_EXP_USER_LED2] = "user_led2",
- [DA850_EVM_BB_EXP_USER_LED1] = "user_led1",
- [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1",
- [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2",
- [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3",
- [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4",
- [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5",
- [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6",
- [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7",
- [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8",
-};
-
-#define DA850_N_BB_USER_SW 8
-
-static struct gpio_keys_button da850_evm_bb_keys[] = {
- [0] = {
- .type = EV_KEY,
- .active_low = 1,
- .wakeup = 0,
- .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
- .code = KEY_PROG1,
- .desc = NULL, /* assigned at runtime */
- .gpio = -1, /* assigned at runtime */
- },
- [1 ... DA850_N_BB_USER_SW] = {
- .type = EV_SW,
- .active_low = 1,
- .wakeup = 0,
- .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
- .code = -1, /* assigned at runtime */
- .desc = NULL, /* assigned at runtime */
- .gpio = -1, /* assigned at runtime */
- },
-};
-
-static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
- .buttons = da850_evm_bb_keys,
- .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
- .poll_interval = DA850_GPIO_KEYS_POLL_MS,
-};
-
-static struct platform_device da850_evm_bb_keys_device = {
- .name = "gpio-keys-polled",
- .id = 1,
- .dev = {
- .platform_data = &da850_evm_bb_keys_pdata
- },
-};
-
-static void da850_evm_bb_keys_init(unsigned gpio)
-{
- int i;
- struct gpio_keys_button *button;
-
- button = &da850_evm_bb_keys[0];
- button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
- button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
-
- for (i = 0; i < DA850_N_BB_USER_SW; i++) {
- button = &da850_evm_bb_keys[i + 1];
- button->code = SW_LID + i;
- button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
- button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
- }
-}
-
-static struct gpio_led da850_evm_bb_leds[] = {
- {
- .name = "user_led2",
- },
- {
- .name = "user_led1",
- },
-};
-
-static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
- .leds = da850_evm_bb_leds,
- .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
-};
-
-static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = {
- .dev_id = "leds-gpio",
- .table = {
- GPIO_LOOKUP_IDX("i2c-bb-expander",
- DA850_EVM_BB_EXP_USER_LED2, NULL,
- 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("i2c-bb-expander",
- DA850_EVM_BB_EXP_USER_LED2 + 1, NULL,
- 1, GPIO_ACTIVE_LOW),
-
- { },
- },
-};
-
-static struct platform_device da850_evm_bb_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &da850_evm_bb_leds_pdata
- }
-};
-
-static int da850_evm_bb_expander_setup(struct i2c_client *client,
- unsigned gpio, unsigned ngpio,
- void *c)
-{
- int ret;
-
- /*
- * Register the switches and pushbutton on the baseboard as a gpio-keys
- * device.
- */
- da850_evm_bb_keys_init(gpio);
- ret = platform_device_register(&da850_evm_bb_keys_device);
- if (ret) {
- pr_warn("Could not register baseboard GPIO expander keys");
- goto io_exp_setup_sw_fail;
- }
-
- gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table);
- ret = platform_device_register(&da850_evm_bb_leds_device);
- if (ret) {
- pr_warn("Could not register baseboard GPIO expander LEDs");
- goto io_exp_setup_leds_fail;
- }
-
- return 0;
-
-io_exp_setup_leds_fail:
- platform_device_unregister(&da850_evm_bb_keys_device);
-io_exp_setup_sw_fail:
- return ret;
-}
-
-static int da850_evm_bb_expander_teardown(struct i2c_client *client,
- unsigned gpio, unsigned ngpio, void *c)
-{
- platform_device_unregister(&da850_evm_bb_leds_device);
- platform_device_unregister(&da850_evm_bb_keys_device);
-
- return 0;
-}
-
-static struct pca953x_platform_data da850_evm_ui_expander_info = {
- .gpio_base = DAVINCI_N_GPIO,
- .setup = da850_evm_ui_expander_setup,
- .teardown = da850_evm_ui_expander_teardown,
- .names = da850_evm_ui_exp,
-};
-
-static struct pca953x_platform_data da850_evm_bb_expander_info = {
- .gpio_base = DA850_BB_EXPANDER_GPIO_BASE,
- .setup = da850_evm_bb_expander_setup,
- .teardown = da850_evm_bb_expander_teardown,
- .names = da850_evm_bb_exp,
-};
-
-static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- },
- {
- I2C_BOARD_INFO("tca6416", 0x20),
- .dev_name = "ui-expander",
- .platform_data = &da850_evm_ui_expander_info,
- },
- {
- I2C_BOARD_INFO("tca6416", 0x21),
- .dev_name = "bb-expander",
- .platform_data = &da850_evm_bb_expander_info,
- },
-};
-
-static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
- .bus_freq = 100, /* kHz */
- .bus_delay = 0, /* usec */
-};
-
-/* davinci da850 evm audio machine driver */
-static u8 da850_iis_serializer_direction[] = {
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
- INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
- RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
-};
-
-static struct snd_platform_data da850_evm_snd_data = {
- .tx_dma_offset = 0x2000,
- .rx_dma_offset = 0x2000,
- .op_mode = DAVINCI_MCASP_IIS_MODE,
- .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
- .tdm_slots = 2,
- .serial_dir = da850_iis_serializer_direction,
- .asp_chan_q = EVENTQ_0,
- .ram_chan_q = EVENTQ_1,
- .version = MCASP_VERSION_2,
- .txnumevt = 1,
- .rxnumevt = 1,
- .sram_size_playback = SZ_8K,
- .sram_size_capture = SZ_8K,
-};
-
-static const short da850_evm_mcasp_pins[] __initconst = {
- DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
- DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
- DA850_AXR_11, DA850_AXR_12,
- -1
-};
-
-#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
-#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
-
-static struct gpiod_lookup_table mmc_gpios_table = {
- .dev_id = "da830-mmc.0",
- .table = {
- /* gpio chip 2 contains gpio range 64-95 */
- GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd",
- GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp",
- GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static struct davinci_mmc_config da850_mmc_config = {
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static const short da850_evm_mmcsd0_pins[] __initconst = {
- DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
- DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
- DA850_GPIO4_0, DA850_GPIO4_1,
- -1
-};
-
-static struct property_entry da850_lcd_backlight_props[] = {
- PROPERTY_ENTRY_BOOL("default-on"),
- { }
-};
-
-static struct gpiod_lookup_table da850_lcd_backlight_gpio_table = {
- .dev_id = "gpio-backlight",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_LCD_BL_PIN, NULL, 0),
- { }
- },
-};
-
-static const struct platform_device_info da850_lcd_backlight_info = {
- .name = "gpio-backlight",
- .id = PLATFORM_DEVID_NONE,
- .properties = da850_lcd_backlight_props,
-};
-
-static struct regulator_consumer_supply da850_lcd_supplies[] = {
- REGULATOR_SUPPLY("lcd", NULL),
-};
-
-static struct regulator_init_data da850_lcd_supply_data = {
- .consumer_supplies = da850_lcd_supplies,
- .num_consumer_supplies = ARRAY_SIZE(da850_lcd_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config da850_lcd_supply = {
- .supply_name = "lcd",
- .microvolts = 33000000,
- .init_data = &da850_lcd_supply_data,
-};
-
-static struct platform_device da850_lcd_supply_device = {
- .name = "reg-fixed-voltage",
- .id = 1, /* Dummy fixed regulator is 0 */
- .dev = {
- .platform_data = &da850_lcd_supply,
- },
-};
-
-static struct gpiod_lookup_table da850_lcd_supply_gpio_table = {
- .dev_id = "reg-fixed-voltage.1",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_LCD_PWR_PIN, NULL, 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table *da850_lcd_gpio_lookups[] = {
- &da850_lcd_backlight_gpio_table,
- &da850_lcd_supply_gpio_table,
-};
-
-static int da850_lcd_hw_init(void)
-{
- struct platform_device *backlight;
- int status;
-
- gpiod_add_lookup_tables(da850_lcd_gpio_lookups,
- ARRAY_SIZE(da850_lcd_gpio_lookups));
-
- backlight = platform_device_register_full(&da850_lcd_backlight_info);
- if (IS_ERR(backlight))
- return PTR_ERR(backlight);
-
- status = platform_device_register(&da850_lcd_supply_device);
- if (status)
- return status;
-
- return 0;
-}
-
-/* Fixed regulator support */
-static struct regulator_consumer_supply fixed_supplies[] = {
- /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */
- REGULATOR_SUPPLY("AVDD", "1-0018"),
- REGULATOR_SUPPLY("DRVDD", "1-0018"),
-
- /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
- REGULATOR_SUPPLY("DVDD", "1-0018"),
-
- /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */
- REGULATOR_SUPPLY("vcc", "1-0020"),
-};
-
-/* TPS65070 voltage regulator support */
-
-/* 3.3V */
-static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
- {
- .supply = "usb0_vdda33",
- },
- {
- .supply = "usb1_vdda33",
- },
-};
-
-/* 3.3V or 1.8V */
-static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
- {
- .supply = "dvdd3318_a",
- },
- {
- .supply = "dvdd3318_b",
- },
- {
- .supply = "dvdd3318_c",
- },
- REGULATOR_SUPPLY("IOVDD", "1-0018"),
-};
-
-/* 1.2V */
-static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
- {
- .supply = "cvdd",
- },
-};
-
-/* 1.8V LDO */
-static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
- {
- .supply = "sata_vddr",
- },
- {
- .supply = "usb0_vdda18",
- },
- {
- .supply = "usb1_vdda18",
- },
- {
- .supply = "ddr_dvdd18",
- },
-};
-
-/* 1.2V LDO */
-static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
- {
- .supply = "sata_vdd",
- },
- {
- .supply = "pll0_vdda",
- },
- {
- .supply = "pll1_vdda",
- },
- {
- .supply = "usbs_cvdd",
- },
- {
- .supply = "vddarnwa1",
- },
-};
-
-/* We take advantage of the fact that both defdcdc{2,3} are tied high */
-static struct tps6507x_reg_platform_data tps6507x_platform_data = {
- .defdcdc_default = true,
-};
-
-static struct regulator_init_data tps65070_regulator_data[] = {
- /* dcdc1 */
- {
- .constraints = {
- .min_uV = 3150000,
- .max_uV = 3450000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
- .consumer_supplies = tps65070_dcdc1_consumers,
- },
-
- /* dcdc2 */
- {
- .constraints = {
- .min_uV = 1710000,
- .max_uV = 3450000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- .always_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
- .consumer_supplies = tps65070_dcdc2_consumers,
- .driver_data = &tps6507x_platform_data,
- },
-
- /* dcdc3 */
- {
- .constraints = {
- .min_uV = 950000,
- .max_uV = 1350000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
- .consumer_supplies = tps65070_dcdc3_consumers,
- .driver_data = &tps6507x_platform_data,
- },
-
- /* ldo1 */
- {
- .constraints = {
- .min_uV = 1710000,
- .max_uV = 1890000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
- .consumer_supplies = tps65070_ldo1_consumers,
- },
-
- /* ldo2 */
- {
- .constraints = {
- .min_uV = 1140000,
- .max_uV = 1320000,
- .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS),
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
- .consumer_supplies = tps65070_ldo2_consumers,
- },
-};
-
-static struct touchscreen_init_data tps6507x_touchscreen_data = {
- .poll_period = 30, /* ms between touch samples */
- .min_pressure = 0x30, /* minimum pressure to trigger touch */
- .vendor = 0, /* /sys/class/input/input?/id/vendor */
- .product = 65070, /* /sys/class/input/input?/id/product */
- .version = 0x100, /* /sys/class/input/input?/id/version */
-};
-
-static struct tps6507x_board tps_board = {
- .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
- .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
-};
-
-static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
- {
- I2C_BOARD_INFO("tps6507x", 0x48),
- .platform_data = &tps_board,
- },
-};
-
-static int __init pmic_tps65070_init(void)
-{
- return i2c_register_board_info(1, da850_evm_tps65070_info,
- ARRAY_SIZE(da850_evm_tps65070_info));
-}
-
-static const short da850_evm_lcdc_pins[] = {
- DA850_GPIO2_8, DA850_GPIO2_15,
- -1
-};
-
-static const short da850_evm_mii_pins[] = {
- DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
- DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
- DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
- DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static const short da850_evm_rmii_pins[] = {
- DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
- DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
- DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static struct gpiod_hog da850_evm_emac_gpio_hogs[] = {
- {
- .chip_label = "davinci_gpio",
- .chip_hwnum = DA850_MII_MDIO_CLKEN_PIN,
- .line_name = "mdio_clk_en",
- .lflags = 0,
- /* dflags set in da850_evm_config_emac() */
- },
- { }
-};
-
-static int __init da850_evm_config_emac(void)
-{
- void __iomem *cfg_chip3_base;
- int ret;
- u32 val;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
- u8 rmii_en = soc_info->emac_pdata->rmii_en;
-
- if (!machine_is_davinci_da850_evm())
- return 0;
-
- cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
-
- val = __raw_readl(cfg_chip3_base);
-
- if (rmii_en) {
- val |= BIT(8);
- ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
- pr_info("EMAC: RMII PHY configured, MII PHY will not be"
- " functional\n");
- } else {
- val &= ~BIT(8);
- ret = davinci_cfg_reg_list(da850_evm_mii_pins);
- pr_info("EMAC: MII PHY configured, RMII PHY will not be"
- " functional\n");
- }
-
- if (ret)
- pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n",
- __func__, ret);
-
- /* configure the CFGCHIP3 register for RMII or MII */
- __raw_writel(val, cfg_chip3_base);
-
- ret = davinci_cfg_reg(DA850_GPIO2_6);
- if (ret)
- pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__);
-
- da850_evm_emac_gpio_hogs[0].dflags = rmii_en ? GPIOD_OUT_HIGH
- : GPIOD_OUT_LOW;
- gpiod_add_hogs(da850_evm_emac_gpio_hogs);
-
- soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
-
- return 0;
-}
-device_initcall(da850_evm_config_emac);
-
-/*
- * The following EDMA channels/slots are not being used by drivers (for
- * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
- * they are being reserved for codecs on the DSP side.
- */
-static const s16 da850_dma0_rsv_chans[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma0_rsv_slots[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 50},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_chans[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_slots[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 90},
- {-1, -1}
-};
-
-static struct edma_rsv_info da850_edma_cc0_rsv = {
- .rsv_chans = da850_dma0_rsv_chans,
- .rsv_slots = da850_dma0_rsv_slots,
-};
-
-static struct edma_rsv_info da850_edma_cc1_rsv = {
- .rsv_chans = da850_dma1_rsv_chans,
- .rsv_slots = da850_dma1_rsv_slots,
-};
-
-static struct edma_rsv_info *da850_edma_rsv[2] = {
- &da850_edma_cc0_rsv,
- &da850_edma_cc1_rsv,
-};
-
-#ifdef CONFIG_CPU_FREQ
-static __init int da850_evm_init_cpufreq(void)
-{
- switch (system_rev & 0xF) {
- case 3:
- da850_max_speed = 456000;
- break;
- case 2:
- da850_max_speed = 408000;
- break;
- case 1:
- da850_max_speed = 372000;
- break;
- }
-
- return da850_register_cpufreq("pll0_sysclk3");
-}
-#else
-static __init int da850_evm_init_cpufreq(void) { return 0; }
-#endif
-
-#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
-
-#define TVP5147_CH0 "tvp514x-0"
-#define TVP5147_CH1 "tvp514x-1"
-
-/* VPIF capture configuration */
-static struct tvp514x_platform_data tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1,
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-static struct vpif_input da850_ch0_inputs[] = {
- {
- .input = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_STD,
- .std = TVP514X_STD_ALL,
- },
- .input_route = INPUT_CVBS_VI2B,
- .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- .subdev_name = TVP5147_CH0,
- },
-};
-
-static struct vpif_input da850_ch1_inputs[] = {
- {
- .input = {
- .index = 0,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_STD,
- .std = TVP514X_STD_ALL,
- },
- .input_route = INPUT_SVIDEO_VI2C_VI1C,
- .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- .subdev_name = TVP5147_CH1,
- },
-};
-
-static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
- {
- .name = TVP5147_CH0,
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &tvp5146_pdata,
- },
- },
- {
- .name = TVP5147_CH1,
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5c),
- .platform_data = &tvp5146_pdata,
- },
- },
-};
-
-static struct vpif_capture_config da850_vpif_capture_config = {
- .subdev_info = da850_vpif_capture_sdev_info,
- .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
- .i2c_adapter_id = 1,
- .chan_config[0] = {
- .inputs = da850_ch0_inputs,
- .input_count = ARRAY_SIZE(da850_ch0_inputs),
- .vpif_if = {
- .if_type = VPIF_IF_BT656,
- .hd_pol = 1,
- .vd_pol = 1,
- .fid_pol = 0,
- },
- },
- .chan_config[1] = {
- .inputs = da850_ch1_inputs,
- .input_count = ARRAY_SIZE(da850_ch1_inputs),
- .vpif_if = {
- .if_type = VPIF_IF_BT656,
- .hd_pol = 1,
- .vd_pol = 1,
- .fid_pol = 0,
- },
- },
- .card_name = "DA850/OMAP-L138 Video Capture",
-};
-
-/* VPIF display configuration */
-
-static struct adv7343_platform_data adv7343_pdata = {
- .mode_config = {
- .dac = { 1, 1, 1 },
- },
- .sd_config = {
- .sd_dac_out = { 1 },
- },
-};
-
-static struct vpif_subdev_info da850_vpif_subdev[] = {
- {
- .name = "adv7343",
- .board_info = {
- I2C_BOARD_INFO("adv7343", 0x2a),
- .platform_data = &adv7343_pdata,
- },
- },
-};
-
-static const struct vpif_output da850_ch0_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_STD,
- .std = V4L2_STD_ALL,
- },
- .subdev_name = "adv7343",
- .output_route = ADV7343_COMPOSITE_ID,
- },
- {
- .output = {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_STD,
- .std = V4L2_STD_ALL,
- },
- .subdev_name = "adv7343",
- .output_route = ADV7343_SVIDEO_ID,
- },
-};
-
-static struct vpif_display_config da850_vpif_display_config = {
- .subdevinfo = da850_vpif_subdev,
- .subdev_count = ARRAY_SIZE(da850_vpif_subdev),
- .chan_config[0] = {
- .outputs = da850_ch0_outputs,
- .output_count = ARRAY_SIZE(da850_ch0_outputs),
- },
- .card_name = "DA850/OMAP-L138 Video Display",
- .i2c_adapter_id = 1,
-};
-
-static __init void da850_vpif_init(void)
-{
- int ret;
-
- ret = da850_register_vpif();
- if (ret)
- pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
-
- ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
- if (ret)
- pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n",
- ret);
-
- ret = da850_register_vpif_capture(&da850_vpif_capture_config);
- if (ret)
- pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret);
-
- ret = davinci_cfg_reg_list(da850_vpif_display_pins);
- if (ret)
- pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n",
- ret);
-
- ret = da850_register_vpif_display(&da850_vpif_display_config);
- if (ret)
- pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret);
-}
-
-#else
-static __init void da850_vpif_init(void) {}
-#endif
-
-#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
-
-static __init void da850_evm_init(void)
-{
- int ret;
-
- da850_register_clocks();
-
- ret = da850_register_gpio();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies));
-
- ret = pmic_tps65070_init();
- if (ret)
- pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
-
- ret = da850_register_edma(da850_edma_rsv);
- if (ret)
- pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
-
- ret = davinci_cfg_reg_list(da850_i2c0_pins);
- if (ret)
- pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
- if (ret)
- pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret);
-
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("%s: watchdog registration failed: %d\n",
- __func__, ret);
-
- if (HAS_MMC) {
- ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
- if (ret)
- pr_warn("%s: MMCSD0 mux setup failed: %d\n",
- __func__, ret);
-
- gpiod_add_lookup_table(&mmc_gpios_table);
-
- ret = da8xx_register_mmcsd0(&da850_mmc_config);
- if (ret)
- pr_warn("%s: MMCSD0 registration failed: %d\n",
- __func__, ret);
- }
-
- davinci_serial_init(da8xx_serial_device);
-
- nvmem_add_cell_table(&da850evm_nvmem_cell_table);
- nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1);
-
- i2c_register_board_info(1, da850_evm_i2c_devices,
- ARRAY_SIZE(da850_evm_i2c_devices));
-
- /*
- * shut down uart 0 and 1; they are not used on the board and
- * accessing them causes endless "too much work in irq53" messages
- * with arago fs
- */
- __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
- __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
-
- ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
- if (ret)
- pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret);
-
- da850_evm_snd_data.sram_pool = sram_get_gen_pool();
- da8xx_register_mcasp(0, &da850_evm_snd_data);
-
- ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
- if (ret)
- pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret);
-
- ret = da8xx_register_uio_pruss();
- if (ret)
- pr_warn("da850_evm_init: pruss initialization failed: %d\n",
- ret);
-
- /* Handle board specific muxing for LCD here */
- ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
- if (ret)
- pr_warn("%s: EVM specific LCD mux setup failed: %d\n",
- __func__, ret);
-
- ret = da850_lcd_hw_init();
- if (ret)
- pr_warn("%s: LCD initialization failed: %d\n", __func__, ret);
-
- ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
- if (ret)
- pr_warn("%s: LCDC registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_rtc();
- if (ret)
- pr_warn("%s: RTC setup failed: %d\n", __func__, ret);
-
- ret = da850_evm_init_cpufreq();
- if (ret)
- pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_cpuidle();
- if (ret)
- pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
-
- davinci_pm_init();
- da850_vpif_init();
-
- ret = spi_register_board_info(da850evm_spi_info,
- ARRAY_SIZE(da850evm_spi_info));
- if (ret)
- pr_warn("%s: spi info registration failed: %d\n", __func__,
- ret);
-
- ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));
- if (ret)
- pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret);
-
- ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
- if (ret)
- pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_rproc();
- if (ret)
- pr_warn("%s: dsp/rproc registration failed: %d\n",
- __func__, ret);
-
- regulator_has_full_constraints();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init da850_evm_console_init(void)
-{
- if (!machine_is_davinci_da850_evm())
- return 0;
-
- return add_preferred_console("ttyS", 2, "115200");
-}
-console_initcall(da850_evm_console_init);
-#endif
-
-static void __init da850_evm_map_io(void)
-{
- da850_init();
-}
-
-MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
- .atag_offset = 0x100,
- .map_io = da850_evm_map_io,
- .init_irq = da850_init_irq,
- .init_time = da850_init_time,
- .init_machine = da850_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
- .reserve = da8xx_rproc_reserve_cma,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
deleted file mode 100644
index 3c5a9e3c128a..000000000000
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * TI DaVinci EVM board support
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/clk.h>
-#include <linux/dm9000.h>
-#include <linux/videodev2.h>
-#include <media/i2c/tvp514x.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/serial.h>
-#include <mach/common.h>
-
-#include "davinci.h"
-
-/* NOTE: this is geared for the standard config, with a socketed
- * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
- * swap chips, maybe with a different block size, partitioning may
- * need to be changed.
- */
-#define NAND_BLOCK_SIZE SZ_128K
-
-static struct mtd_partition davinci_nand_partitions[] = {
- {
- /* UBL (a few copies) plus U-Boot */
- .name = "bootloader",
- .offset = 0,
- .size = 15 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- /* U-Boot environment */
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 1 * NAND_BLOCK_SIZE,
- .mask_flags = 0,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- .name = "filesystem1",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512M,
- .mask_flags = 0,
- }, {
- .name = "filesystem2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* two blocks with bad block table (and mirror) at the end */
-};
-
-static struct davinci_nand_pdata davinci_nand_data = {
- .core_chipsel = 0,
- .mask_chipsel = BIT(14),
- .parts = davinci_nand_partitions,
- .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .bbt_options = NAND_BBT_USE_FLASH,
- .ecc_bits = 4,
-};
-
-static struct resource davinci_nand_resources[] = {
- {
- .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM355_ASYNC_EMIF_CONTROL_BASE,
- .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_nand_device = {
- .name = "davinci_nand",
- .id = 0,
-
- .num_resources = ARRAY_SIZE(davinci_nand_resources),
- .resource = davinci_nand_resources,
-
- .dev = {
- .platform_data = &davinci_nand_data,
- },
-};
-
-#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15)
-#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14)
-
-static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
- .dev_id = "i2c_davinci.1",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda",
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- { }
- },
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 400 /* kHz */,
- .bus_delay = 0 /* usec */,
- .gpio_recovery = true,
-};
-
-static int dm355evm_mmc_gpios = -EINVAL;
-
-static void dm355evm_mmcsd_gpios(unsigned gpio)
-{
- gpio_request(gpio + 0, "mmc0_ro");
- gpio_request(gpio + 1, "mmc0_cd");
- gpio_request(gpio + 2, "mmc1_ro");
- gpio_request(gpio + 3, "mmc1_cd");
-
- /* we "know" these are input-only so we don't
- * need to call gpio_direction_input()
- */
-
- dm355evm_mmc_gpios = gpio;
-}
-
-static struct i2c_board_info dm355evm_i2c_info[] = {
- { I2C_BOARD_INFO("dm355evm_msp", 0x25),
- .platform_data = dm355evm_mmcsd_gpios,
- },
- /* { plus irq }, */
- { I2C_BOARD_INFO("tlv320aic33", 0x1b), },
-};
-
-static void __init evm_init_i2c(void)
-{
- gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
- davinci_init_i2c(&i2c_pdata);
-
- gpio_request(5, "dm355evm_msp");
- gpio_direction_input(5);
- dm355evm_i2c_info[0].irq = gpio_to_irq(5);
-
- i2c_register_board_info(1, dm355evm_i2c_info,
- ARRAY_SIZE(dm355evm_i2c_info));
-}
-
-static struct resource dm355evm_dm9000_rsrc[] = {
- {
- /* addr */
- .start = 0x04014000,
- .end = 0x04014001,
- .flags = IORESOURCE_MEM,
- }, {
- /* data */
- .start = 0x04014002,
- .end = 0x04014003,
- .flags = IORESOURCE_MEM,
- }, {
- .flags = IORESOURCE_IRQ
- | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
- },
-};
-
-static struct dm9000_plat_data dm335evm_dm9000_platdata;
-
-static struct platform_device dm355evm_dm9000 = {
- .name = "dm9000",
- .id = -1,
- .resource = dm355evm_dm9000_rsrc,
- .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
- .dev = {
- .platform_data = &dm335evm_dm9000_platdata,
- },
-};
-
-static struct tvp514x_platform_data tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-/* Inputs available at the TVP5146 */
-static struct v4l2_input tvp5146_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
-};
-
-/*
- * this is the route info for connecting each input to decoder
- * ouput that goes to vpfe. There is a one to one correspondence
- * with tvp5146_inputs
- */
-static struct vpfe_route tvp5146_routes[] = {
- {
- .input = INPUT_CVBS_VI2B,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
- {
- .input = INPUT_SVIDEO_VI2C_VI1C,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-};
-
-static struct vpfe_subdev_info vpfe_sub_devs[] = {
- {
- .name = "tvp5146",
- .grp_id = 0,
- .num_inputs = ARRAY_SIZE(tvp5146_inputs),
- .inputs = tvp5146_inputs,
- .routes = tvp5146_routes,
- .can_route = 1,
- .ccdc_if_params = {
- .if_type = VPFE_BT656,
- .hdpol = VPFE_PINPOL_POSITIVE,
- .vdpol = VPFE_PINPOL_POSITIVE,
- },
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &tvp5146_pdata,
- },
- }
-};
-
-static struct vpfe_config vpfe_cfg = {
- .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
- .i2c_adapter_id = 1,
- .sub_devs = vpfe_sub_devs,
- .card_name = "DM355 EVM",
- .ccdc = "DM355 CCDC",
-};
-
-/* venc standards timings */
-static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = {
- {
- .name = "ntsc",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_NTSC,
- .interlaced = 1,
- .xres = 720,
- .yres = 480,
- .aspect = {11, 10},
- .fps = {30000, 1001},
- .left_margin = 0x79,
- .upper_margin = 0x10,
- },
- {
- .name = "pal",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_PAL,
- .interlaced = 1,
- .xres = 720,
- .yres = 576,
- .aspect = {54, 59},
- .fps = {25, 1},
- .left_margin = 0x7E,
- .upper_margin = 0x16
- },
-};
-
-#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-/*
- * The outputs available from VPBE + ecnoders. Keep the
- * the order same as that of encoders. First those from venc followed by that
- * from encoders. Index in the output refers to index on a particular encoder.
- * Driver uses this index to pass it to encoder when it supports more than
- * one output. Application uses index of the array to set an output.
- */
-static struct vpbe_output dm355evm_vpbe_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = VENC_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- .subdev_name = DM355_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "ntsc",
- .num_modes = ARRAY_SIZE(dm355evm_enc_preset_timing),
- .modes = dm355evm_enc_preset_timing,
- .if_params = MEDIA_BUS_FMT_FIXED,
- },
-};
-
-static struct vpbe_config dm355evm_display_cfg = {
- .module_name = "dm355-vpbe-display",
- .i2c_adapter_id = 1,
- .osd = {
- .module_name = DM355_VPBE_OSD_SUBDEV_NAME,
- },
- .venc = {
- .module_name = DM355_VPBE_VENC_SUBDEV_NAME,
- },
- .num_outputs = ARRAY_SIZE(dm355evm_vpbe_outputs),
- .outputs = dm355evm_vpbe_outputs,
-};
-
-static struct platform_device *davinci_evm_devices[] __initdata = {
- &dm355evm_dm9000,
- &davinci_nand_device,
-};
-
-static void __init dm355_evm_map_io(void)
-{
- dm355_init();
-}
-
-static int dm355evm_mmc_get_cd(int module)
-{
- if (!gpio_is_valid(dm355evm_mmc_gpios))
- return -ENXIO;
- /* low == card present */
- return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1);
-}
-
-static int dm355evm_mmc_get_ro(int module)
-{
- if (!gpio_is_valid(dm355evm_mmc_gpios))
- return -ENXIO;
- /* high == card's write protect switch active */
- return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0);
-}
-
-static struct davinci_mmc_config dm355evm_mmc_config = {
- .get_cd = dm355evm_mmc_get_cd,
- .get_ro = dm355evm_mmc_get_ro,
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-/* Don't connect anything to J10 unless you're only using USB host
- * mode *and* have to do so with some kind of gender-bender. If
- * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
- * the ID pin won't need any help.
- */
-#define USB_ID_VALUE 1 /* ID pulled low */
-
-static struct spi_eeprom at25640a = {
- .byte_len = SZ_64K / 8,
- .name = "at25640a",
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static const struct spi_board_info dm355_evm_spi_info[] __initconst = {
- {
- .modalias = "at25",
- .platform_data = &at25640a,
- .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
- .bus_num = 0,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-static __init void dm355_evm_init(void)
-{
- struct clk *aemif;
- int ret;
-
- dm355_register_clocks();
-
- ret = dm355_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- gpio_request(1, "dm9000");
- gpio_direction_input(1);
- dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
-
- aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
- if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
- clk_prepare_enable(aemif);
-
- platform_add_devices(davinci_evm_devices,
- ARRAY_SIZE(davinci_evm_devices));
- evm_init_i2c();
- davinci_serial_init(dm355_serial_device);
-
- /* NOTE: NAND flash timings set by the UBL are slower than
- * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
- * but could be 0x0400008c for about 25% faster page reads.
- */
-
- gpio_request(2, "usb_id_toggle");
- gpio_direction_output(2, USB_ID_VALUE);
- /* irlml6401 switches over 1A in under 8 msec */
- davinci_setup_usb(1000, 8);
-
- davinci_setup_mmc(0, &dm355evm_mmc_config);
- davinci_setup_mmc(1, &dm355evm_mmc_config);
-
- dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg);
-
- dm355_init_spi0(BIT(0), dm355_evm_spi_info,
- ARRAY_SIZE(dm355_evm_spi_info));
-
- /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */
- dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN);
-}
-
-MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
- .atag_offset = 0x100,
- .map_io = dm355_evm_map_io,
- .init_irq = dm355_init_irq,
- .init_time = dm355_init_time,
- .init_machine = dm355_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
deleted file mode 100644
index e475b2113e70..000000000000
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * DM355 leopard board support
- *
- * Based on board-dm355-evm.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/serial.h>
-
-#include "davinci.h"
-
-/* NOTE: this is geared for the standard config, with a socketed
- * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
- * swap chips, maybe with a different block size, partitioning may
- * need to be changed.
- */
-#define NAND_BLOCK_SIZE SZ_128K
-
-static struct mtd_partition davinci_nand_partitions[] = {
- {
- /* UBL (a few copies) plus U-Boot */
- .name = "bootloader",
- .offset = 0,
- .size = 15 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- /* U-Boot environment */
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 1 * NAND_BLOCK_SIZE,
- .mask_flags = 0,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- .name = "filesystem1",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512M,
- .mask_flags = 0,
- }, {
- .name = "filesystem2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* two blocks with bad block table (and mirror) at the end */
-};
-
-static struct davinci_nand_pdata davinci_nand_data = {
- .core_chipsel = 0,
- .mask_chipsel = BIT(14),
- .parts = davinci_nand_partitions,
- .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
-};
-
-static struct resource davinci_nand_resources[] = {
- {
- .start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM355_ASYNC_EMIF_CONTROL_BASE,
- .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_nand_device = {
- .name = "davinci_nand",
- .id = 0,
-
- .num_resources = ARRAY_SIZE(davinci_nand_resources),
- .resource = davinci_nand_resources,
-
- .dev = {
- .platform_data = &davinci_nand_data,
- },
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 400 /* kHz */,
- .bus_delay = 0 /* usec */,
-};
-
-static int leopard_mmc_gpio = -EINVAL;
-
-static void dm355leopard_mmcsd_gpios(unsigned gpio)
-{
- gpio_request(gpio + 0, "mmc0_ro");
- gpio_request(gpio + 1, "mmc0_cd");
- gpio_request(gpio + 2, "mmc1_ro");
- gpio_request(gpio + 3, "mmc1_cd");
-
- /* we "know" these are input-only so we don't
- * need to call gpio_direction_input()
- */
-
- leopard_mmc_gpio = gpio;
-}
-
-static struct i2c_board_info dm355leopard_i2c_info[] = {
- { I2C_BOARD_INFO("dm355leopard_msp", 0x25),
- .platform_data = dm355leopard_mmcsd_gpios,
- /* plus irq */ },
- /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
- /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
-};
-
-static void __init leopard_init_i2c(void)
-{
- davinci_init_i2c(&i2c_pdata);
-
- gpio_request(5, "dm355leopard_msp");
- gpio_direction_input(5);
- dm355leopard_i2c_info[0].irq = gpio_to_irq(5);
-
- i2c_register_board_info(1, dm355leopard_i2c_info,
- ARRAY_SIZE(dm355leopard_i2c_info));
-}
-
-static struct resource dm355leopard_dm9000_rsrc[] = {
- {
- /* addr */
- .start = 0x04000000,
- .end = 0x04000001,
- .flags = IORESOURCE_MEM,
- }, {
- /* data */
- .start = 0x04000016,
- .end = 0x04000017,
- .flags = IORESOURCE_MEM,
- }, {
- .flags = IORESOURCE_IRQ
- | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
- },
-};
-
-static struct platform_device dm355leopard_dm9000 = {
- .name = "dm9000",
- .id = -1,
- .resource = dm355leopard_dm9000_rsrc,
- .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc),
-};
-
-static struct platform_device *davinci_leopard_devices[] __initdata = {
- &dm355leopard_dm9000,
- &davinci_nand_device,
-};
-
-static void __init dm355_leopard_map_io(void)
-{
- dm355_init();
-}
-
-static int dm355leopard_mmc_get_cd(int module)
-{
- if (!gpio_is_valid(leopard_mmc_gpio))
- return -ENXIO;
- /* low == card present */
- return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1);
-}
-
-static int dm355leopard_mmc_get_ro(int module)
-{
- if (!gpio_is_valid(leopard_mmc_gpio))
- return -ENXIO;
- /* high == card's write protect switch active */
- return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0);
-}
-
-static struct davinci_mmc_config dm355leopard_mmc_config = {
- .get_cd = dm355leopard_mmc_get_cd,
- .get_ro = dm355leopard_mmc_get_ro,
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-/* Don't connect anything to J10 unless you're only using USB host
- * mode *and* have to do so with some kind of gender-bender. If
- * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
- * the ID pin won't need any help.
- */
-#define USB_ID_VALUE 1 /* ID pulled low */
-
-static struct spi_eeprom at25640a = {
- .byte_len = SZ_64K / 8,
- .name = "at25640a",
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static const struct spi_board_info dm355_leopard_spi_info[] __initconst = {
- {
- .modalias = "at25",
- .platform_data = &at25640a,
- .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */
- .bus_num = 0,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-static __init void dm355_leopard_init(void)
-{
- struct clk *aemif;
- int ret;
-
- dm355_register_clocks();
-
- ret = dm355_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- gpio_request(9, "dm9000");
- gpio_direction_input(9);
- dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9);
-
- aemif = clk_get(&dm355leopard_dm9000.dev, "aemif");
- if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
- clk_prepare_enable(aemif);
-
- platform_add_devices(davinci_leopard_devices,
- ARRAY_SIZE(davinci_leopard_devices));
- leopard_init_i2c();
- davinci_serial_init(dm355_serial_device);
-
- /* NOTE: NAND flash timings set by the UBL are slower than
- * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
- * but could be 0x0400008c for about 25% faster page reads.
- */
-
- gpio_request(2, "usb_id_toggle");
- gpio_direction_output(2, USB_ID_VALUE);
- /* irlml6401 switches over 1A in under 8 msec */
- davinci_setup_usb(1000, 8);
-
- davinci_setup_mmc(0, &dm355leopard_mmc_config);
- davinci_setup_mmc(1, &dm355leopard_mmc_config);
-
- dm355_init_spi0(BIT(0), dm355_leopard_spi_info,
- ARRAY_SIZE(dm355_leopard_spi_info));
-}
-
-MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
- .atag_offset = 0x100,
- .map_io = dm355_leopard_map_io,
- .init_irq = dm355_init_irq,
- .init_time = dm355_init_time,
- .init_machine = dm355_leopard_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
deleted file mode 100644
index b3bef74c982a..000000000000
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ /dev/null
@@ -1,864 +0,0 @@
-/*
- * TI DaVinci DM365 EVM board support
- *
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/property.h>
-#include <linux/leds.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/slab.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/nvmem-provider.h>
-#include <linux/input.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/v4l2-dv-timings.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/mux.h>
-#include <mach/common.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <mach/serial.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/keyscan-davinci.h>
-
-#include <media/i2c/ths7303.h>
-#include <media/i2c/tvp514x.h>
-
-#include "davinci.h"
-
-static inline int have_imager(void)
-{
- /* REVISIT when it's supported, trigger via Kconfig */
- return 0;
-}
-
-static inline int have_tvp7002(void)
-{
- /* REVISIT when it's supported, trigger via Kconfig */
- return 0;
-}
-
-#define DM365_EVM_PHY_ID "davinci_mdio-0:01"
-/*
- * A MAX-II CPLD is used for various board control functions.
- */
-#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
-
-#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
-#define CPLD_TEST CPLD_OFFSET(0,1)
-#define CPLD_LEDS CPLD_OFFSET(0,2)
-#define CPLD_MUX CPLD_OFFSET(0,3)
-#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
-#define CPLD_POWER CPLD_OFFSET(1,1)
-#define CPLD_VIDEO CPLD_OFFSET(1,2)
-#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
-
-#define CPLD_DILC_OUT CPLD_OFFSET(2,0)
-#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
-
-#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
-#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
-#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
-#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
-#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
-#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
-#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
-#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
-#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
-
-#define CPLD_RESETS CPLD_OFFSET(4,3)
-
-#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
-#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
-#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
-#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
-#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
-#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
-
-static void __iomem *cpld;
-
-
-/* NOTE: this is geared for the standard config, with a socketed
- * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
- * swap chips with a different block size, partitioning will
- * need to be changed. This NAND chip MT29F16G08FAA is the default
- * NAND shipped with the Spectrum Digital DM365 EVM
- */
-#define NAND_BLOCK_SIZE SZ_128K
-
-static struct mtd_partition davinci_nand_partitions[] = {
- {
- /* UBL (a few copies) plus U-Boot */
- .name = "bootloader",
- .offset = 0,
- .size = 30 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- /* U-Boot environment */
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 2 * NAND_BLOCK_SIZE,
- .mask_flags = 0,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- .name = "filesystem1",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512M,
- .mask_flags = 0,
- }, {
- .name = "filesystem2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* two blocks with bad block table (and mirror) at the end */
-};
-
-static struct davinci_nand_pdata davinci_nand_data = {
- .core_chipsel = 0,
- .mask_chipsel = BIT(14),
- .parts = davinci_nand_partitions,
- .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .bbt_options = NAND_BBT_USE_FLASH,
- .ecc_bits = 4,
-};
-
-static struct resource davinci_nand_resources[] = {
- {
- .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM365_ASYNC_EMIF_CONTROL_BASE,
- .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(davinci_nand_resources),
- .resource = davinci_nand_resources,
- .dev = {
- .platform_data = &davinci_nand_data,
- },
- }
-};
-
-static struct resource davinci_aemif_resources[] = {
- {
- .start = DM365_ASYNC_EMIF_CONTROL_BASE,
- .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
- {
- .cs = 1,
- },
-};
-
-static struct aemif_platform_data davinci_aemif_pdata = {
- .abus_data = da850_evm_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
- .sub_devices = davinci_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
-};
-
-static struct platform_device davinci_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &davinci_aemif_pdata,
- },
- .resource = davinci_aemif_resources,
- .num_resources = ARRAY_SIZE(davinci_aemif_resources),
-};
-
-static struct nvmem_cell_info davinci_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x7f00,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table davinci_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = davinci_nvmem_cells,
- .ncells = ARRAY_SIZE(davinci_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 64),
- { }
-};
-
-static const struct software_node eeprom_node = {
- .properties = eeprom_properties,
-};
-
-static struct i2c_board_info i2c_info[] = {
- {
- I2C_BOARD_INFO("24c256", 0x50),
- .swnode = &eeprom_node,
- },
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- },
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 400 /* kHz */,
- .bus_delay = 0 /* usec */,
-};
-
-/* Fixed regulator support */
-static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
- /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
- REGULATOR_SUPPLY("AVDD", "1-0018"),
- REGULATOR_SUPPLY("DRVDD", "1-0018"),
- REGULATOR_SUPPLY("IOVDD", "1-0018"),
-};
-
-static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
- /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
- REGULATOR_SUPPLY("DVDD", "1-0018"),
-};
-
-static int dm365evm_keyscan_enable(struct device *dev)
-{
- return davinci_cfg_reg(DM365_KEYSCAN);
-}
-
-static unsigned short dm365evm_keymap[] = {
- KEY_KP2,
- KEY_LEFT,
- KEY_EXIT,
- KEY_DOWN,
- KEY_ENTER,
- KEY_UP,
- KEY_KP1,
- KEY_RIGHT,
- KEY_MENU,
- KEY_RECORD,
- KEY_REWIND,
- KEY_KPMINUS,
- KEY_STOP,
- KEY_FASTFORWARD,
- KEY_KPPLUS,
- KEY_PLAYPAUSE,
- 0
-};
-
-static struct davinci_ks_platform_data dm365evm_ks_data = {
- .device_enable = dm365evm_keyscan_enable,
- .keymap = dm365evm_keymap,
- .keymapsize = ARRAY_SIZE(dm365evm_keymap),
- .rep = 1,
- /* Scan period = strobe + interval */
- .strobe = 0x5,
- .interval = 0x2,
- .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
-};
-
-static int cpld_mmc_get_cd(int module)
-{
- if (!cpld)
- return -ENXIO;
-
- /* low == card present */
- return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
-}
-
-static int cpld_mmc_get_ro(int module)
-{
- if (!cpld)
- return -ENXIO;
-
- /* high == card's write protect switch active */
- return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
-}
-
-static struct davinci_mmc_config dm365evm_mmc_config = {
- .get_cd = cpld_mmc_get_cd,
- .get_ro = cpld_mmc_get_ro,
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static void dm365evm_emac_configure(void)
-{
- /*
- * EMAC pins are multiplexed with GPIO and UART
- * Further details are available at the DM365 ARM
- * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
- */
- davinci_cfg_reg(DM365_EMAC_TX_EN);
- davinci_cfg_reg(DM365_EMAC_TX_CLK);
- davinci_cfg_reg(DM365_EMAC_COL);
- davinci_cfg_reg(DM365_EMAC_TXD3);
- davinci_cfg_reg(DM365_EMAC_TXD2);
- davinci_cfg_reg(DM365_EMAC_TXD1);
- davinci_cfg_reg(DM365_EMAC_TXD0);
- davinci_cfg_reg(DM365_EMAC_RXD3);
- davinci_cfg_reg(DM365_EMAC_RXD2);
- davinci_cfg_reg(DM365_EMAC_RXD1);
- davinci_cfg_reg(DM365_EMAC_RXD0);
- davinci_cfg_reg(DM365_EMAC_RX_CLK);
- davinci_cfg_reg(DM365_EMAC_RX_DV);
- davinci_cfg_reg(DM365_EMAC_RX_ER);
- davinci_cfg_reg(DM365_EMAC_CRS);
- davinci_cfg_reg(DM365_EMAC_MDIO);
- davinci_cfg_reg(DM365_EMAC_MDCLK);
-
- /*
- * EMAC interrupts are multiplexed with GPIO interrupts
- * Details are available at the DM365 ARM
- * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
- */
- davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
- davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
- davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
- davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
-}
-
-static void dm365evm_mmc_configure(void)
-{
- /*
- * MMC/SD pins are multiplexed with GPIO and EMIF
- * Further details are available at the DM365 ARM
- * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
- */
- davinci_cfg_reg(DM365_SD1_CLK);
- davinci_cfg_reg(DM365_SD1_CMD);
- davinci_cfg_reg(DM365_SD1_DATA3);
- davinci_cfg_reg(DM365_SD1_DATA2);
- davinci_cfg_reg(DM365_SD1_DATA1);
- davinci_cfg_reg(DM365_SD1_DATA0);
-}
-
-static struct tvp514x_platform_data tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-/* Inputs available at the TVP5146 */
-static struct v4l2_input tvp5146_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
-};
-
-/*
- * this is the route info for connecting each input to decoder
- * ouput that goes to vpfe. There is a one to one correspondence
- * with tvp5146_inputs
- */
-static struct vpfe_route tvp5146_routes[] = {
- {
- .input = INPUT_CVBS_VI2B,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-{
- .input = INPUT_SVIDEO_VI2C_VI1C,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-};
-
-static struct vpfe_subdev_info vpfe_sub_devs[] = {
- {
- .name = "tvp5146",
- .grp_id = 0,
- .num_inputs = ARRAY_SIZE(tvp5146_inputs),
- .inputs = tvp5146_inputs,
- .routes = tvp5146_routes,
- .can_route = 1,
- .ccdc_if_params = {
- .if_type = VPFE_BT656,
- .hdpol = VPFE_PINPOL_POSITIVE,
- .vdpol = VPFE_PINPOL_POSITIVE,
- },
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &tvp5146_pdata,
- },
- },
-};
-
-static struct vpfe_config vpfe_cfg = {
- .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
- .sub_devs = vpfe_sub_devs,
- .i2c_adapter_id = 1,
- .card_name = "DM365 EVM",
- .ccdc = "ISIF",
-};
-
-/* venc standards timings */
-static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
- {
- .name = "ntsc",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_NTSC,
- .interlaced = 1,
- .xres = 720,
- .yres = 480,
- .aspect = {11, 10},
- .fps = {30000, 1001},
- .left_margin = 0x79,
- .upper_margin = 0x10,
- },
- {
- .name = "pal",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_PAL,
- .interlaced = 1,
- .xres = 720,
- .yres = 576,
- .aspect = {54, 59},
- .fps = {25, 1},
- .left_margin = 0x7E,
- .upper_margin = 0x16,
- },
-};
-
-/* venc dv timings */
-static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
- {
- .name = "480p59_94",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
- .interlaced = 0,
- .xres = 720,
- .yres = 480,
- .aspect = {1, 1},
- .fps = {5994, 100},
- .left_margin = 0x8F,
- .upper_margin = 0x2D,
- },
- {
- .name = "576p50",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_720X576P50,
- .interlaced = 0,
- .xres = 720,
- .yres = 576,
- .aspect = {1, 1},
- .fps = {50, 1},
- .left_margin = 0x8C,
- .upper_margin = 0x36,
- },
- {
- .name = "720p60",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
- .interlaced = 0,
- .xres = 1280,
- .yres = 720,
- .aspect = {1, 1},
- .fps = {60, 1},
- .left_margin = 0x117,
- .right_margin = 70,
- .upper_margin = 38,
- .lower_margin = 3,
- .hsync_len = 80,
- .vsync_len = 5,
- },
- {
- .name = "1080i60",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
- .interlaced = 1,
- .xres = 1920,
- .yres = 1080,
- .aspect = {1, 1},
- .fps = {30, 1},
- .left_margin = 0xc9,
- .right_margin = 80,
- .upper_margin = 30,
- .lower_margin = 3,
- .hsync_len = 88,
- .vsync_len = 5,
- },
-};
-
-#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-/*
- * The outputs available from VPBE + ecnoders. Keep the
- * the order same as that of encoders. First those from venc followed by that
- * from encoders. Index in the output refers to index on a particular
- * encoder.Driver uses this index to pass it to encoder when it supports more
- * than one output. Application uses index of the array to set an output.
- */
-static struct vpbe_output dm365evm_vpbe_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = VENC_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "ntsc",
- .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
- .modes = dm365evm_enc_std_timing,
- .if_params = MEDIA_BUS_FMT_FIXED,
- },
- {
- .output = {
- .index = 1,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
- .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "480p59_94",
- .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
- .modes = dm365evm_enc_preset_timing,
- .if_params = MEDIA_BUS_FMT_FIXED,
- },
-};
-
-/*
- * Amplifiers on the board
- */
-static struct ths7303_platform_data ths7303_pdata = {
- .ch_1 = 3,
- .ch_2 = 3,
- .ch_3 = 3,
-};
-
-static struct amp_config_info vpbe_amp = {
- .module_name = "ths7303",
- .is_i2c = 1,
- .board_info = {
- I2C_BOARD_INFO("ths7303", 0x2c),
- .platform_data = &ths7303_pdata,
- }
-};
-
-static struct vpbe_config dm365evm_display_cfg = {
- .module_name = "dm365-vpbe-display",
- .i2c_adapter_id = 1,
- .amp = &vpbe_amp,
- .osd = {
- .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
- },
- .venc = {
- .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
- },
- .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
- .outputs = dm365evm_vpbe_outputs,
-};
-
-static void __init evm_init_i2c(void)
-{
- davinci_init_i2c(&i2c_pdata);
- i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
-}
-
-static inline int have_leds(void)
-{
-#ifdef CONFIG_LEDS_CLASS
- return 1;
-#else
- return 0;
-#endif
-}
-
-struct cpld_led {
- struct led_classdev cdev;
- u8 mask;
-};
-
-static const struct {
- const char *name;
- const char *trigger;
-} cpld_leds[] = {
- { "dm365evm::ds2", },
- { "dm365evm::ds3", },
- { "dm365evm::ds4", },
- { "dm365evm::ds5", },
- { "dm365evm::ds6", "nand-disk", },
- { "dm365evm::ds7", "mmc1", },
- { "dm365evm::ds8", "mmc0", },
- { "dm365evm::ds9", "heartbeat", },
-};
-
-static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
-{
- struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
- u8 reg = __raw_readb(cpld + CPLD_LEDS);
-
- if (b != LED_OFF)
- reg &= ~led->mask;
- else
- reg |= led->mask;
- __raw_writeb(reg, cpld + CPLD_LEDS);
-}
-
-static enum led_brightness cpld_led_get(struct led_classdev *cdev)
-{
- struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
- u8 reg = __raw_readb(cpld + CPLD_LEDS);
-
- return (reg & led->mask) ? LED_OFF : LED_FULL;
-}
-
-static int __init cpld_leds_init(void)
-{
- int i;
-
- if (!have_leds() || !cpld)
- return 0;
-
- /* setup LEDs */
- __raw_writeb(0xff, cpld + CPLD_LEDS);
- for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
- struct cpld_led *led;
-
- led = kzalloc(sizeof(*led), GFP_KERNEL);
- if (!led)
- break;
-
- led->cdev.name = cpld_leds[i].name;
- led->cdev.brightness_set = cpld_led_set;
- led->cdev.brightness_get = cpld_led_get;
- led->cdev.default_trigger = cpld_leds[i].trigger;
- led->mask = BIT(i);
-
- if (led_classdev_register(NULL, &led->cdev) < 0) {
- kfree(led);
- break;
- }
- }
-
- return 0;
-}
-/* run after subsys_initcall() for LEDs */
-fs_initcall(cpld_leds_init);
-
-
-static void __init evm_init_cpld(void)
-{
- u8 mux, resets;
- const char *label;
- struct clk *aemif_clk;
- int rc;
-
- /* Make sure we can configure the CPLD through CS1. Then
- * leave it on for later access to MMC and LED registers.
- */
- aemif_clk = clk_get(NULL, "aemif");
- if (IS_ERR(aemif_clk))
- return;
- clk_prepare_enable(aemif_clk);
-
- if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
- "cpld") == NULL)
- goto fail;
- cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
- if (!cpld) {
- release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
- SECTION_SIZE);
-fail:
- pr_err("ERROR: can't map CPLD\n");
- clk_disable_unprepare(aemif_clk);
- return;
- }
-
- /* External muxing for some signals */
- mux = 0;
-
- /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
- * NOTE: SW4 bus width setting must match!
- */
- if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
- /* external keypad mux */
- mux |= BIT(7);
-
- rc = platform_device_register(&davinci_aemif_device);
- if (rc)
- pr_warn("%s(): error registering the aemif device: %d\n",
- __func__, rc);
- } else {
- /* no OneNAND support yet */
- }
-
- /* Leave external chips in reset when unused. */
- resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
-
- /* Static video input config with SN74CBT16214 1-of-3 mux:
- * - port b1 == tvp7002 (mux lowbits == 1 or 6)
- * - port b2 == imager (mux lowbits == 2 or 7)
- * - port b3 == tvp5146 (mux lowbits == 5)
- *
- * Runtime switching could work too, with limitations.
- */
- if (have_imager()) {
- label = "HD imager";
- mux |= 2;
-
- /* externally mux MMC1/ENET/AIC33 to imager */
- mux |= BIT(6) | BIT(5) | BIT(3);
- } else {
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- /* we can use MMC1 ... */
- dm365evm_mmc_configure();
- davinci_setup_mmc(1, &dm365evm_mmc_config);
-
- /* ... and ENET ... */
- dm365evm_emac_configure();
- soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
- resets &= ~BIT(3);
-
- /* ... and AIC33 */
- resets &= ~BIT(1);
-
- if (have_tvp7002()) {
- mux |= 1;
- resets &= ~BIT(2);
- label = "tvp7002 HD";
- } else {
- /* default to tvp5146 */
- mux |= 5;
- resets &= ~BIT(0);
- label = "tvp5146 SD";
- }
- }
- __raw_writeb(mux, cpld + CPLD_MUX);
- __raw_writeb(resets, cpld + CPLD_RESETS);
- pr_info("EVM: %s video input\n", label);
-
- /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
-}
-
-static void __init dm365_evm_map_io(void)
-{
- dm365_init();
-}
-
-static struct spi_eeprom at25640 = {
- .byte_len = SZ_64K / 8,
- .name = "at25640",
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
- {
- .modalias = "at25",
- .platform_data = &at25640,
- .max_speed_hz = 10 * 1000 * 1000,
- .bus_num = 0,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-static __init void dm365_evm_init(void)
-{
- int ret;
-
- dm365_register_clocks();
-
- ret = dm365_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
- ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
- regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
- ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
-
- nvmem_add_cell_table(&davinci_nvmem_cell_table);
- nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
-
- evm_init_i2c();
- davinci_serial_init(dm365_serial_device);
-
- dm365evm_emac_configure();
- dm365evm_mmc_configure();
-
- davinci_setup_mmc(0, &dm365evm_mmc_config);
-
- dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
-
- /* maybe setup mmc1/etc ... _after_ mmc0 */
- evm_init_cpld();
-
-#ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
- dm365_init_asp();
-#elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
- dm365_init_vc();
-#endif
- dm365_init_rtc();
- dm365_init_ks(&dm365evm_ks_data);
-
- dm365_init_spi0(BIT(0), dm365_evm_spi_info,
- ARRAY_SIZE(dm365_evm_spi_info));
-}
-
-MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
- .atag_offset = 0x100,
- .map_io = dm365_evm_map_io,
- .init_irq = dm365_init_irq,
- .init_time = dm365_init_time,
- .init_machine = dm365_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
-
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
deleted file mode 100644
index cce3a621eb20..000000000000
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ /dev/null
@@ -1,932 +0,0 @@
-/*
- * TI DaVinci EVM board support
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/pcf857x.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/property.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/nvmem-provider.h>
-#include <linux/phy.h>
-#include <linux/clk.h>
-#include <linux/videodev2.h>
-#include <linux/v4l2-dv-timings.h>
-#include <linux/export.h>
-#include <linux/leds.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include <media/i2c/tvp514x.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/mux.h>
-#include <mach/serial.h>
-
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/ti-aemif.h>
-
-#include "davinci.h"
-#include "irqs.h"
-
-#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
-#define LXT971_PHY_ID (0x001378e2)
-#define LXT971_PHY_MASK (0xfffffff0)
-
-static struct mtd_partition davinci_evm_norflash_partitions[] = {
- /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
- {
- .name = "bootloader",
- .offset = 0,
- .size = 5 * SZ_64K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next 1 sectors */
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_64K,
- .mask_flags = 0,
- },
- /* kernel */
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0
- },
- /* file system */
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data davinci_evm_norflash_data = {
- .width = 2,
- .parts = davinci_evm_norflash_partitions,
- .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
-};
-
-/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
- * limits addresses to 16M, so using addresses past 16M will wrap */
-static struct resource davinci_evm_norflash_resource = {
- .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device davinci_evm_norflash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &davinci_evm_norflash_data,
- },
- .num_resources = 1,
- .resource = &davinci_evm_norflash_resource,
-};
-
-/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
- * It may used instead of the (default) NOR chip to boot, using TI's
- * tools to install the secondary boot loader (UBL) and U-Boot.
- */
-static struct mtd_partition davinci_evm_nandflash_partition[] = {
- /* Bootloader layout depends on whose u-boot is installed, but we
- * can hide all the details.
- * - block 0 for u-boot environment ... in mainline u-boot
- * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
- * - blocks 6...? for u-boot
- * - blocks 16..23 for u-boot environment ... in TI's u-boot
- */
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_256K + SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* Kernel */
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- },
- /* File system (older GIT kernels started this on the 5MB mark) */
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* A few blocks at end hold a flash BBT ... created by TI's CCS
- * using flashwriter_nand.out, but ignored by TI's versions of
- * Linux and u-boot. We boot faster by using them.
- */
-};
-
-static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
- .wsetup = 20,
- .wstrobe = 40,
- .whold = 20,
- .rsetup = 10,
- .rstrobe = 40,
- .rhold = 10,
- .ta = 40,
-};
-
-static struct davinci_nand_pdata davinci_evm_nandflash_data = {
- .core_chipsel = 0,
- .parts = davinci_evm_nandflash_partition,
- .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 1,
- .bbt_options = NAND_BBT_USE_FLASH,
- .timing = &davinci_evm_nandflash_timing,
-};
-
-static struct resource davinci_evm_nandflash_resource[] = {
- {
- .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
- .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource davinci_evm_aemif_resource[] = {
- {
- .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
- .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data davinci_evm_aemif_abus_data[] = {
- {
- .cs = 1,
- },
-};
-
-static struct platform_device davinci_evm_nandflash_devices[] = {
- {
- .name = "davinci_nand",
- .id = 0,
- .dev = {
- .platform_data = &davinci_evm_nandflash_data,
- },
- .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
- .resource = davinci_evm_nandflash_resource,
- },
-};
-
-static struct aemif_platform_data davinci_evm_aemif_pdata = {
- .abus_data = davinci_evm_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data),
- .sub_devices = davinci_evm_nandflash_devices,
- .num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices),
-};
-
-static struct platform_device davinci_evm_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &davinci_evm_aemif_pdata,
- },
- .resource = davinci_evm_aemif_resource,
- .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource),
-};
-
-static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device davinci_fb_device = {
- .name = "davincifb",
- .id = -1,
- .dev = {
- .dma_mask = &davinci_fb_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = 0,
-};
-
-static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-/* Inputs available at the TVP5146 */
-static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = TVP514X_STD_ALL,
- },
-};
-
-/*
- * this is the route info for connecting each input to decoder
- * ouput that goes to vpfe. There is a one to one correspondence
- * with tvp5146_inputs
- */
-static struct vpfe_route dm644xevm_tvp5146_routes[] = {
- {
- .input = INPUT_CVBS_VI2B,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
- {
- .input = INPUT_SVIDEO_VI2C_VI1C,
- .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-};
-
-static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
- {
- .name = "tvp5146",
- .grp_id = 0,
- .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
- .inputs = dm644xevm_tvp5146_inputs,
- .routes = dm644xevm_tvp5146_routes,
- .can_route = 1,
- .ccdc_if_params = {
- .if_type = VPFE_BT656,
- .hdpol = VPFE_PINPOL_POSITIVE,
- .vdpol = VPFE_PINPOL_POSITIVE,
- },
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &dm644xevm_tvp5146_pdata,
- },
- },
-};
-
-static struct vpfe_config dm644xevm_capture_cfg = {
- .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
- .i2c_adapter_id = 1,
- .sub_devs = dm644xevm_vpfe_sub_devs,
- .card_name = "DM6446 EVM",
- .ccdc = "DM6446 CCDC",
-};
-
-static struct platform_device rtc_dev = {
- .name = "rtc_davinci_evm",
- .id = -1,
-};
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_I2C
-/*
- * I2C GPIO expanders
- */
-
-#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
-
-
-/* U2 -- LEDs */
-
-static struct gpio_led evm_leds[] = {
- { .name = "DS8", .active_low = 1,
- .default_trigger = "heartbeat", },
- { .name = "DS7", .active_low = 1, },
- { .name = "DS6", .active_low = 1, },
- { .name = "DS5", .active_low = 1, },
- { .name = "DS4", .active_low = 1, },
- { .name = "DS3", .active_low = 1, },
- { .name = "DS2", .active_low = 1,
- .default_trigger = "mmc0", },
- { .name = "DS1", .active_low = 1,
- .default_trigger = "disk-activity", },
-};
-
-static const struct gpio_led_platform_data evm_led_data = {
- .num_leds = ARRAY_SIZE(evm_leds),
- .leds = evm_leds,
-};
-
-static struct platform_device *evm_led_dev;
-
-static int
-evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
-{
- struct gpio_led *leds = evm_leds;
- int status;
-
- while (ngpio--) {
- leds->gpio = gpio++;
- leds++;
- }
-
- /* what an extremely annoying way to be forced to handle
- * device unregistration ...
- */
- evm_led_dev = platform_device_alloc("leds-gpio", 0);
- platform_device_add_data(evm_led_dev,
- &evm_led_data, sizeof evm_led_data);
-
- evm_led_dev->dev.parent = &client->dev;
- status = platform_device_add(evm_led_dev);
- if (status < 0) {
- platform_device_put(evm_led_dev);
- evm_led_dev = NULL;
- }
- return status;
-}
-
-static int
-evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
-{
- if (evm_led_dev) {
- platform_device_unregister(evm_led_dev);
- evm_led_dev = NULL;
- }
- return 0;
-}
-
-static struct pcf857x_platform_data pcf_data_u2 = {
- .gpio_base = PCF_Uxx_BASE(0),
- .setup = evm_led_setup,
- .teardown = evm_led_teardown,
-};
-
-
-/* U18 - A/V clock generator and user switch */
-
-static int sw_gpio;
-
-static ssize_t
-sw_show(struct device *d, struct device_attribute *a, char *buf)
-{
- char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
-
- strcpy(buf, s);
- return strlen(s);
-}
-
-static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
-
-static int
-evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
-{
- int status;
-
- /* export dip switch option */
- sw_gpio = gpio + 7;
- status = gpio_request(sw_gpio, "user_sw");
- if (status == 0)
- status = gpio_direction_input(sw_gpio);
- if (status == 0)
- status = device_create_file(&client->dev, &dev_attr_user_sw);
- else
- gpio_free(sw_gpio);
- if (status != 0)
- sw_gpio = -EINVAL;
-
- /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
- gpio_request(gpio + 3, "pll_fs2");
- gpio_direction_output(gpio + 3, 0);
-
- gpio_request(gpio + 2, "pll_fs1");
- gpio_direction_output(gpio + 2, 0);
-
- gpio_request(gpio + 1, "pll_sr");
- gpio_direction_output(gpio + 1, 0);
-
- return 0;
-}
-
-static int
-evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
-{
- gpio_free(gpio + 1);
- gpio_free(gpio + 2);
- gpio_free(gpio + 3);
-
- if (sw_gpio > 0) {
- device_remove_file(&client->dev, &dev_attr_user_sw);
- gpio_free(sw_gpio);
- }
- return 0;
-}
-
-static struct pcf857x_platform_data pcf_data_u18 = {
- .gpio_base = PCF_Uxx_BASE(1),
- .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
- .setup = evm_u18_setup,
- .teardown = evm_u18_teardown,
-};
-
-
-/* U35 - various I/O signals used to manage USB, CF, ATA, etc */
-
-static int
-evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
-{
- /* p0 = nDRV_VBUS (initial: don't supply it) */
- gpio_request(gpio + 0, "nDRV_VBUS");
- gpio_direction_output(gpio + 0, 1);
-
- /* p1 = VDDIMX_EN */
- gpio_request(gpio + 1, "VDDIMX_EN");
- gpio_direction_output(gpio + 1, 1);
-
- /* p2 = VLYNQ_EN */
- gpio_request(gpio + 2, "VLYNQ_EN");
- gpio_direction_output(gpio + 2, 1);
-
- /* p3 = n3V3_CF_RESET (initial: stay in reset) */
- gpio_request(gpio + 3, "nCF_RESET");
- gpio_direction_output(gpio + 3, 0);
-
- /* (p4 unused) */
-
- /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
- gpio_request(gpio + 5, "WLAN_RESET");
- gpio_direction_output(gpio + 5, 1);
-
- /* p6 = nATA_SEL (initial: select) */
- gpio_request(gpio + 6, "nATA_SEL");
- gpio_direction_output(gpio + 6, 0);
-
- /* p7 = nCF_SEL (initial: deselect) */
- gpio_request(gpio + 7, "nCF_SEL");
- gpio_direction_output(gpio + 7, 1);
-
- return 0;
-}
-
-static int
-evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
-{
- gpio_free(gpio + 7);
- gpio_free(gpio + 6);
- gpio_free(gpio + 5);
- gpio_free(gpio + 3);
- gpio_free(gpio + 2);
- gpio_free(gpio + 1);
- gpio_free(gpio + 0);
- return 0;
-}
-
-static struct pcf857x_platform_data pcf_data_u35 = {
- .gpio_base = PCF_Uxx_BASE(2),
- .setup = evm_u35_setup,
- .teardown = evm_u35_teardown,
-};
-
-/*----------------------------------------------------------------------*/
-
-/* Most of this EEPROM is unused, but U-Boot uses some data:
- * - 0x7f00, 6 bytes Ethernet Address
- * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
- * - ... newer boards may have more
- */
-
-static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x7f00,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = dm644evm_nvmem_cells,
- .ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 64),
- { }
-};
-
-static const struct software_node eeprom_node = {
- .properties = eeprom_properties,
-};
-
-/*
- * MSP430 supports RTC, card detection, input from IR remote, and
- * a bit more. It triggers interrupts on GPIO(7) from pressing
- * buttons on the IR remote, and for card detect switches.
- */
-static struct i2c_client *dm6446evm_msp;
-
-static int dm6446evm_msp_probe(struct i2c_client *client)
-{
- dm6446evm_msp = client;
- return 0;
-}
-
-static int dm6446evm_msp_remove(struct i2c_client *client)
-{
- dm6446evm_msp = NULL;
- return 0;
-}
-
-static const struct i2c_device_id dm6446evm_msp_ids[] = {
- { "dm6446evm_msp", 0, },
- { /* end of list */ },
-};
-
-static struct i2c_driver dm6446evm_msp_driver = {
- .driver.name = "dm6446evm_msp",
- .id_table = dm6446evm_msp_ids,
- .probe_new = dm6446evm_msp_probe,
- .remove = dm6446evm_msp_remove,
-};
-
-static int dm6444evm_msp430_get_pins(void)
-{
- static const char txbuf[2] = { 2, 4, };
- char buf[4];
- struct i2c_msg msg[2] = {
- {
- .flags = 0,
- .len = 2,
- .buf = (void __force *)txbuf,
- },
- {
- .flags = I2C_M_RD,
- .len = 4,
- .buf = buf,
- },
- };
- int status;
-
- if (!dm6446evm_msp)
- return -ENXIO;
-
- msg[0].addr = dm6446evm_msp->addr;
- msg[1].addr = dm6446evm_msp->addr;
-
- /* Command 4 == get input state, returns port 2 and port3 data
- * S Addr W [A] len=2 [A] cmd=4 [A]
- * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
- */
- status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
- if (status < 0)
- return status;
-
- dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
-
- return (buf[3] << 8) | buf[2];
-}
-
-static int dm6444evm_mmc_get_cd(int module)
-{
- int status = dm6444evm_msp430_get_pins();
-
- return (status < 0) ? status : !(status & BIT(1));
-}
-
-static int dm6444evm_mmc_get_ro(int module)
-{
- int status = dm6444evm_msp430_get_pins();
-
- return (status < 0) ? status : status & BIT(6 + 8);
-}
-
-static struct davinci_mmc_config dm6446evm_mmc_config = {
- .get_cd = dm6444evm_mmc_get_cd,
- .get_ro = dm6444evm_mmc_get_ro,
- .wires = 4,
-};
-
-static struct i2c_board_info __initdata i2c_info[] = {
- {
- I2C_BOARD_INFO("dm6446evm_msp", 0x23),
- },
- {
- I2C_BOARD_INFO("pcf8574", 0x38),
- .platform_data = &pcf_data_u2,
- },
- {
- I2C_BOARD_INFO("pcf8574", 0x39),
- .platform_data = &pcf_data_u18,
- },
- {
- I2C_BOARD_INFO("pcf8574", 0x3a),
- .platform_data = &pcf_data_u35,
- },
- {
- I2C_BOARD_INFO("24c256", 0x50),
- .swnode = &eeprom_node,
- },
- {
- I2C_BOARD_INFO("tlv320aic33", 0x1b),
- },
-};
-
-#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
-#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
-
-static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
- .dev_id = "i2c_davinci.1",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- { }
- },
-};
-
-/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
- * which requires 100 usec of idle bus after i2c writes sent to it.
- */
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 20 /* kHz */,
- .bus_delay = 100 /* usec */,
- .gpio_recovery = true,
-};
-
-static void __init evm_init_i2c(void)
-{
- gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
- davinci_init_i2c(&i2c_pdata);
- i2c_add_driver(&dm6446evm_msp_driver);
- i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
-}
-#endif
-
-/* Fixed regulator support */
-static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
- /* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
- REGULATOR_SUPPLY("AVDD", "1-001b"),
- REGULATOR_SUPPLY("DRVDD", "1-001b"),
-};
-
-static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
- /* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
- REGULATOR_SUPPLY("IOVDD", "1-001b"),
- REGULATOR_SUPPLY("DVDD", "1-001b"),
-};
-
-#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-/* venc standard timings */
-static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
- {
- .name = "ntsc",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_NTSC,
- .interlaced = 1,
- .xres = 720,
- .yres = 480,
- .aspect = {11, 10},
- .fps = {30000, 1001},
- .left_margin = 0x79,
- .upper_margin = 0x10,
- },
- {
- .name = "pal",
- .timings_type = VPBE_ENC_STD,
- .std_id = V4L2_STD_PAL,
- .interlaced = 1,
- .xres = 720,
- .yres = 576,
- .aspect = {54, 59},
- .fps = {25, 1},
- .left_margin = 0x7e,
- .upper_margin = 0x16,
- },
-};
-
-/* venc dv preset timings */
-static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
- {
- .name = "480p59_94",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
- .interlaced = 0,
- .xres = 720,
- .yres = 480,
- .aspect = {1, 1},
- .fps = {5994, 100},
- .left_margin = 0x80,
- .upper_margin = 0x20,
- },
- {
- .name = "576p50",
- .timings_type = VPBE_ENC_DV_TIMINGS,
- .dv_timings = V4L2_DV_BT_CEA_720X576P50,
- .interlaced = 0,
- .xres = 720,
- .yres = 576,
- .aspect = {1, 1},
- .fps = {50, 1},
- .left_margin = 0x7e,
- .upper_margin = 0x30,
- },
-};
-
-/*
- * The outputs available from VPBE + encoders. Keep the order same
- * as that of encoders. First those from venc followed by that from
- * encoders. Index in the output refers to index on a particular encoder.
- * Driver uses this index to pass it to encoder when it supports more
- * than one output. Userspace applications use index of the array to
- * set an output.
- */
-static struct vpbe_output dm644xevm_vpbe_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = VENC_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "ntsc",
- .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
- .modes = dm644xevm_enc_std_timing,
- },
- {
- .output = {
- .index = 1,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
- .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
- .default_mode = "480p59_94",
- .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
- .modes = dm644xevm_enc_preset_timing,
- },
-};
-
-static struct vpbe_config dm644xevm_display_cfg = {
- .module_name = "dm644x-vpbe-display",
- .i2c_adapter_id = 1,
- .osd = {
- .module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
- },
- .venc = {
- .module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
- },
- .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
- .outputs = dm644xevm_vpbe_outputs,
-};
-
-static struct platform_device *davinci_evm_devices[] __initdata = {
- &davinci_fb_device,
- &rtc_dev,
-};
-
-static void __init
-davinci_evm_map_io(void)
-{
- dm644x_init();
-}
-
-static int davinci_phy_fixup(struct phy_device *phydev)
-{
- unsigned int control;
- /* CRITICAL: Fix for increasing PHY signal drive strength for
- * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
- * signal strength was low causing TX to fail randomly. The
- * fix is to Set bit 11 (Increased MII drive strength) of PHY
- * register 26 (Digital Config register) on this phy. */
- control = phy_read(phydev, 26);
- phy_write(phydev, 26, (control | 0x800));
- return 0;
-}
-
-#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
- IS_ENABLED(CONFIG_PATA_BK3710))
-
-#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
-
-#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
-
-#define GPIO_nVBUS_DRV 160
-
-static struct gpiod_lookup_table dm644evm_usb_gpio_table = {
- .dev_id = "musb-davinci",
- .table = {
- GPIO_LOOKUP("davinci_gpio", GPIO_nVBUS_DRV, NULL,
- GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static __init void davinci_evm_init(void)
-{
- int ret;
- struct clk *aemif_clk;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- dm644x_register_clocks();
-
- regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
- ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
- regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
- ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
-
- dm644x_init_devices();
-
- ret = dm644x_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- aemif_clk = clk_get(NULL, "aemif");
- clk_prepare_enable(aemif_clk);
-
- if (HAS_ATA) {
- if (HAS_NAND || HAS_NOR)
- pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
- "\tDisable IDE for NAND/NOR support\n");
- davinci_init_ide();
- } else if (HAS_NAND || HAS_NOR) {
- davinci_cfg_reg(DM644X_HPIEN_DISABLE);
- davinci_cfg_reg(DM644X_ATAEN_DISABLE);
-
- /* only one device will be jumpered and detected */
- if (HAS_NAND) {
- platform_device_register(&davinci_evm_aemif_device);
-#ifdef CONFIG_I2C
- evm_leds[7].default_trigger = "nand-disk";
-#endif
- if (HAS_NOR)
- pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
- } else if (HAS_NOR)
- platform_device_register(&davinci_evm_norflash_device);
- }
-
- platform_add_devices(davinci_evm_devices,
- ARRAY_SIZE(davinci_evm_devices));
-#ifdef CONFIG_I2C
- nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
- nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
- evm_init_i2c();
- davinci_setup_mmc(0, &dm6446evm_mmc_config);
-#endif
- dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
-
- davinci_serial_init(dm644x_serial_device);
- dm644x_init_asp();
-
- /* irlml6401 switches over 1A, in under 8 msec */
- gpiod_add_lookup_table(&dm644evm_usb_gpio_table);
- davinci_setup_usb(1000, 8);
-
- if (IS_BUILTIN(CONFIG_PHYLIB)) {
- soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
- /* Register the fixup for PHY on DaVinci */
- phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
- davinci_phy_fixup);
- }
-}
-
-MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
- /* Maintainer: MontaVista Software <source@mvista.com> */
- .atag_offset = 0x100,
- .map_io = davinci_evm_map_io,
- .init_irq = dm644x_init_irq,
- .init_time = dm644x_init_time,
- .init_machine = davinci_evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
deleted file mode 100644
index ee91d81ebbfd..000000000000
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ /dev/null
@@ -1,876 +0,0 @@
-/*
- * TI DaVinci DM646X EVM board
- *
- * Derived from: arch/arm/mach-davinci/board-evm.c
- * Copyright (C) 2006 Texas Instruments.
- *
- * (C) 2007-2008, MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- */
-
-/**************************************************************************
- * Included Files
- **************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/property.h>
-#include <linux/platform_data/pcf857x.h>
-#include <linux/platform_data/ti-aemif.h>
-
-#include <media/i2c/tvp514x.h>
-#include <media/i2c/adv7343.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/nvmem-provider.h>
-#include <linux/clk.h>
-#include <linux/export.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/serial.h>
-
-#include "davinci.h"
-#include "irqs.h"
-
-#define NAND_BLOCK_SIZE SZ_128K
-
-/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
- * and U-Boot environment this avoids dependency on any particular combination
- * of UBL, U-Boot or flashing tools etc.
- */
-static struct mtd_partition davinci_nand_partitions[] = {
- {
- /* UBL, U-Boot with environment */
- .name = "bootloader",
- .offset = MTDPART_OFS_APPEND,
- .size = 16 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
-};
-
-static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
- .wsetup = 29,
- .wstrobe = 24,
- .whold = 14,
- .rsetup = 19,
- .rstrobe = 33,
- .rhold = 0,
- .ta = 29,
-};
-
-static struct davinci_nand_pdata davinci_nand_data = {
- .core_chipsel = 0,
- .mask_cle = 0x80000,
- .mask_ale = 0x40000,
- .parts = davinci_nand_partitions,
- .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 1,
- .options = 0,
-};
-
-static struct resource davinci_nand_resources[] = {
- {
- .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
- .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
- .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(davinci_nand_resources),
- .resource = davinci_nand_resources,
- .dev = {
- .platform_data = &davinci_nand_data,
- },
- },
-};
-
-static struct resource davinci_aemif_resources[] = {
- {
- .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
- .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data davinci_aemif_abus_data[] = {
- {
- .cs = 1,
- },
-};
-
-static struct aemif_platform_data davinci_aemif_pdata = {
- .abus_data = davinci_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(davinci_aemif_abus_data),
- .sub_devices = davinci_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
-};
-
-static struct platform_device davinci_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &davinci_aemif_pdata,
- },
- .resource = davinci_aemif_resources,
- .num_resources = ARRAY_SIZE(davinci_aemif_resources),
-};
-
-#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
- IS_ENABLED(CONFIG_PATA_BK3710))
-
-#ifdef CONFIG_I2C
-/* CPLD Register 0 bits to control ATA */
-#define DM646X_EVM_ATA_RST BIT(0)
-#define DM646X_EVM_ATA_PWD BIT(1)
-
-/* CPLD Register 0 Client: used for I/O Control */
-static int cpld_reg0_probe(struct i2c_client *client)
-{
- if (HAS_ATA) {
- u8 data;
- struct i2c_msg msg[2] = {
- {
- .addr = client->addr,
- .flags = I2C_M_RD,
- .len = 1,
- .buf = &data,
- },
- {
- .addr = client->addr,
- .flags = 0,
- .len = 1,
- .buf = &data,
- },
- };
-
- /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
- i2c_transfer(client->adapter, msg, 1);
- data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
- i2c_transfer(client->adapter, msg + 1, 1);
- }
-
- return 0;
-}
-
-static const struct i2c_device_id cpld_reg_ids[] = {
- { "cpld_reg0", 0, },
- { },
-};
-
-static struct i2c_driver dm6467evm_cpld_driver = {
- .driver.name = "cpld_reg0",
- .id_table = cpld_reg_ids,
- .probe_new = cpld_reg0_probe,
-};
-
-/* LEDS */
-
-static struct gpio_led evm_leds[] = {
- { .name = "DS1", .active_low = 1, },
- { .name = "DS2", .active_low = 1, },
- { .name = "DS3", .active_low = 1, },
- { .name = "DS4", .active_low = 1, },
-};
-
-static const struct gpio_led_platform_data evm_led_data = {
- .num_leds = ARRAY_SIZE(evm_leds),
- .leds = evm_leds,
-};
-
-static struct platform_device *evm_led_dev;
-
-static int evm_led_setup(struct i2c_client *client, int gpio,
- unsigned int ngpio, void *c)
-{
- struct gpio_led *leds = evm_leds;
- int status;
-
- while (ngpio--) {
- leds->gpio = gpio++;
- leds++;
- }
-
- evm_led_dev = platform_device_alloc("leds-gpio", 0);
- platform_device_add_data(evm_led_dev, &evm_led_data,
- sizeof(evm_led_data));
-
- evm_led_dev->dev.parent = &client->dev;
- status = platform_device_add(evm_led_dev);
- if (status < 0) {
- platform_device_put(evm_led_dev);
- evm_led_dev = NULL;
- }
- return status;
-}
-
-static int evm_led_teardown(struct i2c_client *client, int gpio,
- unsigned ngpio, void *c)
-{
- if (evm_led_dev) {
- platform_device_unregister(evm_led_dev);
- evm_led_dev = NULL;
- }
- return 0;
-}
-
-static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
-
-static int evm_sw_setup(struct i2c_client *client, int gpio,
- unsigned ngpio, void *c)
-{
- int status;
- int i;
- char label[10];
-
- for (i = 0; i < 4; ++i) {
- snprintf(label, 10, "user_sw%d", i);
- status = gpio_request(gpio, label);
- if (status)
- goto out_free;
- evm_sw_gpio[i] = gpio++;
-
- status = gpio_direction_input(evm_sw_gpio[i]);
- if (status)
- goto out_free;
-
- status = gpio_export(evm_sw_gpio[i], 0);
- if (status)
- goto out_free;
- }
- return 0;
-
-out_free:
- for (i = 0; i < 4; ++i) {
- if (evm_sw_gpio[i] != -EINVAL) {
- gpio_free(evm_sw_gpio[i]);
- evm_sw_gpio[i] = -EINVAL;
- }
- }
- return status;
-}
-
-static int evm_sw_teardown(struct i2c_client *client, int gpio,
- unsigned ngpio, void *c)
-{
- int i;
-
- for (i = 0; i < 4; ++i) {
- if (evm_sw_gpio[i] != -EINVAL) {
- gpio_unexport(evm_sw_gpio[i]);
- gpio_free(evm_sw_gpio[i]);
- evm_sw_gpio[i] = -EINVAL;
- }
- }
- return 0;
-}
-
-static int evm_pcf_setup(struct i2c_client *client, int gpio,
- unsigned int ngpio, void *c)
-{
- int status;
-
- if (ngpio < 8)
- return -EINVAL;
-
- status = evm_sw_setup(client, gpio, 4, c);
- if (status)
- return status;
-
- return evm_led_setup(client, gpio+4, 4, c);
-}
-
-static int evm_pcf_teardown(struct i2c_client *client, int gpio,
- unsigned int ngpio, void *c)
-{
- BUG_ON(ngpio < 8);
-
- evm_sw_teardown(client, gpio, 4, c);
- evm_led_teardown(client, gpio+4, 4, c);
-
- return 0;
-}
-
-static struct pcf857x_platform_data pcf_data = {
- .gpio_base = DAVINCI_N_GPIO+1,
- .setup = evm_pcf_setup,
- .teardown = evm_pcf_teardown,
-};
-
-/* Most of this EEPROM is unused, but U-Boot uses some data:
- * - 0x7f00, 6 bytes Ethernet Address
- * - ... newer boards may have more
- */
-
-static struct nvmem_cell_info dm646x_evm_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x7f00,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table dm646x_evm_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = dm646x_evm_nvmem_cells,
- .ncells = ARRAY_SIZE(dm646x_evm_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup dm646x_evm_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 64),
- { }
-};
-
-static const struct software_node eeprom_node = {
- .properties = eeprom_properties,
-};
-#endif
-
-static u8 dm646x_iis_serializer_direction[] = {
- TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
-};
-
-static u8 dm646x_dit_serializer_direction[] = {
- TX_MODE,
-};
-
-static struct snd_platform_data dm646x_evm_snd_data[] = {
- {
- .tx_dma_offset = 0x400,
- .rx_dma_offset = 0x400,
- .op_mode = DAVINCI_MCASP_IIS_MODE,
- .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
- .tdm_slots = 2,
- .serial_dir = dm646x_iis_serializer_direction,
- .asp_chan_q = EVENTQ_0,
- },
- {
- .tx_dma_offset = 0x400,
- .rx_dma_offset = 0,
- .op_mode = DAVINCI_MCASP_DIT_MODE,
- .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
- .tdm_slots = 32,
- .serial_dir = dm646x_dit_serializer_direction,
- .asp_chan_q = EVENTQ_0,
- },
-};
-
-#ifdef CONFIG_I2C
-static struct i2c_client *cpld_client;
-
-static int cpld_video_probe(struct i2c_client *client)
-{
- cpld_client = client;
- return 0;
-}
-
-static int cpld_video_remove(struct i2c_client *client)
-{
- cpld_client = NULL;
- return 0;
-}
-
-static const struct i2c_device_id cpld_video_id[] = {
- { "cpld_video", 0 },
- { }
-};
-
-static struct i2c_driver cpld_video_driver = {
- .driver = {
- .name = "cpld_video",
- },
- .probe_new = cpld_video_probe,
- .remove = cpld_video_remove,
- .id_table = cpld_video_id,
-};
-
-static void evm_init_cpld(void)
-{
- i2c_add_driver(&cpld_video_driver);
-}
-
-static struct i2c_board_info __initdata i2c_info[] = {
- {
- I2C_BOARD_INFO("24c256", 0x50),
- .swnode = &eeprom_node,
- },
- {
- I2C_BOARD_INFO("pcf8574a", 0x38),
- .platform_data = &pcf_data,
- },
- {
- I2C_BOARD_INFO("cpld_reg0", 0x3a),
- },
- {
- I2C_BOARD_INFO("tlv320aic33", 0x18),
- },
- {
- I2C_BOARD_INFO("cpld_video", 0x3b),
- },
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 100 /* kHz */,
- .bus_delay = 0 /* usec */,
-};
-
-#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
-#define VCH2CLK_SYSCLK8 (BIT(9))
-#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
-#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
-#define VCH3CLK_SYSCLK8 (BIT(13))
-#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
-
-#define VIDCH2CLK (BIT(10))
-#define VIDCH3CLK (BIT(11))
-#define VIDCH1CLK (BIT(4))
-#define TVP7002_INPUT (BIT(4))
-#define TVP5147_INPUT (~BIT(4))
-#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
-#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
-#define TVP5147_CH0 "tvp514x-0"
-#define TVP5147_CH1 "tvp514x-1"
-
-/* spin lock for updating above registers */
-static spinlock_t vpif_reg_lock;
-
-static int set_vpif_clock(int mux_mode, int hd)
-{
- unsigned long flags;
- unsigned int value;
- int val = 0;
- int err = 0;
-
- if (!cpld_client)
- return -ENXIO;
-
- /* disable the clock */
- spin_lock_irqsave(&vpif_reg_lock, flags);
- value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
- value |= (VIDCH3CLK | VIDCH2CLK);
- __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
- spin_unlock_irqrestore(&vpif_reg_lock, flags);
-
- val = i2c_smbus_read_byte(cpld_client);
- if (val < 0)
- return val;
-
- if (mux_mode == 1)
- val &= ~0x40;
- else
- val |= 0x40;
-
- err = i2c_smbus_write_byte(cpld_client, val);
- if (err)
- return err;
-
- value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
- value &= ~(VCH2CLK_MASK);
- value &= ~(VCH3CLK_MASK);
-
- if (hd >= 1)
- value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
- else
- value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
-
- __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
-
- spin_lock_irqsave(&vpif_reg_lock, flags);
- value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
- /* enable the clock */
- value &= ~(VIDCH3CLK | VIDCH2CLK);
- __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
- spin_unlock_irqrestore(&vpif_reg_lock, flags);
-
- return 0;
-}
-
-static struct vpif_subdev_info dm646x_vpif_subdev[] = {
- {
- .name = "adv7343",
- .board_info = {
- I2C_BOARD_INFO("adv7343", 0x2a),
- },
- },
- {
- .name = "ths7303",
- .board_info = {
- I2C_BOARD_INFO("ths7303", 0x2c),
- },
- },
-};
-
-static const struct vpif_output dm6467_ch0_outputs[] = {
- {
- .output = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_STD,
- .std = V4L2_STD_ALL,
- },
- .subdev_name = "adv7343",
- .output_route = ADV7343_COMPOSITE_ID,
- },
- {
- .output = {
- .index = 1,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
- .subdev_name = "adv7343",
- .output_route = ADV7343_COMPONENT_ID,
- },
- {
- .output = {
- .index = 2,
- .name = "S-Video",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .capabilities = V4L2_OUT_CAP_STD,
- .std = V4L2_STD_ALL,
- },
- .subdev_name = "adv7343",
- .output_route = ADV7343_SVIDEO_ID,
- },
-};
-
-static struct vpif_display_config dm646x_vpif_display_config = {
- .set_clock = set_vpif_clock,
- .subdevinfo = dm646x_vpif_subdev,
- .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
- .i2c_adapter_id = 1,
- .chan_config[0] = {
- .outputs = dm6467_ch0_outputs,
- .output_count = ARRAY_SIZE(dm6467_ch0_outputs),
- },
- .card_name = "DM646x EVM Video Display",
-};
-
-/**
- * setup_vpif_input_path()
- * @channel: channel id (0 - CH0, 1 - CH1)
- * @sub_dev_name: ptr sub device name
- *
- * This will set vpif input to capture data from tvp514x or
- * tvp7002.
- */
-static int setup_vpif_input_path(int channel, const char *sub_dev_name)
-{
- int err = 0;
- int val;
-
- /* for channel 1, we don't do anything */
- if (channel != 0)
- return 0;
-
- if (!cpld_client)
- return -ENXIO;
-
- val = i2c_smbus_read_byte(cpld_client);
- if (val < 0)
- return val;
-
- if (!strcmp(sub_dev_name, TVP5147_CH0) ||
- !strcmp(sub_dev_name, TVP5147_CH1))
- val &= TVP5147_INPUT;
- else
- val |= TVP7002_INPUT;
-
- err = i2c_smbus_write_byte(cpld_client, val);
- if (err)
- return err;
- return 0;
-}
-
-/**
- * setup_vpif_input_channel_mode()
- * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
- *
- * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
- */
-static int setup_vpif_input_channel_mode(int mux_mode)
-{
- unsigned long flags;
- int err = 0;
- int val;
- u32 value;
-
- if (!cpld_client)
- return -ENXIO;
-
- val = i2c_smbus_read_byte(cpld_client);
- if (val < 0)
- return val;
-
- spin_lock_irqsave(&vpif_reg_lock, flags);
- value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
- if (mux_mode) {
- val &= VPIF_INPUT_TWO_CHANNEL;
- value |= VIDCH1CLK;
- } else {
- val |= VPIF_INPUT_ONE_CHANNEL;
- value &= ~VIDCH1CLK;
- }
- __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
- spin_unlock_irqrestore(&vpif_reg_lock, flags);
-
- err = i2c_smbus_write_byte(cpld_client, val);
- if (err)
- return err;
-
- return 0;
-}
-
-static struct tvp514x_platform_data tvp5146_pdata = {
- .clk_polarity = 0,
- .hs_polarity = 1,
- .vs_polarity = 1
-};
-
-#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
-
-static struct vpif_subdev_info vpif_capture_sdev_info[] = {
- {
- .name = TVP5147_CH0,
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5d),
- .platform_data = &tvp5146_pdata,
- },
- },
- {
- .name = TVP5147_CH1,
- .board_info = {
- I2C_BOARD_INFO("tvp5146", 0x5c),
- .platform_data = &tvp5146_pdata,
- },
- },
-};
-
-static struct vpif_input dm6467_ch0_inputs[] = {
- {
- .input = {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_STD,
- .std = TVP514X_STD_ALL,
- },
- .subdev_name = TVP5147_CH0,
- .input_route = INPUT_CVBS_VI2B,
- .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-};
-
-static struct vpif_input dm6467_ch1_inputs[] = {
- {
- .input = {
- .index = 0,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_STD,
- .std = TVP514X_STD_ALL,
- },
- .subdev_name = TVP5147_CH1,
- .input_route = INPUT_SVIDEO_VI2C_VI1C,
- .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
- },
-};
-
-static struct vpif_capture_config dm646x_vpif_capture_cfg = {
- .setup_input_path = setup_vpif_input_path,
- .setup_input_channel_mode = setup_vpif_input_channel_mode,
- .subdev_info = vpif_capture_sdev_info,
- .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
- .i2c_adapter_id = 1,
- .chan_config[0] = {
- .inputs = dm6467_ch0_inputs,
- .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
- .vpif_if = {
- .if_type = VPIF_IF_BT656,
- .hd_pol = 1,
- .vd_pol = 1,
- .fid_pol = 0,
- },
- },
- .chan_config[1] = {
- .inputs = dm6467_ch1_inputs,
- .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
- .vpif_if = {
- .if_type = VPIF_IF_BT656,
- .hd_pol = 1,
- .vd_pol = 1,
- .fid_pol = 0,
- },
- },
- .card_name = "DM646x EVM Video Capture",
-};
-
-static void __init evm_init_video(void)
-{
- spin_lock_init(&vpif_reg_lock);
-
- dm646x_setup_vpif(&dm646x_vpif_display_config,
- &dm646x_vpif_capture_cfg);
-}
-
-static void __init evm_init_i2c(void)
-{
- davinci_init_i2c(&i2c_pdata);
- i2c_add_driver(&dm6467evm_cpld_driver);
- i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
- evm_init_cpld();
- evm_init_video();
-}
-#endif
-
-#define DM646X_REF_FREQ 27000000
-#define DM646X_AUX_FREQ 24000000
-#define DM6467T_EVM_REF_FREQ 33000000
-
-static void __init davinci_map_io(void)
-{
- dm646x_init();
-}
-
-static void __init dm646x_evm_init_time(void)
-{
- dm646x_init_time(DM646X_REF_FREQ, DM646X_AUX_FREQ);
-}
-
-static void __init dm6467t_evm_init_time(void)
-{
- dm646x_init_time(DM6467T_EVM_REF_FREQ, DM646X_AUX_FREQ);
-}
-
-#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
-/*
- * The following EDMA channels/slots are not being used by drivers (for
- * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
- * reserved for codecs on the DSP side.
- */
-static const s16 dm646x_dma_rsv_chans[][2] = {
- /* (offset, number) */
- { 0, 4},
- {13, 3},
- {24, 4},
- {30, 2},
- {54, 3},
- {-1, -1}
-};
-
-static const s16 dm646x_dma_rsv_slots[][2] = {
- /* (offset, number) */
- { 0, 4},
- {13, 3},
- {24, 4},
- {30, 2},
- {54, 3},
- {128, 384},
- {-1, -1}
-};
-
-static struct edma_rsv_info dm646x_edma_rsv[] = {
- {
- .rsv_chans = dm646x_dma_rsv_chans,
- .rsv_slots = dm646x_dma_rsv_slots,
- },
-};
-
-static __init void evm_init(void)
-{
- int ret;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- dm646x_register_clocks();
-
- ret = dm646x_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
-#ifdef CONFIG_I2C
- nvmem_add_cell_table(&dm646x_evm_nvmem_cell_table);
- nvmem_add_cell_lookups(&dm646x_evm_nvmem_cell_lookup, 1);
- evm_init_i2c();
-#endif
-
- davinci_serial_init(dm646x_serial_device);
- dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
- dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
-
- if (machine_is_davinci_dm6467tevm())
- davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
-
- if (platform_device_register(&davinci_aemif_device))
- pr_warn("%s: Cannot register AEMIF device.\n", __func__);
-
- dm646x_init_edma(dm646x_edma_rsv);
-
- if (HAS_ATA)
- davinci_init_ide();
-
- soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
-}
-
-MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
- .atag_offset = 0x100,
- .map_io = davinci_map_io,
- .init_irq = dm646x_init_irq,
- .init_time = dm646x_evm_init_time,
- .init_machine = evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
-
-MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
- .atag_offset = 0x100,
- .map_io = davinci_map_io,
- .init_irq = dm646x_init_irq,
- .init_time = dm6467t_evm_init_time,
- .init_machine = evm_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
-
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
deleted file mode 100644
index 2127969beb96..000000000000
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/*
- * Critical Link MityOMAP-L138 SoM
- *
- * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of
- * any kind, whether express or implied.
- */
-
-#define pr_fmt(fmt) "MityOMAPL138: " fmt
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/platform_device.h>
-#include <linux/property.h>
-#include <linux/mtd/partitions.h>
-#include <linux/notifier.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/nvmem-provider.h>
-#include <linux/regulator/machine.h>
-#include <linux/i2c.h>
-#include <linux/etherdevice.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/common.h>
-#include <mach/da8xx.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <mach/mux.h>
-#include <linux/platform_data/spi-davinci.h>
-
-#define MITYOMAPL138_PHY_ID ""
-
-#define FACTORY_CONFIG_MAGIC 0x012C0138
-#define FACTORY_CONFIG_VERSION 0x00010001
-
-/* Data Held in On-Board I2C device */
-struct factory_config {
- u32 magic;
- u32 version;
- u8 mac[6];
- u32 fpga_type;
- u32 spare;
- u32 serialnumber;
- char partnum[32];
-};
-
-static struct factory_config factory_config;
-
-#ifdef CONFIG_CPU_FREQ
-struct part_no_info {
- const char *part_no; /* part number string of interest */
- int max_freq; /* khz */
-};
-
-static struct part_no_info mityomapl138_pn_info[] = {
- {
- .part_no = "L138-C",
- .max_freq = 300000,
- },
- {
- .part_no = "L138-D",
- .max_freq = 375000,
- },
- {
- .part_no = "L138-F",
- .max_freq = 456000,
- },
- {
- .part_no = "1808-C",
- .max_freq = 300000,
- },
- {
- .part_no = "1808-D",
- .max_freq = 375000,
- },
- {
- .part_no = "1808-F",
- .max_freq = 456000,
- },
- {
- .part_no = "1810-D",
- .max_freq = 375000,
- },
-};
-
-static void mityomapl138_cpufreq_init(const char *partnum)
-{
- int i, ret;
-
- for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
- /*
- * the part number has additional characters beyond what is
- * stored in the table. This information is not needed for
- * determining the speed grade, and would require several
- * more table entries. Only check the first N characters
- * for a match.
- */
- if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
- strlen(mityomapl138_pn_info[i].part_no))) {
- da850_max_speed = mityomapl138_pn_info[i].max_freq;
- break;
- }
- }
-
- ret = da850_register_cpufreq("pll0_sysclk3");
- if (ret)
- pr_warn("cpufreq registration failed: %d\n", ret);
-}
-#else
-static void mityomapl138_cpufreq_init(const char *partnum) { }
-#endif
-
-static int read_factory_config(struct notifier_block *nb,
- unsigned long event, void *data)
-{
- int ret;
- const char *partnum = NULL;
- struct nvmem_device *nvmem = data;
-
- if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
- return NOTIFY_DONE;
-
- if (!IS_BUILTIN(CONFIG_NVMEM)) {
- pr_warn("Factory Config not available without CONFIG_NVMEM\n");
- goto bad_config;
- }
-
- ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
- &factory_config);
- if (ret != sizeof(struct factory_config)) {
- pr_warn("Read Factory Config Failed: %d\n", ret);
- goto bad_config;
- }
-
- if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
- pr_warn("Factory Config Magic Wrong (%X)\n",
- factory_config.magic);
- goto bad_config;
- }
-
- if (factory_config.version != FACTORY_CONFIG_VERSION) {
- pr_warn("Factory Config Version Wrong (%X)\n",
- factory_config.version);
- goto bad_config;
- }
-
- partnum = factory_config.partnum;
- pr_info("Part Number = %s\n", partnum);
-
-bad_config:
- /* default maximum speed is valid for all platforms */
- mityomapl138_cpufreq_init(partnum);
-
- return NOTIFY_STOP;
-}
-
-static struct notifier_block mityomapl138_nvmem_notifier = {
- .notifier_call = read_factory_config,
-};
-
-/*
- * We don't define a cell for factory config as it will be accessed from the
- * board file using the nvmem notifier chain.
- */
-static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
- {
- .name = "macaddr",
- .offset = 0x64,
- .bytes = ETH_ALEN,
- }
-};
-
-static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
- .nvmem_name = "1-00500",
- .cells = mityomapl138_nvmem_cells,
- .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
-};
-
-static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
- .nvmem_name = "1-00500",
- .cell_name = "macaddr",
- .dev_id = "davinci_emac.1",
- .con_id = "mac-address",
-};
-
-static const struct property_entry mityomapl138_fd_chip_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 8),
- PROPERTY_ENTRY_BOOL("read-only"),
- { }
-};
-
-static const struct software_node mityomapl138_fd_chip_node = {
- .properties = mityomapl138_fd_chip_properties,
-};
-
-static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
- .bus_freq = 100, /* kHz */
- .bus_delay = 0, /* usec */
-};
-
-/* TPS65023 voltage regulator support */
-/* 1.2V Core */
-static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
- {
- .supply = "cvdd",
- },
-};
-
-/* 1.8V */
-static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
- {
- .supply = "usb0_vdda18",
- },
- {
- .supply = "usb1_vdda18",
- },
- {
- .supply = "ddr_dvdd18",
- },
- {
- .supply = "sata_vddr",
- },
-};
-
-/* 1.2V */
-static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
- {
- .supply = "sata_vdd",
- },
- {
- .supply = "usb_cvdd",
- },
- {
- .supply = "pll0_vdda",
- },
- {
- .supply = "pll1_vdda",
- },
-};
-
-/* 1.8V Aux LDO, not used */
-static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
- {
- .supply = "1.8v_aux",
- },
-};
-
-/* FPGA VCC Aux (2.5 or 3.3) LDO */
-static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
- {
- .supply = "vccaux",
- },
-};
-
-static struct regulator_init_data tps65023_regulator_data[] = {
- /* dcdc1 */
- {
- .constraints = {
- .min_uV = 1150000,
- .max_uV = 1350000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
- .consumer_supplies = tps65023_dcdc1_consumers,
- },
- /* dcdc2 */
- {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
- .consumer_supplies = tps65023_dcdc2_consumers,
- },
- /* dcdc3 */
- {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 1200000,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
- .consumer_supplies = tps65023_dcdc3_consumers,
- },
- /* ldo1 */
- {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
- .consumer_supplies = tps65023_ldo1_consumers,
- },
- /* ldo2 */
- {
- .constraints = {
- .min_uV = 2500000,
- .max_uV = 3300000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
- .consumer_supplies = tps65023_ldo2_consumers,
- },
-};
-
-static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
- {
- I2C_BOARD_INFO("tps65023", 0x48),
- .platform_data = &tps65023_regulator_data[0],
- },
- {
- I2C_BOARD_INFO("24c02", 0x50),
- .swnode = &mityomapl138_fd_chip_node,
- },
-};
-
-static int __init pmic_tps65023_init(void)
-{
- return i2c_register_board_info(1, mityomap_tps65023_info,
- ARRAY_SIZE(mityomap_tps65023_info));
-}
-
-/*
- * SPI Devices:
- * SPI1_CS0: 8M Flash ST-M25P64-VME6G
- */
-static struct mtd_partition spi_flash_partitions[] = {
- [0] = {
- .name = "ubl",
- .offset = 0,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [1] = {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- [2] = {
- .name = "u-boot-env",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [3] = {
- .name = "periph-config",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_64K,
- .mask_flags = MTD_WRITEABLE,
- },
- [4] = {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_256K + SZ_64K,
- },
- [5] = {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M + SZ_1M,
- },
- [6] = {
- .name = "fpga",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- },
- [7] = {
- .name = "spare",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct flash_platform_data mityomapl138_spi_flash_data = {
- .name = "m25p80",
- .parts = spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(spi_flash_partitions),
- .type = "m24p64",
-};
-
-static struct davinci_spi_config spi_eprom_config = {
- .io_type = SPI_IO_TYPE_DMA,
- .c2tdelay = 8,
- .t2cdelay = 8,
-};
-
-static struct spi_board_info mityomapl138_spi_flash_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &mityomapl138_spi_flash_data,
- .controller_data = &spi_eprom_config,
- .mode = SPI_MODE_0,
- .max_speed_hz = 30000000,
- .bus_num = 1,
- .chip_select = 0,
- },
-};
-
-/*
- * MityDSP-L138 includes a 256 MByte large-page NAND flash
- * (128K blocks).
- */
-static struct mtd_partition mityomapl138_nandflash_partition[] = {
- {
- .name = "rootfs",
- .offset = 0,
- .size = SZ_128M,
- .mask_flags = 0, /* MTD_WRITEABLE, */
- },
- {
- .name = "homefs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct davinci_nand_pdata mityomapl138_nandflash_data = {
- .core_chipsel = 1,
- .parts = mityomapl138_nandflash_partition,
- .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .bbt_options = NAND_BBT_USE_FLASH,
- .options = NAND_BUSWIDTH_16,
- .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
-};
-
-static struct resource mityomapl138_nandflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device mityomapl138_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = 1,
- .dev = {
- .platform_data = &mityomapl138_nandflash_data,
- },
- .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
- .resource = mityomapl138_nandflash_resource,
- },
-};
-
-static struct resource mityomapl138_aemif_resources[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
- {
- .cs = 1,
- },
-};
-
-static struct aemif_platform_data mityomapl138_aemif_pdata = {
- .abus_data = mityomapl138_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data),
- .sub_devices = mityomapl138_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices),
-};
-
-static struct platform_device mityomapl138_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &mityomapl138_aemif_pdata,
- },
- .resource = mityomapl138_aemif_resources,
- .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources),
-};
-
-static void __init mityomapl138_setup_nand(void)
-{
- if (platform_device_register(&mityomapl138_aemif_device))
- pr_warn("%s: Cannot register AEMIF device\n", __func__);
-}
-
-static const short mityomap_mii_pins[] = {
- DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
- DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
- DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
- DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static const short mityomap_rmii_pins[] = {
- DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
- DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
- DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static void __init mityomapl138_config_emac(void)
-{
- void __iomem *cfg_chip3_base;
- int ret;
- u32 val;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
-
- cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
- val = __raw_readl(cfg_chip3_base);
-
- if (soc_info->emac_pdata->rmii_en) {
- val |= BIT(8);
- ret = davinci_cfg_reg_list(mityomap_rmii_pins);
- pr_info("RMII PHY configured\n");
- } else {
- val &= ~BIT(8);
- ret = davinci_cfg_reg_list(mityomap_mii_pins);
- pr_info("MII PHY configured\n");
- }
-
- if (ret) {
- pr_warn("mii/rmii mux setup failed: %d\n", ret);
- return;
- }
-
- /* configure the CFGCHIP3 register for RMII or MII */
- __raw_writel(val, cfg_chip3_base);
-
- soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("emac registration failed: %d\n", ret);
-}
-
-static void __init mityomapl138_init(void)
-{
- int ret;
-
- da850_register_clocks();
-
- /* for now, no special EDMA channels are reserved */
- ret = da850_register_edma(NULL);
- if (ret)
- pr_warn("edma registration failed: %d\n", ret);
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("watchdog registration failed: %d\n", ret);
-
- davinci_serial_init(da8xx_serial_device);
-
- nvmem_register_notifier(&mityomapl138_nvmem_notifier);
- nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
- nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
-
- ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
- if (ret)
- pr_warn("i2c0 registration failed: %d\n", ret);
-
- ret = pmic_tps65023_init();
- if (ret)
- pr_warn("TPS65023 PMIC init failed: %d\n", ret);
-
- mityomapl138_setup_nand();
-
- ret = spi_register_board_info(mityomapl138_spi_flash_info,
- ARRAY_SIZE(mityomapl138_spi_flash_info));
- if (ret)
- pr_warn("spi info registration failed: %d\n", ret);
-
- ret = da8xx_register_spi_bus(1,
- ARRAY_SIZE(mityomapl138_spi_flash_info));
- if (ret)
- pr_warn("spi 1 registration failed: %d\n", ret);
-
- mityomapl138_config_emac();
-
- ret = da8xx_register_rtc();
- if (ret)
- pr_warn("rtc setup failed: %d\n", ret);
-
- ret = da8xx_register_cpuidle();
- if (ret)
- pr_warn("cpuidle registration failed: %d\n", ret);
-
- davinci_pm_init();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init mityomapl138_console_init(void)
-{
- if (!machine_is_mityomapl138())
- return 0;
-
- return add_preferred_console("ttyS", 1, "115200");
-}
-console_initcall(mityomapl138_console_init);
-#endif
-
-static void __init mityomapl138_map_io(void)
-{
- da850_init();
-}
-
-MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
- .atag_offset = 0x100,
- .map_io = mityomapl138_map_io,
- .init_irq = da850_init_irq,
- .init_time = da850_init_time,
- .init_machine = mityomapl138_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
deleted file mode 100644
index b4843f68bb57..000000000000
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Neuros Technologies OSD2 board support
- *
- * Modified from original 644X-EVM board support.
- * 2008 (c) Neuros Technology, LLC.
- * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
- * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
- *
- * The Neuros OSD 2.0 is the hardware component of the Neuros Open
- * Internet Television Platform. Hardware is very close to TI
- * DM644X-EVM board. It has:
- * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
- * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
- * Additionally realtime clock, IR remote control receiver,
- * IR Blaster based on MSP430 (firmware although is different
- * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
- * with PATA interface, two muxed red-green leds.
- *
- * For more information please refer to
- * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/mtd/partitions.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-
-#include "davinci.h"
-
-#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
-#define LXT971_PHY_ID 0x001378e2
-#define LXT971_PHY_MASK 0xfffffff0
-
-#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
-#define NTOSD2_MSP430_I2C_ADDR 0x59
-#define NTOSD2_MSP430_IRQ 2
-
-/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
- * 2048 blocks in the device, 64 pages per block, 2048 bytes per
- * page.
- */
-
-#define NAND_BLOCK_SIZE SZ_128K
-
-static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
- {
- /* UBL (a few copies) plus U-Boot */
- .name = "bootloader",
- .offset = 0,
- .size = 15 * NAND_BLOCK_SIZE,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- /* U-Boot environment */
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 1 * NAND_BLOCK_SIZE,
- .mask_flags = 0,
- }, {
- /* Kernel */
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = 0,
- }, {
- /* File System */
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- }
- /* A few blocks at end hold a flash Bad Block Table. */
-};
-
-static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
- .core_chipsel = 0,
- .parts = davinci_ntosd2_nandflash_partition,
- .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 1,
- .bbt_options = NAND_BBT_USE_FLASH,
-};
-
-static struct resource davinci_ntosd2_nandflash_resource[] = {
- {
- .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
- .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_ntosd2_nandflash_device = {
- .name = "davinci_nand",
- .id = 0,
- .dev = {
- .platform_data = &davinci_ntosd2_nandflash_data,
- },
- .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
- .resource = davinci_ntosd2_nandflash_resource,
-};
-
-static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device davinci_fb_device = {
- .name = "davincifb",
- .id = -1,
- .dev = {
- .dma_mask = &davinci_fb_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = 0,
-};
-
-static const struct gpio_led ntosd2_leds[] = {
- { .name = "led1_green", .gpio = 10, },
- { .name = "led1_red", .gpio = 11, },
- { .name = "led2_green", .gpio = 12, },
- { .name = "led2_red", .gpio = 13, },
-};
-
-static struct gpio_led_platform_data ntosd2_leds_data = {
- .num_leds = ARRAY_SIZE(ntosd2_leds),
- .leds = ntosd2_leds,
-};
-
-static struct platform_device ntosd2_leds_dev = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &ntosd2_leds_data,
- },
-};
-
-
-static struct platform_device *davinci_ntosd2_devices[] __initdata = {
- &davinci_fb_device,
- &ntosd2_leds_dev,
-};
-
-static void __init davinci_ntosd2_map_io(void)
-{
- dm644x_init();
-}
-
-static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
- .wires = 4,
-};
-
-#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
- IS_ENABLED(CONFIG_PATA_BK3710))
-
-#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
-
-static __init void davinci_ntosd2_init(void)
-{
- int ret;
- struct clk *aemif_clk;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- dm644x_register_clocks();
-
- dm644x_init_devices();
-
- ret = dm644x_gpio_register();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- aemif_clk = clk_get(NULL, "aemif");
- clk_prepare_enable(aemif_clk);
-
- if (HAS_ATA) {
- if (HAS_NAND)
- pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
- "\tDisable IDE for NAND/NOR support\n");
- davinci_init_ide();
- } else if (HAS_NAND) {
- davinci_cfg_reg(DM644X_HPIEN_DISABLE);
- davinci_cfg_reg(DM644X_ATAEN_DISABLE);
-
- /* only one device will be jumpered and detected */
- if (HAS_NAND)
- platform_device_register(
- &davinci_ntosd2_nandflash_device);
- }
-
- platform_add_devices(davinci_ntosd2_devices,
- ARRAY_SIZE(davinci_ntosd2_devices));
-
- davinci_serial_init(dm644x_serial_device);
- dm644x_init_asp();
-
- soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
-
- davinci_setup_usb(1000, 8);
- /*
- * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
- * The AEAWx are five new AEAW pins that can be muxed by separately.
- * They are a bitmask for GPIO management. According TI
- * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
- * gpio(10,11,12,13) for leds any combination of bits works except
- * four last. So we are to reset all five.
- */
- davinci_cfg_reg(DM644X_AEAW0);
- davinci_cfg_reg(DM644X_AEAW1);
- davinci_cfg_reg(DM644X_AEAW2);
- davinci_cfg_reg(DM644X_AEAW3);
- davinci_cfg_reg(DM644X_AEAW4);
-
- davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
-}
-
-MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
- /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
- .atag_offset = 0x100,
- .map_io = davinci_ntosd2_map_io,
- .init_irq = dm644x_init_irq,
- .init_time = dm644x_init_time,
- .init_machine = davinci_ntosd2_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
deleted file mode 100644
index 88df8011a4e6..000000000000
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ /dev/null
@@ -1,454 +0,0 @@
-/*
- * Hawkboard.org based on TI's OMAP-L138 Platform
- *
- * Initial code: Syed Mohammed Khasim
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of
- * any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <linux/platform_data/mtd-davinci-aemif.h>
-#include <linux/platform_data/ti-aemif.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/da8xx.h>
-#include <mach/mux.h>
-
-#define HAWKBOARD_PHY_ID "davinci_mdio-0:07"
-
-#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4)
-#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13)
-
-static short omapl138_hawk_mii_pins[] __initdata = {
- DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
- DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
- DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
- DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
- DA850_MDIO_D,
- -1
-};
-
-static __init void omapl138_hawk_config_emac(void)
-{
- void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
- int ret;
- u32 val;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- val = __raw_readl(cfgchip3);
- val &= ~BIT(8);
- ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
- if (ret) {
- pr_warn("%s: CPGMAC/MII mux setup failed: %d\n", __func__, ret);
- return;
- }
-
- /* configure the CFGCHIP3 register for MII */
- __raw_writel(val, cfgchip3);
- pr_info("EMAC: MII PHY configured\n");
-
- soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID;
-
- ret = da8xx_register_emac();
- if (ret)
- pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
-}
-
-/*
- * The following EDMA channels/slots are not being used by drivers (for
- * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard,
- * hence they are being reserved for codecs on the DSP side.
- */
-static const s16 da850_dma0_rsv_chans[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma0_rsv_slots[][2] = {
- /* (offset, number) */
- { 8, 6},
- {24, 4},
- {30, 50},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_chans[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 2},
- {-1, -1}
-};
-
-static const s16 da850_dma1_rsv_slots[][2] = {
- /* (offset, number) */
- { 0, 28},
- {30, 90},
- {-1, -1}
-};
-
-static struct edma_rsv_info da850_edma_cc0_rsv = {
- .rsv_chans = da850_dma0_rsv_chans,
- .rsv_slots = da850_dma0_rsv_slots,
-};
-
-static struct edma_rsv_info da850_edma_cc1_rsv = {
- .rsv_chans = da850_dma1_rsv_chans,
- .rsv_slots = da850_dma1_rsv_slots,
-};
-
-static struct edma_rsv_info *da850_edma_rsv[2] = {
- &da850_edma_cc0_rsv,
- &da850_edma_cc1_rsv,
-};
-
-static const short hawk_mmcsd0_pins[] = {
- DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
- DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
- DA850_GPIO3_12, DA850_GPIO3_13,
- -1
-};
-
-#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
-#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
-
-static struct gpiod_lookup_table mmc_gpios_table = {
- .dev_id = "da830-mmc.0",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd",
- GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp",
- GPIO_ACTIVE_LOW),
- },
-};
-
-static struct davinci_mmc_config da850_mmc_config = {
- .wires = 4,
- .max_freq = 50000000,
- .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static __init void omapl138_hawk_mmc_init(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(hawk_mmcsd0_pins);
- if (ret) {
- pr_warn("%s: MMC/SD0 mux setup failed: %d\n", __func__, ret);
- return;
- }
-
- gpiod_add_lookup_table(&mmc_gpios_table);
-
- ret = da8xx_register_mmcsd0(&da850_mmc_config);
- if (ret) {
- pr_warn("%s: MMC/SD0 registration failed: %d\n", __func__, ret);
- goto mmc_setup_mmcsd_fail;
- }
-
- return;
-
-mmc_setup_mmcsd_fail:
- gpiod_remove_lookup_table(&mmc_gpios_table);
-}
-
-static struct mtd_partition omapl138_hawk_nandflash_partition[] = {
- {
- .name = "u-boot env",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "free space",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0,
- },
-};
-
-static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = {
- .wsetup = 24,
- .wstrobe = 21,
- .whold = 14,
- .rsetup = 19,
- .rstrobe = 50,
- .rhold = 0,
- .ta = 20,
-};
-
-static struct davinci_nand_pdata omapl138_hawk_nandflash_data = {
- .core_chipsel = 1,
- .parts = omapl138_hawk_nandflash_partition,
- .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition),
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
- .ecc_bits = 4,
- .bbt_options = NAND_BBT_USE_FLASH,
- .options = NAND_BUSWIDTH_16,
- .timing = &omapl138_hawk_nandflash_timing,
- .mask_chipsel = 0,
- .mask_ale = 0,
- .mask_cle = 0,
-};
-
-static struct resource omapl138_hawk_nandflash_resource[] = {
- {
- .start = DA8XX_AEMIF_CS3_BASE,
- .end = DA8XX_AEMIF_CS3_BASE + SZ_32M,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource omapl138_hawk_aemif_resource[] = {
- {
- .start = DA8XX_AEMIF_CTL_BASE,
- .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = {
- {
- .cs = 3,
- }
-};
-
-static struct platform_device omapl138_hawk_aemif_devices[] = {
- {
- .name = "davinci_nand",
- .id = -1,
- .dev = {
- .platform_data = &omapl138_hawk_nandflash_data,
- },
- .resource = omapl138_hawk_nandflash_resource,
- .num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource),
- }
-};
-
-static struct aemif_platform_data omapl138_hawk_aemif_pdata = {
- .cs_offset = 2,
- .abus_data = omapl138_hawk_aemif_abus_data,
- .num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data),
- .sub_devices = omapl138_hawk_aemif_devices,
- .num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices),
-};
-
-static struct platform_device omapl138_hawk_aemif_device = {
- .name = "ti-aemif",
- .id = -1,
- .dev = {
- .platform_data = &omapl138_hawk_aemif_pdata,
- },
- .resource = omapl138_hawk_aemif_resource,
- .num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource),
-};
-
-static const short omapl138_hawk_nand_pins[] = {
- DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3,
- DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
- DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
- DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
- DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
- DA850_EMA_A_1, DA850_EMA_A_2,
- -1
-};
-
-static int omapl138_hawk_register_aemif(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins);
- if (ret)
- pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret);
-
- return platform_device_register(&omapl138_hawk_aemif_device);
-}
-
-static const short da850_hawk_usb11_pins[] = {
- DA850_GPIO2_4, DA850_GPIO6_13,
- -1
-};
-
-static struct regulator_consumer_supply hawk_usb_supplies[] = {
- REGULATOR_SUPPLY("vbus", NULL),
-};
-
-static struct regulator_init_data hawk_usb_vbus_data = {
- .consumer_supplies = hawk_usb_supplies,
- .num_consumer_supplies = ARRAY_SIZE(hawk_usb_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config hawk_usb_vbus = {
- .supply_name = "vbus",
- .microvolts = 3300000,
- .init_data = &hawk_usb_vbus_data,
-};
-
-static struct platform_device hawk_usb_vbus_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &hawk_usb_vbus,
- },
-};
-
-static struct gpiod_lookup_table hawk_usb_oc_gpio_lookup = {
- .dev_id = "ohci-da8xx",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_USB1_OC_PIN, "oc", 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table hawk_usb_vbus_gpio_lookup = {
- .dev_id = "reg-fixed-voltage.0",
- .table = {
- GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, NULL, 0),
- { }
- },
-};
-
-static struct gpiod_lookup_table *hawk_usb_gpio_lookups[] = {
- &hawk_usb_oc_gpio_lookup,
- &hawk_usb_vbus_gpio_lookup,
-};
-
-static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
- /* TPS2087 switch @ 5V */
- .potpgt = (3 + 1) / 2, /* 3 ms max */
-};
-
-static __init void omapl138_hawk_usb_init(void)
-{
- int ret;
-
- ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
- if (ret) {
- pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
- return;
- }
-
- ret = da8xx_register_usb_phy_clocks();
- if (ret)
- pr_warn("%s: USB PHY CLK registration failed: %d\n",
- __func__, ret);
-
- gpiod_add_lookup_tables(hawk_usb_gpio_lookups,
- ARRAY_SIZE(hawk_usb_gpio_lookups));
-
- ret = da8xx_register_usb_phy();
- if (ret)
- pr_warn("%s: USB PHY registration failed: %d\n",
- __func__, ret);
-
- ret = platform_device_register(&hawk_usb_vbus_device);
- if (ret) {
- pr_warn("%s: Unable to register the vbus supply\n", __func__);
- return;
- }
-
- ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
- if (ret)
- pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
-
- return;
-}
-
-static __init void omapl138_hawk_init(void)
-{
- int ret;
-
- da850_register_clocks();
-
- ret = da850_register_gpio();
- if (ret)
- pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
-
- davinci_serial_init(da8xx_serial_device);
-
- omapl138_hawk_config_emac();
-
- ret = da850_register_edma(da850_edma_rsv);
- if (ret)
- pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
-
- omapl138_hawk_mmc_init();
-
- omapl138_hawk_usb_init();
-
- ret = omapl138_hawk_register_aemif();
- if (ret)
- pr_warn("%s: aemif registration failed: %d\n", __func__, ret);
-
- ret = da8xx_register_watchdog();
- if (ret)
- pr_warn("%s: watchdog registration failed: %d\n",
- __func__, ret);
-
- ret = da8xx_register_rproc();
- if (ret)
- pr_warn("%s: dsp/rproc registration failed: %d\n",
- __func__, ret);
-
- regulator_has_full_constraints();
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init omapl138_hawk_console_init(void)
-{
- if (!machine_is_omapl138_hawkboard())
- return 0;
-
- return add_preferred_console("ttyS", 2, "115200");
-}
-console_initcall(omapl138_hawk_console_init);
-#endif
-
-static void __init omapl138_hawk_map_io(void)
-{
- da850_init();
-}
-
-MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
- .atag_offset = 0x100,
- .map_io = omapl138_hawk_map_io,
- .init_irq = da850_init_irq,
- .init_time = da850_init_time,
- .init_machine = omapl138_hawk_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
- .reserve = da8xx_rproc_reserve_cma,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
deleted file mode 100644
index 6930b2f485d1..000000000000
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Lyrtech SFFSDR board support.
- *
- * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- *
- * Based on DV-EVM platform, original copyright follows:
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/property.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-
-#include <mach/common.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-#include <linux/platform_data/usb-davinci.h>
-
-#include "davinci.h"
-
-#define SFFSDR_PHY_ID "davinci_mdio-0:01"
-static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
- /* U-Boot Environment: Block 0
- * UBL: Block 1
- * U-Boot: Blocks 6-7 (256 kb)
- * Integrity Kernel: Blocks 8-31 (3 Mb)
- * Integrity Data: Blocks 100-END
- */
- {
- .name = "Linux Kernel",
- .offset = 32 * SZ_128K,
- .size = 16 * SZ_128K, /* 2 Mb */
- .mask_flags = MTD_WRITEABLE, /* Force read-only */
- },
- {
- .name = "Linux ROOT",
- .offset = MTDPART_OFS_APPEND,
- .size = 256 * SZ_128K, /* 32 Mb */
- .mask_flags = 0, /* R/W */
- },
-};
-
-static struct flash_platform_data davinci_sffsdr_nandflash_data = {
- .parts = davinci_sffsdr_nandflash_partition,
- .nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition),
-};
-
-static struct resource davinci_sffsdr_nandflash_resource[] = {
- {
- .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
- .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
- .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_sffsdr_nandflash_device = {
- .name = "davinci_nand", /* Name of driver */
- .id = 0,
- .dev = {
- .platform_data = &davinci_sffsdr_nandflash_data,
- },
- .num_resources = ARRAY_SIZE(davinci_sffsdr_nandflash_resource),
- .resource = davinci_sffsdr_nandflash_resource,
-};
-
-static const struct property_entry eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 32),
- { }
-};
-
-static const struct software_node eeprom_node = {
- .properties = eeprom_properties,
-};
-
-static struct i2c_board_info __initdata i2c_info[] = {
- {
- I2C_BOARD_INFO("24c64", 0x50),
- .swnode = &eeprom_node,
- },
- /* Other I2C devices:
- * MSP430, addr 0x23 (not used)
- * PCA9543, addr 0x70 (setup done by U-Boot)
- * ADS7828, addr 0x48 (ADC for voltage monitoring.)
- */
-};
-
-static struct davinci_i2c_platform_data i2c_pdata = {
- .bus_freq = 20 /* kHz */,
- .bus_delay = 100 /* usec */,
-};
-
-static void __init sffsdr_init_i2c(void)
-{
- davinci_init_i2c(&i2c_pdata);
- i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
-}
-
-static struct platform_device *davinci_sffsdr_devices[] __initdata = {
- &davinci_sffsdr_nandflash_device,
-};
-
-static void __init davinci_sffsdr_map_io(void)
-{
- dm644x_init();
-}
-
-static __init void davinci_sffsdr_init(void)
-{
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- dm644x_register_clocks();
-
- dm644x_init_devices();
-
- platform_add_devices(davinci_sffsdr_devices,
- ARRAY_SIZE(davinci_sffsdr_devices));
- sffsdr_init_i2c();
- davinci_serial_init(dm644x_serial_device);
- soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
- davinci_setup_usb(0, 0); /* We support only peripheral mode. */
-
- /* mux VLYNQ pins */
- davinci_cfg_reg(DM644X_VLYNQEN);
- davinci_cfg_reg(DM644X_VLYNQWD);
-}
-
-MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
- .atag_offset = 0x100,
- .map_io = davinci_sffsdr_map_io,
- .init_irq = dm644x_init_irq,
- .init_time = dm644x_init_time,
- .init_machine = davinci_sffsdr_init,
- .init_late = davinci_init_late,
- .dma_zone_size = SZ_128M,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index ae61d19f9b3a..c1ce6b2a8d48 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Code commons to all DaVinci SoCs.
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
- * 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2009 (c) MontaVista Software, Inc.
*/
#include <linux/module.h>
#include <linux/io.h>
@@ -17,8 +15,8 @@
#include <asm/tlb.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/cputype.h>
+#include "common.h"
+#include "cputype.h"
struct davinci_soc_info davinci_soc_info;
EXPORT_SYMBOL(davinci_soc_info);
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/common.h
index 139b83de011d..b4fd0e9acf6c 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/common.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header for code common to all DaVinci machines.
*
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
*
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
*/
#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
@@ -19,8 +17,8 @@
#include <asm/irq.h>
-#define DAVINCI_INTC_START NR_IRQS
-#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
+#define DAVINCI_INTC_START NR_IRQS
+#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
struct davinci_gpio_controller;
@@ -47,9 +45,6 @@ struct davinci_soc_info {
unsigned gpio_num;
unsigned gpio_irq;
unsigned gpio_unbanked;
- struct davinci_gpio_controller *gpio_ctlrs;
- int gpio_ctlrs_num;
- struct emac_platform_data *emac_pdata;
dma_addr_t sram_dma;
unsigned sram_len;
};
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index dd38785536d5..78a1575c387d 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -44,8 +44,8 @@ static void davinci_save_ddr_power(int enter, bool pdown)
}
/* Actual code that puts the SoC in different idle states */
-static int davinci_enter_idle(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+static __cpuidle int davinci_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
davinci_save_ddr_power(1, ddr2_pdown);
cpu_do_idle();
diff --git a/arch/arm/mach-davinci/cpuidle.h b/arch/arm/mach-davinci/cpuidle.h
index 0d9193aefab5..976d43073597 100644
--- a/arch/arm/mach-davinci/cpuidle.h
+++ b/arch/arm/mach-davinci/cpuidle.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI DaVinci cpuidle platform support
*
* 2009 (C) Texas Instruments, Inc. https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#ifndef _MACH_DAVINCI_CPUIDLE_H
#define _MACH_DAVINCI_CPUIDLE_H
diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h
new file mode 100644
index 000000000000..148a738391dc
--- /dev/null
+++ b/arch/arm/mach-davinci/cputype.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * DaVinci CPU type detection
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Defines the cpu_is_*() macros for runtime detection of DaVinci
+ * device type. In addition, if support for a given device is not
+ * compiled in to the kernel, the macros return 0 so that
+ * resulting code can be optimized out.
+ *
+ * 2009 (c) Deep Root Systems, LLC.
+ */
+#ifndef _ASM_ARCH_CPU_H
+#define _ASM_ARCH_CPU_H
+
+#include "common.h"
+
+struct davinci_id {
+ u8 variant; /* JTAG ID bits 31:28 */
+ u16 part_no; /* JTAG ID bits 27:12 */
+ u16 manufacturer; /* JTAG ID bits 11:1 */
+ u32 cpu_id;
+ char *name;
+};
+
+/* Can use lower 16 bits of cpu id for a variant when required */
+#define DAVINCI_CPU_ID_DA830 0x08300000
+#define DAVINCI_CPU_ID_DA850 0x08500000
+
+#endif
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 018ab4b549f1..2e497745b624 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* TI DA830/OMAP L137 chip specific setup
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
- * 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2009 (c) MontaVista Software, Inc.
*/
#include <linux/clk-provider.h>
#include <linux/clk/davinci.h>
@@ -14,16 +12,14 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqchip/irq-davinci-cp-intc.h>
-#include <linux/platform_data/gpio-davinci.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/da8xx.h>
#include <clocksource/timer-davinci.h>
+#include <asm/mach/map.h>
+
+#include "common.h"
+#include "cputype.h"
+#include "da8xx.h"
#include "irqs.h"
#include "mux.h"
@@ -451,181 +447,6 @@ static const struct mux_config da830_pins[] = {
#endif
};
-const short da830_emif25_pins[] __initconst = {
- DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
- DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
- DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
- DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15,
- DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
- DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
- DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
- DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK,
- DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE,
- DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE,
- DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0,
- -1
-};
-
-const short da830_spi0_pins[] __initconst = {
- DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
- DA830_NSPI0_SCS_0,
- -1
-};
-
-const short da830_spi1_pins[] __initconst = {
- DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
- DA830_NSPI1_SCS_0,
- -1
-};
-
-const short da830_mmc_sd_pins[] __initconst = {
- DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
- DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
- DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
- DA830_MMCSD_CMD,
- -1
-};
-
-const short da830_uart0_pins[] __initconst = {
- DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
- -1
-};
-
-const short da830_uart1_pins[] __initconst = {
- DA830_UART1_RXD, DA830_UART1_TXD,
- -1
-};
-
-const short da830_uart2_pins[] __initconst = {
- DA830_UART2_RXD, DA830_UART2_TXD,
- -1
-};
-
-const short da830_usb20_pins[] __initconst = {
- DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
- -1
-};
-
-const short da830_usb11_pins[] __initconst = {
- DA830_USB_REFCLKIN,
- -1
-};
-
-const short da830_uhpi_pins[] __initconst = {
- DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
- DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
- DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
- DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15,
- DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW,
- DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2,
- DA830_NUHPI_HINT, DA830_NUHPI_HRDY,
- -1
-};
-
-const short da830_cpgmac_pins[] __initconst = {
- DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
- DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
- DA830_MDIO_D,
- -1
-};
-
-const short da830_emif3c_pins[] __initconst = {
- DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
- DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
- DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
- DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6,
- DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10,
- DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3,
- DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2,
- DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6,
- DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10,
- DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14,
- DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18,
- DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22,
- DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26,
- DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30,
- DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0,
- -1
-};
-
-const short da830_mcasp0_pins[] __initconst = {
- DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
- DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
- DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
- DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7,
- DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11,
- DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15,
- -1
-};
-
-const short da830_mcasp1_pins[] __initconst = {
- DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
- DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
- DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
- DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7,
- DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11,
- -1
-};
-
-const short da830_mcasp2_pins[] __initconst = {
- DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
- DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
- DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
- -1
-};
-
-const short da830_i2c0_pins[] __initconst = {
- DA830_I2C0_SDA, DA830_I2C0_SCL,
- -1
-};
-
-const short da830_i2c1_pins[] __initconst = {
- DA830_I2C1_SCL, DA830_I2C1_SDA,
- -1
-};
-
-const short da830_lcdcntl_pins[] __initconst = {
- DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
- DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
- DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
- DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15,
- DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS,
- DA830_LCD_MCLK,
- -1
-};
-
-const short da830_pwm_pins[] __initconst = {
- DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
- DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
- DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
- -1
-};
-
-const short da830_ecap0_pins[] __initconst = {
- DA830_ECAP0_APWM0,
- -1
-};
-
-const short da830_ecap1_pins[] __initconst = {
- DA830_ECAP1_APWM1,
- -1
-};
-
-const short da830_ecap2_pins[] __initconst = {
- DA830_ECAP2_APWM2,
- -1
-};
-
-const short da830_eqep0_pins[] __initconst = {
- DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
- -1
-};
-
-const short da830_eqep1_pins[] __initconst = {
- DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
- -1
-};
-
static struct map_desc da830_io_desc[] = {
{
.virtual = IO_VIRT,
@@ -666,30 +487,6 @@ static struct davinci_id da830_ids[] = {
},
};
-static struct davinci_gpio_platform_data da830_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 128,
-};
-
-int __init da830_register_gpio(void)
-{
- return da8xx_register_gpio(&da830_gpio_platform_data);
-}
-
-/*
- * Bottom half of timer0 is used both for clock even and clocksource.
- * Top half is used by DSP.
- */
-static const struct davinci_timer_cfg da830_timer_cfg = {
- .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
- },
- .cmp_off = DA830_CMP12_0,
-};
-
static const struct davinci_soc_info davinci_soc_info_da830 = {
.io_desc = da830_io_desc,
.io_desc_num = ARRAY_SIZE(da830_io_desc),
@@ -699,7 +496,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da830_pins,
.pinmux_pins_num = ARRAY_SIZE(da830_pins),
- .emac_pdata = &da8xx_emac_pdata,
};
void __init da830_init(void)
@@ -709,76 +505,3 @@ void __init da830_init(void)
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
}
-
-static const struct davinci_cp_intc_config da830_cp_intc_config = {
- .reg = {
- .start = DA8XX_CP_INTC_BASE,
- .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = DA830_N_CP_INTC_IRQ,
-};
-
-void __init da830_init_irq(void)
-{
- davinci_cp_intc_init(&da830_cp_intc_config);
-}
-
-void __init da830_init_time(void)
-{
- void __iomem *pll;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ);
-
- pll = ioremap(DA8XX_PLL0_BASE, SZ_4K);
-
- da830_pll_init(NULL, pll, NULL);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &da830_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource da830_psc0_resources[] = {
- {
- .start = DA8XX_PSC0_BASE,
- .end = DA8XX_PSC0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da830_psc0_device = {
- .name = "da830-psc0",
- .id = -1,
- .resource = da830_psc0_resources,
- .num_resources = ARRAY_SIZE(da830_psc0_resources),
-};
-
-static struct resource da830_psc1_resources[] = {
- {
- .start = DA8XX_PSC1_BASE,
- .end = DA8XX_PSC1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da830_psc1_device = {
- .name = "da830-psc1",
- .id = -1,
- .resource = da830_psc1_resources,
- .num_resources = ARRAY_SIZE(da830_psc1_resources),
-};
-
-void __init da830_register_clocks(void)
-{
- /* PLL is registered in da830_init_time() */
- platform_device_register(&da830_psc0_device);
- platform_device_register(&da830_psc1_device);
-}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 68156e7239a6..287dd987908e 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* TI DA850/OMAP-L138 chip specific setup
*
@@ -6,38 +7,25 @@
* Derived from: arch/arm/mach-davinci/da830.c
* Original Copyrights follow:
*
- * 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2009 (c) MontaVista Software, Inc.
*/
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/cpufreq.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/mfd/da8xx-cfgchip.h>
-#include <linux/platform_data/clk-da8xx-cfgchip.h>
-#include <linux/platform_data/clk-davinci-pll.h>
-#include <linux/platform_data/davinci-cpufreq.h>
-#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
+#include <clocksource/timer-davinci.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/da8xx.h>
-#include <mach/pm.h>
-
-#include <clocksource/timer-davinci.h>
-
+#include "common.h"
+#include "cputype.h"
+#include "da8xx.h"
+#include "hardware.h"
+#include "pm.h"
#include "irqs.h"
#include "mux.h"
@@ -262,45 +250,6 @@ static const struct mux_config da850_pins[] = {
#endif
};
-const short da850_i2c0_pins[] __initconst = {
- DA850_I2C0_SDA, DA850_I2C0_SCL,
- -1
-};
-
-const short da850_i2c1_pins[] __initconst = {
- DA850_I2C1_SCL, DA850_I2C1_SDA,
- -1
-};
-
-const short da850_lcdcntl_pins[] __initconst = {
- DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
- DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
- DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
- DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
- DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
- -1
-};
-
-const short da850_vpif_capture_pins[] __initconst = {
- DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
- DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
- DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
- DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
- DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
- DA850_VPIF_CLKIN3,
- -1
-};
-
-const short da850_vpif_display_pins[] __initconst = {
- DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
- DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
- DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
- DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
- DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
- DA850_VPIF_CLKO3,
- -1
-};
-
static struct map_desc da850_io_desc[] = {
{
.virtual = IO_VIRT,
@@ -334,204 +283,9 @@ static struct davinci_id da850_ids[] = {
},
};
-/*
- * Bottom half of timer 0 is used for clock_event, top half for
- * clocksource.
- */
-static const struct davinci_timer_cfg da850_timer_cfg = {
- .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
- },
-};
-
-#ifdef CONFIG_CPU_FREQ
-/*
- * Notes:
- * According to the TRM, minimum PLLM results in maximum power savings.
- * The OPP definitions below should keep the PLLM as low as possible.
- *
- * The output of the PLLM must be between 300 to 600 MHz.
- */
-struct da850_opp {
- unsigned int freq; /* in KHz */
- unsigned int prediv;
- unsigned int mult;
- unsigned int postdiv;
- unsigned int cvdd_min; /* in uV */
- unsigned int cvdd_max; /* in uV */
-};
-
-static const struct da850_opp da850_opp_456 = {
- .freq = 456000,
- .prediv = 1,
- .mult = 19,
- .postdiv = 1,
- .cvdd_min = 1300000,
- .cvdd_max = 1350000,
-};
-
-static const struct da850_opp da850_opp_408 = {
- .freq = 408000,
- .prediv = 1,
- .mult = 17,
- .postdiv = 1,
- .cvdd_min = 1300000,
- .cvdd_max = 1350000,
-};
-
-static const struct da850_opp da850_opp_372 = {
- .freq = 372000,
- .prediv = 2,
- .mult = 31,
- .postdiv = 1,
- .cvdd_min = 1200000,
- .cvdd_max = 1320000,
-};
-
-static const struct da850_opp da850_opp_300 = {
- .freq = 300000,
- .prediv = 1,
- .mult = 25,
- .postdiv = 2,
- .cvdd_min = 1200000,
- .cvdd_max = 1320000,
-};
-
-static const struct da850_opp da850_opp_200 = {
- .freq = 200000,
- .prediv = 1,
- .mult = 25,
- .postdiv = 3,
- .cvdd_min = 1100000,
- .cvdd_max = 1160000,
-};
-
-static const struct da850_opp da850_opp_96 = {
- .freq = 96000,
- .prediv = 1,
- .mult = 20,
- .postdiv = 5,
- .cvdd_min = 1000000,
- .cvdd_max = 1050000,
-};
-
-#define OPP(freq) \
- { \
- .driver_data = (unsigned int) &da850_opp_##freq, \
- .frequency = freq * 1000, \
- }
-
-static struct cpufreq_frequency_table da850_freq_table[] = {
- OPP(456),
- OPP(408),
- OPP(372),
- OPP(300),
- OPP(200),
- OPP(96),
- {
- .driver_data = 0,
- .frequency = CPUFREQ_TABLE_END,
- },
-};
-
-#ifdef CONFIG_REGULATOR
-static int da850_set_voltage(unsigned int index);
-static int da850_regulator_init(void);
-#endif
-
-static struct davinci_cpufreq_config cpufreq_info = {
- .freq_table = da850_freq_table,
-#ifdef CONFIG_REGULATOR
- .init = da850_regulator_init,
- .set_voltage = da850_set_voltage,
-#endif
-};
-
-#ifdef CONFIG_REGULATOR
-static struct regulator *cvdd;
-
-static int da850_set_voltage(unsigned int index)
-{
- struct da850_opp *opp;
-
- if (!cvdd)
- return -ENODEV;
-
- opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
-
- return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
-}
-
-static int da850_regulator_init(void)
-{
- cvdd = regulator_get(NULL, "cvdd");
- if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
- " voltage scaling unsupported\n")) {
- return PTR_ERR(cvdd);
- }
-
- return 0;
-}
-#endif
-
-static struct platform_device da850_cpufreq_device = {
- .name = "cpufreq-davinci",
- .dev = {
- .platform_data = &cpufreq_info,
- },
- .id = -1,
-};
-
-unsigned int da850_max_speed = 300000;
-
-int da850_register_cpufreq(char *async_clk)
-{
- int i;
-
- /* cpufreq driver can help keep an "async" clock constant */
- if (async_clk)
- clk_add_alias("async", da850_cpufreq_device.name,
- async_clk, NULL);
- for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
- if (da850_freq_table[i].frequency <= da850_max_speed) {
- cpufreq_info.freq_table = &da850_freq_table[i];
- break;
- }
- }
-
- return platform_device_register(&da850_cpufreq_device);
-}
-#else
-int __init da850_register_cpufreq(char *async_clk)
-{
- return 0;
-}
-#endif
-
/* VPIF resource, platform data */
static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
-static struct resource da850_vpif_resource[] = {
- {
- .start = DA8XX_VPIF_BASE,
- .end = DA8XX_VPIF_BASE + 0xfff,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device da850_vpif_dev = {
- .name = "vpif",
- .id = -1,
- .dev = {
- .dma_mask = &da850_vpif_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = da850_vpif_resource,
- .num_resources = ARRAY_SIZE(da850_vpif_resource),
-};
-
static struct resource da850_vpif_display_resource[] = {
{
.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
@@ -575,11 +329,6 @@ static struct platform_device da850_vpif_capture_dev = {
.num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
};
-int __init da850_register_vpif(void)
-{
- return platform_device_register(&da850_vpif_dev);
-}
-
int __init da850_register_vpif_display(struct vpif_display_config
*display_config)
{
@@ -594,17 +343,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config
return platform_device_register(&da850_vpif_capture_dev);
}
-static struct davinci_gpio_platform_data da850_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 144,
-};
-
-int __init da850_register_gpio(void)
-{
- return da8xx_register_gpio(&da850_gpio_platform_data);
-}
-
static const struct davinci_soc_info davinci_soc_info_da850 = {
.io_desc = da850_io_desc,
.io_desc_num = ARRAY_SIZE(da850_io_desc),
@@ -614,7 +352,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da850_pins,
.pinmux_pins_num = ARRAY_SIZE(da850_pins),
- .emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_SHARED_RAM_BASE,
.sram_len = SZ_128K,
};
@@ -630,142 +367,3 @@ void __init da850_init(void)
da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
}
-
-static const struct davinci_cp_intc_config da850_cp_intc_config = {
- .reg = {
- .start = DA8XX_CP_INTC_BASE,
- .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = DA850_N_CP_INTC_IRQ,
-};
-
-void __init da850_init_irq(void)
-{
- davinci_cp_intc_init(&da850_cp_intc_config);
-}
-
-void __init da850_init_time(void)
-{
- void __iomem *pll0;
- struct regmap *cfgchip;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
-
- pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
- cfgchip = da8xx_get_cfgchip();
-
- da850_pll0_init(NULL, pll0, cfgchip);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &da850_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource da850_pll1_resources[] = {
- {
- .start = DA850_PLL1_BASE,
- .end = DA850_PLL1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct davinci_pll_platform_data da850_pll1_pdata;
-
-static struct platform_device da850_pll1_device = {
- .name = "da850-pll1",
- .id = -1,
- .resource = da850_pll1_resources,
- .num_resources = ARRAY_SIZE(da850_pll1_resources),
- .dev = {
- .platform_data = &da850_pll1_pdata,
- },
-};
-
-static struct resource da850_psc0_resources[] = {
- {
- .start = DA8XX_PSC0_BASE,
- .end = DA8XX_PSC0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da850_psc0_device = {
- .name = "da850-psc0",
- .id = -1,
- .resource = da850_psc0_resources,
- .num_resources = ARRAY_SIZE(da850_psc0_resources),
-};
-
-static struct resource da850_psc1_resources[] = {
- {
- .start = DA8XX_PSC1_BASE,
- .end = DA8XX_PSC1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da850_psc1_device = {
- .name = "da850-psc1",
- .id = -1,
- .resource = da850_psc1_resources,
- .num_resources = ARRAY_SIZE(da850_psc1_resources),
-};
-
-static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
-
-static struct platform_device da850_async1_clksrc_device = {
- .name = "da850-async1-clksrc",
- .id = -1,
- .dev = {
- .platform_data = &da850_async1_pdata,
- },
-};
-
-static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
-
-static struct platform_device da850_async3_clksrc_device = {
- .name = "da850-async3-clksrc",
- .id = -1,
- .dev = {
- .platform_data = &da850_async3_pdata,
- },
-};
-
-static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
-
-static struct platform_device da850_tbclksync_device = {
- .name = "da830-tbclksync",
- .id = -1,
- .dev = {
- .platform_data = &da850_tbclksync_pdata,
- },
-};
-
-void __init da850_register_clocks(void)
-{
- /* PLL0 is registered in da850_init_time() */
-
- da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_pll1_device);
-
- da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_async1_clksrc_device);
-
- da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_async3_clksrc_device);
-
- platform_device_register(&da850_psc0_device);
-
- platform_device_register(&da850_psc1_device);
-
- da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
- platform_device_register(&da850_tbclksync_device);
-}
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 0cd2f30aeb9c..45763a9b37ee 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -7,8 +7,8 @@
#include <asm/mach/arch.h>
-#include <mach/common.h>
-#include <mach/da8xx.h>
+#include "common.h"
+#include "da8xx.h"
#ifdef CONFIG_ARCH_DAVINCI_DA850
diff --git a/arch/arm/mach-davinci/da8xx.h b/arch/arm/mach-davinci/da8xx.h
new file mode 100644
index 000000000000..54a255b8d8d8
--- /dev/null
+++ b/arch/arm/mach-davinci/da8xx.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Chip specific defines for DA8XX/OMAP L1XX SoC
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007, 2009-2010 (c) MontaVista Software, Inc.
+ */
+#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
+#define __ASM_ARCH_DAVINCI_DA8XX_H
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/videodev2.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+
+#include "hardware.h"
+#include "pm.h"
+
+#include <media/davinci/vpif_types.h>
+
+extern void __iomem *da8xx_syscfg0_base;
+extern void __iomem *da8xx_syscfg1_base;
+
+/*
+ * The cp_intc interrupt controller for the da8xx isn't in the same
+ * chunk of physical memory space as the other registers (like it is
+ * on the davincis) so it needs to be mapped separately. It will be
+ * mapped early on when the I/O space is mapped and we'll put it just
+ * before the I/O space in the processor's virtual memory space.
+ */
+#define DA8XX_CP_INTC_BASE 0xfffee000
+#define DA8XX_CP_INTC_SIZE SZ_8K
+#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
+
+#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
+#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
+#define DA8XX_JTAG_ID_REG 0x18
+#define DA8XX_HOST1CFG_REG 0x44
+#define DA8XX_CHIPSIG_REG 0x174
+#define DA8XX_CFGCHIP0_REG 0x17c
+#define DA8XX_CFGCHIP1_REG 0x180
+#define DA8XX_CFGCHIP2_REG 0x184
+#define DA8XX_CFGCHIP3_REG 0x188
+#define DA8XX_CFGCHIP4_REG 0x18c
+
+#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
+#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
+#define DA8XX_DEEPSLEEP_REG 0x8
+#define DA8XX_PWRDN_REG 0x18
+
+#define DA8XX_PSC0_BASE 0x01c10000
+#define DA8XX_PLL0_BASE 0x01c11000
+#define DA8XX_TIMER64P0_BASE 0x01c20000
+#define DA8XX_TIMER64P1_BASE 0x01c21000
+#define DA8XX_VPIF_BASE 0x01e17000
+#define DA8XX_GPIO_BASE 0x01e26000
+#define DA8XX_PSC1_BASE 0x01e27000
+
+#define DA8XX_DSP_L2_RAM_BASE 0x11800000
+#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000)
+#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000)
+
+#define DA8XX_AEMIF_CS2_BASE 0x60000000
+#define DA8XX_AEMIF_CS3_BASE 0x62000000
+#define DA8XX_AEMIF_CTL_BASE 0x68000000
+#define DA8XX_SHARED_RAM_BASE 0x80000000
+#define DA8XX_ARM_RAM_BASE 0xffff0000
+
+void da830_init(void);
+
+void da850_init(void);
+
+int da850_register_vpif_display
+ (struct vpif_display_config *display_config);
+int da850_register_vpif_capture
+ (struct vpif_capture_config *capture_config);
+struct regmap *da8xx_get_cfgchip(void);
+void __iomem *da8xx_get_mem_ctlr(void);
+
+#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
deleted file mode 100644
index 208d7a4d3597..000000000000
--- a/arch/arm/mach-davinci/davinci.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file contains the processor specific definitions
- * of the TI DM644x, DM355, DM365, and DM646x.
- *
- * Copyright (C) 2011 Texas Instruments Incorporated
- * Copyright (c) 2007 Deep Root Systems, LLC
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __DAVINCI_H
-#define __DAVINCI_H
-
-#include <linux/clk.h>
-#include <linux/videodev2.h>
-#include <linux/davinci_emac.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/platform_data/davinci_asp.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/keyscan-davinci.h>
-#include <mach/hardware.h>
-
-#include <media/davinci/vpfe_capture.h>
-#include <media/davinci/vpif_types.h>
-#include <media/davinci/vpss.h>
-#include <media/davinci/vpbe_types.h>
-#include <media/davinci/vpbe_venc.h>
-#include <media/davinci/vpbe.h>
-#include <media/davinci/vpbe_osd.h>
-
-#define DAVINCI_PLL1_BASE 0x01c40800
-#define DAVINCI_PLL2_BASE 0x01c40c00
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
-
-#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
-#define SYSMOD_VDAC_CONFIG 0x2c
-#define SYSMOD_VIDCLKCTL 0x38
-#define SYSMOD_VPSS_CLKCTL 0x44
-#define SYSMOD_VDD3P3VPWDN 0x48
-#define SYSMOD_VSCLKDIS 0x6c
-#define SYSMOD_PUPDCTL1 0x7c
-
-/* VPSS CLKCTL bit definitions */
-#define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1)
-#define VPSS_VENCCLKEN_ENABLE BIT(3)
-#define VPSS_DACCLKEN_ENABLE BIT(4)
-#define VPSS_PLLC2SYSCLK5_ENABLE BIT(5)
-
-extern void __iomem *davinci_sysmod_base;
-#define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x))
-void davinci_map_sysmod(void);
-
-#define DAVINCI_GPIO_BASE 0x01C67000
-int davinci_gpio_register(struct resource *res, int size, void *pdata);
-
-#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
-#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
-
-/* DM355 base addresses */
-#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
-#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-
-#define ASP1_TX_EVT_EN 1
-#define ASP1_RX_EVT_EN 2
-
-/* DM365 base addresses */
-#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
-#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-
-/* DM644x base addresses */
-#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000
-#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
-#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
-
-/* DM646x base addresses */
-#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
-#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
-
-int davinci_init_wdt(void);
-
-/* DM355 function declarations */
-void dm355_init(void);
-void dm355_init_time(void);
-void dm355_init_irq(void);
-void dm355_register_clocks(void);
-void dm355_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len);
-void dm355_init_asp1(u32 evt_enable);
-int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
-int dm355_gpio_register(void);
-
-/* DM365 function declarations */
-void dm365_init(void);
-void dm365_init_irq(void);
-void dm365_init_time(void);
-void dm365_register_clocks(void);
-void dm365_init_asp(void);
-void dm365_init_vc(void);
-void dm365_init_ks(struct davinci_ks_platform_data *pdata);
-void dm365_init_rtc(void);
-void dm365_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len);
-int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
-int dm365_gpio_register(void);
-
-/* DM644x function declarations */
-void dm644x_init(void);
-void dm644x_init_irq(void);
-void dm644x_init_devices(void);
-void dm644x_init_time(void);
-void dm644x_register_clocks(void);
-void dm644x_init_asp(void);
-int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
-int dm644x_gpio_register(void);
-
-/* DM646x function declarations */
-void dm646x_init(void);
-void dm646x_init_irq(void);
-void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
-void dm646x_register_clocks(void);
-void dm646x_init_mcasp0(struct snd_platform_data *pdata);
-void dm646x_init_mcasp1(struct snd_platform_data *pdata);
-int dm646x_init_edma(struct edma_rsv_info *rsv);
-void dm646x_video_init(void);
-void dm646x_setup_vpif(struct vpif_display_config *,
- struct vpif_capture_config *);
-int dm646x_gpio_register(void);
-
-extern struct platform_device dm365_serial_device[];
-extern struct platform_device dm355_serial_device[];
-extern struct platform_device dm644x_serial_device[];
-extern struct platform_device dm646x_serial_device[];
-#endif /*__DAVINCI_H */
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bb368938fc49..6939166c33c2 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -18,11 +18,9 @@
#include <linux/reboot.h>
#include <linux/serial_8250.h>
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/da8xx.h>
-
-#include "asp.h"
+#include "common.h"
+#include "cputype.h"
+#include "da8xx.h"
#include "cpuidle.h"
#include "irqs.h"
#include "sram.h"
@@ -58,911 +56,6 @@
void __iomem *da8xx_syscfg0_base;
void __iomem *da8xx_syscfg1_base;
-static struct plat_serial8250_port da8xx_serial0_pdata[] = {
- {
- .mapbase = DA8XX_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port da8xx_serial1_pdata[] = {
- {
- .mapbase = DA8XX_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port da8xx_serial2_pdata[] = {
- {
- .mapbase = DA8XX_UART2_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device da8xx_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = da8xx_serial0_pdata,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = da8xx_serial1_pdata,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM2,
- .dev = {
- .platform_data = da8xx_serial2_pdata,
- }
- },
- {
- }
-};
-
-static s8 da8xx_queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 3},
- {1, 7},
- {-1, -1}
-};
-
-static s8 da850_queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 3},
- {-1, -1}
-};
-
-static struct edma_soc_info da8xx_edma0_pdata = {
- .queue_priority_mapping = da8xx_queue_priority_mapping,
- .default_queue = EVENTQ_1,
-};
-
-static struct edma_soc_info da850_edma1_pdata = {
- .queue_priority_mapping = da850_queue_priority_mapping,
- .default_queue = EVENTQ_0,
-};
-
-static struct resource da8xx_edma0_resources[] = {
- {
- .name = "edma3_cc",
- .start = DA8XX_TPCC_BASE,
- .end = DA8XX_TPCC_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = DA8XX_TPTC0_BASE,
- .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = DA8XX_TPTC1_BASE,
- .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource da850_edma1_resources[] = {
- {
- .name = "edma3_cc",
- .start = DA850_TPCC1_BASE,
- .end = DA850_TPCC1_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = DA850_TPTC2_BASE,
- .end = DA850_TPTC2_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct platform_device_info da8xx_edma0_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = da8xx_edma0_resources,
- .num_res = ARRAY_SIZE(da8xx_edma0_resources),
- .data = &da8xx_edma0_pdata,
- .size_data = sizeof(da8xx_edma0_pdata),
-};
-
-static const struct platform_device_info da850_edma1_device __initconst = {
- .name = "edma",
- .id = 1,
- .dma_mask = DMA_BIT_MASK(32),
- .res = da850_edma1_resources,
- .num_res = ARRAY_SIZE(da850_edma1_resources),
- .data = &da850_edma1_pdata,
- .size_data = sizeof(da850_edma1_pdata),
-};
-
-static const struct dma_slave_map da830_edma_map[] = {
- { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
- { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
- { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
- { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
- { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
- { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
-};
-
-int __init da830_register_edma(struct edma_rsv_info *rsv)
-{
- struct platform_device *edma_pdev;
-
- da8xx_edma0_pdata.rsv = rsv;
-
- da8xx_edma0_pdata.slave_map = da830_edma_map;
- da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
-
- edma_pdev = platform_device_register_full(&da8xx_edma0_device);
- return PTR_ERR_OR_ZERO(edma_pdev);
-}
-
-static const struct dma_slave_map da850_edma0_map[] = {
- { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
- { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
- { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
- { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
- { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
- { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
-};
-
-static const struct dma_slave_map da850_edma1_map[] = {
- { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
- { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
-};
-
-int __init da850_register_edma(struct edma_rsv_info *rsv[2])
-{
- struct platform_device *edma_pdev;
-
- if (rsv) {
- da8xx_edma0_pdata.rsv = rsv[0];
- da850_edma1_pdata.rsv = rsv[1];
- }
-
- da8xx_edma0_pdata.slave_map = da850_edma0_map;
- da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
-
- edma_pdev = platform_device_register_full(&da8xx_edma0_device);
- if (IS_ERR(edma_pdev)) {
- pr_warn("%s: Failed to register eDMA0\n", __func__);
- return PTR_ERR(edma_pdev);
- }
-
- da850_edma1_pdata.slave_map = da850_edma1_map;
- da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
-
- edma_pdev = platform_device_register_full(&da850_edma1_device);
- return PTR_ERR_OR_ZERO(edma_pdev);
-}
-
-static struct resource da8xx_i2c_resources0[] = {
- {
- .start = DA8XX_I2C0_BASE,
- .end = DA8XX_I2C0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_i2c_device0 = {
- .name = "i2c_davinci",
- .id = 1,
- .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
- .resource = da8xx_i2c_resources0,
-};
-
-static struct resource da8xx_i2c_resources1[] = {
- {
- .start = DA8XX_I2C1_BASE,
- .end = DA8XX_I2C1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_i2c_device1 = {
- .name = "i2c_davinci",
- .id = 2,
- .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
- .resource = da8xx_i2c_resources1,
-};
-
-int __init da8xx_register_i2c(int instance,
- struct davinci_i2c_platform_data *pdata)
-{
- struct platform_device *pdev;
-
- if (instance == 0)
- pdev = &da8xx_i2c_device0;
- else if (instance == 1)
- pdev = &da8xx_i2c_device1;
- else
- return -EINVAL;
-
- pdev->dev.platform_data = pdata;
- return platform_device_register(pdev);
-}
-
-static struct resource da8xx_watchdog_resources[] = {
- {
- .start = DA8XX_WDOG_BASE,
- .end = DA8XX_WDOG_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da8xx_wdt_device = {
- .name = "davinci-wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
- .resource = da8xx_watchdog_resources,
-};
-
-int __init da8xx_register_watchdog(void)
-{
- return platform_device_register(&da8xx_wdt_device);
-}
-
-static struct resource da8xx_emac_resources[] = {
- {
- .start = DA8XX_EMAC_CPPI_PORT_BASE,
- .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct emac_platform_data da8xx_emac_pdata = {
- .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
- .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
- .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
- .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
- .version = EMAC_VERSION_2,
-};
-
-static struct platform_device da8xx_emac_device = {
- .name = "davinci_emac",
- .id = 1,
- .dev = {
- .platform_data = &da8xx_emac_pdata,
- },
- .num_resources = ARRAY_SIZE(da8xx_emac_resources),
- .resource = da8xx_emac_resources,
-};
-
-static struct resource da8xx_mdio_resources[] = {
- {
- .start = DA8XX_EMAC_MDIO_BASE,
- .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device da8xx_mdio_device = {
- .name = "davinci_mdio",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
- .resource = da8xx_mdio_resources,
-};
-
-int __init da8xx_register_emac(void)
-{
- int ret;
-
- ret = platform_device_register(&da8xx_mdio_device);
- if (ret < 0)
- return ret;
-
- return platform_device_register(&da8xx_emac_device);
-}
-
-static struct resource da830_mcasp1_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DA830_MCASP1_REG_BASE,
- .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
- .flags = IORESOURCE_MEM,
- },
- /* TX event */
- {
- .name = "tx",
- .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
- .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
- .flags = IORESOURCE_DMA,
- },
- /* RX event */
- {
- .name = "rx",
- .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
- .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "common",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da830_mcasp1_device = {
- .name = "davinci-mcasp",
- .id = 1,
- .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
- .resource = da830_mcasp1_resources,
-};
-
-static struct resource da830_mcasp2_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DA830_MCASP2_REG_BASE,
- .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
- .flags = IORESOURCE_MEM,
- },
- /* TX event */
- {
- .name = "tx",
- .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
- .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
- .flags = IORESOURCE_DMA,
- },
- /* RX event */
- {
- .name = "rx",
- .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
- .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "common",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da830_mcasp2_device = {
- .name = "davinci-mcasp",
- .id = 2,
- .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
- .resource = da830_mcasp2_resources,
-};
-
-static struct resource da850_mcasp_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
- .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
- .flags = IORESOURCE_MEM,
- },
- /* TX event */
- {
- .name = "tx",
- .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
- .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
- .flags = IORESOURCE_DMA,
- },
- /* RX event */
- {
- .name = "rx",
- .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
- .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "common",
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da850_mcasp_device = {
- .name = "davinci-mcasp",
- .id = 0,
- .num_resources = ARRAY_SIZE(da850_mcasp_resources),
- .resource = da850_mcasp_resources,
-};
-
-void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
-{
- struct platform_device *pdev;
-
- switch (id) {
- case 0:
- /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
- pdev = &da850_mcasp_device;
- break;
- case 1:
- /* Valid for DA830/OMAP-L137 only */
- if (!cpu_is_davinci_da830())
- return;
- pdev = &da830_mcasp1_device;
- break;
- case 2:
- /* Valid for DA830/OMAP-L137 only */
- if (!cpu_is_davinci_da830())
- return;
- pdev = &da830_mcasp2_device;
- break;
- default:
- return;
- }
-
- pdev->dev.platform_data = pdata;
- platform_device_register(pdev);
-}
-
-static struct resource da8xx_pruss_resources[] = {
- {
- .start = DA8XX_PRUSS_MEM_BASE,
- .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
- .pintc_base = 0x4000,
-};
-
-static struct platform_device da8xx_uio_pruss_dev = {
- .name = "pruss_uio",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
- .resource = da8xx_pruss_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &da8xx_uio_pruss_pdata,
- }
-};
-
-int __init da8xx_register_uio_pruss(void)
-{
- da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
- return platform_device_register(&da8xx_uio_pruss_dev);
-}
-
-static struct lcd_ctrl_config lcd_cfg = {
- .panel_shade = COLOR_ACTIVE,
- .bpp = 16,
-};
-
-struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
- .manu_name = "sharp",
- .controller_data = &lcd_cfg,
- .type = "Sharp_LCD035Q3DG01",
-};
-
-struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
- .manu_name = "sharp",
- .controller_data = &lcd_cfg,
- .type = "Sharp_LK043T1DG01",
-};
-
-static struct resource da8xx_lcdc_resources[] = {
- [0] = { /* registers */
- .start = DA8XX_LCD_CNTRL_BASE,
- .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_lcdc_device = {
- .name = "da8xx_lcdc",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
- .resource = da8xx_lcdc_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-
-int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
-{
- da8xx_lcdc_device.dev.platform_data = pdata;
- return platform_device_register(&da8xx_lcdc_device);
-}
-
-static struct resource da8xx_gpio_resources[] = {
- { /* registers */
- .start = DA8XX_GPIO_BASE,
- .end = DA8XX_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_gpio_device = {
- .name = "davinci_gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
- .resource = da8xx_gpio_resources,
-};
-
-int __init da8xx_register_gpio(void *pdata)
-{
- da8xx_gpio_device.dev.platform_data = pdata;
- return platform_device_register(&da8xx_gpio_device);
-}
-
-static struct resource da8xx_mmcsd0_resources[] = {
- { /* registers */
- .start = DA8XX_MMCSD0_BASE,
- .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_mmcsd0_device = {
- .name = "da830-mmc",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
- .resource = da8xx_mmcsd0_resources,
-};
-
-int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
-{
- da8xx_mmcsd0_device.dev.platform_data = config;
- return platform_device_register(&da8xx_mmcsd0_device);
-}
-
-#ifdef CONFIG_ARCH_DAVINCI_DA850
-static struct resource da850_mmcsd1_resources[] = {
- { /* registers */
- .start = DA850_MMCSD1_BASE,
- .end = DA850_MMCSD1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da850_mmcsd1_device = {
- .name = "da830-mmc",
- .id = 1,
- .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
- .resource = da850_mmcsd1_resources,
-};
-
-int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
-{
- da850_mmcsd1_device.dev.platform_data = config;
- return platform_device_register(&da850_mmcsd1_device);
-}
-#endif
-
-static struct resource da8xx_rproc_resources[] = {
- { /* DSP boot address */
- .name = "host1cfg",
- .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
- .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP interrupt registers */
- .name = "chipsig",
- .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
- .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP L2 RAM */
- .name = "l2sram",
- .start = DA8XX_DSP_L2_RAM_BASE,
- .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP L1P RAM */
- .name = "l1pram",
- .start = DA8XX_DSP_L1P_RAM_BASE,
- .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* DSP L1D RAM */
- .name = "l1dram",
- .start = DA8XX_DSP_L1D_RAM_BASE,
- .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* dsp irq */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_dsp = {
- .name = "davinci-rproc",
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
- .resource = da8xx_rproc_resources,
-};
-
-static bool rproc_mem_inited __initdata;
-
-#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
-
-static phys_addr_t rproc_base __initdata;
-static unsigned long rproc_size __initdata;
-
-static int __init early_rproc_mem(char *p)
-{
- char *endp;
-
- if (p == NULL)
- return 0;
-
- rproc_size = memparse(p, &endp);
- if (*endp == '@')
- rproc_base = memparse(endp + 1, NULL);
-
- return 0;
-}
-early_param("rproc_mem", early_rproc_mem);
-
-void __init da8xx_rproc_reserve_cma(void)
-{
- struct cma *cma;
- int ret;
-
- if (!rproc_base || !rproc_size) {
- pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
- " 'nn' and 'address' must both be non-zero\n",
- __func__);
-
- return;
- }
-
- pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
- __func__, rproc_size, (unsigned long)rproc_base);
-
- ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
- true);
- if (ret) {
- pr_err("%s: dma_contiguous_reserve_area failed %d\n",
- __func__, ret);
- return;
- }
- da8xx_dsp.dev.cma_area = cma;
- rproc_mem_inited = true;
-}
-#else
-
-void __init da8xx_rproc_reserve_cma(void)
-{
-}
-
-#endif
-
-int __init da8xx_register_rproc(void)
-{
- int ret;
-
- if (!rproc_mem_inited) {
- pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
- __func__);
- return -ENOMEM;
- }
-
- ret = platform_device_register(&da8xx_dsp);
- if (ret)
- pr_err("%s: can't register DSP device: %d\n", __func__, ret);
-
- return ret;
-};
-
-static struct resource da8xx_rtc_resources[] = {
- {
- .start = DA8XX_RTC_BASE,
- .end = DA8XX_RTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* timer irq */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .flags = IORESOURCE_IRQ,
- },
- { /* alarm irq */
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device da8xx_rtc_device = {
- .name = "da830-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
- .resource = da8xx_rtc_resources,
-};
-
-int da8xx_register_rtc(void)
-{
- return platform_device_register(&da8xx_rtc_device);
-}
-
static void __iomem *da8xx_ddr2_ctlr_base;
void __iomem * __init da8xx_get_mem_ctlr(void)
{
@@ -975,192 +68,3 @@ void __iomem * __init da8xx_get_mem_ctlr(void)
return da8xx_ddr2_ctlr_base;
}
-
-static struct resource da8xx_cpuidle_resources[] = {
- {
- .start = DA8XX_DDR2_CTL_BASE,
- .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-/* DA8XX devices support DDR2 power down */
-static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
- .ddr2_pdown = 1,
-};
-
-
-static struct platform_device da8xx_cpuidle_device = {
- .name = "cpuidle-davinci",
- .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
- .resource = da8xx_cpuidle_resources,
- .dev = {
- .platform_data = &da8xx_cpuidle_pdata,
- },
-};
-
-int __init da8xx_register_cpuidle(void)
-{
- da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
-
- return platform_device_register(&da8xx_cpuidle_device);
-}
-
-static struct resource da8xx_spi0_resources[] = {
- [0] = {
- .start = DA8XX_SPI0_BASE,
- .end = DA8XX_SPI0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource da8xx_spi1_resources[] = {
- [0] = {
- .start = DA830_SPI1_BASE,
- .end = DA830_SPI1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
- [0] = {
- .version = SPI_VERSION_2,
- .intr_line = 1,
- .dma_event_q = EVENTQ_0,
- .prescaler_limit = 2,
- },
- [1] = {
- .version = SPI_VERSION_2,
- .intr_line = 1,
- .dma_event_q = EVENTQ_0,
- .prescaler_limit = 2,
- },
-};
-
-static struct platform_device da8xx_spi_device[] = {
- [0] = {
- .name = "spi_davinci",
- .id = 0,
- .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
- .resource = da8xx_spi0_resources,
- .dev = {
- .platform_data = &da8xx_spi_pdata[0],
- },
- },
- [1] = {
- .name = "spi_davinci",
- .id = 1,
- .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
- .resource = da8xx_spi1_resources,
- .dev = {
- .platform_data = &da8xx_spi_pdata[1],
- },
- },
-};
-
-int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
-{
- if (instance < 0 || instance > 1)
- return -EINVAL;
-
- da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
-
- if (instance == 1 && cpu_is_davinci_da850()) {
- da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
- da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
- }
-
- return platform_device_register(&da8xx_spi_device[instance]);
-}
-
-#ifdef CONFIG_ARCH_DAVINCI_DA850
-int __init da850_register_sata_refclk(int rate)
-{
- struct clk *clk;
-
- clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- return clk_register_clkdev(clk, "refclk", "ahci_da850");
-}
-
-static struct resource da850_sata_resources[] = {
- {
- .start = DA850_SATA_BASE,
- .end = DA850_SATA_BASE + 0x1fff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
- .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device da850_sata_device = {
- .name = "ahci_da850",
- .id = -1,
- .dev = {
- .dma_mask = &da850_sata_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(da850_sata_resources),
- .resource = da850_sata_resources,
-};
-
-int __init da850_register_sata(unsigned long refclkpn)
-{
- int ret;
-
- ret = da850_register_sata_refclk(refclkpn);
- if (ret)
- return ret;
-
- return platform_device_register(&da850_sata_device);
-}
-#endif
-
-static struct regmap *da8xx_cfgchip;
-
-static const struct regmap_config da8xx_cfgchip_config __initconst = {
- .name = "cfgchip",
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
-};
-
-/**
- * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
- *
- * This is for use on non-DT boards only. For DT boards, use
- * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
- *
- * Returns: Pointer to the CFGCHIP regmap or negative error code.
- */
-struct regmap * __init da8xx_get_cfgchip(void)
-{
- if (IS_ERR_OR_NULL(da8xx_cfgchip))
- da8xx_cfgchip = regmap_init_mmio(NULL,
- DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
- &da8xx_cfgchip_config);
-
- return da8xx_cfgchip;
-}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
deleted file mode 100644
index 849e811fade7..000000000000
--- a/arch/arm/mach-davinci/devices.c
+++ /dev/null
@@ -1,304 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * mach-davinci/devices.c
- *
- * DaVinci platform device setup/initialization
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/edma.h>
-#include <linux/dma-mapping.h>
-#include <linux/io.h>
-#include <linux/reboot.h>
-
-#include <mach/hardware.h>
-#include <mach/cputype.h>
-#include <mach/mux.h>
-
-#include "davinci.h"
-#include "irqs.h"
-
-#define DAVINCI_I2C_BASE 0x01C21000
-#define DAVINCI_ATA_BASE 0x01C66000
-#define DAVINCI_MMCSD0_BASE 0x01E10000
-#define DM355_MMCSD0_BASE 0x01E11000
-#define DM355_MMCSD1_BASE 0x01E00000
-#define DM365_MMCSD0_BASE 0x01D11000
-#define DM365_MMCSD1_BASE 0x01D00000
-
-void __iomem *davinci_sysmod_base;
-
-void davinci_map_sysmod(void)
-{
- davinci_sysmod_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE,
- 0x800);
- /*
- * Throw a bug since a lot of board initialization code depends
- * on system module availability. ioremap() failing this early
- * need careful looking into anyway.
- */
- BUG_ON(!davinci_sysmod_base);
-}
-
-static struct resource i2c_resources[] = {
- {
- .start = DAVINCI_I2C_BASE,
- .end = DAVINCI_I2C_BASE + 0x40,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_I2C),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device davinci_i2c_device = {
- .name = "i2c_davinci",
- .id = 1,
- .num_resources = ARRAY_SIZE(i2c_resources),
- .resource = i2c_resources,
-};
-
-void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
-{
- if (cpu_is_davinci_dm644x())
- davinci_cfg_reg(DM644X_I2C);
-
- davinci_i2c_device.dev.platform_data = pdata;
- (void) platform_device_register(&davinci_i2c_device);
-}
-
-static struct resource ide_resources[] = {
- {
- .start = DAVINCI_ATA_BASE,
- .end = DAVINCI_ATA_BASE + 0x7ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_IDE),
- .end = DAVINCI_INTC_IRQ(IRQ_IDE),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 ide_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_device = {
- .name = "palm_bk3710",
- .id = -1,
- .resource = ide_resources,
- .num_resources = ARRAY_SIZE(ide_resources),
- .dev = {
- .dma_mask = &ide_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init davinci_init_ide(void)
-{
- if (cpu_is_davinci_dm644x()) {
- davinci_cfg_reg(DM644X_HPIEN_DISABLE);
- davinci_cfg_reg(DM644X_ATAEN);
- davinci_cfg_reg(DM644X_HDIREN);
- } else if (cpu_is_davinci_dm646x()) {
- /* IRQ_DM646X_IDE is the same as IRQ_IDE */
- davinci_cfg_reg(DM646X_ATAEN);
- } else {
- WARN_ON(1);
- return;
- }
-
- platform_device_register(&ide_device);
-}
-
-#if IS_ENABLED(CONFIG_MMC_DAVINCI)
-
-static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource mmcsd0_resources[] = {
- {
- /* different on dm355 */
- .start = DAVINCI_MMCSD0_BASE,
- .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- /* IRQs: MMC/SD, then SDIO */
- {
- .start = DAVINCI_INTC_IRQ(IRQ_MMCINT),
- .flags = IORESOURCE_IRQ,
- }, {
- /* different on dm355 */
- .start = DAVINCI_INTC_IRQ(IRQ_SDIOINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device davinci_mmcsd0_device = {
- .name = "dm6441-mmc",
- .id = 0,
- .dev = {
- .dma_mask = &mmcsd0_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(mmcsd0_resources),
- .resource = mmcsd0_resources,
-};
-
-static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource mmcsd1_resources[] = {
- {
- .start = DM355_MMCSD1_BASE,
- .end = DM355_MMCSD1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- /* IRQs: MMC/SD, then SDIO */
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1),
- .flags = IORESOURCE_IRQ,
- }, {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device davinci_mmcsd1_device = {
- .name = "dm6441-mmc",
- .id = 1,
- .dev = {
- .dma_mask = &mmcsd1_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(mmcsd1_resources),
- .resource = mmcsd1_resources,
-};
-
-
-void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
-{
- struct platform_device *pdev = NULL;
-
- if (WARN_ON(cpu_is_davinci_dm646x()))
- return;
-
- /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
- * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
- *
- * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
- * not handled right here ...
- */
- switch (module) {
- case 1:
- if (cpu_is_davinci_dm355()) {
- /* REVISIT we may not need all these pins if e.g. this
- * is a hard-wired SDIO device...
- */
- davinci_cfg_reg(DM355_SD1_CMD);
- davinci_cfg_reg(DM355_SD1_CLK);
- davinci_cfg_reg(DM355_SD1_DATA0);
- davinci_cfg_reg(DM355_SD1_DATA1);
- davinci_cfg_reg(DM355_SD1_DATA2);
- davinci_cfg_reg(DM355_SD1_DATA3);
- } else if (cpu_is_davinci_dm365()) {
- /* Configure pull down control */
- unsigned v;
-
- v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
- __raw_writel(v & ~0xfc0,
- DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
-
- mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
- mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
- SZ_4K - 1;
- mmcsd1_resources[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM365_SDIOINT1);
- davinci_mmcsd1_device.name = "da830-mmc";
- } else
- break;
-
- pdev = &davinci_mmcsd1_device;
- break;
- case 0:
- if (cpu_is_davinci_dm355()) {
- mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
- mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
- mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM355_SDIOINT0);
-
- /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
- davinci_cfg_reg(DM355_MMCSD0);
-
- /* enable RX EDMA */
- davinci_cfg_reg(DM355_EVT26_MMC0_RX);
- } else if (cpu_is_davinci_dm365()) {
- mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
- mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
- SZ_4K - 1;
- mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM365_SDIOINT0);
- davinci_mmcsd0_device.name = "da830-mmc";
- } else if (cpu_is_davinci_dm644x()) {
- /* REVISIT: should this be in board-init code? */
- /* Power-on 3.3V IO cells */
- __raw_writel(0,
- DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
- /*Set up the pull regiter for MMC */
- davinci_cfg_reg(DM644X_MSTK);
- }
-
- pdev = &davinci_mmcsd0_device;
- break;
- }
-
- if (WARN_ON(!pdev))
- return;
-
- pdev->dev.platform_data = config;
- platform_device_register(pdev);
-}
-
-#else
-
-void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
-{
-}
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-static struct resource wdt_resources[] = {
- {
- .start = DAVINCI_WDOG_BASE,
- .end = DAVINCI_WDOG_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device davinci_wdt_device = {
- .name = "davinci-wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(wdt_resources),
- .resource = wdt_resources,
-};
-
-int davinci_init_wdt(void)
-{
- return platform_device_register(&davinci_wdt_device);
-}
-
-static struct platform_device davinci_gpio_device = {
- .name = "davinci_gpio",
- .id = -1,
-};
-
-int davinci_gpio_register(struct resource *res, int size, void *pdata)
-{
- davinci_gpio_device.resource = res;
- davinci_gpio_device.num_resources = size;
- davinci_gpio_device.dev.platform_data = pdata;
- return platform_device_register(&davinci_gpio_device);
-}
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
deleted file mode 100644
index 5de72d2fa8f0..000000000000
--- a/arch/arm/mach-davinci/dm355.c
+++ /dev/null
@@ -1,836 +0,0 @@
-/*
- * TI DaVinci DM355 chip specific setup
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-aintc.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/mux.h>
-#include <mach/serial.h>
-
-#include <clocksource/timer-davinci.h>
-
-#include "asp.h"
-#include "davinci.h"
-#include "irqs.h"
-#include "mux.h"
-
-#define DM355_UART2_BASE (IO_PHYS + 0x206000)
-#define DM355_OSD_BASE (IO_PHYS + 0x70200)
-#define DM355_VENC_BASE (IO_PHYS + 0x70400)
-
-/*
- * Device specific clocks
- */
-#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
-
-static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource dm355_spi0_resources[] = {
- {
- .start = 0x01c66000,
- .end = 0x01c667ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_spi_platform_data dm355_spi0_pdata = {
- .version = SPI_VERSION_1,
- .num_chipselect = 2,
- .cshold_bug = true,
- .dma_event_q = EVENTQ_1,
- .prescaler_limit = 1,
-};
-static struct platform_device dm355_spi0_device = {
- .name = "spi_davinci",
- .id = 0,
- .dev = {
- .dma_mask = &dm355_spi0_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dm355_spi0_pdata,
- },
- .num_resources = ARRAY_SIZE(dm355_spi0_resources),
- .resource = dm355_spi0_resources,
-};
-
-void __init dm355_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len)
-{
- /* for now, assume we need MISO */
- davinci_cfg_reg(DM355_SPI0_SDI);
-
- /* not all slaves will be wired up */
- if (chipselect_mask & BIT(0))
- davinci_cfg_reg(DM355_SPI0_SDENA0);
- if (chipselect_mask & BIT(1))
- davinci_cfg_reg(DM355_SPI0_SDENA1);
-
- spi_register_board_info(info, len);
-
- platform_device_register(&dm355_spi0_device);
-}
-
-/*----------------------------------------------------------------------*/
-
-#define INTMUX 0x18
-#define EVTMUX 0x1c
-
-/*
- * Device specific mux setup
- *
- * soc description mux mode mode mux dbg
- * reg offset mask mode
- */
-static const struct mux_config dm355_pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
-
-MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
-MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
-MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
-MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
-MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
-MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
-
-MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
-MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
-
-MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
-MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
-
-MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
-MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
-MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
-
-INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
-INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
-INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
-
-EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
-EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
-EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
-
-MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
-MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
-MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
-MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
-MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
-
-MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
-MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
-MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
-MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
-MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
-MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
-MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
-#endif
-};
-
-static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
- [IRQ_DM355_CCDC_VDINT0] = 2,
- [IRQ_DM355_CCDC_VDINT1] = 6,
- [IRQ_DM355_CCDC_VDINT2] = 6,
- [IRQ_DM355_IPIPE_HST] = 6,
- [IRQ_DM355_H3AINT] = 6,
- [IRQ_DM355_IPIPE_SDR] = 6,
- [IRQ_DM355_IPIPEIFINT] = 6,
- [IRQ_DM355_OSDINT] = 7,
- [IRQ_DM355_VENCINT] = 6,
- [IRQ_ASQINT] = 6,
- [IRQ_IMXINT] = 6,
- [IRQ_USBINT] = 4,
- [IRQ_DM355_RTOINT] = 4,
- [IRQ_DM355_UARTINT2] = 7,
- [IRQ_DM355_TINT6] = 7,
- [IRQ_CCINT0] = 5, /* dma */
- [IRQ_CCERRINT] = 5, /* dma */
- [IRQ_TCERRINT0] = 5, /* dma */
- [IRQ_TCERRINT] = 5, /* dma */
- [IRQ_DM355_SPINT2_1] = 7,
- [IRQ_DM355_TINT7] = 4,
- [IRQ_DM355_SDIOINT0] = 7,
- [IRQ_MBXINT] = 7,
- [IRQ_MBRINT] = 7,
- [IRQ_MMCINT] = 7,
- [IRQ_DM355_MMCINT1] = 7,
- [IRQ_DM355_PWMINT3] = 7,
- [IRQ_DDRINT] = 7,
- [IRQ_AEMIFINT] = 7,
- [IRQ_DM355_SDIOINT1] = 4,
- [IRQ_TINT0_TINT12] = 2, /* clockevent */
- [IRQ_TINT0_TINT34] = 2, /* clocksource */
- [IRQ_TINT1_TINT12] = 7, /* DSP timer */
- [IRQ_TINT1_TINT34] = 7, /* system tick */
- [IRQ_PWMINT0] = 7,
- [IRQ_PWMINT1] = 7,
- [IRQ_PWMINT2] = 7,
- [IRQ_I2C] = 3,
- [IRQ_UARTINT0] = 3,
- [IRQ_UARTINT1] = 3,
- [IRQ_DM355_SPINT0_0] = 3,
- [IRQ_DM355_SPINT0_1] = 3,
- [IRQ_DM355_GPIO0] = 3,
- [IRQ_DM355_GPIO1] = 7,
- [IRQ_DM355_GPIO2] = 4,
- [IRQ_DM355_GPIO3] = 4,
- [IRQ_DM355_GPIO4] = 7,
- [IRQ_DM355_GPIO5] = 7,
- [IRQ_DM355_GPIO6] = 7,
- [IRQ_DM355_GPIO7] = 7,
- [IRQ_DM355_GPIO8] = 7,
- [IRQ_DM355_GPIO9] = 7,
- [IRQ_DM355_GPIOBNK0] = 7,
- [IRQ_DM355_GPIOBNK1] = 7,
- [IRQ_DM355_GPIOBNK2] = 7,
- [IRQ_DM355_GPIOBNK3] = 7,
- [IRQ_DM355_GPIOBNK4] = 7,
- [IRQ_DM355_GPIOBNK5] = 7,
- [IRQ_DM355_GPIOBNK6] = 7,
- [IRQ_COMMTX] = 7,
- [IRQ_COMMRX] = 7,
- [IRQ_EMUINT] = 7,
-};
-
-/*----------------------------------------------------------------------*/
-
-static s8 queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 3},
- {1, 7},
- {-1, -1},
-};
-
-static const struct dma_slave_map dm355_edma_map[] = {
- { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
- { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
- { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
- { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
- { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
- { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
- { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
- { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
-};
-
-static struct edma_soc_info dm355_edma_pdata = {
- .queue_priority_mapping = queue_priority_mapping,
- .default_queue = EVENTQ_1,
- .slave_map = dm355_edma_map,
- .slavecnt = ARRAY_SIZE(dm355_edma_map),
-};
-
-static struct resource edma_resources[] = {
- {
- .name = "edma3_cc",
- .start = 0x01c00000,
- .end = 0x01c00000 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = 0x01c10000,
- .end = 0x01c10000 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = 0x01c10400,
- .end = 0x01c10400 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
- /* not using (or muxing) TC*_ERR */
-};
-
-static const struct platform_device_info dm355_edma_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = edma_resources,
- .num_res = ARRAY_SIZE(edma_resources),
- .data = &dm355_edma_pdata,
- .size_data = sizeof(dm355_edma_pdata),
-};
-
-static struct resource dm355_asp1_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_ASP1_BASE,
- .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_DMA_ASP1_TX,
- .end = DAVINCI_DMA_ASP1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DAVINCI_DMA_ASP1_RX,
- .end = DAVINCI_DMA_ASP1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device dm355_asp1_device = {
- .name = "davinci-mcbsp",
- .id = 1,
- .num_resources = ARRAY_SIZE(dm355_asp1_resources),
- .resource = dm355_asp1_resources,
-};
-
-static void dm355_ccdc_setup_pinmux(void)
-{
- davinci_cfg_reg(DM355_VIN_PCLK);
- davinci_cfg_reg(DM355_VIN_CAM_WEN);
- davinci_cfg_reg(DM355_VIN_CAM_VD);
- davinci_cfg_reg(DM355_VIN_CAM_HD);
- davinci_cfg_reg(DM355_VIN_YIN_EN);
- davinci_cfg_reg(DM355_VIN_CINL_EN);
- davinci_cfg_reg(DM355_VIN_CINH_EN);
-}
-
-static struct resource dm355_vpss_resources[] = {
- {
- /* VPSS BL Base address */
- .name = "vpss",
- .start = 0x01c70800,
- .end = 0x01c70800 + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- /* VPSS CLK Base address */
- .name = "vpss",
- .start = 0x01c70000,
- .end = 0x01c70000 + 0xf,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm355_vpss_device = {
- .name = "vpss",
- .id = -1,
- .dev.platform_data = "dm355_vpss",
- .num_resources = ARRAY_SIZE(dm355_vpss_resources),
- .resource = dm355_vpss_resources,
-};
-
-static struct resource vpfe_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
-static struct resource dm355_ccdc_resource[] = {
- /* CCDC Base address */
- {
- .flags = IORESOURCE_MEM,
- .start = 0x01c70600,
- .end = 0x01c70600 + 0x1ff,
- },
-};
-static struct platform_device dm355_ccdc_dev = {
- .name = "dm355_ccdc",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
- .resource = dm355_ccdc_resource,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = dm355_ccdc_setup_pinmux,
- },
-};
-
-static struct platform_device vpfe_capture_dev = {
- .name = CAPTURE_DRV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(vpfe_resources),
- .resource = vpfe_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm355_osd_resources[] = {
- {
- .start = DM355_OSD_BASE,
- .end = DM355_OSD_BASE + 0x17f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm355_osd_dev = {
- .name = DM355_VPBE_OSD_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_osd_resources),
- .resource = dm355_osd_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm355_venc_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM355_VENC_BASE,
- .end = DM355_VENC_BASE + 0x17f,
- .flags = IORESOURCE_MEM,
- },
- /* VDAC config register io space */
- {
- .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
- .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource dm355_v4l2_disp_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM355_VENC_BASE,
- .end = DM355_VENC_BASE + 0x17f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
-{
- switch (if_type) {
- case MEDIA_BUS_FMT_SGRBG8_1X8:
- davinci_cfg_reg(DM355_VOUT_FIELD_G70);
- break;
- case MEDIA_BUS_FMT_YUYV10_1X20:
- if (field)
- davinci_cfg_reg(DM355_VOUT_FIELD);
- else
- davinci_cfg_reg(DM355_VOUT_FIELD_G70);
- break;
- default:
- return -EINVAL;
- }
-
- davinci_cfg_reg(DM355_VOUT_COUTL_EN);
- davinci_cfg_reg(DM355_VOUT_COUTH_EN);
-
- return 0;
-}
-
-static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
- unsigned int pclock)
-{
- void __iomem *vpss_clk_ctrl_reg;
-
- vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
-
- switch (type) {
- case VPBE_ENC_STD:
- writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
- vpss_clk_ctrl_reg);
- break;
- case VPBE_ENC_DV_TIMINGS:
- if (pclock > 27000000)
- /*
- * For HD, use external clock source since we cannot
- * support HD mode with internal clocks.
- */
- writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static struct platform_device dm355_vpbe_display = {
- .name = "vpbe-v4l2",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
- .resource = dm355_v4l2_disp_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct venc_platform_data dm355_venc_pdata = {
- .setup_pinmux = dm355_vpbe_setup_pinmux,
- .setup_clock = dm355_venc_setup_clock,
-};
-
-static struct platform_device dm355_venc_dev = {
- .name = DM355_VPBE_VENC_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm355_venc_resources),
- .resource = dm355_venc_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = (void *)&dm355_venc_pdata,
- },
-};
-
-static struct platform_device dm355_vpbe_dev = {
- .name = "vpbe_controller",
- .id = -1,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm355_gpio_resources[] = {
- { /* registers */
- .start = DAVINCI_GPIO_BASE,
- .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
- .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 104,
-};
-
-int __init dm355_gpio_register(void)
-{
- return davinci_gpio_register(dm355_gpio_resources,
- ARRAY_SIZE(dm355_gpio_resources),
- &dm355_gpio_platform_data);
-}
-/*----------------------------------------------------------------------*/
-
-static struct map_desc dm355_io_desc[] = {
- {
- .virtual = IO_VIRT,
- .pfn = __phys_to_pfn(IO_PHYS),
- .length = IO_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id dm355_ids[] = {
- {
- .variant = 0x0,
- .part_no = 0xb73b,
- .manufacturer = 0x00f,
- .cpu_id = DAVINCI_CPU_ID_DM355,
- .name = "dm355",
- },
-};
-
-/*
- * Bottom half of timer0 is used for clockevent, top half is used for
- * clocksource.
- */
-static const struct davinci_timer_cfg dm355_timer_cfg = {
- .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
- },
-};
-
-static struct plat_serial8250_port dm355_serial0_platform_data[] = {
- {
- .mapbase = DAVINCI_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm355_serial1_platform_data[] = {
- {
- .mapbase = DAVINCI_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm355_serial2_platform_data[] = {
- {
- .mapbase = DM355_UART2_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device dm355_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = dm355_serial0_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = dm355_serial1_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM2,
- .dev = {
- .platform_data = dm355_serial2_platform_data,
- }
- },
- {
- }
-};
-
-static const struct davinci_soc_info davinci_soc_info_dm355 = {
- .io_desc = dm355_io_desc,
- .io_desc_num = ARRAY_SIZE(dm355_io_desc),
- .jtag_id_reg = 0x01c40028,
- .ids = dm355_ids,
- .ids_num = ARRAY_SIZE(dm355_ids),
- .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
- .pinmux_pins = dm355_pins,
- .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
- .sram_dma = 0x00010000,
- .sram_len = SZ_32K,
-};
-
-void __init dm355_init_asp1(u32 evt_enable)
-{
- /* we don't use ASP1 IRQs, or we'd need to mux them ... */
- if (evt_enable & ASP1_TX_EVT_EN)
- davinci_cfg_reg(DM355_EVT8_ASP1_TX);
-
- if (evt_enable & ASP1_RX_EVT_EN)
- davinci_cfg_reg(DM355_EVT9_ASP1_RX);
-
- platform_device_register(&dm355_asp1_device);
-}
-
-void __init dm355_init(void)
-{
- davinci_common_init(&davinci_soc_info_dm355);
- davinci_map_sysmod();
-}
-
-void __init dm355_init_time(void)
-{
- void __iomem *pll1, *psc;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
-
- pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
- dm355_pll1_init(NULL, pll1, NULL);
-
- psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
- dm355_psc_init(NULL, psc);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &dm355_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource dm355_pll2_resources[] = {
- {
- .start = DAVINCI_PLL2_BASE,
- .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm355_pll2_device = {
- .name = "dm355-pll2",
- .id = -1,
- .resource = dm355_pll2_resources,
- .num_resources = ARRAY_SIZE(dm355_pll2_resources),
-};
-
-void __init dm355_register_clocks(void)
-{
- /* PLL1 and PSC are registered in dm355_init_time() */
- platform_device_register(&dm355_pll2_device);
-}
-
-int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
- struct vpbe_config *vpbe_cfg)
-{
- if (vpfe_cfg || vpbe_cfg)
- platform_device_register(&dm355_vpss_device);
-
- if (vpfe_cfg) {
- vpfe_capture_dev.dev.platform_data = vpfe_cfg;
- platform_device_register(&dm355_ccdc_dev);
- platform_device_register(&vpfe_capture_dev);
- }
-
- if (vpbe_cfg) {
- dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
- platform_device_register(&dm355_osd_dev);
- platform_device_register(&dm355_venc_dev);
- platform_device_register(&dm355_vpbe_dev);
- platform_device_register(&dm355_vpbe_display);
- }
-
- return 0;
-}
-
-static const struct davinci_aintc_config dm355_aintc_config = {
- .reg = {
- .start = DAVINCI_ARM_INTC_BASE,
- .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = 64,
- .prios = dm355_default_priorities,
-};
-
-void __init dm355_init_irq(void)
-{
- davinci_aintc_init(&dm355_aintc_config);
-}
-
-static int __init dm355_init_devices(void)
-{
- struct platform_device *edma_pdev;
- int ret = 0;
-
- if (!cpu_is_davinci_dm355())
- return 0;
-
- davinci_cfg_reg(DM355_INT_EDMA_CC);
- edma_pdev = platform_device_register_full(&dm355_edma_device);
- if (IS_ERR(edma_pdev)) {
- pr_warn("%s: Failed to register eDMA\n", __func__);
- return PTR_ERR(edma_pdev);
- }
-
- ret = davinci_init_wdt();
- if (ret)
- pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
-
- return ret;
-}
-postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
deleted file mode 100644
index c1e0d46996e4..000000000000
--- a/arch/arm/mach-davinci/dm365.c
+++ /dev/null
@@ -1,1104 +0,0 @@
-/*
- * TI DaVinci DM365 chip specific setup
- *
- * Copyright (C) 2009 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-aintc.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_data/keyscan-davinci.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/mux.h>
-#include <mach/serial.h>
-
-#include <clocksource/timer-davinci.h>
-
-#include "asp.h"
-#include "davinci.h"
-#include "irqs.h"
-#include "mux.h"
-
-#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
-#define DM365_RTC_BASE 0x01c69000
-#define DM365_KEYSCAN_BASE 0x01c69400
-#define DM365_OSD_BASE 0x01c71c00
-#define DM365_VENC_BASE 0x01c71e00
-#define DAVINCI_DM365_VC_BASE 0x01d0c000
-#define DAVINCI_DMA_VC_TX 2
-#define DAVINCI_DMA_VC_RX 3
-#define DM365_EMAC_BASE 0x01d07000
-#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
-#define DM365_EMAC_CNTRL_OFFSET 0x0000
-#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
-#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
-#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
-
-#define INTMUX 0x18
-#define EVTMUX 0x1c
-
-
-static const struct mux_config dm365_pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
-
-MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
-MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
-MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
-
-MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
-MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
-
-MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
-MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
-MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
-MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
-MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
-MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
-MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
-MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
-
-MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
-MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
-
-MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
-MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
-MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
-MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
-MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
-
-MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
-MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
-MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
-MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
-MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
-MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
-
-MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
-MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
-MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
-MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
-MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
-MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
-MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
-MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
-MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
-MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
-MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
-
-MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
-
-MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
-MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
-MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
-MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
-MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
-MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
-MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
-MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
-MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
-MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
-MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
-MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
-
-MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
-MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
-MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
-MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
-MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
-
-MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
-MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
-
-MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
-MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
-
-MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
-MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
-
-MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
-MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
-MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
-
-MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
-MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
-MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
-MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
-MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
-MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
-MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
-
-MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
-MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
-MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
-MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
-MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
-MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
-MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
-MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
-MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
-MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
-
-INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
-INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
-INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
-INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
-INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
-INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
-INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
-INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
-INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
-INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
-INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
-INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
-
-EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
-EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
-EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
-EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
-#endif
-};
-
-static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
-
-static struct davinci_spi_platform_data dm365_spi0_pdata = {
- .version = SPI_VERSION_1,
- .num_chipselect = 2,
- .dma_event_q = EVENTQ_3,
- .prescaler_limit = 1,
-};
-
-static struct resource dm365_spi0_resources[] = {
- {
- .start = 0x01c66000,
- .end = 0x01c667ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_spi0_device = {
- .name = "spi_davinci",
- .id = 0,
- .dev = {
- .dma_mask = &dm365_spi0_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dm365_spi0_pdata,
- },
- .num_resources = ARRAY_SIZE(dm365_spi0_resources),
- .resource = dm365_spi0_resources,
-};
-
-void __init dm365_init_spi0(unsigned chipselect_mask,
- const struct spi_board_info *info, unsigned len)
-{
- davinci_cfg_reg(DM365_SPI0_SCLK);
- davinci_cfg_reg(DM365_SPI0_SDI);
- davinci_cfg_reg(DM365_SPI0_SDO);
-
- /* not all slaves will be wired up */
- if (chipselect_mask & BIT(0))
- davinci_cfg_reg(DM365_SPI0_SDENA0);
- if (chipselect_mask & BIT(1))
- davinci_cfg_reg(DM365_SPI0_SDENA1);
-
- spi_register_board_info(info, len);
-
- platform_device_register(&dm365_spi0_device);
-}
-
-static struct resource dm365_gpio_resources[] = {
- { /* registers */
- .start = DAVINCI_GPIO_BASE,
- .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 104,
- .gpio_unbanked = 8,
-};
-
-int __init dm365_gpio_register(void)
-{
- return davinci_gpio_register(dm365_gpio_resources,
- ARRAY_SIZE(dm365_gpio_resources),
- &dm365_gpio_platform_data);
-}
-
-static struct emac_platform_data dm365_emac_pdata = {
- .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
- .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
- .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
- .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
- .version = EMAC_VERSION_2,
-};
-
-static struct resource dm365_emac_resources[] = {
- {
- .start = DM365_EMAC_BASE,
- .end = DM365_EMAC_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_emac_device = {
- .name = "davinci_emac",
- .id = 1,
- .dev = {
- .platform_data = &dm365_emac_pdata,
- },
- .num_resources = ARRAY_SIZE(dm365_emac_resources),
- .resource = dm365_emac_resources,
-};
-
-static struct resource dm365_mdio_resources[] = {
- {
- .start = DM365_EMAC_MDIO_BASE,
- .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm365_mdio_device = {
- .name = "davinci_mdio",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm365_mdio_resources),
- .resource = dm365_mdio_resources,
-};
-
-static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
- [IRQ_VDINT0] = 2,
- [IRQ_VDINT1] = 6,
- [IRQ_VDINT2] = 6,
- [IRQ_HISTINT] = 6,
- [IRQ_H3AINT] = 6,
- [IRQ_PRVUINT] = 6,
- [IRQ_RSZINT] = 6,
- [IRQ_DM365_INSFINT] = 7,
- [IRQ_VENCINT] = 6,
- [IRQ_ASQINT] = 6,
- [IRQ_IMXINT] = 6,
- [IRQ_DM365_IMCOPINT] = 4,
- [IRQ_USBINT] = 4,
- [IRQ_DM365_RTOINT] = 7,
- [IRQ_DM365_TINT5] = 7,
- [IRQ_DM365_TINT6] = 5,
- [IRQ_CCINT0] = 5,
- [IRQ_CCERRINT] = 5,
- [IRQ_TCERRINT0] = 5,
- [IRQ_TCERRINT] = 7,
- [IRQ_PSCIN] = 4,
- [IRQ_DM365_SPINT2_1] = 7,
- [IRQ_DM365_TINT7] = 7,
- [IRQ_DM365_SDIOINT0] = 7,
- [IRQ_MBXINT] = 7,
- [IRQ_MBRINT] = 7,
- [IRQ_MMCINT] = 7,
- [IRQ_DM365_MMCINT1] = 7,
- [IRQ_DM365_PWMINT3] = 7,
- [IRQ_AEMIFINT] = 2,
- [IRQ_DM365_SDIOINT1] = 2,
- [IRQ_TINT0_TINT12] = 7,
- [IRQ_TINT0_TINT34] = 7,
- [IRQ_TINT1_TINT12] = 7,
- [IRQ_TINT1_TINT34] = 7,
- [IRQ_PWMINT0] = 7,
- [IRQ_PWMINT1] = 3,
- [IRQ_PWMINT2] = 3,
- [IRQ_I2C] = 3,
- [IRQ_UARTINT0] = 3,
- [IRQ_UARTINT1] = 3,
- [IRQ_DM365_RTCINT] = 3,
- [IRQ_DM365_SPIINT0_0] = 3,
- [IRQ_DM365_SPIINT3_0] = 3,
- [IRQ_DM365_GPIO0] = 3,
- [IRQ_DM365_GPIO1] = 7,
- [IRQ_DM365_GPIO2] = 4,
- [IRQ_DM365_GPIO3] = 4,
- [IRQ_DM365_GPIO4] = 7,
- [IRQ_DM365_GPIO5] = 7,
- [IRQ_DM365_GPIO6] = 7,
- [IRQ_DM365_GPIO7] = 7,
- [IRQ_DM365_EMAC_RXTHRESH] = 7,
- [IRQ_DM365_EMAC_RXPULSE] = 7,
- [IRQ_DM365_EMAC_TXPULSE] = 7,
- [IRQ_DM365_EMAC_MISCPULSE] = 7,
- [IRQ_DM365_GPIO12] = 7,
- [IRQ_DM365_GPIO13] = 7,
- [IRQ_DM365_GPIO14] = 7,
- [IRQ_DM365_GPIO15] = 7,
- [IRQ_DM365_KEYINT] = 7,
- [IRQ_DM365_TCERRINT2] = 7,
- [IRQ_DM365_TCERRINT3] = 7,
- [IRQ_DM365_EMUINT] = 7,
-};
-
-/* Four Transfer Controllers on DM365 */
-static s8 dm365_queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 7},
- {1, 7},
- {2, 7},
- {3, 0},
- {-1, -1},
-};
-
-static const struct dma_slave_map dm365_edma_map[] = {
- { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
- { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
- { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
- { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
- { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
- { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
- { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
- { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
- { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
- { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
- { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
- { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
- { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
- { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
-};
-
-static struct edma_soc_info dm365_edma_pdata = {
- .queue_priority_mapping = dm365_queue_priority_mapping,
- .default_queue = EVENTQ_3,
- .slave_map = dm365_edma_map,
- .slavecnt = ARRAY_SIZE(dm365_edma_map),
-};
-
-static struct resource edma_resources[] = {
- {
- .name = "edma3_cc",
- .start = 0x01c00000,
- .end = 0x01c00000 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = 0x01c10000,
- .end = 0x01c10000 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = 0x01c10400,
- .end = 0x01c10400 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc2",
- .start = 0x01c10800,
- .end = 0x01c10800 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc3",
- .start = 0x01c10c00,
- .end = 0x01c10c00 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
- /* not using TC*_ERR */
-};
-
-static const struct platform_device_info dm365_edma_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = edma_resources,
- .num_res = ARRAY_SIZE(edma_resources),
- .data = &dm365_edma_pdata,
- .size_data = sizeof(dm365_edma_pdata),
-};
-
-static struct resource dm365_asp_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DM365_ASP0_BASE,
- .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_DMA_ASP0_TX,
- .end = DAVINCI_DMA_ASP0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DAVINCI_DMA_ASP0_RX,
- .end = DAVINCI_DMA_ASP0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device dm365_asp_device = {
- .name = "davinci-mcbsp",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_asp_resources),
- .resource = dm365_asp_resources,
-};
-
-static struct resource dm365_vc_resources[] = {
- {
- .start = DAVINCI_DM365_VC_BASE,
- .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_DMA_VC_TX,
- .end = DAVINCI_DMA_VC_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DAVINCI_DMA_VC_RX,
- .end = DAVINCI_DMA_VC_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device dm365_vc_device = {
- .name = "davinci_voicecodec",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_vc_resources),
- .resource = dm365_vc_resources,
-};
-
-static struct resource dm365_rtc_resources[] = {
- {
- .start = DM365_RTC_BASE,
- .end = DM365_RTC_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_rtc_device = {
- .name = "rtc_davinci",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm365_rtc_resources),
- .resource = dm365_rtc_resources,
-};
-
-static struct map_desc dm365_io_desc[] = {
- {
- .virtual = IO_VIRT,
- .pfn = __phys_to_pfn(IO_PHYS),
- .length = IO_SIZE,
- .type = MT_DEVICE
- },
-};
-
-static struct resource dm365_ks_resources[] = {
- {
- /* registers */
- .start = DM365_KEYSCAN_BASE,
- .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm365_ks_device = {
- .name = "davinci_keyscan",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm365_ks_resources),
- .resource = dm365_ks_resources,
-};
-
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id dm365_ids[] = {
- {
- .variant = 0x0,
- .part_no = 0xb83e,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM365,
- .name = "dm365_rev1.1",
- },
- {
- .variant = 0x8,
- .part_no = 0xb83e,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM365,
- .name = "dm365_rev1.2",
- },
-};
-
-/*
- * Bottom half of timer0 is used for clockevent, top half is used for
- * clocksource.
- */
-static const struct davinci_timer_cfg dm365_timer_cfg = {
- .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
- },
-};
-
-#define DM365_UART1_BASE (IO_PHYS + 0x106000)
-
-static struct plat_serial8250_port dm365_serial0_platform_data[] = {
- {
- .mapbase = DAVINCI_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm365_serial1_platform_data[] = {
- {
- .mapbase = DM365_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device dm365_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = dm365_serial0_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = dm365_serial1_platform_data,
- }
- },
- {
- }
-};
-
-static const struct davinci_soc_info davinci_soc_info_dm365 = {
- .io_desc = dm365_io_desc,
- .io_desc_num = ARRAY_SIZE(dm365_io_desc),
- .jtag_id_reg = 0x01c40028,
- .ids = dm365_ids,
- .ids_num = ARRAY_SIZE(dm365_ids),
- .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
- .pinmux_pins = dm365_pins,
- .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
- .emac_pdata = &dm365_emac_pdata,
- .sram_dma = 0x00010000,
- .sram_len = SZ_32K,
-};
-
-void __init dm365_init_asp(void)
-{
- davinci_cfg_reg(DM365_MCBSP0_BDX);
- davinci_cfg_reg(DM365_MCBSP0_X);
- davinci_cfg_reg(DM365_MCBSP0_BFSX);
- davinci_cfg_reg(DM365_MCBSP0_BDR);
- davinci_cfg_reg(DM365_MCBSP0_R);
- davinci_cfg_reg(DM365_MCBSP0_BFSR);
- davinci_cfg_reg(DM365_EVT2_ASP_TX);
- davinci_cfg_reg(DM365_EVT3_ASP_RX);
- platform_device_register(&dm365_asp_device);
-}
-
-void __init dm365_init_vc(void)
-{
- davinci_cfg_reg(DM365_EVT2_VC_TX);
- davinci_cfg_reg(DM365_EVT3_VC_RX);
- platform_device_register(&dm365_vc_device);
-}
-
-void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
-{
- dm365_ks_device.dev.platform_data = pdata;
- platform_device_register(&dm365_ks_device);
-}
-
-void __init dm365_init_rtc(void)
-{
- davinci_cfg_reg(DM365_INT_PRTCSS);
- platform_device_register(&dm365_rtc_device);
-}
-
-void __init dm365_init(void)
-{
- davinci_common_init(&davinci_soc_info_dm365);
- davinci_map_sysmod();
-}
-
-void __init dm365_init_time(void)
-{
- void __iomem *pll1, *pll2, *psc;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
-
- pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
- dm365_pll1_init(NULL, pll1, NULL);
-
- pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
- dm365_pll2_init(NULL, pll2, NULL);
-
- psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
- dm365_psc_init(NULL, psc);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &dm365_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-void __init dm365_register_clocks(void)
-{
- /* all clocks are currently registered in dm365_init_time() */
-}
-
-static struct resource dm365_vpss_resources[] = {
- {
- /* VPSS ISP5 Base address */
- .name = "isp5",
- .start = 0x01c70000,
- .end = 0x01c70000 + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- /* VPSS CLK Base address */
- .name = "vpss",
- .start = 0x01c70200,
- .end = 0x01c70200 + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm365_vpss_device = {
- .name = "vpss",
- .id = -1,
- .dev.platform_data = "dm365_vpss",
- .num_resources = ARRAY_SIZE(dm365_vpss_resources),
- .resource = dm365_vpss_resources,
-};
-
-static struct resource vpfe_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
-static struct platform_device vpfe_capture_dev = {
- .name = CAPTURE_DRV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(vpfe_resources),
- .resource = vpfe_resources,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static void dm365_isif_setup_pinmux(void)
-{
- davinci_cfg_reg(DM365_VIN_CAM_WEN);
- davinci_cfg_reg(DM365_VIN_CAM_VD);
- davinci_cfg_reg(DM365_VIN_CAM_HD);
- davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
- davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
-}
-
-static struct resource isif_resource[] = {
- /* ISIF Base address */
- {
- .start = 0x01c71000,
- .end = 0x01c71000 + 0x1ff,
- .flags = IORESOURCE_MEM,
- },
- /* ISIF Linearization table 0 */
- {
- .start = 0x1C7C000,
- .end = 0x1C7C000 + 0x2ff,
- .flags = IORESOURCE_MEM,
- },
- /* ISIF Linearization table 1 */
- {
- .start = 0x1C7C400,
- .end = 0x1C7C400 + 0x2ff,
- .flags = IORESOURCE_MEM,
- },
-};
-static struct platform_device dm365_isif_dev = {
- .name = "isif",
- .id = -1,
- .num_resources = ARRAY_SIZE(isif_resource),
- .resource = isif_resource,
- .dev = {
- .dma_mask = &vpfe_capture_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = dm365_isif_setup_pinmux,
- },
-};
-
-static struct resource dm365_osd_resources[] = {
- {
- .start = DM365_OSD_BASE,
- .end = DM365_OSD_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device dm365_osd_dev = {
- .name = DM365_VPBE_OSD_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_osd_resources),
- .resource = dm365_osd_resources,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm365_venc_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM365_VENC_BASE,
- .end = DM365_VENC_BASE + 0x177,
- .flags = IORESOURCE_MEM,
- },
- /* vdaccfg registers io space */
- {
- .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
- .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource dm365_v4l2_disp_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
- /* venc registers io space */
- {
- .start = DM365_VENC_BASE,
- .end = DM365_VENC_BASE + 0x177,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
-{
- switch (if_type) {
- case MEDIA_BUS_FMT_SGRBG8_1X8:
- davinci_cfg_reg(DM365_VOUT_FIELD_G81);
- davinci_cfg_reg(DM365_VOUT_COUTL_EN);
- davinci_cfg_reg(DM365_VOUT_COUTH_EN);
- break;
- case MEDIA_BUS_FMT_YUYV10_1X20:
- if (field)
- davinci_cfg_reg(DM365_VOUT_FIELD);
- else
- davinci_cfg_reg(DM365_VOUT_FIELD_G81);
- davinci_cfg_reg(DM365_VOUT_COUTL_EN);
- davinci_cfg_reg(DM365_VOUT_COUTH_EN);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
- unsigned int pclock)
-{
- void __iomem *vpss_clkctl_reg;
- u32 val;
-
- vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
-
- switch (type) {
- case VPBE_ENC_STD:
- val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
- break;
- case VPBE_ENC_DV_TIMINGS:
- if (pclock <= 27000000) {
- val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
- } else {
- /* set sysclk4 to output 74.25 MHz from pll1 */
- val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
- VPSS_VENCCLKEN_ENABLE;
- }
- break;
- default:
- return -EINVAL;
- }
- writel(val, vpss_clkctl_reg);
-
- return 0;
-}
-
-static struct platform_device dm365_vpbe_display = {
- .name = "vpbe-v4l2",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
- .resource = dm365_v4l2_disp_resources,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct venc_platform_data dm365_venc_pdata = {
- .setup_pinmux = dm365_vpbe_setup_pinmux,
- .setup_clock = dm365_venc_setup_clock,
-};
-
-static struct platform_device dm365_venc_dev = {
- .name = DM365_VPBE_VENC_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm365_venc_resources),
- .resource = dm365_venc_resources,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = (void *)&dm365_venc_pdata,
- },
-};
-
-static struct platform_device dm365_vpbe_dev = {
- .name = "vpbe_controller",
- .id = -1,
- .dev = {
- .dma_mask = &dm365_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
- struct vpbe_config *vpbe_cfg)
-{
- if (vpfe_cfg || vpbe_cfg)
- platform_device_register(&dm365_vpss_device);
-
- if (vpfe_cfg) {
- vpfe_capture_dev.dev.platform_data = vpfe_cfg;
- platform_device_register(&dm365_isif_dev);
- platform_device_register(&vpfe_capture_dev);
- }
- if (vpbe_cfg) {
- dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
- platform_device_register(&dm365_osd_dev);
- platform_device_register(&dm365_venc_dev);
- platform_device_register(&dm365_vpbe_dev);
- platform_device_register(&dm365_vpbe_display);
- }
-
- return 0;
-}
-
-static const struct davinci_aintc_config dm365_aintc_config = {
- .reg = {
- .start = DAVINCI_ARM_INTC_BASE,
- .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = 64,
- .prios = dm365_default_priorities,
-};
-
-void __init dm365_init_irq(void)
-{
- davinci_aintc_init(&dm365_aintc_config);
-}
-
-static int __init dm365_init_devices(void)
-{
- struct platform_device *edma_pdev;
- int ret = 0;
-
- if (!cpu_is_davinci_dm365())
- return 0;
-
- davinci_cfg_reg(DM365_INT_EDMA_CC);
- edma_pdev = platform_device_register_full(&dm365_edma_device);
- if (IS_ERR(edma_pdev)) {
- pr_warn("%s: Failed to register eDMA\n", __func__);
- return PTR_ERR(edma_pdev);
- }
-
- platform_device_register(&dm365_mdio_device);
- platform_device_register(&dm365_emac_device);
-
- ret = davinci_init_wdt();
- if (ret)
- pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
-
- return ret;
-}
-postcore_initcall(dm365_init_devices);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
deleted file mode 100644
index 24988939ae46..000000000000
--- a/arch/arm/mach-davinci/dm644x.c
+++ /dev/null
@@ -1,767 +0,0 @@
-/*
- * TI DaVinci DM644x chip specific setup
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-aintc.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/mux.h>
-#include <mach/serial.h>
-
-#include <clocksource/timer-davinci.h>
-
-#include "asp.h"
-#include "davinci.h"
-#include "irqs.h"
-#include "mux.h"
-
-/*
- * Device specific clocks
- */
-#define DM644X_REF_FREQ 27000000
-
-#define DM644X_EMAC_BASE 0x01c80000
-#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
-#define DM644X_EMAC_CNTRL_OFFSET 0x0000
-#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
-#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
-#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
-
-static struct emac_platform_data dm644x_emac_pdata = {
- .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
- .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
- .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
- .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
- .version = EMAC_VERSION_1,
-};
-
-static struct resource dm644x_emac_resources[] = {
- {
- .start = DM644X_EMAC_BASE,
- .end = DM644X_EMAC_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
- .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm644x_emac_device = {
- .name = "davinci_emac",
- .id = 1,
- .dev = {
- .platform_data = &dm644x_emac_pdata,
- },
- .num_resources = ARRAY_SIZE(dm644x_emac_resources),
- .resource = dm644x_emac_resources,
-};
-
-static struct resource dm644x_mdio_resources[] = {
- {
- .start = DM644X_EMAC_MDIO_BASE,
- .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm644x_mdio_device = {
- .name = "davinci_mdio",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
- .resource = dm644x_mdio_resources,
-};
-
-/*
- * Device specific mux setup
- *
- * soc description mux mode mode mux dbg
- * reg offset mask mode
- */
-static const struct mux_config dm644x_pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
-MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
-MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
-
-MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
-
-MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
-MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
-MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
-MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
-MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
-MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
-
-MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
-
-MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
-
-MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
-
-MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
-MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
-
-MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
-
-MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
-
-MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
-
-MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
-MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
-MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
-
-MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
-
-MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
-
-MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
-MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
-MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
-MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
-
-MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
-
-MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
-MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
-#endif
-};
-
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
- [IRQ_VDINT0] = 2,
- [IRQ_VDINT1] = 6,
- [IRQ_VDINT2] = 6,
- [IRQ_HISTINT] = 6,
- [IRQ_H3AINT] = 6,
- [IRQ_PRVUINT] = 6,
- [IRQ_RSZINT] = 6,
- [7] = 7,
- [IRQ_VENCINT] = 6,
- [IRQ_ASQINT] = 6,
- [IRQ_IMXINT] = 6,
- [IRQ_VLCDINT] = 6,
- [IRQ_USBINT] = 4,
- [IRQ_EMACINT] = 4,
- [14] = 7,
- [15] = 7,
- [IRQ_CCINT0] = 5, /* dma */
- [IRQ_CCERRINT] = 5, /* dma */
- [IRQ_TCERRINT0] = 5, /* dma */
- [IRQ_TCERRINT] = 5, /* dma */
- [IRQ_PSCIN] = 7,
- [21] = 7,
- [IRQ_IDE] = 4,
- [23] = 7,
- [IRQ_MBXINT] = 7,
- [IRQ_MBRINT] = 7,
- [IRQ_MMCINT] = 7,
- [IRQ_SDIOINT] = 7,
- [28] = 7,
- [IRQ_DDRINT] = 7,
- [IRQ_AEMIFINT] = 7,
- [IRQ_VLQINT] = 4,
- [IRQ_TINT0_TINT12] = 2, /* clockevent */
- [IRQ_TINT0_TINT34] = 2, /* clocksource */
- [IRQ_TINT1_TINT12] = 7, /* DSP timer */
- [IRQ_TINT1_TINT34] = 7, /* system tick */
- [IRQ_PWMINT0] = 7,
- [IRQ_PWMINT1] = 7,
- [IRQ_PWMINT2] = 7,
- [IRQ_I2C] = 3,
- [IRQ_UARTINT0] = 3,
- [IRQ_UARTINT1] = 3,
- [IRQ_UARTINT2] = 3,
- [IRQ_SPINT0] = 3,
- [IRQ_SPINT1] = 3,
- [45] = 7,
- [IRQ_DSP2ARM0] = 4,
- [IRQ_DSP2ARM1] = 4,
- [IRQ_GPIO0] = 7,
- [IRQ_GPIO1] = 7,
- [IRQ_GPIO2] = 7,
- [IRQ_GPIO3] = 7,
- [IRQ_GPIO4] = 7,
- [IRQ_GPIO5] = 7,
- [IRQ_GPIO6] = 7,
- [IRQ_GPIO7] = 7,
- [IRQ_GPIOBNK0] = 7,
- [IRQ_GPIOBNK1] = 7,
- [IRQ_GPIOBNK2] = 7,
- [IRQ_GPIOBNK3] = 7,
- [IRQ_GPIOBNK4] = 7,
- [IRQ_COMMTX] = 7,
- [IRQ_COMMRX] = 7,
- [IRQ_EMUINT] = 7,
-};
-
-/*----------------------------------------------------------------------*/
-
-static s8 queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 3},
- {1, 7},
- {-1, -1},
-};
-
-static const struct dma_slave_map dm644x_edma_map[] = {
- { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
- { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
- { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
- { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
- { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
- { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
-};
-
-static struct edma_soc_info dm644x_edma_pdata = {
- .queue_priority_mapping = queue_priority_mapping,
- .default_queue = EVENTQ_1,
- .slave_map = dm644x_edma_map,
- .slavecnt = ARRAY_SIZE(dm644x_edma_map),
-};
-
-static struct resource edma_resources[] = {
- {
- .name = "edma3_cc",
- .start = 0x01c00000,
- .end = 0x01c00000 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = 0x01c10000,
- .end = 0x01c10000 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = 0x01c10400,
- .end = 0x01c10400 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
- /* not using TC*_ERR */
-};
-
-static const struct platform_device_info dm644x_edma_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = edma_resources,
- .num_res = ARRAY_SIZE(edma_resources),
- .data = &dm644x_edma_pdata,
- .size_data = sizeof(dm644x_edma_pdata),
-};
-
-/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
-static struct resource dm644x_asp_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_ASP0_BASE,
- .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_DMA_ASP0_TX,
- .end = DAVINCI_DMA_ASP0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = DAVINCI_DMA_ASP0_RX,
- .end = DAVINCI_DMA_ASP0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device dm644x_asp_device = {
- .name = "davinci-mcbsp",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm644x_asp_resources),
- .resource = dm644x_asp_resources,
-};
-
-#define DM644X_VPSS_BASE 0x01c73400
-
-static struct resource dm644x_vpss_resources[] = {
- {
- /* VPSS Base address */
- .name = "vpss",
- .start = DM644X_VPSS_BASE,
- .end = DM644X_VPSS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm644x_vpss_device = {
- .name = "vpss",
- .id = -1,
- .dev.platform_data = "dm644x_vpss",
- .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
- .resource = dm644x_vpss_resources,
-};
-
-static struct resource dm644x_vpfe_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
-static struct resource dm644x_ccdc_resource[] = {
- /* CCDC Base address */
- {
- .start = 0x01c70400,
- .end = 0x01c70400 + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm644x_ccdc_dev = {
- .name = "dm644x_ccdc",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
- .resource = dm644x_ccdc_resource,
- .dev = {
- .dma_mask = &dm644x_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct platform_device dm644x_vpfe_dev = {
- .name = CAPTURE_DRV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
- .resource = dm644x_vpfe_resources,
- .dev = {
- .dma_mask = &dm644x_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-#define DM644X_OSD_BASE 0x01c72600
-
-static struct resource dm644x_osd_resources[] = {
- {
- .start = DM644X_OSD_BASE,
- .end = DM644X_OSD_BASE + 0x1ff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm644x_osd_dev = {
- .name = DM644X_VPBE_OSD_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm644x_osd_resources),
- .resource = dm644x_osd_resources,
- .dev = {
- .dma_mask = &dm644x_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-#define DM644X_VENC_BASE 0x01c72400
-
-static struct resource dm644x_venc_resources[] = {
- {
- .start = DM644X_VENC_BASE,
- .end = DM644X_VENC_BASE + 0x17f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
-#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
-#define DM644X_VPSS_VENCLKEN BIT(3)
-#define DM644X_VPSS_DACCLKEN BIT(4)
-
-static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
- unsigned int pclock)
-{
- int ret = 0;
- u32 v = DM644X_VPSS_VENCLKEN;
-
- switch (type) {
- case VPBE_ENC_STD:
- v |= DM644X_VPSS_DACCLKEN;
- writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
- break;
- case VPBE_ENC_DV_TIMINGS:
- if (pclock <= 27000000) {
- v |= DM644X_VPSS_DACCLKEN;
- writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
- } else {
- /*
- * For HD, use external clock source since
- * HD requires higher clock rate
- */
- v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
- writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
- }
- break;
- default:
- ret = -EINVAL;
- }
-
- return ret;
-}
-
-static struct resource dm644x_v4l2_disp_resources[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm644x_vpbe_display = {
- .name = "vpbe-v4l2",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
- .resource = dm644x_v4l2_disp_resources,
- .dev = {
- .dma_mask = &dm644x_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct venc_platform_data dm644x_venc_pdata = {
- .setup_clock = dm644x_venc_setup_clock,
-};
-
-static struct platform_device dm644x_venc_dev = {
- .name = DM644X_VPBE_VENC_SUBDEV_NAME,
- .id = -1,
- .num_resources = ARRAY_SIZE(dm644x_venc_resources),
- .resource = dm644x_venc_resources,
- .dev = {
- .dma_mask = &dm644x_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dm644x_venc_pdata,
- },
-};
-
-static struct platform_device dm644x_vpbe_dev = {
- .name = "vpbe_controller",
- .id = -1,
- .dev = {
- .dma_mask = &dm644x_video_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dm644_gpio_resources[] = {
- { /* registers */
- .start = DAVINCI_GPIO_BASE,
- .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
- .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
- .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
- .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
- .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
- .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 71,
-};
-
-int __init dm644x_gpio_register(void)
-{
- return davinci_gpio_register(dm644_gpio_resources,
- ARRAY_SIZE(dm644_gpio_resources),
- &dm644_gpio_platform_data);
-}
-/*----------------------------------------------------------------------*/
-
-static struct map_desc dm644x_io_desc[] = {
- {
- .virtual = IO_VIRT,
- .pfn = __phys_to_pfn(IO_PHYS),
- .length = IO_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id dm644x_ids[] = {
- {
- .variant = 0x0,
- .part_no = 0xb700,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM6446,
- .name = "dm6446",
- },
- {
- .variant = 0x1,
- .part_no = 0xb700,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM6446,
- .name = "dm6446a",
- },
-};
-
-/*
- * Bottom half of timer0 is used for clockevent, top half is used for
- * clocksource.
- */
-static const struct davinci_timer_cfg dm644x_timer_cfg = {
- .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
- },
-};
-
-static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
- {
- .mapbase = DAVINCI_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
- {
- .mapbase = DAVINCI_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
- {
- .mapbase = DAVINCI_UART2_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device dm644x_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = dm644x_serial0_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = dm644x_serial1_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM2,
- .dev = {
- .platform_data = dm644x_serial2_platform_data,
- }
- },
- {
- }
-};
-
-static const struct davinci_soc_info davinci_soc_info_dm644x = {
- .io_desc = dm644x_io_desc,
- .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
- .jtag_id_reg = 0x01c40028,
- .ids = dm644x_ids,
- .ids_num = ARRAY_SIZE(dm644x_ids),
- .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
- .pinmux_pins = dm644x_pins,
- .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
- .emac_pdata = &dm644x_emac_pdata,
- .sram_dma = 0x00008000,
- .sram_len = SZ_16K,
-};
-
-void __init dm644x_init_asp(void)
-{
- davinci_cfg_reg(DM644X_MCBSP);
- platform_device_register(&dm644x_asp_device);
-}
-
-void __init dm644x_init(void)
-{
- davinci_common_init(&davinci_soc_info_dm644x);
- davinci_map_sysmod();
-}
-
-void __init dm644x_init_time(void)
-{
- void __iomem *pll1, *psc;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
-
- pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
- dm644x_pll1_init(NULL, pll1, NULL);
-
- psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
- dm644x_psc_init(NULL, psc);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &dm644x_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource dm644x_pll2_resources[] = {
- {
- .start = DAVINCI_PLL2_BASE,
- .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm644x_pll2_device = {
- .name = "dm644x-pll2",
- .id = -1,
- .resource = dm644x_pll2_resources,
- .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
-};
-
-void __init dm644x_register_clocks(void)
-{
- /* PLL1 and PSC are registered in dm644x_init_time() */
- platform_device_register(&dm644x_pll2_device);
-}
-
-int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
- struct vpbe_config *vpbe_cfg)
-{
- if (vpfe_cfg || vpbe_cfg)
- platform_device_register(&dm644x_vpss_device);
-
- if (vpfe_cfg) {
- dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
- platform_device_register(&dm644x_ccdc_dev);
- platform_device_register(&dm644x_vpfe_dev);
- }
-
- if (vpbe_cfg) {
- dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
- platform_device_register(&dm644x_osd_dev);
- platform_device_register(&dm644x_venc_dev);
- platform_device_register(&dm644x_vpbe_dev);
- platform_device_register(&dm644x_vpbe_display);
- }
-
- return 0;
-}
-
-static const struct davinci_aintc_config dm644x_aintc_config = {
- .reg = {
- .start = DAVINCI_ARM_INTC_BASE,
- .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = 64,
- .prios = dm644x_default_priorities,
-};
-
-void __init dm644x_init_irq(void)
-{
- davinci_aintc_init(&dm644x_aintc_config);
-}
-
-void __init dm644x_init_devices(void)
-{
- struct platform_device *edma_pdev;
- int ret;
-
- edma_pdev = platform_device_register_full(&dm644x_edma_device);
- if (IS_ERR(edma_pdev))
- pr_warn("%s: Failed to register eDMA\n", __func__);
-
- platform_device_register(&dm644x_mdio_device);
- platform_device_register(&dm644x_emac_device);
-
- ret = davinci_init_wdt();
- if (ret)
- pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
-
-}
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
deleted file mode 100644
index 4ffd028ed997..000000000000
--- a/arch/arm/mach-davinci/dm646x.c
+++ /dev/null
@@ -1,728 +0,0 @@
-/*
- * TI DaVinci DM646x chip specific setup
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clk/davinci.h>
-#include <linux/clkdev.h>
-#include <linux/dma-mapping.h>
-#include <linux/dmaengine.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irqchip/irq-davinci-aintc.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/gpio-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/mux.h>
-#include <mach/serial.h>
-
-#include <clocksource/timer-davinci.h>
-
-#include "asp.h"
-#include "davinci.h"
-#include "irqs.h"
-#include "mux.h"
-
-#define DAVINCI_VPIF_BASE (0x01C12000)
-
-#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
- BIT_MASK(0))
-#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
- BIT_MASK(8))
-
-#define DM646X_EMAC_BASE 0x01c80000
-#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
-#define DM646X_EMAC_CNTRL_OFFSET 0x0000
-#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
-#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
-#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
-
-static struct emac_platform_data dm646x_emac_pdata = {
- .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
- .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
- .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
- .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
- .version = EMAC_VERSION_2,
-};
-
-static struct resource dm646x_emac_resources[] = {
- {
- .start = DM646X_EMAC_BASE,
- .end = DM646X_EMAC_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm646x_emac_device = {
- .name = "davinci_emac",
- .id = 1,
- .dev = {
- .platform_data = &dm646x_emac_pdata,
- },
- .num_resources = ARRAY_SIZE(dm646x_emac_resources),
- .resource = dm646x_emac_resources,
-};
-
-static struct resource dm646x_mdio_resources[] = {
- {
- .start = DM646X_EMAC_MDIO_BASE,
- .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm646x_mdio_device = {
- .name = "davinci_mdio",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
- .resource = dm646x_mdio_resources,
-};
-
-/*
- * Device specific mux setup
- *
- * soc description mux mode mode mux dbg
- * reg offset mask mode
- */
-static const struct mux_config dm646x_pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
-
-MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
-
-MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
-
-MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
-
-MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
-
-MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
-
-MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
-
-MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
-
-MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
-
-MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
-
-MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
-
-MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
-
-MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
-
-MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
-#endif
-};
-
-static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
- [IRQ_DM646X_VP_VERTINT0] = 7,
- [IRQ_DM646X_VP_VERTINT1] = 7,
- [IRQ_DM646X_VP_VERTINT2] = 7,
- [IRQ_DM646X_VP_VERTINT3] = 7,
- [IRQ_DM646X_VP_ERRINT] = 7,
- [IRQ_DM646X_RESERVED_1] = 7,
- [IRQ_DM646X_RESERVED_2] = 7,
- [IRQ_DM646X_WDINT] = 7,
- [IRQ_DM646X_CRGENINT0] = 7,
- [IRQ_DM646X_CRGENINT1] = 7,
- [IRQ_DM646X_TSIFINT0] = 7,
- [IRQ_DM646X_TSIFINT1] = 7,
- [IRQ_DM646X_VDCEINT] = 7,
- [IRQ_DM646X_USBINT] = 7,
- [IRQ_DM646X_USBDMAINT] = 7,
- [IRQ_DM646X_PCIINT] = 7,
- [IRQ_CCINT0] = 7, /* dma */
- [IRQ_CCERRINT] = 7, /* dma */
- [IRQ_TCERRINT0] = 7, /* dma */
- [IRQ_TCERRINT] = 7, /* dma */
- [IRQ_DM646X_TCERRINT2] = 7,
- [IRQ_DM646X_TCERRINT3] = 7,
- [IRQ_DM646X_IDE] = 7,
- [IRQ_DM646X_HPIINT] = 7,
- [IRQ_DM646X_EMACRXTHINT] = 7,
- [IRQ_DM646X_EMACRXINT] = 7,
- [IRQ_DM646X_EMACTXINT] = 7,
- [IRQ_DM646X_EMACMISCINT] = 7,
- [IRQ_DM646X_MCASP0TXINT] = 7,
- [IRQ_DM646X_MCASP0RXINT] = 7,
- [IRQ_DM646X_RESERVED_3] = 7,
- [IRQ_DM646X_MCASP1TXINT] = 7,
- [IRQ_TINT0_TINT12] = 7, /* clockevent */
- [IRQ_TINT0_TINT34] = 7, /* clocksource */
- [IRQ_TINT1_TINT12] = 7, /* DSP timer */
- [IRQ_TINT1_TINT34] = 7, /* system tick */
- [IRQ_PWMINT0] = 7,
- [IRQ_PWMINT1] = 7,
- [IRQ_DM646X_VLQINT] = 7,
- [IRQ_I2C] = 7,
- [IRQ_UARTINT0] = 7,
- [IRQ_UARTINT1] = 7,
- [IRQ_DM646X_UARTINT2] = 7,
- [IRQ_DM646X_SPINT0] = 7,
- [IRQ_DM646X_SPINT1] = 7,
- [IRQ_DM646X_DSP2ARMINT] = 7,
- [IRQ_DM646X_RESERVED_4] = 7,
- [IRQ_DM646X_PSCINT] = 7,
- [IRQ_DM646X_GPIO0] = 7,
- [IRQ_DM646X_GPIO1] = 7,
- [IRQ_DM646X_GPIO2] = 7,
- [IRQ_DM646X_GPIO3] = 7,
- [IRQ_DM646X_GPIO4] = 7,
- [IRQ_DM646X_GPIO5] = 7,
- [IRQ_DM646X_GPIO6] = 7,
- [IRQ_DM646X_GPIO7] = 7,
- [IRQ_DM646X_GPIOBNK0] = 7,
- [IRQ_DM646X_GPIOBNK1] = 7,
- [IRQ_DM646X_GPIOBNK2] = 7,
- [IRQ_DM646X_DDRINT] = 7,
- [IRQ_DM646X_AEMIFINT] = 7,
- [IRQ_COMMTX] = 7,
- [IRQ_COMMRX] = 7,
- [IRQ_EMUINT] = 7,
-};
-
-/*----------------------------------------------------------------------*/
-
-/* Four Transfer Controllers on DM646x */
-static s8 dm646x_queue_priority_mapping[][2] = {
- /* {event queue no, Priority} */
- {0, 4},
- {1, 0},
- {2, 5},
- {3, 1},
- {-1, -1},
-};
-
-static const struct dma_slave_map dm646x_edma_map[] = {
- { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
- { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
- { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
- { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
- { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
-};
-
-static struct edma_soc_info dm646x_edma_pdata = {
- .queue_priority_mapping = dm646x_queue_priority_mapping,
- .default_queue = EVENTQ_1,
- .slave_map = dm646x_edma_map,
- .slavecnt = ARRAY_SIZE(dm646x_edma_map),
-};
-
-static struct resource edma_resources[] = {
- {
- .name = "edma3_cc",
- .start = 0x01c00000,
- .end = 0x01c00000 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc0",
- .start = 0x01c10000,
- .end = 0x01c10000 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc1",
- .start = 0x01c10400,
- .end = 0x01c10400 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc2",
- .start = 0x01c10800,
- .end = 0x01c10800 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_tc3",
- .start = 0x01c10c00,
- .end = 0x01c10c00 + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma3_ccint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma3_ccerrint",
- .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
- .flags = IORESOURCE_IRQ,
- },
- /* not using TC*_ERR */
-};
-
-static const struct platform_device_info dm646x_edma_device __initconst = {
- .name = "edma",
- .id = 0,
- .dma_mask = DMA_BIT_MASK(32),
- .res = edma_resources,
- .num_res = ARRAY_SIZE(edma_resources),
- .data = &dm646x_edma_pdata,
- .size_data = sizeof(dm646x_edma_pdata),
-};
-
-static struct resource dm646x_mcasp0_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DM646X_MCASP0_REG_BASE,
- .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "tx",
- .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
- .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "rx",
- .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
- .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "tx",
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "rx",
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* DIT mode only, rx is not supported */
-static struct resource dm646x_mcasp1_resources[] = {
- {
- .name = "mpu",
- .start = DAVINCI_DM646X_MCASP1_REG_BASE,
- .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "tx",
- .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
- .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "tx",
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dm646x_mcasp0_device = {
- .name = "davinci-mcasp",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
- .resource = dm646x_mcasp0_resources,
-};
-
-static struct platform_device dm646x_mcasp1_device = {
- .name = "davinci-mcasp",
- .id = 1,
- .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
- .resource = dm646x_mcasp1_resources,
-};
-
-static struct platform_device dm646x_dit_device = {
- .name = "spdif-dit",
- .id = -1,
-};
-
-static u64 vpif_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource vpif_resource[] = {
- {
- .start = DAVINCI_VPIF_BASE,
- .end = DAVINCI_VPIF_BASE + 0x03ff,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device vpif_dev = {
- .name = "vpif",
- .id = -1,
- .dev = {
- .dma_mask = &vpif_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = vpif_resource,
- .num_resources = ARRAY_SIZE(vpif_resource),
-};
-
-static struct resource vpif_display_resource[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device vpif_display_dev = {
- .name = "vpif_display",
- .id = -1,
- .dev = {
- .dma_mask = &vpif_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = vpif_display_resource,
- .num_resources = ARRAY_SIZE(vpif_display_resource),
-};
-
-static struct resource vpif_capture_resource[] = {
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device vpif_capture_dev = {
- .name = "vpif_capture",
- .id = -1,
- .dev = {
- .dma_mask = &vpif_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = vpif_capture_resource,
- .num_resources = ARRAY_SIZE(vpif_capture_resource),
-};
-
-static struct resource dm646x_gpio_resources[] = {
- { /* registers */
- .start = DAVINCI_GPIO_BASE,
- .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- { /* interrupt */
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
- .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
- .no_auto_base = true,
- .base = 0,
- .ngpio = 43,
-};
-
-int __init dm646x_gpio_register(void)
-{
- return davinci_gpio_register(dm646x_gpio_resources,
- ARRAY_SIZE(dm646x_gpio_resources),
- &dm646x_gpio_platform_data);
-}
-/*----------------------------------------------------------------------*/
-
-static struct map_desc dm646x_io_desc[] = {
- {
- .virtual = IO_VIRT,
- .pfn = __phys_to_pfn(IO_PHYS),
- .length = IO_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id dm646x_ids[] = {
- {
- .variant = 0x0,
- .part_no = 0xb770,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM6467,
- .name = "dm6467_rev1.x",
- },
- {
- .variant = 0x1,
- .part_no = 0xb770,
- .manufacturer = 0x017,
- .cpu_id = DAVINCI_CPU_ID_DM6467,
- .name = "dm6467_rev3.x",
- },
-};
-
-/*
- * Bottom half of timer0 is used for clockevent, top half is used for
- * clocksource.
- */
-static const struct davinci_timer_cfg dm646x_timer_cfg = {
- .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
- .irq = {
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
- DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
- },
-};
-
-static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
- {
- .mapbase = DAVINCI_UART0_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM32,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
- {
- .mapbase = DAVINCI_UART1_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM32,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
- {
- .mapbase = DAVINCI_UART2_BASE,
- .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_IOREMAP,
- .iotype = UPIO_MEM32,
- .regshift = 2,
- },
- {
- .flags = 0,
- }
-};
-
-struct platform_device dm646x_serial_device[] = {
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = dm646x_serial0_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = dm646x_serial1_platform_data,
- }
- },
- {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM2,
- .dev = {
- .platform_data = dm646x_serial2_platform_data,
- }
- },
- {
- }
-};
-
-static const struct davinci_soc_info davinci_soc_info_dm646x = {
- .io_desc = dm646x_io_desc,
- .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
- .jtag_id_reg = 0x01c40028,
- .ids = dm646x_ids,
- .ids_num = ARRAY_SIZE(dm646x_ids),
- .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
- .pinmux_pins = dm646x_pins,
- .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
- .emac_pdata = &dm646x_emac_pdata,
- .sram_dma = 0x10010000,
- .sram_len = SZ_32K,
-};
-
-void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
-{
- dm646x_mcasp0_device.dev.platform_data = pdata;
- platform_device_register(&dm646x_mcasp0_device);
-}
-
-void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
-{
- dm646x_mcasp1_device.dev.platform_data = pdata;
- platform_device_register(&dm646x_mcasp1_device);
- platform_device_register(&dm646x_dit_device);
-}
-
-void dm646x_setup_vpif(struct vpif_display_config *display_config,
- struct vpif_capture_config *capture_config)
-{
- unsigned int value;
-
- value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
- value &= ~VSCLKDIS_MASK;
- __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
-
- value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
- value &= ~VDD3P3V_VID_MASK;
- __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
-
- davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
- davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
- davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
- davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
-
- vpif_display_dev.dev.platform_data = display_config;
- vpif_capture_dev.dev.platform_data = capture_config;
- platform_device_register(&vpif_dev);
- platform_device_register(&vpif_display_dev);
- platform_device_register(&vpif_capture_dev);
-}
-
-int __init dm646x_init_edma(struct edma_rsv_info *rsv)
-{
- struct platform_device *edma_pdev;
-
- dm646x_edma_pdata.rsv = rsv;
-
- edma_pdev = platform_device_register_full(&dm646x_edma_device);
- return PTR_ERR_OR_ZERO(edma_pdev);
-}
-
-void __init dm646x_init(void)
-{
- davinci_common_init(&davinci_soc_info_dm646x);
- davinci_map_sysmod();
-}
-
-void __init dm646x_init_time(unsigned long ref_clk_rate,
- unsigned long aux_clkin_rate)
-{
- void __iomem *pll1, *psc;
- struct clk *clk;
- int rv;
-
- clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
- clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
-
- pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
- dm646x_pll1_init(NULL, pll1, NULL);
-
- psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
- dm646x_psc_init(NULL, psc);
-
- clk = clk_get(NULL, "timer0");
- if (WARN_ON(IS_ERR(clk))) {
- pr_err("Unable to get the timer clock\n");
- return;
- }
-
- rv = davinci_timer_register(clk, &dm646x_timer_cfg);
- WARN(rv, "Unable to register the timer: %d\n", rv);
-}
-
-static struct resource dm646x_pll2_resources[] = {
- {
- .start = DAVINCI_PLL2_BASE,
- .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dm646x_pll2_device = {
- .name = "dm646x-pll2",
- .id = -1,
- .resource = dm646x_pll2_resources,
- .num_resources = ARRAY_SIZE(dm646x_pll2_resources),
-};
-
-void __init dm646x_register_clocks(void)
-{
- /* PLL1 and PSC are registered in dm646x_init_time() */
- platform_device_register(&dm646x_pll2_device);
-}
-
-static const struct davinci_aintc_config dm646x_aintc_config = {
- .reg = {
- .start = DAVINCI_ARM_INTC_BASE,
- .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- .num_irqs = 64,
- .prios = dm646x_default_priorities,
-};
-
-void __init dm646x_init_irq(void)
-{
- davinci_aintc_init(&dm646x_aintc_config);
-}
-
-static int __init dm646x_init_devices(void)
-{
- int ret = 0;
-
- if (!cpu_is_davinci_dm646x())
- return 0;
-
- platform_device_register(&dm646x_mdio_device);
- platform_device_register(&dm646x_emac_device);
-
- ret = davinci_init_wdt();
- if (ret)
- pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
-
- return ret;
-}
-postcore_initcall(dm646x_init_devices);
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/hardware.h
index 16bb42291d39..7848b6a240b4 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/hardware.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Hardware definitions common to all DaVinci family processors
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) Deep Root Systems, LLC.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
deleted file mode 100644
index 1fc84e21664d..000000000000
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * DaVinci CPU type detection
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * Defines the cpu_is_*() macros for runtime detection of DaVinci
- * device type. In addition, if support for a given device is not
- * compiled in to the kernel, the macros return 0 so that
- * resulting code can be optimized out.
- *
- * 2009 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef _ASM_ARCH_CPU_H
-#define _ASM_ARCH_CPU_H
-
-#include <mach/common.h>
-
-struct davinci_id {
- u8 variant; /* JTAG ID bits 31:28 */
- u16 part_no; /* JTAG ID bits 27:12 */
- u16 manufacturer; /* JTAG ID bits 11:1 */
- u32 cpu_id;
- char *name;
-};
-
-/* Can use lower 16 bits of cpu id for a variant when required */
-#define DAVINCI_CPU_ID_DM6446 0x64460000
-#define DAVINCI_CPU_ID_DM6467 0x64670000
-#define DAVINCI_CPU_ID_DM355 0x03550000
-#define DAVINCI_CPU_ID_DM365 0x03650000
-#define DAVINCI_CPU_ID_DA830 0x08300000
-#define DAVINCI_CPU_ID_DA850 0x08500000
-
-#define IS_DAVINCI_CPU(type, id) \
-static inline int is_davinci_ ##type(void) \
-{ \
- return (davinci_soc_info.cpu_id == (id)); \
-}
-
-IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
-IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
-IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
-IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
-IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
-IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
-
-#ifdef CONFIG_ARCH_DAVINCI_DM644x
-#define cpu_is_davinci_dm644x() is_davinci_dm644x()
-#else
-#define cpu_is_davinci_dm644x() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM646x
-#define cpu_is_davinci_dm646x() is_davinci_dm646x()
-#else
-#define cpu_is_davinci_dm646x() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM355
-#define cpu_is_davinci_dm355() is_davinci_dm355()
-#else
-#define cpu_is_davinci_dm355() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DM365
-#define cpu_is_davinci_dm365() is_davinci_dm365()
-#else
-#define cpu_is_davinci_dm365() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DA830
-#define cpu_is_davinci_da830() is_davinci_da830()
-#else
-#define cpu_is_davinci_da830() 0
-#endif
-
-#ifdef CONFIG_ARCH_DAVINCI_DA850
-#define cpu_is_davinci_da850() is_davinci_da850()
-#else
-#define cpu_is_davinci_da850() 0
-#endif
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
deleted file mode 100644
index 1618b30661a9..000000000000
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Chip specific defines for DA8XX/OMAP L1XX SoC
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
-#define __ASM_ARCH_DAVINCI_DA8XX_H
-
-#include <video/da8xx-fb.h>
-
-#include <linux/platform_device.h>
-#include <linux/davinci_emac.h>
-#include <linux/spi/spi.h>
-#include <linux/platform_data/davinci_asp.h>
-#include <linux/reboot.h>
-#include <linux/regmap.h>
-#include <linux/videodev2.h>
-
-#include <mach/serial.h>
-#include <mach/pm.h>
-#include <linux/platform_data/edma.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_data/spi-davinci.h>
-#include <linux/platform_data/uio_pruss.h>
-
-#include <media/davinci/vpif_types.h>
-
-extern void __iomem *da8xx_syscfg0_base;
-extern void __iomem *da8xx_syscfg1_base;
-
-/*
- * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
- * (than the regular 300MHz variant), the board code should set this up
- * with the supported speed before calling da850_register_cpufreq().
- */
-extern unsigned int da850_max_speed;
-
-/*
- * The cp_intc interrupt controller for the da8xx isn't in the same
- * chunk of physical memory space as the other registers (like it is
- * on the davincis) so it needs to be mapped separately. It will be
- * mapped early on when the I/O space is mapped and we'll put it just
- * before the I/O space in the processor's virtual memory space.
- */
-#define DA8XX_CP_INTC_BASE 0xfffee000
-#define DA8XX_CP_INTC_SIZE SZ_8K
-#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
-
-#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
-#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
-#define DA8XX_JTAG_ID_REG 0x18
-#define DA8XX_HOST1CFG_REG 0x44
-#define DA8XX_CHIPSIG_REG 0x174
-#define DA8XX_CFGCHIP0_REG 0x17c
-#define DA8XX_CFGCHIP1_REG 0x180
-#define DA8XX_CFGCHIP2_REG 0x184
-#define DA8XX_CFGCHIP3_REG 0x188
-#define DA8XX_CFGCHIP4_REG 0x18c
-
-#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
-#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
-#define DA8XX_DEEPSLEEP_REG 0x8
-#define DA8XX_PWRDN_REG 0x18
-
-#define DA8XX_PSC0_BASE 0x01c10000
-#define DA8XX_PLL0_BASE 0x01c11000
-#define DA8XX_TIMER64P0_BASE 0x01c20000
-#define DA8XX_TIMER64P1_BASE 0x01c21000
-#define DA8XX_VPIF_BASE 0x01e17000
-#define DA8XX_GPIO_BASE 0x01e26000
-#define DA8XX_PSC1_BASE 0x01e27000
-
-#define DA8XX_DSP_L2_RAM_BASE 0x11800000
-#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000)
-#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000)
-
-#define DA8XX_AEMIF_CS2_BASE 0x60000000
-#define DA8XX_AEMIF_CS3_BASE 0x62000000
-#define DA8XX_AEMIF_CTL_BASE 0x68000000
-#define DA8XX_SHARED_RAM_BASE 0x80000000
-#define DA8XX_ARM_RAM_BASE 0xffff0000
-
-void da830_init(void);
-void da830_init_irq(void);
-void da830_init_time(void);
-void da830_register_clocks(void);
-
-void da850_init(void);
-void da850_init_irq(void);
-void da850_init_time(void);
-void da850_register_clocks(void);
-
-int da830_register_edma(struct edma_rsv_info *rsv);
-int da850_register_edma(struct edma_rsv_info *rsv[2]);
-int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
-int da8xx_register_spi_bus(int instance, unsigned num_chipselect);
-int da8xx_register_watchdog(void);
-int da8xx_register_usb_phy(void);
-int da8xx_register_usb20(unsigned mA, unsigned potpgt);
-int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
-int da8xx_register_usb_phy_clocks(void);
-int da850_register_sata_refclk(int rate);
-int da8xx_register_emac(void);
-int da8xx_register_uio_pruss(void);
-int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
-int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
-int da850_register_mmcsd1(struct davinci_mmc_config *config);
-void da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
-int da8xx_register_rtc(void);
-int da8xx_register_gpio(void *pdata);
-int da850_register_cpufreq(char *async_clk);
-int da8xx_register_cpuidle(void);
-void __iomem *da8xx_get_mem_ctlr(void);
-int da850_register_sata(unsigned long refclkpn);
-int da850_register_vpif(void);
-int da850_register_vpif_display
- (struct vpif_display_config *display_config);
-int da850_register_vpif_capture
- (struct vpif_capture_config *capture_config);
-void da8xx_rproc_reserve_cma(void);
-int da8xx_register_rproc(void);
-int da850_register_gpio(void);
-int da830_register_gpio(void);
-struct regmap *da8xx_get_cfgchip(void);
-
-extern struct platform_device da8xx_serial_device[];
-extern struct emac_platform_data da8xx_emac_pdata;
-extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
-extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
-
-
-extern const short da830_emif25_pins[];
-extern const short da830_spi0_pins[];
-extern const short da830_spi1_pins[];
-extern const short da830_mmc_sd_pins[];
-extern const short da830_uart0_pins[];
-extern const short da830_uart1_pins[];
-extern const short da830_uart2_pins[];
-extern const short da830_usb20_pins[];
-extern const short da830_usb11_pins[];
-extern const short da830_uhpi_pins[];
-extern const short da830_cpgmac_pins[];
-extern const short da830_emif3c_pins[];
-extern const short da830_mcasp0_pins[];
-extern const short da830_mcasp1_pins[];
-extern const short da830_mcasp2_pins[];
-extern const short da830_i2c0_pins[];
-extern const short da830_i2c1_pins[];
-extern const short da830_lcdcntl_pins[];
-extern const short da830_pwm_pins[];
-extern const short da830_ecap0_pins[];
-extern const short da830_ecap1_pins[];
-extern const short da830_ecap2_pins[];
-extern const short da830_eqep0_pins[];
-extern const short da830_eqep1_pins[];
-extern const short da850_vpif_capture_pins[];
-extern const short da850_vpif_display_pins[];
-
-extern const short da850_i2c0_pins[];
-extern const short da850_i2c1_pins[];
-extern const short da850_lcdcntl_pins[];
-
-#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
deleted file mode 100644
index 631655e68ae0..000000000000
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ /dev/null
@@ -1,990 +0,0 @@
-/*
- * Table of the DAVINCI register configurations for the PINMUX combinations
- *
- * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
- *
- * Based on linux/include/asm-arm/arch-omap/mux.h:
- * Copyright (C) 2003 - 2005 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Copyright (C) 2008 Texas Instruments.
- */
-
-#ifndef __INC_MACH_MUX_H
-#define __INC_MACH_MUX_H
-
-struct mux_config {
- const char *name;
- const char *mux_reg_name;
- const unsigned char mux_reg;
- const unsigned char mask_offset;
- const unsigned char mask;
- const unsigned char mode;
- bool debug;
-};
-
-enum davinci_dm644x_index {
- /* ATA and HDDIR functions */
- DM644X_HDIREN,
- DM644X_ATAEN,
- DM644X_ATAEN_DISABLE,
-
- /* HPI functions */
- DM644X_HPIEN_DISABLE,
-
- /* AEAW functions */
- DM644X_AEAW,
- DM644X_AEAW0,
- DM644X_AEAW1,
- DM644X_AEAW2,
- DM644X_AEAW3,
- DM644X_AEAW4,
-
- /* Memory Stick */
- DM644X_MSTK,
-
- /* I2C */
- DM644X_I2C,
-
- /* ASP function */
- DM644X_MCBSP,
-
- /* UART1 */
- DM644X_UART1,
-
- /* UART2 */
- DM644X_UART2,
-
- /* PWM0 */
- DM644X_PWM0,
-
- /* PWM1 */
- DM644X_PWM1,
-
- /* PWM2 */
- DM644X_PWM2,
-
- /* VLYNQ function */
- DM644X_VLYNQEN,
- DM644X_VLSCREN,
- DM644X_VLYNQWD,
-
- /* EMAC and MDIO function */
- DM644X_EMACEN,
-
- /* GPIO3V[0:16] pins */
- DM644X_GPIO3V,
-
- /* GPIO pins */
- DM644X_GPIO0,
- DM644X_GPIO3,
- DM644X_GPIO43_44,
- DM644X_GPIO46_47,
-
- /* VPBE */
- DM644X_RGB666,
-
- /* LCD */
- DM644X_LOEEN,
- DM644X_LFLDEN,
-};
-
-enum davinci_dm646x_index {
- /* ATA function */
- DM646X_ATAEN,
-
- /* AUDIO Clock */
- DM646X_AUDCK1,
- DM646X_AUDCK0,
-
- /* CRGEN Control */
- DM646X_CRGMUX,
-
- /* VPIF Control */
- DM646X_STSOMUX_DISABLE,
- DM646X_STSIMUX_DISABLE,
- DM646X_PTSOMUX_DISABLE,
- DM646X_PTSIMUX_DISABLE,
-
- /* TSIF Control */
- DM646X_STSOMUX,
- DM646X_STSIMUX,
- DM646X_PTSOMUX_PARALLEL,
- DM646X_PTSIMUX_PARALLEL,
- DM646X_PTSOMUX_SERIAL,
- DM646X_PTSIMUX_SERIAL,
-};
-
-enum davinci_dm355_index {
- /* MMC/SD 0 */
- DM355_MMCSD0,
-
- /* MMC/SD 1 */
- DM355_SD1_CLK,
- DM355_SD1_CMD,
- DM355_SD1_DATA3,
- DM355_SD1_DATA2,
- DM355_SD1_DATA1,
- DM355_SD1_DATA0,
-
- /* I2C */
- DM355_I2C_SDA,
- DM355_I2C_SCL,
-
- /* ASP0 function */
- DM355_MCBSP0_BDX,
- DM355_MCBSP0_X,
- DM355_MCBSP0_BFSX,
- DM355_MCBSP0_BDR,
- DM355_MCBSP0_R,
- DM355_MCBSP0_BFSR,
-
- /* SPI0 */
- DM355_SPI0_SDI,
- DM355_SPI0_SDENA0,
- DM355_SPI0_SDENA1,
-
- /* IRQ muxing */
- DM355_INT_EDMA_CC,
- DM355_INT_EDMA_TC0_ERR,
- DM355_INT_EDMA_TC1_ERR,
-
- /* EDMA event muxing */
- DM355_EVT8_ASP1_TX,
- DM355_EVT9_ASP1_RX,
- DM355_EVT26_MMC0_RX,
-
- /* Video Out */
- DM355_VOUT_FIELD,
- DM355_VOUT_FIELD_G70,
- DM355_VOUT_HVSYNC,
- DM355_VOUT_COUTL_EN,
- DM355_VOUT_COUTH_EN,
-
- /* Video In Pin Mux */
- DM355_VIN_PCLK,
- DM355_VIN_CAM_WEN,
- DM355_VIN_CAM_VD,
- DM355_VIN_CAM_HD,
- DM355_VIN_YIN_EN,
- DM355_VIN_CINL_EN,
- DM355_VIN_CINH_EN,
-};
-
-enum davinci_dm365_index {
- /* MMC/SD 0 */
- DM365_MMCSD0,
-
- /* MMC/SD 1 */
- DM365_SD1_CLK,
- DM365_SD1_CMD,
- DM365_SD1_DATA3,
- DM365_SD1_DATA2,
- DM365_SD1_DATA1,
- DM365_SD1_DATA0,
-
- /* I2C */
- DM365_I2C_SDA,
- DM365_I2C_SCL,
-
- /* AEMIF */
- DM365_AEMIF_AR_A14,
- DM365_AEMIF_AR_BA0,
- DM365_AEMIF_A3,
- DM365_AEMIF_A7,
- DM365_AEMIF_D15_8,
- DM365_AEMIF_CE0,
- DM365_AEMIF_CE1,
- DM365_AEMIF_WE_OE,
-
- /* ASP0 function */
- DM365_MCBSP0_BDX,
- DM365_MCBSP0_X,
- DM365_MCBSP0_BFSX,
- DM365_MCBSP0_BDR,
- DM365_MCBSP0_R,
- DM365_MCBSP0_BFSR,
-
- /* SPI0 */
- DM365_SPI0_SCLK,
- DM365_SPI0_SDI,
- DM365_SPI0_SDO,
- DM365_SPI0_SDENA0,
- DM365_SPI0_SDENA1,
-
- /* UART */
- DM365_UART0_RXD,
- DM365_UART0_TXD,
- DM365_UART1_RXD,
- DM365_UART1_TXD,
- DM365_UART1_RTS,
- DM365_UART1_CTS,
-
- /* EMAC */
- DM365_EMAC_TX_EN,
- DM365_EMAC_TX_CLK,
- DM365_EMAC_COL,
- DM365_EMAC_TXD3,
- DM365_EMAC_TXD2,
- DM365_EMAC_TXD1,
- DM365_EMAC_TXD0,
- DM365_EMAC_RXD3,
- DM365_EMAC_RXD2,
- DM365_EMAC_RXD1,
- DM365_EMAC_RXD0,
- DM365_EMAC_RX_CLK,
- DM365_EMAC_RX_DV,
- DM365_EMAC_RX_ER,
- DM365_EMAC_CRS,
- DM365_EMAC_MDIO,
- DM365_EMAC_MDCLK,
-
- /* Key Scan */
- DM365_KEYSCAN,
-
- /* PWM */
- DM365_PWM0,
- DM365_PWM0_G23,
- DM365_PWM1,
- DM365_PWM1_G25,
- DM365_PWM2_G87,
- DM365_PWM2_G88,
- DM365_PWM2_G89,
- DM365_PWM2_G90,
- DM365_PWM3_G80,
- DM365_PWM3_G81,
- DM365_PWM3_G85,
- DM365_PWM3_G86,
-
- /* SPI1 */
- DM365_SPI1_SCLK,
- DM365_SPI1_SDO,
- DM365_SPI1_SDI,
- DM365_SPI1_SDENA0,
- DM365_SPI1_SDENA1,
-
- /* SPI2 */
- DM365_SPI2_SCLK,
- DM365_SPI2_SDO,
- DM365_SPI2_SDI,
- DM365_SPI2_SDENA0,
- DM365_SPI2_SDENA1,
-
- /* SPI3 */
- DM365_SPI3_SCLK,
- DM365_SPI3_SDO,
- DM365_SPI3_SDI,
- DM365_SPI3_SDENA0,
- DM365_SPI3_SDENA1,
-
- /* SPI4 */
- DM365_SPI4_SCLK,
- DM365_SPI4_SDO,
- DM365_SPI4_SDI,
- DM365_SPI4_SDENA0,
- DM365_SPI4_SDENA1,
-
- /* Clock */
- DM365_CLKOUT0,
- DM365_CLKOUT1,
- DM365_CLKOUT2,
-
- /* GPIO */
- DM365_GPIO20,
- DM365_GPIO30,
- DM365_GPIO31,
- DM365_GPIO32,
- DM365_GPIO33,
- DM365_GPIO40,
- DM365_GPIO64_57,
-
- /* Video */
- DM365_VOUT_FIELD,
- DM365_VOUT_FIELD_G81,
- DM365_VOUT_HVSYNC,
- DM365_VOUT_COUTL_EN,
- DM365_VOUT_COUTH_EN,
- DM365_VIN_CAM_WEN,
- DM365_VIN_CAM_VD,
- DM365_VIN_CAM_HD,
- DM365_VIN_YIN4_7_EN,
- DM365_VIN_YIN0_3_EN,
-
- /* IRQ muxing */
- DM365_INT_EDMA_CC,
- DM365_INT_EDMA_TC0_ERR,
- DM365_INT_EDMA_TC1_ERR,
- DM365_INT_EDMA_TC2_ERR,
- DM365_INT_EDMA_TC3_ERR,
- DM365_INT_PRTCSS,
- DM365_INT_EMAC_RXTHRESH,
- DM365_INT_EMAC_RXPULSE,
- DM365_INT_EMAC_TXPULSE,
- DM365_INT_EMAC_MISCPULSE,
- DM365_INT_IMX0_ENABLE,
- DM365_INT_IMX0_DISABLE,
- DM365_INT_HDVICP_ENABLE,
- DM365_INT_HDVICP_DISABLE,
- DM365_INT_IMX1_ENABLE,
- DM365_INT_IMX1_DISABLE,
- DM365_INT_NSF_ENABLE,
- DM365_INT_NSF_DISABLE,
-
- /* EDMA event muxing */
- DM365_EVT2_ASP_TX,
- DM365_EVT3_ASP_RX,
- DM365_EVT2_VC_TX,
- DM365_EVT3_VC_RX,
- DM365_EVT26_MMC0_RX,
-};
-
-enum da830_index {
- DA830_GPIO7_14,
- DA830_RTCK,
- DA830_GPIO7_15,
- DA830_EMU_0,
- DA830_EMB_SDCKE,
- DA830_EMB_CLK_GLUE,
- DA830_EMB_CLK,
- DA830_NEMB_CS_0,
- DA830_NEMB_CAS,
- DA830_NEMB_RAS,
- DA830_NEMB_WE,
- DA830_EMB_BA_1,
- DA830_EMB_BA_0,
- DA830_EMB_A_0,
- DA830_EMB_A_1,
- DA830_EMB_A_2,
- DA830_EMB_A_3,
- DA830_EMB_A_4,
- DA830_EMB_A_5,
- DA830_GPIO7_0,
- DA830_GPIO7_1,
- DA830_GPIO7_2,
- DA830_GPIO7_3,
- DA830_GPIO7_4,
- DA830_GPIO7_5,
- DA830_GPIO7_6,
- DA830_GPIO7_7,
- DA830_EMB_A_6,
- DA830_EMB_A_7,
- DA830_EMB_A_8,
- DA830_EMB_A_9,
- DA830_EMB_A_10,
- DA830_EMB_A_11,
- DA830_EMB_A_12,
- DA830_EMB_D_31,
- DA830_GPIO7_8,
- DA830_GPIO7_9,
- DA830_GPIO7_10,
- DA830_GPIO7_11,
- DA830_GPIO7_12,
- DA830_GPIO7_13,
- DA830_GPIO3_13,
- DA830_EMB_D_30,
- DA830_EMB_D_29,
- DA830_EMB_D_28,
- DA830_EMB_D_27,
- DA830_EMB_D_26,
- DA830_EMB_D_25,
- DA830_EMB_D_24,
- DA830_EMB_D_23,
- DA830_EMB_D_22,
- DA830_EMB_D_21,
- DA830_EMB_D_20,
- DA830_EMB_D_19,
- DA830_EMB_D_18,
- DA830_EMB_D_17,
- DA830_EMB_D_16,
- DA830_NEMB_WE_DQM_3,
- DA830_NEMB_WE_DQM_2,
- DA830_EMB_D_0,
- DA830_EMB_D_1,
- DA830_EMB_D_2,
- DA830_EMB_D_3,
- DA830_EMB_D_4,
- DA830_EMB_D_5,
- DA830_EMB_D_6,
- DA830_GPIO6_0,
- DA830_GPIO6_1,
- DA830_GPIO6_2,
- DA830_GPIO6_3,
- DA830_GPIO6_4,
- DA830_GPIO6_5,
- DA830_GPIO6_6,
- DA830_EMB_D_7,
- DA830_EMB_D_8,
- DA830_EMB_D_9,
- DA830_EMB_D_10,
- DA830_EMB_D_11,
- DA830_EMB_D_12,
- DA830_EMB_D_13,
- DA830_EMB_D_14,
- DA830_GPIO6_7,
- DA830_GPIO6_8,
- DA830_GPIO6_9,
- DA830_GPIO6_10,
- DA830_GPIO6_11,
- DA830_GPIO6_12,
- DA830_GPIO6_13,
- DA830_GPIO6_14,
- DA830_EMB_D_15,
- DA830_NEMB_WE_DQM_1,
- DA830_NEMB_WE_DQM_0,
- DA830_SPI0_SOMI_0,
- DA830_SPI0_SIMO_0,
- DA830_SPI0_CLK,
- DA830_NSPI0_ENA,
- DA830_NSPI0_SCS_0,
- DA830_EQEP0I,
- DA830_EQEP0S,
- DA830_EQEP1I,
- DA830_NUART0_CTS,
- DA830_NUART0_RTS,
- DA830_EQEP0A,
- DA830_EQEP0B,
- DA830_GPIO6_15,
- DA830_GPIO5_14,
- DA830_GPIO5_15,
- DA830_GPIO5_0,
- DA830_GPIO5_1,
- DA830_GPIO5_2,
- DA830_GPIO5_3,
- DA830_GPIO5_4,
- DA830_SPI1_SOMI_0,
- DA830_SPI1_SIMO_0,
- DA830_SPI1_CLK,
- DA830_UART0_RXD,
- DA830_UART0_TXD,
- DA830_AXR1_10,
- DA830_AXR1_11,
- DA830_NSPI1_ENA,
- DA830_I2C1_SCL,
- DA830_I2C1_SDA,
- DA830_EQEP1S,
- DA830_I2C0_SDA,
- DA830_I2C0_SCL,
- DA830_UART2_RXD,
- DA830_TM64P0_IN12,
- DA830_TM64P0_OUT12,
- DA830_GPIO5_5,
- DA830_GPIO5_6,
- DA830_GPIO5_7,
- DA830_GPIO5_8,
- DA830_GPIO5_9,
- DA830_GPIO5_10,
- DA830_GPIO5_11,
- DA830_GPIO5_12,
- DA830_NSPI1_SCS_0,
- DA830_USB0_DRVVBUS,
- DA830_AHCLKX0,
- DA830_ACLKX0,
- DA830_AFSX0,
- DA830_AHCLKR0,
- DA830_ACLKR0,
- DA830_AFSR0,
- DA830_UART2_TXD,
- DA830_AHCLKX2,
- DA830_ECAP0_APWM0,
- DA830_RMII_MHZ_50_CLK,
- DA830_ECAP1_APWM1,
- DA830_USB_REFCLKIN,
- DA830_GPIO5_13,
- DA830_GPIO4_15,
- DA830_GPIO2_11,
- DA830_GPIO2_12,
- DA830_GPIO2_13,
- DA830_GPIO2_14,
- DA830_GPIO2_15,
- DA830_GPIO3_12,
- DA830_AMUTE0,
- DA830_AXR0_0,
- DA830_AXR0_1,
- DA830_AXR0_2,
- DA830_AXR0_3,
- DA830_AXR0_4,
- DA830_AXR0_5,
- DA830_AXR0_6,
- DA830_RMII_TXD_0,
- DA830_RMII_TXD_1,
- DA830_RMII_TXEN,
- DA830_RMII_CRS_DV,
- DA830_RMII_RXD_0,
- DA830_RMII_RXD_1,
- DA830_RMII_RXER,
- DA830_AFSR2,
- DA830_ACLKX2,
- DA830_AXR2_3,
- DA830_AXR2_2,
- DA830_AXR2_1,
- DA830_AFSX2,
- DA830_ACLKR2,
- DA830_NRESETOUT,
- DA830_GPIO3_0,
- DA830_GPIO3_1,
- DA830_GPIO3_2,
- DA830_GPIO3_3,
- DA830_GPIO3_4,
- DA830_GPIO3_5,
- DA830_GPIO3_6,
- DA830_AXR0_7,
- DA830_AXR0_8,
- DA830_UART1_RXD,
- DA830_UART1_TXD,
- DA830_AXR0_11,
- DA830_AHCLKX1,
- DA830_ACLKX1,
- DA830_AFSX1,
- DA830_MDIO_CLK,
- DA830_MDIO_D,
- DA830_AXR0_9,
- DA830_AXR0_10,
- DA830_EPWM0B,
- DA830_EPWM0A,
- DA830_EPWMSYNCI,
- DA830_AXR2_0,
- DA830_EPWMSYNC0,
- DA830_GPIO3_7,
- DA830_GPIO3_8,
- DA830_GPIO3_9,
- DA830_GPIO3_10,
- DA830_GPIO3_11,
- DA830_GPIO3_14,
- DA830_GPIO3_15,
- DA830_GPIO4_10,
- DA830_AHCLKR1,
- DA830_ACLKR1,
- DA830_AFSR1,
- DA830_AMUTE1,
- DA830_AXR1_0,
- DA830_AXR1_1,
- DA830_AXR1_2,
- DA830_AXR1_3,
- DA830_ECAP2_APWM2,
- DA830_EHRPWMGLUETZ,
- DA830_EQEP1A,
- DA830_GPIO4_11,
- DA830_GPIO4_12,
- DA830_GPIO4_13,
- DA830_GPIO4_14,
- DA830_GPIO4_0,
- DA830_GPIO4_1,
- DA830_GPIO4_2,
- DA830_GPIO4_3,
- DA830_AXR1_4,
- DA830_AXR1_5,
- DA830_AXR1_6,
- DA830_AXR1_7,
- DA830_AXR1_8,
- DA830_AXR1_9,
- DA830_EMA_D_0,
- DA830_EMA_D_1,
- DA830_EQEP1B,
- DA830_EPWM2B,
- DA830_EPWM2A,
- DA830_EPWM1B,
- DA830_EPWM1A,
- DA830_MMCSD_DAT_0,
- DA830_MMCSD_DAT_1,
- DA830_UHPI_HD_0,
- DA830_UHPI_HD_1,
- DA830_GPIO4_4,
- DA830_GPIO4_5,
- DA830_GPIO4_6,
- DA830_GPIO4_7,
- DA830_GPIO4_8,
- DA830_GPIO4_9,
- DA830_GPIO0_0,
- DA830_GPIO0_1,
- DA830_EMA_D_2,
- DA830_EMA_D_3,
- DA830_EMA_D_4,
- DA830_EMA_D_5,
- DA830_EMA_D_6,
- DA830_EMA_D_7,
- DA830_EMA_D_8,
- DA830_EMA_D_9,
- DA830_MMCSD_DAT_2,
- DA830_MMCSD_DAT_3,
- DA830_MMCSD_DAT_4,
- DA830_MMCSD_DAT_5,
- DA830_MMCSD_DAT_6,
- DA830_MMCSD_DAT_7,
- DA830_UHPI_HD_8,
- DA830_UHPI_HD_9,
- DA830_UHPI_HD_2,
- DA830_UHPI_HD_3,
- DA830_UHPI_HD_4,
- DA830_UHPI_HD_5,
- DA830_UHPI_HD_6,
- DA830_UHPI_HD_7,
- DA830_LCD_D_8,
- DA830_LCD_D_9,
- DA830_GPIO0_2,
- DA830_GPIO0_3,
- DA830_GPIO0_4,
- DA830_GPIO0_5,
- DA830_GPIO0_6,
- DA830_GPIO0_7,
- DA830_GPIO0_8,
- DA830_GPIO0_9,
- DA830_EMA_D_10,
- DA830_EMA_D_11,
- DA830_EMA_D_12,
- DA830_EMA_D_13,
- DA830_EMA_D_14,
- DA830_EMA_D_15,
- DA830_EMA_A_0,
- DA830_EMA_A_1,
- DA830_UHPI_HD_10,
- DA830_UHPI_HD_11,
- DA830_UHPI_HD_12,
- DA830_UHPI_HD_13,
- DA830_UHPI_HD_14,
- DA830_UHPI_HD_15,
- DA830_LCD_D_7,
- DA830_MMCSD_CLK,
- DA830_LCD_D_10,
- DA830_LCD_D_11,
- DA830_LCD_D_12,
- DA830_LCD_D_13,
- DA830_LCD_D_14,
- DA830_LCD_D_15,
- DA830_UHPI_HCNTL0,
- DA830_GPIO0_10,
- DA830_GPIO0_11,
- DA830_GPIO0_12,
- DA830_GPIO0_13,
- DA830_GPIO0_14,
- DA830_GPIO0_15,
- DA830_GPIO1_0,
- DA830_GPIO1_1,
- DA830_EMA_A_2,
- DA830_EMA_A_3,
- DA830_EMA_A_4,
- DA830_EMA_A_5,
- DA830_EMA_A_6,
- DA830_EMA_A_7,
- DA830_EMA_A_8,
- DA830_EMA_A_9,
- DA830_MMCSD_CMD,
- DA830_LCD_D_6,
- DA830_LCD_D_3,
- DA830_LCD_D_2,
- DA830_LCD_D_1,
- DA830_LCD_D_0,
- DA830_LCD_PCLK,
- DA830_LCD_HSYNC,
- DA830_UHPI_HCNTL1,
- DA830_GPIO1_2,
- DA830_GPIO1_3,
- DA830_GPIO1_4,
- DA830_GPIO1_5,
- DA830_GPIO1_6,
- DA830_GPIO1_7,
- DA830_GPIO1_8,
- DA830_GPIO1_9,
- DA830_EMA_A_10,
- DA830_EMA_A_11,
- DA830_EMA_A_12,
- DA830_EMA_BA_1,
- DA830_EMA_BA_0,
- DA830_EMA_CLK,
- DA830_EMA_SDCKE,
- DA830_NEMA_CAS,
- DA830_LCD_VSYNC,
- DA830_NLCD_AC_ENB_CS,
- DA830_LCD_MCLK,
- DA830_LCD_D_5,
- DA830_LCD_D_4,
- DA830_OBSCLK,
- DA830_NEMA_CS_4,
- DA830_UHPI_HHWIL,
- DA830_AHCLKR2,
- DA830_GPIO1_10,
- DA830_GPIO1_11,
- DA830_GPIO1_12,
- DA830_GPIO1_13,
- DA830_GPIO1_14,
- DA830_GPIO1_15,
- DA830_GPIO2_0,
- DA830_GPIO2_1,
- DA830_NEMA_RAS,
- DA830_NEMA_WE,
- DA830_NEMA_CS_0,
- DA830_NEMA_CS_2,
- DA830_NEMA_CS_3,
- DA830_NEMA_OE,
- DA830_NEMA_WE_DQM_1,
- DA830_NEMA_WE_DQM_0,
- DA830_NEMA_CS_5,
- DA830_UHPI_HRNW,
- DA830_NUHPI_HAS,
- DA830_NUHPI_HCS,
- DA830_NUHPI_HDS1,
- DA830_NUHPI_HDS2,
- DA830_NUHPI_HINT,
- DA830_AXR0_12,
- DA830_AMUTE2,
- DA830_AXR0_13,
- DA830_AXR0_14,
- DA830_AXR0_15,
- DA830_GPIO2_2,
- DA830_GPIO2_3,
- DA830_GPIO2_4,
- DA830_GPIO2_5,
- DA830_GPIO2_6,
- DA830_GPIO2_7,
- DA830_GPIO2_8,
- DA830_GPIO2_9,
- DA830_EMA_WAIT_0,
- DA830_NUHPI_HRDY,
- DA830_GPIO2_10,
-};
-
-enum davinci_da850_index {
- /* UART0 function */
- DA850_NUART0_CTS,
- DA850_NUART0_RTS,
- DA850_UART0_RXD,
- DA850_UART0_TXD,
-
- /* UART1 function */
- DA850_NUART1_CTS,
- DA850_NUART1_RTS,
- DA850_UART1_RXD,
- DA850_UART1_TXD,
-
- /* UART2 function */
- DA850_NUART2_CTS,
- DA850_NUART2_RTS,
- DA850_UART2_RXD,
- DA850_UART2_TXD,
-
- /* I2C1 function */
- DA850_I2C1_SCL,
- DA850_I2C1_SDA,
-
- /* I2C0 function */
- DA850_I2C0_SDA,
- DA850_I2C0_SCL,
-
- /* EMAC function */
- DA850_MII_TXEN,
- DA850_MII_TXCLK,
- DA850_MII_COL,
- DA850_MII_TXD_3,
- DA850_MII_TXD_2,
- DA850_MII_TXD_1,
- DA850_MII_TXD_0,
- DA850_MII_RXER,
- DA850_MII_CRS,
- DA850_MII_RXCLK,
- DA850_MII_RXDV,
- DA850_MII_RXD_3,
- DA850_MII_RXD_2,
- DA850_MII_RXD_1,
- DA850_MII_RXD_0,
- DA850_MDIO_CLK,
- DA850_MDIO_D,
- DA850_RMII_TXD_0,
- DA850_RMII_TXD_1,
- DA850_RMII_TXEN,
- DA850_RMII_CRS_DV,
- DA850_RMII_RXD_0,
- DA850_RMII_RXD_1,
- DA850_RMII_RXER,
- DA850_RMII_MHZ_50_CLK,
-
- /* McASP function */
- DA850_ACLKR,
- DA850_ACLKX,
- DA850_AFSR,
- DA850_AFSX,
- DA850_AHCLKR,
- DA850_AHCLKX,
- DA850_AMUTE,
- DA850_AXR_15,
- DA850_AXR_14,
- DA850_AXR_13,
- DA850_AXR_12,
- DA850_AXR_11,
- DA850_AXR_10,
- DA850_AXR_9,
- DA850_AXR_8,
- DA850_AXR_7,
- DA850_AXR_6,
- DA850_AXR_5,
- DA850_AXR_4,
- DA850_AXR_3,
- DA850_AXR_2,
- DA850_AXR_1,
- DA850_AXR_0,
-
- /* LCD function */
- DA850_LCD_D_7,
- DA850_LCD_D_6,
- DA850_LCD_D_5,
- DA850_LCD_D_4,
- DA850_LCD_D_3,
- DA850_LCD_D_2,
- DA850_LCD_D_1,
- DA850_LCD_D_0,
- DA850_LCD_D_15,
- DA850_LCD_D_14,
- DA850_LCD_D_13,
- DA850_LCD_D_12,
- DA850_LCD_D_11,
- DA850_LCD_D_10,
- DA850_LCD_D_9,
- DA850_LCD_D_8,
- DA850_LCD_PCLK,
- DA850_LCD_HSYNC,
- DA850_LCD_VSYNC,
- DA850_NLCD_AC_ENB_CS,
-
- /* MMC/SD0 function */
- DA850_MMCSD0_DAT_0,
- DA850_MMCSD0_DAT_1,
- DA850_MMCSD0_DAT_2,
- DA850_MMCSD0_DAT_3,
- DA850_MMCSD0_CLK,
- DA850_MMCSD0_CMD,
-
- /* MMC/SD1 function */
- DA850_MMCSD1_DAT_0,
- DA850_MMCSD1_DAT_1,
- DA850_MMCSD1_DAT_2,
- DA850_MMCSD1_DAT_3,
- DA850_MMCSD1_CLK,
- DA850_MMCSD1_CMD,
-
- /* EMIF2.5/EMIFA function */
- DA850_EMA_D_7,
- DA850_EMA_D_6,
- DA850_EMA_D_5,
- DA850_EMA_D_4,
- DA850_EMA_D_3,
- DA850_EMA_D_2,
- DA850_EMA_D_1,
- DA850_EMA_D_0,
- DA850_EMA_A_1,
- DA850_EMA_A_2,
- DA850_NEMA_CS_3,
- DA850_NEMA_CS_4,
- DA850_NEMA_WE,
- DA850_NEMA_OE,
- DA850_EMA_D_15,
- DA850_EMA_D_14,
- DA850_EMA_D_13,
- DA850_EMA_D_12,
- DA850_EMA_D_11,
- DA850_EMA_D_10,
- DA850_EMA_D_9,
- DA850_EMA_D_8,
- DA850_EMA_A_0,
- DA850_EMA_A_3,
- DA850_EMA_A_4,
- DA850_EMA_A_5,
- DA850_EMA_A_6,
- DA850_EMA_A_7,
- DA850_EMA_A_8,
- DA850_EMA_A_9,
- DA850_EMA_A_10,
- DA850_EMA_A_11,
- DA850_EMA_A_12,
- DA850_EMA_A_13,
- DA850_EMA_A_14,
- DA850_EMA_A_15,
- DA850_EMA_A_16,
- DA850_EMA_A_17,
- DA850_EMA_A_18,
- DA850_EMA_A_19,
- DA850_EMA_A_20,
- DA850_EMA_A_21,
- DA850_EMA_A_22,
- DA850_EMA_A_23,
- DA850_EMA_BA_1,
- DA850_EMA_CLK,
- DA850_EMA_WAIT_1,
- DA850_NEMA_CS_2,
-
- /* GPIO function */
- DA850_GPIO2_4,
- DA850_GPIO2_6,
- DA850_GPIO2_8,
- DA850_GPIO2_15,
- DA850_GPIO3_12,
- DA850_GPIO3_13,
- DA850_GPIO4_0,
- DA850_GPIO4_1,
- DA850_GPIO6_9,
- DA850_GPIO6_10,
- DA850_GPIO6_13,
- DA850_RTC_ALARM,
-
- /* VPIF Capture */
- DA850_VPIF_DIN0,
- DA850_VPIF_DIN1,
- DA850_VPIF_DIN2,
- DA850_VPIF_DIN3,
- DA850_VPIF_DIN4,
- DA850_VPIF_DIN5,
- DA850_VPIF_DIN6,
- DA850_VPIF_DIN7,
- DA850_VPIF_DIN8,
- DA850_VPIF_DIN9,
- DA850_VPIF_DIN10,
- DA850_VPIF_DIN11,
- DA850_VPIF_DIN12,
- DA850_VPIF_DIN13,
- DA850_VPIF_DIN14,
- DA850_VPIF_DIN15,
- DA850_VPIF_CLKIN0,
- DA850_VPIF_CLKIN1,
- DA850_VPIF_CLKIN2,
- DA850_VPIF_CLKIN3,
-
- /* VPIF Display */
- DA850_VPIF_DOUT0,
- DA850_VPIF_DOUT1,
- DA850_VPIF_DOUT2,
- DA850_VPIF_DOUT3,
- DA850_VPIF_DOUT4,
- DA850_VPIF_DOUT5,
- DA850_VPIF_DOUT6,
- DA850_VPIF_DOUT7,
- DA850_VPIF_DOUT8,
- DA850_VPIF_DOUT9,
- DA850_VPIF_DOUT10,
- DA850_VPIF_DOUT11,
- DA850_VPIF_DOUT12,
- DA850_VPIF_DOUT13,
- DA850_VPIF_DOUT14,
- DA850_VPIF_DOUT15,
- DA850_VPIF_CLKO2,
- DA850_VPIF_CLKO3,
-};
-
-#define PINMUX(x) (4 * (x))
-
-#ifdef CONFIG_DAVINCI_MUX
-/* setup pin muxing */
-extern int davinci_cfg_reg(unsigned long reg_cfg);
-extern int davinci_cfg_reg_list(const short pins[]);
-#else
-/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
-static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
-static inline int davinci_cfg_reg_list(const short pins[])
-{
- return 0;
-}
-#endif
-
-#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
deleted file mode 100644
index d4b4aa87964f..000000000000
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * DaVinci serial device definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#include <asm/memory.h>
-
-#include <mach/hardware.h>
-
-#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
-#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
-#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
-
-#define DA8XX_UART0_BASE (IO_PHYS + 0x042000)
-#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
-#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
-
-/* DaVinci UART register offsets */
-#define UART_DAVINCI_PWREMU 0x0c
-#define UART_DM646X_SCR 0x10
-#define UART_DM646X_SCR_TX_WATERMARK 0x08
-
-#ifndef __ASSEMBLY__
-#include <linux/platform_device.h>
-
-extern int davinci_serial_init(struct platform_device *);
-#endif
-
-#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
deleted file mode 100644
index 53b456a5bbe0..000000000000
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Original copyrights follow.
- *
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/serial.h>
-
-#define IOMEM(x) ((void __force __iomem *)(x))
-
-u32 *uart;
-
-/* PORT_16C550A, in polled non-fifo mode */
-static inline void putc(char c)
-{
- if (!uart)
- return;
-
- while (!(uart[UART_LSR] & UART_LSR_THRE))
- barrier();
- uart[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
- if (!uart)
- return;
-
- while (!(uart[UART_LSR] & UART_LSR_THRE))
- barrier();
-}
-
-static inline void set_uart_info(u32 phys)
-{
- uart = (u32 *)phys;
-}
-
-#define _DEBUG_LL_ENTRY(machine, phys) \
- { \
- if (machine_is_##machine()) { \
- set_uart_info(phys); \
- break; \
- } \
- }
-
-#define DEBUG_LL_DAVINCI(machine, port) \
- _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE)
-
-#define DEBUG_LL_DA8XX(machine, port) \
- _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
-
-static inline void __arch_decomp_setup(unsigned long arch_id)
-{
- /*
- * Initialize the port based on the machine ID from the bootloader.
- * Note that we're using macros here instead of switch statement
- * as machine_is functions are optimized out for the boards that
- * are not selected.
- */
- do {
- /* Davinci boards */
- DEBUG_LL_DAVINCI(davinci_evm, 0);
- DEBUG_LL_DAVINCI(sffsdr, 0);
- DEBUG_LL_DAVINCI(neuros_osd2, 0);
- DEBUG_LL_DAVINCI(davinci_dm355_evm, 0);
- DEBUG_LL_DAVINCI(dm355_leopard, 0);
- DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0);
- DEBUG_LL_DAVINCI(davinci_dm365_evm, 0);
-
- /* DA8xx boards */
- DEBUG_LL_DA8XX(davinci_da830_evm, 2);
- DEBUG_LL_DA8XX(davinci_da850_evm, 2);
- DEBUG_LL_DA8XX(mityomapl138, 1);
- DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
- } while (0);
-}
-
-#define arch_decomp_setup() __arch_decomp_setup(arch_id)
diff --git a/arch/arm/mach-davinci/irqs.h b/arch/arm/mach-davinci/irqs.h
index 8f9fc7a56ce8..b1ceed81e9fa 100644
--- a/arch/arm/mach-davinci/irqs.h
+++ b/arch/arm/mach-davinci/irqs.h
@@ -27,219 +27,6 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
-/* Base address */
-#define DAVINCI_ARM_INTC_BASE 0x01C48000
-
-/* Interrupt lines */
-#define IRQ_VDINT0 0
-#define IRQ_VDINT1 1
-#define IRQ_VDINT2 2
-#define IRQ_HISTINT 3
-#define IRQ_H3AINT 4
-#define IRQ_PRVUINT 5
-#define IRQ_RSZINT 6
-#define IRQ_VFOCINT 7
-#define IRQ_VENCINT 8
-#define IRQ_ASQINT 9
-#define IRQ_IMXINT 10
-#define IRQ_VLCDINT 11
-#define IRQ_USBINT 12
-#define IRQ_EMACINT 13
-
-#define IRQ_CCINT0 16
-#define IRQ_CCERRINT 17
-#define IRQ_TCERRINT0 18
-#define IRQ_TCERRINT 19
-#define IRQ_PSCIN 20
-
-#define IRQ_IDE 22
-#define IRQ_HPIINT 23
-#define IRQ_MBXINT 24
-#define IRQ_MBRINT 25
-#define IRQ_MMCINT 26
-#define IRQ_SDIOINT 27
-#define IRQ_MSINT 28
-#define IRQ_DDRINT 29
-#define IRQ_AEMIFINT 30
-#define IRQ_VLQINT 31
-#define IRQ_TINT0_TINT12 32
-#define IRQ_TINT0_TINT34 33
-#define IRQ_TINT1_TINT12 34
-#define IRQ_TINT1_TINT34 35
-#define IRQ_PWMINT0 36
-#define IRQ_PWMINT1 37
-#define IRQ_PWMINT2 38
-#define IRQ_I2C 39
-#define IRQ_UARTINT0 40
-#define IRQ_UARTINT1 41
-#define IRQ_UARTINT2 42
-#define IRQ_SPINT0 43
-#define IRQ_SPINT1 44
-
-#define IRQ_DSP2ARM0 46
-#define IRQ_DSP2ARM1 47
-#define IRQ_GPIO0 48
-#define IRQ_GPIO1 49
-#define IRQ_GPIO2 50
-#define IRQ_GPIO3 51
-#define IRQ_GPIO4 52
-#define IRQ_GPIO5 53
-#define IRQ_GPIO6 54
-#define IRQ_GPIO7 55
-#define IRQ_GPIOBNK0 56
-#define IRQ_GPIOBNK1 57
-#define IRQ_GPIOBNK2 58
-#define IRQ_GPIOBNK3 59
-#define IRQ_GPIOBNK4 60
-#define IRQ_COMMTX 61
-#define IRQ_COMMRX 62
-#define IRQ_EMUINT 63
-
-#define DAVINCI_N_AINTC_IRQ 64
-
-#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
-
-/* DaVinci DM6467-specific Interrupts */
-#define IRQ_DM646X_VP_VERTINT0 0
-#define IRQ_DM646X_VP_VERTINT1 1
-#define IRQ_DM646X_VP_VERTINT2 2
-#define IRQ_DM646X_VP_VERTINT3 3
-#define IRQ_DM646X_VP_ERRINT 4
-#define IRQ_DM646X_RESERVED_1 5
-#define IRQ_DM646X_RESERVED_2 6
-#define IRQ_DM646X_WDINT 7
-#define IRQ_DM646X_CRGENINT0 8
-#define IRQ_DM646X_CRGENINT1 9
-#define IRQ_DM646X_TSIFINT0 10
-#define IRQ_DM646X_TSIFINT1 11
-#define IRQ_DM646X_VDCEINT 12
-#define IRQ_DM646X_USBINT 13
-#define IRQ_DM646X_USBDMAINT 14
-#define IRQ_DM646X_PCIINT 15
-#define IRQ_DM646X_TCERRINT2 20
-#define IRQ_DM646X_TCERRINT3 21
-#define IRQ_DM646X_IDE 22
-#define IRQ_DM646X_HPIINT 23
-#define IRQ_DM646X_EMACRXTHINT 24
-#define IRQ_DM646X_EMACRXINT 25
-#define IRQ_DM646X_EMACTXINT 26
-#define IRQ_DM646X_EMACMISCINT 27
-#define IRQ_DM646X_MCASP0TXINT 28
-#define IRQ_DM646X_MCASP0RXINT 29
-#define IRQ_DM646X_MCASP1TXINT 30
-#define IRQ_DM646X_RESERVED_3 31
-#define IRQ_DM646X_VLQINT 38
-#define IRQ_DM646X_UARTINT2 42
-#define IRQ_DM646X_SPINT0 43
-#define IRQ_DM646X_SPINT1 44
-#define IRQ_DM646X_DSP2ARMINT 45
-#define IRQ_DM646X_RESERVED_4 46
-#define IRQ_DM646X_PSCINT 47
-#define IRQ_DM646X_GPIO0 48
-#define IRQ_DM646X_GPIO1 49
-#define IRQ_DM646X_GPIO2 50
-#define IRQ_DM646X_GPIO3 51
-#define IRQ_DM646X_GPIO4 52
-#define IRQ_DM646X_GPIO5 53
-#define IRQ_DM646X_GPIO6 54
-#define IRQ_DM646X_GPIO7 55
-#define IRQ_DM646X_GPIOBNK0 56
-#define IRQ_DM646X_GPIOBNK1 57
-#define IRQ_DM646X_GPIOBNK2 58
-#define IRQ_DM646X_DDRINT 59
-#define IRQ_DM646X_AEMIFINT 60
-
-/* DaVinci DM355-specific Interrupts */
-#define IRQ_DM355_CCDC_VDINT0 0
-#define IRQ_DM355_CCDC_VDINT1 1
-#define IRQ_DM355_CCDC_VDINT2 2
-#define IRQ_DM355_IPIPE_HST 3
-#define IRQ_DM355_H3AINT 4
-#define IRQ_DM355_IPIPE_SDR 5
-#define IRQ_DM355_IPIPEIFINT 6
-#define IRQ_DM355_OSDINT 7
-#define IRQ_DM355_VENCINT 8
-#define IRQ_DM355_IMCOPINT 11
-#define IRQ_DM355_RTOINT 13
-#define IRQ_DM355_TINT4 13
-#define IRQ_DM355_TINT2_TINT12 13
-#define IRQ_DM355_UARTINT2 14
-#define IRQ_DM355_TINT5 14
-#define IRQ_DM355_TINT2_TINT34 14
-#define IRQ_DM355_TINT6 15
-#define IRQ_DM355_TINT3_TINT12 15
-#define IRQ_DM355_SPINT1_0 17
-#define IRQ_DM355_SPINT1_1 18
-#define IRQ_DM355_SPINT2_0 19
-#define IRQ_DM355_SPINT2_1 21
-#define IRQ_DM355_TINT7 22
-#define IRQ_DM355_TINT3_TINT34 22
-#define IRQ_DM355_SDIOINT0 23
-#define IRQ_DM355_MMCINT0 26
-#define IRQ_DM355_MSINT 26
-#define IRQ_DM355_MMCINT1 27
-#define IRQ_DM355_PWMINT3 28
-#define IRQ_DM355_SDIOINT1 31
-#define IRQ_DM355_SPINT0_0 42
-#define IRQ_DM355_SPINT0_1 43
-#define IRQ_DM355_GPIO0 44
-#define IRQ_DM355_GPIO1 45
-#define IRQ_DM355_GPIO2 46
-#define IRQ_DM355_GPIO3 47
-#define IRQ_DM355_GPIO4 48
-#define IRQ_DM355_GPIO5 49
-#define IRQ_DM355_GPIO6 50
-#define IRQ_DM355_GPIO7 51
-#define IRQ_DM355_GPIO8 52
-#define IRQ_DM355_GPIO9 53
-#define IRQ_DM355_GPIOBNK0 54
-#define IRQ_DM355_GPIOBNK1 55
-#define IRQ_DM355_GPIOBNK2 56
-#define IRQ_DM355_GPIOBNK3 57
-#define IRQ_DM355_GPIOBNK4 58
-#define IRQ_DM355_GPIOBNK5 59
-#define IRQ_DM355_GPIOBNK6 60
-
-/* DaVinci DM365-specific Interrupts */
-#define IRQ_DM365_INSFINT 7
-#define IRQ_DM365_IMXINT1 8
-#define IRQ_DM365_IMXINT0 10
-#define IRQ_DM365_KLD_ARMINT 10
-#define IRQ_DM365_IMCOPINT 11
-#define IRQ_DM365_RTOINT 13
-#define IRQ_DM365_TINT5 14
-#define IRQ_DM365_TINT6 15
-#define IRQ_DM365_SPINT2_1 21
-#define IRQ_DM365_TINT7 22
-#define IRQ_DM365_SDIOINT0 23
-#define IRQ_DM365_MMCINT1 27
-#define IRQ_DM365_PWMINT3 28
-#define IRQ_DM365_RTCINT 29
-#define IRQ_DM365_SDIOINT1 31
-#define IRQ_DM365_SPIINT0_0 42
-#define IRQ_DM365_SPIINT3_0 43
-#define IRQ_DM365_GPIO0 44
-#define IRQ_DM365_GPIO1 45
-#define IRQ_DM365_GPIO2 46
-#define IRQ_DM365_GPIO3 47
-#define IRQ_DM365_GPIO4 48
-#define IRQ_DM365_GPIO5 49
-#define IRQ_DM365_GPIO6 50
-#define IRQ_DM365_GPIO7 51
-#define IRQ_DM365_EMAC_RXTHRESH 52
-#define IRQ_DM365_EMAC_RXPULSE 53
-#define IRQ_DM365_EMAC_TXPULSE 54
-#define IRQ_DM365_EMAC_MISCPULSE 55
-#define IRQ_DM365_GPIO12 56
-#define IRQ_DM365_GPIO13 57
-#define IRQ_DM365_GPIO14 58
-#define IRQ_DM365_GPIO15 59
-#define IRQ_DM365_ADCINT 59
-#define IRQ_DM365_KEYINT 60
-#define IRQ_DM365_TCERRINT2 61
-#define IRQ_DM365_TCERRINT3 62
-#define IRQ_DM365_EMUINT 63
-
/* DA8XX interrupts */
#define IRQ_DA8XX_COMMTX 0
#define IRQ_DA8XX_COMMRX 1
@@ -398,8 +185,4 @@
#define DA850_N_CP_INTC_IRQ 101
-/* da850 currently has the most gpio pins (144) */
-#define DAVINCI_N_GPIO 144
-/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
-
#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 6a2ff0a654a5..37de35eb6e8b 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Utility to set the DAVINCI MUX register from a table in mux.h
*
@@ -8,10 +9,7 @@
*
* Written by Tony Lindgren
*
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
*
* Copyright (C) 2008 Texas Instruments.
*/
@@ -22,8 +20,8 @@
#include <linux/module.h>
#include <linux/spinlock.h>
-#include <mach/mux.h>
-#include <mach/common.h>
+#include "mux.h"
+#include "common.h"
static void __iomem *pinmux_base;
@@ -99,18 +97,3 @@ int davinci_cfg_reg(const unsigned long index)
return 0;
}
-EXPORT_SYMBOL(davinci_cfg_reg);
-
-int davinci_cfg_reg_list(const short pins[])
-{
- int i, error = -EINVAL;
-
- if (pins)
- for (i = 0; pins[i] >= 0; i++) {
- error = davinci_cfg_reg(pins[i]);
- if (error)
- break;
- }
-
- return error;
-}
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
index 5aad1e7dd210..38f0e427291e 100644
--- a/arch/arm/mach-davinci/mux.h
+++ b/arch/arm/mach-davinci/mux.h
@@ -1,19 +1,669 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Pin-multiplex helper macros for TI DaVinci family devices
*
* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
*
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
*
* Copyright (C) 2008 Texas Instruments.
*/
#ifndef _MACH_DAVINCI_MUX_H_
#define _MACH_DAVINCI_MUX_H_
-#include <mach/mux.h>
+struct mux_config {
+ const char *name;
+ const char *mux_reg_name;
+ const unsigned char mux_reg;
+ const unsigned char mask_offset;
+ const unsigned char mask;
+ const unsigned char mode;
+ bool debug;
+};
+
+enum da830_index {
+ DA830_GPIO7_14,
+ DA830_RTCK,
+ DA830_GPIO7_15,
+ DA830_EMU_0,
+ DA830_EMB_SDCKE,
+ DA830_EMB_CLK_GLUE,
+ DA830_EMB_CLK,
+ DA830_NEMB_CS_0,
+ DA830_NEMB_CAS,
+ DA830_NEMB_RAS,
+ DA830_NEMB_WE,
+ DA830_EMB_BA_1,
+ DA830_EMB_BA_0,
+ DA830_EMB_A_0,
+ DA830_EMB_A_1,
+ DA830_EMB_A_2,
+ DA830_EMB_A_3,
+ DA830_EMB_A_4,
+ DA830_EMB_A_5,
+ DA830_GPIO7_0,
+ DA830_GPIO7_1,
+ DA830_GPIO7_2,
+ DA830_GPIO7_3,
+ DA830_GPIO7_4,
+ DA830_GPIO7_5,
+ DA830_GPIO7_6,
+ DA830_GPIO7_7,
+ DA830_EMB_A_6,
+ DA830_EMB_A_7,
+ DA830_EMB_A_8,
+ DA830_EMB_A_9,
+ DA830_EMB_A_10,
+ DA830_EMB_A_11,
+ DA830_EMB_A_12,
+ DA830_EMB_D_31,
+ DA830_GPIO7_8,
+ DA830_GPIO7_9,
+ DA830_GPIO7_10,
+ DA830_GPIO7_11,
+ DA830_GPIO7_12,
+ DA830_GPIO7_13,
+ DA830_GPIO3_13,
+ DA830_EMB_D_30,
+ DA830_EMB_D_29,
+ DA830_EMB_D_28,
+ DA830_EMB_D_27,
+ DA830_EMB_D_26,
+ DA830_EMB_D_25,
+ DA830_EMB_D_24,
+ DA830_EMB_D_23,
+ DA830_EMB_D_22,
+ DA830_EMB_D_21,
+ DA830_EMB_D_20,
+ DA830_EMB_D_19,
+ DA830_EMB_D_18,
+ DA830_EMB_D_17,
+ DA830_EMB_D_16,
+ DA830_NEMB_WE_DQM_3,
+ DA830_NEMB_WE_DQM_2,
+ DA830_EMB_D_0,
+ DA830_EMB_D_1,
+ DA830_EMB_D_2,
+ DA830_EMB_D_3,
+ DA830_EMB_D_4,
+ DA830_EMB_D_5,
+ DA830_EMB_D_6,
+ DA830_GPIO6_0,
+ DA830_GPIO6_1,
+ DA830_GPIO6_2,
+ DA830_GPIO6_3,
+ DA830_GPIO6_4,
+ DA830_GPIO6_5,
+ DA830_GPIO6_6,
+ DA830_EMB_D_7,
+ DA830_EMB_D_8,
+ DA830_EMB_D_9,
+ DA830_EMB_D_10,
+ DA830_EMB_D_11,
+ DA830_EMB_D_12,
+ DA830_EMB_D_13,
+ DA830_EMB_D_14,
+ DA830_GPIO6_7,
+ DA830_GPIO6_8,
+ DA830_GPIO6_9,
+ DA830_GPIO6_10,
+ DA830_GPIO6_11,
+ DA830_GPIO6_12,
+ DA830_GPIO6_13,
+ DA830_GPIO6_14,
+ DA830_EMB_D_15,
+ DA830_NEMB_WE_DQM_1,
+ DA830_NEMB_WE_DQM_0,
+ DA830_SPI0_SOMI_0,
+ DA830_SPI0_SIMO_0,
+ DA830_SPI0_CLK,
+ DA830_NSPI0_ENA,
+ DA830_NSPI0_SCS_0,
+ DA830_EQEP0I,
+ DA830_EQEP0S,
+ DA830_EQEP1I,
+ DA830_NUART0_CTS,
+ DA830_NUART0_RTS,
+ DA830_EQEP0A,
+ DA830_EQEP0B,
+ DA830_GPIO6_15,
+ DA830_GPIO5_14,
+ DA830_GPIO5_15,
+ DA830_GPIO5_0,
+ DA830_GPIO5_1,
+ DA830_GPIO5_2,
+ DA830_GPIO5_3,
+ DA830_GPIO5_4,
+ DA830_SPI1_SOMI_0,
+ DA830_SPI1_SIMO_0,
+ DA830_SPI1_CLK,
+ DA830_UART0_RXD,
+ DA830_UART0_TXD,
+ DA830_AXR1_10,
+ DA830_AXR1_11,
+ DA830_NSPI1_ENA,
+ DA830_I2C1_SCL,
+ DA830_I2C1_SDA,
+ DA830_EQEP1S,
+ DA830_I2C0_SDA,
+ DA830_I2C0_SCL,
+ DA830_UART2_RXD,
+ DA830_TM64P0_IN12,
+ DA830_TM64P0_OUT12,
+ DA830_GPIO5_5,
+ DA830_GPIO5_6,
+ DA830_GPIO5_7,
+ DA830_GPIO5_8,
+ DA830_GPIO5_9,
+ DA830_GPIO5_10,
+ DA830_GPIO5_11,
+ DA830_GPIO5_12,
+ DA830_NSPI1_SCS_0,
+ DA830_USB0_DRVVBUS,
+ DA830_AHCLKX0,
+ DA830_ACLKX0,
+ DA830_AFSX0,
+ DA830_AHCLKR0,
+ DA830_ACLKR0,
+ DA830_AFSR0,
+ DA830_UART2_TXD,
+ DA830_AHCLKX2,
+ DA830_ECAP0_APWM0,
+ DA830_RMII_MHZ_50_CLK,
+ DA830_ECAP1_APWM1,
+ DA830_USB_REFCLKIN,
+ DA830_GPIO5_13,
+ DA830_GPIO4_15,
+ DA830_GPIO2_11,
+ DA830_GPIO2_12,
+ DA830_GPIO2_13,
+ DA830_GPIO2_14,
+ DA830_GPIO2_15,
+ DA830_GPIO3_12,
+ DA830_AMUTE0,
+ DA830_AXR0_0,
+ DA830_AXR0_1,
+ DA830_AXR0_2,
+ DA830_AXR0_3,
+ DA830_AXR0_4,
+ DA830_AXR0_5,
+ DA830_AXR0_6,
+ DA830_RMII_TXD_0,
+ DA830_RMII_TXD_1,
+ DA830_RMII_TXEN,
+ DA830_RMII_CRS_DV,
+ DA830_RMII_RXD_0,
+ DA830_RMII_RXD_1,
+ DA830_RMII_RXER,
+ DA830_AFSR2,
+ DA830_ACLKX2,
+ DA830_AXR2_3,
+ DA830_AXR2_2,
+ DA830_AXR2_1,
+ DA830_AFSX2,
+ DA830_ACLKR2,
+ DA830_NRESETOUT,
+ DA830_GPIO3_0,
+ DA830_GPIO3_1,
+ DA830_GPIO3_2,
+ DA830_GPIO3_3,
+ DA830_GPIO3_4,
+ DA830_GPIO3_5,
+ DA830_GPIO3_6,
+ DA830_AXR0_7,
+ DA830_AXR0_8,
+ DA830_UART1_RXD,
+ DA830_UART1_TXD,
+ DA830_AXR0_11,
+ DA830_AHCLKX1,
+ DA830_ACLKX1,
+ DA830_AFSX1,
+ DA830_MDIO_CLK,
+ DA830_MDIO_D,
+ DA830_AXR0_9,
+ DA830_AXR0_10,
+ DA830_EPWM0B,
+ DA830_EPWM0A,
+ DA830_EPWMSYNCI,
+ DA830_AXR2_0,
+ DA830_EPWMSYNC0,
+ DA830_GPIO3_7,
+ DA830_GPIO3_8,
+ DA830_GPIO3_9,
+ DA830_GPIO3_10,
+ DA830_GPIO3_11,
+ DA830_GPIO3_14,
+ DA830_GPIO3_15,
+ DA830_GPIO4_10,
+ DA830_AHCLKR1,
+ DA830_ACLKR1,
+ DA830_AFSR1,
+ DA830_AMUTE1,
+ DA830_AXR1_0,
+ DA830_AXR1_1,
+ DA830_AXR1_2,
+ DA830_AXR1_3,
+ DA830_ECAP2_APWM2,
+ DA830_EHRPWMGLUETZ,
+ DA830_EQEP1A,
+ DA830_GPIO4_11,
+ DA830_GPIO4_12,
+ DA830_GPIO4_13,
+ DA830_GPIO4_14,
+ DA830_GPIO4_0,
+ DA830_GPIO4_1,
+ DA830_GPIO4_2,
+ DA830_GPIO4_3,
+ DA830_AXR1_4,
+ DA830_AXR1_5,
+ DA830_AXR1_6,
+ DA830_AXR1_7,
+ DA830_AXR1_8,
+ DA830_AXR1_9,
+ DA830_EMA_D_0,
+ DA830_EMA_D_1,
+ DA830_EQEP1B,
+ DA830_EPWM2B,
+ DA830_EPWM2A,
+ DA830_EPWM1B,
+ DA830_EPWM1A,
+ DA830_MMCSD_DAT_0,
+ DA830_MMCSD_DAT_1,
+ DA830_UHPI_HD_0,
+ DA830_UHPI_HD_1,
+ DA830_GPIO4_4,
+ DA830_GPIO4_5,
+ DA830_GPIO4_6,
+ DA830_GPIO4_7,
+ DA830_GPIO4_8,
+ DA830_GPIO4_9,
+ DA830_GPIO0_0,
+ DA830_GPIO0_1,
+ DA830_EMA_D_2,
+ DA830_EMA_D_3,
+ DA830_EMA_D_4,
+ DA830_EMA_D_5,
+ DA830_EMA_D_6,
+ DA830_EMA_D_7,
+ DA830_EMA_D_8,
+ DA830_EMA_D_9,
+ DA830_MMCSD_DAT_2,
+ DA830_MMCSD_DAT_3,
+ DA830_MMCSD_DAT_4,
+ DA830_MMCSD_DAT_5,
+ DA830_MMCSD_DAT_6,
+ DA830_MMCSD_DAT_7,
+ DA830_UHPI_HD_8,
+ DA830_UHPI_HD_9,
+ DA830_UHPI_HD_2,
+ DA830_UHPI_HD_3,
+ DA830_UHPI_HD_4,
+ DA830_UHPI_HD_5,
+ DA830_UHPI_HD_6,
+ DA830_UHPI_HD_7,
+ DA830_LCD_D_8,
+ DA830_LCD_D_9,
+ DA830_GPIO0_2,
+ DA830_GPIO0_3,
+ DA830_GPIO0_4,
+ DA830_GPIO0_5,
+ DA830_GPIO0_6,
+ DA830_GPIO0_7,
+ DA830_GPIO0_8,
+ DA830_GPIO0_9,
+ DA830_EMA_D_10,
+ DA830_EMA_D_11,
+ DA830_EMA_D_12,
+ DA830_EMA_D_13,
+ DA830_EMA_D_14,
+ DA830_EMA_D_15,
+ DA830_EMA_A_0,
+ DA830_EMA_A_1,
+ DA830_UHPI_HD_10,
+ DA830_UHPI_HD_11,
+ DA830_UHPI_HD_12,
+ DA830_UHPI_HD_13,
+ DA830_UHPI_HD_14,
+ DA830_UHPI_HD_15,
+ DA830_LCD_D_7,
+ DA830_MMCSD_CLK,
+ DA830_LCD_D_10,
+ DA830_LCD_D_11,
+ DA830_LCD_D_12,
+ DA830_LCD_D_13,
+ DA830_LCD_D_14,
+ DA830_LCD_D_15,
+ DA830_UHPI_HCNTL0,
+ DA830_GPIO0_10,
+ DA830_GPIO0_11,
+ DA830_GPIO0_12,
+ DA830_GPIO0_13,
+ DA830_GPIO0_14,
+ DA830_GPIO0_15,
+ DA830_GPIO1_0,
+ DA830_GPIO1_1,
+ DA830_EMA_A_2,
+ DA830_EMA_A_3,
+ DA830_EMA_A_4,
+ DA830_EMA_A_5,
+ DA830_EMA_A_6,
+ DA830_EMA_A_7,
+ DA830_EMA_A_8,
+ DA830_EMA_A_9,
+ DA830_MMCSD_CMD,
+ DA830_LCD_D_6,
+ DA830_LCD_D_3,
+ DA830_LCD_D_2,
+ DA830_LCD_D_1,
+ DA830_LCD_D_0,
+ DA830_LCD_PCLK,
+ DA830_LCD_HSYNC,
+ DA830_UHPI_HCNTL1,
+ DA830_GPIO1_2,
+ DA830_GPIO1_3,
+ DA830_GPIO1_4,
+ DA830_GPIO1_5,
+ DA830_GPIO1_6,
+ DA830_GPIO1_7,
+ DA830_GPIO1_8,
+ DA830_GPIO1_9,
+ DA830_EMA_A_10,
+ DA830_EMA_A_11,
+ DA830_EMA_A_12,
+ DA830_EMA_BA_1,
+ DA830_EMA_BA_0,
+ DA830_EMA_CLK,
+ DA830_EMA_SDCKE,
+ DA830_NEMA_CAS,
+ DA830_LCD_VSYNC,
+ DA830_NLCD_AC_ENB_CS,
+ DA830_LCD_MCLK,
+ DA830_LCD_D_5,
+ DA830_LCD_D_4,
+ DA830_OBSCLK,
+ DA830_NEMA_CS_4,
+ DA830_UHPI_HHWIL,
+ DA830_AHCLKR2,
+ DA830_GPIO1_10,
+ DA830_GPIO1_11,
+ DA830_GPIO1_12,
+ DA830_GPIO1_13,
+ DA830_GPIO1_14,
+ DA830_GPIO1_15,
+ DA830_GPIO2_0,
+ DA830_GPIO2_1,
+ DA830_NEMA_RAS,
+ DA830_NEMA_WE,
+ DA830_NEMA_CS_0,
+ DA830_NEMA_CS_2,
+ DA830_NEMA_CS_3,
+ DA830_NEMA_OE,
+ DA830_NEMA_WE_DQM_1,
+ DA830_NEMA_WE_DQM_0,
+ DA830_NEMA_CS_5,
+ DA830_UHPI_HRNW,
+ DA830_NUHPI_HAS,
+ DA830_NUHPI_HCS,
+ DA830_NUHPI_HDS1,
+ DA830_NUHPI_HDS2,
+ DA830_NUHPI_HINT,
+ DA830_AXR0_12,
+ DA830_AMUTE2,
+ DA830_AXR0_13,
+ DA830_AXR0_14,
+ DA830_AXR0_15,
+ DA830_GPIO2_2,
+ DA830_GPIO2_3,
+ DA830_GPIO2_4,
+ DA830_GPIO2_5,
+ DA830_GPIO2_6,
+ DA830_GPIO2_7,
+ DA830_GPIO2_8,
+ DA830_GPIO2_9,
+ DA830_EMA_WAIT_0,
+ DA830_NUHPI_HRDY,
+ DA830_GPIO2_10,
+};
+
+enum davinci_da850_index {
+ /* UART0 function */
+ DA850_NUART0_CTS,
+ DA850_NUART0_RTS,
+ DA850_UART0_RXD,
+ DA850_UART0_TXD,
+
+ /* UART1 function */
+ DA850_NUART1_CTS,
+ DA850_NUART1_RTS,
+ DA850_UART1_RXD,
+ DA850_UART1_TXD,
+
+ /* UART2 function */
+ DA850_NUART2_CTS,
+ DA850_NUART2_RTS,
+ DA850_UART2_RXD,
+ DA850_UART2_TXD,
+
+ /* I2C1 function */
+ DA850_I2C1_SCL,
+ DA850_I2C1_SDA,
+
+ /* I2C0 function */
+ DA850_I2C0_SDA,
+ DA850_I2C0_SCL,
+
+ /* EMAC function */
+ DA850_MII_TXEN,
+ DA850_MII_TXCLK,
+ DA850_MII_COL,
+ DA850_MII_TXD_3,
+ DA850_MII_TXD_2,
+ DA850_MII_TXD_1,
+ DA850_MII_TXD_0,
+ DA850_MII_RXER,
+ DA850_MII_CRS,
+ DA850_MII_RXCLK,
+ DA850_MII_RXDV,
+ DA850_MII_RXD_3,
+ DA850_MII_RXD_2,
+ DA850_MII_RXD_1,
+ DA850_MII_RXD_0,
+ DA850_MDIO_CLK,
+ DA850_MDIO_D,
+ DA850_RMII_TXD_0,
+ DA850_RMII_TXD_1,
+ DA850_RMII_TXEN,
+ DA850_RMII_CRS_DV,
+ DA850_RMII_RXD_0,
+ DA850_RMII_RXD_1,
+ DA850_RMII_RXER,
+ DA850_RMII_MHZ_50_CLK,
+
+ /* McASP function */
+ DA850_ACLKR,
+ DA850_ACLKX,
+ DA850_AFSR,
+ DA850_AFSX,
+ DA850_AHCLKR,
+ DA850_AHCLKX,
+ DA850_AMUTE,
+ DA850_AXR_15,
+ DA850_AXR_14,
+ DA850_AXR_13,
+ DA850_AXR_12,
+ DA850_AXR_11,
+ DA850_AXR_10,
+ DA850_AXR_9,
+ DA850_AXR_8,
+ DA850_AXR_7,
+ DA850_AXR_6,
+ DA850_AXR_5,
+ DA850_AXR_4,
+ DA850_AXR_3,
+ DA850_AXR_2,
+ DA850_AXR_1,
+ DA850_AXR_0,
+
+ /* LCD function */
+ DA850_LCD_D_7,
+ DA850_LCD_D_6,
+ DA850_LCD_D_5,
+ DA850_LCD_D_4,
+ DA850_LCD_D_3,
+ DA850_LCD_D_2,
+ DA850_LCD_D_1,
+ DA850_LCD_D_0,
+ DA850_LCD_D_15,
+ DA850_LCD_D_14,
+ DA850_LCD_D_13,
+ DA850_LCD_D_12,
+ DA850_LCD_D_11,
+ DA850_LCD_D_10,
+ DA850_LCD_D_9,
+ DA850_LCD_D_8,
+ DA850_LCD_PCLK,
+ DA850_LCD_HSYNC,
+ DA850_LCD_VSYNC,
+ DA850_NLCD_AC_ENB_CS,
+
+ /* MMC/SD0 function */
+ DA850_MMCSD0_DAT_0,
+ DA850_MMCSD0_DAT_1,
+ DA850_MMCSD0_DAT_2,
+ DA850_MMCSD0_DAT_3,
+ DA850_MMCSD0_CLK,
+ DA850_MMCSD0_CMD,
+
+ /* MMC/SD1 function */
+ DA850_MMCSD1_DAT_0,
+ DA850_MMCSD1_DAT_1,
+ DA850_MMCSD1_DAT_2,
+ DA850_MMCSD1_DAT_3,
+ DA850_MMCSD1_CLK,
+ DA850_MMCSD1_CMD,
+
+ /* EMIF2.5/EMIFA function */
+ DA850_EMA_D_7,
+ DA850_EMA_D_6,
+ DA850_EMA_D_5,
+ DA850_EMA_D_4,
+ DA850_EMA_D_3,
+ DA850_EMA_D_2,
+ DA850_EMA_D_1,
+ DA850_EMA_D_0,
+ DA850_EMA_A_1,
+ DA850_EMA_A_2,
+ DA850_NEMA_CS_3,
+ DA850_NEMA_CS_4,
+ DA850_NEMA_WE,
+ DA850_NEMA_OE,
+ DA850_EMA_D_15,
+ DA850_EMA_D_14,
+ DA850_EMA_D_13,
+ DA850_EMA_D_12,
+ DA850_EMA_D_11,
+ DA850_EMA_D_10,
+ DA850_EMA_D_9,
+ DA850_EMA_D_8,
+ DA850_EMA_A_0,
+ DA850_EMA_A_3,
+ DA850_EMA_A_4,
+ DA850_EMA_A_5,
+ DA850_EMA_A_6,
+ DA850_EMA_A_7,
+ DA850_EMA_A_8,
+ DA850_EMA_A_9,
+ DA850_EMA_A_10,
+ DA850_EMA_A_11,
+ DA850_EMA_A_12,
+ DA850_EMA_A_13,
+ DA850_EMA_A_14,
+ DA850_EMA_A_15,
+ DA850_EMA_A_16,
+ DA850_EMA_A_17,
+ DA850_EMA_A_18,
+ DA850_EMA_A_19,
+ DA850_EMA_A_20,
+ DA850_EMA_A_21,
+ DA850_EMA_A_22,
+ DA850_EMA_A_23,
+ DA850_EMA_BA_1,
+ DA850_EMA_CLK,
+ DA850_EMA_WAIT_1,
+ DA850_NEMA_CS_2,
+
+ /* GPIO function */
+ DA850_GPIO2_4,
+ DA850_GPIO2_6,
+ DA850_GPIO2_8,
+ DA850_GPIO2_15,
+ DA850_GPIO3_12,
+ DA850_GPIO3_13,
+ DA850_GPIO4_0,
+ DA850_GPIO4_1,
+ DA850_GPIO6_9,
+ DA850_GPIO6_10,
+ DA850_GPIO6_13,
+ DA850_RTC_ALARM,
+
+ /* VPIF Capture */
+ DA850_VPIF_DIN0,
+ DA850_VPIF_DIN1,
+ DA850_VPIF_DIN2,
+ DA850_VPIF_DIN3,
+ DA850_VPIF_DIN4,
+ DA850_VPIF_DIN5,
+ DA850_VPIF_DIN6,
+ DA850_VPIF_DIN7,
+ DA850_VPIF_DIN8,
+ DA850_VPIF_DIN9,
+ DA850_VPIF_DIN10,
+ DA850_VPIF_DIN11,
+ DA850_VPIF_DIN12,
+ DA850_VPIF_DIN13,
+ DA850_VPIF_DIN14,
+ DA850_VPIF_DIN15,
+ DA850_VPIF_CLKIN0,
+ DA850_VPIF_CLKIN1,
+ DA850_VPIF_CLKIN2,
+ DA850_VPIF_CLKIN3,
+
+ /* VPIF Display */
+ DA850_VPIF_DOUT0,
+ DA850_VPIF_DOUT1,
+ DA850_VPIF_DOUT2,
+ DA850_VPIF_DOUT3,
+ DA850_VPIF_DOUT4,
+ DA850_VPIF_DOUT5,
+ DA850_VPIF_DOUT6,
+ DA850_VPIF_DOUT7,
+ DA850_VPIF_DOUT8,
+ DA850_VPIF_DOUT9,
+ DA850_VPIF_DOUT10,
+ DA850_VPIF_DOUT11,
+ DA850_VPIF_DOUT12,
+ DA850_VPIF_DOUT13,
+ DA850_VPIF_DOUT14,
+ DA850_VPIF_DOUT15,
+ DA850_VPIF_CLKO2,
+ DA850_VPIF_CLKO3,
+};
+
+#define PINMUX(x) (4 * (x))
+
+#ifdef CONFIG_DAVINCI_MUX
+/* setup pin muxing */
+extern int davinci_cfg_reg(unsigned long reg_cfg);
+extern int davinci_cfg_reg_list(const short pins[]);
+#else
+/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
+static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
+static inline int davinci_cfg_reg_list(const short pins[])
+{
+ return 0;
+}
+#endif
+
#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
[soc##_##desc] = { \
diff --git a/arch/arm/mach-davinci/pdata-quirks.c b/arch/arm/mach-davinci/pdata-quirks.c
index 67f1c8537354..b8b5f1a5e092 100644
--- a/arch/arm/mach-davinci/pdata-quirks.c
+++ b/arch/arm/mach-davinci/pdata-quirks.c
@@ -10,8 +10,8 @@
#include <media/i2c/tvp514x.h>
#include <media/i2c/adv7343.h>
-#include <mach/common.h>
-#include <mach/da8xx.h>
+#include "common.h"
+#include "da8xx.h"
struct pdata_init {
const char *compatible;
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index 323ee4e657c4..8aa39db095d7 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -16,11 +16,10 @@
#include <asm/delay.h>
#include <asm/io.h>
-#include <mach/common.h>
-#include <mach/da8xx.h>
-#include <mach/mux.h>
-#include <mach/pm.h>
-
+#include "common.h"
+#include "da8xx.h"
+#include "mux.h"
+#include "pm.h"
#include "clock.h"
#include "psc.h"
#include "sram.h"
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/pm.h
index 5a5f0ecc0704..6f50d6eb8da8 100644
--- a/arch/arm/mach-davinci/include/mach/pm.h
+++ b/arch/arm/mach-davinci/pm.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI DaVinci platform support for power management.
*
* Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MACH_DAVINCI_PM_H
#define _MACH_DAVINCI_PM_H
diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c
index e251fd593bfd..6b21d5bd999c 100644
--- a/arch/arm/mach-davinci/pm_domain.c
+++ b/arch/arm/mach-davinci/pm_domain.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Runtime PM support code for DaVinci
*
* Author: Kevin Hilman
*
* Copyright (C) 2012 Texas Instruments, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/pm_runtime.h>
diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h
index 68cd9d3fc82b..acfef063295f 100644
--- a/arch/arm/mach-davinci/psc.h
+++ b/arch/arm/mach-davinci/psc.h
@@ -70,70 +70,6 @@
#define DAVINCI_LPSC_GEM 39
#define DAVINCI_LPSC_IMCOP 40
-#define DM355_LPSC_TIMER3 5
-#define DM355_LPSC_SPI1 6
-#define DM355_LPSC_MMC_SD1 7
-#define DM355_LPSC_McBSP1 8
-#define DM355_LPSC_PWM3 10
-#define DM355_LPSC_SPI2 11
-#define DM355_LPSC_RTO 12
-#define DM355_LPSC_VPSS_DAC 41
-
-/* DM365 */
-#define DM365_LPSC_TIMER3 5
-#define DM365_LPSC_SPI1 6
-#define DM365_LPSC_MMC_SD1 7
-#define DM365_LPSC_McBSP1 8
-#define DM365_LPSC_PWM3 10
-#define DM365_LPSC_SPI2 11
-#define DM365_LPSC_RTO 12
-#define DM365_LPSC_TIMER4 17
-#define DM365_LPSC_SPI0 22
-#define DM365_LPSC_SPI3 38
-#define DM365_LPSC_SPI4 39
-#define DM365_LPSC_EMAC 40
-#define DM365_LPSC_VOICE_CODEC 44
-#define DM365_LPSC_DAC_CLK 46
-#define DM365_LPSC_VPSSMSTR 47
-#define DM365_LPSC_MJCP 50
-
-/*
- * LPSC Assignments
- */
-#define DM646X_LPSC_ARM 0
-#define DM646X_LPSC_C64X_CPU 1
-#define DM646X_LPSC_HDVICP0 2
-#define DM646X_LPSC_HDVICP1 3
-#define DM646X_LPSC_TPCC 4
-#define DM646X_LPSC_TPTC0 5
-#define DM646X_LPSC_TPTC1 6
-#define DM646X_LPSC_TPTC2 7
-#define DM646X_LPSC_TPTC3 8
-#define DM646X_LPSC_PCI 13
-#define DM646X_LPSC_EMAC 14
-#define DM646X_LPSC_VDCE 15
-#define DM646X_LPSC_VPSSMSTR 16
-#define DM646X_LPSC_VPSSSLV 17
-#define DM646X_LPSC_TSIF0 18
-#define DM646X_LPSC_TSIF1 19
-#define DM646X_LPSC_DDR_EMIF 20
-#define DM646X_LPSC_AEMIF 21
-#define DM646X_LPSC_McASP0 22
-#define DM646X_LPSC_McASP1 23
-#define DM646X_LPSC_CRGEN0 24
-#define DM646X_LPSC_CRGEN1 25
-#define DM646X_LPSC_UART0 26
-#define DM646X_LPSC_UART1 27
-#define DM646X_LPSC_UART2 28
-#define DM646X_LPSC_PWM0 29
-#define DM646X_LPSC_PWM1 30
-#define DM646X_LPSC_I2C 31
-#define DM646X_LPSC_SPI 32
-#define DM646X_LPSC_GPIO 33
-#define DM646X_LPSC_TIMER0 34
-#define DM646X_LPSC_TIMER1 35
-#define DM646X_LPSC_ARM_INTC 45
-
/* PSC0 defines */
#define DA8XX_LPSC0_TPCC 0
#define DA8XX_LPSC0_TPTC0 1
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
deleted file mode 100644
index 127b62ce7b1e..000000000000
--- a/arch/arm/mach-davinci/serial.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * TI DaVinci serial driver
- *
- * Copyright (C) 2006 Texas Instruments.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/serial.h>
-#include <mach/cputype.h>
-
-static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
- int value)
-{
- offset <<= p->regshift;
-
- WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
-
- __raw_writel(value, p->membase + offset);
-}
-
-static void __init davinci_serial_reset(struct plat_serial8250_port *p)
-{
- unsigned int pwremu = 0;
-
- serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
-
- /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
- serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
- mdelay(10);
-
- pwremu |= (0x3 << 13);
- pwremu |= 0x1;
- serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
-
- if (cpu_is_davinci_dm646x())
- serial_write_reg(p, UART_DM646X_SCR,
- UART_DM646X_SCR_TX_WATERMARK);
-}
-
-int __init davinci_serial_init(struct platform_device *serial_dev)
-{
- int i, ret = 0;
- struct device *dev;
- struct plat_serial8250_port *p;
- struct clk *clk;
-
- /*
- * Make sure the serial ports are muxed on at this point.
- * You have to mux them off in device drivers later on if not needed.
- */
- for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
- dev = &serial_dev[i].dev;
- p = dev->platform_data;
-
- ret = platform_device_register(&serial_dev[i]);
- if (ret)
- continue;
-
- clk = clk_get(dev, NULL);
- if (IS_ERR(clk)) {
- pr_err("%s:%d: failed to get UART%d clock\n",
- __func__, __LINE__, i);
- continue;
- }
-
- clk_prepare_enable(clk);
-
- p->uartclk = clk_get_rate(clk);
-
- if (!p->membase && p->mapbase) {
- p->membase = ioremap(p->mapbase, SZ_4K);
-
- if (p->membase)
- p->flags &= ~UPF_IOREMAP;
- else
- pr_err("uart regs ioremap failed\n");
- }
-
- if (p->membase && p->type != PORT_AR7)
- davinci_serial_reset(p);
- }
- return ret;
-}
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index bbae190fd82c..d04f39fc84b6 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -9,7 +9,7 @@
#include <linux/io.h>
#include <linux/genalloc.h>
-#include <mach/common.h>
+#include "common.h"
#include "sram.h"
static struct gen_pool *sram_pool;
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
deleted file mode 100644
index 25f21ee86f1a..000000000000
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ /dev/null
@@ -1,147 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * DA8xx USB
- */
-#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/mfd/da8xx-cfgchip.h>
-#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_data/clk-da8xx-cfgchip.h>
-#include <linux/platform_data/phy-da8xx-usb.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/platform_device.h>
-#include <linux/usb/musb.h>
-
-#include <mach/common.h>
-#include <mach/cputype.h>
-#include <mach/da8xx.h>
-
-#include "irqs.h"
-
-#define DA8XX_USB0_BASE 0x01e00000
-#define DA8XX_USB1_BASE 0x01e25000
-
-#ifndef CONFIG_COMMON_CLK
-static struct clk *usb20_clk;
-#endif
-
-static struct da8xx_usb_phy_platform_data da8xx_usb_phy_pdata;
-
-static struct platform_device da8xx_usb_phy = {
- .name = "da8xx-usb-phy",
- .id = -1,
- .dev = {
- /*
- * Setting init_name so that clock lookup will work in
- * da8xx_register_usb11_phy_clk() even if this device is not
- * registered yet.
- */
- .init_name = "da8xx-usb-phy",
- .platform_data = &da8xx_usb_phy_pdata,
- },
-};
-
-int __init da8xx_register_usb_phy(void)
-{
- da8xx_usb_phy_pdata.cfgchip = da8xx_get_cfgchip();
-
- return platform_device_register(&da8xx_usb_phy);
-}
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = true,
- .num_eps = 5,
- .ram_bits = 10,
-};
-
-static struct musb_hdrc_platform_data usb_data = {
- /* OTG requires a Mini-AB connector */
- .mode = MUSB_OTG,
- .clock = "usb20",
- .config = &musb_config,
-};
-
-static struct resource da8xx_usb20_resources[] = {
- {
- .start = DA8XX_USB0_BASE,
- .end = DA8XX_USB0_BASE + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_USB_INT),
- .flags = IORESOURCE_IRQ,
- .name = "mc",
- },
-};
-
-static u64 usb_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device da8xx_usb20_dev = {
- .name = "musb-da8xx",
- .id = -1,
- .dev = {
- .platform_data = &usb_data,
- .dma_mask = &usb_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = da8xx_usb20_resources,
- .num_resources = ARRAY_SIZE(da8xx_usb20_resources),
-};
-
-int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
-{
- usb_data.power = mA > 510 ? 255 : mA / 2;
- usb_data.potpgt = (potpgt + 1) / 2;
-
- return platform_device_register(&da8xx_usb20_dev);
-}
-
-static struct resource da8xx_usb11_resources[] = {
- [0] = {
- .start = DA8XX_USB1_BASE,
- .end = DA8XX_USB1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
- .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device da8xx_usb11_device = {
- .name = "ohci-da8xx",
- .id = -1,
- .dev = {
- .dma_mask = &da8xx_usb11_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(da8xx_usb11_resources),
- .resource = da8xx_usb11_resources,
-};
-
-int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
-{
- da8xx_usb11_device.dev.platform_data = pdata;
- return platform_device_register(&da8xx_usb11_device);
-}
-
-static struct platform_device da8xx_usb_phy_clks_device = {
- .name = "da830-usb-phy-clks",
- .id = -1,
-};
-
-int __init da8xx_register_usb_phy_clocks(void)
-{
- struct da8xx_cfgchip_clk_platform_data pdata;
-
- pdata.cfgchip = da8xx_get_cfgchip();
- da8xx_usb_phy_clks_device.dev.platform_data = &pdata;
-
- return platform_device_register(&da8xx_usb_phy_clks_device);
-}
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
deleted file mode 100644
index dd8db61cdd1c..000000000000
--- a/arch/arm/mach-davinci/usb.c
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * USB
- */
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/usb-davinci.h>
-#include <linux/usb/musb.h>
-
-#include <mach/common.h>
-#include <mach/cputype.h>
-
-#include "irqs.h"
-
-#define DAVINCI_USB_OTG_BASE 0x01c64000
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct musb_hdrc_config musb_config = {
- .multipoint = true,
-
- .num_eps = 5,
- .ram_bits = 10,
-};
-
-static struct musb_hdrc_platform_data usb_data = {
- /* OTG requires a Mini-AB connector */
- .mode = MUSB_OTG,
- .clock = "usb",
- .config = &musb_config,
-};
-
-static struct resource usb_resources[] = {
- {
- /* physical address */
- .start = DAVINCI_USB_OTG_BASE,
- .end = DAVINCI_USB_OTG_BASE + 0x5ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = DAVINCI_INTC_IRQ(IRQ_USBINT),
- .flags = IORESOURCE_IRQ,
- .name = "mc"
- },
- {
- /* placeholder for the dedicated CPPI IRQ */
- .flags = IORESOURCE_IRQ,
- .name = "dma"
- },
-};
-
-static u64 usb_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device usb_dev = {
- .name = "musb-davinci",
- .id = -1,
- .dev = {
- .platform_data = &usb_data,
- .dma_mask = &usb_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = usb_resources,
- .num_resources = ARRAY_SIZE(usb_resources),
-};
-
-void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
-{
- usb_data.power = mA > 510 ? 255 : mA / 2;
- usb_data.potpgt = (potpgt_ms + 1) / 2;
-
- if (cpu_is_davinci_dm646x()) {
- /* Override the defaults as DM6467 uses different IRQs. */
- usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT);
- usb_dev.resource[2].start = DAVINCI_INTC_IRQ(
- IRQ_DM646X_USBDMAINT);
- } else /* other devices don't have dedicated CPPI IRQ */
- usb_dev.num_resources = 2;
-
- platform_device_register(&usb_dev);
-}
-
-#else
-
-void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
-{
-}
-
-#endif /* CONFIG_USB_MUSB_HDRC */
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 7747fe64420a..996888ffcfe7 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -1,19 +1,23 @@
# SPDX-License-Identifier: GPL-2.0
-if ARCH_DOVE
+menuconfig ARCH_DOVE
+ bool "Marvell Dove" if ARCH_MULTI_V7
+ depends on ATAGS
+ select CPU_PJ4
+ select GPIOLIB
+ select MVEBU_MBUS
+ select PINCTRL
+ select PINCTRL_DOVE
+ select PLAT_ORION_LEGACY
+ select PM_GENERIC_DOMAINS if PM
+ select PCI_QUIRKS if PCI
+ help
+ Support for the Marvell Dove SoC 88AP510
-menu "Marvell Dove Implementations"
+if ARCH_DOVE
config DOVE_LEGACY
bool
-config MACH_DOVE_DB
- bool "Marvell DB-MV88AP510 Development Board"
- select DOVE_LEGACY
- select I2C_BOARDINFO if I2C
- help
- Say 'Y' here if you want your kernel to support the
- Marvell DB-MV88AP510 Development Board.
-
config MACH_CM_A510
bool "CompuLab CM-A510 Board"
select DOVE_LEGACY
@@ -21,6 +25,4 @@ config MACH_CM_A510
Say 'Y' here if you want your kernel to support the
CompuLab CM-A510 Board.
-endmenu
-
endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index cdf163cab738..0d31390be069 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
+ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
+
obj-y += common.o
obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o
obj-$(CONFIG_PCI) += pcie.o
-obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
deleted file mode 100644
index e4dd1d26038f..000000000000
--- a/arch/arm/mach-dove/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
- zreladdr-y += 0x00008000
-params_phys-y := 0x00000100
-initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-dove/bridge-regs.h b/arch/arm/mach-dove/bridge-regs.h
index ace0b0bfbf11..6fbc152d0950 100644
--- a/arch/arm/mach-dove/bridge-regs.h
+++ b/arch/arm/mach-dove/bridge-regs.h
@@ -1,10 +1,5 @@
-/*
- * Mbus-L to Mbus Bridge Registers
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Mbus-L to Mbus Bridge Registers */
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 9f25c993d863..beb532537c22 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-dove/cm-a510.c
*
@@ -5,10 +6,6 @@
* Konstantin Sinyuk <kostyas@compulab.co.il>
*
* Based on Marvell DB-MV88AP510-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index dbe970e37895..cd4ae7e4768d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-dove/common.c
*
* Core functions for Marvell Dove 88AP510 System On Chip
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/clk-provider.h>
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 1d725224d146..57ebc413d68c 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-dove/common.h
*
* Core functions for Marvell Dove 88AP510 System On Chip
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __ARCH_DOVE_COMMON_H
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
deleted file mode 100644
index 418ab21b9d9b..000000000000
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * arch/arm/mach-dove/dove-db-setup.c
- *
- * Marvell DB-MV88AP510-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/timer.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/pci.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "dove.h"
-#include "common.h"
-
-static struct mv643xx_eth_platform_data dove_db_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
-};
-
-static struct mv_sata_platform_data dove_db_sata_data = {
- .n_ports = 1,
-};
-
-/*****************************************************************************
- * SPI Devices:
- * SPI0: 4M Flash ST-M25P32-VMF6P
- ****************************************************************************/
-static const struct flash_platform_data dove_db_spi_flash_data = {
- .type = "m25p64",
-};
-
-static struct spi_board_info __initdata dove_db_spi_flash_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &dove_db_spi_flash_data,
- .irq = -1,
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-/*****************************************************************************
- * PCI
- ****************************************************************************/
-static int __init dove_db_pci_init(void)
-{
- if (machine_is_dove_db())
- dove_pcie_init(1, 1);
-
- return 0;
-}
-
-subsys_initcall(dove_db_pci_init);
-
-/*****************************************************************************
- * Board Init
- ****************************************************************************/
-static void __init dove_db_init(void)
-{
- /*
- * Basic Dove setup. Needs to be called early.
- */
- dove_init();
-
- dove_ge00_init(&dove_db_ge00_data);
- dove_ehci0_init();
- dove_ehci1_init();
- dove_sata_init(&dove_db_sata_data);
- dove_sdio0_init();
- dove_sdio1_init();
- dove_spi0_init();
- dove_spi1_init();
- dove_uart0_init();
- dove_uart1_init();
- dove_i2c_init();
- spi_register_board_info(dove_db_spi_flash_info,
- ARRAY_SIZE(dove_db_spi_flash_info));
-}
-
-MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
- .atag_offset = 0x100,
- .nr_irqs = DOVE_NR_IRQS,
- .init_machine = dove_db_init,
- .map_io = dove_map_io,
- .init_early = dove_init_early,
- .init_irq = dove_init_irq,
- .init_time = dove_timer_init,
- .restart = dove_restart,
-MACHINE_END
diff --git a/arch/arm/mach-dove/dove.h b/arch/arm/mach-dove/dove.h
index 320ed1696abd..e5054e3b0b78 100644
--- a/arch/arm/mach-dove/dove.h
+++ b/arch/arm/mach-dove/dove.h
@@ -1,10 +1,5 @@
-/*
- * Generic definitions for Marvell Dove 88AP510 SoC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Generic definitions for Marvell Dove 88AP510 SoC */
#ifndef __ASM_ARCH_DOVE_H
#define __ASM_ARCH_DOVE_H
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h
deleted file mode 100644
index ddf873f35e2b..000000000000
--- a/arch/arm/mach-dove/include/mach/uncompress.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define UART0_PHYS_BASE (0xf1000000 + 0x12000)
-
-#define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
-#define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
-
-#define LSR_THRE 0x20
-
-static inline void putc(const char c)
-{
- int i;
-
- for (i = 0; i < 0x1000; i++) {
- /* Transmit fifo not full? */
- if (*UART_LSR & LSR_THRE)
- break;
- }
-
- *UART_THR = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index d36f6b8269c2..027a8f87bc2e 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-dove/irq.c
*
* Dove IRQ handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/irq.h>
diff --git a/arch/arm/mach-dove/irqs.h b/arch/arm/mach-dove/irqs.h
index a0742179faff..5467098c7042 100644
--- a/arch/arm/mach-dove/irqs.h
+++ b/arch/arm/mach-dove/irqs.h
@@ -1,10 +1,5 @@
-/*
- * IRQ definitions for Marvell Dove 88AP510 SoC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* IRQ definitions for Marvell Dove 88AP510 SoC */
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 6acd8488bb05..93cb137da5f8 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-dove/mpp.c
*
* MPP functions for Marvell Dove SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 2a493bdfffc6..3044b7e03890 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-dove/pcie.c
*
* PCIe functions for Marvell Dove 88AP510 SoC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
@@ -136,18 +133,23 @@ static struct pci_ops pcie_ops = {
.write = pcie_wr_conf,
};
+/*
+ * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
+ * is operating as a root complex this needs to be switched to
+ * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
+ * the device. Decoding setup is handled by the orion code.
+ */
static void rc_pci_fixup(struct pci_dev *dev)
{
- /*
- * Prevent enumeration of root complex.
- */
if (dev->bus->parent == NULL && dev->devfn == 0) {
- int i;
-
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
+ struct resource *r;
+
+ dev->class &= 0xff;
+ dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
+ pci_dev_for_each_resource(dev, r) {
+ r->start = 0;
+ r->end = 0;
+ r->flags = 0;
}
}
}
diff --git a/arch/arm/mach-dove/pm.h b/arch/arm/mach-dove/pm.h
index 01267746d707..a4c3aba1e2d0 100644
--- a/arch/arm/mach-dove/pm.h
+++ b/arch/arm/mach-dove/pm.h
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ASM_ARCH_PM_H
#define __ASM_ARCH_PM_H
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 15c68a646d51..703f3d232a60 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -1,4 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only
+menuconfig ARCH_EP93XX
+ bool "EP93xx-based"
+ depends on ATAGS
+ depends on ARCH_MULTI_V4T
+ depends on CPU_LITTLE_ENDIAN
+ select ARCH_SPARSEMEM_ENABLE
+ select ARM_AMBA
+ select ARM_VIC
+ select CLKSRC_MMIO
+ select CPU_ARM920T
+ select GPIOLIB
+ help
+ This enables support for the Cirrus EP93xx series of CPUs.
+
if ARCH_EP93XX
menu "Cirrus EP93xx Implementation Options"
@@ -11,12 +25,6 @@ config EP93XX_SOC_COMMON
comment "EP93xx Platforms"
-config MACH_ADSSPHERE
- bool "Support ADS Sphere"
- help
- Say 'Y' here if you want your kernel to support the ADS
- Sphere board.
-
config MACH_BK3
bool "Support Liebherr BK3.1"
select MACH_TS72XX
@@ -83,55 +91,6 @@ config MACH_EDB9315A
Say 'Y' here if you want your kernel to support the Cirrus
Logic EDB9315A Evaluation Board.
-config MACH_GESBC9312
- bool "Support Glomation GESBC-9312-sx"
- help
- Say 'Y' here if you want your kernel to support the Glomation
- GESBC-9312-sx board.
-
-config MACH_MICRO9
- bool
-
-config MACH_MICRO9H
- bool "Support Contec Micro9-High"
- select MACH_MICRO9
- help
- Say 'Y' here if you want your kernel to support the
- Contec Micro9-High board.
-
-config MACH_MICRO9M
- bool "Support Contec Micro9-Mid"
- select MACH_MICRO9
- help
- Say 'Y' here if you want your kernel to support the
- Contec Micro9-Mid board.
-
-config MACH_MICRO9L
- bool "Support Contec Micro9-Lite"
- select MACH_MICRO9
- help
- Say 'Y' here if you want your kernel to support the
- Contec Micro9-Lite board.
-
-config MACH_MICRO9S
- bool "Support Contec Micro9-Slim"
- select MACH_MICRO9
- help
- Say 'Y' here if you want your kernel to support the
- Contec Micro9-Slim board.
-
-config MACH_SIM_ONE
- bool "Support Simplemachines Sim.One board"
- help
- Say 'Y' here if you want your kernel to support the
- Simplemachines Sim.One board.
-
-config MACH_SNAPPER_CL15
- bool "Support Bluewater Systems Snapper CL15 Module"
- help
- Say 'Y' here if you want your kernel to support the Bluewater
- Systems Snapper CL15 Module.
-
config MACH_TS72XX
bool "Support Technologic Systems TS-72xx SBC"
help
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index cfad517fac46..62e37403df14 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -6,11 +6,6 @@ obj-y := core.o clock.o timer-ep93xx.o
obj-$(CONFIG_EP93XX_DMA) += dma.o
-obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o
obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o
-obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o
-obj-$(CONFIG_MACH_MICRO9) += micro9.o
-obj-$(CONFIG_MACH_SIM_ONE) += simone.o
-obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o
obj-$(CONFIG_MACH_TS72XX) += ts72xx.o
obj-$(CONFIG_MACH_VISION_EP9307)+= vision_ep9307.o
diff --git a/arch/arm/mach-ep93xx/Makefile.boot b/arch/arm/mach-ep93xx/Makefile.boot
deleted file mode 100644
index 4c0a039a5027..000000000000
--- a/arch/arm/mach-ep93xx/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-# Empty file waiting for deletion once Makefile.boot isn't needed any more.
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
deleted file mode 100644
index 8d5e349a7a6d..000000000000
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-ep93xx/adssphere.c
- * ADS Sphere support.
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/sizes.h>
-
-#include "hardware.h"
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "soc.h"
-
-static struct ep93xx_eth_data __initdata adssphere_eth_data = {
- .phy_id = 1,
-};
-
-static void __init adssphere_init_machine(void)
-{
- ep93xx_init_devices();
- ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
- ep93xx_register_eth(&adssphere_eth_data, 1);
-}
-
-MACHINE_START(ADSSPHERE, "ADS Sphere board")
- /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = adssphere_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index cc75087134d3..85a496ddc619 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -148,8 +148,10 @@ static struct clk_hw *ep93xx_clk_register_gate(const char *name,
psc->lock = &clk_lock;
clk = clk_register(NULL, &psc->hw);
- if (IS_ERR(clk))
+ if (IS_ERR(clk)) {
kfree(psc);
+ return ERR_CAST(clk);
+ }
return &psc->hw;
}
@@ -207,7 +209,7 @@ static int ep93xx_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned long rate = req->rate;
- struct clk *best_parent = 0;
+ struct clk *best_parent = NULL;
unsigned long __parent_rate;
unsigned long best_rate = 0, actual_rate, mclk_rate;
unsigned long best_parent_rate;
@@ -343,9 +345,10 @@ static struct clk_hw *clk_hw_register_ddiv(const char *name,
psc->hw.init = &init;
clk = clk_register(NULL, &psc->hw);
- if (IS_ERR(clk))
+ if (IS_ERR(clk)) {
kfree(psc);
-
+ return ERR_CAST(clk);
+ }
return &psc->hw;
}
@@ -450,9 +453,10 @@ static struct clk_hw *clk_hw_register_div(const char *name,
psc->hw.init = &init;
clk = clk_register(NULL, &psc->hw);
- if (IS_ERR(clk))
+ if (IS_ERR(clk)) {
kfree(psc);
-
+ return ERR_CAST(clk);
+ }
return &psc->hw;
}
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index a3b4e843456a..71b113976420 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/leds.h>
+#include <linux/uaccess.h>
#include <linux/termios.h>
#include <linux/amba/bus.h>
#include <linux/amba/serial.h>
@@ -47,6 +48,7 @@
#include <asm/mach/map.h>
#include "soc.h"
+#include "irqs.h"
/*************************************************************************
* Static I/O mappings that are needed for all EP93xx platforms
@@ -75,8 +77,8 @@ void __init ep93xx_map_io(void)
*************************************************************************/
void __init ep93xx_init_irq(void)
{
- vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
- vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
+ vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
+ vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0);
}
@@ -424,10 +426,8 @@ void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
static const struct gpio_led ep93xx_led_pins[] __initconst = {
{
.name = "platform:grled",
- .gpio = EP93XX_GPIO_LINE_GRLED,
}, {
.name = "platform:rdled",
- .gpio = EP93XX_GPIO_LINE_RDLED,
},
};
@@ -436,6 +436,16 @@ static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
.leds = ep93xx_led_pins,
};
+static struct gpiod_lookup_table ep93xx_leds_gpio_table = {
+ .dev_id = "leds-gpio",
+ .table = {
+ /* Use local offsets on gpiochip/port "E" */
+ GPIO_LOOKUP_IDX("E", 0, NULL, 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("E", 1, NULL, 1, GPIO_ACTIVE_HIGH),
+ { }
+ },
+};
+
/*************************************************************************
* EP93xx pwm peripheral handling
*************************************************************************/
@@ -988,6 +998,7 @@ struct device __init *ep93xx_init_devices(void)
platform_device_register(&ep93xx_ohci_device);
platform_device_register(&ep93xx_wdt_device);
+ gpiod_add_lookup_table(&ep93xx_leds_gpio_table);
gpio_led_register_device(-1, &ep93xx_led_data);
return parent;
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index af0e22471ebd..4b90899a66e9 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -243,6 +243,7 @@ static void __init edb93xx_init_machine(void)
MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -255,6 +256,7 @@ MACHINE_END
MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
/* Maintainer: George Kashperko <george@chas.com.ua> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -267,6 +269,7 @@ MACHINE_END
MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -279,6 +282,7 @@ MACHINE_END
MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -291,6 +295,7 @@ MACHINE_END
MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -303,6 +308,7 @@ MACHINE_END
MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
/* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -315,6 +321,7 @@ MACHINE_END
MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -327,6 +334,7 @@ MACHINE_END
MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/ep93xx-regs.h
index 6839ea032e58..8fa3646de0a4 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/ep93xx-regs.h
@@ -1,8 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
- */
-
#ifndef __ASM_ARCH_EP93XX_REGS_H
#define __ASM_ARCH_EP93XX_REGS_H
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
deleted file mode 100644
index d7f9890321eb..000000000000
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-ep93xx/gesbc9312.c
- * Glomation GESBC-9312-sx support.
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/sizes.h>
-
-#include "hardware.h"
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "soc.h"
-
-static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
- .phy_id = 1,
-};
-
-static void __init gesbc9312_init_machine(void)
-{
- ep93xx_init_devices();
- ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
- ep93xx_register_eth(&gesbc9312_eth_data, 0);
-}
-
-MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
- /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = gesbc9312_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio-ep93xx.h
index 242af4a401ea..7b46eb7e5507 100644
--- a/arch/arm/mach-ep93xx/gpio-ep93xx.h
+++ b/arch/arm/mach-ep93xx/gpio-ep93xx.h
@@ -4,7 +4,7 @@
#ifndef __GPIO_EP93XX_H
#define __GPIO_EP93XX_H
-#include <mach/ep93xx-regs.h>
+#include "ep93xx-regs.h"
#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
diff --git a/arch/arm/mach-ep93xx/include/mach/irqs.h b/arch/arm/mach-ep93xx/include/mach/irqs.h
deleted file mode 100644
index 244daf83ce6d..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/irqs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-ep93xx/include/mach/irqs.h
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define IRQ_EP93XX_COMMRX 2
-#define IRQ_EP93XX_COMMTX 3
-#define IRQ_EP93XX_TIMER1 4
-#define IRQ_EP93XX_TIMER2 5
-#define IRQ_EP93XX_AACINTR 6
-#define IRQ_EP93XX_DMAM2P0 7
-#define IRQ_EP93XX_DMAM2P1 8
-#define IRQ_EP93XX_DMAM2P2 9
-#define IRQ_EP93XX_DMAM2P3 10
-#define IRQ_EP93XX_DMAM2P4 11
-#define IRQ_EP93XX_DMAM2P5 12
-#define IRQ_EP93XX_DMAM2P6 13
-#define IRQ_EP93XX_DMAM2P7 14
-#define IRQ_EP93XX_DMAM2P8 15
-#define IRQ_EP93XX_DMAM2P9 16
-#define IRQ_EP93XX_DMAM2M0 17
-#define IRQ_EP93XX_DMAM2M1 18
-#define IRQ_EP93XX_GPIO0MUX 19
-#define IRQ_EP93XX_GPIO1MUX 20
-#define IRQ_EP93XX_GPIO2MUX 21
-#define IRQ_EP93XX_GPIO3MUX 22
-#define IRQ_EP93XX_UART1RX 23
-#define IRQ_EP93XX_UART1TX 24
-#define IRQ_EP93XX_UART2RX 25
-#define IRQ_EP93XX_UART2TX 26
-#define IRQ_EP93XX_UART3RX 27
-#define IRQ_EP93XX_UART3TX 28
-#define IRQ_EP93XX_KEY 29
-#define IRQ_EP93XX_TOUCH 30
-#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
-
-#define IRQ_EP93XX_EXT0 32
-#define IRQ_EP93XX_EXT1 33
-#define IRQ_EP93XX_EXT2 34
-#define IRQ_EP93XX_64HZ 35
-#define IRQ_EP93XX_WATCHDOG 36
-#define IRQ_EP93XX_RTC 37
-#define IRQ_EP93XX_IRDA 38
-#define IRQ_EP93XX_ETHERNET 39
-#define IRQ_EP93XX_EXT3 40
-#define IRQ_EP93XX_PROG 41
-#define IRQ_EP93XX_1HZ 42
-#define IRQ_EP93XX_VSYNC 43
-#define IRQ_EP93XX_VIDEO_FIFO 44
-#define IRQ_EP93XX_SSP1RX 45
-#define IRQ_EP93XX_SSP1TX 46
-#define IRQ_EP93XX_GPIO4MUX 47
-#define IRQ_EP93XX_GPIO5MUX 48
-#define IRQ_EP93XX_GPIO6MUX 49
-#define IRQ_EP93XX_GPIO7MUX 50
-#define IRQ_EP93XX_TIMER3 51
-#define IRQ_EP93XX_UART1 52
-#define IRQ_EP93XX_SSP 53
-#define IRQ_EP93XX_UART2 54
-#define IRQ_EP93XX_UART3 55
-#define IRQ_EP93XX_USB 56
-#define IRQ_EP93XX_ETHERNET_PME 57
-#define IRQ_EP93XX_DSP 58
-#define IRQ_EP93XX_GPIO_AB 59
-#define IRQ_EP93XX_SAI 60
-#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
-
-#define NR_EP93XX_IRQS (64 + 24)
-
-#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
-#define EP93XX_BOARD_IRQS 32
-
-#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS)
-
-
-#endif
diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h
new file mode 100644
index 000000000000..353201b90c66
--- /dev/null
+++ b/arch/arm/mach-ep93xx/irqs.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define IRQ_EP93XX_VIC0 1
+
+#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2)
+#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3)
+#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4)
+#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5)
+#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6)
+#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7)
+#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8)
+#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9)
+#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10)
+#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11)
+#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12)
+#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13)
+#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14)
+#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15)
+#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16)
+#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17)
+#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18)
+#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19)
+#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20)
+#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21)
+#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22)
+#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23)
+#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24)
+#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25)
+#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26)
+#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27)
+#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28)
+#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29)
+#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30)
+#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
+
+#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32)
+
+#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0)
+#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1)
+#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2)
+#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3)
+#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4)
+#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5)
+#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6)
+#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7)
+#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8)
+#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9)
+#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10)
+#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11)
+#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12)
+#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13)
+#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14)
+#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15)
+#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16)
+#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17)
+#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18)
+#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19)
+#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20)
+#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21)
+#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22)
+#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23)
+#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24)
+#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25)
+#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26)
+#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27)
+#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28)
+#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
+
+#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24)
+
+#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
+#define EP93XX_BOARD_IRQS 32
+
+#endif
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
deleted file mode 100644
index e6ead8ded6ee..000000000000
--- a/arch/arm/mach-ep93xx/micro9.c
+++ /dev/null
@@ -1,121 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-ep93xx/micro9.c
- *
- * Copyright (C) 2006 Contec Steuerungstechnik & Automation GmbH
- * Manfred Gruber <m.gruber@tirol.com>
- * Copyright (C) 2009 Contec Steuerungstechnik & Automation GmbH
- * Hubert Feurstein <hubert.feurstein@contec.at>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include "hardware.h"
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "soc.h"
-
-/*************************************************************************
- * Micro9 NOR Flash
- *
- * Micro9-High has up to 64MB of 32-bit flash on CS1
- * Micro9-Mid has up to 64MB of either 32-bit or 16-bit flash on CS1
- * Micro9-Lite uses a separate MTD map driver for flash support
- * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
- *************************************************************************/
-static unsigned int __init micro9_detect_bootwidth(void)
-{
- u32 v;
-
- /* Detect the bus width of the external flash memory */
- v = __raw_readl(EP93XX_SYSCON_SYSCFG);
- if (v & EP93XX_SYSCON_SYSCFG_LCSN7)
- return 4; /* 32-bit */
- else
- return 2; /* 16-bit */
-}
-
-static void __init micro9_register_flash(void)
-{
- unsigned int width;
-
- if (machine_is_micro9())
- width = 4;
- else if (machine_is_micro9m() || machine_is_micro9s())
- width = micro9_detect_bootwidth();
- else
- width = 0;
-
- if (width)
- ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
-}
-
-
-/*************************************************************************
- * Micro9 Ethernet
- *************************************************************************/
-static struct ep93xx_eth_data __initdata micro9_eth_data = {
- .phy_id = 0x1f,
-};
-
-
-static void __init micro9_init_machine(void)
-{
- ep93xx_init_devices();
- ep93xx_register_eth(&micro9_eth_data, 1);
- micro9_register_flash();
-}
-
-
-#ifdef CONFIG_MACH_MICRO9H
-MACHINE_START(MICRO9, "Contec Micro9-High")
- /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = micro9_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_MICRO9M
-MACHINE_START(MICRO9M, "Contec Micro9-Mid")
- /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = micro9_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_MICRO9L
-MACHINE_START(MICRO9L, "Contec Micro9-Lite")
- /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = micro9_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_MICRO9S
-MACHINE_START(MICRO9S, "Contec Micro9-Slim")
- /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = micro9_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
deleted file mode 100644
index 5291053023b2..000000000000
--- a/arch/arm/mach-ep93xx/simone.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-ep93xx/simone.c
- * Simplemachines Sim.One support.
- *
- * Copyright (C) 2010 Ryan Mallon
- *
- * Based on the 2.6.24.7 support:
- * Copyright (C) 2009 Simplemachines
- * MMC support by Peter Ivanov <ivanovp@gmail.com>, 2007
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/mmc/host.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/platform_data/video-ep93xx.h>
-#include <linux/platform_data/spi-ep93xx.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-
-#include "hardware.h"
-#include "gpio-ep93xx.h"
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "soc.h"
-
-static struct ep93xx_eth_data __initdata simone_eth_data = {
- .phy_id = 1,
-};
-
-static struct ep93xxfb_mach_info __initdata simone_fb_info = {
- .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
-};
-
-static struct mmc_spi_platform_data simone_mmc_spi_data = {
- .detect_delay = 500,
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table simone_mmc_spi_gpio_table = {
- .dev_id = "mmc_spi.0", /* "mmc_spi" @ CS0 */
- .table = {
- /* Card detect */
- GPIO_LOOKUP_IDX("A", 0, NULL, 0, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct spi_board_info simone_spi_devices[] __initdata = {
- {
- .modalias = "mmc_spi",
- .platform_data = &simone_mmc_spi_data,
- /*
- * We use 10 MHz even though the maximum is 3.7 MHz. The driver
- * will limit it automatically to max. frequency.
- */
- .max_speed_hz = 10 * 1000 * 1000,
- .bus_num = 0,
- .chip_select = 0,
- .mode = SPI_MODE_3,
- },
-};
-
-/*
- * Up to v1.3, the Sim.One used SFRMOUT as SD card chip select, but this goes
- * low between multi-message command blocks. From v1.4, it uses a GPIO instead.
- * v1.3 parts will still work, since the signal on SFRMOUT is automatic.
- */
-static struct gpiod_lookup_table simone_spi_cs_gpio_table = {
- .dev_id = "spi0",
- .table = {
- GPIO_LOOKUP("A", 1, "cs", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct ep93xx_spi_info simone_spi_info __initdata = {
- .use_dma = 1,
-};
-
-static struct i2c_board_info __initdata simone_i2c_board_info[] = {
- {
- I2C_BOARD_INFO("ds1337", 0x68),
- },
-};
-
-static struct platform_device simone_audio_device = {
- .name = "simone-audio",
- .id = -1,
-};
-
-static void __init simone_register_audio(void)
-{
- ep93xx_register_ac97();
- platform_device_register(&simone_audio_device);
-}
-
-static void __init simone_init_machine(void)
-{
- ep93xx_init_devices();
- ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
- ep93xx_register_eth(&simone_eth_data, 1);
- ep93xx_register_fb(&simone_fb_info);
- ep93xx_register_i2c(simone_i2c_board_info,
- ARRAY_SIZE(simone_i2c_board_info));
- gpiod_add_lookup_table(&simone_mmc_spi_gpio_table);
- gpiod_add_lookup_table(&simone_spi_cs_gpio_table);
- ep93xx_register_spi(&simone_spi_info, simone_spi_devices,
- ARRAY_SIZE(simone_spi_devices));
- simone_register_audio();
-}
-
-MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
- /* Maintainer: Ryan Mallon */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = simone_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
deleted file mode 100644
index e200d69471e9..000000000000
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-ep93xx/snappercl15.c
- * Bluewater Systems Snapper CL15 system module
- *
- * Copyright (C) 2009 Bluewater Systems Ltd
- * Author: Ryan Mallon
- *
- * NAND code adapted from driver by:
- * Andre Renaud <andre@bluewatersys.com>
- * James R. McKaskill
- */
-
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/fb.h>
-
-#include <linux/mtd/platnand.h>
-
-#include "hardware.h"
-#include <linux/platform_data/video-ep93xx.h>
-#include "gpio-ep93xx.h"
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "soc.h"
-
-#define SNAPPERCL15_NAND_BASE (EP93XX_CS7_PHYS_BASE + SZ_16M)
-
-#define SNAPPERCL15_NAND_WPN (1 << 8) /* Write protect (active low) */
-#define SNAPPERCL15_NAND_ALE (1 << 9) /* Address latch */
-#define SNAPPERCL15_NAND_CLE (1 << 10) /* Command latch */
-#define SNAPPERCL15_NAND_CEN (1 << 11) /* Chip enable (active low) */
-#define SNAPPERCL15_NAND_RDY (1 << 14) /* Device ready */
-
-#define NAND_CTRL_ADDR(chip) (chip->legacy.IO_ADDR_W + 0x40)
-
-static void snappercl15_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
- unsigned int ctrl)
-{
- static u16 nand_state = SNAPPERCL15_NAND_WPN;
- u16 set;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN;
-
- if (ctrl & NAND_NCE)
- set &= ~SNAPPERCL15_NAND_CEN;
- if (ctrl & NAND_CLE)
- set |= SNAPPERCL15_NAND_CLE;
- if (ctrl & NAND_ALE)
- set |= SNAPPERCL15_NAND_ALE;
-
- nand_state &= ~(SNAPPERCL15_NAND_CEN |
- SNAPPERCL15_NAND_CLE |
- SNAPPERCL15_NAND_ALE);
- nand_state |= set;
- __raw_writew(nand_state, NAND_CTRL_ADDR(chip));
- }
-
- if (cmd != NAND_CMD_NONE)
- __raw_writew((cmd & 0xff) | nand_state,
- chip->legacy.IO_ADDR_W);
-}
-
-static int snappercl15_nand_dev_ready(struct nand_chip *chip)
-{
- return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
-}
-
-static struct mtd_partition snappercl15_nand_parts[] = {
- {
- .name = "Kernel",
- .offset = 0,
- .size = SZ_2M,
- },
- {
- .name = "Filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct platform_nand_data snappercl15_nand_data = {
- .chip = {
- .nr_chips = 1,
- .partitions = snappercl15_nand_parts,
- .nr_partitions = ARRAY_SIZE(snappercl15_nand_parts),
- .chip_delay = 25,
- },
- .ctrl = {
- .dev_ready = snappercl15_nand_dev_ready,
- .cmd_ctrl = snappercl15_nand_cmd_ctrl,
- },
-};
-
-static struct resource snappercl15_nand_resource[] = {
- {
- .start = SNAPPERCL15_NAND_BASE,
- .end = SNAPPERCL15_NAND_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device snappercl15_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .dev.platform_data = &snappercl15_nand_data,
- .resource = snappercl15_nand_resource,
- .num_resources = ARRAY_SIZE(snappercl15_nand_resource),
-};
-
-static struct ep93xx_eth_data __initdata snappercl15_eth_data = {
- .phy_id = 1,
-};
-
-static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
- {
- /* Audio codec */
- I2C_BOARD_INFO("tlv320aic23", 0x1a),
- },
-};
-
-static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = {
-};
-
-static struct platform_device snappercl15_audio_device = {
- .name = "snappercl15-audio",
- .id = -1,
-};
-
-static void __init snappercl15_register_audio(void)
-{
- ep93xx_register_i2s();
- platform_device_register(&snappercl15_audio_device);
-}
-
-static void __init snappercl15_init_machine(void)
-{
- ep93xx_init_devices();
- ep93xx_register_eth(&snappercl15_eth_data, 1);
- ep93xx_register_i2c(snappercl15_i2c_data,
- ARRAY_SIZE(snappercl15_i2c_data));
- ep93xx_register_fb(&snappercl15_fb_info);
- snappercl15_register_audio();
- platform_device_register(&snappercl15_nand_device);
-}
-
-MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
- /* Maintainer: Ryan Mallon */
- .atag_offset = 0x100,
- .map_io = ep93xx_map_io,
- .init_irq = ep93xx_init_irq,
- .init_time = ep93xx_timer_init,
- .init_machine = snappercl15_init_machine,
- .restart = ep93xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index 94ef7f275f94..3245ebbd5069 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -9,7 +9,8 @@
#ifndef _EP93XX_SOC_H
#define _EP93XX_SOC_H
-#include <mach/ep93xx-regs.h>
+#include "ep93xx-regs.h"
+#include "irqs.h"
/*
* EP93xx Physical Memory Map:
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 12eff8c8074d..d3de7283ecb3 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -22,7 +22,6 @@
#include "gpio-ep93xx.h"
#include "hardware.h"
-#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
@@ -151,7 +150,7 @@ static struct platform_device ts72xx_nand_flash = {
.num_resources = ARRAY_SIZE(ts72xx_nand_resource),
};
-void __init ts72xx_register_flash(struct mtd_partition *parts, int n,
+static void __init ts72xx_register_flash(struct mtd_partition *parts, int n,
resource_size_t start)
{
/*
@@ -350,6 +349,7 @@ static void __init ts72xx_init_machine(void)
MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ts72xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -413,6 +413,7 @@ static void __init bk3_init_machine(void)
MACHINE_START(BK3, "Liebherr controller BK3.1")
/* Maintainer: Lukasz Majewski <lukma@denx.de> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS,
.map_io = ts72xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index e46281e60bf7..30d9cf3791eb 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -302,6 +302,7 @@ static void __init vision_init_machine(void)
MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
/* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
.atag_offset = 0x100,
+ .nr_irqs = NR_EP93XX_IRQS + EP93XX_BOARD_IRQS,
.map_io = vision_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f7d993628cb7..4d3b40e4049a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -8,7 +8,6 @@
menuconfig ARCH_EXYNOS
bool "Samsung Exynos"
depends on ARCH_MULTI_V7
- select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_GIC
select EXYNOS_IRQ_COMBINER
@@ -17,7 +16,6 @@ menuconfig ARCH_EXYNOS
select EXYNOS_PMU
select EXYNOS_SROM
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
- select GPIOLIB
select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
select HAVE_ARM_SCU if SMP
select PINCTRL
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 8b48326be9fd..966a0995e047 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -50,11 +50,13 @@ void __init exynos_sysram_init(void)
struct device_node *node;
for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
+ struct resource res;
if (!of_device_is_available(node))
continue;
- sysram_base_addr = of_iomap(node, 0);
- sysram_base_phys = of_translate_address(node,
- of_get_address(node, 0, NULL, NULL));
+
+ of_address_to_resource(node, 0, &res);
+ sysram_base_addr = ioremap(res.start, resource_size(&res));
+ sysram_base_phys = res.start;
of_node_put(node);
break;
}
@@ -149,6 +151,7 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
+ of_node_put(np);
}
static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 3bf14ca78b62..6d5d7696aaf7 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -667,7 +667,7 @@ void __init exynos_pm_init(void)
return;
}
- if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
+ if (WARN_ON(!of_property_read_bool(np, "interrupt-controller"))) {
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
of_node_put(np);
return;
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index 728aff93fba9..78189997caa1 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -1,37 +1,25 @@
# SPDX-License-Identifier: GPL-2.0-only
-if ARCH_FOOTBRIDGE
-
-menu "Footbridge Implementations"
-
-config ARCH_CATS
- bool "CATS"
- select CLKEVT_I8253
- select CLKSRC_I8253
- select FOOTBRIDGE_HOST
- select ISA
- select ISA_DMA
- select FORCE_PCI
+menuconfig ARCH_FOOTBRIDGE
+ bool "FootBridge Implementations"
+ depends on ARCH_MULTI_V4 && !(ARCH_MULTI_V4T || ARCH_MULTI_V5)
+ depends on !(ARCH_MOXART || ARCH_GEMINI || ARCH_SA1100)
+ depends on ATAGS
+ depends on CPU_LITTLE_ENDIAN
+ depends on MMU
+ select ARCH_NO_SG_CHAIN
+ select CPU_SA110
+ select FOOTBRIDGE
+ select NEED_MACH_MEMORY_H
help
- Say Y here if you intend to run this kernel on the CATS.
-
- Saying N will reduce the size of the Footbridge kernel.
+ Support for systems based on the DC21285 companion chip
+ ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
-config ARCH_EBSA285_ADDIN
- bool "EBSA285 (addin mode)"
- select ARCH_EBSA285
- select FOOTBRIDGE_ADDIN
- help
- Say Y here if you intend to run this kernel on the EBSA285 card
- in addin mode.
-
- Saying N will reduce the size of the Footbridge kernel.
+if ARCH_FOOTBRIDGE
config ARCH_EBSA285_HOST
bool "EBSA285 (host mode)"
select ARCH_EBSA285
- select FOOTBRIDGE_HOST
select ISA
- select ISA_DMA
select ARCH_MAY_HAVE_PC_FDC
select FORCE_PCI
help
@@ -44,9 +32,7 @@ config ARCH_NETWINDER
bool "NetWinder"
select CLKEVT_I8253
select CLKSRC_I8253
- select FOOTBRIDGE_HOST
select ISA
- select ISA_DMA
select FORCE_PCI
help
Say Y here if you intend to run this kernel on the Rebel.COM
@@ -56,22 +42,12 @@ config ARCH_NETWINDER
Saying N will reduce the size of the Footbridge kernel.
-endmenu
-
# Footbridge support
config FOOTBRIDGE
- bool
-
-# Footbridge in host mode
-config FOOTBRIDGE_HOST
- bool
+ def_bool y
select ARCH_MIGHT_HAVE_PC_SERIO
+ select ISA_DMA_API
-# Footbridge in addin mode
-config FOOTBRIDGE_ADDIN
- bool
-
-# EBSA285 board in either host or addin mode
config ARCH_EBSA285
bool
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 6262993c0555..1553cc01b45c 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -5,17 +5,14 @@
# Object file lists.
-obj-y := common.o dma.o isa-irq.o
+obj-y := common.o isa-irq.o isa.o isa-rtc.o dma-isa.o
pci-y += dc21285.o
-pci-$(CONFIG_ARCH_CATS) += cats-pci.o
-pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
+pci-$(CONFIG_ARCH_EBSA285) += ebsa285-pci.o
pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
-obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
obj-$(CONFIG_PCI) +=$(pci-y)
-obj-$(CONFIG_ISA) += isa.o isa-rtc.o
diff --git a/arch/arm/mach-footbridge/Makefile.boot b/arch/arm/mach-footbridge/Makefile.boot
deleted file mode 100644
index e4313e912cac..000000000000
--- a/arch/arm/mach-footbridge/Makefile.boot
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
- zreladdr-y += 0x00008000
-params_phys-y := 0x00000100
-initrd_phys-y := 0x00800000
-
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
deleted file mode 100644
index e575dc0698cd..000000000000
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/cats-hw.c
- *
- * CATS machine fixup
- *
- * Copyright (C) 1998, 1999 Russell King, Phil Blundell
- */
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/screen_info.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#include <asm/hardware/dec21285.h>
-#include <asm/mach-types.h>
-#include <asm/setup.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-#define CFG_PORT 0x370
-#define INDEX_PORT (CFG_PORT)
-#define DATA_PORT (CFG_PORT + 1)
-
-static int __init cats_hw_init(void)
-{
- if (machine_is_cats()) {
- /* Set Aladdin to CONFIGURE mode */
- outb(0x51, CFG_PORT);
- outb(0x23, CFG_PORT);
-
- /* Select logical device 3 */
- outb(0x07, INDEX_PORT);
- outb(0x03, DATA_PORT);
-
- /* Set parallel port to DMA channel 3, ECP+EPP1.9,
- enable EPP timeout */
- outb(0x74, INDEX_PORT);
- outb(0x03, DATA_PORT);
-
- outb(0xf0, INDEX_PORT);
- outb(0x0f, DATA_PORT);
-
- outb(0xf1, INDEX_PORT);
- outb(0x07, DATA_PORT);
-
- /* Select logical device 4 */
- outb(0x07, INDEX_PORT);
- outb(0x04, DATA_PORT);
-
- /* UART1 high speed mode */
- outb(0xf0, INDEX_PORT);
- outb(0x02, DATA_PORT);
-
- /* Select logical device 5 */
- outb(0x07, INDEX_PORT);
- outb(0x05, DATA_PORT);
-
- /* UART2 high speed mode */
- outb(0xf0, INDEX_PORT);
- outb(0x02, DATA_PORT);
-
- /* Set Aladdin to RUN mode */
- outb(0xbb, CFG_PORT);
- }
-
- return 0;
-}
-
-__initcall(cats_hw_init);
-
-/*
- * CATS uses soft-reboot by default, since
- * hard reboots fail on early boards.
- */
-static void __init
-fixup_cats(struct tag *tags, char **cmdline)
-{
-#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
- screen_info.orig_video_lines = 25;
- screen_info.orig_video_points = 16;
- screen_info.orig_y = 24;
-#endif
-}
-
-MACHINE_START(CATS, "Chalice-CATS")
- /* Maintainer: Philip Blundell */
- .atag_offset = 0x100,
- .reboot_mode = REBOOT_SOFT,
- .fixup = fixup_cats,
- .map_io = footbridge_map_io,
- .init_irq = footbridge_init_irq,
- .init_time = isa_timer_init,
- .restart = footbridge_restart,
-MACHINE_END
diff --git a/arch/arm/mach-footbridge/cats-pci.c b/arch/arm/mach-footbridge/cats-pci.c
deleted file mode 100644
index 90b1e9be430e..000000000000
--- a/arch/arm/mach-footbridge/cats-pci.c
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/mach-footbridge/cats-pci.c
- *
- * PCI bios-type initialisation for PCI machines
- *
- * Bits taken from various places.
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-/* cats host-specific stuff */
-static int irqmap_cats[] = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
-
-static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin)
-{
- return 0;
-}
-
-static int cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- if (dev->irq >= 255)
- return -1; /* not a valid interrupt. */
-
- if (dev->irq >= 128)
- return dev->irq & 0x1f;
-
- if (dev->irq >= 1 && dev->irq <= 4)
- return irqmap_cats[dev->irq - 1];
-
- if (dev->irq != 0)
- printk("PCI: device %02x:%02x has unknown irq line %x\n",
- dev->bus->number, dev->devfn, dev->irq);
-
- return -1;
-}
-
-/*
- * why not the standard PCI swizzle? does this prevent 4-port tulip
- * cards being used (ie, pci-pci bridge based cards)?
- */
-static struct hw_pci cats_pci __initdata = {
- .swizzle = cats_no_swizzle,
- .map_irq = cats_map_irq,
- .nr_controllers = 1,
- .ops = &dc21285_ops,
- .setup = dc21285_setup,
- .preinit = dc21285_preinit,
- .postinit = dc21285_postinit,
-};
-
-static int __init cats_pci_init(void)
-{
- if (machine_is_cats())
- pci_common_init(&cats_pci);
- return 0;
-}
-
-subsys_initcall(cats_pci_init);
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 322495df271d..85c598708c10 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
+#include <linux/dma-direct.h>
#include <video/vga.h>
#include <asm/page.h>
@@ -197,9 +198,6 @@ void __init footbridge_init_irq(void)
__fb_init_irq();
- if (!footbridge_cfn_mode())
- return;
-
if (machine_is_ebsa285())
/* The following is dependent on which slot
* you plug the Southbridge card into. We
@@ -208,9 +206,6 @@ void __init footbridge_init_irq(void)
*/
isa_init_irq(IRQ_PCI);
- if (machine_is_cats())
- isa_init_irq(IRQ_IN2);
-
if (machine_is_netwinder())
isa_init_irq(IRQ_IN3);
}
@@ -220,21 +215,13 @@ void __init footbridge_init_irq(void)
* commented out since there is a "No Fix" problem with it. Not mapping
* it means that we have extra bullet protection on our feet.
*/
-static struct map_desc fb_common_io_desc[] __initdata = {
+static struct map_desc ebsa285_host_io_desc[] __initdata = {
{
.virtual = ARMCSR_BASE,
.pfn = __phys_to_pfn(DC21285_ARMCSR_BASE),
.length = ARMCSR_SIZE,
.type = MT_DEVICE,
- }
-};
-
-/*
- * The mapping when the footbridge is in host mode. We don't map any of
- * this when we are in add-in mode.
- */
-static struct map_desc ebsa285_host_io_desc[] __initdata = {
-#if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
+ },
{
.virtual = PCIMEM_BASE,
.pfn = __phys_to_pfn(DC21285_PCI_MEM),
@@ -256,26 +243,12 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
.length = PCIIACK_SIZE,
.type = MT_DEVICE,
},
-#endif
};
void __init footbridge_map_io(void)
{
- /*
- * Set up the common mapping first; we need this to
- * determine whether we're in host mode or not.
- */
- iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
-
- /*
- * Now, work out what we've got to map in addition on this
- * platform.
- */
- if (footbridge_cfn_mode()) {
- iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
- pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
- }
-
+ iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
+ pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
vga_base = PCIMEM_BASE;
}
@@ -305,47 +278,3 @@ void footbridge_restart(enum reboot_mode mode, const char *cmd)
*CSR_SA110_CNTL |= (1 << 13);
}
}
-
-#ifdef CONFIG_FOOTBRIDGE_ADDIN
-
-static inline unsigned long fb_bus_sdram_offset(void)
-{
- return *CSR_PCISDRAMBASE & 0xfffffff0;
-}
-
-/*
- * These two functions convert virtual addresses to PCI addresses and PCI
- * addresses to virtual addresses. Note that it is only legal to use these
- * on memory obtained via get_zeroed_page or kmalloc.
- */
-unsigned long __virt_to_bus(unsigned long res)
-{
- WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
-
- return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
-}
-EXPORT_SYMBOL(__virt_to_bus);
-
-unsigned long __bus_to_virt(unsigned long res)
-{
- res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
-
- WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
-
- return res;
-}
-EXPORT_SYMBOL(__bus_to_virt);
-
-unsigned long __pfn_to_bus(unsigned long pfn)
-{
- return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
-}
-EXPORT_SYMBOL(__pfn_to_bus);
-
-unsigned long __bus_to_pfn(unsigned long bus)
-{
- return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET));
-}
-EXPORT_SYMBOL(__bus_to_pfn);
-
-#endif
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index f9713dc561cf..f8920d0010de 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -5,6 +5,7 @@
* Copyright (C) 1998-2001 Russell King
* Copyright (C) 1998-2000 Phil Blundell
*/
+#include <linux/dma-map-ops.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
@@ -241,13 +242,26 @@ static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static int dc21285_pci_bus_notifier(struct notifier_block *nb,
+ unsigned long action,
+ void *data)
+{
+ if (action != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ dma_direct_set_offset(data, PHYS_OFFSET, BUS_OFFSET, SZ_256M);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block dc21285_pci_bus_nb = {
+ .notifier_call = dc21285_pci_bus_notifier,
+};
+
int __init dc21285_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
- if (nr || !footbridge_cfn_mode())
- return 0;
-
res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
if (!res) {
printk("out of memory for root bus resources");
@@ -269,6 +283,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+ bus_register_notifier(&pci_bus_type, &dc21285_pci_bus_nb);
+
return 1;
}
@@ -278,7 +294,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
void __init dc21285_preinit(void)
{
unsigned int mem_size, mem_mask;
- int cfn_mode;
pcibios_min_mem = 0x81000000;
@@ -298,21 +313,15 @@ void __init dc21285_preinit(void)
*CSR_CSRBASEOFFSET = 0;
*CSR_PCIADDR_EXTN = 0;
- cfn_mode = __footbridge_cfn_mode();
-
printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
- "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ?
- "central function" : "addin");
-
- if (footbridge_cfn_mode()) {
- /*
- * Clear any existing errors - we aren't
- * interested in historical data...
- */
- *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) |
- SA110_CNTL_RXSERR;
- *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
- }
+ "central function mode\n", *CSR_CLASSREV & 0xff);
+
+ /*
+ * Clear any existing errors - we aren't
+ * interested in historical data...
+ */
+ *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) | SA110_CNTL_RXSERR;
+ *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
timer_setup(&serr_timer, dc21285_enable_error, 0);
timer_setup(&perr_timer, dc21285_enable_error, 0);
@@ -331,29 +340,18 @@ void __init dc21285_preinit(void)
dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0,
"PCI data parity", NULL);
- if (cfn_mode) {
- /*
- * Map our SDRAM at a known address in PCI space, just in case
- * the firmware had other ideas. Using a nonzero base is
- * necessary, since some VGA cards forcefully use PCI addresses
- * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
- */
- *CSR_PCICSRBASE = 0xf4000000;
- *CSR_PCICSRIOBASE = 0;
- *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
- *CSR_PCIROMBASE = 0;
- *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
- PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
- } else if (footbridge_cfn_mode() != 0) {
- /*
- * If we are not compiled to accept "add-in" mode, then
- * we are using a constant virt_to_bus translation which
- * can not hope to cater for the way the host BIOS has
- * set up the machine.
- */
- panic("PCI: this kernel is compiled for central "
- "function mode only");
- }
+ /*
+ * Map our SDRAM at a known address in PCI space, just in case
+ * the firmware had other ideas. Using a nonzero base is
+ * necessary, since some VGA cards forcefully use PCI addresses
+ * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
+ */
+ *CSR_PCICSRBASE = 0xf4000000;
+ *CSR_PCICSRIOBASE = 0;
+ *CSR_PCISDRAMBASE = BUS_OFFSET;
+ *CSR_PCIROMBASE = 0;
+ *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+ PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
}
void __init dc21285_postinit(void)
diff --git a/arch/arm/kernel/dma-isa.c b/arch/arm/mach-footbridge/dma-isa.c
index 2d90ecce5a11..937f5376d5e7 100644
--- a/arch/arm/kernel/dma-isa.c
+++ b/arch/arm/mach-footbridge/dma-isa.c
@@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * linux/arch/arm/kernel/dma-isa.c
- *
* Copyright (C) 1999-2000 Russell King
*
* ISA DMA primitives
@@ -13,6 +11,7 @@
* arch/arm/kernel/dma-ebsa285.c
* Copyright (C) 1998 Phil Blundell
*/
+#include <linux/dma-map-ops.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
@@ -20,6 +19,7 @@
#include <asm/dma.h>
#include <asm/mach/dma.h>
+#include <asm/hardware/dec21285.h>
#define ISA_DMA_MASK 0
#define ISA_DMA_MODE 1
@@ -157,7 +157,7 @@ static dma_t isa_dma[8];
/*
* ISA DMA always starts at channel 0
*/
-void __init isa_init_dma(void)
+static int __init isa_dma_init(void)
{
/*
* Try to autodetect presence of an ISA DMA controller.
@@ -222,4 +222,9 @@ void __init isa_init_dma(void)
request_dma(DMA_ISA_CASCADE, "cascade");
}
+
+ dma_direct_set_offset(&isa_dma_dev, PHYS_OFFSET, BUS_OFFSET, SZ_256M);
+
+ return 0;
}
+core_initcall(isa_dma_init);
diff --git a/arch/arm/mach-footbridge/dma.c b/arch/arm/mach-footbridge/dma.c
deleted file mode 100644
index 86618074a7a5..000000000000
--- a/arch/arm/mach-footbridge/dma.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/arm/kernel/dma-ebsa285.c
- *
- * Copyright (C) 1998 Phil Blundell
- *
- * DMA functions specific to EBSA-285/CATS architectures
- *
- * Changelog:
- * 09-Nov-1998 RMK Split out ISA DMA functions to dma-isa.c
- * 17-Mar-1999 RMK Allow any EBSA285-like architecture to have
- * ISA DMA controllers.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <linux/scatterlist.h>
-
-#include <asm/dma.h>
-
-#include <asm/mach/dma.h>
-#include <asm/hardware/dec21285.h>
-
-#if 0
-static int fb_dma_request(unsigned int chan, dma_t *dma)
-{
- return -EINVAL;
-}
-
-static void fb_dma_enable(unsigned int chan, dma_t *dma)
-{
-}
-
-static void fb_dma_disable(unsigned int chan, dma_t *dma)
-{
-}
-
-static struct dma_ops fb_dma_ops = {
- .type = "fb",
- .request = fb_dma_request,
- .enable = fb_dma_enable,
- .disable = fb_dma_disable,
-};
-#endif
-
-static int __init fb_dma_init(void)
-{
-#if 0
- dma[_DC21285_DMA(0)].d_ops = &fb_dma_ops;
- dma[_DC21285_DMA(1)].d_ops = &fb_dma_ops;
-#endif
-#ifdef CONFIG_ISA_DMA
- if (footbridge_cfn_mode())
- isa_init_dma();
-#endif
- return 0;
-}
-core_initcall(fb_dma_init);
diff --git a/arch/arm/mach-footbridge/include/mach/isa-dma.h b/arch/arm/mach-footbridge/include/mach/isa-dma.h
index 8a1b991076e1..b10731a1f66a 100644
--- a/arch/arm/mach-footbridge/include/mach/isa-dma.h
+++ b/arch/arm/mach-footbridge/include/mach/isa-dma.h
@@ -10,17 +10,9 @@
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
-/*
- * The 21285 has two internal DMA channels; we call these 8 and 9.
- * On CATS hardware we have an additional eight ISA dma channels
- * numbered 0..7.
- */
-#define _ISA_DMA(x) (0+(x))
-#define _DC21285_DMA(x) (8+(x))
-
-#define MAX_DMA_CHANNELS 10
+#define MAX_DMA_CHANNELS 8
-#define DMA_FLOPPY _ISA_DMA(2)
-#define DMA_ISA_CASCADE _ISA_DMA(4)
+#define DMA_FLOPPY (2)
+#define DMA_ISA_CASCADE (4)
#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h
index 46fd4a8872b9..9516877667d7 100644
--- a/arch/arm/mach-footbridge/include/mach/memory.h
+++ b/arch/arm/mach-footbridge/include/mach/memory.h
@@ -16,41 +16,6 @@
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
-
-#if defined(CONFIG_FOOTBRIDGE_ADDIN)
-/*
- * If we may be using add-in footbridge mode, then we must
- * use the out-of-line translation that makes use of the
- * PCI BAR
- */
-#ifndef __ASSEMBLY__
-extern unsigned long __virt_to_bus(unsigned long);
-extern unsigned long __bus_to_virt(unsigned long);
-extern unsigned long __pfn_to_bus(unsigned long);
-extern unsigned long __bus_to_pfn(unsigned long);
-#endif
-#define __virt_to_bus __virt_to_bus
-#define __bus_to_virt __bus_to_virt
-
-#elif defined(CONFIG_FOOTBRIDGE_HOST)
-
-/*
- * The footbridge is programmed to expose the system RAM at 0xe0000000.
- * The requirement is that the RAM isn't placed at bus address 0, which
- * would clash with VGA cards.
- */
-#define BUS_OFFSET 0xe0000000
-#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
-#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
-#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
-#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
-
-#else
-
-#error "Undefined footbridge mode"
-
-#endif
-
/*
* Cache flushing area.
*/
diff --git a/arch/arm/mach-footbridge/isa-rtc.c b/arch/arm/mach-footbridge/isa-rtc.c
index b8f741a3a37e..237b828dd2f1 100644
--- a/arch/arm/mach-footbridge/isa-rtc.c
+++ b/arch/arm/mach-footbridge/isa-rtc.c
@@ -20,7 +20,6 @@
#include <linux/init.h>
#include <linux/mc146818rtc.h>
-#include <linux/bcd.h>
#include <linux/io.h>
#include "common.h"
diff --git a/arch/arm/mach-footbridge/isa.c b/arch/arm/mach-footbridge/isa.c
index ec5af521cf95..84caccddce44 100644
--- a/arch/arm/mach-footbridge/isa.c
+++ b/arch/arm/mach-footbridge/isa.c
@@ -79,16 +79,12 @@ static int __init footbridge_isa_init(void)
{
int err = 0;
- if (!footbridge_cfn_mode())
- return 0;
-
/* Personal server doesn't have RTC */
- if (!machine_is_personal_server()) {
- isa_rtc_init();
- err = platform_device_register(&rtc_device);
- if (err)
- printk(KERN_ERR "Unable to register RTC device: %d\n", err);
- }
+ isa_rtc_init();
+ err = platform_device_register(&rtc_device);
+ if (err)
+ printk(KERN_ERR "Unable to register RTC device: %d\n", err);
+
err = platform_device_register(&serial_device);
if (err)
printk(KERN_ERR "Unable to register serial device: %d\n", err);
diff --git a/arch/arm/mach-gemini/Kconfig b/arch/arm/mach-gemini/Kconfig
index 969674ea5f17..f436a2009eca 100644
--- a/arch/arm/mach-gemini/Kconfig
+++ b/arch/arm/mach-gemini/Kconfig
@@ -2,6 +2,7 @@
menuconfig ARCH_GEMINI
bool "Cortina Systems Gemini"
depends on ARCH_MULTI_V4
+ depends on CPU_LITTLE_ENDIAN
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
diff --git a/arch/arm/mach-gemini/board-dt.c b/arch/arm/mach-gemini/board-dt.c
index de0afcc8d94a..fbafe7475c02 100644
--- a/arch/arm/mach-gemini/board-dt.c
+++ b/arch/arm/mach-gemini/board-dt.c
@@ -42,8 +42,9 @@ static void gemini_idle(void)
*/
/* FIXME: Enabling interrupts here is racy! */
- local_irq_enable();
+ raw_local_irq_enable();
cpu_do_idle();
+ raw_local_irq_disable();
}
static void __init gemini_init_machine(void)
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 9de38ce8124f..c2d6ef6b3927 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -2,7 +2,6 @@
config ARCH_HIGHBANK
bool "Calxeda ECX-1000/2000 (Highbank/Midway)"
depends on ARCH_MULTI_V7
- select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index db607955a7e4..5d4f977ac7d2 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -98,7 +98,7 @@ static int highbank_platform_notifier(struct notifier_block *nb,
if (of_property_read_bool(dev->of_node, "dma-coherent")) {
val = readl(sregs_base + reg);
writel(val | 0xff01, sregs_base + reg);
- set_dma_ops(dev, &arm_coherent_dma_ops);
+ dev->dma_coherent = true;
}
return NOTIFY_OK;
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 2e980f834a6a..7b3440687176 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HISI
bool "Hisilicon SoC Support"
- depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
+ depends on ARCH_MULTI_V7 || (ARCH_MULTI_V5 && CPU_LITTLE_ENDIAN)
select ARM_AMBA
select ARM_GIC if ARCH_MULTI_V7
select ARM_TIMER_SP804
@@ -40,7 +40,7 @@ config ARCH_HIP04
select HAVE_ARM_ARCH_TIMER
select MCPM if SMP
select MCPM_QUAD_CLUSTER if SMP
- select GENERIC_IRQ_EFFECTIVE_AFF_MASK
+ select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
help
Support for Hisilicon HiP04 SoC family
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index a56cc64deeb8..9ce93e0b6cdc 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -67,14 +67,17 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
}
ctrl_base = of_iomap(np, 0);
if (!ctrl_base) {
+ of_node_put(np);
pr_err("failed to map address\n");
return;
}
if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
+ of_node_put(np);
pr_err("failed to find smp-offset property\n");
return;
}
ctrl_base += offset;
+ of_node_put(np);
}
}
@@ -160,6 +163,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
if (WARN_ON(!node))
return -1;
ctrl_base = of_iomap(node, 0);
+ of_node_put(node);
/* set the secondary core boot from DDR */
remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
diff --git a/arch/arm/mach-hpe/Kconfig b/arch/arm/mach-hpe/Kconfig
new file mode 100644
index 000000000000..3372bbf38d38
--- /dev/null
+++ b/arch/arm/mach-hpe/Kconfig
@@ -0,0 +1,23 @@
+menuconfig ARCH_HPE
+ bool "HPE SoC support"
+ depends on ARCH_MULTI_V7
+ help
+ This enables support for HPE ARM based BMC chips.
+if ARCH_HPE
+
+config ARCH_HPE_GXP
+ bool "HPE GXP SoC"
+ depends on ARCH_MULTI_V7
+ select ARM_VIC
+ select GENERIC_IRQ_CHIP
+ select CLKSRC_MMIO
+ help
+ HPE GXP is the name of the HPE Soc. This SoC is used to implement many
+ BMC features at HPE. It supports ARMv7 architecture based on the Cortex
+ A9 core. It is capable of using an AXI bus to which a memory controller
+ is attached. It has multiple SPI interfaces to connect boot flash and
+ BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It
+ has multiple i2c engines to drive connectivity with a host
+ infrastructure.
+
+endif
diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile
new file mode 100644
index 000000000000..8b0a91234df4
--- /dev/null
+++ b/arch/arm/mach-hpe/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o
diff --git a/arch/arm/mach-hpe/gxp.c b/arch/arm/mach-hpe/gxp.c
new file mode 100644
index 000000000000..ef3341373006
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+static const char * const gxp_board_dt_compat[] = {
+ "hpe,gxp",
+ NULL,
+};
+
+DT_MACHINE_START(GXP_DT, "HPE GXP")
+ .dt_compat = gxp_board_dt_compat,
+ .l2c_aux_val = 0,
+ .l2c_aux_mask = ~0,
+MACHINE_END
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c5a59158722b..ab767f059929 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MXC
bool "Freescale i.MX family"
- depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
- select ARCH_SUPPORTS_BIG_ENDIAN
+ depends on ((ARCH_MULTI_V4T || ARCH_MULTI_V5) && CPU_LITTLE_ENDIAN) || \
+ ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
select CLKSRC_IMX_GPT
select GENERIC_IRQ_CHIP
select GPIOLIB
@@ -96,7 +96,7 @@ config SOC_IMX5
select HAVE_IMX_SRC
select MXC_TZIC
-config SOC_IMX50
+config SOC_IMX50
bool "i.MX50 support"
select PINCTRL_IMX50
select SOC_IMX5
@@ -111,7 +111,7 @@ config SOC_IMX51
help
This enables support for Freescale i.MX51 processor
-config SOC_IMX53
+config SOC_IMX53
bool "i.MX53 support"
select PINCTRL_IMX53
select SOC_IMX5
@@ -216,7 +216,7 @@ config SOC_IMX7D
select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
select ARM_ERRATA_814220 if ARCH_MULTI_V7
help
- This enables support for Freescale i.MX7 Dual processor.
+ This enables support for Freescale i.MX7 Dual processor.
config SOC_IMX7ULP
bool "i.MX7ULP support"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 6fb3965b9ae6..5c650bf40e02 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -34,7 +34,6 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),)
-AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
endif
@@ -48,12 +47,10 @@ obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
-AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
endif
ifeq ($(CONFIG_ARM_CPU_SUSPEND),y)
-AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/arch/arm/mach-imx/Makefile.boot
+++ /dev/null
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
index b2e1963f473d..cc86977d0a34 100644
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -23,6 +23,7 @@ static int mx25_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
iim_base = of_iomap(np, 0);
+ of_node_put(np);
BUG_ON(!iim_base);
rev = readl(iim_base + MXC_IIMSREV);
iounmap(iim_base);
@@ -32,6 +33,8 @@ static int mx25_read_cpu_rev(void)
return IMX_CHIP_REVISION_1_0;
case 0x01:
return IMX_CHIP_REVISION_1_1;
+ case 0x02:
+ return IMX_CHIP_REVISION_1_2;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index bf70e13bbe9e..1d2893908368 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -28,6 +28,7 @@ static int mx27_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
ccm_base = of_iomap(np, 0);
+ of_node_put(np);
BUG_ON(!ccm_base);
/*
* now we have access to the IO registers. As we need
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index b9c24b851d1a..35c544924e50 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -39,6 +39,7 @@ static int mx31_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
iim_base = of_iomap(np, 0);
+ of_node_put(np);
BUG_ON(!iim_base);
/* read SREV register from IIM module */
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
index 80e7d8ab9f1b..1fe75b39c2d9 100644
--- a/arch/arm/mach-imx/cpu-imx35.c
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -21,6 +21,7 @@ static int mx35_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim");
iim_base = of_iomap(np, 0);
+ of_node_put(np);
BUG_ON(!iim_base);
rev = imx_readl(iim_base + MXC_IIMSREV);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index ad56263778f9..a67c89bf155d 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -28,6 +28,7 @@ static u32 imx5_read_srev_reg(const char *compat)
np = of_find_compatible_node(NULL, NULL, compat);
iim_base = of_iomap(np, 0);
+ of_node_put(np);
WARN_ON(!iim_base);
srev = readl(iim_base + IIM_SREV) & 0xff;
diff --git a/arch/arm/mach-imx/cpuidle-imx5.c b/arch/arm/mach-imx/cpuidle-imx5.c
index a8457c4eb99a..5ad9f2f533cd 100644
--- a/arch/arm/mach-imx/cpuidle-imx5.c
+++ b/arch/arm/mach-imx/cpuidle-imx5.c
@@ -8,8 +8,8 @@
#include <asm/system_misc.h>
#include "cpuidle.h"
-static int imx5_cpuidle_enter(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+static __cpuidle int imx5_cpuidle_enter(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
arm_pm_idle();
return index;
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 094337dc1bc7..2b0d3160f993 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -3,6 +3,7 @@
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*/
+#include <linux/context_tracking.h>
#include <linux/cpuidle.h>
#include <linux/module.h>
#include <asm/cpuidle.h>
@@ -16,17 +17,17 @@
static int num_idle_cpus = 0;
static DEFINE_RAW_SPINLOCK(cpuidle_lock);
-static int imx6q_enter_wait(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+static __cpuidle int imx6q_enter_wait(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
raw_spin_lock(&cpuidle_lock);
if (++num_idle_cpus == num_online_cpus())
imx6_set_lpm(WAIT_UNCLOCKED);
raw_spin_unlock(&cpuidle_lock);
- rcu_idle_enter();
+ ct_cpuidle_enter();
cpu_do_idle();
- rcu_idle_exit();
+ ct_cpuidle_exit();
raw_spin_lock(&cpuidle_lock);
if (num_idle_cpus-- == num_online_cpus())
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
index b86ffbeb28e4..b49cd6302dce 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sl.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -11,8 +11,8 @@
#include "common.h"
#include "cpuidle.h"
-static int imx6sl_enter_wait(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+static __cpuidle int imx6sl_enter_wait(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
imx6_set_lpm(WAIT_UNCLOCKED);
/*
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c
index 74ea1720e3d8..83c5cbd3748e 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -30,8 +30,8 @@ static int imx6sx_idle_finish(unsigned long val)
return 0;
}
-static int imx6sx_enter_wait(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+static __cpuidle int imx6sx_enter_wait(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
imx6_set_lpm(WAIT_UNCLOCKED);
@@ -47,7 +47,9 @@ static int imx6sx_enter_wait(struct cpuidle_device *dev,
cpu_pm_enter();
cpu_cluster_pm_enter();
+ ct_cpuidle_enter();
cpu_suspend(0, imx6sx_idle_finish);
+ ct_cpuidle_exit();
cpu_cluster_pm_exit();
cpu_pm_exit();
@@ -87,7 +89,8 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = {
*/
.exit_latency = 300,
.target_residency = 500,
- .flags = CPUIDLE_FLAG_TIMER_STOP,
+ .flags = CPUIDLE_FLAG_TIMER_STOP |
+ CPUIDLE_FLAG_RCU_IDLE,
.enter = imx6sx_enter_wait,
.name = "LOW-POWER-IDLE",
.desc = "ARM power off",
diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c b/arch/arm/mach-imx/cpuidle-imx7ulp.c
index ca86c967d19e..f55ed74acfae 100644
--- a/arch/arm/mach-imx/cpuidle-imx7ulp.c
+++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c
@@ -12,8 +12,8 @@
#include "common.h"
#include "cpuidle.h"
-static int imx7ulp_enter_wait(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+static __cpuidle int imx7ulp_enter_wait(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
if (index == 1)
imx7ulp_set_lpm(ULP_PM_WAIT);
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index ebc4339b8be4..5909088d5482 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -275,7 +275,7 @@ void __init imx_gpc_check_dt(void)
if (WARN_ON(!np))
return;
- if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
+ if (WARN_ON(!of_property_read_bool(np, "interrupt-controller"))) {
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
/* map GPC, so that at least CPUidle and WARs keep working */
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index fcba58be8e79..5f9c7b48ae80 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -8,6 +8,8 @@
#include <linux/init.h>
#include <asm/assembler.h>
+.arch armv7-a
+
diag_reg_offset:
.word g_diag_reg - .
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index c9d7c29d95e1..7f6200925752 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -79,7 +79,7 @@ static void __init imx6q_enet_phy_init(void)
static void __init imx6q_1588_init(void)
{
struct device_node *np;
- struct clk *ptp_clk;
+ struct clk *ptp_clk, *fec_enet_ref;
struct clk *enet_ref;
struct regmap *gpr;
u32 clksel;
@@ -90,6 +90,14 @@ static void __init imx6q_1588_init(void)
return;
}
+ /*
+ * If enet_clk_ref configured, we assume DT did it properly and .
+ * clk-imx6q.c will do needed configuration.
+ */
+ fec_enet_ref = of_clk_get_by_name(np, "enet_clk_ref");
+ if (!IS_ERR(fec_enet_ref))
+ goto put_node;
+
ptp_clk = of_clk_get(np, 2);
if (IS_ERR(ptp_clk)) {
pr_warn("%s: failed to get ptp clock\n", __func__);
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index 35e81201cb5d..7a0299de1db6 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -4,8 +4,6 @@
*/
#include <linux/irqchip.h>
#include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-#include <linux/micrel_phy.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/regmap.h>
@@ -16,30 +14,12 @@
#include "cpuidle.h"
#include "hardware.h"
-static void __init imx6ul_enet_clk_init(void)
-{
- struct regmap *gpr;
-
- gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
- if (!IS_ERR(gpr))
- regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
- IMX6UL_GPR1_ENET_CLK_OUTPUT);
- else
- pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
-}
-
-static inline void imx6ul_enet_init(void)
-{
- imx6ul_enet_clk_init();
-}
-
static void __init imx6ul_init_machine(void)
{
imx_print_silicon_rev(cpu_is_imx6ull() ? "i.MX6ULL" : "i.MX6UL",
imx_get_soc_revision());
of_platform_default_populate(NULL, NULL, NULL);
- imx6ul_enet_init();
imx_anatop_init();
imx6ul_pm_init();
}
@@ -63,6 +43,7 @@ static void __init imx6ul_init_late(void)
static const char * const imx6ul_dt_compat[] __initconst = {
"fsl,imx6ul",
"fsl,imx6ull",
+ "fsl,imx6ulz",
NULL,
};
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 28db97289ee8..0788c5cc7f9e 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -12,7 +12,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_address.h>
-#include <linux/pinctrl/machine.h>
#include <asm/system_misc.h>
#include <asm/hardware/cache-l2x0.h>
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index af12668d0bf5..2157493b78a9 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -99,6 +99,7 @@ struct mmdc_pmu {
cpumask_t cpu;
struct hrtimer hrtimer;
unsigned int active_events;
+ int id;
struct device *dev;
struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
struct hlist_node node;
@@ -433,8 +434,6 @@ static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
void __iomem *mmdc_base, struct device *dev)
{
- int mmdc_num;
-
*pmu_mmdc = (struct mmdc_pmu) {
.pmu = (struct pmu) {
.task_ctx_nr = perf_invalid_context,
@@ -452,21 +451,21 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
.active_events = 0,
};
- mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
+ pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
- return mmdc_num;
+ return pmu_mmdc->id;
}
-static int imx_mmdc_remove(struct platform_device *pdev)
+static void imx_mmdc_remove(struct platform_device *pdev)
{
struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
+ ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
perf_pmu_unregister(&pmu_mmdc->pmu);
iounmap(pmu_mmdc->mmdc_base);
clk_disable_unprepare(pmu_mmdc->mmdc_ipg_clk);
kfree(pmu_mmdc);
- return 0;
}
static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base,
@@ -474,7 +473,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
{
struct mmdc_pmu *pmu_mmdc;
char *name;
- int mmdc_num;
int ret;
const struct of_device_id *of_id =
of_match_device(imx_mmdc_dt_ids, &pdev->dev);
@@ -497,14 +495,14 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
cpuhp_mmdc_state = ret;
}
- mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
- pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
- if (mmdc_num == 0)
- name = "mmdc";
- else
- name = devm_kasprintf(&pdev->dev,
- GFP_KERNEL, "mmdc%d", mmdc_num);
+ ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
+ if (ret < 0)
+ goto pmu_free;
+ name = devm_kasprintf(&pdev->dev,
+ GFP_KERNEL, "mmdc%d", ret);
+
+ pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
@@ -525,6 +523,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
+ ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
hrtimer_cancel(&pmu_mmdc->hrtimer);
pmu_free:
@@ -592,7 +591,7 @@ static struct platform_driver imx_mmdc_driver = {
.of_match_table = imx_mmdc_dt_ids,
},
.probe = imx_mmdc_probe,
- .remove = imx_mmdc_remove,
+ .remove_new = imx_mmdc_remove,
};
static int __init imx_mmdc_init(void)
diff --git a/arch/arm/mach-imx/resume-imx6.S b/arch/arm/mach-imx/resume-imx6.S
index 5bd1ba7ef15b..2c0c5c771251 100644
--- a/arch/arm/mach-imx/resume-imx6.S
+++ b/arch/arm/mach-imx/resume-imx6.S
@@ -9,6 +9,8 @@
#include <asm/hardware/cache-l2x0.h>
#include "hardware.h"
+.arch armv7-a
+
/*
* The following code must assume it is running from physical address
* where absolute virtual addresses to the data section have to be
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index e06f946b75b9..63ccc2d0e920 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -9,6 +9,8 @@
#include <asm/hardware/cache-l2x0.h>
#include "hardware.h"
+.arch armv7-a
+
/*
* ==================== low level suspend ====================
*
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
deleted file mode 100644
index d61ea616cf8e..000000000000
--- a/arch/arm/mach-integrator/Kconfig
+++ /dev/null
@@ -1,125 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-menuconfig ARCH_INTEGRATOR
- bool "ARM Ltd. Integrator family"
- depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6
- select ARM_AMBA
- select CMA
- select DMA_CMA
- select HAVE_TCM
- select CLK_ICST
- select MFD_SYSCON
- select PLAT_VERSATILE
- select POWER_RESET
- select POWER_RESET_VERSATILE
- select POWER_SUPPLY
- select SOC_INTEGRATOR_CM
- select VERSATILE_FPGA_IRQ
- help
- Support for ARM's Integrator platform.
-
-if ARCH_INTEGRATOR
-
-config ARCH_INTEGRATOR_AP
- bool "Support Integrator/AP and Integrator/PP2 platforms"
- select INTEGRATOR_AP_TIMER
- select SERIAL_AMBA_PL010 if TTY
- select SERIAL_AMBA_PL010_CONSOLE if TTY
- select SOC_BUS
- help
- Include support for the ARM(R) Integrator/AP and
- Integrator/PP2 platforms.
-
-config INTEGRATOR_IMPD1
- bool "Include support for Integrator/IM-PD1"
- depends on ARCH_INTEGRATOR_AP
- select ARM_VIC
- select GPIO_PL061
- select GPIOLIB
- select REGULATOR
- select REGULATOR_FIXED_VOLTAGE
- help
- The IM-PD1 is an add-on logic module for the Integrator which
- allows ARM(R) Ltd PrimeCells to be developed and evaluated.
- The IM-PD1 can be found on the Integrator/PP2 platform.
-
-config INTEGRATOR_CM720T
- bool "Integrator/CM720T core module"
- depends on ARCH_INTEGRATOR_AP
- depends on ARCH_MULTI_V4T
- select CPU_ARM720T
-
-config INTEGRATOR_CM920T
- bool "Integrator/CM920T core module"
- depends on ARCH_INTEGRATOR_AP
- depends on ARCH_MULTI_V4T
- select CPU_ARM920T
-
-config INTEGRATOR_CM922T_XA10
- bool "Integrator/CM922T-XA10 core module"
- depends on ARCH_MULTI_V4T
- depends on ARCH_INTEGRATOR_AP
- select CPU_ARM922T
-
-config INTEGRATOR_CM926EJS
- bool "Integrator/CM926EJ-S core module"
- depends on ARCH_INTEGRATOR_AP
- depends on ARCH_MULTI_V5
- select CPU_ARM926T
-
-config INTEGRATOR_CM10200E_REV0
- bool "Integrator/CM10200E rev.0 core module"
- depends on ARCH_INTEGRATOR_AP && n
- depends on ARCH_MULTI_V5
- select CPU_ARM1020
-
-config INTEGRATOR_CM10200E
- bool "Integrator/CM10200E core module"
- depends on ARCH_INTEGRATOR_AP && n
- depends on ARCH_MULTI_V5
- select CPU_ARM1020E
-
-config INTEGRATOR_CM10220E
- bool "Integrator/CM10220E core module"
- depends on ARCH_INTEGRATOR_AP
- depends on ARCH_MULTI_V5
- select CPU_ARM1022
-
-config INTEGRATOR_CM1026EJS
- bool "Integrator/CM1026EJ-S core module"
- depends on ARCH_INTEGRATOR_AP
- depends on ARCH_MULTI_V5
- select CPU_ARM1026
-
-config INTEGRATOR_CM1136JFS
- bool "Integrator/CM1136JF-S core module"
- depends on ARCH_INTEGRATOR_AP
- depends on ARCH_MULTI_V6
- select CPU_V6
-
-config ARCH_INTEGRATOR_CP
- bool "Support Integrator/CP platform"
- depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
- select ARM_TIMER_SP804
- select SERIAL_AMBA_PL011 if TTY
- select SERIAL_AMBA_PL011_CONSOLE if TTY
- select SOC_BUS
- help
- Include support for the ARM(R) Integrator CP platform.
-
-config INTEGRATOR_CT926
- bool "Integrator/CT926 (ARM926EJ-S) core tile"
- depends on ARCH_INTEGRATOR_CP
- depends on ARCH_MULTI_V5
- select CPU_ARM926T
-
-config INTEGRATOR_CTB36
- bool "Integrator/CTB36 (ARM1136JF-S) core tile"
- depends on ARCH_INTEGRATOR_CP
- depends on ARCH_MULTI_V6
- select CPU_V6
-
-config ARCH_CINTEGRATOR
- depends on ARCH_INTEGRATOR_CP
- def_bool y
-
-endif
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
deleted file mode 100644
index 7857a55c90b0..000000000000
--- a/arch/arm/mach-integrator/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := core.o
-obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
-obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
deleted file mode 100644
index f1f342cb0509..000000000000
--- a/arch/arm/mach-iop32x/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ARCH_IOP32X
-
-menu "IOP32x Implementation Options"
-
-comment "IOP32x Platform Types"
-
-config MACH_EP80219
- bool
-
-config MACH_GLANTANK
- bool "Enable support for the IO-Data GLAN Tank"
- help
- Say Y here if you want to run your kernel on the GLAN Tank
- NAS appliance or machines from IO-Data's HDL-Gxxx, HDL-GWxxx
- and HDL-GZxxx series.
-
-config ARCH_IQ80321
- bool "Enable support for IQ80321"
- help
- Say Y here if you want to run your kernel on the Intel IQ80321
- evaluation kit for the IOP321 processor.
-
-config ARCH_IQ31244
- bool "Enable support for EP80219/IQ31244"
- select MACH_EP80219
- help
- Say Y here if you want to run your kernel on the Intel EP80219
- evaluation kit for the Intel 80219 processor (a IOP321 variant)
- or the IQ31244 evaluation kit for the IOP321 processor.
-
-config MACH_N2100
- bool "Enable support for the Thecus n2100"
- help
- Say Y here if you want to run your kernel on the Thecus n2100
- NAS appliance.
-
-config MACH_EM7210
- bool "Enable support for the Lanner EM7210"
- help
- Say Y here if you want to run your kernel on the Lanner EM7210
- board. Say also Y here if you have a SS4000e Baxter Creek NAS
- appliance."
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile
deleted file mode 100644
index c8018ef5c6a9..000000000000
--- a/arch/arm/mach-iop32x/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-obj-$(CONFIG_ARCH_IOP32X) += irq.o
-obj-$(CONFIG_ARCH_IOP32X) += i2c.o
-obj-$(CONFIG_ARCH_IOP32X) += pci.o
-obj-$(CONFIG_ARCH_IOP32X) += setup.o
-obj-$(CONFIG_ARCH_IOP32X) += time.o
-obj-$(CONFIG_ARCH_IOP32X) += cp6.o
-obj-$(CONFIG_ARCH_IOP32X) += adma.o
-obj-$(CONFIG_ARCH_IOP32X) += pmu.o
-obj-$(CONFIG_ARCH_IOP32X) += restart.o
-
-obj-$(CONFIG_MACH_GLANTANK) += glantank.o
-obj-$(CONFIG_ARCH_IQ80321) += iq80321.o
-obj-$(CONFIG_ARCH_IQ31244) += iq31244.o
-obj-$(CONFIG_MACH_N2100) += n2100.o
-obj-$(CONFIG_MACH_EM7210) += em7210.o
diff --git a/arch/arm/mach-iop32x/Makefile.boot b/arch/arm/mach-iop32x/Makefile.boot
deleted file mode 100644
index 5c3af01c4000..000000000000
--- a/arch/arm/mach-iop32x/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
- zreladdr-y += 0xa0008000
-params_phys-y := 0xa0000100
-initrd_phys-y := 0xa0800000
diff --git a/arch/arm/mach-iop32x/adma.c b/arch/arm/mach-iop32x/adma.c
deleted file mode 100644
index 764bcbff98df..000000000000
--- a/arch/arm/mach-iop32x/adma.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * platform device definitions for the iop3xx dma/xor engines
- * Copyright © 2006, Intel Corporation.
- */
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_data/dma-iop32x.h>
-
-#include "iop3xx.h"
-#include "irqs.h"
-
-#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
-#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
-#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
-
-#define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
-#define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
-#define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
-
-#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
-#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
-#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
-
-/* AAU and DMA Channels */
-static struct resource iop3xx_dma_0_resources[] = {
- [0] = {
- .start = IOP3XX_DMA_PHYS_BASE(0),
- .end = IOP3XX_DMA_UPPER_PA(0),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMA0_EOT,
- .end = IRQ_DMA0_EOT,
- .flags = IORESOURCE_IRQ
- },
- [2] = {
- .start = IRQ_DMA0_EOC,
- .end = IRQ_DMA0_EOC,
- .flags = IORESOURCE_IRQ
- },
- [3] = {
- .start = IRQ_DMA0_ERR,
- .end = IRQ_DMA0_ERR,
- .flags = IORESOURCE_IRQ
- }
-};
-
-static struct resource iop3xx_dma_1_resources[] = {
- [0] = {
- .start = IOP3XX_DMA_PHYS_BASE(1),
- .end = IOP3XX_DMA_UPPER_PA(1),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_DMA1_EOT,
- .end = IRQ_DMA1_EOT,
- .flags = IORESOURCE_IRQ
- },
- [2] = {
- .start = IRQ_DMA1_EOC,
- .end = IRQ_DMA1_EOC,
- .flags = IORESOURCE_IRQ
- },
- [3] = {
- .start = IRQ_DMA1_ERR,
- .end = IRQ_DMA1_ERR,
- .flags = IORESOURCE_IRQ
- }
-};
-
-
-static struct resource iop3xx_aau_resources[] = {
- [0] = {
- .start = IOP3XX_AAU_PHYS_BASE,
- .end = IOP3XX_AAU_UPPER_PA,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_AA_EOT,
- .end = IRQ_AA_EOT,
- .flags = IORESOURCE_IRQ
- },
- [2] = {
- .start = IRQ_AA_EOC,
- .end = IRQ_AA_EOC,
- .flags = IORESOURCE_IRQ
- },
- [3] = {
- .start = IRQ_AA_ERR,
- .end = IRQ_AA_ERR,
- .flags = IORESOURCE_IRQ
- }
-};
-
-static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
-
-static struct iop_adma_platform_data iop3xx_dma_0_data = {
- .hw_id = DMA0_ID,
- .pool_size = PAGE_SIZE,
-};
-
-static struct iop_adma_platform_data iop3xx_dma_1_data = {
- .hw_id = DMA1_ID,
- .pool_size = PAGE_SIZE,
-};
-
-static struct iop_adma_platform_data iop3xx_aau_data = {
- .hw_id = AAU_ID,
- .pool_size = 3 * PAGE_SIZE,
-};
-
-struct platform_device iop3xx_dma_0_channel = {
- .name = "iop-adma",
- .id = 0,
- .num_resources = 4,
- .resource = iop3xx_dma_0_resources,
- .dev = {
- .dma_mask = &iop3xx_adma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = (void *) &iop3xx_dma_0_data,
- },
-};
-
-struct platform_device iop3xx_dma_1_channel = {
- .name = "iop-adma",
- .id = 1,
- .num_resources = 4,
- .resource = iop3xx_dma_1_resources,
- .dev = {
- .dma_mask = &iop3xx_adma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = (void *) &iop3xx_dma_1_data,
- },
-};
-
-struct platform_device iop3xx_aau_channel = {
- .name = "iop-adma",
- .id = 2,
- .num_resources = 4,
- .resource = iop3xx_aau_resources,
- .dev = {
- .dma_mask = &iop3xx_adma_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = (void *) &iop3xx_aau_data,
- },
-};
-
-static int __init iop3xx_adma_cap_init(void)
-{
- dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
- dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
-
- dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
- dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
-
- dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
- dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
-
- return 0;
-}
-
-arch_initcall(iop3xx_adma_cap_init);
diff --git a/arch/arm/mach-iop32x/cp6.c b/arch/arm/mach-iop32x/cp6.c
deleted file mode 100644
index 2882674a1c39..000000000000
--- a/arch/arm/mach-iop32x/cp6.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * IOP Coprocessor-6 access handler
- * Copyright (c) 2006, Intel Corporation.
- */
-#include <linux/init.h>
-#include <asm/traps.h>
-#include <asm/ptrace.h>
-
-void iop_enable_cp6(void)
-{
- u32 temp;
-
- /* enable cp6 access */
- asm volatile (
- "mrc p15, 0, %0, c15, c1, 0\n\t"
- "orr %0, %0, #(1 << 6)\n\t"
- "mcr p15, 0, %0, c15, c1, 0\n\t"
- "mrc p15, 0, %0, c15, c1, 0\n\t"
- "mov %0, %0\n\t"
- "sub pc, pc, #4 @ cp_wait\n\t"
- : "=r"(temp));
-}
-
-static int cp6_trap(struct pt_regs *regs, unsigned int instr)
-{
- iop_enable_cp6();
-
- return 0;
-}
-
-/* permit kernel space cp6 access
- * deny user space cp6 access
- */
-static struct undef_hook cp6_hook = {
- .instr_mask = 0x0f000ff0,
- .instr_val = 0x0e000610,
- .cpsr_mask = MODE_MASK,
- .cpsr_val = SVC_MODE,
- .fn = cp6_trap,
-};
-
-void __init iop_init_cp6_handler(void)
-{
- register_undef_hook(&cp6_hook);
-}
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
deleted file mode 100644
index d43ced3cd4e7..000000000000
--- a/arch/arm/mach-iop32x/em7210.c
+++ /dev/null
@@ -1,231 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-iop32x/em7210.c
- *
- * Board support code for the Lanner EM7210 platforms.
- *
- * Based on arch/arm/mach-iop32x/iq31244.c file.
- *
- * Copyright (C) 2007 Arnaud Patard <arnaud.patard@rtp-net.org>
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/pm.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/time.h>
-#include <asm/mach-types.h>
-
-#include "hardware.h"
-#include "gpio-iop32x.h"
-#include "irqs.h"
-
-static void __init em7210_timer_init(void)
-{
- /* http://www.kwaak.net/fotos/fotos-nas/slide_24.html */
- /* 33.333 MHz crystal. */
- iop_init_time(200000000);
-}
-
-/*
- * EM7210 RTC
- */
-static struct i2c_board_info __initdata em7210_i2c_devices[] = {
- {
- I2C_BOARD_INFO("rs5c372a", 0x32),
- },
-};
-
-/*
- * EM7210 I/O
- */
-static struct map_desc em7210_io_desc[] __initdata = {
- { /* on-board devices */
- .virtual = IQ31244_UART,
- .pfn = __phys_to_pfn(IQ31244_UART),
- .length = 0x00100000,
- .type = MT_DEVICE,
- },
-};
-
-void __init em7210_map_io(void)
-{
- iop3xx_map_io();
- iotable_init(em7210_io_desc, ARRAY_SIZE(em7210_io_desc));
-}
-
-
-/*
- * EM7210 PCI
- */
-#define INTA IRQ_IOP32X_XINT0
-#define INTB IRQ_IOP32X_XINT1
-#define INTC IRQ_IOP32X_XINT2
-#define INTD IRQ_IOP32X_XINT3
-
-static int __init
-em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- static int pci_irq_table[][4] = {
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {INTB, INTB, INTB, INTB}, /* console / uart */
- {INTA, INTA, INTA, INTA}, /* 1st 82541 */
- {INTD, INTD, INTD, INTD}, /* 2nd 82541 */
- {INTC, INTC, INTC, INTC}, /* GD31244 */
- {INTD, INTA, INTA, INTA}, /* mini-PCI */
- {INTD, INTC, INTA, INTA}, /* NEC USB */
- };
-
- if (pin < 1 || pin > 4)
- return -1;
-
- return pci_irq_table[slot % 6][pin - 1];
-}
-
-static struct hw_pci em7210_pci __initdata = {
- .nr_controllers = 1,
- .ops = &iop3xx_ops,
- .setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
- .map_irq = em7210_pci_map_irq,
-};
-
-static int __init em7210_pci_init(void)
-{
- if (machine_is_em7210())
- pci_common_init(&em7210_pci);
-
- return 0;
-}
-
-subsys_initcall(em7210_pci_init);
-
-
-/*
- * EM7210 Flash
- */
-static struct physmap_flash_data em7210_flash_data = {
- .width = 2,
-};
-
-static struct resource em7210_flash_resource = {
- .start = 0xf0000000,
- .end = 0xf1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device em7210_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &em7210_flash_data,
- },
- .num_resources = 1,
- .resource = &em7210_flash_resource,
-};
-
-
-/*
- * EM7210 UART
- * The physical address of the serial port is 0xfe800000,
- * so it can be used for physical and virtual address.
- */
-static struct plat_serial8250_port em7210_serial_port[] = {
- {
- .mapbase = IQ31244_UART,
- .membase = (char *)IQ31244_UART,
- .irq = IRQ_IOP32X_XINT1,
- .flags = UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- .regshift = 0,
- .uartclk = 1843200,
- },
- { },
-};
-
-static struct resource em7210_uart_resource = {
- .start = IQ31244_UART,
- .end = IQ31244_UART + 7,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device em7210_serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = em7210_serial_port,
- },
- .num_resources = 1,
- .resource = &em7210_uart_resource,
-};
-
-#define EM7210_HARDWARE_POWER 0
-
-void em7210_power_off(void)
-{
- int ret;
-
- ret = gpio_direction_output(EM7210_HARDWARE_POWER, 1);
- if (ret)
- pr_crit("could not drive power off GPIO high\n");
-}
-
-static int __init em7210_request_gpios(void)
-{
- int ret;
-
- if (!machine_is_em7210())
- return 0;
-
- ret = gpio_request(EM7210_HARDWARE_POWER, "power");
- if (ret) {
- pr_err("could not request power off GPIO\n");
- return 0;
- }
-
- pm_power_off = em7210_power_off;
-
- return 0;
-}
-device_initcall(em7210_request_gpios);
-
-static void __init em7210_init_machine(void)
-{
- register_iop32x_gpio();
- platform_device_register(&em7210_serial_device);
- gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
- gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup);
- platform_device_register(&iop3xx_i2c0_device);
- platform_device_register(&iop3xx_i2c1_device);
- platform_device_register(&em7210_flash_device);
- platform_device_register(&iop3xx_dma_0_channel);
- platform_device_register(&iop3xx_dma_1_channel);
-
- i2c_register_board_info(0, em7210_i2c_devices,
- ARRAY_SIZE(em7210_i2c_devices));
-}
-
-MACHINE_START(EM7210, "Lanner EM7210")
- .atag_offset = 0x100,
- .map_io = em7210_map_io,
- .init_irq = iop32x_init_irq,
- .init_time = em7210_timer_init,
- .init_machine = em7210_init_machine,
- .restart = iop3xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
deleted file mode 100644
index 2fe0f77d1f1d..000000000000
--- a/arch/arm/mach-iop32x/glantank.c
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-iop32x/glantank.c
- *
- * Board support code for the GLAN Tank.
- *
- * Copyright (C) 2006, 2007 Martin Michlmayr <tbm@cyrius.com>
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/f75375s.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/pm.h>
-#include <linux/string.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio/machine.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/time.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-
-#include "hardware.h"
-#include "gpio-iop32x.h"
-#include "irqs.h"
-
-/*
- * GLAN Tank timer tick configuration.
- */
-static void __init glantank_timer_init(void)
-{
- /* 33.333 MHz crystal. */
- iop_init_time(200000000);
-}
-
-
-/*
- * GLAN Tank I/O.
- */
-static struct map_desc glantank_io_desc[] __initdata = {
- { /* on-board devices */
- .virtual = GLANTANK_UART,
- .pfn = __phys_to_pfn(GLANTANK_UART),
- .length = 0x00100000,
- .type = MT_DEVICE
- },
-};
-
-void __init glantank_map_io(void)
-{
- iop3xx_map_io();
- iotable_init(glantank_io_desc, ARRAY_SIZE(glantank_io_desc));
-}
-
-
-/*
- * GLAN Tank PCI.
- */
-#define INTA IRQ_IOP32X_XINT0
-#define INTB IRQ_IOP32X_XINT1
-#define INTC IRQ_IOP32X_XINT2
-#define INTD IRQ_IOP32X_XINT3
-
-static int __init
-glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- static int pci_irq_table[][4] = {
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {INTD, INTD, INTD, INTD}, /* UART (8250) */
- {INTA, INTA, INTA, INTA}, /* Ethernet (E1000) */
- {INTB, INTB, INTB, INTB}, /* IDE (AEC6280R) */
- {INTC, INTC, INTC, INTC}, /* USB (NEC) */
- };
-
- BUG_ON(pin < 1 || pin > 4);
-
- return pci_irq_table[slot % 4][pin - 1];
-}
-
-static struct hw_pci glantank_pci __initdata = {
- .nr_controllers = 1,
- .ops = &iop3xx_ops,
- .setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
- .map_irq = glantank_pci_map_irq,
-};
-
-static int __init glantank_pci_init(void)
-{
- if (machine_is_glantank())
- pci_common_init(&glantank_pci);
-
- return 0;
-}
-
-subsys_initcall(glantank_pci_init);
-
-
-/*
- * GLAN Tank machine initialization.
- */
-static struct physmap_flash_data glantank_flash_data = {
- .width = 2,
-};
-
-static struct resource glantank_flash_resource = {
- .start = 0xf0000000,
- .end = 0xf007ffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device glantank_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &glantank_flash_data,
- },
- .num_resources = 1,
- .resource = &glantank_flash_resource,
-};
-
-static struct plat_serial8250_port glantank_serial_port[] = {
- {
- .mapbase = GLANTANK_UART,
- .membase = (char *)GLANTANK_UART,
- .irq = IRQ_IOP32X_XINT3,
- .flags = UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- .regshift = 0,
- .uartclk = 1843200,
- },
- { },
-};
-
-static struct resource glantank_uart_resource = {
- .start = GLANTANK_UART,
- .end = GLANTANK_UART + 7,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device glantank_serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = glantank_serial_port,
- },
- .num_resources = 1,
- .resource = &glantank_uart_resource,
-};
-
-static struct f75375s_platform_data glantank_f75375s = {
- .pwm = { 255, 255 },
- .pwm_enable = { 0, 0 },
-};
-
-static struct i2c_board_info __initdata glantank_i2c_devices[] = {
- {
- I2C_BOARD_INFO("rs5c372a", 0x32),
- },
- {
- I2C_BOARD_INFO("f75375", 0x2e),
- .platform_data = &glantank_f75375s,
- },
-};
-
-static void glantank_power_off(void)
-{
- __raw_writeb(0x01, IOMEM(0xfe8d0004));
-
- while (1)
- ;
-}
-
-static void __init glantank_init_machine(void)
-{
- register_iop32x_gpio();
- gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
- gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup);
- platform_device_register(&iop3xx_i2c0_device);
- platform_device_register(&iop3xx_i2c1_device);
- platform_device_register(&glantank_flash_device);
- platform_device_register(&glantank_serial_device);
- platform_device_register(&iop3xx_dma_0_channel);
- platform_device_register(&iop3xx_dma_1_channel);
-
- i2c_register_board_info(0, glantank_i2c_devices,
- ARRAY_SIZE(glantank_i2c_devices));
-
- pm_power_off = glantank_power_off;
-}
-
-MACHINE_START(GLANTANK, "GLAN Tank")
- /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
- .atag_offset = 0x100,
- .map_io = glantank_map_io,
- .init_irq = iop32x_init_irq,
- .init_time = glantank_timer_init,
- .init_machine = glantank_init_machine,
- .restart = iop3xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-iop32x/glantank.h b/arch/arm/mach-iop32x/glantank.h
deleted file mode 100644
index f38e86b82c3d..000000000000
--- a/arch/arm/mach-iop32x/glantank.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * IO-Data GLAN Tank board registers
- */
-
-#ifndef __GLANTANK_H
-#define __GLANTANK_H
-
-#define GLANTANK_UART 0xfe800000 /* UART */
-
-
-#endif
diff --git a/arch/arm/mach-iop32x/gpio-iop32x.h b/arch/arm/mach-iop32x/gpio-iop32x.h
deleted file mode 100644
index 20af87e4c5e8..000000000000
--- a/arch/arm/mach-iop32x/gpio-iop32x.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-static struct resource iop32x_gpio_res[] = {
- DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x07c4), 0x10),
-};
-
-static inline void register_iop32x_gpio(void)
-{
- platform_device_register_simple("gpio-iop", 0,
- iop32x_gpio_res,
- ARRAY_SIZE(iop32x_gpio_res));
-}
diff --git a/arch/arm/mach-iop32x/hardware.h b/arch/arm/mach-iop32x/hardware.h
deleted file mode 100644
index 43ab4fb8f9b0..000000000000
--- a/arch/arm/mach-iop32x/hardware.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __HARDWARE_H
-#define __HARDWARE_H
-
-#include <asm/types.h>
-
-/*
- * Note about PCI IO space mappings
- *
- * To make IO space accesses efficient, we store virtual addresses in
- * the IO resources.
- *
- * The PCI IO space is located at virtual 0xfe000000 from physical
- * 0x90000000. The PCI BARs must be programmed with physical addresses,
- * but when we read them, we convert them to virtual addresses. See
- * arch/arm/plat-iop/pci.c.
- */
-
-#ifndef __ASSEMBLY__
-void iop32x_init_irq(void);
-#endif
-
-
-/*
- * Generic chipset bits
- */
-#include "iop3xx.h"
-
-/*
- * Board specific bits
- */
-#include "glantank.h"
-#include "iq80321.h"
-#include "iq31244.h"
-#include "n2100.h"
-
-
-#endif
diff --git a/arch/arm/mach-iop32x/i2c.c b/arch/arm/mach-iop32x/i2c.c
deleted file mode 100644
index e422286af469..000000000000
--- a/arch/arm/mach-iop32x/i2c.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/plat-iop/i2c.c
- *
- * Author: Nicolas Pitre <nico@cam.org>
- * Copyright (C) 2001 MontaVista Software, Inc.
- * Copyright (C) 2004 Intel Corporation.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/fs.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_core.h>
-#include <linux/io.h>
-#include <linux/gpio/machine.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach/arch.h>
-
-#include "hardware.h"
-#include "iop3xx.h"
-#include "irqs.h"
-
-/*
- * Each of the I2C busses have corresponding GPIO lines, and the driver
- * need to access these directly to drive the bus low at times.
- */
-
-struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup = {
- .dev_id = "IOP3xx-I2C.0",
- .table = {
- GPIO_LOOKUP("gpio-iop", 7, "scl", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-iop", 6, "sda", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup = {
- .dev_id = "IOP3xx-I2C.1",
- .table = {
- GPIO_LOOKUP("gpio-iop", 5, "scl", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-iop", 4, "sda", GPIO_ACTIVE_HIGH),
- { }
- },
-};
-
-static struct resource iop3xx_i2c0_resources[] = {
- [0] = {
- .start = 0xfffff680,
- .end = 0xfffff697,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_IOP32X_I2C_0,
- .end = IRQ_IOP32X_I2C_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device iop3xx_i2c0_device = {
- .name = "IOP3xx-I2C",
- .id = 0,
- .num_resources = 2,
- .resource = iop3xx_i2c0_resources,
-};
-
-
-static struct resource iop3xx_i2c1_resources[] = {
- [0] = {
- .start = 0xfffff6a0,
- .end = 0xfffff6b7,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_IOP32X_I2C_1,
- .end = IRQ_IOP32X_I2C_1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-struct platform_device iop3xx_i2c1_device = {
- .name = "IOP3xx-I2C",
- .id = 1,
- .num_resources = 2,
- .resource = iop3xx_i2c1_resources,
-};
diff --git a/arch/arm/mach-iop32x/include/mach/irqs.h b/arch/arm/mach-iop32x/include/mach/irqs.h
deleted file mode 100644
index e09ae5f48aec..000000000000
--- a/arch/arm/mach-iop32x/include/mach/irqs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-iop32x/include/mach/irqs.h
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright: (C) 2002 Rory Bolt
- */
-
-#ifndef __IRQS_H
-#define __IRQS_H
-
-#define NR_IRQS 33
-
-#endif
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
deleted file mode 100644
index c8548875d942..000000000000
--- a/arch/arm/mach-iop32x/include/mach/uncompress.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-iop32x/include/mach/uncompress.h
- */
-
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <linux/serial_reg.h>
-
-#define uart_base ((volatile u8 *)0xfe800000)
-
-#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-
-static inline void putc(char c)
-{
- while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
- barrier();
- uart_base[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup() do { } while (0)
diff --git a/arch/arm/mach-iop32x/iop3xx.h b/arch/arm/mach-iop32x/iop3xx.h
deleted file mode 100644
index a6ec7ebadb35..000000000000
--- a/arch/arm/mach-iop32x/iop3xx.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Intel IOP32X and IOP33X register definitions
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- * Copyright (C) 2004 Intel Corp.
- */
-
-#ifndef __IOP3XX_H
-#define __IOP3XX_H
-
-/*
- * Peripherals that are shared between the iop32x and iop33x but
- * located at different addresses.
- */
-#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
-
-#include "iop3xx.h"
-
-/* ATU Parameters
- * set up a 1:1 bus to physical ram relationship
- * w/ physical ram on top of pci in the memory map
- */
-#define IOP32X_MAX_RAM_SIZE 0x40000000UL
-#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
-#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
-
-/*
- * IOP3XX GPIO handling
- */
-#define IOP3XX_GPIO_LINE(x) (x)
-
-#ifndef __ASSEMBLY__
-extern int init_atu;
-extern int iop3xx_get_init_atu(void);
-#endif
-
-
-/*
- * IOP3XX processor registers
- */
-#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
-#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
-#define IOP3XX_PERIPHERAL_SIZE 0x00002000
-#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
- IOP3XX_PERIPHERAL_SIZE - 1)
-#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
- IOP3XX_PERIPHERAL_SIZE - 1)
-#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
- (IOP3XX_PERIPHERAL_PHYS_BASE\
- - IOP3XX_PERIPHERAL_VIRT_BASE))
-#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
-
-/* Address Translation Unit */
-#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
-#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
-#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
-#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
-#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
-#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
-#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
-#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
-#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
-#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
-#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
-#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
-#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
-#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
-#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
-#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
-#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
-#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
-#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
-#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
-#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
-#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
-#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
-#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
-#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
-#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
-#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
-#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
-#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
-#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
-#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
-#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
-#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
-#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
-#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
-#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
-#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
-#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
-#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
-#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
-#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
-#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
-#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
-#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
-#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
-#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
-#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
-#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
-#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
-#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
-#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
-#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
-#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
-#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
-#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
-#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
-#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
-#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
-#define IOP3XX_ATUCR_OUT_EN (1 << 1)
-
-#define IOP3XX_INIT_ATU_DEFAULT 0
-#define IOP3XX_INIT_ATU_DISABLE -1
-#define IOP3XX_INIT_ATU_ENABLE 1
-
-/* Messaging Unit */
-#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
-#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
-#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
-#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
-#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
-#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
-#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
-#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
-#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
-#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
-#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
-#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
-#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
-#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
-#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
-#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
-#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
-#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
-#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
-#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
-#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
-
-/* DMA Controller */
-#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
- (0x400 + (chan << 6)))
-#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
-
-/* Peripheral bus interface */
-#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
-#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
-#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
-#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
-#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
-#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
-#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
-#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
-#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
-#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
-#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
-#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
-#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
-#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
-#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
-#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
-#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
-
-/* Peripheral performance monitoring unit */
-#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
-#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
-#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
-#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
-/* PERCR0 DOESN'T EXIST - index from 1! */
-#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
-
-/* Timers */
-#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
-#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
-#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
-#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
-#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
-#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
-#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
-#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
-#define IOP_TMR_EN 0x02
-#define IOP_TMR_RELOAD 0x04
-#define IOP_TMR_PRIVILEGED 0x08
-#define IOP_TMR_RATIO_1_1 0x00
-
-/* Watchdog timer definitions */
-#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
-#define IOP_WDTCR_EN 0xe1e1e1e1
-/* iop3xx does not support stopping the watchdog, so we just re-arm */
-#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
-#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
-
-/* Application accelerator unit */
-#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
-#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
-
-/* I2C bus interface unit */
-#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
-#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
-#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
-#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
-#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
-#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
-#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
-#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
-#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
-#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
-
-
-/*
- * IOP3XX I/O and Mem space regions for PCI autoconfiguration
- */
-#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
-#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
-
-#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
-#define IOP3XX_PCI_LOWER_IO_BA 0x00000000
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/reboot.h>
-
-void iop3xx_map_io(void);
-void iop_enable_cp6(void);
-void iop_init_cp6_handler(void);
-void iop_init_time(unsigned long tickrate);
-void iop3xx_restart(enum reboot_mode, const char *);
-
-static inline u32 read_tmr0(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
- return val;
-}
-
-static inline void write_tmr0(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
-}
-
-static inline void write_tmr1(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
-}
-
-static inline u32 read_tcr0(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
- return val;
-}
-
-static inline void write_tcr0(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
-}
-
-static inline u32 read_tcr1(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
- return val;
-}
-
-static inline void write_tcr1(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
-}
-
-static inline void write_trr0(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
-}
-
-static inline void write_trr1(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
-}
-
-static inline void write_tisr(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
-}
-
-static inline u32 read_wdtcr(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
- return val;
-}
-static inline void write_wdtcr(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
-}
-
-extern unsigned long get_iop_tick_rate(void);
-
-/* only iop13xx has these registers, we define these to present a
- * common register interface for the iop_wdt driver.
- */
-#define IOP_RCSR_WDT (0)
-static inline u32 read_rcsr(void)
-{
- return 0;
-}
-static inline void write_wdtsr(u32 val)
-{
- do { } while (0);
-}
-
-extern struct platform_device iop3xx_dma_0_channel;
-extern struct platform_device iop3xx_dma_1_channel;
-extern struct platform_device iop3xx_aau_channel;
-extern struct platform_device iop3xx_i2c0_device;
-extern struct platform_device iop3xx_i2c1_device;
-extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup;
-extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup;
-
-#endif
-
-
-#endif
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
deleted file mode 100644
index 49caaa703881..000000000000
--- a/arch/arm/mach-iop32x/iq31244.c
+++ /dev/null
@@ -1,332 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-iop32x/iq31244.c
- *
- * Board support code for the Intel EP80219 and IQ31244 platforms.
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- * Copyright 2003 (c) MontaVista, Software, Inc.
- * Copyright (C) 2004 Intel Corp.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/pm.h>
-#include <linux/string.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio/machine.h>
-#include <asm/cputype.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/time.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-
-#include "hardware.h"
-#include "irqs.h"
-#include "gpio-iop32x.h"
-
-/*
- * Until March of 2007 iq31244 platforms and ep80219 platforms shared the
- * same machine id, and the processor type was used to select board type.
- * However this assumption breaks for an iq80219 board which is an iop219
- * processor on an iq31244 board. The force_ep80219 flag has been added
- * for old boot loaders using the iq31244 machine id for an ep80219 platform.
- */
-static int force_ep80219;
-
-static int is_80219(void)
-{
- return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
-}
-
-static int is_ep80219(void)
-{
- if (machine_is_ep80219() || force_ep80219)
- return 1;
- else
- return 0;
-}
-
-
-/*
- * EP80219/IQ31244 timer tick configuration.
- */
-static void __init iq31244_timer_init(void)
-{
- if (is_ep80219()) {
- /* 33.333 MHz crystal. */
- iop_init_time(200000000);
- } else {
- /* 33.000 MHz crystal. */
- iop_init_time(198000000);
- }
-}
-
-
-/*
- * IQ31244 I/O.
- */
-static struct map_desc iq31244_io_desc[] __initdata = {
- { /* on-board devices */
- .virtual = IQ31244_UART,
- .pfn = __phys_to_pfn(IQ31244_UART),
- .length = 0x00100000,
- .type = MT_DEVICE,
- },
-};
-
-void __init iq31244_map_io(void)
-{
- iop3xx_map_io();
- iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
-}
-
-
-/*
- * EP80219/IQ31244 PCI.
- */
-static int __init
-ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- if (slot == 0) {
- /* CFlash */
- irq = IRQ_IOP32X_XINT1;
- } else if (slot == 1) {
- /* 82551 Pro 100 */
- irq = IRQ_IOP32X_XINT0;
- } else if (slot == 2) {
- /* PCI-X Slot */
- irq = IRQ_IOP32X_XINT3;
- } else if (slot == 3) {
- /* SATA */
- irq = IRQ_IOP32X_XINT2;
- } else {
- printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
- "device PCI:%d:%d:%d\n", dev->bus->number,
- PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
- irq = -1;
- }
-
- return irq;
-}
-
-static struct hw_pci ep80219_pci __initdata = {
- .nr_controllers = 1,
- .ops = &iop3xx_ops,
- .setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
- .map_irq = ep80219_pci_map_irq,
-};
-
-static int __init
-iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- if (slot == 0) {
- /* CFlash */
- irq = IRQ_IOP32X_XINT1;
- } else if (slot == 1) {
- /* SATA */
- irq = IRQ_IOP32X_XINT2;
- } else if (slot == 2) {
- /* PCI-X Slot */
- irq = IRQ_IOP32X_XINT3;
- } else if (slot == 3) {
- /* 82546 GigE */
- irq = IRQ_IOP32X_XINT0;
- } else {
- printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
- "device PCI:%d:%d:%d\n", dev->bus->number,
- PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
- irq = -1;
- }
-
- return irq;
-}
-
-static struct hw_pci iq31244_pci __initdata = {
- .nr_controllers = 1,
- .ops = &iop3xx_ops,
- .setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
- .map_irq = iq31244_pci_map_irq,
-};
-
-static int __init iq31244_pci_init(void)
-{
- if (is_ep80219())
- pci_common_init(&ep80219_pci);
- else if (machine_is_iq31244()) {
- if (is_80219()) {
- printk("note: iq31244 board type has been selected\n");
- printk("note: to select ep80219 operation:\n");
- printk("\t1/ specify \"force_ep80219\" on the kernel"
- " command line\n");
- printk("\t2/ update boot loader to pass"
- " the ep80219 id: %d\n", MACH_TYPE_EP80219);
- }
- pci_common_init(&iq31244_pci);
- }
-
- return 0;
-}
-
-subsys_initcall(iq31244_pci_init);
-
-
-/*
- * IQ31244 machine initialisation.
- */
-static struct physmap_flash_data iq31244_flash_data = {
- .width = 2,
-};
-
-static struct resource iq31244_flash_resource = {
- .start = 0xf0000000,
- .end = 0xf07fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device iq31244_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &iq31244_flash_data,
- },
- .num_resources = 1,
- .resource = &iq31244_flash_resource,
-};
-
-static struct plat_serial8250_port iq31244_serial_port[] = {
- {
- .mapbase = IQ31244_UART,
- .membase = (char *)IQ31244_UART,
- .irq = IRQ_IOP32X_XINT1,
- .flags = UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- .regshift = 0,
- .uartclk = 1843200,
- },
- { },
-};
-
-static struct resource iq31244_uart_resource = {
- .start = IQ31244_UART,
- .end = IQ31244_UART + 7,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device iq31244_serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = iq31244_serial_port,
- },
- .num_resources = 1,
- .resource = &iq31244_uart_resource,
-};
-
-/*
- * This function will send a SHUTDOWN_COMPLETE message to the PIC
- * controller over I2C. We are not using the i2c subsystem since
- * we are going to power off and it may be removed
- */
-void ep80219_power_off(void)
-{
- /*
- * Send the Address byte w/ the start condition
- */
- *IOP3XX_IDBR1 = 0x60;
- *IOP3XX_ICR1 = 0xE9;
- mdelay(1);
-
- /*
- * Send the START_MSG byte w/ no start or stop condition
- */
- *IOP3XX_IDBR1 = 0x0F;
- *IOP3XX_ICR1 = 0xE8;
- mdelay(1);
-
- /*
- * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
- * stop condition
- */
- *IOP3XX_IDBR1 = 0x03;
- *IOP3XX_ICR1 = 0xE8;
- mdelay(1);
-
- /*
- * Send an ignored byte w/ stop condition
- */
- *IOP3XX_IDBR1 = 0x00;
- *IOP3XX_ICR1 = 0xEA;
-
- while (1)
- ;
-}
-
-static void __init iq31244_init_machine(void)
-{
- register_iop32x_gpio();
- gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
- gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup);
- platform_device_register(&iop3xx_i2c0_device);
- platform_device_register(&iop3xx_i2c1_device);
- platform_device_register(&iq31244_flash_device);
- platform_device_register(&iq31244_serial_device);
- platform_device_register(&iop3xx_dma_0_channel);
- platform_device_register(&iop3xx_dma_1_channel);
-
- if (is_ep80219())
- pm_power_off = ep80219_power_off;
-
- if (!is_80219())
- platform_device_register(&iop3xx_aau_channel);
-}
-
-static int __init force_ep80219_setup(char *str)
-{
- force_ep80219 = 1;
- return 1;
-}
-
-__setup("force_ep80219", force_ep80219_setup);
-
-MACHINE_START(IQ31244, "Intel IQ31244")
- /* Maintainer: Intel Corp. */
- .atag_offset = 0x100,
- .map_io = iq31244_map_io,
- .init_irq = iop32x_init_irq,
- .init_time = iq31244_timer_init,
- .init_machine = iq31244_init_machine,
- .restart = iop3xx_restart,
-MACHINE_END
-
-/* There should have been an ep80219 machine identifier from the beginning.
- * Boot roms older than March 2007 do not know the ep80219 machine id. Pass
- * "force_ep80219" on the kernel command line, otherwise iq31244 operation
- * will be selected.
- */
-MACHINE_START(EP80219, "Intel EP80219")
- /* Maintainer: Intel Corp. */
- .atag_offset = 0x100,
- .map_io = iq31244_map_io,
- .init_irq = iop32x_init_irq,
- .init_time = iq31244_timer_init,
- .init_machine = iq31244_init_machine,
- .restart = iop3xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq31244.h b/arch/arm/mach-iop32x/iq31244.h
deleted file mode 100644
index a7ac691e48d3..000000000000
--- a/arch/arm/mach-iop32x/iq31244.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Intel IQ31244 evaluation board registers
- */
-
-#ifndef __IQ31244_H
-#define __IQ31244_H
-
-#define IQ31244_UART 0xfe800000 /* UART #1 */
-#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
-#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
-#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
-#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
-
-
-#endif
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
deleted file mode 100644
index b455d7073296..000000000000
--- a/arch/arm/mach-iop32x/iq80321.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-iop32x/iq80321.c
- *
- * Board support code for the Intel IQ80321 platform.
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- * Copyright (C) 2004 Intel Corp.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/string.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio/machine.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/time.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-
-#include "hardware.h"
-#include "irqs.h"
-#include "gpio-iop32x.h"
-
-/*
- * IQ80321 timer tick configuration.
- */
-static void __init iq80321_timer_init(void)
-{
- /* 33.333 MHz crystal. */
- iop_init_time(200000000);
-}
-
-
-/*
- * IQ80321 I/O.
- */
-static struct map_desc iq80321_io_desc[] __initdata = {
- { /* on-board devices */
- .virtual = IQ80321_UART,
- .pfn = __phys_to_pfn(IQ80321_UART),
- .length = 0x00100000,
- .type = MT_DEVICE,
- },
-};
-
-void __init iq80321_map_io(void)
-{
- iop3xx_map_io();
- iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
-}
-
-
-/*
- * IQ80321 PCI.
- */
-static int __init
-iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- if ((slot == 2 || slot == 6) && pin == 1) {
- /* PCI-X Slot INTA */
- irq = IRQ_IOP32X_XINT2;
- } else if ((slot == 2 || slot == 6) && pin == 2) {
- /* PCI-X Slot INTA */
- irq = IRQ_IOP32X_XINT3;
- } else if ((slot == 2 || slot == 6) && pin == 3) {
- /* PCI-X Slot INTA */
- irq = IRQ_IOP32X_XINT0;
- } else if ((slot == 2 || slot == 6) && pin == 4) {
- /* PCI-X Slot INTA */
- irq = IRQ_IOP32X_XINT1;
- } else if (slot == 4 || slot == 8) {
- /* Gig-E */
- irq = IRQ_IOP32X_XINT0;
- } else {
- printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
- "device PCI:%d:%d:%d\n", dev->bus->number,
- PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
- irq = -1;
- }
-
- return irq;
-}
-
-static struct hw_pci iq80321_pci __initdata = {
- .nr_controllers = 1,
- .ops = &iop3xx_ops,
- .setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit_cond,
- .map_irq = iq80321_pci_map_irq,
-};
-
-static int __init iq80321_pci_init(void)
-{
- if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
- machine_is_iq80321())
- pci_common_init(&iq80321_pci);
-
- return 0;
-}
-
-subsys_initcall(iq80321_pci_init);
-
-
-/*
- * IQ80321 machine initialisation.
- */
-static struct physmap_flash_data iq80321_flash_data = {
- .width = 1,
-};
-
-static struct resource iq80321_flash_resource = {
- .start = 0xf0000000,
- .end = 0xf07fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device iq80321_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &iq80321_flash_data,
- },
- .num_resources = 1,
- .resource = &iq80321_flash_resource,
-};
-
-static struct plat_serial8250_port iq80321_serial_port[] = {
- {
- .mapbase = IQ80321_UART,
- .membase = (char *)IQ80321_UART,
- .irq = IRQ_IOP32X_XINT1,
- .flags = UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- .regshift = 0,
- .uartclk = 1843200,
- },
- { },
-};
-
-static struct resource iq80321_uart_resource = {
- .start = IQ80321_UART,
- .end = IQ80321_UART + 7,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device iq80321_serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = iq80321_serial_port,
- },
- .num_resources = 1,
- .resource = &iq80321_uart_resource,
-};
-
-static void __init iq80321_init_machine(void)
-{
- register_iop32x_gpio();
- gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
- gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup);
- platform_device_register(&iop3xx_i2c0_device);
- platform_device_register(&iop3xx_i2c1_device);
- platform_device_register(&iq80321_flash_device);
- platform_device_register(&iq80321_serial_device);
- platform_device_register(&iop3xx_dma_0_channel);
- platform_device_register(&iop3xx_dma_1_channel);
- platform_device_register(&iop3xx_aau_channel);
-}
-
-MACHINE_START(IQ80321, "Intel IQ80321")
- /* Maintainer: Intel Corp. */
- .atag_offset = 0x100,
- .map_io = iq80321_map_io,
- .init_irq = iop32x_init_irq,
- .init_time = iq80321_timer_init,
- .init_machine = iq80321_init_machine,
- .restart = iop3xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321.h b/arch/arm/mach-iop32x/iq80321.h
deleted file mode 100644
index 3a5d10626ea6..000000000000
--- a/arch/arm/mach-iop32x/iq80321.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Intel IQ80321 evaluation board registers
- */
-
-#ifndef __IQ80321_H
-#define __IQ80321_H
-
-#define IQ80321_UART 0xfe800000 /* UART #1 */
-#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
-#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
-#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
-#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
-
-
-#endif
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
deleted file mode 100644
index 6dca7e97d81f..000000000000
--- a/arch/arm/mach-iop32x/irq.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-iop32x/irq.c
- *
- * Generic IOP32X IRQ handling functionality
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <asm/mach/irq.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include "hardware.h"
-
-static u32 iop32x_mask;
-
-static void intctl_write(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
-}
-
-static void intstr_write(u32 val)
-{
- asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
-}
-
-static u32 iintsrc_read(void)
-{
- int irq;
-
- asm volatile("mrc p6, 0, %0, c8, c0, 0" : "=r" (irq));
-
- return irq;
-}
-
-static void
-iop32x_irq_mask(struct irq_data *d)
-{
- iop32x_mask &= ~(1 << (d->irq - 1));
- intctl_write(iop32x_mask);
-}
-
-static void
-iop32x_irq_unmask(struct irq_data *d)
-{
- iop32x_mask |= 1 << (d->irq - 1);
- intctl_write(iop32x_mask);
-}
-
-struct irq_chip ext_chip = {
- .name = "IOP32x",
- .irq_ack = iop32x_irq_mask,
- .irq_mask = iop32x_irq_mask,
- .irq_unmask = iop32x_irq_unmask,
-};
-
-static void iop_handle_irq(struct pt_regs *regs)
-{
- u32 mask;
-
- iop_enable_cp6();
-
- do {
- mask = iintsrc_read();
- if (mask)
- generic_handle_irq(fls(mask));
- } while (mask);
-}
-
-void __init iop32x_init_irq(void)
-{
- int i;
-
- iop_init_cp6_handler();
- set_handle_irq(iop_handle_irq);
-
- intctl_write(0);
- intstr_write(0);
- if (machine_is_glantank() ||
- machine_is_iq80321() ||
- machine_is_iq31244() ||
- machine_is_n2100() ||
- machine_is_em7210())
- *IOP3XX_PCIIRSR = 0x0f;
-
- for (i = 1; i < NR_IRQS; i++) {
- irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
- irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-}
diff --git a/arch/arm/mach-iop32x/irqs.h b/arch/arm/mach-iop32x/irqs.h
deleted file mode 100644
index e1dfc8b4e7d7..000000000000
--- a/arch/arm/mach-iop32x/irqs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright: (C) 2002 Rory Bolt
- */
-
-#ifndef __IOP32X_IRQS_H
-#define __IOP32X_IRQS_H
-
-/* Interrupts in Linux start at 1, hardware starts at 0 */
-
-#define IOP_IRQ(x) ((x) + 1)
-
-/*
- * IOP80321 chipset interrupts
- */
-#define IRQ_IOP32X_DMA0_EOT IOP_IRQ(0)
-#define IRQ_IOP32X_DMA0_EOC IOP_IRQ(1)
-#define IRQ_IOP32X_DMA1_EOT IOP_IRQ(2)
-#define IRQ_IOP32X_DMA1_EOC IOP_IRQ(3)
-#define IRQ_IOP32X_AA_EOT IOP_IRQ(6)
-#define IRQ_IOP32X_AA_EOC IOP_IRQ(7)
-#define IRQ_IOP32X_CORE_PMON IOP_IRQ(8)
-#define IRQ_IOP32X_TIMER0 IOP_IRQ(9)
-#define IRQ_IOP32X_TIMER1 IOP_IRQ(10)
-#define IRQ_IOP32X_I2C_0 IOP_IRQ(11)
-#define IRQ_IOP32X_I2C_1 IOP_IRQ(12)
-#define IRQ_IOP32X_MESSAGING IOP_IRQ(13)
-#define IRQ_IOP32X_ATU_BIST IOP_IRQ(14)
-#define IRQ_IOP32X_PERFMON IOP_IRQ(15)
-#define IRQ_IOP32X_CORE_PMU IOP_IRQ(16)
-#define IRQ_IOP32X_BIU_ERR IOP_IRQ(17)
-#define IRQ_IOP32X_ATU_ERR IOP_IRQ(18)
-#define IRQ_IOP32X_MCU_ERR IOP_IRQ(19)
-#define IRQ_IOP32X_DMA0_ERR IOP_IRQ(20)
-#define IRQ_IOP32X_DMA1_ERR IOP_IRQ(21)
-#define IRQ_IOP32X_AA_ERR IOP_IRQ(23)
-#define IRQ_IOP32X_MSG_ERR IOP_IRQ(24)
-#define IRQ_IOP32X_SSP IOP_IRQ(25)
-#define IRQ_IOP32X_XINT0 IOP_IRQ(27)
-#define IRQ_IOP32X_XINT1 IOP_IRQ(28)
-#define IRQ_IOP32X_XINT2 IOP_IRQ(29)
-#define IRQ_IOP32X_XINT3 IOP_IRQ(30)
-#define IRQ_IOP32X_HPI IOP_IRQ(31)
-
-#endif
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
deleted file mode 100644
index bf99e718f8b8..000000000000
--- a/arch/arm/mach-iop32x/n2100.c
+++ /dev/null
@@ -1,366 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-iop32x/n2100.c
- *
- * Board support code for the Thecus N2100 platform.
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- * Copyright 2003 (c) MontaVista, Software, Inc.
- * Copyright (C) 2004 Intel Corp.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/f75375s.h>
-#include <linux/leds-pca9532.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/pm.h>
-#include <linux/string.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/time.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-
-#include "hardware.h"
-#include "irqs.h"
-#include "gpio-iop32x.h"
-
-/*
- * N2100 timer tick configuration.
- */
-static void __init n2100_timer_init(void)
-{
- /* 33.000 MHz crystal. */
- iop_init_time(198000000);
-}
-
-
-/*
- * N2100 I/O.
- */
-static struct map_desc n2100_io_desc[] __initdata = {
- { /* on-board devices */
- .virtual = N2100_UART,
- .pfn = __phys_to_pfn(N2100_UART),
- .length = 0x00100000,
- .type = MT_DEVICE
- },
-};
-
-void __init n2100_map_io(void)
-{
- iop3xx_map_io();
- iotable_init(n2100_io_desc, ARRAY_SIZE(n2100_io_desc));
-}
-
-
-/*
- * N2100 PCI.
- */
-static int n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- if (PCI_SLOT(dev->devfn) == 1) {
- /* RTL8110SB #1 */
- irq = IRQ_IOP32X_XINT0;
- } else if (PCI_SLOT(dev->devfn) == 2) {
- /* RTL8110SB #2 */
- irq = IRQ_IOP32X_XINT3;
- } else if (PCI_SLOT(dev->devfn) == 3) {
- /* Sil3512 */
- irq = IRQ_IOP32X_XINT2;
- } else if (PCI_SLOT(dev->devfn) == 4 && pin == 1) {
- /* VT6212 INTA */
- irq = IRQ_IOP32X_XINT1;
- } else if (PCI_SLOT(dev->devfn) == 4 && pin == 2) {
- /* VT6212 INTB */
- irq = IRQ_IOP32X_XINT0;
- } else if (PCI_SLOT(dev->devfn) == 4 && pin == 3) {
- /* VT6212 INTC */
- irq = IRQ_IOP32X_XINT2;
- } else if (PCI_SLOT(dev->devfn) == 5) {
- /* Mini-PCI slot */
- irq = IRQ_IOP32X_XINT3;
- } else {
- printk(KERN_ERR "n2100_pci_map_irq() called for unknown "
- "device PCI:%d:%d:%d\n", dev->bus->number,
- PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
- irq = -1;
- }
-
- return irq;
-}
-
-static struct hw_pci n2100_pci __initdata = {
- .nr_controllers = 1,
- .ops = &iop3xx_ops,
- .setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
- .map_irq = n2100_pci_map_irq,
-};
-
-/*
- * Both r8169 chips on the n2100 exhibit PCI parity problems. Turn
- * off parity reporting for both ports so we don't get error interrupts
- * for them.
- */
-static void n2100_fixup_r8169(struct pci_dev *dev)
-{
- if (dev->bus->number == 0 &&
- (dev->devfn == PCI_DEVFN(1, 0) ||
- dev->devfn == PCI_DEVFN(2, 0)))
- pci_disable_parity(dev);
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, PCI_ANY_ID, n2100_fixup_r8169);
-
-static int __init n2100_pci_init(void)
-{
- if (machine_is_n2100())
- pci_common_init(&n2100_pci);
-
- return 0;
-}
-
-subsys_initcall(n2100_pci_init);
-
-
-/*
- * N2100 machine initialisation.
- */
-static struct physmap_flash_data n2100_flash_data = {
- .width = 2,
-};
-
-static struct resource n2100_flash_resource = {
- .start = 0xf0000000,
- .end = 0xf0ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device n2100_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &n2100_flash_data,
- },
- .num_resources = 1,
- .resource = &n2100_flash_resource,
-};
-
-
-static struct plat_serial8250_port n2100_serial_port[] = {
- {
- .mapbase = N2100_UART,
- .membase = (char *)N2100_UART,
- .irq = 0,
- .flags = UPF_SKIP_TEST | UPF_AUTO_IRQ | UPF_SHARE_IRQ,
- .iotype = UPIO_MEM,
- .regshift = 0,
- .uartclk = 1843200,
- },
- { },
-};
-
-static struct resource n2100_uart_resource = {
- .start = N2100_UART,
- .end = N2100_UART + 7,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device n2100_serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = n2100_serial_port,
- },
- .num_resources = 1,
- .resource = &n2100_uart_resource,
-};
-
-static struct f75375s_platform_data n2100_f75375s = {
- .pwm = { 255, 255 },
- .pwm_enable = { 0, 0 },
-};
-
-static struct pca9532_platform_data n2100_leds = {
- .leds = {
- { .name = "n2100:red:satafail0",
- .state = PCA9532_OFF,
- .type = PCA9532_TYPE_LED,
- },
- { .name = "n2100:red:satafail1",
- .state = PCA9532_OFF,
- .type = PCA9532_TYPE_LED,
- },
- { .name = "n2100:blue:usb",
- .state = PCA9532_OFF,
- .type = PCA9532_TYPE_LED,
- },
- { .type = PCA9532_TYPE_NONE },
-
- { .type = PCA9532_TYPE_NONE },
- { .type = PCA9532_TYPE_NONE },
- { .type = PCA9532_TYPE_NONE },
- { .name = "n2100:red:usb",
- .state = PCA9532_OFF,
- .type = PCA9532_TYPE_LED,
- },
-
- { .type = PCA9532_TYPE_NONE }, /* power OFF gpio */
- { .type = PCA9532_TYPE_NONE }, /* reset gpio */
- { .type = PCA9532_TYPE_NONE },
- { .type = PCA9532_TYPE_NONE },
-
- { .type = PCA9532_TYPE_NONE },
- { .name = "n2100:orange:system",
- .state = PCA9532_OFF,
- .type = PCA9532_TYPE_LED,
- },
- { .name = "n2100:red:system",
- .state = PCA9532_OFF,
- .type = PCA9532_TYPE_LED,
- },
- { .name = "N2100 beeper" ,
- .state = PCA9532_OFF,
- .type = PCA9532_TYPE_N2100_BEEP,
- },
- },
- .psc = { 0, 0 },
- .pwm = { 0, 0 },
-};
-
-static struct i2c_board_info __initdata n2100_i2c_devices[] = {
- {
- I2C_BOARD_INFO("rs5c372b", 0x32),
- },
- {
- I2C_BOARD_INFO("f75375", 0x2e),
- .platform_data = &n2100_f75375s,
- },
- {
- I2C_BOARD_INFO("pca9532", 0x60),
- .platform_data = &n2100_leds,
- },
-};
-
-/*
- * Pull PCA9532 GPIO #8 low to power off the machine.
- */
-static void n2100_power_off(void)
-{
- local_irq_disable();
-
- /* Start condition, I2C address of PCA9532, write transaction. */
- *IOP3XX_IDBR0 = 0xc0;
- *IOP3XX_ICR0 = 0xe9;
- mdelay(1);
-
- /* Write address 0x08. */
- *IOP3XX_IDBR0 = 0x08;
- *IOP3XX_ICR0 = 0xe8;
- mdelay(1);
-
- /* Write data 0x01, stop condition. */
- *IOP3XX_IDBR0 = 0x01;
- *IOP3XX_ICR0 = 0xea;
-
- while (1)
- ;
-}
-
-static void n2100_restart(enum reboot_mode mode, const char *cmd)
-{
- int ret;
-
- ret = gpio_direction_output(N2100_HARDWARE_RESET, 0);
- if (ret) {
- pr_crit("could not drive reset GPIO low\n");
- return;
- }
- /* Wait for reset to happen */
- while (1)
- ;
-}
-
-
-static struct timer_list power_button_poll_timer;
-
-static void power_button_poll(struct timer_list *unused)
-{
- if (gpio_get_value(N2100_POWER_BUTTON) == 0) {
- ctrl_alt_del();
- return;
- }
-
- power_button_poll_timer.expires = jiffies + (HZ / 10);
- add_timer(&power_button_poll_timer);
-}
-
-static int __init n2100_request_gpios(void)
-{
- int ret;
-
- if (!machine_is_n2100())
- return 0;
-
- ret = gpio_request(N2100_HARDWARE_RESET, "reset");
- if (ret)
- pr_err("could not request reset GPIO\n");
-
- ret = gpio_request(N2100_POWER_BUTTON, "power");
- if (ret)
- pr_err("could not request power GPIO\n");
- else {
- ret = gpio_direction_input(N2100_POWER_BUTTON);
- if (ret)
- pr_err("could not set power GPIO as input\n");
- }
- /* Set up power button poll timer */
- timer_setup(&power_button_poll_timer, power_button_poll, 0);
- power_button_poll_timer.expires = jiffies + (HZ / 10);
- add_timer(&power_button_poll_timer);
- return 0;
-}
-device_initcall(n2100_request_gpios);
-
-static void __init n2100_init_machine(void)
-{
- register_iop32x_gpio();
- gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup);
- platform_device_register(&iop3xx_i2c0_device);
- platform_device_register(&n2100_flash_device);
- platform_device_register(&n2100_serial_device);
- platform_device_register(&iop3xx_dma_0_channel);
- platform_device_register(&iop3xx_dma_1_channel);
-
- i2c_register_board_info(0, n2100_i2c_devices,
- ARRAY_SIZE(n2100_i2c_devices));
-
- pm_power_off = n2100_power_off;
-}
-
-MACHINE_START(N2100, "Thecus N2100")
- /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
- .atag_offset = 0x100,
- .map_io = n2100_map_io,
- .init_irq = iop32x_init_irq,
- .init_time = n2100_timer_init,
- .init_machine = n2100_init_machine,
- .restart = n2100_restart,
-MACHINE_END
diff --git a/arch/arm/mach-iop32x/n2100.h b/arch/arm/mach-iop32x/n2100.h
deleted file mode 100644
index 0b97b940d3e7..000000000000
--- a/arch/arm/mach-iop32x/n2100.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Thecus N2100 board registers
- */
-
-#ifndef __N2100_H
-#define __N2100_H
-
-#define N2100_UART 0xfe800000 /* UART */
-
-#define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0)
-#define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2)
-#define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3)
-#define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4)
-#define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5)
-
-
-#endif
diff --git a/arch/arm/mach-iop32x/pci.c b/arch/arm/mach-iop32x/pci.c
deleted file mode 100644
index 7a215d2ee7e2..000000000000
--- a/arch/arm/mach-iop32x/pci.c
+++ /dev/null
@@ -1,404 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/plat-iop/pci.c
- *
- * PCI support for the Intel IOP32X and IOP33X processors
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/signal.h>
-#include <asm/mach/pci.h>
-#include "hardware.h"
-#include "iop3xx.h"
-
-// #define DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...) do { } while (0)
-#endif
-
-/*
- * This routine builds either a type0 or type1 configuration command. If the
- * bus is on the 803xx then a type0 made, else a type1 is created.
- */
-static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
-{
- struct pci_sys_data *sys = bus->sysdata;
- u32 addr;
-
- if (sys->busnr == bus->number)
- addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
- else
- addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
-
- addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
-
- return addr;
-}
-
-/*
- * This routine checks the status of the last configuration cycle. If an error
- * was detected it returns a 1, else it returns a 0. The errors being checked
- * are parity, master abort, target abort (master and target). These types of
- * errors occur during a config cycle where there is no device, like during
- * the discovery stage.
- */
-static int iop3xx_pci_status(void)
-{
- unsigned int status;
- int ret = 0;
-
- /*
- * Check the status registers.
- */
- status = *IOP3XX_ATUSR;
- if (status & 0xf900) {
- DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
- *IOP3XX_ATUSR = status & 0xf900;
- ret = 1;
- }
-
- status = *IOP3XX_ATUISR;
- if (status & 0x679f) {
- DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
- *IOP3XX_ATUISR = status & 0x679f;
- ret = 1;
- }
-
- return ret;
-}
-
-/*
- * Simply write the address register and read the configuration
- * data. Note that the 4 nops ensure that we are able to handle
- * a delayed abort (in theory.)
- */
-static u32 iop3xx_read(unsigned long addr)
-{
- u32 val;
-
- __asm__ __volatile__(
- "str %1, [%2]\n\t"
- "ldr %0, [%3]\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- : "=r" (val)
- : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
-
- return val;
-}
-
-/*
- * The read routines must check the error status of the last configuration
- * cycle. If there was an error, the routine returns all hex f's.
- */
-static int
-iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *value)
-{
- unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
- u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
-
- if (iop3xx_pci_status())
- val = 0xffffffff;
-
- *value = val;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 value)
-{
- unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
- u32 val;
-
- if (size != 4) {
- val = iop3xx_read(addr);
- if (iop3xx_pci_status())
- return PCIBIOS_SUCCESSFUL;
-
- where = (where & 3) * 8;
-
- if (size == 1)
- val &= ~(0xff << where);
- else
- val &= ~(0xffff << where);
-
- *IOP3XX_OCCDR = val | value << where;
- } else {
- asm volatile(
- "str %1, [%2]\n\t"
- "str %0, [%3]\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- :
- : "r" (value), "r" (addr),
- "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops iop3xx_ops = {
- .read = iop3xx_read_config,
- .write = iop3xx_write_config,
-};
-
-/*
- * When a PCI device does not exist during config cycles, the 80200 gets a
- * bus error instead of returning 0xffffffff. This handler simply returns.
- */
-static int
-iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
-{
- DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
- addr, fsr, regs->ARM_pc, regs->ARM_lr);
-
- /*
- * If it was an imprecise abort, then we need to correct the
- * return address to be _after_ the instruction.
- */
- if (fsr & (1 << 10))
- regs->ARM_pc += 4;
-
- return 0;
-}
-
-int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
-{
- struct resource *res;
- struct resource realio;
-
- if (nr != 0)
- return 0;
-
- res = kzalloc(sizeof(struct resource), GFP_KERNEL);
- if (!res)
- panic("PCI: unable to alloc resources");
-
- res->start = IOP3XX_PCI_LOWER_MEM_PA;
- res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
- res->name = "IOP3XX PCI Memory Space";
- res->flags = IORESOURCE_MEM;
- request_resource(&iomem_resource, res);
-
- /*
- * Use whatever translation is already setup.
- */
- sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
-
- pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
-
- realio.start = 0;
- realio.end = realio.start + SZ_64K - 1;
- pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA);
-
- return 1;
-}
-
-void __init iop3xx_atu_setup(void)
-{
- /* BAR 0 ( Disabled ) */
- *IOP3XX_IAUBAR0 = 0x0;
- *IOP3XX_IABAR0 = 0x0;
- *IOP3XX_IATVR0 = 0x0;
- *IOP3XX_IALR0 = 0x0;
-
- /* BAR 1 ( Disabled ) */
- *IOP3XX_IAUBAR1 = 0x0;
- *IOP3XX_IABAR1 = 0x0;
- *IOP3XX_IALR1 = 0x0;
-
- /* BAR 2 (1:1 mapping with Physical RAM) */
- /* Set limit and enable */
- *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
- *IOP3XX_IAUBAR2 = 0x0;
-
- /* Align the inbound bar with the base of memory */
- *IOP3XX_IABAR2 = PHYS_OFFSET |
- PCI_BASE_ADDRESS_MEM_TYPE_64 |
- PCI_BASE_ADDRESS_MEM_PREFETCH;
-
- *IOP3XX_IATVR2 = PHYS_OFFSET;
-
- /* Outbound window 0 */
- *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
- *IOP3XX_OUMWTVR0 = 0;
-
- /* Outbound window 1 */
- *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA +
- IOP3XX_PCI_MEM_WINDOW_SIZE / 2;
- *IOP3XX_OUMWTVR1 = 0;
-
- /* BAR 3 ( Disabled ) */
- *IOP3XX_IAUBAR3 = 0x0;
- *IOP3XX_IABAR3 = 0x0;
- *IOP3XX_IATVR3 = 0x0;
- *IOP3XX_IALR3 = 0x0;
-
- /* Setup the I/O Bar
- */
- *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
-
- /* Enable inbound and outbound cycles
- */
- *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
- PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
- *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN;
-}
-
-void __init iop3xx_atu_disable(void)
-{
- *IOP3XX_ATUCMD = 0;
- *IOP3XX_ATUCR = 0;
-
- /* wait for cycles to quiesce */
- while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY |
- IOP3XX_PCSR_IN_Q_BUSY))
- cpu_relax();
-
- /* BAR 0 ( Disabled ) */
- *IOP3XX_IAUBAR0 = 0x0;
- *IOP3XX_IABAR0 = 0x0;
- *IOP3XX_IATVR0 = 0x0;
- *IOP3XX_IALR0 = 0x0;
-
- /* BAR 1 ( Disabled ) */
- *IOP3XX_IAUBAR1 = 0x0;
- *IOP3XX_IABAR1 = 0x0;
- *IOP3XX_IALR1 = 0x0;
-
- /* BAR 2 ( Disabled ) */
- *IOP3XX_IAUBAR2 = 0x0;
- *IOP3XX_IABAR2 = 0x0;
- *IOP3XX_IATVR2 = 0x0;
- *IOP3XX_IALR2 = 0x0;
-
- /* BAR 3 ( Disabled ) */
- *IOP3XX_IAUBAR3 = 0x0;
- *IOP3XX_IABAR3 = 0x0;
- *IOP3XX_IATVR3 = 0x0;
- *IOP3XX_IALR3 = 0x0;
-
- /* Clear the outbound windows */
- *IOP3XX_OIOWTVR = 0;
-
- /* Outbound window 0 */
- *IOP3XX_OMWTVR0 = 0;
- *IOP3XX_OUMWTVR0 = 0;
-
- /* Outbound window 1 */
- *IOP3XX_OMWTVR1 = 0;
- *IOP3XX_OUMWTVR1 = 0;
-}
-
-/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
-int init_atu;
-
-int iop3xx_get_init_atu(void) {
- /* check if default has been overridden */
- if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
- return init_atu;
- else
- return IOP3XX_INIT_ATU_DISABLE;
-}
-
-static void __init iop3xx_atu_debug(void)
-{
- DBG("PCI: Intel IOP3xx PCI init.\n");
- DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
- *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
- DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
- *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
- DBG("PCI: Outbound IO window: PCI 0x%08x\n",
- *IOP3XX_OIOWTVR);
-
- DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
- *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
- DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
- *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
- DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
- *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
- DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
- *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
-
- DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
- 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
-
- DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
- DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
-
- hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
-}
-
-/* for platforms that might be host-bus-adapters */
-void __init iop3xx_pci_preinit_cond(void)
-{
- if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
- iop3xx_atu_disable();
- iop3xx_atu_setup();
- iop3xx_atu_debug();
- }
-}
-
-void __init iop3xx_pci_preinit(void)
-{
- pcibios_min_mem = 0;
-
- iop3xx_atu_disable();
- iop3xx_atu_setup();
- iop3xx_atu_debug();
-}
-
-/* allow init_atu to be user overridden */
-static int __init iop3xx_init_atu_setup(char *str)
-{
- init_atu = IOP3XX_INIT_ATU_DEFAULT;
- if (str) {
- while (*str != '\0') {
- switch (*str) {
- case 'y':
- case 'Y':
- init_atu = IOP3XX_INIT_ATU_ENABLE;
- break;
- case 'n':
- case 'N':
- init_atu = IOP3XX_INIT_ATU_DISABLE;
- break;
- case ',':
- case '=':
- break;
- default:
- printk(KERN_DEBUG "\"%s\" malformed at "
- "character: \'%c\'",
- __func__,
- *str);
- *(str + 1) = '\0';
- }
- str++;
- }
- }
-
- return 1;
-}
-
-__setup("iop3xx_init_atu", iop3xx_init_atu_setup);
-
diff --git a/arch/arm/mach-iop32x/pmu.c b/arch/arm/mach-iop32x/pmu.c
deleted file mode 100644
index bdbc7a3cb8a3..000000000000
--- a/arch/arm/mach-iop32x/pmu.c
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * PMU IRQ registration for the iop3xx xscale PMU families.
- * Copyright (C) 2010 Will Deacon, ARM Ltd.
- */
-
-#include <linux/platform_device.h>
-#include "irqs.h"
-
-static struct resource pmu_resource = {
- .start = IRQ_IOP32X_CORE_PMU,
- .end = IRQ_IOP32X_CORE_PMU,
- .flags = IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
- .name = "xscale-pmu",
- .id = -1,
- .resource = &pmu_resource,
- .num_resources = 1,
-};
-
-static int __init iop3xx_pmu_init(void)
-{
- platform_device_register(&pmu_device);
- return 0;
-}
-
-arch_initcall(iop3xx_pmu_init);
diff --git a/arch/arm/mach-iop32x/restart.c b/arch/arm/mach-iop32x/restart.c
deleted file mode 100644
index 3dfa54d3a7a8..000000000000
--- a/arch/arm/mach-iop32x/restart.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * restart.c
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- */
-#include <asm/system_misc.h>
-#include "hardware.h"
-#include "iop3xx.h"
-
-void iop3xx_restart(enum reboot_mode mode, const char *cmd)
-{
- *IOP3XX_PCSR = 0x30;
-
- /* Jump into ROM at address 0 */
- soft_restart(0);
-}
diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c
deleted file mode 100644
index a0a81c28a632..000000000000
--- a/arch/arm/mach-iop32x/setup.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/plat-iop/setup.c
- *
- * Author: Nicolas Pitre <nico@fluxnic.net>
- * Copyright (C) 2001 MontaVista Software, Inc.
- * Copyright (C) 2004 Intel Corporation.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <asm/mach/map.h>
-#include "iop3xx.h"
-
-/*
- * Standard IO mapping for all IOP3xx based systems. Note that
- * the IOP3xx OCCDR must be mapped uncached and unbuffered.
- */
-static struct map_desc iop3xx_std_desc[] __initdata = {
- { /* mem mapped registers */
- .virtual = IOP3XX_PERIPHERAL_VIRT_BASE,
- .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
- .length = IOP3XX_PERIPHERAL_SIZE,
- .type = MT_UNCACHED,
- },
-};
-
-void __init iop3xx_map_io(void)
-{
- iotable_init(iop3xx_std_desc, ARRAY_SIZE(iop3xx_std_desc));
-}
diff --git a/arch/arm/mach-iop32x/time.c b/arch/arm/mach-iop32x/time.c
deleted file mode 100644
index ae533b66fefd..000000000000
--- a/arch/arm/mach-iop32x/time.c
+++ /dev/null
@@ -1,179 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/plat-iop/time.c
- *
- * Timer code for IOP32x and IOP33x based systems
- *
- * Author: Deepak Saxena <dsaxena@mvista.com>
- *
- * Copyright 2002-2003 MontaVista Software Inc.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/timex.h>
-#include <linux/io.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/export.h>
-#include <linux/sched_clock.h>
-#include <asm/irq.h>
-#include <linux/uaccess.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-
-#include "hardware.h"
-#include "irqs.h"
-
-/*
- * Minimum clocksource/clockevent timer range in seconds
- */
-#define IOP_MIN_RANGE 4
-
-/*
- * IOP clocksource (free-running timer 1).
- */
-static u64 notrace iop_clocksource_read(struct clocksource *unused)
-{
- return 0xffffffffu - read_tcr1();
-}
-
-static struct clocksource iop_clocksource = {
- .name = "iop_timer1",
- .rating = 300,
- .read = iop_clocksource_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-/*
- * IOP sched_clock() implementation via its clocksource.
- */
-static u64 notrace iop_read_sched_clock(void)
-{
- return 0xffffffffu - read_tcr1();
-}
-
-/*
- * IOP clockevents (interrupting timer 0).
- */
-static int iop_set_next_event(unsigned long delta,
- struct clock_event_device *unused)
-{
- u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
-
- BUG_ON(delta == 0);
- write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
- write_tcr0(delta);
- write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
-
- return 0;
-}
-
-static unsigned long ticks_per_jiffy;
-
-static int iop_set_periodic(struct clock_event_device *evt)
-{
- u32 tmr = read_tmr0();
-
- write_tmr0(tmr & ~IOP_TMR_EN);
- write_tcr0(ticks_per_jiffy - 1);
- write_trr0(ticks_per_jiffy - 1);
- tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
-
- write_tmr0(tmr);
- return 0;
-}
-
-static int iop_set_oneshot(struct clock_event_device *evt)
-{
- u32 tmr = read_tmr0();
-
- /* ->set_next_event sets period and enables timer */
- tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
- write_tmr0(tmr);
- return 0;
-}
-
-static int iop_shutdown(struct clock_event_device *evt)
-{
- u32 tmr = read_tmr0();
-
- tmr &= ~IOP_TMR_EN;
- write_tmr0(tmr);
- return 0;
-}
-
-static int iop_resume(struct clock_event_device *evt)
-{
- u32 tmr = read_tmr0();
-
- tmr |= IOP_TMR_EN;
- write_tmr0(tmr);
- return 0;
-}
-
-static struct clock_event_device iop_clockevent = {
- .name = "iop_timer0",
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .rating = 300,
- .set_next_event = iop_set_next_event,
- .set_state_shutdown = iop_shutdown,
- .set_state_periodic = iop_set_periodic,
- .tick_resume = iop_resume,
- .set_state_oneshot = iop_set_oneshot,
-};
-
-static irqreturn_t
-iop_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
-
- write_tisr(1);
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static unsigned long iop_tick_rate;
-unsigned long get_iop_tick_rate(void)
-{
- return iop_tick_rate;
-}
-EXPORT_SYMBOL(get_iop_tick_rate);
-
-void __init iop_init_time(unsigned long tick_rate)
-{
- u32 timer_ctl;
- int irq = IRQ_IOP32X_TIMER0;
-
- sched_clock_register(iop_read_sched_clock, 32, tick_rate);
-
- ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
- iop_tick_rate = tick_rate;
-
- timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
- IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
-
- /*
- * Set up interrupting clockevent timer 0.
- */
- write_tmr0(timer_ctl & ~IOP_TMR_EN);
- write_tisr(1);
- if (request_irq(irq, iop_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
- "IOP Timer Tick", &iop_clockevent))
- pr_err("Failed to request irq() %d (IOP Timer Tick)\n", irq);
- iop_clockevent.cpumask = cpumask_of(0);
- clockevents_config_and_register(&iop_clockevent, tick_rate,
- 0xf, 0xfffffffe);
-
- /*
- * Set up free-running clocksource timer 1.
- */
- write_trr1(0xffffffff);
- write_tcr1(0xffffffff);
- write_tmr1(timer_ctl);
- clocksource_register_hz(&iop_clocksource, tick_rate);
-}
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index f41ba3f42fc8..cb46802f5ce5 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -1,22 +1,19 @@
# SPDX-License-Identifier: GPL-2.0-only
-if ARCH_IXP4XX
-
-menu "Intel IXP4xx Implementation Options"
-
-comment "IXP4xx Platforms"
-
-config MACH_IXP4XX_OF
- bool
- prompt "Device Tree IXP4xx boards"
- default y
+menuconfig ARCH_IXP4XX
+ bool "IXP4xx-based platforms"
+ depends on ARCH_MULTI_V5
+ depends on CPU_BIG_ENDIAN
select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
+ select CPU_XSCALE
+ select GPIO_IXP4XX
+ select GPIOLIB
+ select FORCE_PCI
select I2C
select I2C_IOP3XX
- select PCI
+ select IXP4XX_IRQ
+ select IXP4XX_TIMER
+ select USB_EHCI_BIG_ENDIAN_DESC
+ select USB_EHCI_BIG_ENDIAN_MMIO
select USE_OF
help
- Say 'Y' here to support Device Tree-based IXP4xx platforms.
-
-endmenu
-
-endif
+ Support for Intel's IXP4XX (XScale) family of processors.
diff --git a/arch/arm/mach-ixp4xx/Makefile.boot b/arch/arm/mach-ixp4xx/Makefile.boot
deleted file mode 100644
index 9b015bd1ef27..000000000000
--- a/arch/arm/mach-ixp4xx/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
- zreladdr-y += 0x00008000
-params_phys-y := 0x00000100
-
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
deleted file mode 100644
index 09e7663e6a55..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-ixp4xx/include/mach/uncompress.h
- *
- * Copyright (C) 2002 Intel Corporation.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- */
-
-#ifndef _ARCH_UNCOMPRESS_H_
-#define _ARCH_UNCOMPRESS_H_
-
-#include <asm/mach-types.h>
-#include <linux/serial_reg.h>
-
-#define IXP4XX_UART1_BASE_PHYS 0xc8000000
-#define IXP4XX_UART2_BASE_PHYS 0xc8001000
-
-#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
-
-volatile u32* uart_base;
-
-static inline void putc(int c)
-{
- /* Check THRE and TEMT bits before we transmit the character.
- */
- while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
- barrier();
-
- *uart_base = c;
-}
-
-static void flush(void)
-{
-}
-
-static __inline__ void __arch_decomp_setup(unsigned long arch_id)
-{
- /*
- * Some boards are using UART2 as console
- */
- if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
- machine_is_gateway7001() || machine_is_wg302v2() ||
- machine_is_devixp() || machine_is_miccpt() || machine_is_mic256())
- uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
- else
- uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
-}
-
-/*
- * arch_id is a variable in decompress_kernel()
- */
-#define arch_decomp_setup() __arch_decomp_setup(arch_id)
-
-#endif
diff --git a/arch/arm/mach-ixp4xx/ixp4xx-of.c b/arch/arm/mach-ixp4xx/ixp4xx-of.c
index f9904716ec7f..1b4d84a5b02f 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx-of.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx-of.c
@@ -2,51 +2,10 @@
/*
* IXP4xx Device Tree boot support
*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-/*
- * These are the only fixed phys to virt mappings we ever need
- * we put it right after the UART mapping at 0xffc80000-0xffc81fff
- */
-#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
-#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
-
-static struct map_desc ixp4xx_of_io_desc[] __initdata = {
- /*
- * This is needed for runtime system configuration checks,
- * such as reading if hardware so-and-so is present. This
- * could eventually be converted into a syscon once all boards
- * are converted to device tree.
- */
- {
- .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
- .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#ifdef CONFIG_DEBUG_UART_8250
- /* This is needed for LL-debug/earlyprintk/debug-macro.S */
- {
- .virtual = CONFIG_DEBUG_UART_VIRT,
- .pfn = __phys_to_pfn(CONFIG_DEBUG_UART_PHYS),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#endif
-};
-
-static void __init ixp4xx_of_map_io(void)
-{
- iotable_init(ixp4xx_of_io_desc, ARRAY_SIZE(ixp4xx_of_io_desc));
-}
/*
- * We handle 4 differen SoC families. These compatible strings are enough
+ * We handle 4 different SoC families. These compatible strings are enough
* to provide the core so that different boards can add their more detailed
* specifics.
*/
@@ -59,6 +18,5 @@ static const char *ixp4xx_of_board_compat[] = {
};
DT_MACHINE_START(IXP4XX_DT, "IXP4xx (Device Tree)")
- .map_io = ixp4xx_of_map_io,
.dt_compat = ixp4xx_of_board_compat,
MACHINE_END
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index cfd39f729f8e..de69cc2dd483 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -8,7 +8,6 @@ config ARCH_KEYSTONE
select ARCH_HAS_RESET_CONTROLLER
select ARM_ERRATA_798181 if SMP
select COMMON_CLK_KEYSTONE
- select ARCH_SUPPORTS_BIG_ENDIAN
select ZONE_DMA if ARM_LPAE
select PINCTRL
select PM_GENERIC_DOMAINS if PM
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index 739b38be5696..0c1d54aec60f 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -1,7 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-y := keystone.o smc.o
-
-obj-$(CONFIG_SMP) += platsmp.o
+obj-y := keystone.o
# PM domain driver for Keystone SOCs
obj-$(CONFIG_ARCH_KEYSTONE) += pm_domain.o
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index 2c647bdf8d25..aa352c2de313 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -18,7 +18,6 @@
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <asm/smp_plat.h>
#include <asm/memory.h>
#include "memory.h"
@@ -103,7 +102,6 @@ DT_MACHINE_START(KEYSTONE, "Keystone")
#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
.dma_zone_size = SZ_2G,
#endif
- .smp = smp_ops(keystone_smp_ops),
.init_machine = keystone_init,
.dt_compat = keystone_match,
.pv_fixup = keystone_pv_fixup,
diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h
index 438e531cc007..71ff8cd2ee4a 100644
--- a/arch/arm/mach-keystone/keystone.h
+++ b/arch/arm/mach-keystone/keystone.h
@@ -8,13 +8,8 @@
#ifndef __KEYSTONE_H__
#define __KEYSTONE_H__
-#define KEYSTONE_MON_CPU_UP_IDX 0x00
-
#ifndef __ASSEMBLER__
-extern const struct smp_operations keystone_smp_ops;
-extern void secondary_startup(void);
-extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr);
extern int keystone_pm_runtime_init(void);
#endif /* __ASSEMBLER__ */
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
deleted file mode 100644
index 673fcf3b34b1..000000000000
--- a/arch/arm/mach-keystone/platsmp.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Keystone SOC SMP platform code
- *
- * Copyright 2013 Texas Instruments, Inc.
- * Cyril Chemparathy <cyril@ti.com>
- * Santosh Shilimkar <santosh.shillimkar@ti.com>
- *
- * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-#include <linux/pgtable.h>
-
-#include <asm/smp_plat.h>
-#include <asm/prom.h>
-#include <asm/tlbflush.h>
-
-#include "keystone.h"
-
-static int keystone_smp_boot_secondary(unsigned int cpu,
- struct task_struct *idle)
-{
- unsigned long start = virt_to_idmap(&secondary_startup);
- int error;
-
- pr_debug("keystone-smp: booting cpu %d, vector %08lx\n",
- cpu, start);
-
- error = keystone_cpu_smc(KEYSTONE_MON_CPU_UP_IDX, cpu, start);
- if (error)
- pr_err("CPU %d bringup failed with %d\n", cpu, error);
-
- return error;
-}
-
-const struct smp_operations keystone_smp_ops __initconst = {
- .smp_boot_secondary = keystone_smp_boot_secondary,
-};
diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S
deleted file mode 100644
index 21ef75cf5370..000000000000
--- a/arch/arm/mach-keystone/smc.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Keystone Secure APIs
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- */
-
-#include <linux/linkage.h>
-
-/**
- * u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr)
- *
- * Low level CPU monitor API
- * @command: Monitor command.
- * @cpu: CPU Number
- * @addr: Kernel jump address for boot CPU
- *
- * Return: Non zero value on failure
- */
- .arch_extension sec
-ENTRY(keystone_cpu_smc)
- stmfd sp!, {r4-r11, lr}
- smc #0
- ldmfd sp!, {r4-r11, pc}
-ENDPROC(keystone_cpu_smc)
diff --git a/arch/arm/mach-lpc18xx/Makefile.boot b/arch/arm/mach-lpc18xx/Makefile.boot
deleted file mode 100644
index cec195d4fcba..000000000000
--- a/arch/arm/mach-lpc18xx/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-# Empty file waiting for deletion once Makefile.boot isn't needed any more.
-# Patch waits for application at
-# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-lpc18xx/board-dt.c b/arch/arm/mach-lpc18xx/board-dt.c
index fdcee78d1bc4..4729eb83401a 100644
--- a/arch/arm/mach-lpc18xx/board-dt.c
+++ b/arch/arm/mach-lpc18xx/board-dt.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree board file for NXP LPC18xx/43xx
*
* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index ec87c65f4536..35730d3696d0 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -3,6 +3,7 @@
config ARCH_LPC32XX
bool "NXP LPC32XX"
depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
select ARM_AMBA
select CLKSRC_LPC32XX
select CPU_ARM926T
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
deleted file mode 100644
index 37d09ddb27f8..000000000000
--- a/arch/arm/mach-lpc32xx/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
- zreladdr-y += 0x80008000
-params_phys-y := 0x80000100
-initrd_phys-y := 0x82000000
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index b27fa1b9f56c..2572bd89a5e8 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -1,13 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-lpc32xx/pm.c
*
* Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
* Modified by Kevin Wells <kevin.wells@nxp.com>
*
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2005 (c) MontaVista Software, Inc.
*/
/*
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
index 3f0a8282ef6f..a95c5e0e4038 100644
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -1,13 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-lpc32xx/suspend.S
*
* Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
* Modified by Kevin Wells <kevin.wells@nxp.com>
*
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2005 (c) MontaVista Software, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 9e0f592d87d8..35a3430c7942 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -30,6 +30,7 @@ config MACH_MT7623
config MACH_MT7629
bool "MediaTek MT7629 SoCs support"
default ARCH_MEDIATEK
+ select HAVE_ARM_ARCH_TIMER
config MACH_MT8127
bool "MediaTek MT8127 SoCs support"
diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
index 4b8ad728bb42..32ac60b89fdc 100644
--- a/arch/arm/mach-meson/platsmp.c
+++ b/arch/arm/mach-meson/platsmp.c
@@ -71,6 +71,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
}
sram_base = of_iomap(node, 0);
+ of_node_put(node);
if (!sram_base) {
pr_err("Couldn't map SRAM registers\n");
return;
@@ -91,6 +92,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
}
scu_base = of_iomap(node, 0);
+ of_node_put(node);
if (!scu_base) {
pr_err("Couldn't map SCU registers\n");
return;
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 0dd999212944..8c1d4402fd69 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MMP
bool "Marvell PXA168/910/MMP2/MMP3"
- depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
+ depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V7
select GPIO_PXA
select GPIOLIB
select PINCTRL
@@ -13,98 +13,6 @@ if ARCH_MMP
menu "Marvell PXA168/910/MMP2 Implementations"
-if ATAGS
-
-config MACH_ASPENITE
- bool "Marvell's PXA168 Aspenite Development Board"
- depends on ARCH_MULTI_V5
- select CPU_PXA168
- help
- Say 'Y' here if you want to support the Marvell PXA168-based
- Aspenite Development Board.
-
-config MACH_ZYLONITE2
- bool "Marvell's PXA168 Zylonite2 Development Board"
- depends on ARCH_MULTI_V5
- select CPU_PXA168
- help
- Say 'Y' here if you want to support the Marvell PXA168-based
- Zylonite2 Development Board.
-
-config MACH_AVENGERS_LITE
- bool "Marvell's PXA168 Avengers Lite Development Board"
- depends on ARCH_MULTI_V5
- select CPU_PXA168
- help
- Say 'Y' here if you want to support the Marvell PXA168-based
- Avengers Lite Development Board.
-
-config MACH_TAVOREVB
- bool "Marvell's PXA910 TavorEVB Development Board"
- depends on ARCH_MULTI_V5
- select CPU_PXA910
- help
- Say 'Y' here if you want to support the Marvell PXA910-based
- TavorEVB Development Board.
-
-config MACH_TTC_DKB
- bool "Marvell's PXA910 TavorEVB Development Board"
- depends on ARCH_MULTI_V5
- select CPU_PXA910
- help
- Say 'Y' here if you want to support the Marvell PXA910-based
- TTC_DKB Development Board.
-
-config MACH_BROWNSTONE
- bool "Marvell's Brownstone Development Platform"
- depends on ARCH_MULTI_V7
- select CPU_MMP2
- help
- Say 'Y' here if you want to support the Marvell MMP2-based
- Brown Development Platform.
- MMP2-based board can't be co-existed with PXA168-based &
- PXA910-based development board. Since MMP2 is compatible to
- ARMv7 architecture.
-
-config MACH_FLINT
- bool "Marvell's Flint Development Platform"
- depends on ARCH_MULTI_V7
- select CPU_MMP2
- help
- Say 'Y' here if you want to support the Marvell MMP2-based
- Flint Development Platform.
- MMP2-based board can't be co-existed with PXA168-based &
- PXA910-based development board. Since MMP2 is compatible to
- ARMv7 architecture.
-
-config MACH_MARVELL_JASPER
- bool "Marvell's Jasper Development Platform"
- depends on ARCH_MULTI_V7
- select CPU_MMP2
- help
- Say 'Y' here if you want to support the Marvell MMP2-base
- Jasper Development Platform.
- MMP2-based board can't be co-existed with PXA168-based &
- PXA910-based development board. Since MMP2 is compatible to
- ARMv7 architecture.
-
-config MACH_TETON_BGA
- bool "Marvell's PXA168 Teton BGA Development Board"
- depends on ARCH_MULTI_V5
- select CPU_PXA168
- help
- Say 'Y' here if you want to support the Marvell PXA168-based
- Teton BGA Development Board.
-
-config MACH_GPLUGD
- bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
- depends on ARCH_MULTI_V5
- select CPU_PXA168
- help
- Say 'Y' here if you want to support the Marvell PXA168-based
- GuruPlug Display (gplugD) Board
-endif
-
config MACH_MMP_DT
bool "Support MMP (ARMv5) platforms from device tree"
depends on ARCH_MULTI_V5
@@ -168,13 +76,4 @@ config CPU_MMP2
help
Select code specific to MMP2. MMP2 is ARMv7 compatible.
-config USB_EHCI_MV_U2O
- bool "EHCI support for PXA USB OTG controller"
- depends on USB_EHCI_MV
- help
- Enables support for OTG controller which can be switched to host mode.
-
-config MMP_SRAM
- bool
-
endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index e3758f7e1fe7..5d4a1a4a48cf 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,35 +2,13 @@
#
# Makefile for Marvell's PXA168 processors line
#
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-pxa/include
+obj-y += common.o time.o
-obj-y += common.o devices.o time.o
-
-# SoC support
-obj-$(CONFIG_CPU_PXA168) += pxa168.o
-obj-$(CONFIG_CPU_PXA910) += pxa910.o
-obj-$(CONFIG_CPU_MMP2) += mmp2.o
-obj-$(CONFIG_MMP_SRAM) += sram.o
-
-ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
-obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
-endif
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o
endif
# board support
-obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
-obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
-obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
-obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
-obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
-obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
-obj-$(CONFIG_MACH_FLINT) += flint.o
-obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o
-obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
-obj-$(CONFIG_MACH_GPLUGD) += gplugd.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
deleted file mode 100644
index 6314824b62fc..000000000000
--- a/arch/arm/mach-mmp/aspenite.c
+++ /dev/null
@@ -1,284 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/aspenite.c
- *
- * Support for the Marvell PXA168-based Aspenite and Zylonite2
- * Development Platform.
- */
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/smc91x.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/interrupt.h>
-#include <linux/platform_data/mv_usb.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <video/pxa168fb.h>
-#include <linux/input.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-
-#include "addr-map.h"
-#include "mfp-pxa168.h"
-#include "pxa168.h"
-#include "pxa910.h"
-#include "irqs.h"
-#include "common.h"
-
-static unsigned long common_pin_config[] __initdata = {
- /* Data Flash Interface */
- GPIO0_DFI_D15,
- GPIO1_DFI_D14,
- GPIO2_DFI_D13,
- GPIO3_DFI_D12,
- GPIO4_DFI_D11,
- GPIO5_DFI_D10,
- GPIO6_DFI_D9,
- GPIO7_DFI_D8,
- GPIO8_DFI_D7,
- GPIO9_DFI_D6,
- GPIO10_DFI_D5,
- GPIO11_DFI_D4,
- GPIO12_DFI_D3,
- GPIO13_DFI_D2,
- GPIO14_DFI_D1,
- GPIO15_DFI_D0,
-
- /* Static Memory Controller */
- GPIO18_SMC_nCS0,
- GPIO34_SMC_nCS1,
- GPIO23_SMC_nLUA,
- GPIO25_SMC_nLLA,
- GPIO28_SMC_RDY,
- GPIO29_SMC_SCLK,
- GPIO35_SMC_BE1,
- GPIO36_SMC_BE2,
- GPIO27_GPIO, /* Ethernet IRQ */
-
- /* UART1 */
- GPIO107_UART1_RXD,
- GPIO108_UART1_TXD,
-
- /* SSP1 */
- GPIO113_I2S_MCLK,
- GPIO114_I2S_FRM,
- GPIO115_I2S_BCLK,
- GPIO116_I2S_RXD,
- GPIO117_I2S_TXD,
-
- /* LCD */
- GPIO56_LCD_FCLK_RD,
- GPIO57_LCD_LCLK_A0,
- GPIO58_LCD_PCLK_WR,
- GPIO59_LCD_DENA_BIAS,
- GPIO60_LCD_DD0,
- GPIO61_LCD_DD1,
- GPIO62_LCD_DD2,
- GPIO63_LCD_DD3,
- GPIO64_LCD_DD4,
- GPIO65_LCD_DD5,
- GPIO66_LCD_DD6,
- GPIO67_LCD_DD7,
- GPIO68_LCD_DD8,
- GPIO69_LCD_DD9,
- GPIO70_LCD_DD10,
- GPIO71_LCD_DD11,
- GPIO72_LCD_DD12,
- GPIO73_LCD_DD13,
- GPIO74_LCD_DD14,
- GPIO75_LCD_DD15,
- GPIO76_LCD_DD16,
- GPIO77_LCD_DD17,
- GPIO78_LCD_DD18,
- GPIO79_LCD_DD19,
- GPIO80_LCD_DD20,
- GPIO81_LCD_DD21,
- GPIO82_LCD_DD22,
- GPIO83_LCD_DD23,
-
- /* Keypad */
- GPIO109_KP_MKIN1,
- GPIO110_KP_MKIN0,
- GPIO111_KP_MKOUT7,
- GPIO112_KP_MKOUT6,
- GPIO121_KP_MKIN4,
-};
-
-static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = SMC_CS1_PHYS_BASE + 0x300,
- .end = SMC_CS1_PHYS_BASE + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = MMP_GPIO_TO_IRQ(27),
- .end = MMP_GPIO_TO_IRQ(27),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &smc91x_info,
- },
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static struct mtd_partition aspenite_nand_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_1M,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_8M,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = (SZ_2M + SZ_1M),
- .mask_flags = 0,
- }, {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_32M + SZ_16M,
- .mask_flags = 0,
- }
-};
-
-static struct pxa3xx_nand_platform_data aspenite_nand_info = {
- .parts = aspenite_nand_partitions,
- .nr_parts = ARRAY_SIZE(aspenite_nand_partitions),
-};
-
-static struct i2c_board_info aspenite_i2c_info[] __initdata = {
- { I2C_BOARD_INFO("wm8753", 0x1b), },
-};
-
-static struct fb_videomode video_modes[] = {
- [0] = {
- .pixclock = 30120,
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .hsync_len = 1,
- .left_margin = 215,
- .right_margin = 40,
- .vsync_len = 1,
- .upper_margin = 34,
- .lower_margin = 10,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
- },
-};
-
-struct pxa168fb_mach_info aspenite_lcd_info = {
- .id = "Graphic Frame",
- .modes = video_modes,
- .num_modes = ARRAY_SIZE(video_modes),
- .pix_fmt = PIX_FMT_RGB565,
- .io_pin_allocation_mode = PIN_MODE_DUMB_24,
- .dumb_mode = DUMB_MODE_RGB888,
- .active = 1,
- .panel_rbswap = 0,
- .invert_pixclock = 0,
-};
-
-static const unsigned int aspenite_matrix_key_map[] = {
- KEY(0, 6, KEY_UP), /* SW 4 */
- KEY(0, 7, KEY_DOWN), /* SW 5 */
- KEY(1, 6, KEY_LEFT), /* SW 6 */
- KEY(1, 7, KEY_RIGHT), /* SW 7 */
- KEY(4, 6, KEY_ENTER), /* SW 8 */
- KEY(4, 7, KEY_ESC), /* SW 9 */
-};
-
-static struct matrix_keymap_data aspenite_matrix_keymap_data = {
- .keymap = aspenite_matrix_key_map,
- .keymap_size = ARRAY_SIZE(aspenite_matrix_key_map),
-};
-
-static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
- .matrix_key_rows = 5,
- .matrix_key_cols = 8,
- .matrix_keymap_data = &aspenite_matrix_keymap_data,
- .debounce_interval = 30,
-};
-
-#if IS_ENABLED(CONFIG_USB_EHCI_MV)
-static struct mv_usb_platform_data pxa168_sph_pdata = {
- .mode = MV_USB_MODE_HOST,
- .phy_init = pxa_usb_phy_init,
- .phy_deinit = pxa_usb_phy_deinit,
- .set_vbus = NULL,
-};
-#endif
-
-static void __init common_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(common_pin_config));
-
- /* on-chip devices */
- pxa168_add_uart(1);
- pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
- pxa168_add_ssp(1);
- pxa168_add_nand(&aspenite_nand_info);
- pxa168_add_fb(&aspenite_lcd_info);
- pxa168_add_keypad(&aspenite_keypad_info);
- platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&pxa168_device_gpio);
-
- /* off-chip devices */
- platform_device_register(&smc91x_device);
-
-#if IS_ENABLED(CONFIG_USB_SUPPORT)
-#if IS_ENABLED(CONFIG_PHY_PXA_USB)
- platform_device_register(&pxa168_device_usb_phy);
-#endif
-
-#if IS_ENABLED(CONFIG_USB_EHCI_MV)
- pxa168_add_usb_host(&pxa168_sph_pdata);
-#endif
-#endif
-}
-
-MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
- .map_io = mmp_map_io,
- .nr_irqs = MMP_NR_IRQS,
- .init_irq = pxa168_init_irq,
- .init_time = pxa168_timer_init,
- .init_machine = common_init,
- .restart = pxa168_restart,
-MACHINE_END
-
-MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
- .map_io = mmp_map_io,
- .nr_irqs = MMP_NR_IRQS,
- .init_irq = pxa168_init_irq,
- .init_time = pxa168_timer_init,
- .init_machine = common_init,
- .restart = pxa168_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
deleted file mode 100644
index 12e5a9441df9..000000000000
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/avengers_lite.c
- *
- * Support for the Marvell PXA168-based Avengers lite Development Platform.
- *
- * Copyright (C) 2009-2010 Marvell International Ltd.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/gpio-pxa.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "addr-map.h"
-#include "mfp-pxa168.h"
-#include "pxa168.h"
-#include "irqs.h"
-
-
-#include "common.h"
-#include <linux/delay.h>
-
-/* Avengers lite MFP configurations */
-static unsigned long avengers_lite_pin_config_V16F[] __initdata = {
- /* DEBUG_UART */
- GPIO88_UART2_TXD,
- GPIO89_UART2_RXD,
-};
-
-static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static void __init avengers_lite_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F));
-
- /* on-chip devices */
- pxa168_add_uart(2);
- platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&pxa168_device_gpio);
-}
-
-MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
- .map_io = mmp_map_io,
- .nr_irqs = MMP_NR_IRQS,
- .init_irq = pxa168_init_irq,
- .init_time = pxa168_timer_init,
- .init_machine = avengers_lite_init,
- .restart = pxa168_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
deleted file mode 100644
index ce93bc395546..000000000000
--- a/arch/arm/mach-mmp/brownstone.c
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/brownstone.c
- *
- * Support for the Marvell Brownstone Development Platform.
- *
- * Copyright (C) 2009-2010 Marvell International Ltd.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio-pxa.h>
-#include <linux/gpio/machine.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/max8649.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/max8925.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "addr-map.h"
-#include "mfp-mmp2.h"
-#include "mmp2.h"
-#include "irqs.h"
-
-#include "common.h"
-
-#define BROWNSTONE_NR_IRQS (MMP_NR_IRQS + 40)
-
-#define GPIO_5V_ENABLE (89)
-
-static unsigned long brownstone_pin_config[] __initdata = {
- /* UART1 */
- GPIO29_UART1_RXD,
- GPIO30_UART1_TXD,
-
- /* UART3 */
- GPIO51_UART3_RXD,
- GPIO52_UART3_TXD,
-
- /* DFI */
- GPIO168_DFI_D0,
- GPIO167_DFI_D1,
- GPIO166_DFI_D2,
- GPIO165_DFI_D3,
- GPIO107_DFI_D4,
- GPIO106_DFI_D5,
- GPIO105_DFI_D6,
- GPIO104_DFI_D7,
- GPIO111_DFI_D8,
- GPIO164_DFI_D9,
- GPIO163_DFI_D10,
- GPIO162_DFI_D11,
- GPIO161_DFI_D12,
- GPIO110_DFI_D13,
- GPIO109_DFI_D14,
- GPIO108_DFI_D15,
- GPIO143_ND_nCS0,
- GPIO144_ND_nCS1,
- GPIO147_ND_nWE,
- GPIO148_ND_nRE,
- GPIO150_ND_ALE,
- GPIO149_ND_CLE,
- GPIO112_ND_RDY0,
- GPIO160_ND_RDY1,
-
- /* PMIC */
- PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
-
- /* MMC0 */
- GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
- GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
- GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
- GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
- GPIO136_MMC1_CMD | MFP_PULL_HIGH,
- GPIO139_MMC1_CLK,
- GPIO140_MMC1_CD | MFP_PULL_LOW,
- GPIO141_MMC1_WP | MFP_PULL_LOW,
-
- /* MMC1 */
- GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
- GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
- GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
- GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
- GPIO41_MMC2_CMD | MFP_PULL_HIGH,
- GPIO42_MMC2_CLK,
-
- /* MMC2 */
- GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
- GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
- GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
- GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
- GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
- GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
- GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
- GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
- GPIO112_MMC3_CMD | MFP_PULL_HIGH,
- GPIO151_MMC3_CLK,
-
- /* 5V regulator */
- GPIO89_GPIO,
-};
-
-static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static struct regulator_consumer_supply max8649_supply[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data max8649_init_data = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 1150000,
- .max_uV = 1280000,
- .always_on = 1,
- .boot_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &max8649_supply[0],
-};
-
-static struct max8649_platform_data brownstone_max8649_info = {
- .mode = 2, /* VID1 = 1, VID0 = 0 */
- .extclk = 0,
- .ramp_timing = MAX8649_RAMP_32MV,
- .regulator = &max8649_init_data,
-};
-
-static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
- REGULATOR_SUPPLY("v_5vp", NULL),
-};
-
-static struct regulator_init_data brownstone_v_5vp_data = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies),
- .consumer_supplies = brownstone_v_5vp_supplies,
-};
-
-static struct fixed_voltage_config brownstone_v_5vp = {
- .supply_name = "v_5vp",
- .microvolts = 5000000,
- .enabled_at_boot = 1,
- .init_data = &brownstone_v_5vp_data,
-};
-
-static struct platform_device brownstone_v_5vp_device = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &brownstone_v_5vp,
- },
-};
-
-static struct gpiod_lookup_table brownstone_v_5vp_gpiod_table = {
- .dev_id = "reg-fixed-voltage.1", /* .id set to 1 above */
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_5V_ENABLE,
- NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct max8925_platform_data brownstone_max8925_info = {
- .irq_base = MMP_NR_IRQS,
-};
-
-static struct i2c_board_info brownstone_twsi1_info[] = {
- [0] = {
- .type = "max8649",
- .addr = 0x60,
- .platform_data = &brownstone_max8649_info,
- },
- [1] = {
- .type = "max8925",
- .addr = 0x3c,
- .irq = IRQ_MMP2_PMIC,
- .platform_data = &brownstone_max8925_info,
- },
-};
-
-static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
- .clk_delay_cycles = 0x1f,
-};
-
-static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
- .clk_delay_cycles = 0x1f,
- .flags = PXA_FLAG_CARD_PERMANENT
- | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
-};
-
-static struct sram_platdata mmp2_asram_platdata = {
- .pool_name = "asram",
- .granularity = SRAM_GRANULARITY,
-};
-
-static struct sram_platdata mmp2_isram_platdata = {
- .pool_name = "isram",
- .granularity = SRAM_GRANULARITY,
-};
-
-static void __init brownstone_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
-
- /* on-chip devices */
- mmp2_add_uart(1);
- mmp2_add_uart(3);
- platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&mmp2_device_gpio);
- mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
- mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
- mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
- mmp2_add_asram(&mmp2_asram_platdata);
- mmp2_add_isram(&mmp2_isram_platdata);
-
- /* enable 5v regulator */
- gpiod_add_lookup_table(&brownstone_v_5vp_gpiod_table);
- platform_device_register(&brownstone_v_5vp_device);
-}
-
-MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
- /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
- .map_io = mmp_map_io,
- .nr_irqs = BROWNSTONE_NR_IRQS,
- .init_irq = mmp2_init_irq,
- .init_time = mmp2_timer_init,
- .init_machine = brownstone_init,
- .restart = mmp_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index e94349d4726c..b3c1a248db31 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -58,8 +58,3 @@ void __init mmp2_map_io(void)
mmp_map_io();
iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc));
}
-
-void mmp_restart(enum reboot_mode mode, const char *cmd)
-{
- soft_restart(0);
-}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index ed56b3f15b45..e18f05d5d68d 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/reboot.h>
-#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
extern void mmp_timer_init(int irq, unsigned long rate);
extern void __init mmp_map_io(void);
extern void __init mmp2_map_io(void);
-extern void mmp_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
deleted file mode 100644
index 18bee66a671f..000000000000
--- a/arch/arm/mach-mmp/devices.c
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/devices.c
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/delay.h>
-
-#include <asm/irq.h>
-#include "irqs.h"
-#include "devices.h"
-#include <linux/soc/mmp/cputype.h>
-#include "regs-usb.h"
-
-int __init pxa_register_device(struct pxa_device_desc *desc,
- void *data, size_t size)
-{
- struct platform_device *pdev;
- struct resource res[2 + MAX_RESOURCE_DMA];
- int i, ret = 0, nres = 0;
-
- pdev = platform_device_alloc(desc->drv_name, desc->id);
- if (pdev == NULL)
- return -ENOMEM;
-
- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
- memset(res, 0, sizeof(res));
-
- if (desc->start != -1ul && desc->size > 0) {
- res[nres].start = desc->start;
- res[nres].end = desc->start + desc->size - 1;
- res[nres].flags = IORESOURCE_MEM;
- nres++;
- }
-
- if (desc->irq != NO_IRQ) {
- res[nres].start = desc->irq;
- res[nres].end = desc->irq;
- res[nres].flags = IORESOURCE_IRQ;
- nres++;
- }
-
- for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) {
- if (desc->dma[i] == 0)
- break;
-
- res[nres].start = desc->dma[i];
- res[nres].end = desc->dma[i];
- res[nres].flags = IORESOURCE_DMA;
- }
-
- ret = platform_device_add_resources(pdev, res, nres);
- if (ret) {
- platform_device_put(pdev);
- return ret;
- }
-
- if (data && size) {
- ret = platform_device_add_data(pdev, data, size);
- if (ret) {
- platform_device_put(pdev);
- return ret;
- }
- }
-
- return platform_device_add(pdev);
-}
-
-#if IS_ENABLED(CONFIG_USB) || IS_ENABLED(CONFIG_USB_GADGET)
-#if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV)
-#if IS_ENABLED(CONFIG_CPU_PXA910) || IS_ENABLED(CONFIG_CPU_PXA168)
-
-/*****************************************************************************
- * The registers read/write routines
- *****************************************************************************/
-
-static unsigned int u2o_get(void __iomem *base, unsigned int offset)
-{
- return readl_relaxed(base + offset);
-}
-
-static void u2o_set(void __iomem *base, unsigned int offset,
- unsigned int value)
-{
- u32 reg;
-
- reg = readl_relaxed(base + offset);
- reg |= value;
- writel_relaxed(reg, base + offset);
- readl_relaxed(base + offset);
-}
-
-static void u2o_clear(void __iomem *base, unsigned int offset,
- unsigned int value)
-{
- u32 reg;
-
- reg = readl_relaxed(base + offset);
- reg &= ~value;
- writel_relaxed(reg, base + offset);
- readl_relaxed(base + offset);
-}
-
-static void u2o_write(void __iomem *base, unsigned int offset,
- unsigned int value)
-{
- writel_relaxed(value, base + offset);
- readl_relaxed(base + offset);
-}
-
-
-static DEFINE_MUTEX(phy_lock);
-static int phy_init_cnt;
-
-static int usb_phy_init_internal(void __iomem *base)
-{
- int loops;
-
- pr_info("Init usb phy!!!\n");
-
- /* Initialize the USB PHY power */
- if (cpu_is_pxa910()) {
- u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
- | (1<<UTMI_CTRL_PU_REF_SHIFT));
- }
-
- u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
- u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
-
- /* UTMI_PLL settings */
- u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
- | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
- | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
- | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
-
- u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
- | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
- | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
- | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
-
- /* UTMI_TX */
- u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
- | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
- | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
- | UTMI_TX_AMP_MASK);
- u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
- | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
- | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
-
- /* UTMI_RX */
- u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
- | UTMI_REG_SQ_LENGTH_MASK);
- u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
- | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
-
- /* UTMI_IVREF */
- if (cpu_is_pxa168())
- /* fixing Microsoft Altair board interface with NEC hub issue -
- * Set UTMI_IVREF from 0x4a3 to 0x4bf */
- u2o_write(base, UTMI_IVREF, 0x4bf);
-
- /* toggle VCOCAL_START bit of UTMI_PLL */
- udelay(200);
- u2o_set(base, UTMI_PLL, VCOCAL_START);
- udelay(40);
- u2o_clear(base, UTMI_PLL, VCOCAL_START);
-
- /* toggle REG_RCAL_START bit of UTMI_TX */
- udelay(400);
- u2o_set(base, UTMI_TX, REG_RCAL_START);
- udelay(40);
- u2o_clear(base, UTMI_TX, REG_RCAL_START);
- udelay(400);
-
- /* Make sure PHY PLL is ready */
- loops = 0;
- while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
- mdelay(1);
- loops++;
- if (loops > 100) {
- printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n",
- u2o_get(base, UTMI_PLL));
- break;
- }
- }
-
- if (cpu_is_pxa168()) {
- u2o_set(base, UTMI_RESERVE, 1 << 5);
- /* Turn on UTMI PHY OTG extension */
- u2o_write(base, UTMI_OTG_ADDON, 1);
- }
-
- return 0;
-}
-
-static int usb_phy_deinit_internal(void __iomem *base)
-{
- pr_info("Deinit usb phy!!!\n");
-
- if (cpu_is_pxa168())
- u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
-
- u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
- u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
- u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
- u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
- u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
-
- return 0;
-}
-
-int pxa_usb_phy_init(void __iomem *phy_reg)
-{
- mutex_lock(&phy_lock);
- if (phy_init_cnt++ == 0)
- usb_phy_init_internal(phy_reg);
- mutex_unlock(&phy_lock);
- return 0;
-}
-
-void pxa_usb_phy_deinit(void __iomem *phy_reg)
-{
- WARN_ON(phy_init_cnt == 0);
-
- mutex_lock(&phy_lock);
- if (--phy_init_cnt == 0)
- usb_phy_deinit_internal(phy_reg);
- mutex_unlock(&phy_lock);
-}
-#endif
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SUPPORT)
-static u64 __maybe_unused usb_dma_mask = ~(u32)0;
-
-#if IS_ENABLED(CONFIG_PHY_PXA_USB)
-struct resource pxa168_usb_phy_resources[] = {
- [0] = {
- .start = PXA168_U2O_PHYBASE,
- .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device pxa168_device_usb_phy = {
- .name = "pxa-usb-phy",
- .id = -1,
- .resource = pxa168_usb_phy_resources,
- .num_resources = ARRAY_SIZE(pxa168_usb_phy_resources),
- .dev = {
- .dma_mask = &usb_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- }
-};
-#endif /* CONFIG_PHY_PXA_USB */
-
-#if IS_ENABLED(CONFIG_USB_MV_UDC)
-struct resource pxa168_u2o_resources[] = {
- /* regbase */
- [0] = {
- .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
- .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
- .flags = IORESOURCE_MEM,
- .name = "capregs",
- },
- /* phybase */
- [1] = {
- .start = PXA168_U2O_PHYBASE,
- .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
- .flags = IORESOURCE_MEM,
- .name = "phyregs",
- },
- [2] = {
- .start = IRQ_PXA168_USB1,
- .end = IRQ_PXA168_USB1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa168_device_u2o = {
- .name = "mv-udc",
- .id = -1,
- .resource = pxa168_u2o_resources,
- .num_resources = ARRAY_SIZE(pxa168_u2o_resources),
- .dev = {
- .dma_mask = &usb_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- }
-};
-#endif /* CONFIG_USB_MV_UDC */
-
-#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
-struct resource pxa168_u2oehci_resources[] = {
- [0] = {
- .start = PXA168_U2O_REGBASE,
- .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PXA168_USB1,
- .end = IRQ_PXA168_USB1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa168_device_u2oehci = {
- .name = "pxa-u2oehci",
- .id = -1,
- .dev = {
- .dma_mask = &usb_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
-
- .num_resources = ARRAY_SIZE(pxa168_u2oehci_resources),
- .resource = pxa168_u2oehci_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MV_OTG)
-struct resource pxa168_u2ootg_resources[] = {
- /* regbase */
- [0] = {
- .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
- .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
- .flags = IORESOURCE_MEM,
- .name = "capregs",
- },
- /* phybase */
- [1] = {
- .start = PXA168_U2O_PHYBASE,
- .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
- .flags = IORESOURCE_MEM,
- .name = "phyregs",
- },
- [2] = {
- .start = IRQ_PXA168_USB1,
- .end = IRQ_PXA168_USB1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa168_device_u2ootg = {
- .name = "mv-otg",
- .id = -1,
- .dev = {
- .dma_mask = &usb_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
-
- .num_resources = ARRAY_SIZE(pxa168_u2ootg_resources),
- .resource = pxa168_u2ootg_resources,
-};
-#endif /* CONFIG_USB_MV_OTG */
-
-#endif
diff --git a/arch/arm/mach-mmp/devices.h b/arch/arm/mach-mmp/devices.h
deleted file mode 100644
index 4df596c5c201..000000000000
--- a/arch/arm/mach-mmp/devices.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_DEVICE_H
-#define __MACH_DEVICE_H
-
-#include <linux/types.h>
-
-#define MAX_RESOURCE_DMA 2
-
-/* structure for describing the on-chip devices */
-struct pxa_device_desc {
- const char *dev_name;
- const char *drv_name;
- int id;
- int irq;
- unsigned long start;
- unsigned long size;
- int dma[MAX_RESOURCE_DMA];
-};
-
-#define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
-struct pxa_device_desc pxa168_device_##_name __initdata = { \
- .dev_name = "pxa168-" #_name, \
- .drv_name = _drv, \
- .id = _id, \
- .irq = IRQ_PXA168_##_irq, \
- .start = _start, \
- .size = _size, \
- .dma = { _dma }, \
-};
-
-#define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
-struct pxa_device_desc pxa910_device_##_name __initdata = { \
- .dev_name = "pxa910-" #_name, \
- .drv_name = _drv, \
- .id = _id, \
- .irq = IRQ_PXA910_##_irq, \
- .start = _start, \
- .size = _size, \
- .dma = { _dma }, \
-};
-
-#define MMP2_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \
-struct pxa_device_desc mmp2_device_##_name __initdata = { \
- .dev_name = "mmp2-" #_name, \
- .drv_name = _drv, \
- .id = _id, \
- .irq = IRQ_MMP2_##_irq, \
- .start = _start, \
- .size = _size, \
- .dma = { _dma }, \
-}
-
-extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
-extern int pxa_usb_phy_init(void __iomem *phy_reg);
-extern void pxa_usb_phy_deinit(void __iomem *phy_reg);
-
-#endif /* __MACH_DEVICE_H */
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
deleted file mode 100644
index 9a7054368e55..000000000000
--- a/arch/arm/mach-mmp/flint.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/flint.c
- *
- * Support for the Marvell Flint Development Platform.
- *
- * Copyright (C) 2009 Marvell International Ltd.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/smc91x.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "addr-map.h"
-#include "mfp-mmp2.h"
-#include "mmp2.h"
-#include "irqs.h"
-
-#include "common.h"
-
-#define FLINT_NR_IRQS (MMP_NR_IRQS + 48)
-
-static unsigned long flint_pin_config[] __initdata = {
- /* UART1 */
- GPIO45_UART1_RXD,
- GPIO46_UART1_TXD,
-
- /* UART2 */
- GPIO47_UART2_RXD,
- GPIO48_UART2_TXD,
-
- /* SMC */
- GPIO151_SMC_SCLK,
- GPIO145_SMC_nCS0,
- GPIO146_SMC_nCS1,
- GPIO152_SMC_BE0,
- GPIO153_SMC_BE1,
- GPIO154_SMC_IRQ,
- GPIO113_SMC_RDY,
-
- /*Ethernet*/
- GPIO155_GPIO,
-
- /* DFI */
- GPIO168_DFI_D0,
- GPIO167_DFI_D1,
- GPIO166_DFI_D2,
- GPIO165_DFI_D3,
- GPIO107_DFI_D4,
- GPIO106_DFI_D5,
- GPIO105_DFI_D6,
- GPIO104_DFI_D7,
- GPIO111_DFI_D8,
- GPIO164_DFI_D9,
- GPIO163_DFI_D10,
- GPIO162_DFI_D11,
- GPIO161_DFI_D12,
- GPIO110_DFI_D13,
- GPIO109_DFI_D14,
- GPIO108_DFI_D15,
- GPIO143_ND_nCS0,
- GPIO144_ND_nCS1,
- GPIO147_ND_nWE,
- GPIO148_ND_nRE,
- GPIO150_ND_ALE,
- GPIO149_ND_CLE,
- GPIO112_ND_RDY0,
- GPIO160_ND_RDY1,
-};
-
-static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static struct smc91x_platdata flint_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = SMC_CS1_PHYS_BASE + 0x300,
- .end = SMC_CS1_PHYS_BASE + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = MMP_GPIO_TO_IRQ(155),
- .end = MMP_GPIO_TO_IRQ(155),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &flint_smc91x_info,
- },
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static void __init flint_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(flint_pin_config));
-
- /* on-chip devices */
- mmp2_add_uart(1);
- mmp2_add_uart(2);
- platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&mmp2_device_gpio);
-
- /* off-chip devices */
- platform_device_register(&smc91x_device);
-}
-
-MACHINE_START(FLINT, "Flint Development Platform")
- .map_io = mmp_map_io,
- .nr_irqs = FLINT_NR_IRQS,
- .init_irq = mmp2_init_irq,
- .init_time = mmp2_timer_init,
- .init_machine = flint_init,
- .restart = mmp_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
deleted file mode 100644
index 5888b71944b8..000000000000
--- a/arch/arm/mach-mmp/gplugd.c
+++ /dev/null
@@ -1,206 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/gplugd.c
- *
- * Support for the Marvell PXA168-based GuruPlug Display (gplugD) Platform.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include "irqs.h"
-#include "pxa168.h"
-#include "mfp-pxa168.h"
-
-#include "common.h"
-
-static unsigned long gplugd_pin_config[] __initdata = {
- /* UART3 */
- GPIO8_UART3_TXD,
- GPIO9_UART3_RXD,
- GPIO1O_UART3_CTS,
- GPIO11_UART3_RTS,
-
- /* USB OTG PEN */
- GPIO18_GPIO,
-
- /* MMC2 */
- GPIO28_MMC2_CMD,
- GPIO29_MMC2_CLK,
- GPIO30_MMC2_DAT0,
- GPIO31_MMC2_DAT1,
- GPIO32_MMC2_DAT2,
- GPIO33_MMC2_DAT3,
-
- /* LCD & HDMI clock selection GPIO: 0: 74.176MHz, 1: 74.25 MHz */
- GPIO35_GPIO,
- GPIO36_GPIO, /* CEC Interrupt */
-
- /* MMC1 */
- GPIO43_MMC1_CLK,
- GPIO49_MMC1_CMD,
- GPIO41_MMC1_DAT0,
- GPIO40_MMC1_DAT1,
- GPIO52_MMC1_DAT2,
- GPIO51_MMC1_DAT3,
- GPIO53_MMC1_CD,
-
- /* LCD */
- GPIO56_LCD_FCLK_RD,
- GPIO57_LCD_LCLK_A0,
- GPIO58_LCD_PCLK_WR,
- GPIO59_LCD_DENA_BIAS,
- GPIO60_LCD_DD0,
- GPIO61_LCD_DD1,
- GPIO62_LCD_DD2,
- GPIO63_LCD_DD3,
- GPIO64_LCD_DD4,
- GPIO65_LCD_DD5,
- GPIO66_LCD_DD6,
- GPIO67_LCD_DD7,
- GPIO68_LCD_DD8,
- GPIO69_LCD_DD9,
- GPIO70_LCD_DD10,
- GPIO71_LCD_DD11,
- GPIO72_LCD_DD12,
- GPIO73_LCD_DD13,
- GPIO74_LCD_DD14,
- GPIO75_LCD_DD15,
- GPIO76_LCD_DD16,
- GPIO77_LCD_DD17,
- GPIO78_LCD_DD18,
- GPIO79_LCD_DD19,
- GPIO80_LCD_DD20,
- GPIO81_LCD_DD21,
- GPIO82_LCD_DD22,
- GPIO83_LCD_DD23,
-
- /* GPIO */
- GPIO84_GPIO,
- GPIO85_GPIO,
-
- /* Fast-Ethernet*/
- GPIO86_TX_CLK,
- GPIO87_TX_EN,
- GPIO88_TX_DQ3,
- GPIO89_TX_DQ2,
- GPIO90_TX_DQ1,
- GPIO91_TX_DQ0,
- GPIO92_MII_CRS,
- GPIO93_MII_COL,
- GPIO94_RX_CLK,
- GPIO95_RX_ER,
- GPIO96_RX_DQ3,
- GPIO97_RX_DQ2,
- GPIO98_RX_DQ1,
- GPIO99_RX_DQ0,
- GPIO100_MII_MDC,
- GPIO101_MII_MDIO,
- GPIO103_RX_DV,
- GPIO104_GPIO, /* Reset PHY */
-
- /* RTC interrupt */
- GPIO102_GPIO,
-
- /* I2C */
- GPIO105_CI2C_SDA,
- GPIO106_CI2C_SCL,
-
- /* SPI NOR Flash on SSP2 */
- GPIO107_SSP2_RXD,
- GPIO108_SSP2_TXD,
- GPIO110_GPIO, /* SPI_CSn */
- GPIO111_SSP2_CLK,
-
- /* Select JTAG */
- GPIO109_GPIO,
-
- /* I2S */
- GPIO114_I2S_FRM,
- GPIO115_I2S_BCLK,
- GPIO116_I2S_TXD
-};
-
-static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static struct i2c_board_info gplugd_i2c_board_info[] = {
- {
- .type = "isl1208",
- .addr = 0x6F,
- }
-};
-
-/* Bring PHY out of reset by setting GPIO 104 */
-static int gplugd_eth_init(void)
-{
- if (unlikely(gpio_request(104, "ETH_RESET_N"))) {
- printk(KERN_ERR "Can't get hold of GPIO 104 to bring Ethernet "
- "PHY out of reset\n");
- return -EIO;
- }
-
- gpio_direction_output(104, 1);
- gpio_free(104);
- return 0;
-}
-
-struct pxa168_eth_platform_data gplugd_eth_platform_data = {
- .port_number = 0,
- .phy_addr = 0,
- .speed = 0, /* Autonagotiation */
- .intf = PHY_INTERFACE_MODE_RMII,
- .init = gplugd_eth_init,
-};
-
-static void __init select_disp_freq(void)
-{
- /* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
- if (unlikely(gpio_request(35, "DISP_FREQ_SEL"))) {
- printk(KERN_ERR "Can't get hold of GPIO 35 to select display "
- "frequency\n");
- } else {
- gpio_direction_output(35, 1);
- gpio_free(35);
- }
-
- if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) {
- printk(KERN_ERR "Can't get hold of GPIO 85 to select display "
- "frequency\n");
- } else {
- gpio_direction_output(85, 0);
- gpio_free(85);
- }
-}
-
-static void __init gplugd_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(gplugd_pin_config));
-
- select_disp_freq();
-
- /* on-chip devices */
- pxa168_add_uart(3);
- pxa168_add_ssp(1);
- pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
- platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&pxa168_device_gpio);
-
- pxa168_add_eth(&gplugd_eth_platform_data);
-}
-
-MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
- .map_io = mmp_map_io,
- .nr_irqs = MMP_NR_IRQS,
- .init_irq = pxa168_init_irq,
- .init_time = pxa168_timer_init,
- .init_machine = gplugd_init,
- .restart = pxa168_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/irqs.h b/arch/arm/mach-mmp/irqs.h
deleted file mode 100644
index 5acc4d532a43..000000000000
--- a/arch/arm/mach-mmp/irqs.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_IRQS_H
-#define __ASM_MACH_IRQS_H
-
-/*
- * Interrupt numbers for PXA168
- */
-#define IRQ_PXA168_NONE (-1)
-#define IRQ_PXA168_SSP4 0
-#define IRQ_PXA168_SSP3 1
-#define IRQ_PXA168_SSP2 2
-#define IRQ_PXA168_SSP1 3
-#define IRQ_PXA168_PMIC_INT 4
-#define IRQ_PXA168_RTC_INT 5
-#define IRQ_PXA168_RTC_ALARM 6
-#define IRQ_PXA168_TWSI0 7
-#define IRQ_PXA168_GPU 8
-#define IRQ_PXA168_KEYPAD 9
-#define IRQ_PXA168_ONEWIRE 12
-#define IRQ_PXA168_TIMER1 13
-#define IRQ_PXA168_TIMER2 14
-#define IRQ_PXA168_TIMER3 15
-#define IRQ_PXA168_CMU 16
-#define IRQ_PXA168_SSP5 17
-#define IRQ_PXA168_MSP_WAKEUP 19
-#define IRQ_PXA168_CF_WAKEUP 20
-#define IRQ_PXA168_XD_WAKEUP 21
-#define IRQ_PXA168_MFU 22
-#define IRQ_PXA168_MSP 23
-#define IRQ_PXA168_CF 24
-#define IRQ_PXA168_XD 25
-#define IRQ_PXA168_DDR_INT 26
-#define IRQ_PXA168_UART1 27
-#define IRQ_PXA168_UART2 28
-#define IRQ_PXA168_UART3 29
-#define IRQ_PXA168_WDT 35
-#define IRQ_PXA168_MAIN_PMU 36
-#define IRQ_PXA168_FRQ_CHANGE 38
-#define IRQ_PXA168_SDH1 39
-#define IRQ_PXA168_SDH2 40
-#define IRQ_PXA168_LCD 41
-#define IRQ_PXA168_CI 42
-#define IRQ_PXA168_USB1 44
-#define IRQ_PXA168_NAND 45
-#define IRQ_PXA168_HIFI_DMA 46
-#define IRQ_PXA168_DMA_INT0 47
-#define IRQ_PXA168_DMA_INT1 48
-#define IRQ_PXA168_GPIOX 49
-#define IRQ_PXA168_USB2 51
-#define IRQ_PXA168_AC97 57
-#define IRQ_PXA168_TWSI1 58
-#define IRQ_PXA168_AP_PMU 60
-#define IRQ_PXA168_SM_INT 63
-
-/*
- * Interrupt numbers for PXA910
- */
-#define IRQ_PXA910_NONE (-1)
-#define IRQ_PXA910_AIRQ 0
-#define IRQ_PXA910_SSP3 1
-#define IRQ_PXA910_SSP2 2
-#define IRQ_PXA910_SSP1 3
-#define IRQ_PXA910_PMIC_INT 4
-#define IRQ_PXA910_RTC_INT 5
-#define IRQ_PXA910_RTC_ALARM 6
-#define IRQ_PXA910_TWSI0 7
-#define IRQ_PXA910_GPU 8
-#define IRQ_PXA910_KEYPAD 9
-#define IRQ_PXA910_ROTARY 10
-#define IRQ_PXA910_TRACKBALL 11
-#define IRQ_PXA910_ONEWIRE 12
-#define IRQ_PXA910_AP1_TIMER1 13
-#define IRQ_PXA910_AP1_TIMER2 14
-#define IRQ_PXA910_AP1_TIMER3 15
-#define IRQ_PXA910_IPC_AP0 16
-#define IRQ_PXA910_IPC_AP1 17
-#define IRQ_PXA910_IPC_AP2 18
-#define IRQ_PXA910_IPC_AP3 19
-#define IRQ_PXA910_IPC_AP4 20
-#define IRQ_PXA910_IPC_CP0 21
-#define IRQ_PXA910_IPC_CP1 22
-#define IRQ_PXA910_IPC_CP2 23
-#define IRQ_PXA910_IPC_CP3 24
-#define IRQ_PXA910_IPC_CP4 25
-#define IRQ_PXA910_L2_DDR 26
-#define IRQ_PXA910_UART2 27
-#define IRQ_PXA910_UART3 28
-#define IRQ_PXA910_AP2_TIMER1 29
-#define IRQ_PXA910_AP2_TIMER2 30
-#define IRQ_PXA910_CP2_TIMER1 31
-#define IRQ_PXA910_CP2_TIMER2 32
-#define IRQ_PXA910_CP2_TIMER3 33
-#define IRQ_PXA910_GSSP 34
-#define IRQ_PXA910_CP2_WDT 35
-#define IRQ_PXA910_MAIN_PMU 36
-#define IRQ_PXA910_CP_FREQ_CHG 37
-#define IRQ_PXA910_AP_FREQ_CHG 38
-#define IRQ_PXA910_MMC 39
-#define IRQ_PXA910_AEU 40
-#define IRQ_PXA910_LCD 41
-#define IRQ_PXA910_CCIC 42
-#define IRQ_PXA910_IRE 43
-#define IRQ_PXA910_USB1 44
-#define IRQ_PXA910_NAND 45
-#define IRQ_PXA910_HIFI_DMA 46
-#define IRQ_PXA910_DMA_INT0 47
-#define IRQ_PXA910_DMA_INT1 48
-#define IRQ_PXA910_AP_GPIO 49
-#define IRQ_PXA910_AP2_TIMER3 50
-#define IRQ_PXA910_USB2 51
-#define IRQ_PXA910_TWSI1 54
-#define IRQ_PXA910_CP_GPIO 55
-#define IRQ_PXA910_UART1 59 /* Slow UART */
-#define IRQ_PXA910_AP_PMU 60
-#define IRQ_PXA910_SM_INT 63 /* from PinMux */
-
-/*
- * Interrupt numbers for MMP2
- */
-#define IRQ_MMP2_NONE (-1)
-#define IRQ_MMP2_SSP1 0
-#define IRQ_MMP2_SSP2 1
-#define IRQ_MMP2_SSPA1 2
-#define IRQ_MMP2_SSPA2 3
-#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */
-#define IRQ_MMP2_RTC_MUX 5
-#define IRQ_MMP2_TWSI1 7
-#define IRQ_MMP2_GPU 8
-#define IRQ_MMP2_KEYPAD_MUX 9
-#define IRQ_MMP2_ROTARY 10
-#define IRQ_MMP2_TRACKBALL 11
-#define IRQ_MMP2_ONEWIRE 12
-#define IRQ_MMP2_TIMER1 13
-#define IRQ_MMP2_TIMER2 14
-#define IRQ_MMP2_TIMER3 15
-#define IRQ_MMP2_RIPC 16
-#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */
-#define IRQ_MMP2_HDMI 19
-#define IRQ_MMP2_SSP3 20
-#define IRQ_MMP2_SSP4 21
-#define IRQ_MMP2_USB_HS1 22
-#define IRQ_MMP2_USB_HS2 23
-#define IRQ_MMP2_UART3 24
-#define IRQ_MMP2_UART1 27
-#define IRQ_MMP2_UART2 28
-#define IRQ_MMP2_MIPI_DSI 29
-#define IRQ_MMP2_CI2 30
-#define IRQ_MMP2_PMU_TIMER1 31
-#define IRQ_MMP2_PMU_TIMER2 32
-#define IRQ_MMP2_PMU_TIMER3 33
-#define IRQ_MMP2_USB_FS 34
-#define IRQ_MMP2_MISC_MUX 35
-#define IRQ_MMP2_WDT1 36
-#define IRQ_MMP2_NAND_DMA 37
-#define IRQ_MMP2_USIM 38
-#define IRQ_MMP2_MMC 39
-#define IRQ_MMP2_WTM 40
-#define IRQ_MMP2_LCD 41
-#define IRQ_MMP2_CI 42
-#define IRQ_MMP2_IRE 43
-#define IRQ_MMP2_USB_OTG 44
-#define IRQ_MMP2_NAND 45
-#define IRQ_MMP2_UART4 46
-#define IRQ_MMP2_DMA_FIQ 47
-#define IRQ_MMP2_DMA_RIQ 48
-#define IRQ_MMP2_GPIO 49
-#define IRQ_MMP2_MIPI_HSI1_MUX 51
-#define IRQ_MMP2_MMC2 52
-#define IRQ_MMP2_MMC3 53
-#define IRQ_MMP2_MMC4 54
-#define IRQ_MMP2_MIPI_HSI0_MUX 55
-#define IRQ_MMP2_MSP 58
-#define IRQ_MMP2_MIPI_SLIM_DMA 59
-#define IRQ_MMP2_PJ4_FREQ_CHG 60
-#define IRQ_MMP2_MIPI_SLIM 62
-#define IRQ_MMP2_SM 63
-
-#define IRQ_MMP2_MUX_BASE 64
-
-/* secondary interrupt of INT #4 */
-#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE)
-#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0)
-#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1)
-
-/* secondary interrupt of INT #5 */
-#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2)
-#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0)
-#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1)
-
-/* secondary interrupt of INT #9 */
-#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2)
-#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0)
-#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1)
-#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2)
-
-/* secondary interrupt of INT #17 */
-#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3)
-#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0)
-#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1)
-#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2)
-#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3)
-#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4)
-
-/* secondary interrupt of INT #35 */
-#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5)
-#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0)
-#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1)
-#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2)
-#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3)
-#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4)
-#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5)
-#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6)
-#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7)
-#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9)
-#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10)
-#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11)
-#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12)
-#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13)
-#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14)
-
-/* secondary interrupt of INT #51 */
-#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15)
-#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0)
-#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1)
-
-/* secondary interrupt of INT #55 */
-#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2)
-#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0)
-#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1)
-
-#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2)
-
-#define IRQ_GPIO_START 128
-#define MMP_NR_BUILTIN_GPIO 192
-#define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio))
-
-#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
-#define MMP_NR_IRQS IRQ_BOARD_START
-
-#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
deleted file mode 100644
index 2578e176fd48..000000000000
--- a/arch/arm/mach-mmp/jasper.c
+++ /dev/null
@@ -1,185 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/jasper.c
- *
- * Support for the Marvell Jasper Development Platform.
- *
- * Copyright (C) 2009-2010 Marvell International Ltd.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/gpio-pxa.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/max8649.h>
-#include <linux/mfd/max8925.h>
-#include <linux/interrupt.h>
-
-#include "irqs.h"
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "addr-map.h"
-#include "mfp-mmp2.h"
-#include "mmp2.h"
-
-#include "common.h"
-
-#define JASPER_NR_IRQS (MMP_NR_IRQS + 48)
-
-static unsigned long jasper_pin_config[] __initdata = {
- /* UART1 */
- GPIO29_UART1_RXD,
- GPIO30_UART1_TXD,
-
- /* UART3 */
- GPIO51_UART3_RXD,
- GPIO52_UART3_TXD,
-
- /* DFI */
- GPIO168_DFI_D0,
- GPIO167_DFI_D1,
- GPIO166_DFI_D2,
- GPIO165_DFI_D3,
- GPIO107_DFI_D4,
- GPIO106_DFI_D5,
- GPIO105_DFI_D6,
- GPIO104_DFI_D7,
- GPIO111_DFI_D8,
- GPIO164_DFI_D9,
- GPIO163_DFI_D10,
- GPIO162_DFI_D11,
- GPIO161_DFI_D12,
- GPIO110_DFI_D13,
- GPIO109_DFI_D14,
- GPIO108_DFI_D15,
- GPIO143_ND_nCS0,
- GPIO144_ND_nCS1,
- GPIO147_ND_nWE,
- GPIO148_ND_nRE,
- GPIO150_ND_ALE,
- GPIO149_ND_CLE,
- GPIO112_ND_RDY0,
- GPIO160_ND_RDY1,
-
- /* PMIC */
- PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
-
- /* MMC1 */
- GPIO131_MMC1_DAT3,
- GPIO132_MMC1_DAT2,
- GPIO133_MMC1_DAT1,
- GPIO134_MMC1_DAT0,
- GPIO136_MMC1_CMD,
- GPIO139_MMC1_CLK,
- GPIO140_MMC1_CD,
- GPIO141_MMC1_WP,
-
- /* MMC2 */
- GPIO37_MMC2_DAT3,
- GPIO38_MMC2_DAT2,
- GPIO39_MMC2_DAT1,
- GPIO40_MMC2_DAT0,
- GPIO41_MMC2_CMD,
- GPIO42_MMC2_CLK,
-
- /* MMC3 */
- GPIO165_MMC3_DAT7,
- GPIO162_MMC3_DAT6,
- GPIO166_MMC3_DAT5,
- GPIO163_MMC3_DAT4,
- GPIO167_MMC3_DAT3,
- GPIO164_MMC3_DAT2,
- GPIO168_MMC3_DAT1,
- GPIO111_MMC3_DAT0,
- GPIO112_MMC3_CMD,
- GPIO151_MMC3_CLK,
-};
-
-static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static struct regulator_consumer_supply max8649_supply[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data max8649_init_data = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 1150000,
- .max_uV = 1280000,
- .always_on = 1,
- .boot_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &max8649_supply[0],
-};
-
-static struct max8649_platform_data jasper_max8649_info = {
- .mode = 2, /* VID1 = 1, VID0 = 0 */
- .extclk = 0,
- .ramp_timing = MAX8649_RAMP_32MV,
- .regulator = &max8649_init_data,
-};
-
-static struct max8925_backlight_pdata jasper_backlight_data = {
- .dual_string = 0,
-};
-
-static struct max8925_power_pdata jasper_power_data = {
- .batt_detect = 0, /* can't detect battery by ID pin */
- .topoff_threshold = MAX8925_TOPOFF_THR_10PER,
- .fast_charge = MAX8925_FCHG_1000MA,
-};
-
-static struct max8925_platform_data jasper_max8925_info = {
- .backlight = &jasper_backlight_data,
- .power = &jasper_power_data,
- .irq_base = MMP_NR_IRQS,
-};
-
-static struct i2c_board_info jasper_twsi1_info[] = {
- [0] = {
- .type = "max8649",
- .addr = 0x60,
- .platform_data = &jasper_max8649_info,
- },
- [1] = {
- .type = "max8925",
- .addr = 0x3c,
- .irq = IRQ_MMP2_PMIC,
- .platform_data = &jasper_max8925_info,
- },
-};
-
-static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
- .clk_delay_cycles = 0x1f,
-};
-
-static void __init jasper_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
-
- /* on-chip devices */
- mmp2_add_uart(1);
- mmp2_add_uart(3);
- mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
- platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&mmp2_device_gpio);
- mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
-
- regulator_has_full_constraints();
-}
-
-MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
- .map_io = mmp_map_io,
- .nr_irqs = JASPER_NR_IRQS,
- .init_irq = mmp2_init_irq,
- .init_time = mmp2_timer_init,
- .init_machine = jasper_init,
- .restart = mmp_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/mfp-mmp2.h b/arch/arm/mach-mmp/mfp-mmp2.h
deleted file mode 100644
index 1620222981e3..000000000000
--- a/arch/arm/mach-mmp/mfp-mmp2.h
+++ /dev/null
@@ -1,396 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_MFP_MMP2_H
-#define __ASM_MACH_MFP_MMP2_H
-
-#include "mfp.h"
-
-#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
-#define MFP_DRIVE_SLOW (0x2 << 13)
-#define MFP_DRIVE_MEDIUM (0x4 << 13)
-#define MFP_DRIVE_FAST (0x6 << 13)
-
-/* GPIO */
-#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
-#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
-#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
-#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
-#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
-#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
-#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
-#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
-#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
-#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
-#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
-#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
-#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
-#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
-#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
-#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
-#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
-#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
-#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
-#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
-#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
-#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
-#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
-#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
-#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
-#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
-#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
-#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
-#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
-#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
-#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
-#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
-#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
-#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
-#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
-#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
-#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
-#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
-#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
-#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
-#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
-#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
-#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
-#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
-#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
-#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
-#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
-#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
-#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
-#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
-#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
-#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
-#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
-#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
-#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
-#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
-#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
-#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
-#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
-#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
-#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
-#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
-#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
-#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
-#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
-#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
-#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
-#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
-#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
-#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
-#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
-#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
-#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
-#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
-#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
-#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
-#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
-#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
-#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
-#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
-#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
-#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
-#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
-#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
-#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
-#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
-#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
-#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
-#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
-#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
-#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
-#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
-#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
-#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
-#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
-#define GPIO102_GPIO MFP_CFG(GPIO102, AF1)
-#define GPIO103_GPIO MFP_CFG(GPIO103, AF1)
-#define GPIO104_GPIO MFP_CFG(GPIO104, AF1)
-#define GPIO105_GPIO MFP_CFG(GPIO105, AF1)
-#define GPIO106_GPIO MFP_CFG(GPIO106, AF1)
-#define GPIO107_GPIO MFP_CFG(GPIO107, AF1)
-#define GPIO108_GPIO MFP_CFG(GPIO108, AF1)
-#define GPIO109_GPIO MFP_CFG(GPIO109, AF1)
-#define GPIO110_GPIO MFP_CFG(GPIO110, AF1)
-#define GPIO111_GPIO MFP_CFG(GPIO111, AF1)
-#define GPIO112_GPIO MFP_CFG(GPIO112, AF1)
-#define GPIO113_GPIO MFP_CFG(GPIO113, AF1)
-#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
-#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
-#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
-#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
-#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
-#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
-#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
-#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
-#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
-#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
-#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
-#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
-#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
-#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
-#define GPIO128_GPIO MFP_CFG(GPIO128, AF0)
-#define GPIO129_GPIO MFP_CFG(GPIO129, AF0)
-#define GPIO130_GPIO MFP_CFG(GPIO130, AF0)
-#define GPIO131_GPIO MFP_CFG(GPIO131, AF0)
-#define GPIO132_GPIO MFP_CFG(GPIO132, AF0)
-#define GPIO133_GPIO MFP_CFG(GPIO133, AF0)
-#define GPIO134_GPIO MFP_CFG(GPIO134, AF0)
-#define GPIO135_GPIO MFP_CFG(GPIO135, AF0)
-#define GPIO136_GPIO MFP_CFG(GPIO136, AF0)
-#define GPIO137_GPIO MFP_CFG(GPIO137, AF0)
-#define GPIO138_GPIO MFP_CFG(GPIO138, AF0)
-#define GPIO139_GPIO MFP_CFG(GPIO139, AF0)
-#define GPIO140_GPIO MFP_CFG(GPIO140, AF0)
-#define GPIO141_GPIO MFP_CFG(GPIO141, AF0)
-#define GPIO142_GPIO MFP_CFG(GPIO142, AF1)
-#define GPIO143_GPIO MFP_CFG(GPIO143, AF1)
-#define GPIO144_GPIO MFP_CFG(GPIO144, AF1)
-#define GPIO145_GPIO MFP_CFG(GPIO145, AF1)
-#define GPIO146_GPIO MFP_CFG(GPIO146, AF1)
-#define GPIO147_GPIO MFP_CFG(GPIO147, AF1)
-#define GPIO148_GPIO MFP_CFG(GPIO148, AF1)
-#define GPIO149_GPIO MFP_CFG(GPIO149, AF1)
-#define GPIO150_GPIO MFP_CFG(GPIO150, AF1)
-#define GPIO151_GPIO MFP_CFG(GPIO151, AF1)
-#define GPIO152_GPIO MFP_CFG(GPIO152, AF1)
-#define GPIO153_GPIO MFP_CFG(GPIO153, AF1)
-#define GPIO154_GPIO MFP_CFG(GPIO154, AF1)
-#define GPIO155_GPIO MFP_CFG(GPIO155, AF1)
-#define GPIO156_GPIO MFP_CFG(GPIO156, AF1)
-#define GPIO157_GPIO MFP_CFG(GPIO157, AF1)
-#define GPIO158_GPIO MFP_CFG(GPIO158, AF1)
-#define GPIO159_GPIO MFP_CFG(GPIO159, AF1)
-#define GPIO160_GPIO MFP_CFG(GPIO160, AF1)
-#define GPIO161_GPIO MFP_CFG(GPIO161, AF1)
-#define GPIO162_GPIO MFP_CFG(GPIO162, AF1)
-#define GPIO163_GPIO MFP_CFG(GPIO163, AF1)
-#define GPIO164_GPIO MFP_CFG(GPIO164, AF1)
-#define GPIO165_GPIO MFP_CFG(GPIO165, AF1)
-#define GPIO166_GPIO MFP_CFG(GPIO166, AF1)
-#define GPIO167_GPIO MFP_CFG(GPIO167, AF1)
-#define GPIO168_GPIO MFP_CFG(GPIO168, AF1)
-
-/* DFI */
-#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)
-#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0)
-#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0)
-#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0)
-#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0)
-#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0)
-#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0)
-#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0)
-#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0)
-#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0)
-#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0)
-#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0)
-#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0)
-#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0)
-#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0)
-#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0)
-#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0)
-#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0)
-#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0)
-#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0)
-#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0)
-#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0)
-#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0)
-#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0)
-
-/* Static Memory Controller */
-#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0)
-#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0)
-#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0)
-#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0)
-#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0)
-#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0)
-#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0)
-
-/* Ethernet */
-#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2)
-
-/* UART1 */
-#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1)
-#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1)
-#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1)
-#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1)
-#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1)
-#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1)
-
-/* UART2 */
-#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1)
-#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1)
-#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1)
-#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1)
-
-/* UART3 */
-#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1)
-#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1)
-#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1)
-#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1)
-
-/* MMC1 */
-#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST)
-#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST)
-#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST)
-#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST)
-#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST)
-#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST)
-#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST)
-#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST)
-#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST)
-#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST)
-#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST)
-#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST)
-
-/*MMC2*/
-#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST)
-#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST)
-#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST)
-#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST)
-#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST)
-#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST)
-
-/*MMC3*/
-#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST)
-#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST)
-#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST)
-#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST)
-#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST)
-#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST)
-#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST)
-#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST)
-#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST)
-#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST)
-
-/* LCD */
-#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST)
-#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST)
-#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST)
-#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST)
-#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST)
-#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST)
-#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST)
-#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST)
-#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST)
-#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST)
-#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST)
-#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST)
-#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST)
-#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST)
-#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST)
-#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST)
-#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST)
-#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST)
-#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST)
-#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST)
-#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST)
-#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST)
-#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST)
-#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST)
-#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST)
-#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST)
-#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST)
-#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST)
-#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST)
-#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST)
-#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST)
-#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST)
-#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST)
-
-#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST)
-
-/*LCD TV path*/
-#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST)
-#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST)
-#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST)
-#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST)
-#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST)
-#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST)
-#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST)
-#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST)
-#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST)
-#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST)
-#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST)
-#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST)
-
-/* I2C */
-#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW)
-#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW)
-#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW)
-#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW)
-#define TWSI4_SCL MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW)
-#define TWSI4_SDA MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW)
-#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW)
-#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW)
-#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW)
-#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW)
-
-/* SSPA1 */
-#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1)
-#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1)
-#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1)
-#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1)
-#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1)
-#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1)
-
-/* SSPA2 */
-#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1)
-#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1)
-#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1)
-#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1)
-
-/* Keypad */
-#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
-#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
-#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
-#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
-#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
-#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
-#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
-#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
-#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
-#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
-#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
-#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
-#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
-#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
-#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
-#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
-#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
-#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
-#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
-#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
-#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1)
-#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1)
-#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1)
-#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1)
-
-/* CAMERA */
-#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST)
-#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST)
-#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST)
-#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST)
-#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST)
-#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST)
-#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST)
-#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST)
-#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST)
-#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST)
-#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST)
-#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST)
-
-/* PMIC */
-#define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0)
-
-#endif /* __ASM_MACH_MFP_MMP2_H */
-
diff --git a/arch/arm/mach-mmp/mfp-pxa168.h b/arch/arm/mach-mmp/mfp-pxa168.h
deleted file mode 100644
index 90d16d3419a4..000000000000
--- a/arch/arm/mach-mmp/mfp-pxa168.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_MFP_PXA168_H
-#define __ASM_MACH_MFP_PXA168_H
-
-#include "mfp.h"
-
-#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
-#define MFP_DRIVE_SLOW (0x1 << 13)
-#define MFP_DRIVE_MEDIUM (0x2 << 13)
-#define MFP_DRIVE_FAST (0x3 << 13)
-
-#undef MFP_CFG
-#undef MFP_CFG_DRV
-
-#define MFP_CFG(pin, af) \
- (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
-
-#define MFP_CFG_DRV(pin, af, drv) \
- (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
-
-/* GPIO */
-#define GPIO0_GPIO MFP_CFG(GPIO0, AF5)
-#define GPIO1_GPIO MFP_CFG(GPIO1, AF5)
-#define GPIO2_GPIO MFP_CFG(GPIO2, AF5)
-#define GPIO3_GPIO MFP_CFG(GPIO3, AF5)
-#define GPIO4_GPIO MFP_CFG(GPIO4, AF5)
-#define GPIO5_GPIO MFP_CFG(GPIO5, AF5)
-#define GPIO6_GPIO MFP_CFG(GPIO6, AF5)
-#define GPIO7_GPIO MFP_CFG(GPIO7, AF5)
-#define GPIO8_GPIO MFP_CFG(GPIO8, AF5)
-#define GPIO9_GPIO MFP_CFG(GPIO9, AF5)
-#define GPIO10_GPIO MFP_CFG(GPIO10, AF5)
-#define GPIO11_GPIO MFP_CFG(GPIO11, AF5)
-#define GPIO12_GPIO MFP_CFG(GPIO12, AF5)
-#define GPIO13_GPIO MFP_CFG(GPIO13, AF5)
-#define GPIO14_GPIO MFP_CFG(GPIO14, AF5)
-#define GPIO15_GPIO MFP_CFG(GPIO15, AF5)
-#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
-#define GPIO17_GPIO MFP_CFG(GPIO17, AF5)
-#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
-#define GPIO19_GPIO MFP_CFG(GPIO19, AF5)
-#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
-#define GPIO21_GPIO MFP_CFG(GPIO21, AF5)
-#define GPIO22_GPIO MFP_CFG(GPIO22, AF5)
-#define GPIO23_GPIO MFP_CFG(GPIO23, AF5)
-#define GPIO24_GPIO MFP_CFG(GPIO24, AF5)
-#define GPIO25_GPIO MFP_CFG(GPIO25, AF5)
-#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
-#define GPIO27_GPIO MFP_CFG(GPIO27, AF5)
-#define GPIO28_GPIO MFP_CFG(GPIO28, AF5)
-#define GPIO29_GPIO MFP_CFG(GPIO29, AF5)
-#define GPIO30_GPIO MFP_CFG(GPIO30, AF5)
-#define GPIO31_GPIO MFP_CFG(GPIO31, AF5)
-#define GPIO32_GPIO MFP_CFG(GPIO32, AF5)
-#define GPIO33_GPIO MFP_CFG(GPIO33, AF5)
-#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
-#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
-#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
-#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
-#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
-#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
-#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
-#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
-#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
-#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
-#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
-#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
-#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
-#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
-#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
-#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
-#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
-#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
-#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
-#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
-#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
-#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
-#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
-#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
-#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
-#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
-#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
-#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
-#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
-#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
-#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
-#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
-#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
-#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
-#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
-#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
-#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
-#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
-#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
-#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
-#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
-#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
-#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
-#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
-#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
-#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
-#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
-#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
-#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
-#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
-#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
-#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
-#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
-#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
-#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
-#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
-#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
-#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
-#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
-#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
-#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
-#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
-#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
-#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
-#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
-#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
-#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
-#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
-#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
-#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
-#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
-#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
-#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
-#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
-#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
-#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
-#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
-#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
-#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
-#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
-#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
-#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
-
-/* DFI */
-#define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0)
-#define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0)
-#define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0)
-#define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0)
-#define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0)
-#define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0)
-#define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0)
-#define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0)
-#define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0)
-#define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0)
-#define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0)
-#define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0)
-#define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0)
-#define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0)
-#define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0)
-#define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0)
-
-#define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0)
-#define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0)
-#define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0)
-#define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0)
-
-/* NAND */
-#define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1)
-#define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0)
-#define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0)
-#define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0)
-#define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0)
-#define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1)
-#define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1)
-
-/* Static Memory Controller */
-#define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3)
-#define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2)
-#define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2)
-#define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3)
-#define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0)
-#define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2)
-#define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0)
-#define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0)
-#define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0)
-#define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0)
-#define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0)
-#define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2)
-#define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2)
-#define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2)
-
-/* Compact Flash */
-#define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3)
-#define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3)
-#define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3)
-#define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3)
-#define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3)
-#define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3)
-#define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3)
-#define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3)
-#define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3)
-#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3)
-
-/* UART */
-#define GPIO8_UART3_TXD MFP_CFG(GPIO8, AF2)
-#define GPIO9_UART3_RXD MFP_CFG(GPIO9, AF2)
-#define GPIO1O_UART3_CTS MFP_CFG(GPIO10, AF2)
-#define GPIO11_UART3_RTS MFP_CFG(GPIO11, AF2)
-#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2)
-#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2)
-#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST)
-#define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST)
-#define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST)
-#define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST)
-#define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1)
-#define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2)
-#define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1)
-#define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2)
-#define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1)
-#define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2)
-#define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1)
-#define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2)
-
-/* MMC1 */
-#define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1)
-#define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1)
-#define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1)
-#define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1)
-#define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1)
-#define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1)
-#define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1)
-#define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1)
-#define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1)
-#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1)
-#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1)
-#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1)
-
-/* MMC2 */
-#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
-#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
-#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
-#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
-#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
-#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
-
-/* MMC4 */
-#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
-#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
-#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
-#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
-#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
-#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
-
-/* LCD */
-#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1)
-#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1)
-#define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1)
-#define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1)
-#define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1)
-#define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1)
-#define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1)
-#define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1)
-#define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1)
-#define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1)
-#define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1)
-#define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1)
-#define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1)
-#define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1)
-#define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1)
-#define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1)
-#define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1)
-#define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1)
-#define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1)
-#define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1)
-#define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1)
-#define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1)
-#define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1)
-#define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1)
-#define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1)
-#define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1)
-#define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1)
-#define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1)
-#define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1)
-#define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1)
-
-/* I2C */
-#define GPIO105_CI2C_SDA MFP_CFG(GPIO105, AF1)
-#define GPIO106_CI2C_SCL MFP_CFG(GPIO106, AF1)
-
-/* I2S */
-#define GPIO113_I2S_MCLK MFP_CFG(GPIO113, AF6)
-#define GPIO114_I2S_FRM MFP_CFG(GPIO114, AF1)
-#define GPIO115_I2S_BCLK MFP_CFG(GPIO115, AF1)
-#define GPIO116_I2S_RXD MFP_CFG(GPIO116, AF2)
-#define GPIO116_I2S_TXD MFP_CFG(GPIO116, AF1)
-#define GPIO117_I2S_TXD MFP_CFG(GPIO117, AF2)
-
-/* PWM */
-#define GPIO96_PWM3_OUT MFP_CFG(GPIO96, AF1)
-#define GPIO97_PWM2_OUT MFP_CFG(GPIO97, AF1)
-#define GPIO98_PWM1_OUT MFP_CFG(GPIO98, AF1)
-#define GPIO104_PWM4_OUT MFP_CFG(GPIO104, AF1)
-#define GPIO106_PWM2_OUT MFP_CFG(GPIO106, AF2)
-#define GPIO74_PWM4_OUT MFP_CFG(GPIO74, AF2)
-#define GPIO75_PWM3_OUT MFP_CFG(GPIO75, AF2)
-#define GPIO76_PWM2_OUT MFP_CFG(GPIO76, AF2)
-#define GPIO77_PWM1_OUT MFP_CFG(GPIO77, AF2)
-#define GPIO82_PWM4_OUT MFP_CFG(GPIO82, AF2)
-#define GPIO83_PWM3_OUT MFP_CFG(GPIO83, AF2)
-#define GPIO84_PWM2_OUT MFP_CFG(GPIO84, AF2)
-#define GPIO85_PWM1_OUT MFP_CFG(GPIO85, AF2)
-#define GPIO84_PWM1_OUT MFP_CFG(GPIO84, AF4)
-#define GPIO122_PWM3_OUT MFP_CFG(GPIO122, AF3)
-#define GPIO123_PWM1_OUT MFP_CFG(GPIO123, AF1)
-#define GPIO124_PWM2_OUT MFP_CFG(GPIO124, AF1)
-#define GPIO125_PWM3_OUT MFP_CFG(GPIO125, AF1)
-#define GPIO126_PWM4_OUT MFP_CFG(GPIO126, AF1)
-#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2)
-#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3)
-
-/* Keypad */
-#define GPIO109_KP_MKIN1 MFP_CFG(GPIO109, AF7)
-#define GPIO110_KP_MKIN0 MFP_CFG(GPIO110, AF7)
-#define GPIO111_KP_MKOUT7 MFP_CFG(GPIO111, AF7)
-#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
-#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
-
-/* Fast Ethernet */
-#define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5)
-#define GPIO87_TX_EN MFP_CFG(GPIO87, AF5)
-#define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5)
-#define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5)
-#define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5)
-#define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5)
-#define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5)
-#define GPIO93_MII_COL MFP_CFG(GPIO93, AF5)
-#define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5)
-#define GPIO95_RX_ER MFP_CFG(GPIO95, AF5)
-#define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5)
-#define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5)
-#define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5)
-#define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5)
-#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5)
-#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
-#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
-
-/* SSP2 */
-#define GPIO107_SSP2_RXD MFP_CFG(GPIO107, AF4)
-#define GPIO108_SSP2_TXD MFP_CFG(GPIO108, AF4)
-#define GPIO111_SSP2_CLK MFP_CFG(GPIO111, AF4)
-#define GPIO112_SSP2_FRM MFP_CFG(GPIO112, AF4)
-
-#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/mfp-pxa910.h b/arch/arm/mach-mmp/mfp-pxa910.h
deleted file mode 100644
index 6f900cade631..000000000000
--- a/arch/arm/mach-mmp/mfp-pxa910.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_MFP_PXA910_H
-#define __ASM_MACH_MFP_PXA910_H
-
-#include "mfp.h"
-
-#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
-#define MFP_DRIVE_SLOW (0x2 << 13)
-#define MFP_DRIVE_MEDIUM (0x4 << 13)
-#define MFP_DRIVE_FAST (0x6 << 13)
-
-/* UART2 */
-#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)
-#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6)
-
-/* UART3 */
-#define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4)
-#define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4)
-
-/*IRDA*/
-#define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0)
-
-/* SMC */
-#define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0)
-#define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0)
-#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
-#define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1)
-#define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1)
-
-/* I2C */
-#define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2)
-#define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2)
-
-/* SSP1 (I2S) */
-#define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM)
-#define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM)
-#define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM)
-#define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM)
-#define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM)
-#define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM)
-#define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM)
-
-/* DFI */
-#define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0)
-#define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0)
-#define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0)
-#define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0)
-#define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0)
-#define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0)
-#define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0)
-#define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0)
-#define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0)
-#define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0)
-#define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0)
-#define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0)
-#define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0)
-#define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0)
-#define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0)
-#define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0)
-#define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0)
-#define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1)
-#define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0)
-#define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1)
-#define DF_REn_DF_REn MFP_CFG(DF_REn, AF1)
-#define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0)
-
-/*keypad*/
-#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
-#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
-#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
-#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
-#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
-#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
-#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
-#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
-#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
-#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
-#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
-#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
-#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
-#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
-#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
-#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
-#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
-#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
-#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
-#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
-
-/* LCD */
-#define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1)
-#define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1)
-#define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1)
-#define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1)
-#define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1)
-#define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1)
-#define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1)
-#define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1)
-#define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1)
-#define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1)
-#define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1)
-#define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1)
-#define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1)
-#define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1)
-#define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1)
-#define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1)
-#define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1)
-#define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1)
-#define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1)
-#define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1)
-#define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1)
-#define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1)
-#define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1)
-#define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1)
-#define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1)
-#define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1)
-#define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1)
-#define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1)
-
-#define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3)
-#define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3)
-#define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3)
-#define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3)
-
-#define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0)
-
-/*smart panel*/
-#define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0)
-#define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0)
-#define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0)
-
-/*1wire*/
-#define GPIO106_1WIRE MFP_CFG(GPIO106, AF3)
-
-/*CCIC*/
-#define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM)
-#define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM)
-#define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM)
-#define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM)
-#define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM)
-#define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM)
-#define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM)
-#define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM)
-#define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM)
-#define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM)
-#define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM)
-#define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM)
-
-/* MMC1 */
-#define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM)
-#define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM)
-#define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM)
-#define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM)
-#define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM)
-#define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM)
-#define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM)
-#define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM)
-#define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM)
-#define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM)
-#define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM)
-#define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM)
-
-/* PWM */
-#define GPIO27_PWM3_AF2 MFP_CFG(GPIO27, AF2)
-#define GPIO51_PWM2_OUT MFP_CFG(GPIO51, AF2)
-#define GPIO117_PWM1_OUT MFP_CFG(GPIO117, AF2)
-#define GPIO118_PWM2_OUT MFP_CFG(GPIO118, AF2)
-#define GPIO119_PWM3_OUT MFP_CFG(GPIO119, AF2)
-#define GPIO120_PWM4_OUT MFP_CFG(GPIO120, AF2)
-
-#endif /* __ASM_MACH MFP_PXA910_H */
diff --git a/arch/arm/mach-mmp/mfp.h b/arch/arm/mach-mmp/mfp.h
deleted file mode 100644
index 75a4acb33b1b..000000000000
--- a/arch/arm/mach-mmp/mfp.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_MFP_H
-#define __ASM_MACH_MFP_H
-
-#include <plat/mfp.h>
-
-/*
- * NOTE: the MFPR register bit definitions on PXA168 processor lines are a
- * bit different from those on PXA3xx. Bit [7:10] are now reserved, which
- * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits.
- *
- * To cope with this difference and re-use the pxa3xx mfp code as much as
- * possible, we make the following compromise:
- *
- * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT)
- * 2. DRIVE strength definitions redefined to include the reserved bit
- * - the reserved bit differs between pxa168 and pxa910, and the
- * MFP_DRIVE_* macros are individually defined in mfp-pxa{168,910}.h
- * 3. Override MFP_CFG() and MFP_CFG_DRV()
- * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X()
- */
-
-#undef MFP_CFG
-#undef MFP_CFG_DRV
-#undef MFP_CFG_LPM
-#undef MFP_CFG_X
-#undef MFP_CFG_DEFAULT
-
-#define MFP_CFG(pin, af) \
- (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
-
-#define MFP_CFG_DRV(pin, af, drv) \
- (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
-
-#endif /* __ASM_MACH_MFP_H */
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
deleted file mode 100644
index bbc4c2274de3..000000000000
--- a/arch/arm/mach-mmp/mmp2.c
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/mmp2.c
- *
- * code name MMP2
- *
- * Copyright (C) 2009 Marvell International Ltd.
- */
-#include <linux/clk/mmp.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqchip/mmp.h>
-#include <linux/platform_device.h>
-
-#include <asm/hardware/cache-tauros2.h>
-
-#include <asm/mach/time.h>
-#include "addr-map.h"
-#include "regs-apbc.h"
-#include <linux/soc/mmp/cputype.h>
-#include "irqs.h"
-#include "mfp.h"
-#include "devices.h"
-#include "mmp2.h"
-#include "pm-mmp2.h"
-
-#include "common.h"
-
-#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
-
-static struct mfp_addr_map mmp2_addr_map[] __initdata = {
-
- MFP_ADDR_X(GPIO0, GPIO58, 0x54),
- MFP_ADDR_X(GPIO59, GPIO73, 0x280),
- MFP_ADDR_X(GPIO74, GPIO101, 0x170),
-
- MFP_ADDR(GPIO102, 0x0),
- MFP_ADDR(GPIO103, 0x4),
- MFP_ADDR(GPIO104, 0x1fc),
- MFP_ADDR(GPIO105, 0x1f8),
- MFP_ADDR(GPIO106, 0x1f4),
- MFP_ADDR(GPIO107, 0x1f0),
- MFP_ADDR(GPIO108, 0x21c),
- MFP_ADDR(GPIO109, 0x218),
- MFP_ADDR(GPIO110, 0x214),
- MFP_ADDR(GPIO111, 0x200),
- MFP_ADDR(GPIO112, 0x244),
- MFP_ADDR(GPIO113, 0x25c),
- MFP_ADDR(GPIO114, 0x164),
- MFP_ADDR_X(GPIO115, GPIO122, 0x260),
-
- MFP_ADDR(GPIO123, 0x148),
- MFP_ADDR_X(GPIO124, GPIO141, 0xc),
-
- MFP_ADDR(GPIO142, 0x8),
- MFP_ADDR_X(GPIO143, GPIO151, 0x220),
- MFP_ADDR_X(GPIO152, GPIO153, 0x248),
- MFP_ADDR_X(GPIO154, GPIO155, 0x254),
- MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
-
- MFP_ADDR(GPIO160, 0x250),
- MFP_ADDR(GPIO161, 0x210),
- MFP_ADDR(GPIO162, 0x20c),
- MFP_ADDR(GPIO163, 0x208),
- MFP_ADDR(GPIO164, 0x204),
- MFP_ADDR(GPIO165, 0x1ec),
- MFP_ADDR(GPIO166, 0x1e8),
- MFP_ADDR(GPIO167, 0x1e4),
- MFP_ADDR(GPIO168, 0x1e0),
-
- MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
- MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
-
- MFP_ADDR(PMIC_INT, 0x2c4),
- MFP_ADDR(CLK_REQ, 0x160),
-
- MFP_ADDR_END,
-};
-
-void mmp2_clear_pmic_int(void)
-{
- void __iomem *mfpr_pmic;
- unsigned long data;
-
- mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
- data = __raw_readl(mfpr_pmic);
- __raw_writel(data | (1 << 6), mfpr_pmic);
- __raw_writel(data, mfpr_pmic);
-}
-
-void __init mmp2_init_irq(void)
-{
- mmp2_init_icu();
-#ifdef CONFIG_PM
- icu_irq_chip.irq_set_wake = mmp2_set_wake;
-#endif
-}
-
-static int __init mmp2_init(void)
-{
- if (cpu_is_mmp2()) {
-#ifdef CONFIG_CACHE_TAUROS2
- tauros2_init(0);
-#endif
- mfp_init_base(MFPR_VIRT_BASE);
- mfp_init_addr(mmp2_addr_map);
- mmp2_clk_init(APB_PHYS_BASE + 0x50000,
- AXI_PHYS_BASE + 0x82800,
- APB_PHYS_BASE + 0x15000);
- }
-
- return 0;
-}
-postcore_initcall(mmp2_init);
-
-#define APBC_TIMERS APBC_REG(0x024)
-
-void __init mmp2_timer_init(void)
-{
- unsigned long clk_rst;
-
- __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
-
- /*
- * enable bus/functional clock, enable 6.5MHz (divider 4),
- * release reset
- */
- clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
- __raw_writel(clk_rst, APBC_TIMERS);
-
- mmp_timer_init(IRQ_MMP2_TIMER1, 6500000);
-}
-
-/* on-chip devices */
-MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
-MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
-MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
-MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
-MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
-MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
-MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
-MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
-MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
-MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
-MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
-MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
-MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
-MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
-MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
-MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
-/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
-MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
-
-struct resource mmp2_resource_gpio[] = {
- {
- .start = 0xd4019000,
- .end = 0xd4019fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MMP2_GPIO,
- .end = IRQ_MMP2_GPIO,
- .name = "gpio_mux",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mmp2_device_gpio = {
- .name = "mmp2-gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(mmp2_resource_gpio),
- .resource = mmp2_resource_gpio,
-};
diff --git a/arch/arm/mach-mmp/mmp2.h b/arch/arm/mach-mmp/mmp2.h
deleted file mode 100644
index adafc4fba8f4..000000000000
--- a/arch/arm/mach-mmp/mmp2.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_MMP2_H
-#define __ASM_MACH_MMP2_H
-
-#include <linux/platform_data/pxa_sdhci.h>
-
-extern void mmp2_timer_init(void);
-extern void __init mmp2_init_icu(void);
-extern void __init mmp2_init_irq(void);
-extern void mmp2_clear_pmic_int(void);
-
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/dma-mmp_tdma.h>
-
-#include "devices.h"
-
-extern struct pxa_device_desc mmp2_device_uart1;
-extern struct pxa_device_desc mmp2_device_uart2;
-extern struct pxa_device_desc mmp2_device_uart3;
-extern struct pxa_device_desc mmp2_device_uart4;
-extern struct pxa_device_desc mmp2_device_twsi1;
-extern struct pxa_device_desc mmp2_device_twsi2;
-extern struct pxa_device_desc mmp2_device_twsi3;
-extern struct pxa_device_desc mmp2_device_twsi4;
-extern struct pxa_device_desc mmp2_device_twsi5;
-extern struct pxa_device_desc mmp2_device_twsi6;
-extern struct pxa_device_desc mmp2_device_sdh0;
-extern struct pxa_device_desc mmp2_device_sdh1;
-extern struct pxa_device_desc mmp2_device_sdh2;
-extern struct pxa_device_desc mmp2_device_sdh3;
-extern struct pxa_device_desc mmp2_device_asram;
-extern struct pxa_device_desc mmp2_device_isram;
-
-extern struct platform_device mmp2_device_gpio;
-
-static inline int mmp2_add_uart(int id)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 1: d = &mmp2_device_uart1; break;
- case 2: d = &mmp2_device_uart2; break;
- case 3: d = &mmp2_device_uart3; break;
- case 4: d = &mmp2_device_uart4; break;
- default:
- return -EINVAL;
- }
-
- return pxa_register_device(d, NULL, 0);
-}
-
-static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
- struct i2c_board_info *info, unsigned size)
-{
- struct pxa_device_desc *d = NULL;
- int ret;
-
- switch (id) {
- case 1: d = &mmp2_device_twsi1; break;
- case 2: d = &mmp2_device_twsi2; break;
- case 3: d = &mmp2_device_twsi3; break;
- case 4: d = &mmp2_device_twsi4; break;
- case 5: d = &mmp2_device_twsi5; break;
- case 6: d = &mmp2_device_twsi6; break;
- default:
- return -EINVAL;
- }
-
- ret = i2c_register_board_info(id - 1, info, size);
- if (ret)
- return ret;
-
- return pxa_register_device(d, data, sizeof(*data));
-}
-
-static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 0: d = &mmp2_device_sdh0; break;
- case 1: d = &mmp2_device_sdh1; break;
- case 2: d = &mmp2_device_sdh2; break;
- case 3: d = &mmp2_device_sdh3; break;
- default:
- return -EINVAL;
- }
-
- return pxa_register_device(d, data, sizeof(*data));
-}
-
-static inline int mmp2_add_asram(struct sram_platdata *data)
-{
- return pxa_register_device(&mmp2_device_asram, data, sizeof(*data));
-}
-
-static inline int mmp2_add_isram(struct sram_platdata *data)
-{
- return pxa_register_device(&mmp2_device_isram, data, sizeof(*data));
-}
-
-#endif /* __ASM_MACH_MMP2_H */
-
diff --git a/arch/arm/mach-mmp/pm-mmp2.c b/arch/arm/mach-mmp/pm-mmp2.c
deleted file mode 100644
index 7a6f74c32d42..000000000000
--- a/arch/arm/mach-mmp/pm-mmp2.c
+++ /dev/null
@@ -1,248 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * MMP2 Power Management Routines
- *
- * (C) Copyright 2012 Marvell International Ltd.
- * All Rights Reserved
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/suspend.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <asm/mach-types.h>
-
-#include <linux/soc/mmp/cputype.h>
-#include "addr-map.h"
-#include "pm-mmp2.h"
-#include "regs-icu.h"
-#include "irqs.h"
-
-int mmp2_set_wake(struct irq_data *d, unsigned int on)
-{
- unsigned long data = 0;
- int irq = d->irq;
-
- /* enable wakeup sources */
- switch (irq) {
- case IRQ_MMP2_RTC:
- case IRQ_MMP2_RTC_ALARM:
- data = MPMU_WUCRM_PJ_WAKEUP(4) | MPMU_WUCRM_PJ_RTC_ALARM;
- break;
- case IRQ_MMP2_PMIC:
- data = MPMU_WUCRM_PJ_WAKEUP(7);
- break;
- case IRQ_MMP2_MMC2:
- /* mmc use WAKEUP2, same as GPIO wakeup source */
- data = MPMU_WUCRM_PJ_WAKEUP(2);
- break;
- }
- if (on) {
- if (data) {
- data |= __raw_readl(MPMU_WUCRM_PJ);
- __raw_writel(data, MPMU_WUCRM_PJ);
- }
- } else {
- if (data) {
- data = ~data & __raw_readl(MPMU_WUCRM_PJ);
- __raw_writel(data, MPMU_WUCRM_PJ);
- }
- }
- return 0;
-}
-
-static void pm_scu_clk_disable(void)
-{
- unsigned int val;
-
- /* close AXI fabric clock gate */
- __raw_writel(0x0, CIU_REG(0x64));
- __raw_writel(0x0, CIU_REG(0x68));
-
- /* close MCB master clock gate */
- val = __raw_readl(CIU_REG(0x1c));
- val |= 0xf0;
- __raw_writel(val, CIU_REG(0x1c));
-
- return ;
-}
-
-static void pm_scu_clk_enable(void)
-{
- unsigned int val;
-
- /* open AXI fabric clock gate */
- __raw_writel(0x03003003, CIU_REG(0x64));
- __raw_writel(0x00303030, CIU_REG(0x68));
-
- /* open MCB master clock gate */
- val = __raw_readl(CIU_REG(0x1c));
- val &= ~(0xf0);
- __raw_writel(val, CIU_REG(0x1c));
-
- return ;
-}
-
-static void pm_mpmu_clk_disable(void)
-{
- /*
- * disable clocks in MPMU_CGR_PJ register
- * except clock for APMU_PLL1, APMU_PLL1_2 and AP_26M
- */
- __raw_writel(0x0000a010, MPMU_CGR_PJ);
-}
-
-static void pm_mpmu_clk_enable(void)
-{
- unsigned int val;
-
- __raw_writel(0xdffefffe, MPMU_CGR_PJ);
- val = __raw_readl(MPMU_PLL2_CTRL1);
- val |= (1 << 29);
- __raw_writel(val, MPMU_PLL2_CTRL1);
-
- return ;
-}
-
-void mmp2_pm_enter_lowpower_mode(int state)
-{
- uint32_t idle_cfg, apcr;
-
- idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG);
- apcr = __raw_readl(MPMU_PCR_PJ);
- apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD
- | MPMU_PCR_PJ_AXISD | MPMU_PCR_PJ_VCTCXOSD | (1 << 13));
- idle_cfg &= ~APMU_PJ_IDLE_CFG_PJ_IDLE;
-
- switch (state) {
- case POWER_MODE_SYS_SLEEP:
- apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */
- apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */
- fallthrough;
- case POWER_MODE_CHIP_SLEEP:
- apcr |= MPMU_PCR_PJ_SLPEN;
- fallthrough;
- case POWER_MODE_APPS_SLEEP:
- apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */
- fallthrough;
- case POWER_MODE_APPS_IDLE:
- apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */
- apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */
- idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */
- apcr |= MPMU_PCR_PJ_SPSD;
- fallthrough;
- case POWER_MODE_CORE_EXTIDLE:
- idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */
- idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
- idle_cfg |= APMU_PJ_IDLE_CFG_PWR_SW(3)
- | APMU_PJ_IDLE_CFG_L2_PWR_SW;
- break;
- case POWER_MODE_CORE_INTIDLE:
- apcr &= ~MPMU_PCR_PJ_SPSD;
- break;
- }
-
- /* set reserve bits */
- apcr |= (1 << 30) | (1 << 25);
-
- /* finally write the registers back */
- __raw_writel(idle_cfg, APMU_PJ_IDLE_CFG);
- __raw_writel(apcr, MPMU_PCR_PJ); /* 0xfe086000 */
-}
-
-static int mmp2_pm_enter(suspend_state_t state)
-{
- int temp;
-
- temp = __raw_readl(MMP2_ICU_INT4_MASK);
- if (temp & (1 << 1)) {
- printk(KERN_ERR "%s: PMIC interrupt is handling\n", __func__);
- return -EAGAIN;
- }
-
- temp = __raw_readl(APMU_SRAM_PWR_DWN);
- temp |= ((1 << 19) | (1 << 18));
- __raw_writel(temp, APMU_SRAM_PWR_DWN);
- pm_mpmu_clk_disable();
- pm_scu_clk_disable();
-
- printk(KERN_INFO "%s: before suspend\n", __func__);
- cpu_do_idle();
- printk(KERN_INFO "%s: after suspend\n", __func__);
-
- pm_mpmu_clk_enable(); /* enable clocks in MPMU */
- pm_scu_clk_enable(); /* enable clocks in SCU */
-
- return 0;
-}
-
-/*
- * Called after processes are frozen, but before we shut down devices.
- */
-static int mmp2_pm_prepare(void)
-{
- mmp2_pm_enter_lowpower_mode(POWER_MODE_SYS_SLEEP);
-
- return 0;
-}
-
-/*
- * Called after devices are re-setup, but before processes are thawed.
- */
-static void mmp2_pm_finish(void)
-{
- mmp2_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE);
-}
-
-static int mmp2_pm_valid(suspend_state_t state)
-{
- return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM));
-}
-
-/*
- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
- */
-static const struct platform_suspend_ops mmp2_pm_ops = {
- .valid = mmp2_pm_valid,
- .prepare = mmp2_pm_prepare,
- .enter = mmp2_pm_enter,
- .finish = mmp2_pm_finish,
-};
-
-static int __init mmp2_pm_init(void)
-{
- uint32_t apcr;
-
- if (!cpu_is_mmp2())
- return -EIO;
-
- suspend_set_ops(&mmp2_pm_ops);
-
- /*
- * Set bit 0, Slow clock Select 32K clock input instead of VCXO
- * VCXO is chosen by default, which would be disabled in suspend
- */
- __raw_writel(0x5, MPMU_SCCR);
-
- /*
- * Clear bit 23 of CIU_CPU_CONF
- * direct PJ4 to DDR access through Memory Controller slow queue
- * fast queue has issue and cause lcd will flick
- */
- __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8));
-
- /* Clear default low power control bit */
- apcr = __raw_readl(MPMU_PCR_PJ);
- apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD
- | MPMU_PCR_PJ_APBSD | MPMU_PCR_PJ_AXISD | 1 << 13);
- __raw_writel(apcr, MPMU_PCR_PJ);
-
- return 0;
-}
-
-late_initcall(mmp2_pm_init);
diff --git a/arch/arm/mach-mmp/pm-mmp2.h b/arch/arm/mach-mmp/pm-mmp2.h
deleted file mode 100644
index 70299a9450d3..000000000000
--- a/arch/arm/mach-mmp/pm-mmp2.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * MMP2 Power Management Routines
- *
- * (C) Copyright 2010 Marvell International Ltd.
- * All Rights Reserved
- */
-
-#ifndef __MMP2_PM_H__
-#define __MMP2_PM_H__
-
-#include "addr-map.h"
-
-#define APMU_PJ_IDLE_CFG APMU_REG(0x018)
-#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
-#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
-#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
-#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
-#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
-
-#define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
-
-#define MPMU_SCCR MPMU_REG(0x038)
-#define MPMU_PCR_PJ MPMU_REG(0x1000)
-#define MPMU_PCR_PJ_AXISD (1 << 31)
-#define MPMU_PCR_PJ_SLPEN (1 << 29)
-#define MPMU_PCR_PJ_SPSD (1 << 28)
-#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
-#define MPMU_PCR_PJ_APBSD (1 << 26)
-#define MPMU_PCR_PJ_INTCLR (1 << 24)
-#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
-#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
-#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
-#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
-#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
-#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
-#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
-#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
-#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
-
-#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
-#define MPMU_CGR_PJ MPMU_REG(0x1024)
-#define MPMU_WUCRM_PJ MPMU_REG(0x104c)
-#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
-#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
-
-enum {
- POWER_MODE_ACTIVE = 0,
- POWER_MODE_CORE_INTIDLE,
- POWER_MODE_CORE_EXTIDLE,
- POWER_MODE_APPS_IDLE,
- POWER_MODE_APPS_SLEEP,
- POWER_MODE_CHIP_SLEEP,
- POWER_MODE_SYS_SLEEP,
-};
-
-extern void mmp2_pm_enter_lowpower_mode(int state);
-extern int mmp2_set_wake(struct irq_data *d, unsigned int on);
-#endif
diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c
deleted file mode 100644
index 1d71d73c1862..000000000000
--- a/arch/arm/mach-mmp/pm-pxa910.c
+++ /dev/null
@@ -1,272 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * PXA910 Power Management Routines
- *
- * (C) Copyright 2009 Marvell International Ltd.
- * All Rights Reserved
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/suspend.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <asm/mach-types.h>
-#include <asm/outercache.h>
-
-#include <linux/soc/mmp/cputype.h>
-#include "addr-map.h"
-#include "pm-pxa910.h"
-#include "regs-icu.h"
-#include "irqs.h"
-
-int pxa910_set_wake(struct irq_data *data, unsigned int on)
-{
- uint32_t awucrm = 0, apcr = 0;
- int irq = data->irq;
-
- /* setting wakeup sources */
- switch (irq) {
- /* wakeup line 2 */
- case IRQ_PXA910_AP_GPIO:
- awucrm = MPMU_AWUCRM_WAKEUP(2);
- apcr |= MPMU_APCR_SLPWP2;
- break;
- /* wakeup line 3 */
- case IRQ_PXA910_KEYPAD:
- awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_KEYPRESS;
- apcr |= MPMU_APCR_SLPWP3;
- break;
- case IRQ_PXA910_ROTARY:
- awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_NEWROTARY;
- apcr |= MPMU_APCR_SLPWP3;
- break;
- case IRQ_PXA910_TRACKBALL:
- awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_TRACKBALL;
- apcr |= MPMU_APCR_SLPWP3;
- break;
- /* wakeup line 4 */
- case IRQ_PXA910_AP1_TIMER1:
- awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_1;
- apcr |= MPMU_APCR_SLPWP4;
- break;
- case IRQ_PXA910_AP1_TIMER2:
- awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_2;
- apcr |= MPMU_APCR_SLPWP4;
- break;
- case IRQ_PXA910_AP1_TIMER3:
- awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_3;
- apcr |= MPMU_APCR_SLPWP4;
- break;
- case IRQ_PXA910_AP2_TIMER1:
- awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_1;
- apcr |= MPMU_APCR_SLPWP4;
- break;
- case IRQ_PXA910_AP2_TIMER2:
- awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_2;
- apcr |= MPMU_APCR_SLPWP4;
- break;
- case IRQ_PXA910_AP2_TIMER3:
- awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_3;
- apcr |= MPMU_APCR_SLPWP4;
- break;
- case IRQ_PXA910_RTC_ALARM:
- awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_RTC_ALARM;
- apcr |= MPMU_APCR_SLPWP4;
- break;
- /* wakeup line 5 */
- case IRQ_PXA910_USB1:
- case IRQ_PXA910_USB2:
- awucrm = MPMU_AWUCRM_WAKEUP(5);
- apcr |= MPMU_APCR_SLPWP5;
- break;
- /* wakeup line 6 */
- case IRQ_PXA910_MMC:
- awucrm = MPMU_AWUCRM_WAKEUP(6)
- | MPMU_AWUCRM_SDH1
- | MPMU_AWUCRM_SDH2;
- apcr |= MPMU_APCR_SLPWP6;
- break;
- /* wakeup line 7 */
- case IRQ_PXA910_PMIC_INT:
- awucrm = MPMU_AWUCRM_WAKEUP(7);
- apcr |= MPMU_APCR_SLPWP7;
- break;
- default:
- if (irq >= IRQ_GPIO_START && irq < IRQ_BOARD_START) {
- awucrm = MPMU_AWUCRM_WAKEUP(2);
- apcr |= MPMU_APCR_SLPWP2;
- } else {
- /* FIXME: This should return a proper error code ! */
- printk(KERN_ERR "Error: no defined wake up source irq: %d\n",
- irq);
- }
- }
-
- if (on) {
- if (awucrm) {
- awucrm |= __raw_readl(MPMU_AWUCRM);
- __raw_writel(awucrm, MPMU_AWUCRM);
- }
- if (apcr) {
- apcr = ~apcr & __raw_readl(MPMU_APCR);
- __raw_writel(apcr, MPMU_APCR);
- }
- } else {
- if (awucrm) {
- awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM);
- __raw_writel(awucrm, MPMU_AWUCRM);
- }
- if (apcr) {
- apcr |= __raw_readl(MPMU_APCR);
- __raw_writel(apcr, MPMU_APCR);
- }
- }
- return 0;
-}
-
-void pxa910_pm_enter_lowpower_mode(int state)
-{
- uint32_t idle_cfg, apcr;
-
- idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
- apcr = __raw_readl(MPMU_APCR);
-
- apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD
- | MPMU_APCR_VCTCXOSD | MPMU_APCR_STBYEN);
- idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_IDLE
- | APMU_MOH_IDLE_CFG_MOH_PWRDWN);
-
- switch (state) {
- case POWER_MODE_UDR:
- /* only shutdown APB in UDR */
- apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
- fallthrough;
- case POWER_MODE_SYS_SLEEP:
- apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */
- apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */
- fallthrough;
- case POWER_MODE_APPS_SLEEP:
- apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */
- fallthrough;
- case POWER_MODE_APPS_IDLE:
- apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */
- fallthrough;
- case POWER_MODE_CORE_EXTIDLE:
- idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
- idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
- idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
- | APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
- fallthrough;
- case POWER_MODE_CORE_INTIDLE:
- break;
- }
-
- /* program the memory controller hardware sleep type and auto wakeup */
- idle_cfg |= APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ;
- idle_cfg |= APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN;
- __raw_writel(0x0, APMU_MC_HW_SLP_TYPE); /* auto refresh */
-
- /* set DSPSD, DTCMSD, BBSD, MSASLPEN */
- apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD
- | MPMU_APCR_MSASLPEN;
-
- /*always set SLEPEN bit mainly for MSA*/
- apcr |= MPMU_APCR_SLPEN;
-
- /* finally write the registers back */
- __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
- __raw_writel(apcr, MPMU_APCR);
-
-}
-
-static int pxa910_pm_enter(suspend_state_t state)
-{
- unsigned int idle_cfg, reg = 0;
-
- /*pmic thread not completed,exit;otherwise system can't be waked up*/
- reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT));
- if ((reg & 0x3) == 0)
- return -EAGAIN;
-
- idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
- idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN
- | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN;
- __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
-
- /* disable L2 */
- outer_disable();
- /* wait for l2 idle */
- while (!(readl(CIU_REG(0x8)) & (1 << 16)))
- udelay(1);
-
- cpu_do_idle();
-
- /* enable L2 */
- outer_resume();
- /* wait for l2 idle */
- while (!(readl(CIU_REG(0x8)) & (1 << 16)))
- udelay(1);
-
- idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
- idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_PWRDWN
- | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN);
- __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
-
- return 0;
-}
-
-/*
- * Called after processes are frozen, but before we shut down devices.
- */
-static int pxa910_pm_prepare(void)
-{
- pxa910_pm_enter_lowpower_mode(POWER_MODE_UDR);
- return 0;
-}
-
-/*
- * Called after devices are re-setup, but before processes are thawed.
- */
-static void pxa910_pm_finish(void)
-{
- pxa910_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE);
-}
-
-static int pxa910_pm_valid(suspend_state_t state)
-{
- return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM));
-}
-
-static const struct platform_suspend_ops pxa910_pm_ops = {
- .valid = pxa910_pm_valid,
- .prepare = pxa910_pm_prepare,
- .enter = pxa910_pm_enter,
- .finish = pxa910_pm_finish,
-};
-
-static int __init pxa910_pm_init(void)
-{
- uint32_t awucrm = 0;
-
- if (!cpu_is_pxa910())
- return -EIO;
-
- suspend_set_ops(&pxa910_pm_ops);
-
- /* Set the following bits for MMP3 playback with VCTXO on */
- __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30),
- APMU_SQU_CLK_GATE_CTRL);
- __raw_writel(__raw_readl(MPMU_FCCR) | (1 << 28), MPMU_FCCR);
-
- awucrm |= MPMU_AWUCRM_AP_ASYNC_INT | MPMU_AWUCRM_AP_FULL_IDLE;
- __raw_writel(awucrm, MPMU_AWUCRM);
-
- return 0;
-}
-
-late_initcall(pxa910_pm_init);
diff --git a/arch/arm/mach-mmp/pm-pxa910.h b/arch/arm/mach-mmp/pm-pxa910.h
deleted file mode 100644
index 8e6344adaf51..000000000000
--- a/arch/arm/mach-mmp/pm-pxa910.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * PXA910 Power Management Routines
- *
- * (C) Copyright 2009 Marvell International Ltd.
- * All Rights Reserved
- */
-
-#ifndef __PXA910_PM_H__
-#define __PXA910_PM_H__
-
-#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
-#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
-#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
-#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
-#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
-#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
-#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
-#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
-
-#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
-#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
-
-#define MPMU_FCCR MPMU_REG(0x0008)
-#define MPMU_APCR MPMU_REG(0x1000)
-#define MPMU_APCR_AXISD (1 << 31)
-#define MPMU_APCR_DSPSD (1 << 30)
-#define MPMU_APCR_SLPEN (1 << 29)
-#define MPMU_APCR_DTCMSD (1 << 28)
-#define MPMU_APCR_DDRCORSD (1 << 27)
-#define MPMU_APCR_APBSD (1 << 26)
-#define MPMU_APCR_BBSD (1 << 25)
-#define MPMU_APCR_SLPWP0 (1 << 23)
-#define MPMU_APCR_SLPWP1 (1 << 22)
-#define MPMU_APCR_SLPWP2 (1 << 21)
-#define MPMU_APCR_SLPWP3 (1 << 20)
-#define MPMU_APCR_VCTCXOSD (1 << 19)
-#define MPMU_APCR_SLPWP4 (1 << 18)
-#define MPMU_APCR_SLPWP5 (1 << 17)
-#define MPMU_APCR_SLPWP6 (1 << 16)
-#define MPMU_APCR_SLPWP7 (1 << 15)
-#define MPMU_APCR_MSASLPEN (1 << 14)
-#define MPMU_APCR_STBYEN (1 << 13)
-
-#define MPMU_AWUCRM MPMU_REG(0x104c)
-#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
-#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
-#define MPMU_AWUCRM_SDH1 (1 << 23)
-#define MPMU_AWUCRM_SDH2 (1 << 22)
-#define MPMU_AWUCRM_KEYPRESS (1 << 21)
-#define MPMU_AWUCRM_TRACKBALL (1 << 20)
-#define MPMU_AWUCRM_NEWROTARY (1 << 19)
-#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
-#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
-#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
-#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
-#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
-#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
-#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
-#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
-
-enum {
- POWER_MODE_ACTIVE = 0,
- POWER_MODE_CORE_INTIDLE,
- POWER_MODE_CORE_EXTIDLE,
- POWER_MODE_APPS_IDLE,
- POWER_MODE_APPS_SLEEP,
- POWER_MODE_SYS_SLEEP,
- POWER_MODE_HIBERNATE,
- POWER_MODE_UDR,
-};
-
-extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
-
-#endif
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
deleted file mode 100644
index 1e9389245d0e..000000000000
--- a/arch/arm/mach-mmp/pxa168.c
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/pxa168.c
- *
- * Code specific to PXA168
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clk/mmp.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/mv_usb.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/mach/time.h>
-#include <asm/system_misc.h>
-
-#include "addr-map.h"
-#include "common.h"
-#include <linux/soc/mmp/cputype.h>
-#include "devices.h"
-#include "irqs.h"
-#include "mfp.h"
-#include "pxa168.h"
-#include "regs-apbc.h"
-#include "regs-apmu.h"
-#include "regs-usb.h"
-
-#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
-
-static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata =
-{
- MFP_ADDR_X(GPIO0, GPIO36, 0x04c),
- MFP_ADDR_X(GPIO37, GPIO55, 0x000),
- MFP_ADDR_X(GPIO56, GPIO123, 0x0e0),
- MFP_ADDR_X(GPIO124, GPIO127, 0x0f4),
-
- MFP_ADDR_END,
-};
-
-void __init pxa168_init_irq(void)
-{
- icu_init_irq();
-}
-
-static int __init pxa168_init(void)
-{
- if (cpu_is_pxa168()) {
- mfp_init_base(MFPR_VIRT_BASE);
- mfp_init_addr(pxa168_mfp_addr_map);
- pxa168_clk_init(APB_PHYS_BASE + 0x50000,
- AXI_PHYS_BASE + 0x82800,
- APB_PHYS_BASE + 0x15000);
- }
-
- return 0;
-}
-postcore_initcall(pxa168_init);
-
-/* system timer - clock enabled, 3.25MHz */
-#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
-#define APBC_TIMERS APBC_REG(0x34)
-
-void __init pxa168_timer_init(void)
-{
- /* this is early, we have to initialize the CCU registers by
- * ourselves instead of using clk_* API. Clock rate is defined
- * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
- */
- __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
-
- /* 3.25MHz, bus/functional clock enabled, release reset */
- __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
-
- mmp_timer_init(IRQ_PXA168_TIMER1, 3250000);
-}
-
-void pxa168_clear_keypad_wakeup(void)
-{
- uint32_t val;
- uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
-
- /* wake event clear is needed in order to clear keypad interrupt */
- val = __raw_readl(APMU_WAKE_CLR);
- __raw_writel(val | mask, APMU_WAKE_CLR);
-}
-
-/* on-chip devices */
-PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
-PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
-PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24);
-PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
-PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
-PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
-PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10);
-PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10);
-PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10);
-PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
-PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53);
-PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
-PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
-PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
-PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
-PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
-PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
-PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
-
-struct resource pxa168_resource_gpio[] = {
- {
- .start = 0xd4019000,
- .end = 0xd4019fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PXA168_GPIOX,
- .end = IRQ_PXA168_GPIOX,
- .name = "gpio_mux",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa168_device_gpio = {
- .name = "mmp-gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa168_resource_gpio),
- .resource = pxa168_resource_gpio,
-};
-
-struct resource pxa168_usb_host_resources[] = {
- /* USB Host conroller register base */
- [0] = {
- .start = PXA168_U2H_REGBASE + U2x_CAPREGS_OFFSET,
- .end = PXA168_U2H_REGBASE + USB_REG_RANGE,
- .flags = IORESOURCE_MEM,
- .name = "capregs",
- },
- /* USB PHY register base */
- [1] = {
- .start = PXA168_U2H_PHYBASE,
- .end = PXA168_U2H_PHYBASE + USB_PHY_RANGE,
- .flags = IORESOURCE_MEM,
- .name = "phyregs",
- },
- [2] = {
- .start = IRQ_PXA168_USB2,
- .end = IRQ_PXA168_USB2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 pxa168_usb_host_dmamask = DMA_BIT_MASK(32);
-struct platform_device pxa168_device_usb_host = {
- .name = "pxa-sph",
- .id = -1,
- .dev = {
- .dma_mask = &pxa168_usb_host_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-
- .num_resources = ARRAY_SIZE(pxa168_usb_host_resources),
- .resource = pxa168_usb_host_resources,
-};
-
-int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
-{
- pxa168_device_usb_host.dev.platform_data = pdata;
- return platform_device_register(&pxa168_device_usb_host);
-}
-
-void pxa168_restart(enum reboot_mode mode, const char *cmd)
-{
- soft_restart(0xffff0000);
-}
diff --git a/arch/arm/mach-mmp/pxa168.h b/arch/arm/mach-mmp/pxa168.h
deleted file mode 100644
index dff651b9f252..000000000000
--- a/arch/arm/mach-mmp/pxa168.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_PXA168_H
-#define __ASM_MACH_PXA168_H
-
-#include <linux/reboot.h>
-
-extern void pxa168_timer_init(void);
-extern void __init icu_init_irq(void);
-extern void __init pxa168_init_irq(void);
-extern void pxa168_restart(enum reboot_mode, const char *);
-extern void pxa168_clear_keypad_wakeup(void);
-
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-#include <video/pxa168fb.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/pxa168_eth.h>
-#include <linux/platform_data/mv_usb.h>
-#include <linux/soc/mmp/cputype.h>
-
-#include "devices.h"
-
-extern struct pxa_device_desc pxa168_device_uart1;
-extern struct pxa_device_desc pxa168_device_uart2;
-extern struct pxa_device_desc pxa168_device_uart3;
-extern struct pxa_device_desc pxa168_device_twsi0;
-extern struct pxa_device_desc pxa168_device_twsi1;
-extern struct pxa_device_desc pxa168_device_pwm1;
-extern struct pxa_device_desc pxa168_device_pwm2;
-extern struct pxa_device_desc pxa168_device_pwm3;
-extern struct pxa_device_desc pxa168_device_pwm4;
-extern struct pxa_device_desc pxa168_device_ssp1;
-extern struct pxa_device_desc pxa168_device_ssp2;
-extern struct pxa_device_desc pxa168_device_ssp3;
-extern struct pxa_device_desc pxa168_device_ssp4;
-extern struct pxa_device_desc pxa168_device_ssp5;
-extern struct pxa_device_desc pxa168_device_nand;
-extern struct pxa_device_desc pxa168_device_fb;
-extern struct pxa_device_desc pxa168_device_keypad;
-extern struct pxa_device_desc pxa168_device_eth;
-
-/* pdata can be NULL */
-extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata);
-
-
-extern struct platform_device pxa168_device_gpio;
-
-static inline int pxa168_add_uart(int id)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 1: d = &pxa168_device_uart1; break;
- case 2: d = &pxa168_device_uart2; break;
- case 3: d = &pxa168_device_uart3; break;
- }
-
- if (d == NULL)
- return -EINVAL;
-
- return pxa_register_device(d, NULL, 0);
-}
-
-static inline int pxa168_add_twsi(int id, struct i2c_pxa_platform_data *data,
- struct i2c_board_info *info, unsigned size)
-{
- struct pxa_device_desc *d = NULL;
- int ret;
-
- switch (id) {
- case 0: d = &pxa168_device_twsi0; break;
- case 1: d = &pxa168_device_twsi1; break;
- default:
- return -EINVAL;
- }
-
- ret = i2c_register_board_info(id, info, size);
- if (ret)
- return ret;
-
- return pxa_register_device(d, data, sizeof(*data));
-}
-
-static inline int pxa168_add_pwm(int id)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 1: d = &pxa168_device_pwm1; break;
- case 2: d = &pxa168_device_pwm2; break;
- case 3: d = &pxa168_device_pwm3; break;
- case 4: d = &pxa168_device_pwm4; break;
- default:
- return -EINVAL;
- }
-
- return pxa_register_device(d, NULL, 0);
-}
-
-static inline int pxa168_add_ssp(int id)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 1: d = &pxa168_device_ssp1; break;
- case 2: d = &pxa168_device_ssp2; break;
- case 3: d = &pxa168_device_ssp3; break;
- case 4: d = &pxa168_device_ssp4; break;
- case 5: d = &pxa168_device_ssp5; break;
- default:
- return -EINVAL;
- }
- return pxa_register_device(d, NULL, 0);
-}
-
-static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
-{
- return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
-}
-
-static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
-{
- return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
-}
-
-static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
-{
- if (cpu_is_pxa168())
- data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
-
- return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
-}
-
-static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
-{
- return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
-}
-#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
deleted file mode 100644
index b19a069d9fab..000000000000
--- a/arch/arm/mach-mmp/pxa910.c
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/pxa910.c
- *
- * Code specific to PXA910
- */
-#include <linux/clk/mmp.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqchip/mmp.h>
-#include <linux/platform_device.h>
-
-#include <asm/hardware/cache-tauros2.h>
-#include <asm/mach/time.h>
-#include "addr-map.h"
-#include "regs-apbc.h"
-#include <linux/soc/mmp/cputype.h>
-#include "irqs.h"
-#include "mfp.h"
-#include "devices.h"
-#include "pm-pxa910.h"
-#include "pxa910.h"
-
-#include "common.h"
-
-#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
-
-static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
-{
- MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
- MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
- MFP_ADDR_X(GPIO100, GPIO109, 0x238),
-
- MFP_ADDR(GPIO123, 0xcc),
- MFP_ADDR(GPIO124, 0xd0),
-
- MFP_ADDR(DF_IO0, 0x40),
- MFP_ADDR(DF_IO1, 0x3c),
- MFP_ADDR(DF_IO2, 0x38),
- MFP_ADDR(DF_IO3, 0x34),
- MFP_ADDR(DF_IO4, 0x30),
- MFP_ADDR(DF_IO5, 0x2c),
- MFP_ADDR(DF_IO6, 0x28),
- MFP_ADDR(DF_IO7, 0x24),
- MFP_ADDR(DF_IO8, 0x20),
- MFP_ADDR(DF_IO9, 0x1c),
- MFP_ADDR(DF_IO10, 0x18),
- MFP_ADDR(DF_IO11, 0x14),
- MFP_ADDR(DF_IO12, 0x10),
- MFP_ADDR(DF_IO13, 0xc),
- MFP_ADDR(DF_IO14, 0x8),
- MFP_ADDR(DF_IO15, 0x4),
-
- MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
- MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
- MFP_ADDR(SM_nCS0, 0x4c),
- MFP_ADDR(SM_nCS1, 0x50),
- MFP_ADDR(DF_WEn, 0x54),
- MFP_ADDR(DF_REn, 0x58),
- MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
- MFP_ADDR(DF_ALE_SM_WEn, 0x60),
- MFP_ADDR(SM_SCLK, 0x64),
- MFP_ADDR(DF_RDY0, 0x68),
- MFP_ADDR(SM_BE0, 0x6c),
- MFP_ADDR(SM_BE1, 0x70),
- MFP_ADDR(SM_ADV, 0x74),
- MFP_ADDR(DF_RDY1, 0x78),
- MFP_ADDR(SM_ADVMUX, 0x7c),
- MFP_ADDR(SM_RDY, 0x80),
-
- MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
-
- MFP_ADDR_END,
-};
-
-void __init pxa910_init_irq(void)
-{
- icu_init_irq();
-#ifdef CONFIG_PM
- icu_irq_chip.irq_set_wake = pxa910_set_wake;
-#endif
-}
-
-static int __init pxa910_init(void)
-{
- if (cpu_is_pxa910()) {
-#ifdef CONFIG_CACHE_TAUROS2
- tauros2_init(0);
-#endif
- mfp_init_base(MFPR_VIRT_BASE);
- mfp_init_addr(pxa910_mfp_addr_map);
- pxa910_clk_init(APB_PHYS_BASE + 0x50000,
- AXI_PHYS_BASE + 0x82800,
- APB_PHYS_BASE + 0x15000,
- APB_PHYS_BASE + 0x3b000);
- }
-
- return 0;
-}
-postcore_initcall(pxa910_init);
-
-/* system timer - clock enabled, 3.25MHz */
-#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
-#define APBC_TIMERS APBC_REG(0x34)
-
-void __init pxa910_timer_init(void)
-{
- /* reset and configure */
- __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
- __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
-
- mmp_timer_init(IRQ_PXA910_AP1_TIMER1, 3250000);
-}
-
-/* on-chip devices */
-
-/* NOTE: there are totally 3 UARTs on PXA910:
- *
- * UART1 - Slow UART (can be used both by AP and CP)
- * UART2/3 - Fast UART
- *
- * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
- * they are re-ordered as:
- *
- * pxa910_device_uart1 - UART2 as FFUART
- * pxa910_device_uart2 - UART3 as BTUART
- *
- * UART1 is not used by AP for the moment.
- */
-PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
-PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
-PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
-PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
-PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10);
-PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
-PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
-PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
-PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
-PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec);
-PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0);
-PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0);
-
-struct resource pxa910_resource_gpio[] = {
- {
- .start = 0xd4019000,
- .end = 0xd4019fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PXA910_AP_GPIO,
- .end = IRQ_PXA910_AP_GPIO,
- .name = "gpio_mux",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa910_device_gpio = {
- .name = "mmp-gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa910_resource_gpio),
- .resource = pxa910_resource_gpio,
-};
-
-static struct resource pxa910_resource_rtc[] = {
- {
- .start = 0xd4010000,
- .end = 0xd401003f,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PXA910_RTC_INT,
- .end = IRQ_PXA910_RTC_INT,
- .name = "rtc 1Hz",
- .flags = IORESOURCE_IRQ,
- }, {
- .start = IRQ_PXA910_RTC_ALARM,
- .end = IRQ_PXA910_RTC_ALARM,
- .name = "rtc alarm",
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa910_device_rtc = {
- .name = "sa1100-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa910_resource_rtc),
- .resource = pxa910_resource_rtc,
-};
diff --git a/arch/arm/mach-mmp/pxa910.h b/arch/arm/mach-mmp/pxa910.h
deleted file mode 100644
index 2dfe38e4acc1..000000000000
--- a/arch/arm/mach-mmp/pxa910.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_PXA910_H
-#define __ASM_MACH_PXA910_H
-
-extern void pxa910_timer_init(void);
-extern void __init icu_init_irq(void);
-extern void __init pxa910_init_irq(void);
-
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-#include <video/mmp_disp.h>
-
-#include "devices.h"
-
-extern struct pxa_device_desc pxa910_device_uart1;
-extern struct pxa_device_desc pxa910_device_uart2;
-extern struct pxa_device_desc pxa910_device_twsi0;
-extern struct pxa_device_desc pxa910_device_twsi1;
-extern struct pxa_device_desc pxa910_device_pwm1;
-extern struct pxa_device_desc pxa910_device_pwm2;
-extern struct pxa_device_desc pxa910_device_pwm3;
-extern struct pxa_device_desc pxa910_device_pwm4;
-extern struct pxa_device_desc pxa910_device_nand;
-extern struct platform_device pxa168_device_usb_phy;
-extern struct platform_device pxa168_device_u2o;
-extern struct platform_device pxa168_device_u2ootg;
-extern struct platform_device pxa168_device_u2oehci;
-extern struct pxa_device_desc pxa910_device_disp;
-extern struct pxa_device_desc pxa910_device_fb;
-extern struct pxa_device_desc pxa910_device_panel;
-extern struct platform_device pxa910_device_gpio;
-extern struct platform_device pxa910_device_rtc;
-
-static inline int pxa910_add_uart(int id)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 1: d = &pxa910_device_uart1; break;
- case 2: d = &pxa910_device_uart2; break;
- }
-
- if (d == NULL)
- return -EINVAL;
-
- return pxa_register_device(d, NULL, 0);
-}
-
-static inline int pxa910_add_twsi(int id, struct i2c_pxa_platform_data *data,
- struct i2c_board_info *info, unsigned size)
-{
- struct pxa_device_desc *d = NULL;
- int ret;
-
- switch (id) {
- case 0: d = &pxa910_device_twsi0; break;
- case 1: d = &pxa910_device_twsi1; break;
- default:
- return -EINVAL;
- }
-
- ret = i2c_register_board_info(id, info, size);
- if (ret)
- return ret;
-
- return pxa_register_device(d, data, sizeof(*data));
-}
-
-static inline int pxa910_add_pwm(int id)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 1: d = &pxa910_device_pwm1; break;
- case 2: d = &pxa910_device_pwm2; break;
- case 3: d = &pxa910_device_pwm3; break;
- case 4: d = &pxa910_device_pwm4; break;
- default:
- return -EINVAL;
- }
-
- return pxa_register_device(d, NULL, 0);
-}
-
-static inline int pxa910_add_nand(struct pxa3xx_nand_platform_data *info)
-{
- return pxa_register_device(&pxa910_device_nand, info, sizeof(*info));
-}
-#endif /* __ASM_MACH_PXA910_H */
diff --git a/arch/arm/mach-mmp/regs-apbc.h b/arch/arm/mach-mmp/regs-apbc.h
deleted file mode 100644
index d0d00c2cce38..000000000000
--- a/arch/arm/mach-mmp/regs-apbc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Application Peripheral Bus Clock Unit
- */
-
-#ifndef __ASM_MACH_REGS_APBC_H
-#define __ASM_MACH_REGS_APBC_H
-
-#include "addr-map.h"
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
-#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
-#define APBC_RST (1 << 2) /* Reset Generation */
-
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
-
-#endif /* __ASM_MACH_REGS_APBC_H */
diff --git a/arch/arm/mach-mmp/regs-apmu.h b/arch/arm/mach-mmp/regs-apmu.h
deleted file mode 100644
index e36f6503adfb..000000000000
--- a/arch/arm/mach-mmp/regs-apmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Application Subsystem Power Management Unit
- */
-
-#ifndef __ASM_MACH_REGS_APMU_H
-#define __ASM_MACH_REGS_APMU_H
-
-#include "addr-map.h"
-
-#define APMU_FNCLK_EN (1 << 4)
-#define APMU_AXICLK_EN (1 << 3)
-#define APMU_FNRST_DIS (1 << 1)
-#define APMU_AXIRST_DIS (1 << 0)
-
-/* Wake Clear Register */
-#define APMU_WAKE_CLR APMU_REG(0x07c)
-
-#define APMU_PXA168_KP_WAKE_CLR (1 << 7)
-#define APMU_PXA168_CFI_WAKE_CLR (1 << 6)
-#define APMU_PXA168_XD_WAKE_CLR (1 << 5)
-#define APMU_PXA168_MSP_WAKE_CLR (1 << 4)
-#define APMU_PXA168_SD4_WAKE_CLR (1 << 3)
-#define APMU_PXA168_SD3_WAKE_CLR (1 << 2)
-#define APMU_PXA168_SD2_WAKE_CLR (1 << 1)
-#define APMU_PXA168_SD1_WAKE_CLR (1 << 0)
-
-#endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/regs-icu.h b/arch/arm/mach-mmp/regs-icu.h
deleted file mode 100644
index 410743d2b402..000000000000
--- a/arch/arm/mach-mmp/regs-icu.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Interrupt Control Unit
- */
-
-#ifndef __ASM_MACH_ICU_H
-#define __ASM_MACH_ICU_H
-
-#include "addr-map.h"
-
-#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
-#define ICU_REG(x) (ICU_VIRT_BASE + (x))
-
-#define ICU2_VIRT_BASE (AXI_VIRT_BASE + 0x84000)
-#define ICU2_REG(x) (ICU2_VIRT_BASE + (x))
-
-#define ICU_INT_CONF(n) ICU_REG((n) << 2)
-#define ICU_INT_CONF_MASK (0xf)
-
-/************ PXA168/PXA910 (MMP) *********************/
-#define ICU_INT_CONF_AP_INT (1 << 6)
-#define ICU_INT_CONF_CP_INT (1 << 5)
-#define ICU_INT_CONF_IRQ (1 << 4)
-
-#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
-#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
-#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
-#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
-#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
-
-/************************** MMP2 ***********************/
-
-/*
- * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
- * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
- */
-#define ICU_INT_ROUTE_SP_IRQ (1 << 4)
-#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
-#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
-
-#define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
-#define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
-#define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140)
-#define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144)
-
-#define MMP2_ICU_INT4_STATUS ICU_REG(0x150)
-#define MMP2_ICU_INT5_STATUS ICU_REG(0x154)
-#define MMP2_ICU_INT17_STATUS ICU_REG(0x158)
-#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c)
-#define MMP2_ICU_INT51_STATUS ICU_REG(0x160)
-
-#define MMP2_ICU_INT4_MASK ICU_REG(0x168)
-#define MMP2_ICU_INT5_MASK ICU_REG(0x16C)
-#define MMP2_ICU_INT17_MASK ICU_REG(0x170)
-#define MMP2_ICU_INT35_MASK ICU_REG(0x174)
-#define MMP2_ICU_INT51_MASK ICU_REG(0x178)
-
-#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100)
-#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104)
-#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108)
-
-#define MMP2_ICU_INVERT ICU_REG(0x164)
-
-#define MMP2_ICU_INV_PMIC (1 << 0)
-#define MMP2_ICU_INV_PERF (1 << 1)
-#define MMP2_ICU_INV_COMMTX (1 << 2)
-#define MMP2_ICU_INV_COMMRX (1 << 3)
-
-#endif /* __ASM_MACH_ICU_H */
diff --git a/arch/arm/mach-mmp/regs-timers.h b/arch/arm/mach-mmp/regs-timers.h
index a69f4d7e3443..0cc4aca40e2c 100644
--- a/arch/arm/mach-mmp/regs-timers.h
+++ b/arch/arm/mach-mmp/regs-timers.h
@@ -6,11 +6,6 @@
#ifndef __ASM_MACH_REGS_TIMERS_H
#define __ASM_MACH_REGS_TIMERS_H
-#include "addr-map.h"
-
-#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
-#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
-
#define TMR_CCR (0x0000)
#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
#define TMR_CR(n) (0x0028 + ((n) << 2))
diff --git a/arch/arm/mach-mmp/regs-usb.h b/arch/arm/mach-mmp/regs-usb.h
deleted file mode 100644
index ed0d1aa0ad6c..000000000000
--- a/arch/arm/mach-mmp/regs-usb.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
- */
-
-#ifndef __ASM_ARCH_REGS_USB_H
-#define __ASM_ARCH_REGS_USB_H
-
-#define PXA168_U2O_REGBASE (0xd4208000)
-#define PXA168_U2O_PHYBASE (0xd4207000)
-
-#define PXA168_U2H_REGBASE (0xd4209000)
-#define PXA168_U2H_PHYBASE (0xd4206000)
-
-#define MMP3_HSIC1_REGBASE (0xf0001000)
-#define MMP3_HSIC1_PHYBASE (0xf0001800)
-
-#define MMP3_HSIC2_REGBASE (0xf0002000)
-#define MMP3_HSIC2_PHYBASE (0xf0002800)
-
-#define MMP3_FSIC_REGBASE (0xf0003000)
-#define MMP3_FSIC_PHYBASE (0xf0003800)
-
-
-#define USB_REG_RANGE (0x1ff)
-#define USB_PHY_RANGE (0xff)
-
-/* registers */
-#define U2x_CAPREGS_OFFSET 0x100
-
-/* phy regs */
-#define UTMI_REVISION 0x0
-#define UTMI_CTRL 0x4
-#define UTMI_PLL 0x8
-#define UTMI_TX 0xc
-#define UTMI_RX 0x10
-#define UTMI_IVREF 0x14
-#define UTMI_T0 0x18
-#define UTMI_T1 0x1c
-#define UTMI_T2 0x20
-#define UTMI_T3 0x24
-#define UTMI_T4 0x28
-#define UTMI_T5 0x2c
-#define UTMI_RESERVE 0x30
-#define UTMI_USB_INT 0x34
-#define UTMI_DBG_CTL 0x38
-#define UTMI_OTG_ADDON 0x3c
-
-/* For UTMICTRL Register */
-#define UTMI_CTRL_USB_CLK_EN (1 << 31)
-/* pxa168 */
-#define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
-#define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
-#define UTMI_CTRL_RXBUF_PDWN (1 << 24)
-#define UTMI_CTRL_TXBUF_PDWN (1 << 11)
-
-#define UTMI_CTRL_INPKT_DELAY_SHIFT 30
-#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
-#define UTMI_CTRL_PU_REF_SHIFT 20
-#define UTMI_CTRL_ARC_PULLDN_SHIFT 12
-#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
-#define UTMI_CTRL_PWR_UP_SHIFT 0
-
-/* For UTMI_PLL Register */
-#define UTMI_PLL_PLLCALI12_SHIFT 29
-#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
-
-#define UTMI_PLL_PLLVDD18_SHIFT 27
-#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
-
-#define UTMI_PLL_PLLVDD12_SHIFT 25
-#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
-
-#define UTMI_PLL_CLK_BLK_EN_SHIFT 24
-#define CLK_BLK_EN (0x1 << 24)
-#define PLL_READY (0x1 << 23)
-#define KVCO_EXT (0x1 << 22)
-#define VCOCAL_START (0x1 << 21)
-
-#define UTMI_PLL_KVCO_SHIFT 15
-#define UTMI_PLL_KVCO_MASK (0x7 << 15)
-
-#define UTMI_PLL_ICP_SHIFT 12
-#define UTMI_PLL_ICP_MASK (0x7 << 12)
-
-#define UTMI_PLL_FBDIV_SHIFT 4
-#define UTMI_PLL_FBDIV_MASK (0xFF << 4)
-
-#define UTMI_PLL_REFDIV_SHIFT 0
-#define UTMI_PLL_REFDIV_MASK (0xF << 0)
-
-/* For UTMI_TX Register */
-#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
-#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
-
-#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26
-#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26)
-
-#define UTMI_TX_TXVDD12_SHIFT 22
-#define UTMI_TX_TXVDD12_MASK (0x3 << 22)
-
-#define UTMI_TX_CK60_PHSEL_SHIFT 17
-#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
-
-#define UTMI_TX_IMPCAL_VTH_SHIFT 14
-#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
-
-#define REG_RCAL_START (0x1 << 12)
-
-#define UTMI_TX_LOW_VDD_EN_SHIFT 11
-
-#define UTMI_TX_AMP_SHIFT 0
-#define UTMI_TX_AMP_MASK (0x7 << 0)
-
-/* For UTMI_RX Register */
-#define UTMI_REG_SQ_LENGTH_SHIFT 15
-#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
-
-#define UTMI_RX_SQ_THRESH_SHIFT 4
-#define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
-
-#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
-
-/* fsic registers */
-#define FSIC_MISC 0x4
-#define FSIC_INT 0x28
-#define FSIC_CTRL 0x30
-
-/* HSIC registers */
-#define HSIC_PAD_CTRL 0x4
-
-#define HSIC_CTRL 0x8
-#define HSIC_CTRL_HSIC_ENABLE (1<<7)
-#define HSIC_CTRL_PLL_BYPASS (1<<4)
-
-#define TEST_GRP_0 0xc
-#define TEST_GRP_1 0x10
-
-#define HSIC_INT 0x14
-#define HSIC_INT_READY_INT_EN (1<<10)
-#define HSIC_INT_CONNECT_INT_EN (1<<9)
-#define HSIC_INT_CORE_INT_EN (1<<8)
-#define HSIC_INT_HS_READY (1<<2)
-#define HSIC_INT_CONNECT (1<<1)
-#define HSIC_INT_CORE (1<<0)
-
-#define HSIC_CONFIG 0x18
-#define USBHSIC_CTRL 0x20
-
-#define HSIC_USB_CTRL 0x28
-#define HSIC_USB_CTRL_CLKEN 1
-#define HSIC_USB_CLK_PHY 0x0
-#define HSIC_USB_CLK_PMU 0x1
-
-#endif /* __ASM_ARCH_PXA_U2O_H */
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
deleted file mode 100644
index ecc46c31004f..000000000000
--- a/arch/arm/mach-mmp/sram.c
+++ /dev/null
@@ -1,167 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/sram.c
- *
- * based on mach-davinci/sram.c - DaVinci simple SRAM allocator
- *
- * Copyright (c) 2011 Marvell Semiconductors Inc.
- * All Rights Reserved
- *
- * Add for mmp sram support - Leo Yan <leoy@marvell.com>
- */
-
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-#include <linux/genalloc.h>
-
-#include <linux/platform_data/dma-mmp_tdma.h>
-
-struct sram_bank_info {
- char *pool_name;
- struct gen_pool *gpool;
- int granularity;
-
- phys_addr_t sram_phys;
- void __iomem *sram_virt;
- u32 sram_size;
-
- struct list_head node;
-};
-
-static DEFINE_MUTEX(sram_lock);
-static LIST_HEAD(sram_bank_list);
-
-struct gen_pool *sram_get_gpool(char *pool_name)
-{
- struct sram_bank_info *info = NULL;
-
- if (!pool_name)
- return NULL;
-
- mutex_lock(&sram_lock);
-
- list_for_each_entry(info, &sram_bank_list, node)
- if (!strcmp(pool_name, info->pool_name))
- break;
-
- mutex_unlock(&sram_lock);
-
- if (&info->node == &sram_bank_list)
- return NULL;
-
- return info->gpool;
-}
-EXPORT_SYMBOL(sram_get_gpool);
-
-static int sram_probe(struct platform_device *pdev)
-{
- struct sram_platdata *pdata = pdev->dev.platform_data;
- struct sram_bank_info *info;
- struct resource *res;
- int ret = 0;
-
- if (!pdata || !pdata->pool_name)
- return -ENODEV;
-
- info = kzalloc(sizeof(*info), GFP_KERNEL);
- if (!info)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, info);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "no memory resource defined\n");
- ret = -ENODEV;
- goto out;
- }
-
- if (!resource_size(res))
- return 0;
-
- info->sram_phys = (phys_addr_t)res->start;
- info->sram_size = resource_size(res);
- info->sram_virt = ioremap(info->sram_phys, info->sram_size);
- info->pool_name = kstrdup(pdata->pool_name, GFP_KERNEL);
- info->granularity = pdata->granularity;
-
- info->gpool = gen_pool_create(ilog2(info->granularity), -1);
- if (!info->gpool) {
- dev_err(&pdev->dev, "create pool failed\n");
- ret = -ENOMEM;
- goto create_pool_err;
- }
-
- ret = gen_pool_add_virt(info->gpool, (unsigned long)info->sram_virt,
- info->sram_phys, info->sram_size, -1);
- if (ret < 0) {
- dev_err(&pdev->dev, "add new chunk failed\n");
- ret = -ENOMEM;
- goto add_chunk_err;
- }
-
- mutex_lock(&sram_lock);
- list_add(&info->node, &sram_bank_list);
- mutex_unlock(&sram_lock);
-
- dev_info(&pdev->dev, "initialized\n");
- return 0;
-
-add_chunk_err:
- gen_pool_destroy(info->gpool);
-create_pool_err:
- iounmap(info->sram_virt);
- kfree(info->pool_name);
-out:
- kfree(info);
- return ret;
-}
-
-static int sram_remove(struct platform_device *pdev)
-{
- struct sram_bank_info *info;
-
- info = platform_get_drvdata(pdev);
-
- if (info->sram_size) {
- mutex_lock(&sram_lock);
- list_del(&info->node);
- mutex_unlock(&sram_lock);
-
- gen_pool_destroy(info->gpool);
- iounmap(info->sram_virt);
- kfree(info->pool_name);
- }
-
- kfree(info);
-
- return 0;
-}
-
-static const struct platform_device_id sram_id_table[] = {
- { "asram", MMP_ASRAM },
- { "isram", MMP_ISRAM },
- { }
-};
-
-static struct platform_driver sram_driver = {
- .probe = sram_probe,
- .remove = sram_remove,
- .driver = {
- .name = "mmp-sram",
- },
- .id_table = sram_id_table,
-};
-
-static int __init sram_init(void)
-{
- return platform_driver_register(&sram_driver);
-}
-core_initcall(sram_init);
-
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
deleted file mode 100644
index 3261d2322198..000000000000
--- a/arch/arm/mach-mmp/tavorevb.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/tavorevb.c
- *
- * Support for the Marvell PXA910-based TavorEVB Development Platform.
- */
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/smc91x.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "addr-map.h"
-#include "mfp-pxa910.h"
-#include "pxa910.h"
-#include "irqs.h"
-
-#include "common.h"
-
-static unsigned long tavorevb_pin_config[] __initdata = {
- /* UART2 */
- GPIO47_UART2_RXD,
- GPIO48_UART2_TXD,
-
- /* SMC */
- SM_nCS0_nCS0,
- SM_ADV_SM_ADV,
- SM_SCLK_SM_SCLK,
- SM_SCLK_SM_SCLK,
- SM_BE0_SM_BE0,
- SM_BE1_SM_BE1,
-
- /* DFI */
- DF_IO0_ND_IO0,
- DF_IO1_ND_IO1,
- DF_IO2_ND_IO2,
- DF_IO3_ND_IO3,
- DF_IO4_ND_IO4,
- DF_IO5_ND_IO5,
- DF_IO6_ND_IO6,
- DF_IO7_ND_IO7,
- DF_IO8_ND_IO8,
- DF_IO9_ND_IO9,
- DF_IO10_ND_IO10,
- DF_IO11_ND_IO11,
- DF_IO12_ND_IO12,
- DF_IO13_ND_IO13,
- DF_IO14_ND_IO14,
- DF_IO15_ND_IO15,
- DF_nCS0_SM_nCS2_nCS0,
- DF_ALE_SM_WEn_ND_ALE,
- DF_CLE_SM_OEn_ND_CLE,
- DF_WEn_DF_WEn,
- DF_REn_DF_REn,
- DF_RDY0_DF_RDY0,
-};
-
-static struct pxa_gpio_platform_data pxa910_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static struct smc91x_platdata tavorevb_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = SMC_CS1_PHYS_BASE + 0x300,
- .end = SMC_CS1_PHYS_BASE + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = MMP_GPIO_TO_IRQ(80),
- .end = MMP_GPIO_TO_IRQ(80),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &tavorevb_smc91x_info,
- },
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static void __init tavorevb_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(tavorevb_pin_config));
-
- /* on-chip devices */
- pxa910_add_uart(1);
- platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&pxa910_device_gpio);
-
- /* off-chip devices */
- platform_device_register(&smc91x_device);
-}
-
-MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
- .map_io = mmp_map_io,
- .nr_irqs = MMP_NR_IRQS,
- .init_irq = pxa910_init_irq,
- .init_time = pxa910_timer_init,
- .init_machine = tavorevb_init,
- .restart = mmp_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
deleted file mode 100644
index 7111535f325f..000000000000
--- a/arch/arm/mach-mmp/teton_bga.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/teton_bga.c
- *
- * Support for the Marvell PXA168 Teton BGA Development Platform.
- *
- * Author: Mark F. Brown <mark.brown314@gmail.com>
- *
- * This code is based on aspenite.c
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-#include <linux/input.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/i2c.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "addr-map.h"
-#include "mfp-pxa168.h"
-#include "pxa168.h"
-#include "teton_bga.h"
-#include "irqs.h"
-
-#include "common.h"
-
-static unsigned long teton_bga_pin_config[] __initdata = {
- /* UART1 */
- GPIO107_UART1_TXD,
- GPIO108_UART1_RXD,
-
- /* Keypad */
- GPIO109_KP_MKIN1,
- GPIO110_KP_MKIN0,
- GPIO111_KP_MKOUT7,
- GPIO112_KP_MKOUT6,
-
- /* I2C Bus */
- GPIO105_CI2C_SDA,
- GPIO106_CI2C_SCL,
-
- /* RTC */
- GPIO78_GPIO,
-};
-
-static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static unsigned int teton_bga_matrix_key_map[] = {
- KEY(0, 6, KEY_ESC),
- KEY(0, 7, KEY_ENTER),
- KEY(1, 6, KEY_LEFT),
- KEY(1, 7, KEY_RIGHT),
-};
-
-static struct matrix_keymap_data teton_bga_matrix_keymap_data = {
- .keymap = teton_bga_matrix_key_map,
- .keymap_size = ARRAY_SIZE(teton_bga_matrix_key_map),
-};
-
-static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
- .matrix_key_rows = 2,
- .matrix_key_cols = 8,
- .matrix_keymap_data = &teton_bga_matrix_keymap_data,
- .debounce_interval = 30,
-};
-
-static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
- {
- I2C_BOARD_INFO("ds1337", 0x68),
- .irq = MMP_GPIO_TO_IRQ(RTC_INT_GPIO)
- },
-};
-
-static void __init teton_bga_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
-
- /* on-chip devices */
- pxa168_add_uart(1);
- pxa168_add_keypad(&teton_bga_keypad_info);
- pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
- platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_device_register(&pxa168_device_gpio);
-}
-
-MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
- .map_io = mmp_map_io,
- .nr_irqs = MMP_NR_IRQS,
- .init_irq = pxa168_init_irq,
- .init_time = pxa168_timer_init,
- .init_machine = teton_bga_init,
- .restart = pxa168_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mmp/teton_bga.h b/arch/arm/mach-mmp/teton_bga.h
deleted file mode 100644
index 73050096f0bd..000000000000
--- a/arch/arm/mach-mmp/teton_bga.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Support for the Marvell PXA168 Teton BGA Development Platform.
- */
-#ifndef __ASM_MACH_TETON_BGA_H
-#define __ASM_MACH_TETON_BGA_H
-
-/* GPIOs */
-#define MMC_PWENA_GPIO 27
-#define USBHPENB_GPIO 55
-#define RTC_INT_GPIO 78
-#define LCD_VBLK_EN_GPIO 79
-#define LCD_DVDD_EN_GPIO 80
-#define RST_WIFI_GPIO 81
-#define CF_PWEN_GPIO 82
-#define USB_OC_GPIO 83
-#define PWM_GPIO 84
-#define USBHPENA_GPIO 85
-#define TS_INT_GPIO 86
-#define CIR_GPIO 108
-
-#endif /* __ASM_MACH_TETON_BGA_H */
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 41b2e8abc9e6..fcb190826dd1 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -29,32 +29,30 @@
#include <linux/sched_clock.h>
#include <asm/mach/time.h>
-#include "addr-map.h"
#include "regs-timers.h"
-#include "regs-apbc.h"
-#include "irqs.h"
#include <linux/soc/mmp/cputype.h>
-#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
-
#define MAX_DELTA (0xfffffffe)
#define MIN_DELTA (16)
-static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
+static void __iomem *mmp_timer_base;
/*
- * FIXME: the timer needs some delay to stablize the counter capture
+ * Read the timer through the CVWR register. Delay is required after requesting
+ * a read. The CR register cannot be directly read due to metastability issues
+ * documented in the PXA168 software manual.
*/
static inline uint32_t timer_read(void)
{
- int delay = 100;
+ uint32_t val;
+ int delay = 3;
__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
while (delay--)
- cpu_relax();
+ val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
- return __raw_readl(mmp_timer_base + TMR_CVWR(1));
+ return val;
}
static u64 notrace mmp_read_sched_clock(void)
@@ -174,7 +172,7 @@ static void __init timer_config(void)
__raw_writel(0x2, mmp_timer_base + TMR_CER);
}
-void __init mmp_timer_init(int irq, unsigned long rate)
+static void __init mmp_timer_init(int irq, unsigned long rate)
{
timer_config();
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
deleted file mode 100644
index 4f240760d4aa..000000000000
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ /dev/null
@@ -1,315 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/ttc_dkb.c
- *
- * Support for the Marvell PXA910-based TTC_DKB Development Platform.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/onenand.h>
-#include <linux/interrupt.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-#include <linux/mfd/88pm860x.h>
-#include <linux/platform_data/mv_usb.h>
-#include <linux/spi/spi.h>
-#include <linux/delay.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include "addr-map.h"
-#include "mfp-pxa910.h"
-#include "pxa910.h"
-#include "irqs.h"
-#include "regs-usb.h"
-
-#include "common.h"
-
-#define TTCDKB_GPIO_EXT0(x) (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 : \
- ((x < 16) ? x : 15)))
-#define TTCDKB_GPIO_EXT1(x) (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \
- ((x < 16) ? x : 15)))
-
-/*
- * 16 board interrupts -- MAX7312 GPIO expander
- * 16 board interrupts -- PCA9575 GPIO expander
- * 24 board interrupts -- 88PM860x PMIC
- */
-#define TTCDKB_NR_IRQS (MMP_NR_IRQS + 16 + 16 + 24)
-
-static unsigned long ttc_dkb_pin_config[] __initdata = {
- /* UART2 */
- GPIO47_UART2_RXD,
- GPIO48_UART2_TXD,
-
- /* DFI */
- DF_IO0_ND_IO0,
- DF_IO1_ND_IO1,
- DF_IO2_ND_IO2,
- DF_IO3_ND_IO3,
- DF_IO4_ND_IO4,
- DF_IO5_ND_IO5,
- DF_IO6_ND_IO6,
- DF_IO7_ND_IO7,
- DF_IO8_ND_IO8,
- DF_IO9_ND_IO9,
- DF_IO10_ND_IO10,
- DF_IO11_ND_IO11,
- DF_IO12_ND_IO12,
- DF_IO13_ND_IO13,
- DF_IO14_ND_IO14,
- DF_IO15_ND_IO15,
- DF_nCS0_SM_nCS2_nCS0,
- DF_ALE_SM_WEn_ND_ALE,
- DF_CLE_SM_OEn_ND_CLE,
- DF_WEn_DF_WEn,
- DF_REn_DF_REn,
- DF_RDY0_DF_RDY0,
-};
-
-static struct pxa_gpio_platform_data pxa910_gpio_pdata = {
- .irq_base = MMP_GPIO_TO_IRQ(0),
-};
-
-static struct mtd_partition ttc_dkb_onenand_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_1M,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_8M,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = (SZ_2M + SZ_1M),
- .mask_flags = 0,
- }, {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_32M + SZ_16M,
- .mask_flags = 0,
- }
-};
-
-static struct onenand_platform_data ttc_dkb_onenand_info = {
- .parts = ttc_dkb_onenand_partitions,
- .nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions),
-};
-
-static struct resource ttc_dkb_resource_onenand[] = {
- [0] = {
- .start = SMC_CS0_PHYS_BASE,
- .end = SMC_CS0_PHYS_BASE + SZ_1M,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device ttc_dkb_device_onenand = {
- .name = "onenand-flash",
- .id = -1,
- .resource = ttc_dkb_resource_onenand,
- .num_resources = ARRAY_SIZE(ttc_dkb_resource_onenand),
- .dev = {
- .platform_data = &ttc_dkb_onenand_info,
- },
-};
-
-static struct platform_device *ttc_dkb_devices[] = {
- &pxa910_device_gpio,
- &pxa910_device_rtc,
- &ttc_dkb_device_onenand,
-};
-
-static struct pca953x_platform_data max7312_data[] = {
- {
- .gpio_base = TTCDKB_GPIO_EXT0(0),
- .irq_base = MMP_NR_IRQS,
- },
-};
-
-static struct pm860x_platform_data ttc_dkb_pm8607_info = {
- .irq_base = IRQ_BOARD_START,
-};
-
-static struct i2c_board_info ttc_dkb_i2c_info[] = {
- {
- .type = "88PM860x",
- .addr = 0x34,
- .platform_data = &ttc_dkb_pm8607_info,
- .irq = IRQ_PXA910_PMIC_INT,
- },
- {
- .type = "max7312",
- .addr = 0x23,
- .irq = MMP_GPIO_TO_IRQ(80),
- .platform_data = &max7312_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_USB_SUPPORT)
-#if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
-
-static struct mv_usb_platform_data ttc_usb_pdata = {
- .vbus = NULL,
- .mode = MV_USB_MODE_OTG,
- .otg_force_a_bus_req = 1,
- .phy_init = pxa_usb_phy_init,
- .phy_deinit = pxa_usb_phy_deinit,
- .set_vbus = NULL,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
-static struct pxa3xx_nand_platform_data dkb_nand_info = {};
-#endif
-
-#if IS_ENABLED(CONFIG_MMP_DISP)
-/* path config */
-#define CFG_IOPADMODE(iopad) (iopad) /* 0x0 ~ 0xd */
-#define SCLK_SOURCE_SELECT(x) (x << 30) /* 0x0 ~ 0x3 */
-/* link config */
-#define CFG_DUMBMODE(mode) (mode << 28) /* 0x0 ~ 0x6*/
-static struct mmp_mach_path_config dkb_disp_config[] = {
- [0] = {
- .name = "mmp-parallel",
- .overlay_num = 2,
- .output_type = PATH_OUT_PARALLEL,
- .path_config = CFG_IOPADMODE(0x1)
- | SCLK_SOURCE_SELECT(0x1),
- .link_config = CFG_DUMBMODE(0x2),
- },
-};
-
-static struct mmp_mach_plat_info dkb_disp_info = {
- .name = "mmp-disp",
- .clk_name = "disp0",
- .path_num = 1,
- .paths = dkb_disp_config,
-};
-
-static struct mmp_buffer_driver_mach_info dkb_fb_info = {
- .name = "mmp-fb",
- .path_name = "mmp-parallel",
- .overlay_id = 0,
- .dmafetch_id = 1,
- .default_pixfmt = PIXFMT_RGB565,
-};
-
-static void dkb_tpo_panel_power(int on)
-{
- int err;
- u32 spi_reset = mfp_to_gpio(MFP_PIN_GPIO106);
-
- if (on) {
- err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET");
- if (err) {
- pr_err("failed to request GPIO for TPO LCD RESET\n");
- return;
- }
- gpio_direction_output(spi_reset, 0);
- udelay(100);
- gpio_set_value(spi_reset, 1);
- gpio_free(spi_reset);
- } else {
- err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET");
- if (err) {
- pr_err("failed to request LCD RESET gpio\n");
- return;
- }
- gpio_set_value(spi_reset, 0);
- gpio_free(spi_reset);
- }
-}
-
-static struct mmp_mach_panel_info dkb_tpo_panel_info = {
- .name = "tpo-hvga",
- .plat_path_name = "mmp-parallel",
- .plat_set_onoff = dkb_tpo_panel_power,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
- {
- .modalias = "tpo-hvga",
- .platform_data = &dkb_tpo_panel_info,
- .bus_num = 5,
- }
-};
-
-static void __init add_disp(void)
-{
- pxa_register_device(&pxa910_device_disp,
- &dkb_disp_info, sizeof(dkb_disp_info));
- spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
- pxa_register_device(&pxa910_device_fb,
- &dkb_fb_info, sizeof(dkb_fb_info));
- pxa_register_device(&pxa910_device_panel,
- &dkb_tpo_panel_info, sizeof(dkb_tpo_panel_info));
-}
-#endif
-
-static void __init ttc_dkb_init(void)
-{
- mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
-
- /* on-chip devices */
- pxa910_add_uart(1);
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
- pxa910_add_nand(&dkb_nand_info);
-#endif
-
- /* off-chip devices */
- pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
- platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata,
- sizeof(struct pxa_gpio_platform_data));
- platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
-
-#if IS_ENABLED(CONFIG_USB_SUPPORT)
-#if IS_ENABLED(CONFIG_PHY_PXA_USB)
- platform_device_register(&pxa168_device_usb_phy);
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MV_UDC)
- pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
- platform_device_register(&pxa168_device_u2o);
-#endif
-
-#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
- pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata;
- platform_device_register(&pxa168_device_u2oehci);
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MV_OTG)
- pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
- platform_device_register(&pxa168_device_u2ootg);
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MMP_DISP)
- add_disp();
-#endif
-}
-
-MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
- .map_io = mmp_map_io,
- .nr_irqs = TTCDKB_NR_IRQS,
- .init_irq = pxa910_init_irq,
- .init_time = pxa910_timer_init,
- .init_machine = ttc_dkb_init,
- .restart = mmp_restart,
-MACHINE_END
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
index 31ada63ba51b..909c6573ba8b 100644
--- a/arch/arm/mach-moxart/Kconfig
+++ b/arch/arm/mach-moxart/Kconfig
@@ -2,6 +2,7 @@
menuconfig ARCH_MOXART
bool "MOXA ART SoC"
depends on ARCH_MULTI_V4
+ depends on CPU_LITTLE_ENDIAN
select CPU_FA526
select ARM_DMA_MEM_BUFFERABLE
select FARADAY_FTINTC010
diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig
index 5dbea7b485af..fa9709f30b46 100644
--- a/arch/arm/mach-mstar/Kconfig
+++ b/arch/arm/mach-mstar/Kconfig
@@ -20,11 +20,4 @@ config MACH_INFINITY
help
Support for MStar/Sigmastar infinity IP camera SoCs.
-config MACH_MERCURY
- bool "MStar/Sigmastar mercury SoC support"
- default ARCH_MSTARV7
- help
- Support for MStar/Sigmastar mercury dash camera SoCs.
- Note that older Mercury2 SoCs are ARM9 based and not supported.
-
endif
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
index ea52c7fabb79..9de3bbc09c3a 100644
--- a/arch/arm/mach-mv78xx0/Kconfig
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -2,6 +2,8 @@
menuconfig ARCH_MV78XX0
bool "Marvell MV78xx0"
depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
+ depends on ATAGS
select CPU_FEROCEON
select GPIOLIB
select MVEBU_MBUS
@@ -13,18 +15,6 @@ menuconfig ARCH_MV78XX0
if ARCH_MV78XX0
-config MACH_DB78X00_BP
- bool "Marvell DB-78x00-BP Development Board"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell DB-78x00-BP Development Board.
-
-config MACH_RD78X00_MASA
- bool "Marvell RD-78x00-mASA Reference Design"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell RD-78x00-mASA Reference Design.
-
config MACH_TERASTATION_WXL
bool "Buffalo WLX (Terastation Duo) NAS"
help
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
index a839e960b8c6..ddee6ae501bb 100644
--- a/arch/arm/mach-mv78xx0/Makefile
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -1,7 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include
+ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
obj-y += common.o mpp.o irq.o pcie.o
-obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o
-obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o
obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o
diff --git a/arch/arm/mach-mv78xx0/bridge-regs.h b/arch/arm/mach-mv78xx0/bridge-regs.h
index 2f54e1753d45..d57ac967c4b3 100644
--- a/arch/arm/mach-mv78xx0/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/bridge-regs.h
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index e112f2e7cc9a..62e982f74bc2 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
*
* Buffalo WXL (Terastation Duo) Setup routines
*
* sebastien requiem <sebastien@requiem.fr>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
@@ -17,6 +14,9 @@
#include <linux/mv643xx_eth.h>
#include <linux/ethtool.h>
#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "mv78xx0.h"
@@ -24,6 +24,11 @@
#include "mpp.h"
+#define TSWXL_AUTO_SWITCH 15
+#define TSWXL_USB_POWER1 30
+#define TSWXL_USB_POWER2 31
+
+
/* This arch has 2 Giga Ethernet */
static struct mv643xx_eth_platform_data db78x00_ge00_data = {
@@ -42,7 +47,7 @@ static struct mv_sata_platform_data db78x00_sata_data = {
};
static struct i2c_board_info __initdata db78x00_i2c_rtc = {
- I2C_BOARD_INFO("ds1338", 0x68),
+ I2C_BOARD_INFO("rs5c372a", 0x32),
};
@@ -60,9 +65,9 @@ static unsigned int wxl_mpp_config[] __initdata = {
MPP10_GE1_RXD2,
MPP11_GE1_RXD3,
MPP12_GPIO,
- MPP13_SYSRST_OUTn,
- MPP14_SATA1_ACTn,
- MPP15_SATA0_ACTn,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
MPP16_GPIO,
MPP17_GPIO,
MPP18_GPIO,
@@ -76,7 +81,7 @@ static unsigned int wxl_mpp_config[] __initdata = {
MPP26_UA2_CTSn,
MPP27_UA2_RTSn,
MPP28_GPIO,
- MPP29_SYSRST_OUTn,
+ MPP29_GPIO,
MPP30_GPIO,
MPP31_GPIO,
MPP32_GPIO,
@@ -87,19 +92,41 @@ static unsigned int wxl_mpp_config[] __initdata = {
MPP37_GPIO,
MPP38_GPIO,
MPP39_GPIO,
- MPP40_UNUSED,
- MPP41_UNUSED,
- MPP42_UNUSED,
- MPP43_UNUSED,
- MPP44_UNUSED,
- MPP45_UNUSED,
- MPP46_UNUSED,
- MPP47_UNUSED,
- MPP48_SATA1_ACTn,
- MPP49_SATA0_ACTn,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
0
};
+static struct gpio_keys_button tswxl_buttons[] = {
+ {
+ .code = KEY_OPTION,
+ .gpio = TSWXL_AUTO_SWITCH,
+ .desc = "Power-auto Switch",
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_platform_data tswxl_button_data = {
+ .buttons = tswxl_buttons,
+ .nbuttons = ARRAY_SIZE(tswxl_buttons),
+};
+
+static struct platform_device tswxl_button_device = {
+ .name = "gpio-keys",
+ .id = -1,
+ .num_resources = 0,
+ .dev = {
+ .platform_data = &tswxl_button_data,
+ },
+};
static void __init wxl_init(void)
{
@@ -114,7 +141,6 @@ static void __init wxl_init(void)
*/
mv78xx0_ehci0_init();
mv78xx0_ehci1_init();
- mv78xx0_ehci2_init();
mv78xx0_ge00_init(&db78x00_ge00_data);
mv78xx0_ge01_init(&db78x00_ge01_data);
mv78xx0_sata_init(&db78x00_sata_data);
@@ -122,22 +148,23 @@ static void __init wxl_init(void)
mv78xx0_uart1_init();
mv78xx0_uart2_init();
mv78xx0_uart3_init();
+ mv78xx0_xor_init();
+ mv78xx0_crypto_init();
mv78xx0_i2c_init();
i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
+
+ //enable both usb ports
+ gpio_direction_output(TSWXL_USB_POWER1, 1);
+ gpio_direction_output(TSWXL_USB_POWER2, 1);
+
+ //enable rear switch
+ platform_device_register(&tswxl_button_device);
}
static int __init wxl_pci_init(void)
{
- if (machine_is_terastation_wxl()) {
- /*
- * Assign the x16 PCIe slot on the board to CPU core
- * #0, and let CPU core #1 have the four x1 slots.
- */
- if (mv78xx0_core_index() == 0)
- mv78xx0_pcie_init(0, 1);
- else
- mv78xx0_pcie_init(1, 0);
- }
+ if (machine_is_terastation_wxl() && mv78xx0_core_index() == 0)
+ mv78xx0_pcie_init(1, 1);
return 0;
}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index dd762d1b083f..679753fcc0ef 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-mv78xx0/common.c
*
* Core functions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
@@ -345,6 +342,29 @@ void __ref mv78xx0_timer_init(void)
IRQ_MV78XX0_TIMER_1, get_tclk());
}
+/****************************************************************************
+* XOR engine
+****************************************************************************/
+void __init mv78xx0_xor_init(void)
+{
+ orion_xor0_init(XOR_PHYS_BASE,
+ XOR_PHYS_BASE + 0x200,
+ IRQ_MV78XX0_XOR_0, IRQ_MV78XX0_XOR_1);
+}
+
+/****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+****************************************************************************/
+void __init mv78xx0_crypto_init(void)
+{
+ mvebu_mbus_add_window_by_id(MV78XX0_MBUS_SRAM_TARGET,
+ MV78XX0_MBUS_SRAM_ATTR,
+ MV78XX0_SRAM_PHYS_BASE,
+ MV78XX0_SRAM_SIZE);
+ orion_crypto_init(CRYPTO_PHYS_BASE, MV78XX0_SRAM_PHYS_BASE,
+ SZ_8K, IRQ_MV78XX0_CRYPTO);
+}
+
/*****************************************************************************
* General
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 6889af26077d..9f1dfd595003 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-mv78xx0/common.h
*
* Core functions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __ARCH_MV78XX0_COMMON_H
@@ -46,6 +43,8 @@ void mv78xx0_uart0_init(void);
void mv78xx0_uart1_init(void);
void mv78xx0_uart2_init(void);
void mv78xx0_uart3_init(void);
+void mv78xx0_xor_init(void);
+void mv78xx0_crypto_init(void);
void mv78xx0_i2c_init(void);
void mv78xx0_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
deleted file mode 100644
index cf16e08d4cf5..000000000000
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
- *
- * Marvell DB-78x00-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/i2c.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "mv78xx0.h"
-#include "common.h"
-
-static struct mv643xx_eth_platform_data db78x00_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv643xx_eth_platform_data db78x00_ge01_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(9),
-};
-
-static struct mv643xx_eth_platform_data db78x00_ge10_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(10),
-};
-
-static struct mv643xx_eth_platform_data db78x00_ge11_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(11),
-};
-
-static struct mv_sata_platform_data db78x00_sata_data = {
- .n_ports = 2,
-};
-
-static struct i2c_board_info __initdata db78x00_i2c_rtc = {
- I2C_BOARD_INFO("ds1338", 0x68),
-};
-
-
-static void __init db78x00_init(void)
-{
- /*
- * Basic MV78xx0 setup. Needs to be called early.
- */
- mv78xx0_init();
-
- /*
- * Partition on-chip peripherals between the two CPU cores.
- */
- if (mv78xx0_core_index() == 0) {
- mv78xx0_ehci0_init();
- mv78xx0_ehci1_init();
- mv78xx0_ehci2_init();
- mv78xx0_ge00_init(&db78x00_ge00_data);
- mv78xx0_ge01_init(&db78x00_ge01_data);
- mv78xx0_ge10_init(&db78x00_ge10_data);
- mv78xx0_ge11_init(&db78x00_ge11_data);
- mv78xx0_sata_init(&db78x00_sata_data);
- mv78xx0_uart0_init();
- mv78xx0_uart2_init();
- mv78xx0_i2c_init();
- i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
- } else {
- mv78xx0_uart1_init();
- mv78xx0_uart3_init();
- }
-}
-
-static int __init db78x00_pci_init(void)
-{
- if (machine_is_db78x00_bp()) {
- /*
- * Assign the x16 PCIe slot on the board to CPU core
- * #0, and let CPU core #1 have the four x1 slots.
- */
- if (mv78xx0_core_index() == 0)
- mv78xx0_pcie_init(0, 1);
- else
- mv78xx0_pcie_init(1, 0);
- }
-
- return 0;
-}
-subsys_initcall(db78x00_pci_init);
-
-MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
- /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = MV78XX0_NR_IRQS,
- .init_machine = db78x00_init,
- .map_io = mv78xx0_map_io,
- .init_early = mv78xx0_init_early,
- .init_irq = mv78xx0_init_irq,
- .init_time = mv78xx0_timer_init,
- .restart = mv78xx0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 0b5f055ca1c3..a34b6855fb19 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-mv78xx0/irq.c
*
* MV78xx0 IRQ handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/irqs.h b/arch/arm/mach-mv78xx0/irqs.h
index 67e0fe730a13..12b357d383d8 100644
--- a/arch/arm/mach-mv78xx0/irqs.h
+++ b/arch/arm/mach-mv78xx0/irqs.h
@@ -1,10 +1,5 @@
-/*
- * IRQ definitions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* IRQ definitions for Marvell MV78xx0 SoCs */
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 72843c02e95a..aff0e612cbba 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-mv78x00/mpp.c
*
* MPP functions for Marvell MV78x00 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index 3752302ae2ee..47db52f45546 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins
*
- *
* sebastien requiem <sebastien@requiem.fr>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __MV78X00_MPP_H
diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h
index c1a9a1d1b295..88efb1e44142 100644
--- a/arch/arm/mach-mv78xx0/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/mv78xx0.h
@@ -1,10 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Generic definitions for Marvell MV78xx0 SoC flavors:
* MV781x0 and MV782x0.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_MV78XX0_H
@@ -52,9 +49,15 @@
#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
#define MV78XX0_REGS_SIZE SZ_1M
+#define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
+#define MV78XX0_SRAM_SIZE SZ_8K
+
#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
#define MV78XX0_PCIE_MEM_SIZE 0x30000000
+#define MV78XX0_MBUS_SRAM_TARGET 0x09
+#define MV78XX0_MBUS_SRAM_ATTR 0x00
+
/*
* Core-specific peripheral registers.
*/
@@ -101,6 +104,8 @@
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
+#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
+
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
@@ -109,6 +114,8 @@
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
+#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
+
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
/*
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index e15646af7f26..533cb7856943 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-mv78xx0/pcie.c
*
* PCIe functions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
@@ -45,7 +42,7 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
u32 pcie_port_size[8] = {
0,
- 0x30000000,
+ 0x20000000,
0x10000000,
0x10000000,
0x08000000,
@@ -180,18 +177,23 @@ static struct pci_ops pcie_ops = {
.write = pcie_wr_conf,
};
+/*
+ * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
+ * is operating as a root complex this needs to be switched to
+ * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
+ * the device. Decoding setup is handled by the orion code.
+ */
static void rc_pci_fixup(struct pci_dev *dev)
{
- /*
- * Prevent enumeration of root complex.
- */
if (dev->bus->parent == NULL && dev->devfn == 0) {
- int i;
-
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
+ struct resource *r;
+
+ dev->class &= 0xff;
+ dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
+ pci_dev_for_each_resource(dev, r) {
+ r->start = 0;
+ r->end = 0;
+ r->flags = 0;
}
}
}
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
deleted file mode 100644
index 308ab71ec822..000000000000
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * arch/arm/mach-mv78x00/rd78x00-masa-setup.c
- *
- * Marvell RD-78x00-mASA Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "mv78xx0.h"
-#include "common.h"
-
-static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(9),
-};
-
-static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = {
-};
-
-static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = {
-};
-
-static struct mv_sata_platform_data rd78x00_masa_sata_data = {
- .n_ports = 2,
-};
-
-static void __init rd78x00_masa_init(void)
-{
- /*
- * Basic MV78x00 setup. Needs to be called early.
- */
- mv78xx0_init();
-
- /*
- * Partition on-chip peripherals between the two CPU cores.
- */
- if (mv78xx0_core_index() == 0) {
- mv78xx0_ehci0_init();
- mv78xx0_ehci1_init();
- mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
- mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
- mv78xx0_sata_init(&rd78x00_masa_sata_data);
- mv78xx0_uart0_init();
- mv78xx0_uart2_init();
- } else {
- mv78xx0_ehci2_init();
- mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
- mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
- mv78xx0_uart1_init();
- mv78xx0_uart3_init();
- }
-}
-
-static int __init rd78x00_pci_init(void)
-{
- /*
- * Assign all PCIe devices to CPU core #0.
- */
- if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0)
- mv78xx0_pcie_init(1, 1);
-
- return 0;
-}
-subsys_initcall(rd78x00_pci_init);
-
-MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
- /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = MV78XX0_NR_IRQS,
- .init_machine = rd78x00_masa_init,
- .map_io = mv78xx0_map_io,
- .init_early = mv78xx0_init_early,
- .init_irq = mv78xx0_init_irq,
- .init_time = mv78xx0_timer_init,
- .restart = mv78xx0_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 34dbeaab94b0..9f60a6fe0eaf 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,8 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MVEBU
bool "Marvell Engineering Business Unit (MVEBU) SoCs"
- depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
- select ARCH_SUPPORTS_BIG_ENDIAN
+ depends on ARCH_MULTI_V7 || (ARCH_MULTI_V5 && CPU_LITTLE_ENDIAN)
select CLKSRC_MMIO
select PINCTRL
select PLAT_ORION
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index cb106899dd7c..569768a69ffc 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,8 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include
-
-AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
-CFLAGS_pmsu.o := -march=armv7-a
+ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 09413b678409..c96ecdafe31f 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Generic definitions for Marvell Armada_370_XP SoCs
*
@@ -6,10 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __MACH_ARMADA_370_XP_H
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index d2df5ef9382b..fd5d0c8ff695 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree support for Armada 370 and XP platforms.
*
@@ -6,10 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 49e3c8d20c2f..a6b621ff0b87 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
* platforms.
@@ -8,10 +9,6 @@
* Gregory Clement <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
* responsible for ensuring hardware coherency between all CPUs and between
* CPUs and I/O masters. This file initializes the coherency fabric and
@@ -98,7 +95,7 @@ static int mvebu_hwcc_notifier(struct notifier_block *nb,
if (event != BUS_NOTIFY_ADD_DEVICE)
return NOTIFY_DONE;
- set_dma_ops(dev, &arm_coherent_dma_ops);
+ dev->dma_coherent = true;
return NOTIFY_OK;
}
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 6067f14263f7..cae866ab4867 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-mvebu/include/mach/coherency.h
*
- *
* Coherency fabric (Aurora) support for Armada 370 and XP platforms.
*
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __MACH_370_XP_COHERENCY_H
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index a3a64bf97250..35930e03d9c6 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Coherency fabric: low level functions
*
@@ -5,10 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file implements the assembly function to add a CPU to the
* coherency fabric. This function is called by each of the secondary
* CPUs during their early boot in an SMP kernel, this why this
@@ -23,6 +20,7 @@
#include <asm/assembler.h>
#include <asm/cp15.h>
+ .arch armv7-a
.text
/*
* Returns the coherency base address in r1 (r0 is untouched), or 0 if
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 6b775492cfad..fbfa3c4f30df 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Core functions for Marvell System On Chip
*
@@ -6,10 +7,6 @@
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __ARCH_MVEBU_COMMON_H
diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c
index f33a31c6aff8..66b6c0c6ce1d 100644
--- a/arch/arm/mach-mvebu/cpu-reset.c
+++ b/arch/arm/mach-mvebu/cpu-reset.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#define pr_fmt(fmt) "mvebu-cpureset: " fmt
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index d076c5771adc..c938ba725d3e 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-mvebu/dove.c
*
* Marvell Dove 88AP510 System On Chip FDT Board
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index b093a196e801..df723cf85cae 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SMP support: Entry point for secondary CPUs of Marvell EBU
* Cortex-A9 based SOCs (Armada 375 and Armada 38x).
@@ -6,10 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/linkage.h>
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index 2c4032e368ba..f05c59dad32a 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SMP support: Entry point for secondary CPUs
*
@@ -7,10 +8,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* This file implements the assembly entry point for secondary CPUs in
* an SMP kernel. The only thing we need to do is to add the CPU to
* the coherency fabric by writing to 2 registers. Currently the base
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 06b1706595f4..8ff34753e760 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
*
* arch/arm/mach-mvebu/kirkwood.c
*
* Flattened Device Tree board initialization
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
diff --git a/arch/arm/mach-mvebu/kirkwood.h b/arch/arm/mach-mvebu/kirkwood.h
index 89f3d1f51643..15135994ce2f 100644
--- a/arch/arm/mach-mvebu/kirkwood.h
+++ b/arch/arm/mach-mvebu/kirkwood.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-mvebu/kirkwood.h
*
* Generic definitions for Marvell Kirkwood SoC flavors:
* 88F6180, 88F6192 and 88F6281.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index a99434bcee84..f436c7b8c7ae 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* ID and revision information for mvebu SoCs
*
@@ -5,10 +6,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* All the mvebu SoCs have information related to their variant and
* revision that can be read from the PCI control register. This is
* done before the PCI initialization to avoid any conflict. Once the
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.h b/arch/arm/mach-mvebu/mvebu-soc-id.h
index e124a0b82a3e..225649b2288a 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.h
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Marvell EBU SoC ID and revision definitions.
*
* Copyright (C) 2014 Marvell Semiconductor
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __LINUX_MVEBU_SOC_ID_H
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index d715dec1c197..785ee2af5baa 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Symmetric Multi Processing (SMP) support for Marvell EBU Cortex-A9
* based SOCs (Armada 375/38x).
@@ -6,10 +7,6 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index c130497dc6cc..18384ea6862c 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Symmetric Multi Processing (SMP) support for Armada XP
*
@@ -8,10 +9,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
* This file implements the routines for preparing the SMP infrastructure
* and waking up the secondary CPUs
diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
index 070552511699..beec22e17e89 100644
--- a/arch/arm/mach-mvebu/pm-board.c
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -1,29 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Board-level suspend/resume support.
*
* Copyright (C) 2014-2015 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/delay.h>
-#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_gpio.h>
#include <linux/slab.h>
#include "common.h"
#define ARMADA_PIC_NR_GPIOS 3
static void __iomem *gpio_ctrl;
-static int pic_gpios[ARMADA_PIC_NR_GPIOS];
+static struct gpio_desc *pic_gpios[ARMADA_PIC_NR_GPIOS];
static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
@@ -93,27 +90,17 @@ static int __init mvebu_armada_pm_init(void)
char *name;
struct of_phandle_args args;
- pic_gpios[i] = of_get_named_gpio(np, "ctrl-gpios", i);
- if (pic_gpios[i] < 0) {
- ret = -ENODEV;
- goto out;
- }
-
name = kasprintf(GFP_KERNEL, "pic-pin%d", i);
if (!name) {
ret = -ENOMEM;
goto out;
}
- ret = gpio_request(pic_gpios[i], name);
- if (ret < 0) {
- kfree(name);
- goto out;
- }
-
- ret = gpio_direction_output(pic_gpios[i], 0);
- if (ret < 0) {
- gpio_free(pic_gpios[i]);
+ pic_gpios[i] = fwnode_gpiod_get_index(of_fwnode_handle(np),
+ "ctrl", i, GPIOD_OUT_HIGH,
+ name);
+ ret = PTR_ERR_OR_ZERO(pic_gpios[i]);
+ if (ret) {
kfree(name);
goto out;
}
@@ -121,7 +108,7 @@ static int __init mvebu_armada_pm_init(void)
ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2,
i, &args);
if (ret < 0) {
- gpio_free(pic_gpios[i]);
+ gpiod_put(pic_gpios[i]);
kfree(name);
goto out;
}
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index c487be61d6d8..b149d9b77505 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Suspend/resume support. Currently supporting Armada XP only.
*
* Copyright (C) 2014 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/cpu_pm.h>
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 73d5d72dfc3e..6f366d8c4231 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
*
@@ -7,10 +8,6 @@
* Gregory Clement <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* The Armada 370 and Armada XP SOCs have a power management service
* unit which is responsible for powering down and waking up CPUs and
* other SOC units
@@ -294,6 +291,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
/* Test the CR_C bit and set it if it was cleared */
asm volatile(
+ ".arch armv7-a\n\t"
"mrc p15, 0, r0, c1, c0, 0 \n\t"
"tst r0, %0 \n\t"
"orreq r0, r0, #(1 << 2) \n\t"
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
index ea79269c2702..1e847388e8dd 100644
--- a/arch/arm/mach-mvebu/pmsu.h
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Power Management Service Unit (PMSU) support for Armada 370/XP platforms.
*
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __MACH_MVEBU_PMSU_H
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 7aae9a25cfeb..f7d21385fd88 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Gregory Clement <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/linkage.h>
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 04d9ebe6a90a..48224b6ed6dc 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* System controller support for Armada 370, 375 and XP platforms.
*
@@ -7,10 +8,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
* The Armada 370, 375 and Armada XP SoCs have a range of
* miscellaneous registers, that do not belong to a particular device,
* but rather provide system-level features. This basic
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index be1c1388055a..26dd8b9b7321 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -16,6 +16,7 @@ config SOC_IMX28
config ARCH_MXS
bool "Freescale MXS (i.MX23, i.MX28) support"
depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
select GPIOLIB
select MXS_TIMER
select PINCTRL
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 25c9d184fa4c..51e47053c816 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -17,7 +17,6 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
-#include <linux/pinctrl/consumer.h>
#include <linux/sys_soc.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -175,7 +174,7 @@ static void __init update_fec_mac_prop(enum mac_oui oui)
from = np;
- if (of_get_property(np, "local-mac-address", NULL))
+ if (of_property_present(np, "local-mac-address"))
continue;
newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
@@ -393,8 +392,10 @@ static void __init mxs_machine_init(void)
root = of_find_node_by_path("/");
ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
- if (ret)
+ if (ret) {
+ kfree(soc_dev_attr);
return;
+ }
soc_dev_attr->family = "Freescale MXS Family";
soc_dev_attr->soc_id = mxs_get_soc_id();
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index e98429be2b18..f5c4df6d2aad 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -2,10 +2,10 @@
menuconfig ARCH_NOMADIK
bool "ST-Ericsson Nomadik"
depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
select ARM_AMBA
select ARM_VIC
select CLKSRC_NOMADIK_MTU
- select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
select CPU_ARM926T
select GPIOLIB
select MFD_SYSCON
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
index a71cf1d189ae..63b42a19d1b8 100644
--- a/arch/arm/mach-npcm/Kconfig
+++ b/arch/arm/mach-npcm/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_NPCM
bool "Nuvoton NPCM Architecture"
- depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
+ depends on (ARCH_MULTI_V5 && CPU_LITTLE_ENDIAN) || ARCH_MULTI_V7
select PINCTRL
if ARCH_NPCM
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
index 8d61fcd42fb1..ac83e1caf2ee 100644
--- a/arch/arm/mach-npcm/Makefile
+++ b/arch/arm/mach-npcm/Makefile
@@ -1,6 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
-AFLAGS_headsmp.o += -march=armv7-a
-
obj-$(CONFIG_ARCH_WPCM450) += wpcm450.o
obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
index c083fe09a07b..84d2b6daaf0b 100644
--- a/arch/arm/mach-npcm/headsmp.S
+++ b/arch/arm/mach-npcm/headsmp.S
@@ -6,6 +6,8 @@
#include <linux/init.h>
#include <asm/assembler.h>
+.arch armv7-a
+
/*
* The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
* here.
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
index 6ef1b167619b..b7a3871876d7 100644
--- a/arch/arm/mach-nspire/Kconfig
+++ b/arch/arm/mach-nspire/Kconfig
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_NSPIRE
bool "TI-NSPIRE based"
- depends on ARCH_MULTI_V4_V5
+ depends on ARCH_MULTI_V4T
+ depends on CPU_LITTLE_ENDIAN
select CPU_ARM926T
select GENERIC_IRQ_CHIP
select ARM_AMBA
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 93ea86954a84..cbf703f0d850 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -1,28 +1,33 @@
# SPDX-License-Identifier: GPL-2.0-only
+menuconfig ARCH_OMAP1
+ bool "TI OMAP1"
+ depends on ARCH_MULTI_V4T || ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
+ depends on ATAGS
+ select ARCH_OMAP
+ select ARCH_HAS_HOLES_MEMORYMODEL
+ select ARCH_OMAP
+ select CLKSRC_MMIO
+ select FORCE_PCI if PCCARD
+ select GPIOLIB
+ help
+ Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
+
if ARCH_OMAP1
menu "TI OMAP1 specific features"
comment "OMAP Core Type"
-config ARCH_OMAP730
- bool "OMAP730 Based System"
- select ARCH_OMAP_OTG
- select CPU_ARM926T
- select OMAP_MPU_TIMER
-
-config ARCH_OMAP850
- bool "OMAP850 Based System"
- select ARCH_OMAP_OTG
- select CPU_ARM926T
-
config ARCH_OMAP15XX
+ depends on ARCH_MULTI_V4T
default y
bool "OMAP15xx Based System"
select CPU_ARM925T
select OMAP_MPU_TIMER
config ARCH_OMAP16XX
+ depends on ARCH_MULTI_V5
bool "OMAP16xx Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
@@ -108,61 +113,12 @@ config ARCH_OMAP_OTG
comment "OMAP Board Type"
-config MACH_OMAP_INNOVATOR
- bool "TI Innovator"
- depends on ARCH_OMAP15XX || ARCH_OMAP16XX
- help
- TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
- have such a board.
-
-config MACH_OMAP_H2
- bool "TI H2 Support"
- depends on ARCH_OMAP16XX
- help
- TI OMAP 1610/1611B H2 board support. Say Y here if you have such
- a board.
-
-config MACH_OMAP_H3
- bool "TI H3 Support"
- depends on ARCH_OMAP16XX
- help
- TI OMAP 1710 H3 board support. Say Y here if you have such
- a board.
-
-config MACH_HERALD
- bool "HTC Herald"
- depends on ARCH_OMAP850
- help
- HTC Herald smartphone support (AKA T-Mobile Wing, ...)
-
config MACH_OMAP_OSK
bool "TI OSK Support"
depends on ARCH_OMAP16XX
help
TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
- if you have such a board.
-
-config OMAP_OSK_MISTRAL
- bool "Mistral QVGA board Support"
- depends on MACH_OMAP_OSK
- help
- The OSK supports an optional add-on board with a Quarter-VGA
- touchscreen, PDA-ish buttons, a resume button, bicolor LED,
- and camera connector. Say Y here if you have this board.
-
-config MACH_OMAP_PERSEUS2
- bool "TI Perseus2"
- depends on ARCH_OMAP730
- help
- Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
- a board.
-
-config MACH_OMAP_FSAMPLE
- bool "TI F-Sample"
- depends on ARCH_OMAP730
- help
- Support for TI OMAP 850 F-Sample board. Say Y here if you have such
- a board.
+ if you have such a board.
config MACH_OMAP_PALMTE
bool "Palm Tungsten E"
@@ -173,24 +129,6 @@ config MACH_OMAP_PALMTE
http://palmtelinux.sourceforge.net/ for more information.
Say Y here if you have this PDA model, say N otherwise.
-config MACH_OMAP_PALMZ71
- bool "Palm Zire71"
- depends on ARCH_OMAP15XX
- help
- Support for the Palm Zire71 PDA. To boot the kernel,
- you'll need a PalmOS compatible bootloader; check out
- http://hackndev.com/palm/z71 for more information.
- Say Y here if you have such a PDA, say N otherwise.
-
-config MACH_OMAP_PALMTT
- bool "Palm Tungsten|T"
- depends on ARCH_OMAP15XX
- help
- Support for the Palm Tungsten|T PDA. To boot the kernel, you'll
- need a PalmOS compatible bootloader (Garux); check out
- http://garux.sourceforge.net/ for more information.
- Say Y here if you have this PDA model, say N otherwise.
-
config MACH_SX1
bool "Siemens SX1"
depends on ARCH_OMAP15XX
@@ -222,15 +160,6 @@ config MACH_AMS_DELTA
Support for the Amstrad E3 (codename Delta) videophone. Say Y here
if you have such a device.
-config MACH_OMAP_GENERIC
- bool "Generic OMAP board"
- depends on ARCH_OMAP15XX || ARCH_OMAP16XX
- help
- Support for generic OMAP-1510, 1610 or 1710 board with
- no FPGA. Can be used as template for porting Linux to
- custom OMAP boards. Say Y here if you have a custom
- board.
-
endmenu
endif
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 0615cb0ba580..d9e251ea4773 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -29,31 +29,13 @@ usb-fs-$(CONFIG_USB_SUPPORT) := usb.o
obj-y += $(usb-fs-m) $(usb-fs-y)
# Specific board support
-obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o \
- board-nand.o
-obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o
-obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
-obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o board-nand.o
-obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o
obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
-obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \
- board-nand.o
obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
-obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
-obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o
obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \
ams-delta-fiq-handler.o
obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o
-obj-$(CONFIG_MACH_HERALD) += board-htcherald.o
-
-ifeq ($(CONFIG_ARCH_OMAP15XX),y)
-# Innovator-1510 FPGA
-obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o
-endif
# GPIO
-obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o
-obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o
obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o
obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o
diff --git a/arch/arm/mach-omap1/Makefile.boot b/arch/arm/mach-omap1/Makefile.boot
deleted file mode 100644
index 2c771515a606..000000000000
--- a/arch/arm/mach-omap1/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
- zreladdr-y += 0x10008000
-params_phys-y := 0x10000100
-initrd_phys-y := 0x10800000
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index f745a65d3bd7..35c2f9574dbd 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -13,14 +13,15 @@
#include <linux/linkage.h>
#include <linux/platform_data/ams-delta-fiq.h>
#include <linux/platform_data/gpio-omap.h>
+#include <linux/soc/ti/omap1-io.h>
#include <asm/assembler.h>
#include <asm/irq.h>
+#include "hardware.h"
#include "ams-delta-fiq.h"
#include "board-ams-delta.h"
#include "iomap.h"
-#include "soc.h"
/*
* OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c.
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 4eea3e39e633..1f5852be057e 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -21,7 +21,9 @@
#include <linux/platform_device.h>
#include <asm/fiq.h>
+#include <linux/soc/ti/omap1-io.h>
+#include "hardware.h"
#include "ams-delta-fiq.h"
#include "board-ams-delta.h"
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.h b/arch/arm/mach-omap1/ams-delta-fiq.h
index fd76df3cce37..7f843caedb7c 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.h
+++ b/arch/arm/mach-omap1/ams-delta-fiq.h
@@ -16,7 +16,7 @@
#ifndef __AMS_DELTA_FIQ_H
#define __AMS_DELTA_FIQ_H
-#include <mach/irqs.h>
+#include "irqs.h"
/*
* Interrupt number used for passing control from FIQ to IRQ.
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 735f0314dc05..9108c871d129 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -36,11 +36,9 @@
#include <asm/mach/map.h>
#include <linux/platform_data/keypad-omap.h>
-#include <mach/mux.h>
-#include <mach/hardware.h>
+#include "hardware.h"
#include "usb.h"
-
#include "ams-delta-fiq.h"
#include "board-ams-delta.h"
#include "iomap.h"
@@ -666,7 +664,7 @@ static void __init ams_delta_latch2_init(void)
{
u16 latch2 = 1 << LATCH2_PIN_MODEM_NRESET | 1 << LATCH2_PIN_MODEM_CODEC;
- __raw_writew(latch2, LATCH2_VIRT);
+ __raw_writew(latch2, IOMEM(LATCH2_VIRT));
}
static void __init ams_delta_init(void)
@@ -824,8 +822,6 @@ static int __init modem_nreset_init(void)
*/
static int __init ams_delta_modem_init(void)
{
- int err;
-
if (!machine_is_ams_delta())
return -ENODEV;
@@ -834,9 +830,7 @@ static int __init ams_delta_modem_init(void)
/* Initialize the modem_nreset regulator consumer before use */
modem_priv.regulator = ERR_PTR(-ENODEV);
- err = platform_device_register(&ams_delta_modem_device);
-
- return err;
+ return platform_device_register(&ams_delta_modem_device);
}
arch_initcall_sync(ams_delta_modem_init);
@@ -873,7 +867,7 @@ static void __init ams_delta_init_late(void)
static void __init ams_delta_map_io(void)
{
- omap15xx_map_io();
+ omap1_map_io();
iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
}
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
deleted file mode 100644
index c3aa6f2e5546..000000000000
--- a/arch/arm/mach-omap1/board-fsample.c
+++ /dev/null
@@ -1,366 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-fsample.c
- *
- * Modified from board-perseus2.c
- *
- * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
- * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/platnand.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/smc91x.h>
-#include <linux/omapfb.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/tc.h>
-#include <mach/mux.h>
-#include "flash.h"
-#include <linux/platform_data/keypad-omap.h>
-
-#include <mach/hardware.h>
-
-#include "iomap.h"
-#include "common.h"
-#include "fpga.h"
-
-/* fsample is pretty close to p2-sample */
-
-#define fsample_cpld_read(reg) __raw_readb(reg)
-#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
-
-#define FSAMPLE_CPLD_BASE 0xE8100000
-#define FSAMPLE_CPLD_SIZE SZ_4K
-#define FSAMPLE_CPLD_START 0x05080000
-
-#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
-#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
-#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
-#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
-#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
-#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
-
-#define FSAMPLE_CPLD_BIT_BT_RESET 0
-#define FSAMPLE_CPLD_BIT_LCD_RESET 1
-#define FSAMPLE_CPLD_BIT_CAM_PWDN 2
-#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
-#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
-#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
-#define FSAMPLE_CPLD_BIT_BACKLIGHT 6
-#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
-#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
-#define FSAMPLE_CPLD_BIT_OTG_RESET 9
-
-#define fsample_cpld_set(bit) \
- fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
-
-#define fsample_cpld_clear(bit) \
- fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
-
-static const unsigned int fsample_keymap[] = {
- KEY(0, 0, KEY_UP),
- KEY(1, 0, KEY_RIGHT),
- KEY(2, 0, KEY_LEFT),
- KEY(3, 0, KEY_DOWN),
- KEY(4, 0, KEY_ENTER),
- KEY(0, 1, KEY_F10),
- KEY(1, 1, KEY_SEND),
- KEY(2, 1, KEY_END),
- KEY(3, 1, KEY_VOLUMEDOWN),
- KEY(4, 1, KEY_VOLUMEUP),
- KEY(5, 1, KEY_RECORD),
- KEY(0, 2, KEY_F9),
- KEY(1, 2, KEY_3),
- KEY(2, 2, KEY_6),
- KEY(3, 2, KEY_9),
- KEY(4, 2, KEY_KPDOT),
- KEY(0, 3, KEY_BACK),
- KEY(1, 3, KEY_2),
- KEY(2, 3, KEY_5),
- KEY(3, 3, KEY_8),
- KEY(4, 3, KEY_0),
- KEY(5, 3, KEY_KPSLASH),
- KEY(0, 4, KEY_HOME),
- KEY(1, 4, KEY_1),
- KEY(2, 4, KEY_4),
- KEY(3, 4, KEY_7),
- KEY(4, 4, KEY_KPASTERISK),
- KEY(5, 4, KEY_POWER),
-};
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
- .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = INT_7XX_MPU_EXT_NIRQ,
- .end = 0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static void __init fsample_init_smc91x(void)
-{
- __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
- __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
- H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
-}
-
-static struct mtd_partition nor_partitions[] = {
- /* bootloader (U-Boot, etc) in first sector */
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next sector */
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = 0,
- },
- /* kernel */
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0
- },
- /* rest of flash is a file system */
- {
- .name = "rootfs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- },
-};
-
-static struct physmap_flash_data nor_data = {
- .width = 2,
- .set_vpp = omap1_set_vpp,
- .parts = nor_partitions,
- .nr_parts = ARRAY_SIZE(nor_partitions),
-};
-
-static struct resource nor_resource = {
- .start = OMAP_CS0_PHYS,
- .end = OMAP_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device nor_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &nor_data,
- },
- .num_resources = 1,
- .resource = &nor_resource,
-};
-
-#define FSAMPLE_NAND_RB_GPIO_PIN 62
-
-static int nand_dev_ready(struct nand_chip *chip)
-{
- return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
-}
-
-static struct platform_nand_data nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_offset = 0,
- .options = NAND_SAMSUNG_LP_OPTIONS,
- },
- .ctrl = {
- .cmd_ctrl = omap1_nand_cmd_ctl,
- .dev_ready = nand_dev_ready,
- },
-};
-
-static struct resource nand_resource = {
- .start = OMAP_CS3_PHYS,
- .end = OMAP_CS3_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device nand_device = {
- .name = "gen_nand",
- .id = 0,
- .dev = {
- .platform_data = &nand_data,
- },
- .num_resources = 1,
- .resource = &nand_resource,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &smc91x_info,
- },
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static struct resource kp_resources[] = {
- [0] = {
- .start = INT_7XX_MPUIO_KEYPAD,
- .end = INT_7XX_MPUIO_KEYPAD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct matrix_keymap_data fsample_keymap_data = {
- .keymap = fsample_keymap,
- .keymap_size = ARRAY_SIZE(fsample_keymap),
-};
-
-static struct omap_kp_platform_data kp_data = {
- .rows = 8,
- .cols = 8,
- .keymap_data = &fsample_keymap_data,
- .delay = 4,
-};
-
-static struct platform_device kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &kp_data,
- },
- .num_resources = ARRAY_SIZE(kp_resources),
- .resource = kp_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
- &nor_device,
- &nand_device,
- &smc91x_device,
- &kp_device,
-};
-
-static const struct omap_lcd_config fsample_lcd_config = {
- .ctrl_name = "internal",
-};
-
-static void __init omap_fsample_init(void)
-{
- /* Early, board-dependent init */
-
- /*
- * Hold GSM Reset until needed
- */
- omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
-
- /*
- * UARTs -> done automagically by 8250 driver
- */
-
- /*
- * CSx timings, GPIO Mux ... setup
- */
-
- /* Flash: CS0 timings setup */
- omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
- omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
-
- /*
- * Ethernet support through the debug board
- * CS1 timings setup
- */
- omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
- omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
-
- /*
- * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
- * It is used as the Ethernet controller interrupt
- */
- omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
- OMAP7XX_IO_CONF_9);
-
- fsample_init_smc91x();
-
- BUG_ON(gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0);
- gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
-
- omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
- omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
-
- /* Mux pins for keypad */
- omap_cfg_reg(E2_7XX_KBR0);
- omap_cfg_reg(J7_7XX_KBR1);
- omap_cfg_reg(E1_7XX_KBR2);
- omap_cfg_reg(F3_7XX_KBR3);
- omap_cfg_reg(D2_7XX_KBR4);
- omap_cfg_reg(C2_7XX_KBC0);
- omap_cfg_reg(D3_7XX_KBC1);
- omap_cfg_reg(E4_7XX_KBC2);
- omap_cfg_reg(F4_7XX_KBC3);
- omap_cfg_reg(E3_7XX_KBC4);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- omap_serial_init();
- omap_register_i2c_bus(1, 100, NULL, 0);
-
- omapfb_set_lcd_config(&fsample_lcd_config);
-}
-
-/* Only FPGA needs to be mapped here. All others are done with ioremap */
-static struct map_desc omap_fsample_io_desc[] __initdata = {
- {
- .virtual = H2P2_DBG_FPGA_BASE,
- .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
- .length = H2P2_DBG_FPGA_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = FSAMPLE_CPLD_BASE,
- .pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
- .length = FSAMPLE_CPLD_SIZE,
- .type = MT_DEVICE
- }
-};
-
-static void __init omap_fsample_map_io(void)
-{
- omap15xx_map_io();
- iotable_init(omap_fsample_io_desc,
- ARRAY_SIZE(omap_fsample_io_desc));
-}
-
-MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
-/* Maintainer: Brian Swetland <swetland@google.com> */
- .atag_offset = 0x100,
- .map_io = omap_fsample_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = omap_fsample_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
deleted file mode 100644
index 8ef0a9b17e92..000000000000
--- a/arch/arm/mach-omap1/board-generic.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-generic.c
- *
- * Modified from board-innovator1510.c
- *
- * Code for generic OMAP board. Should work on many OMAP systems where
- * the device drivers take care of all the necessary hardware initialization.
- * Do not put any board specific code to this file; create a new machine
- * type if you need custom low-level initializations.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/mux.h>
-
-#include "usb.h"
-
-#include "common.h"
-
-/* assume no Mini-AB port */
-
-#ifdef CONFIG_ARCH_OMAP15XX
-static struct omap_usb_config generic1510_usb_config __initdata = {
- .register_host = 1,
- .register_dev = 1,
- .hmc_mode = 16,
- .pins[0] = 3,
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static struct omap_usb_config generic1610_usb_config __initdata = {
-#ifdef CONFIG_USB_OTG
- .otg = 1,
-#endif
- .register_host = 1,
- .register_dev = 1,
- .hmc_mode = 16,
- .pins[0] = 6,
-};
-#endif
-
-static void __init omap_generic_init(void)
-{
-#ifdef CONFIG_ARCH_OMAP15XX
- if (cpu_is_omap15xx()) {
- /* mux pins for uarts */
- omap_cfg_reg(UART1_TX);
- omap_cfg_reg(UART1_RTS);
- omap_cfg_reg(UART2_TX);
- omap_cfg_reg(UART2_RTS);
- omap_cfg_reg(UART3_TX);
- omap_cfg_reg(UART3_RX);
-
- omap1_usb_init(&generic1510_usb_config);
- }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
- if (!cpu_is_omap1510()) {
- omap1_usb_init(&generic1610_usb_config);
- }
-#endif
-
- omap_serial_init();
- omap_register_i2c_bus(1, 100, NULL, 0);
-}
-
-MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
- /* Maintainer: Tony Lindgren <tony@atomide.com> */
- .atag_offset = 0x100,
- .map_io = omap16xx_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = omap_generic_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
deleted file mode 100644
index 06c5404078aa..000000000000
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-h2-mmc.c
- *
- * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
- * Author: Felipe Balbi <felipe.lima@indt.org.br>
- *
- * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is:
- * Copyright (C) 2006 Nokia Corporation
- */
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/gpio-omap.h>
-#include <linux/mfd/tps65010.h>
-
-#include "board-h2.h"
-#include "mmc.h"
-
-#if IS_ENABLED(CONFIG_MMC_OMAP)
-
-static int mmc_set_power(struct device *dev, int slot, int power_on,
- int vdd)
-{
- gpio_set_value(H2_TPS_GPIO_MMC_PWR_EN, power_on);
- return 0;
-}
-
-static int mmc_late_init(struct device *dev)
-{
- int ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power");
- if (ret < 0)
- return ret;
-
- gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0);
-
- return ret;
-}
-
-static void mmc_cleanup(struct device *dev)
-{
- gpio_free(H2_TPS_GPIO_MMC_PWR_EN);
-}
-
-/*
- * H2 could use the following functions tested:
- * - mmc_get_cover_state that uses OMAP_MPUIO(1)
- * - mmc_get_wp that uses OMAP_MPUIO(3)
- */
-static struct omap_mmc_platform_data mmc1_data = {
- .nr_slots = 1,
- .init = mmc_late_init,
- .cleanup = mmc_cleanup,
- .slots[0] = {
- .set_power = mmc_set_power,
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .name = "mmcblk",
- },
-};
-
-static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC];
-
-void __init h2_mmc_init(void)
-{
- mmc_data[0] = &mmc1_data;
- omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC);
-}
-
-#else
-
-void __init h2_mmc_init(void)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
deleted file mode 100644
index b8cf0d84f8ab..000000000000
--- a/arch/arm/mach-omap1/board-h2.c
+++ /dev/null
@@ -1,450 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-h2.c
- *
- * Board specific inits for OMAP-1610 H2
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * H2 specific changes and cleanup
- * Copyright (C) 2004 Nokia Corporation by Imre Deak <imre.deak@nokia.com>
- */
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/platnand.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/mfd/tps65010.h>
-#include <linux/smc91x.h>
-#include <linux/omapfb.h>
-#include <linux/platform_data/gpio-omap.h>
-#include <linux/leds.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/mux.h>
-#include <linux/omap-dma.h>
-#include <mach/tc.h>
-#include <linux/platform_data/keypad-omap.h>
-#include "flash.h"
-
-#include <mach/hardware.h>
-#include "usb.h"
-
-#include "common.h"
-#include "board-h2.h"
-
-/* The first 16 SoC GPIO lines are on this GPIO chip */
-#define OMAP_GPIO_LABEL "gpio-0-15"
-
-/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
-#define OMAP1610_ETHR_START 0x04000300
-
-static const unsigned int h2_keymap[] = {
- KEY(0, 0, KEY_LEFT),
- KEY(1, 0, KEY_RIGHT),
- KEY(2, 0, KEY_3),
- KEY(3, 0, KEY_F10),
- KEY(4, 0, KEY_F5),
- KEY(5, 0, KEY_9),
- KEY(0, 1, KEY_DOWN),
- KEY(1, 1, KEY_UP),
- KEY(2, 1, KEY_2),
- KEY(3, 1, KEY_F9),
- KEY(4, 1, KEY_F7),
- KEY(5, 1, KEY_0),
- KEY(0, 2, KEY_ENTER),
- KEY(1, 2, KEY_6),
- KEY(2, 2, KEY_1),
- KEY(3, 2, KEY_F2),
- KEY(4, 2, KEY_F6),
- KEY(5, 2, KEY_HOME),
- KEY(0, 3, KEY_8),
- KEY(1, 3, KEY_5),
- KEY(2, 3, KEY_F12),
- KEY(3, 3, KEY_F3),
- KEY(4, 3, KEY_F8),
- KEY(5, 3, KEY_END),
- KEY(0, 4, KEY_7),
- KEY(1, 4, KEY_4),
- KEY(2, 4, KEY_F11),
- KEY(3, 4, KEY_F1),
- KEY(4, 4, KEY_F4),
- KEY(5, 4, KEY_ESC),
- KEY(0, 5, KEY_F13),
- KEY(1, 5, KEY_F14),
- KEY(2, 5, KEY_F15),
- KEY(3, 5, KEY_F16),
- KEY(4, 5, KEY_SLEEP),
-};
-
-static struct mtd_partition h2_nor_partitions[] = {
- /* bootloader (U-Boot, etc) in first sector */
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next sector */
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = 0,
- },
- /* kernel */
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0
- },
- /* file system */
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data h2_nor_data = {
- .width = 2,
- .set_vpp = omap1_set_vpp,
- .parts = h2_nor_partitions,
- .nr_parts = ARRAY_SIZE(h2_nor_partitions),
-};
-
-static struct resource h2_nor_resource = {
- /* This is on CS3, wherever it's mapped */
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device h2_nor_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &h2_nor_data,
- },
- .num_resources = 1,
- .resource = &h2_nor_resource,
-};
-
-static struct mtd_partition h2_nand_partitions[] = {
-#if 0
- /* REVISIT: enable these partitions if you make NAND BOOT
- * work on your H2 (rev C or newer); published versions of
- * x-load only support P2 and H3.
- */
- {
- .name = "xloader",
- .offset = 0,
- .size = 64 * 1024,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "bootloader",
- .offset = MTDPART_OFS_APPEND,
- .size = 256 * 1024,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 192 * 1024,
- },
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = 2 * SZ_1M,
- },
-#endif
- {
- .name = "filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define H2_NAND_RB_GPIO_PIN 62
-
-static int h2_nand_dev_ready(struct nand_chip *chip)
-{
- return gpio_get_value(H2_NAND_RB_GPIO_PIN);
-}
-
-static struct platform_nand_data h2_nand_platdata = {
- .chip = {
- .nr_chips = 1,
- .chip_offset = 0,
- .nr_partitions = ARRAY_SIZE(h2_nand_partitions),
- .partitions = h2_nand_partitions,
- .options = NAND_SAMSUNG_LP_OPTIONS,
- },
- .ctrl = {
- .cmd_ctrl = omap1_nand_cmd_ctl,
- .dev_ready = h2_nand_dev_ready,
- },
-};
-
-static struct resource h2_nand_resource = {
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device h2_nand_device = {
- .name = "gen_nand",
- .id = 0,
- .dev = {
- .platform_data = &h2_nand_platdata,
- },
- .num_resources = 1,
- .resource = &h2_nand_resource,
-};
-
-static struct smc91x_platdata h2_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource h2_smc91x_resources[] = {
- [0] = {
- .start = OMAP1610_ETHR_START, /* Physical */
- .end = OMAP1610_ETHR_START + 0xf,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device h2_smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &h2_smc91x_info,
- },
- .num_resources = ARRAY_SIZE(h2_smc91x_resources),
- .resource = h2_smc91x_resources,
-};
-
-static struct resource h2_kp_resources[] = {
- [0] = {
- .start = INT_KEYBOARD,
- .end = INT_KEYBOARD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct matrix_keymap_data h2_keymap_data = {
- .keymap = h2_keymap,
- .keymap_size = ARRAY_SIZE(h2_keymap),
-};
-
-static struct omap_kp_platform_data h2_kp_data = {
- .rows = 8,
- .cols = 8,
- .keymap_data = &h2_keymap_data,
- .rep = true,
- .delay = 9,
- .dbounce = true,
-};
-
-static struct platform_device h2_kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &h2_kp_data,
- },
- .num_resources = ARRAY_SIZE(h2_kp_resources),
- .resource = h2_kp_resources,
-};
-
-static const struct gpio_led h2_gpio_led_pins[] = {
- {
- .name = "h2:red",
- .default_trigger = "heartbeat",
- .gpio = 3,
- },
- {
- .name = "h2:green",
- .default_trigger = "cpu0",
- .gpio = OMAP_MPUIO(4),
- },
-};
-
-static struct gpio_led_platform_data h2_gpio_led_data = {
- .leds = h2_gpio_led_pins,
- .num_leds = ARRAY_SIZE(h2_gpio_led_pins),
-};
-
-static struct platform_device h2_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &h2_gpio_led_data,
- },
-};
-
-static struct platform_device *h2_devices[] __initdata = {
- &h2_nor_device,
- &h2_nand_device,
- &h2_smc91x_device,
- &h2_kp_device,
- &h2_gpio_leds,
-};
-
-static void __init h2_init_smc91x(void)
-{
- if (gpio_request(0, "SMC91x irq") < 0) {
- printk("Error requesting gpio 0 for smc91x irq\n");
- return;
- }
-}
-
-static int tps_setup(struct i2c_client *client, void *context)
-{
- if (!IS_BUILTIN(CONFIG_TPS65010))
- return -ENOSYS;
-
- tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V |
- TPS_LDO1_ENABLE | TPS_VLDO1_3_0V);
-
- return 0;
-}
-
-static struct tps65010_board tps_board = {
- .base = H2_TPS_GPIO_BASE,
- .outmask = 0x0f,
- .setup = tps_setup,
-};
-
-static struct i2c_board_info __initdata h2_i2c_board_info[] = {
- {
- I2C_BOARD_INFO("tps65010", 0x48),
- .platform_data = &tps_board,
- }, {
- .type = "isp1301_omap",
- .addr = 0x2d,
- .dev_name = "isp1301",
- },
-};
-
-static struct gpiod_lookup_table isp1301_gpiod_table = {
- .dev_id = "isp1301",
- .table = {
- /* Active low since the irq triggers on falling edge */
- GPIO_LOOKUP(OMAP_GPIO_LABEL, 2,
- NULL, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct omap_usb_config h2_usb_config __initdata = {
- /* usb1 has a Mini-AB port and external isp1301 transceiver */
- .otg = 2,
-
-#if IS_ENABLED(CONFIG_USB_OMAP)
- .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
- /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
-#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
- /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */
- .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
-#endif
-
- .pins[1] = 3,
-};
-
-static const struct omap_lcd_config h2_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-
-static void __init h2_init(void)
-{
- h2_init_smc91x();
-
- /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
- * to address 0 by a dip switch), NAND on CS2B. The NAND driver will
- * notice whether a NAND chip is enabled at probe time.
- *
- * FIXME revC boards (and H3) support NAND-boot, with a dip switch to
- * put NOR on CS2B and NAND (which on H2 may be 16bit) on CS3. Try
- * detecting that in code here, to avoid probing every possible flash
- * configuration...
- */
- h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys();
- h2_nor_resource.end += SZ_32M - 1;
-
- h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS;
- h2_nand_resource.end += SZ_4K - 1;
- BUG_ON(gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0);
- gpio_direction_input(H2_NAND_RB_GPIO_PIN);
-
- gpiod_add_lookup_table(&isp1301_gpiod_table);
-
- omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
- omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
-
- /* MMC: card detect and WP */
- /* omap_cfg_reg(U19_ARMIO1); */ /* CD */
- omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */
-
- /* Mux pins for keypad */
- omap_cfg_reg(F18_1610_KBC0);
- omap_cfg_reg(D20_1610_KBC1);
- omap_cfg_reg(D19_1610_KBC2);
- omap_cfg_reg(E18_1610_KBC3);
- omap_cfg_reg(C21_1610_KBC4);
- omap_cfg_reg(G18_1610_KBR0);
- omap_cfg_reg(F19_1610_KBR1);
- omap_cfg_reg(H14_1610_KBR2);
- omap_cfg_reg(E20_1610_KBR3);
- omap_cfg_reg(E19_1610_KBR4);
- omap_cfg_reg(N19_1610_KBR5);
-
- /* GPIO based LEDs */
- omap_cfg_reg(P18_1610_GPIO3);
- omap_cfg_reg(MPUIO4);
-
- h2_smc91x_resources[1].start = gpio_to_irq(0);
- h2_smc91x_resources[1].end = gpio_to_irq(0);
- platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
- omap_serial_init();
-
- /* ISP1301 IRQ wired at M14 */
- omap_cfg_reg(M14_1510_GPIO2);
- h2_i2c_board_info[0].irq = gpio_to_irq(58);
- omap_register_i2c_bus(1, 100, h2_i2c_board_info,
- ARRAY_SIZE(h2_i2c_board_info));
- omap1_usb_init(&h2_usb_config);
- h2_mmc_init();
-
- omapfb_set_lcd_config(&h2_lcd_config);
-}
-
-MACHINE_START(OMAP_H2, "TI-H2")
- /* Maintainer: Imre Deak <imre.deak@nokia.com> */
- .atag_offset = 0x100,
- .map_io = omap16xx_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = h2_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.h b/arch/arm/mach-omap1/board-h2.h
deleted file mode 100644
index 315e2662547e..000000000000
--- a/arch/arm/mach-omap1/board-h2.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * arch/arm/mach-omap1/board-h2.h
- *
- * Hardware definitions for TI OMAP1610 H2 board.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_H2_H
-#define __ASM_ARCH_OMAP_H2_H
-
-#define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
-# define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3)
-
-extern void h2_mmc_init(void);
-
-#endif /* __ASM_ARCH_OMAP_H2_H */
-
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
deleted file mode 100644
index f595bd4f5024..000000000000
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-h3-mmc.c
- *
- * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
- * Author: Felipe Balbi <felipe.lima@indt.org.br>
- *
- * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is:
- * Copyright (C) 2006 Nokia Corporation
- */
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
-#include <linux/mfd/tps65010.h>
-
-#include "common.h"
-#include "board-h3.h"
-#include "mmc.h"
-
-#if IS_ENABLED(CONFIG_MMC_OMAP)
-
-static int mmc_set_power(struct device *dev, int slot, int power_on,
- int vdd)
-{
- gpio_set_value(H3_TPS_GPIO_MMC_PWR_EN, power_on);
- return 0;
-}
-
-/*
- * H3 could use the following functions tested:
- * - mmc_get_cover_state that uses OMAP_MPUIO(1)
- * - mmc_get_wp that maybe uses OMAP_MPUIO(3)
- */
-static struct omap_mmc_platform_data mmc1_data = {
- .nr_slots = 1,
- .slots[0] = {
- .set_power = mmc_set_power,
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .name = "mmcblk",
- },
-};
-
-static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC];
-
-void __init h3_mmc_init(void)
-{
- int ret;
-
- ret = gpio_request(H3_TPS_GPIO_MMC_PWR_EN, "MMC power");
- if (ret < 0)
- return;
- gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0);
-
- mmc_data[0] = &mmc1_data;
- omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC);
-}
-
-#else
-
-void __init h3_mmc_init(void)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
deleted file mode 100644
index 86260498c344..000000000000
--- a/arch/arm/mach-omap1/board-h3.c
+++ /dev/null
@@ -1,457 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-h3.c
- *
- * This file contains OMAP1710 H3 specific code.
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- * Copyright (C) 2002 MontaVista Software, Inc.
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc.
- * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
- */
-#include <linux/gpio.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/errno.h>
-#include <linux/workqueue.h>
-#include <linux/i2c.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/platnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/tps65010.h>
-#include <linux/smc91x.h>
-#include <linux/omapfb.h>
-#include <linux/platform_data/gpio-omap.h>
-#include <linux/leds.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/mux.h>
-#include <mach/tc.h>
-#include <linux/platform_data/keypad-omap.h>
-#include <linux/omap-dma.h>
-#include "flash.h"
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include "usb.h"
-
-#include "common.h"
-#include "board-h3.h"
-
-/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
-#define OMAP1710_ETHR_START 0x04000300
-
-#define H3_TS_GPIO 48
-
-static const unsigned int h3_keymap[] = {
- KEY(0, 0, KEY_LEFT),
- KEY(1, 0, KEY_RIGHT),
- KEY(2, 0, KEY_3),
- KEY(3, 0, KEY_F10),
- KEY(4, 0, KEY_F5),
- KEY(5, 0, KEY_9),
- KEY(0, 1, KEY_DOWN),
- KEY(1, 1, KEY_UP),
- KEY(2, 1, KEY_2),
- KEY(3, 1, KEY_F9),
- KEY(4, 1, KEY_F7),
- KEY(5, 1, KEY_0),
- KEY(0, 2, KEY_ENTER),
- KEY(1, 2, KEY_6),
- KEY(2, 2, KEY_1),
- KEY(3, 2, KEY_F2),
- KEY(4, 2, KEY_F6),
- KEY(5, 2, KEY_HOME),
- KEY(0, 3, KEY_8),
- KEY(1, 3, KEY_5),
- KEY(2, 3, KEY_F12),
- KEY(3, 3, KEY_F3),
- KEY(4, 3, KEY_F8),
- KEY(5, 3, KEY_END),
- KEY(0, 4, KEY_7),
- KEY(1, 4, KEY_4),
- KEY(2, 4, KEY_F11),
- KEY(3, 4, KEY_F1),
- KEY(4, 4, KEY_F4),
- KEY(5, 4, KEY_ESC),
- KEY(0, 5, KEY_F13),
- KEY(1, 5, KEY_F14),
- KEY(2, 5, KEY_F15),
- KEY(3, 5, KEY_F16),
- KEY(4, 5, KEY_SLEEP),
-};
-
-
-static struct mtd_partition nor_partitions[] = {
- /* bootloader (U-Boot, etc) in first sector */
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next sector */
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = 0,
- },
- /* kernel */
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0
- },
- /* file system */
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data nor_data = {
- .width = 2,
- .set_vpp = omap1_set_vpp,
- .parts = nor_partitions,
- .nr_parts = ARRAY_SIZE(nor_partitions),
-};
-
-static struct resource nor_resource = {
- /* This is on CS3, wherever it's mapped */
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device nor_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &nor_data,
- },
- .num_resources = 1,
- .resource = &nor_resource,
-};
-
-static struct mtd_partition nand_partitions[] = {
-#if 0
- /* REVISIT: enable these partitions if you make NAND BOOT work */
- {
- .name = "xloader",
- .offset = 0,
- .size = 64 * 1024,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "bootloader",
- .offset = MTDPART_OFS_APPEND,
- .size = 256 * 1024,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = 192 * 1024,
- },
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = 2 * SZ_1M,
- },
-#endif
- {
- .name = "filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define H3_NAND_RB_GPIO_PIN 10
-
-static int nand_dev_ready(struct nand_chip *chip)
-{
- return gpio_get_value(H3_NAND_RB_GPIO_PIN);
-}
-
-static struct platform_nand_data nand_platdata = {
- .chip = {
- .nr_chips = 1,
- .chip_offset = 0,
- .nr_partitions = ARRAY_SIZE(nand_partitions),
- .partitions = nand_partitions,
- .options = NAND_SAMSUNG_LP_OPTIONS,
- },
- .ctrl = {
- .cmd_ctrl = omap1_nand_cmd_ctl,
- .dev_ready = nand_dev_ready,
-
- },
-};
-
-static struct resource nand_resource = {
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device nand_device = {
- .name = "gen_nand",
- .id = 0,
- .dev = {
- .platform_data = &nand_platdata,
- },
- .num_resources = 1,
- .resource = &nand_resource,
-};
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = OMAP1710_ETHR_START, /* Physical */
- .end = OMAP1710_ETHR_START + 0xf,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &smc91x_info,
- },
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static void __init h3_init_smc91x(void)
-{
- omap_cfg_reg(W15_1710_GPIO40);
- if (gpio_request(40, "SMC91x irq") < 0) {
- printk("Error requesting gpio 40 for smc91x irq\n");
- return;
- }
-}
-
-#define GPTIMER_BASE 0xFFFB1400
-#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
-#define GPTIMER_REGS_SIZE 0x46
-
-static struct resource intlat_resources[] = {
- [0] = {
- .start = GPTIMER_REGS(0), /* Physical */
- .end = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = INT_1610_GPTIMER1,
- .end = INT_1610_GPTIMER1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device intlat_device = {
- .name = "omap_intlat",
- .id = 0,
- .num_resources = ARRAY_SIZE(intlat_resources),
- .resource = intlat_resources,
-};
-
-static struct resource h3_kp_resources[] = {
- [0] = {
- .start = INT_KEYBOARD,
- .end = INT_KEYBOARD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct matrix_keymap_data h3_keymap_data = {
- .keymap = h3_keymap,
- .keymap_size = ARRAY_SIZE(h3_keymap),
-};
-
-static struct omap_kp_platform_data h3_kp_data = {
- .rows = 8,
- .cols = 8,
- .keymap_data = &h3_keymap_data,
- .rep = true,
- .delay = 9,
- .dbounce = true,
-};
-
-static struct platform_device h3_kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &h3_kp_data,
- },
- .num_resources = ARRAY_SIZE(h3_kp_resources),
- .resource = h3_kp_resources,
-};
-
-static struct platform_device h3_lcd_device = {
- .name = "lcd_h3",
- .id = -1,
-};
-
-static struct spi_board_info h3_spi_board_info[] __initdata = {
- [0] = {
- .modalias = "tsc2101",
- .bus_num = 2,
- .chip_select = 0,
- .max_speed_hz = 16000000,
- /* .platform_data = &tsc_platform_data, */
- },
-};
-
-static const struct gpio_led h3_gpio_led_pins[] = {
- {
- .name = "h3:red",
- .default_trigger = "heartbeat",
- .gpio = 3,
- },
- {
- .name = "h3:green",
- .default_trigger = "cpu0",
- .gpio = OMAP_MPUIO(4),
- },
-};
-
-static struct gpio_led_platform_data h3_gpio_led_data = {
- .leds = h3_gpio_led_pins,
- .num_leds = ARRAY_SIZE(h3_gpio_led_pins),
-};
-
-static struct platform_device h3_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &h3_gpio_led_data,
- },
-};
-
-static struct platform_device *devices[] __initdata = {
- &nor_device,
- &nand_device,
- &smc91x_device,
- &intlat_device,
- &h3_kp_device,
- &h3_lcd_device,
- &h3_gpio_leds,
-};
-
-static struct omap_usb_config h3_usb_config __initdata = {
- /* usb1 has a Mini-AB port and external isp1301 transceiver */
- .otg = 2,
-
-#if IS_ENABLED(CONFIG_USB_OMAP)
- .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
-#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
- /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
- .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
-#endif
-
- .pins[1] = 3,
-};
-
-static const struct omap_lcd_config h3_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-
-static struct i2c_board_info __initdata h3_i2c_board_info[] = {
- {
- I2C_BOARD_INFO("tps65013", 0x48),
- },
- {
- I2C_BOARD_INFO("isp1301_omap", 0x2d),
- },
-};
-
-static void __init h3_init(void)
-{
- h3_init_smc91x();
-
- /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
- * to address 0 by a dip switch), NAND on CS2B. The NAND driver will
- * notice whether a NAND chip is enabled at probe time.
- *
- * H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND
- * (which on H2 may be 16bit) on CS3. Try detecting that in code here,
- * to avoid probing every possible flash configuration...
- */
- nor_resource.end = nor_resource.start = omap_cs3_phys();
- nor_resource.end += SZ_32M - 1;
-
- nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS;
- nand_resource.end += SZ_4K - 1;
- BUG_ON(gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0);
- gpio_direction_input(H3_NAND_RB_GPIO_PIN);
-
- /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
- /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
- omap_cfg_reg(V2_1710_GPIO10);
-
- /* Mux pins for keypad */
- omap_cfg_reg(F18_1610_KBC0);
- omap_cfg_reg(D20_1610_KBC1);
- omap_cfg_reg(D19_1610_KBC2);
- omap_cfg_reg(E18_1610_KBC3);
- omap_cfg_reg(C21_1610_KBC4);
- omap_cfg_reg(G18_1610_KBR0);
- omap_cfg_reg(F19_1610_KBR1);
- omap_cfg_reg(H14_1610_KBR2);
- omap_cfg_reg(E20_1610_KBR3);
- omap_cfg_reg(E19_1610_KBR4);
- omap_cfg_reg(N19_1610_KBR5);
-
- /* GPIO based LEDs */
- omap_cfg_reg(P18_1610_GPIO3);
- omap_cfg_reg(MPUIO4);
-
- smc91x_resources[1].start = gpio_to_irq(40);
- smc91x_resources[1].end = gpio_to_irq(40);
- platform_add_devices(devices, ARRAY_SIZE(devices));
- h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO);
- spi_register_board_info(h3_spi_board_info,
- ARRAY_SIZE(h3_spi_board_info));
- omap_serial_init();
- h3_i2c_board_info[1].irq = gpio_to_irq(14);
- omap_register_i2c_bus(1, 100, h3_i2c_board_info,
- ARRAY_SIZE(h3_i2c_board_info));
- omap1_usb_init(&h3_usb_config);
- h3_mmc_init();
-
- omapfb_set_lcd_config(&h3_lcd_config);
-}
-
-MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
- /* Maintainer: Texas Instruments, Inc. */
- .atag_offset = 0x100,
- .map_io = omap16xx_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = h3_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.h b/arch/arm/mach-omap1/board-h3.h
deleted file mode 100644
index 78de535be3c5..000000000000
--- a/arch/arm/mach-omap1/board-h3.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-omap1/board-h3.h
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_H3_H
-#define __ASM_ARCH_OMAP_H3_H
-
-#define H3_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
-# define H3_TPS_GPIO_MMC_PWR_EN (H3_TPS_GPIO_BASE + 4)
-
-extern void h3_mmc_init(void);
-
-#endif /* __ASM_ARCH_OMAP_H3_H */
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
deleted file mode 100644
index f7220b60eb61..000000000000
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ /dev/null
@@ -1,594 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * HTC Herald board configuration
- * Copyright (C) 2009 Cory Maccarrone <darkstar6262@gmail.com>
- * Copyright (C) 2009 Wing Linux
- *
- * Based on the board-htcwizard.c file from the linwizard project:
- * Copyright (C) 2006 Unai Uribarri
- * Copyright (C) 2008 linwizard.sourceforge.net
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-gpio.h>
-#include <linux/htcpld.h>
-#include <linux/leds.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/omapfb.h>
-#include <linux/platform_data/keypad-omap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/omap7xx.h>
-#include "mmc.h"
-
-#include <mach/irqs.h>
-#include "usb.h"
-
-#include "common.h"
-
-/* LCD register definition */
-#define OMAP_LCDC_CONTROL (0xfffec000 + 0x00)
-#define OMAP_LCDC_STATUS (0xfffec000 + 0x10)
-#define OMAP_DMA_LCD_CCR (0xfffee300 + 0xc2)
-#define OMAP_DMA_LCD_CTRL (0xfffee300 + 0xc4)
-#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
-#define OMAP_LCDC_STAT_DONE (1 << 0)
-
-/* GPIO definitions for the power button and keyboard slide switch */
-#define HTCHERALD_GPIO_POWER 139
-#define HTCHERALD_GPIO_SLIDE 174
-#define HTCHERALD_GIRQ_BTNS 141
-
-/* GPIO definitions for the touchscreen */
-#define HTCHERALD_GPIO_TS 76
-
-/* HTCPLD definitions */
-
-/*
- * CPLD Logic
- *
- * Chip 3 - 0x03
- *
- * Function 7 6 5 4 3 2 1 0
- * ------------------------------------
- * DPAD light x x x x x x x 1
- * SoundDev x x x x 1 x x x
- * Screen white 1 x x x x x x x
- * MMC power on x x x x x 1 x x
- * Happy times (n) 0 x x x x 1 x x
- *
- * Chip 4 - 0x04
- *
- * Function 7 6 5 4 3 2 1 0
- * ------------------------------------
- * Keyboard light x x x x x x x 1
- * LCD Bright (4) x x x x x 1 1 x
- * LCD Bright (3) x x x x x 0 1 x
- * LCD Bright (2) x x x x x 1 0 x
- * LCD Bright (1) x x x x x 0 0 x
- * LCD Off x x x x 0 x x x
- * LCD image (fb) 1 x x x x x x x
- * LCD image (white) 0 x x x x x x x
- * Caps lock LED x x 1 x x x x x
- *
- * Chip 5 - 0x05
- *
- * Function 7 6 5 4 3 2 1 0
- * ------------------------------------
- * Red (solid) x x x x x 1 x x
- * Red (flash) x x x x x x 1 x
- * Green (GSM flash) x x x x 1 x x x
- * Green (GSM solid) x x x 1 x x x x
- * Green (wifi flash) x x 1 x x x x x
- * Blue (bt flash) x 1 x x x x x x
- * DPAD Int Enable 1 x x x x x x 0
- *
- * (Combinations of the above can be made for different colors.)
- * The direction pad interrupt enable must be set each time the
- * interrupt is handled.
- *
- * Chip 6 - 0x06
- *
- * Function 7 6 5 4 3 2 1 0
- * ------------------------------------
- * Vibrator x x x x 1 x x x
- * Alt LED x x x 1 x x x x
- * Screen white 1 x x x x x x x
- * Screen white x x 1 x x x x x
- * Screen white x 0 x x x x x x
- * Enable kbd dpad x x x x x x 0 x
- * Happy Times 0 1 0 x x x 0 x
- */
-
-/*
- * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account
- * for the 16 MPUIO lines.
- */
-#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16)
-#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset))
-#define HTCPLD_BASE(chip, offset) \
- (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset))
-
-#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0)
-#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0)
-#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5)
-#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1)
-#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2)
-#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3)
-#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4)
-#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5)
-#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6)
-#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3)
-#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4)
-
-#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7)
-#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6)
-#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5)
-#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4)
-
-#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7)
-#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6)
-#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5)
-#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4)
-#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3)
-
-/*
- * The htcpld chip requires a gpio write to a specific line
- * to re-enable interrupts after one has occurred.
- */
-#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7)
-#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0)
-
-/* Chip 5 */
-#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7)
-#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6)
-#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5)
-#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4)
-
-/* Chip 6 */
-#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7)
-#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6)
-#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5)
-#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4)
-#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3)
-
-/* Keyboard definition */
-
-static const unsigned int htc_herald_keymap[] = {
- KEY(0, 0, KEY_RECORD), /* Mail button */
- KEY(1, 0, KEY_CAMERA), /* Camera */
- KEY(2, 0, KEY_PHONE), /* Send key */
- KEY(3, 0, KEY_VOLUMEUP), /* Volume up */
- KEY(4, 0, KEY_F2), /* Right bar (landscape) */
- KEY(5, 0, KEY_MAIL), /* Win key (portrait) */
- KEY(6, 0, KEY_DIRECTORY), /* Right bar (protrait) */
- KEY(0, 1, KEY_LEFTCTRL), /* Windows key */
- KEY(1, 1, KEY_COMMA),
- KEY(2, 1, KEY_M),
- KEY(3, 1, KEY_K),
- KEY(4, 1, KEY_SLASH), /* OK key */
- KEY(5, 1, KEY_I),
- KEY(6, 1, KEY_U),
- KEY(0, 2, KEY_LEFTALT),
- KEY(1, 2, KEY_TAB),
- KEY(2, 2, KEY_N),
- KEY(3, 2, KEY_J),
- KEY(4, 2, KEY_ENTER),
- KEY(5, 2, KEY_H),
- KEY(6, 2, KEY_Y),
- KEY(0, 3, KEY_SPACE),
- KEY(1, 3, KEY_L),
- KEY(2, 3, KEY_B),
- KEY(3, 3, KEY_V),
- KEY(4, 3, KEY_BACKSPACE),
- KEY(5, 3, KEY_G),
- KEY(6, 3, KEY_T),
- KEY(0, 4, KEY_CAPSLOCK), /* Shift */
- KEY(1, 4, KEY_C),
- KEY(2, 4, KEY_F),
- KEY(3, 4, KEY_R),
- KEY(4, 4, KEY_O),
- KEY(5, 4, KEY_E),
- KEY(6, 4, KEY_D),
- KEY(0, 5, KEY_X),
- KEY(1, 5, KEY_Z),
- KEY(2, 5, KEY_S),
- KEY(3, 5, KEY_W),
- KEY(4, 5, KEY_P),
- KEY(5, 5, KEY_Q),
- KEY(6, 5, KEY_A),
- KEY(0, 6, KEY_CONNECT), /* Voice button */
- KEY(2, 6, KEY_CANCEL), /* End key */
- KEY(3, 6, KEY_VOLUMEDOWN), /* Volume down */
- KEY(4, 6, KEY_F1), /* Left bar (landscape) */
- KEY(5, 6, KEY_WWW), /* OK button (portrait) */
- KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */
-};
-
-static const struct matrix_keymap_data htc_herald_keymap_data = {
- .keymap = htc_herald_keymap,
- .keymap_size = ARRAY_SIZE(htc_herald_keymap),
-};
-
-static struct omap_kp_platform_data htcherald_kp_data = {
- .rows = 7,
- .cols = 7,
- .delay = 20,
- .rep = true,
- .keymap_data = &htc_herald_keymap_data,
-};
-
-static struct resource kp_resources[] = {
- [0] = {
- .start = INT_7XX_MPUIO_KEYPAD,
- .end = INT_7XX_MPUIO_KEYPAD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &htcherald_kp_data,
- },
- .num_resources = ARRAY_SIZE(kp_resources),
- .resource = kp_resources,
-};
-
-/* GPIO buttons for keyboard slide and power button */
-static struct gpio_keys_button herald_gpio_keys_table[] = {
- {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20},
- {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20},
-
- {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20},
- {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20},
- {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20},
- {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20},
-
- {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20},
- {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20},
- {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20},
- {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20},
- {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20},
-};
-
-static struct gpio_keys_platform_data herald_gpio_keys_data = {
- .buttons = herald_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(herald_gpio_keys_table),
- .rep = true,
-};
-
-static struct platform_device herald_gpiokeys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &herald_gpio_keys_data,
- },
-};
-
-/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */
-static const struct gpio_led gpio_leds[] = {
- {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
- {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
-};
-
-static struct gpio_led_platform_data gpio_leds_data = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device gpio_leds_device = {
- .name = "leds-gpio",
- .id = 0,
- .dev = {
- .platform_data = &gpio_leds_data,
- },
-};
-
-/* HTC PLD chips */
-
-static struct resource htcpld_resources[] = {
- [0] = {
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct htcpld_chip_platform_data htcpld_chips[] = {
- [0] = {
- .addr = 0x03,
- .reset = 0x04,
- .num_gpios = 8,
- .gpio_out_base = HTCPLD_BASE(0, 0),
- .gpio_in_base = HTCPLD_BASE(4, 0),
- },
- [1] = {
- .addr = 0x04,
- .reset = 0x8e,
- .num_gpios = 8,
- .gpio_out_base = HTCPLD_BASE(1, 0),
- .gpio_in_base = HTCPLD_BASE(5, 0),
- },
- [2] = {
- .addr = 0x05,
- .reset = 0x80,
- .num_gpios = 8,
- .gpio_out_base = HTCPLD_BASE(2, 0),
- .gpio_in_base = HTCPLD_BASE(6, 0),
- .irq_base = HTCPLD_IRQ(0, 0),
- .num_irqs = 8,
- },
- [3] = {
- .addr = 0x06,
- .reset = 0x40,
- .num_gpios = 8,
- .gpio_out_base = HTCPLD_BASE(3, 0),
- .gpio_in_base = HTCPLD_BASE(7, 0),
- .irq_base = HTCPLD_IRQ(1, 0),
- .num_irqs = 8,
- },
-};
-
-static struct htcpld_core_platform_data htcpld_pfdata = {
- .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI,
- .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO,
- .i2c_adapter_id = 1,
-
- .chip = htcpld_chips,
- .num_chip = ARRAY_SIZE(htcpld_chips),
-};
-
-static struct platform_device htcpld_device = {
- .name = "i2c-htcpld",
- .id = -1,
- .resource = htcpld_resources,
- .num_resources = ARRAY_SIZE(htcpld_resources),
- .dev = {
- .platform_data = &htcpld_pfdata,
- },
-};
-
-/* USB Device */
-static struct omap_usb_config htcherald_usb_config __initdata = {
- .otg = 0,
- .register_host = 0,
- .register_dev = 1,
- .hmc_mode = 4,
- .pins[0] = 2,
-};
-
-/* LCD Device resources */
-static const struct omap_lcd_config htcherald_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-
-static struct platform_device lcd_device = {
- .name = "lcd_htcherald",
- .id = -1,
-};
-
-/* MMC Card */
-#if IS_ENABLED(CONFIG_MMC_OMAP)
-static struct omap_mmc_platform_data htc_mmc1_data = {
- .nr_slots = 1,
- .switch_slot = NULL,
- .slots[0] = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .name = "mmcblk",
- .nomux = 1,
- .wires = 4,
- .switch_pin = -1,
- },
-};
-
-static struct omap_mmc_platform_data *htc_mmc_data[1];
-#endif
-
-
-/* Platform devices for the Herald */
-static struct platform_device *devices[] __initdata = {
- &kp_device,
- &lcd_device,
- &htcpld_device,
- &gpio_leds_device,
- &herald_gpiokeys_device,
-};
-
-/*
- * Touchscreen
- */
-static const struct ads7846_platform_data htcherald_ts_platform_data = {
- .model = 7846,
- .keep_vref_on = 1,
- .x_plate_ohms = 496,
- .gpio_pendown = HTCHERALD_GPIO_TS,
- .pressure_max = 10000,
- .pressure_min = 5000,
- .x_min = 528,
- .x_max = 3760,
- .y_min = 624,
- .y_max = 3760,
-};
-
-static struct spi_board_info __initdata htcherald_spi_board_info[] = {
- {
- .modalias = "ads7846",
- .platform_data = &htcherald_ts_platform_data,
- .max_speed_hz = 2500000,
- .bus_num = 2,
- .chip_select = 1,
- }
-};
-
-/*
- * Init functions from here on
- */
-
-static void __init htcherald_lcd_init(void)
-{
- u32 reg;
- unsigned int tries = 200;
-
- /* disable controller if active */
- reg = omap_readl(OMAP_LCDC_CONTROL);
- if (reg & OMAP_LCDC_CTRL_LCD_EN) {
- reg &= ~OMAP_LCDC_CTRL_LCD_EN;
- omap_writel(reg, OMAP_LCDC_CONTROL);
-
- /* wait for end of frame */
- while (!(omap_readl(OMAP_LCDC_STATUS) & OMAP_LCDC_STAT_DONE)) {
- tries--;
- if (!tries)
- break;
- }
- if (!tries)
- pr_err("Timeout waiting for end of frame -- LCD may not be available\n");
-
- /* turn off DMA */
- reg = omap_readw(OMAP_DMA_LCD_CCR);
- reg &= ~(1 << 7);
- omap_writew(reg, OMAP_DMA_LCD_CCR);
-
- reg = omap_readw(OMAP_DMA_LCD_CTRL);
- reg &= ~(1 << 8);
- omap_writew(reg, OMAP_DMA_LCD_CTRL);
- }
-}
-
-static void __init htcherald_map_io(void)
-{
- omap7xx_map_io();
-
- /*
- * The LCD panel must be disabled and DMA turned off here, as doing
- * it later causes the LCD never to reinitialize.
- */
- htcherald_lcd_init();
-
- printk(KERN_INFO "htcherald_map_io done.\n");
-}
-
-static void __init htcherald_disable_watchdog(void)
-{
- /* Disable watchdog if running */
- if (omap_readl(OMAP_WDT_TIMER_MODE) & 0x8000) {
- /*
- * disable a potentially running watchdog timer before
- * it kills us.
- */
- printk(KERN_WARNING "OMAP850 Watchdog seems to be activated, disabling it for now.\n");
- omap_writel(0xF5, OMAP_WDT_TIMER_MODE);
- omap_writel(0xA0, OMAP_WDT_TIMER_MODE);
- }
-}
-
-#define HTCHERALD_GPIO_USB_EN1 33
-#define HTCHERALD_GPIO_USB_EN2 73
-#define HTCHERALD_GPIO_USB_DM 35
-#define HTCHERALD_GPIO_USB_DP 36
-
-static void __init htcherald_usb_enable(void)
-{
- unsigned int tries = 20;
- unsigned int value = 0;
-
- /* Request the GPIOs we need to control here */
- if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0)
- goto err1;
-
- if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0)
- goto err2;
-
- if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0)
- goto err3;
-
- if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0)
- goto err4;
-
- /* force USB_EN GPIO to 0 */
- do {
- /* output low */
- gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0);
- } while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 &&
- --tries);
-
- if (value == 1)
- printk(KERN_WARNING "Unable to reset USB, trying to continue\n");
-
- gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */
- gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */
- gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */
-
- goto done;
-
-err4:
- gpio_free(HTCHERALD_GPIO_USB_DM);
-err3:
- gpio_free(HTCHERALD_GPIO_USB_EN2);
-err2:
- gpio_free(HTCHERALD_GPIO_USB_EN1);
-err1:
- printk(KERN_ERR "Unabled to request GPIO for USB\n");
-done:
- printk(KERN_INFO "USB setup complete.\n");
-}
-
-static void __init htcherald_init(void)
-{
- printk(KERN_INFO "HTC Herald init.\n");
-
- /* Do board initialization before we register all the devices */
- htcpld_resources[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
- htcpld_resources[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- htcherald_disable_watchdog();
-
- htcherald_usb_enable();
- omap1_usb_init(&htcherald_usb_config);
-
- htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS);
- spi_register_board_info(htcherald_spi_board_info,
- ARRAY_SIZE(htcherald_spi_board_info));
-
- omap_register_i2c_bus(1, 100, NULL, 0);
-
-#if IS_ENABLED(CONFIG_MMC_OMAP)
- htc_mmc_data[0] = &htc_mmc1_data;
- omap1_init_mmc(htc_mmc_data, 1);
-#endif
-
- omapfb_set_lcd_config(&htcherald_lcd_config);
-}
-
-MACHINE_START(HERALD, "HTC Herald")
- /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */
- /* Maintainer: wing-linux.sourceforge.net */
- .atag_offset = 0x100,
- .map_io = htcherald_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = htcherald_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
deleted file mode 100644
index f169e172421d..000000000000
--- a/arch/arm/mach-omap1/board-innovator.c
+++ /dev/null
@@ -1,483 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-innovator.c
- *
- * Board specific inits for OMAP-1510 and OMAP-1610 Innovator
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/smc91x.h>
-#include <linux/omapfb.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/mux.h>
-#include "flash.h"
-#include <mach/tc.h>
-#include <linux/platform_data/keypad-omap.h>
-
-#include <mach/hardware.h>
-#include "usb.h"
-
-#include "iomap.h"
-#include "common.h"
-#include "mmc.h"
-
-/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
-#define INNOVATOR1610_ETHR_START 0x04000300
-
-static const unsigned int innovator_keymap[] = {
- KEY(0, 0, KEY_F1),
- KEY(3, 0, KEY_DOWN),
- KEY(1, 1, KEY_F2),
- KEY(2, 1, KEY_RIGHT),
- KEY(0, 2, KEY_F3),
- KEY(1, 2, KEY_F4),
- KEY(2, 2, KEY_UP),
- KEY(2, 3, KEY_ENTER),
- KEY(3, 3, KEY_LEFT),
-};
-
-static struct mtd_partition innovator_partitions[] = {
- /* bootloader (U-Boot, etc) in first sector */
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next sector */
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = 0,
- },
- /* kernel */
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0
- },
- /* rest of flash1 is a file system */
- {
- .name = "rootfs",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_16M - SZ_2M - 2 * SZ_128K,
- .mask_flags = 0
- },
- /* file system */
- {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data innovator_flash_data = {
- .width = 2,
- .set_vpp = omap1_set_vpp,
- .parts = innovator_partitions,
- .nr_parts = ARRAY_SIZE(innovator_partitions),
-};
-
-static struct resource innovator_flash_resource = {
- .start = OMAP_CS0_PHYS,
- .end = OMAP_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device innovator_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &innovator_flash_data,
- },
- .num_resources = 1,
- .resource = &innovator_flash_resource,
-};
-
-static struct resource innovator_kp_resources[] = {
- [0] = {
- .start = INT_KEYBOARD,
- .end = INT_KEYBOARD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct matrix_keymap_data innovator_keymap_data = {
- .keymap = innovator_keymap,
- .keymap_size = ARRAY_SIZE(innovator_keymap),
-};
-
-static struct omap_kp_platform_data innovator_kp_data = {
- .rows = 8,
- .cols = 8,
- .keymap_data = &innovator_keymap_data,
- .delay = 4,
-};
-
-static struct platform_device innovator_kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &innovator_kp_data,
- },
- .num_resources = ARRAY_SIZE(innovator_kp_resources),
- .resource = innovator_kp_resources,
-};
-
-static struct smc91x_platdata innovator_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-#ifdef CONFIG_ARCH_OMAP15XX
-
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-
-
-/* Only FPGA needs to be mapped here. All others are done with ioremap */
-static struct map_desc innovator1510_io_desc[] __initdata = {
- {
- .virtual = OMAP1510_FPGA_BASE,
- .pfn = __phys_to_pfn(OMAP1510_FPGA_START),
- .length = OMAP1510_FPGA_SIZE,
- .type = MT_DEVICE
- }
-};
-
-static struct resource innovator1510_smc91x_resources[] = {
- [0] = {
- .start = OMAP1510_FPGA_ETHR_START, /* Physical */
- .end = OMAP1510_FPGA_ETHR_START + 0xf,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = OMAP1510_INT_ETHER,
- .end = OMAP1510_INT_ETHER,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct platform_device innovator1510_smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &innovator_smc91x_info,
- },
- .num_resources = ARRAY_SIZE(innovator1510_smc91x_resources),
- .resource = innovator1510_smc91x_resources,
-};
-
-static struct platform_device innovator1510_lcd_device = {
- .name = "lcd_inn1510",
- .id = -1,
- .dev = {
- .platform_data = (void __force *)OMAP1510_FPGA_LCD_PANEL_CONTROL,
- }
-};
-
-static struct platform_device innovator1510_spi_device = {
- .name = "spi_inn1510",
- .id = -1,
-};
-
-static struct platform_device *innovator1510_devices[] __initdata = {
- &innovator_flash_device,
- &innovator1510_smc91x_device,
- &innovator_kp_device,
- &innovator1510_lcd_device,
- &innovator1510_spi_device,
-};
-
-static int innovator_get_pendown_state(void)
-{
- return !(__raw_readb(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
-}
-
-static const struct ads7846_platform_data innovator1510_ts_info = {
- .model = 7846,
- .vref_delay_usecs = 100, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .get_pendown_state = innovator_get_pendown_state,
-};
-
-static struct spi_board_info __initdata innovator1510_boardinfo[] = { {
- /* FPGA (bus "10") CS0 has an ads7846e */
- .modalias = "ads7846",
- .platform_data = &innovator1510_ts_info,
- .irq = OMAP1510_INT_FPGA_TS,
- .max_speed_hz = 120000 /* max sample rate at 3V */
- * 26 /* command + data + overhead */,
- .bus_num = 10,
- .chip_select = 0,
-} };
-
-#endif /* CONFIG_ARCH_OMAP15XX */
-
-#ifdef CONFIG_ARCH_OMAP16XX
-
-static struct resource innovator1610_smc91x_resources[] = {
- [0] = {
- .start = INNOVATOR1610_ETHR_START, /* Physical */
- .end = INNOVATOR1610_ETHR_START + 0xf,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device innovator1610_smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &innovator_smc91x_info,
- },
- .num_resources = ARRAY_SIZE(innovator1610_smc91x_resources),
- .resource = innovator1610_smc91x_resources,
-};
-
-static struct platform_device innovator1610_lcd_device = {
- .name = "inn1610_lcd",
- .id = -1,
-};
-
-static struct platform_device *innovator1610_devices[] __initdata = {
- &innovator_flash_device,
- &innovator1610_smc91x_device,
- &innovator_kp_device,
- &innovator1610_lcd_device,
-};
-
-#endif /* CONFIG_ARCH_OMAP16XX */
-
-static void __init innovator_init_smc91x(void)
-{
- if (cpu_is_omap1510()) {
- __raw_writeb(__raw_readb(OMAP1510_FPGA_RST) & ~1,
- OMAP1510_FPGA_RST);
- udelay(750);
- } else {
- if (gpio_request(0, "SMC91x irq") < 0) {
- printk("Error requesting gpio 0 for smc91x irq\n");
- return;
- }
- }
-}
-
-#ifdef CONFIG_ARCH_OMAP15XX
-/*
- * Board specific gang-switched transceiver power on/off.
- */
-static int innovator_omap_ohci_transceiver_power(int on)
-{
- if (on)
- __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL)
- | ((1 << 5/*usb1*/) | (1 << 3/*usb2*/)),
- INNOVATOR_FPGA_CAM_USB_CONTROL);
- else
- __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL)
- & ~((1 << 5/*usb1*/) | (1 << 3/*usb2*/)),
- INNOVATOR_FPGA_CAM_USB_CONTROL);
-
- return 0;
-}
-
-static struct omap_usb_config innovator1510_usb_config __initdata = {
- /* for bundled non-standard host and peripheral cables */
- .hmc_mode = 4,
-
- .register_host = 1,
- .pins[1] = 6,
- .pins[2] = 6, /* Conflicts with UART2 */
-
- .register_dev = 1,
- .pins[0] = 2,
-
- .transceiver_power = innovator_omap_ohci_transceiver_power,
-};
-
-static const struct omap_lcd_config innovator1510_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP16XX
-static struct omap_usb_config h2_usb_config __initdata = {
- /* usb1 has a Mini-AB port and external isp1301 transceiver */
- .otg = 2,
-
-#if IS_ENABLED(CONFIG_USB_OMAP)
- .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
- /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
-#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
- /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
- .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
-#endif
-
- .pins[1] = 3,
-};
-
-static const struct omap_lcd_config innovator1610_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_OMAP)
-
-static int mmc_set_power(struct device *dev, int slot, int power_on,
- int vdd)
-{
- if (power_on)
- __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) | (1 << 3),
- OMAP1510_FPGA_POWER);
- else
- __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) & ~(1 << 3),
- OMAP1510_FPGA_POWER);
-
- return 0;
-}
-
-/*
- * Innovator could use the following functions tested:
- * - mmc_get_wp that uses OMAP_MPUIO(3)
- * - mmc_get_cover_state that uses FPGA F4 UIO43
- */
-static struct omap_mmc_platform_data mmc1_data = {
- .nr_slots = 1,
- .slots[0] = {
- .set_power = mmc_set_power,
- .wires = 4,
- .name = "mmcblk",
- },
-};
-
-static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC];
-
-static void __init innovator_mmc_init(void)
-{
- mmc_data[0] = &mmc1_data;
- omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC);
-}
-
-#else
-static inline void innovator_mmc_init(void)
-{
-}
-#endif
-
-static void __init innovator_init(void)
-{
- if (cpu_is_omap1510())
- omap1510_fpga_init_irq();
- innovator_init_smc91x();
-
-#ifdef CONFIG_ARCH_OMAP15XX
- if (cpu_is_omap1510()) {
- unsigned char reg;
-
- /* mux pins for uarts */
- omap_cfg_reg(UART1_TX);
- omap_cfg_reg(UART1_RTS);
- omap_cfg_reg(UART2_TX);
- omap_cfg_reg(UART2_RTS);
- omap_cfg_reg(UART3_TX);
- omap_cfg_reg(UART3_RX);
-
- reg = __raw_readb(OMAP1510_FPGA_POWER);
- reg |= OMAP1510_FPGA_PCR_COM1_EN;
- __raw_writeb(reg, OMAP1510_FPGA_POWER);
- udelay(10);
-
- reg = __raw_readb(OMAP1510_FPGA_POWER);
- reg |= OMAP1510_FPGA_PCR_COM2_EN;
- __raw_writeb(reg, OMAP1510_FPGA_POWER);
- udelay(10);
-
- platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
- spi_register_board_info(innovator1510_boardinfo,
- ARRAY_SIZE(innovator1510_boardinfo));
- }
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
- if (!cpu_is_omap1510()) {
- innovator1610_smc91x_resources[1].start = gpio_to_irq(0);
- innovator1610_smc91x_resources[1].end = gpio_to_irq(0);
- platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices));
- }
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
- if (cpu_is_omap1510()) {
- omap1_usb_init(&innovator1510_usb_config);
- omapfb_set_lcd_config(&innovator1510_lcd_config);
- }
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
- if (cpu_is_omap1610()) {
- omap1_usb_init(&h2_usb_config);
- omapfb_set_lcd_config(&innovator1610_lcd_config);
- }
-#endif
- omap_serial_init();
- omap_register_i2c_bus(1, 100, NULL, 0);
- innovator_mmc_init();
-}
-
-/*
- * REVISIT: Assume 15xx for now, we don't want to do revision check
- * until later on. The right way to fix this is to set up a different
- * machine_id for 16xx Innovator, or use device tree.
- */
-static void __init innovator_map_io(void)
-{
-#ifdef CONFIG_ARCH_OMAP15XX
- omap15xx_map_io();
-
- iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
- udelay(10); /* Delay needed for FPGA */
-
- /* Dump the Innovator FPGA rev early - useful info for support. */
- pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n",
- __raw_readb(OMAP1510_FPGA_REV_HIGH),
- __raw_readb(OMAP1510_FPGA_REV_LOW),
- __raw_readb(OMAP1510_FPGA_BOARD_REV));
-#endif
-}
-
-MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
- /* Maintainer: MontaVista Software, Inc. */
- .atag_offset = 0x100,
- .map_io = innovator_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = innovator_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nand.c b/arch/arm/mach-omap1/board-nand.c
deleted file mode 100644
index 479ab9be784d..000000000000
--- a/arch/arm/mach-omap1/board-nand.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-nand.c
- *
- * Common OMAP1 board NAND code
- *
- * Copyright (C) 2004, 2012 Texas Instruments, Inc.
- * Copyright (C) 2002 MontaVista Software, Inc.
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc.
- * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
- */
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-
-#include "common.h"
-
-void omap1_nand_cmd_ctl(struct nand_chip *this, int cmd, unsigned int ctrl)
-{
- unsigned long mask;
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- mask = (ctrl & NAND_CLE) ? 0x02 : 0;
- if (ctrl & NAND_ALE)
- mask |= 0x04;
-
- writeb(cmd, this->legacy.IO_ADDR_W + mask);
-}
-
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index e43c852103f5..a501a473ffd6 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -28,11 +28,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/mux.h>
-
-#include <mach/hardware.h>
+#include "mux.h"
+#include "hardware.h"
#include "usb.h"
-
#include "common.h"
#include "clock.h"
#include "mmc.h"
@@ -290,7 +288,7 @@ static void __init omap_nokia770_init(void)
MACHINE_START(NOKIA770, "Nokia 770")
.atag_offset = 0x100,
- .map_io = omap16xx_map_io,
+ .map_io = omap1_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 5dbc8f109aa7..df758c1f9237 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -42,18 +42,17 @@
#include <linux/mfd/tps65010.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/omap1_bl.h>
+#include <linux/soc/ti/omap1-io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include "tc.h"
#include "flash.h"
-#include <mach/mux.h>
-#include <mach/tc.h>
-
-#include <mach/hardware.h>
+#include "mux.h"
+#include "hardware.h"
#include "usb.h"
-
#include "common.h"
/* Name of the GPIO chip used by the OMAP for GPIOs 0..15 */
@@ -340,267 +339,6 @@ static struct omap_usb_config osk_usb_config __initdata = {
.pins[0] = 2,
};
-#ifdef CONFIG_OMAP_OSK_MISTRAL
-static const struct omap_lcd_config osk_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-#endif
-
-#ifdef CONFIG_OMAP_OSK_MISTRAL
-
-#include <linux/input.h>
-#include <linux/property.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-
-#include <linux/platform_data/keypad-omap.h>
-
-static const struct property_entry mistral_at24_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 16),
- { }
-};
-
-static const struct software_node mistral_at24_node = {
- .properties = mistral_at24_properties,
-};
-
-static struct i2c_board_info __initdata mistral_i2c_board_info[] = {
- {
- /* NOTE: powered from LCD supply */
- I2C_BOARD_INFO("24c04", 0x50),
- .swnode = &mistral_at24_node,
- },
- /* TODO when driver support is ready:
- * - optionally ov9640 camera sensor at 0x30
- */
-};
-
-static const unsigned int osk_keymap[] = {
- /* KEY(col, row, code) */
- KEY(0, 0, KEY_F1), /* SW4 */
- KEY(3, 0, KEY_UP), /* (sw2/up) */
- KEY(1, 1, KEY_LEFTCTRL), /* SW5 */
- KEY(2, 1, KEY_LEFT), /* (sw2/left) */
- KEY(0, 2, KEY_SPACE), /* SW3 */
- KEY(1, 2, KEY_ESC), /* SW6 */
- KEY(2, 2, KEY_DOWN), /* (sw2/down) */
- KEY(2, 3, KEY_ENTER), /* (sw2/select) */
- KEY(3, 3, KEY_RIGHT), /* (sw2/right) */
-};
-
-static const struct matrix_keymap_data osk_keymap_data = {
- .keymap = osk_keymap,
- .keymap_size = ARRAY_SIZE(osk_keymap),
-};
-
-static struct omap_kp_platform_data osk_kp_data = {
- .rows = 8,
- .cols = 8,
- .keymap_data = &osk_keymap_data,
- .delay = 9,
-};
-
-static struct resource osk5912_kp_resources[] = {
- [0] = {
- .start = INT_KEYBOARD,
- .end = INT_KEYBOARD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device osk5912_kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &osk_kp_data,
- },
- .num_resources = ARRAY_SIZE(osk5912_kp_resources),
- .resource = osk5912_kp_resources,
-};
-
-static struct omap_backlight_config mistral_bl_data = {
- .default_intensity = 0xa0,
-};
-
-static struct platform_device mistral_bl_device = {
- .name = "omap-bl",
- .id = -1,
- .dev = {
- .platform_data = &mistral_bl_data,
- },
-};
-
-static struct platform_device osk5912_lcd_device = {
- .name = "lcd_osk",
- .id = -1,
-};
-
-static const struct gpio_led mistral_gpio_led_pins[] = {
- {
- .name = "mistral:red",
- .default_trigger = "heartbeat",
- .gpio = 3,
- },
- {
- .name = "mistral:green",
- .default_trigger = "cpu0",
- .gpio = OMAP_MPUIO(4),
- },
-};
-
-static struct gpio_led_platform_data mistral_gpio_led_data = {
- .leds = mistral_gpio_led_pins,
- .num_leds = ARRAY_SIZE(mistral_gpio_led_pins),
-};
-
-static struct platform_device mistral_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mistral_gpio_led_data,
- },
-};
-
-static struct platform_device *mistral_devices[] __initdata = {
- &osk5912_kp_device,
- &mistral_bl_device,
- &osk5912_lcd_device,
- &mistral_gpio_leds,
-};
-
-static int mistral_get_pendown_state(void)
-{
- return !gpio_get_value(4);
-}
-
-static const struct ads7846_platform_data mistral_ts_info = {
- .model = 7846,
- .vref_delay_usecs = 100, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .get_pendown_state = mistral_get_pendown_state,
-};
-
-static struct spi_board_info __initdata mistral_boardinfo[] = { {
- /* MicroWire (bus 2) CS0 has an ads7846e */
- .modalias = "ads7846",
- .platform_data = &mistral_ts_info,
- .max_speed_hz = 120000 /* max sample rate at 3V */
- * 26 /* command + data + overhead */,
- .bus_num = 2,
- .chip_select = 0,
-} };
-
-static irqreturn_t
-osk_mistral_wake_interrupt(int irq, void *ignored)
-{
- return IRQ_HANDLED;
-}
-
-static void __init osk_mistral_init(void)
-{
- /* NOTE: we could actually tell if there's a Mistral board
- * attached, e.g. by trying to read something from the ads7846.
- * But this arch_init() code is too early for that, since we
- * can't talk to the ads or even the i2c eeprom.
- */
-
- /* parallel camera interface */
- omap_cfg_reg(J15_1610_CAM_LCLK);
- omap_cfg_reg(J18_1610_CAM_D7);
- omap_cfg_reg(J19_1610_CAM_D6);
- omap_cfg_reg(J14_1610_CAM_D5);
- omap_cfg_reg(K18_1610_CAM_D4);
- omap_cfg_reg(K19_1610_CAM_D3);
- omap_cfg_reg(K15_1610_CAM_D2);
- omap_cfg_reg(K14_1610_CAM_D1);
- omap_cfg_reg(L19_1610_CAM_D0);
- omap_cfg_reg(L18_1610_CAM_VS);
- omap_cfg_reg(L15_1610_CAM_HS);
- omap_cfg_reg(M19_1610_CAM_RSTZ);
- omap_cfg_reg(Y15_1610_CAM_OUTCLK);
-
- /* serial camera interface */
- omap_cfg_reg(H19_1610_CAM_EXCLK);
- omap_cfg_reg(W13_1610_CCP_CLKM);
- omap_cfg_reg(Y12_1610_CCP_CLKP);
- /* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */
- /* omap_cfg_reg(Y14_1610_CCP_DATAM); */
- omap_cfg_reg(W14_1610_CCP_DATAP);
-
- /* CAM_PWDN */
- if (gpio_request(11, "cam_pwdn") == 0) {
- omap_cfg_reg(N20_1610_GPIO11);
- gpio_direction_output(11, 0);
- } else
- pr_debug("OSK+Mistral: CAM_PWDN is awol\n");
-
-
- /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */
- gpio_request(6, "ts_busy");
- gpio_direction_input(6);
-
- omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
- gpio_request(4, "ts_int");
- gpio_direction_input(4);
- irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
-
- mistral_boardinfo[0].irq = gpio_to_irq(4);
- spi_register_board_info(mistral_boardinfo,
- ARRAY_SIZE(mistral_boardinfo));
-
- /* the sideways button (SW1) is for use as a "wakeup" button
- *
- * NOTE: The Mistral board has the wakeup button (SW1) wired
- * to the LCD 3.3V rail, which is powered down during suspend.
- * To allow this button to wake up the omap, work around this
- * HW bug by rewiring SW1 to use the main 3.3V rail.
- */
- omap_cfg_reg(N15_1610_MPUIO2);
- if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) {
- int ret = 0;
- int irq = gpio_to_irq(OMAP_MPUIO(2));
-
- gpio_direction_input(OMAP_MPUIO(2));
- irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
- /* share the IRQ in case someone wants to use the
- * button for more than wakeup from system sleep.
- */
- ret = request_irq(irq,
- &osk_mistral_wake_interrupt,
- IRQF_SHARED, "mistral_wakeup",
- &osk_mistral_wake_interrupt);
- if (ret != 0) {
- gpio_free(OMAP_MPUIO(2));
- printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n",
- ret);
- } else
- enable_irq_wake(irq);
- } else
- printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");
-
- /* LCD: backlight, and power; power controls other devices on the
- * board, like the touchscreen, EEPROM, and wakeup (!) switch.
- */
- omap_cfg_reg(PWL);
- if (gpio_request(2, "lcd_pwr") == 0)
- gpio_direction_output(2, 1);
-
- /*
- * GPIO based LEDs
- */
- omap_cfg_reg(P18_1610_GPIO3);
- omap_cfg_reg(MPUIO4);
-
- i2c_register_board_info(1, mistral_i2c_board_info,
- ARRAY_SIZE(mistral_i2c_board_info));
-
- platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices));
-}
-#else
-static void __init osk_mistral_init(void) { }
-#endif
-
#define EMIFS_CS3_VAL (0x88013141)
static void __init osk_init(void)
@@ -643,18 +381,12 @@ static void __init osk_init(void)
osk_i2c_board_info[0].irq = gpio_to_irq(OMAP_MPUIO(1));
omap_register_i2c_bus(1, 400, osk_i2c_board_info,
ARRAY_SIZE(osk_i2c_board_info));
- osk_mistral_init();
-
-#ifdef CONFIG_OMAP_OSK_MISTRAL
- omapfb_set_lcd_config(&osk_lcd_config);
-#endif
-
}
MACHINE_START(OMAP_OSK, "TI-OSK")
/* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
.atag_offset = 0x100,
- .map_io = omap16xx_map_io,
+ .map_io = omap1_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 4ac981c5cf74..f79c497f04d5 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -25,21 +25,19 @@
#include <linux/interrupt.h>
#include <linux/apm-emulation.h>
#include <linux/omapfb.h>
+#include <linux/omap-dma.h>
+#include <linux/platform_data/keypad-omap.h>
#include <linux/platform_data/omap1_bl.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include "tc.h"
#include "flash.h"
-#include <mach/mux.h>
-#include <mach/tc.h>
-#include <linux/omap-dma.h>
-#include <linux/platform_data/keypad-omap.h>
-
-#include <mach/hardware.h>
+#include "mux.h"
+#include "hardware.h"
#include "usb.h"
-
#include "mmc.h"
#include "common.h"
@@ -258,7 +256,7 @@ static void __init omap_palmte_init(void)
MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
.atag_offset = 0x100,
- .map_io = omap15xx_map_io,
+ .map_io = omap1_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
deleted file mode 100644
index e48ae5fbe1b1..000000000000
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ /dev/null
@@ -1,287 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-palmtt.c
- *
- * Modified from board-palmtt2.c
- *
- * Modified and amended for Palm Tungsten|T
- * by Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/notifier.h>
-#include <linux/clk.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/leds.h>
-#include <linux/omapfb.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/platform_data/omap1_bl.h>
-#include <linux/platform_data/leds-omap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "flash.h"
-#include <mach/mux.h>
-#include <linux/omap-dma.h>
-#include <mach/tc.h>
-#include <linux/platform_data/keypad-omap.h>
-
-#include <mach/hardware.h>
-#include "usb.h"
-
-#include "common.h"
-
-#define PALMTT_USBDETECT_GPIO 0
-#define PALMTT_CABLE_GPIO 1
-#define PALMTT_LED_GPIO 3
-#define PALMTT_PENIRQ_GPIO 6
-#define PALMTT_MMC_WP_GPIO 8
-#define PALMTT_HDQ_GPIO 11
-
-static const unsigned int palmtt_keymap[] = {
- KEY(0, 0, KEY_ESC),
- KEY(1, 0, KEY_SPACE),
- KEY(2, 0, KEY_LEFTCTRL),
- KEY(3, 0, KEY_TAB),
- KEY(4, 0, KEY_ENTER),
- KEY(0, 1, KEY_LEFT),
- KEY(1, 1, KEY_DOWN),
- KEY(2, 1, KEY_UP),
- KEY(3, 1, KEY_RIGHT),
- KEY(0, 2, KEY_SLEEP),
- KEY(4, 2, KEY_Y),
-};
-
-static struct mtd_partition palmtt_partitions[] = {
- {
- .name = "write8k",
- .offset = 0,
- .size = SZ_8K,
- .mask_flags = 0,
- },
- {
- .name = "PalmOS-BootLoader(ro)",
- .offset = SZ_8K,
- .size = 7 * SZ_8K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = 8 * SZ_8K,
- .mask_flags = 0,
- },
- {
- .name = "PalmOS-FS(ro)",
- .offset = MTDPART_OFS_APPEND,
- .size = 7 * SZ_1M + 4 * SZ_64K - 16 * SZ_8K,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "u-boot(rez)",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = 0
- },
- {
- .name = "empty",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data palmtt_flash_data = {
- .width = 2,
- .set_vpp = omap1_set_vpp,
- .parts = palmtt_partitions,
- .nr_parts = ARRAY_SIZE(palmtt_partitions),
-};
-
-static struct resource palmtt_flash_resource = {
- .start = OMAP_CS0_PHYS,
- .end = OMAP_CS0_PHYS + SZ_8M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device palmtt_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &palmtt_flash_data,
- },
- .num_resources = 1,
- .resource = &palmtt_flash_resource,
-};
-
-static struct resource palmtt_kp_resources[] = {
- [0] = {
- .start = INT_KEYBOARD,
- .end = INT_KEYBOARD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct matrix_keymap_data palmtt_keymap_data = {
- .keymap = palmtt_keymap,
- .keymap_size = ARRAY_SIZE(palmtt_keymap),
-};
-
-static struct omap_kp_platform_data palmtt_kp_data = {
- .rows = 6,
- .cols = 3,
- .keymap_data = &palmtt_keymap_data,
-};
-
-static struct platform_device palmtt_kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &palmtt_kp_data,
- },
- .num_resources = ARRAY_SIZE(palmtt_kp_resources),
- .resource = palmtt_kp_resources,
-};
-
-static struct platform_device palmtt_lcd_device = {
- .name = "lcd_palmtt",
- .id = -1,
-};
-
-static struct platform_device palmtt_spi_device = {
- .name = "spi_palmtt",
- .id = -1,
-};
-
-static struct omap_backlight_config palmtt_backlight_config = {
- .default_intensity = 0xa0,
-};
-
-static struct platform_device palmtt_backlight_device = {
- .name = "omap-bl",
- .id = -1,
- .dev = {
- .platform_data= &palmtt_backlight_config,
- },
-};
-
-static struct omap_led_config palmtt_led_config[] = {
- {
- .cdev = {
- .name = "palmtt:led0",
- },
- .gpio = PALMTT_LED_GPIO,
- },
-};
-
-static struct omap_led_platform_data palmtt_led_data = {
- .nr_leds = ARRAY_SIZE(palmtt_led_config),
- .leds = palmtt_led_config,
-};
-
-static struct platform_device palmtt_led_device = {
- .name = "omap-led",
- .id = -1,
- .dev = {
- .platform_data = &palmtt_led_data,
- },
-};
-
-static struct platform_device *palmtt_devices[] __initdata = {
- &palmtt_flash_device,
- &palmtt_kp_device,
- &palmtt_lcd_device,
- &palmtt_spi_device,
- &palmtt_backlight_device,
- &palmtt_led_device,
-};
-
-static int palmtt_get_pendown_state(void)
-{
- return !gpio_get_value(6);
-}
-
-static const struct ads7846_platform_data palmtt_ts_info = {
- .model = 7846,
- .vref_delay_usecs = 100, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .get_pendown_state = palmtt_get_pendown_state,
-};
-
-static struct spi_board_info __initdata palmtt_boardinfo[] = {
- {
- /* MicroWire (bus 2) CS0 has an ads7846e */
- .modalias = "ads7846",
- .platform_data = &palmtt_ts_info,
- .max_speed_hz = 120000 /* max sample rate at 3V */
- * 26 /* command + data + overhead */,
- .bus_num = 2,
- .chip_select = 0,
- }
-};
-
-static struct omap_usb_config palmtt_usb_config __initdata = {
- .register_dev = 1,
- .hmc_mode = 0,
- .pins[0] = 2,
-};
-
-static const struct omap_lcd_config palmtt_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-
-static void __init omap_mpu_wdt_mode(int mode) {
- if (mode)
- omap_writew(0x8000, OMAP_WDT_TIMER_MODE);
- else {
- omap_writew(0x00f5, OMAP_WDT_TIMER_MODE);
- omap_writew(0x00a0, OMAP_WDT_TIMER_MODE);
- }
-}
-
-static void __init omap_palmtt_init(void)
-{
- /* mux pins for uarts */
- omap_cfg_reg(UART1_TX);
- omap_cfg_reg(UART1_RTS);
- omap_cfg_reg(UART2_TX);
- omap_cfg_reg(UART2_RTS);
- omap_cfg_reg(UART3_TX);
- omap_cfg_reg(UART3_RX);
-
- omap_mpu_wdt_mode(0);
-
- platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
-
- palmtt_boardinfo[0].irq = gpio_to_irq(6);
- spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
- omap_serial_init();
- omap1_usb_init(&palmtt_usb_config);
- omap_register_i2c_bus(1, 100, NULL, 0);
-
- omapfb_set_lcd_config(&palmtt_lcd_config);
-}
-
-MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
- .atag_offset = 0x100,
- .map_io = omap15xx_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = omap_palmtt_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
deleted file mode 100644
index 37db0ab31528..000000000000
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ /dev/null
@@ -1,302 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-palmz71.c
- *
- * Modified from board-generic.c
- *
- * Support for the Palm Zire71 PDA.
- *
- * Original version : Laurent Gonzalez
- *
- * Modified for zire71 : Marek Vasut
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/notifier.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/omapfb.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/platform_data/omap1_bl.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "flash.h"
-#include <mach/mux.h>
-#include <linux/omap-dma.h>
-#include <mach/tc.h>
-#include <linux/platform_data/keypad-omap.h>
-
-#include <mach/hardware.h>
-#include "usb.h"
-
-#include "common.h"
-
-#define PALMZ71_USBDETECT_GPIO 0
-#define PALMZ71_PENIRQ_GPIO 6
-#define PALMZ71_MMC_WP_GPIO 8
-#define PALMZ71_HDQ_GPIO 11
-
-#define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1)
-#define PALMZ71_CABLE_GPIO OMAP_MPUIO(2)
-#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3)
-#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4)
-
-static const unsigned int palmz71_keymap[] = {
- KEY(0, 0, KEY_F1),
- KEY(1, 0, KEY_F2),
- KEY(2, 0, KEY_F3),
- KEY(3, 0, KEY_F4),
- KEY(4, 0, KEY_POWER),
- KEY(0, 1, KEY_LEFT),
- KEY(1, 1, KEY_DOWN),
- KEY(2, 1, KEY_UP),
- KEY(3, 1, KEY_RIGHT),
- KEY(4, 1, KEY_ENTER),
- KEY(0, 2, KEY_CAMERA),
-};
-
-static const struct matrix_keymap_data palmz71_keymap_data = {
- .keymap = palmz71_keymap,
- .keymap_size = ARRAY_SIZE(palmz71_keymap),
-};
-
-static struct omap_kp_platform_data palmz71_kp_data = {
- .rows = 8,
- .cols = 8,
- .keymap_data = &palmz71_keymap_data,
- .rep = true,
- .delay = 80,
-};
-
-static struct resource palmz71_kp_resources[] = {
- [0] = {
- .start = INT_KEYBOARD,
- .end = INT_KEYBOARD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device palmz71_kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &palmz71_kp_data,
- },
- .num_resources = ARRAY_SIZE(palmz71_kp_resources),
- .resource = palmz71_kp_resources,
-};
-
-static struct mtd_partition palmz71_rom_partitions[] = {
- /* PalmOS "Small ROM", contains the bootloader and the debugger */
- {
- .name = "smallrom",
- .offset = 0,
- .size = 0xa000,
- .mask_flags = MTD_WRITEABLE,
- },
- /* PalmOS "Big ROM", a filesystem with all the OS code and data */
- {
- .name = "bigrom",
- .offset = SZ_128K,
- /*
- * 0x5f0000 bytes big in the multi-language ("EFIGS") version,
- * 0x7b0000 bytes in the English-only ("enUS") version.
- */
- .size = 0x7b0000,
- .mask_flags = MTD_WRITEABLE,
- },
-};
-
-static struct physmap_flash_data palmz71_rom_data = {
- .width = 2,
- .set_vpp = omap1_set_vpp,
- .parts = palmz71_rom_partitions,
- .nr_parts = ARRAY_SIZE(palmz71_rom_partitions),
-};
-
-static struct resource palmz71_rom_resource = {
- .start = OMAP_CS0_PHYS,
- .end = OMAP_CS0_PHYS + SZ_8M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device palmz71_rom_device = {
- .name = "physmap-flash",
- .id = -1,
- .dev = {
- .platform_data = &palmz71_rom_data,
- },
- .num_resources = 1,
- .resource = &palmz71_rom_resource,
-};
-
-static struct platform_device palmz71_lcd_device = {
- .name = "lcd_palmz71",
- .id = -1,
-};
-
-static struct platform_device palmz71_spi_device = {
- .name = "spi_palmz71",
- .id = -1,
-};
-
-static struct omap_backlight_config palmz71_backlight_config = {
- .default_intensity = 0xa0,
-};
-
-static struct platform_device palmz71_backlight_device = {
- .name = "omap-bl",
- .id = -1,
- .dev = {
- .platform_data = &palmz71_backlight_config,
- },
-};
-
-static struct platform_device *devices[] __initdata = {
- &palmz71_rom_device,
- &palmz71_kp_device,
- &palmz71_lcd_device,
- &palmz71_spi_device,
- &palmz71_backlight_device,
-};
-
-static int
-palmz71_get_pendown_state(void)
-{
- return !gpio_get_value(PALMZ71_PENIRQ_GPIO);
-}
-
-static const struct ads7846_platform_data palmz71_ts_info = {
- .model = 7846,
- .vref_delay_usecs = 100, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .get_pendown_state = palmz71_get_pendown_state,
-};
-
-static struct spi_board_info __initdata palmz71_boardinfo[] = { {
- /* MicroWire (bus 2) CS0 has an ads7846e */
- .modalias = "ads7846",
- .platform_data = &palmz71_ts_info,
- .max_speed_hz = 120000 /* max sample rate at 3V */
- * 26 /* command + data + overhead */,
- .bus_num = 2,
- .chip_select = 0,
-} };
-
-static struct omap_usb_config palmz71_usb_config __initdata = {
- .register_dev = 1, /* Mini-B only receptacle */
- .hmc_mode = 0,
- .pins[0] = 2,
-};
-
-static const struct omap_lcd_config palmz71_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-
-static irqreturn_t
-palmz71_powercable(int irq, void *dev_id)
-{
- if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) {
- printk(KERN_INFO "PM: Power cable connected\n");
- irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
- IRQ_TYPE_EDGE_FALLING);
- } else {
- printk(KERN_INFO "PM: Power cable disconnected\n");
- irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
- IRQ_TYPE_EDGE_RISING);
- }
- return IRQ_HANDLED;
-}
-
-static void __init
-omap_mpu_wdt_mode(int mode)
-{
- if (mode)
- omap_writew(0x8000, OMAP_WDT_TIMER_MODE);
- else {
- omap_writew(0x00f5, OMAP_WDT_TIMER_MODE);
- omap_writew(0x00a0, OMAP_WDT_TIMER_MODE);
- }
-}
-
-static void __init
-palmz71_gpio_setup(int early)
-{
- if (early) {
- /* Only set GPIO1 so we have a working serial */
- gpio_direction_output(1, 1);
- } else {
- /* Set MMC/SD host WP pin as input */
- if (gpio_request(PALMZ71_MMC_WP_GPIO, "MMC WP") < 0) {
- printk(KERN_ERR "Could not reserve WP GPIO!\n");
- return;
- }
- gpio_direction_input(PALMZ71_MMC_WP_GPIO);
-
- /* Monitor the Power-cable-connected signal */
- if (gpio_request(PALMZ71_USBDETECT_GPIO, "USB detect") < 0) {
- printk(KERN_ERR
- "Could not reserve cable signal GPIO!\n");
- return;
- }
- gpio_direction_input(PALMZ71_USBDETECT_GPIO);
- if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
- palmz71_powercable, 0, "palmz71-cable", NULL))
- printk(KERN_ERR
- "IRQ request for power cable failed!\n");
- palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL);
- }
-}
-
-static void __init
-omap_palmz71_init(void)
-{
- /* mux pins for uarts */
- omap_cfg_reg(UART1_TX);
- omap_cfg_reg(UART1_RTS);
- omap_cfg_reg(UART2_TX);
- omap_cfg_reg(UART2_RTS);
- omap_cfg_reg(UART3_TX);
- omap_cfg_reg(UART3_RX);
-
- palmz71_gpio_setup(1);
- omap_mpu_wdt_mode(0);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO);
- spi_register_board_info(palmz71_boardinfo,
- ARRAY_SIZE(palmz71_boardinfo));
- omap1_usb_init(&palmz71_usb_config);
- omap_serial_init();
- omap_register_i2c_bus(1, 100, NULL, 0);
- palmz71_gpio_setup(0);
-
- omapfb_set_lcd_config(&palmz71_lcd_config);
-}
-
-MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
- .atag_offset = 0x100,
- .map_io = omap15xx_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = omap_palmz71_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
deleted file mode 100644
index da0155107d85..000000000000
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ /dev/null
@@ -1,334 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/board-perseus2.c
- *
- * Modified from board-generic.c
- *
- * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
- * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/platnand.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/smc91x.h>
-#include <linux/omapfb.h>
-#include <linux/platform_data/keypad-omap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/tc.h>
-#include <mach/mux.h>
-#include "flash.h"
-
-#include <mach/hardware.h>
-
-#include "iomap.h"
-#include "common.h"
-#include "fpga.h"
-
-static const unsigned int p2_keymap[] = {
- KEY(0, 0, KEY_UP),
- KEY(1, 0, KEY_RIGHT),
- KEY(2, 0, KEY_LEFT),
- KEY(3, 0, KEY_DOWN),
- KEY(4, 0, KEY_ENTER),
- KEY(0, 1, KEY_F10),
- KEY(1, 1, KEY_SEND),
- KEY(2, 1, KEY_END),
- KEY(3, 1, KEY_VOLUMEDOWN),
- KEY(4, 1, KEY_VOLUMEUP),
- KEY(5, 1, KEY_RECORD),
- KEY(0, 2, KEY_F9),
- KEY(1, 2, KEY_3),
- KEY(2, 2, KEY_6),
- KEY(3, 2, KEY_9),
- KEY(4, 2, KEY_KPDOT),
- KEY(0, 3, KEY_BACK),
- KEY(1, 3, KEY_2),
- KEY(2, 3, KEY_5),
- KEY(3, 3, KEY_8),
- KEY(4, 3, KEY_0),
- KEY(5, 3, KEY_KPSLASH),
- KEY(0, 4, KEY_HOME),
- KEY(1, 4, KEY_1),
- KEY(2, 4, KEY_4),
- KEY(3, 4, KEY_7),
- KEY(4, 4, KEY_KPASTERISK),
- KEY(5, 4, KEY_POWER),
-};
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
- .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = INT_7XX_MPU_EXT_NIRQ,
- .end = 0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct mtd_partition nor_partitions[] = {
- /* bootloader (U-Boot, etc) in first sector */
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* bootloader params in the next sector */
- {
- .name = "params",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = 0,
- },
- /* kernel */
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_2M,
- .mask_flags = 0
- },
- /* rest of flash is a file system */
- {
- .name = "rootfs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- },
-};
-
-static struct physmap_flash_data nor_data = {
- .width = 2,
- .set_vpp = omap1_set_vpp,
- .parts = nor_partitions,
- .nr_parts = ARRAY_SIZE(nor_partitions),
-};
-
-static struct resource nor_resource = {
- .start = OMAP_CS0_PHYS,
- .end = OMAP_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device nor_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &nor_data,
- },
- .num_resources = 1,
- .resource = &nor_resource,
-};
-
-#define P2_NAND_RB_GPIO_PIN 62
-
-static int nand_dev_ready(struct nand_chip *chip)
-{
- return gpio_get_value(P2_NAND_RB_GPIO_PIN);
-}
-
-static struct platform_nand_data nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_offset = 0,
- .options = NAND_SAMSUNG_LP_OPTIONS,
- },
- .ctrl = {
- .cmd_ctrl = omap1_nand_cmd_ctl,
- .dev_ready = nand_dev_ready,
- },
-};
-
-static struct resource nand_resource = {
- .start = OMAP_CS3_PHYS,
- .end = OMAP_CS3_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device nand_device = {
- .name = "gen_nand",
- .id = 0,
- .dev = {
- .platform_data = &nand_data,
- },
- .num_resources = 1,
- .resource = &nand_resource,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .dev = {
- .platform_data = &smc91x_info,
- },
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static struct resource kp_resources[] = {
- [0] = {
- .start = INT_7XX_MPUIO_KEYPAD,
- .end = INT_7XX_MPUIO_KEYPAD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const struct matrix_keymap_data p2_keymap_data = {
- .keymap = p2_keymap,
- .keymap_size = ARRAY_SIZE(p2_keymap),
-};
-
-static struct omap_kp_platform_data kp_data = {
- .rows = 8,
- .cols = 8,
- .keymap_data = &p2_keymap_data,
- .delay = 4,
- .dbounce = true,
-};
-
-static struct platform_device kp_device = {
- .name = "omap-keypad",
- .id = -1,
- .dev = {
- .platform_data = &kp_data,
- },
- .num_resources = ARRAY_SIZE(kp_resources),
- .resource = kp_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
- &nor_device,
- &nand_device,
- &smc91x_device,
- &kp_device,
-};
-
-static const struct omap_lcd_config perseus2_lcd_config __initconst = {
- .ctrl_name = "internal",
-};
-
-static void __init perseus2_init_smc91x(void)
-{
- __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
- __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
- H2P2_DBG_FPGA_LAN_RESET);
- mdelay(50);
-}
-
-static void __init omap_perseus2_init(void)
-{
- /* Early, board-dependent init */
-
- /*
- * Hold GSM Reset until needed
- */
- omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
-
- /*
- * UARTs -> done automagically by 8250 driver
- */
-
- /*
- * CSx timings, GPIO Mux ... setup
- */
-
- /* Flash: CS0 timings setup */
- omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
- omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
-
- /*
- * Ethernet support through the debug board
- * CS1 timings setup
- */
- omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
- omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
-
- /*
- * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
- * It is used as the Ethernet controller interrupt
- */
- omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
- OMAP7XX_IO_CONF_9);
-
- perseus2_init_smc91x();
-
- BUG_ON(gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0);
- gpio_direction_input(P2_NAND_RB_GPIO_PIN);
-
- omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
- omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
-
- /* Mux pins for keypad */
- omap_cfg_reg(E2_7XX_KBR0);
- omap_cfg_reg(J7_7XX_KBR1);
- omap_cfg_reg(E1_7XX_KBR2);
- omap_cfg_reg(F3_7XX_KBR3);
- omap_cfg_reg(D2_7XX_KBR4);
- omap_cfg_reg(C2_7XX_KBC0);
- omap_cfg_reg(D3_7XX_KBC1);
- omap_cfg_reg(E4_7XX_KBC2);
- omap_cfg_reg(F4_7XX_KBC3);
- omap_cfg_reg(E3_7XX_KBC4);
-
- if (IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)) {
- /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
- int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
- omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
- }
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- omap_serial_init();
- omap_register_i2c_bus(1, 100, NULL, 0);
-
- omapfb_set_lcd_config(&perseus2_lcd_config);
-}
-
-/* Only FPGA needs to be mapped here. All others are done with ioremap */
-static struct map_desc omap_perseus2_io_desc[] __initdata = {
- {
- .virtual = H2P2_DBG_FPGA_BASE,
- .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
- .length = H2P2_DBG_FPGA_SIZE,
- .type = MT_DEVICE
- }
-};
-
-static void __init omap_perseus2_map_io(void)
-{
- omap7xx_map_io();
- iotable_init(omap_perseus2_io_desc,
- ARRAY_SIZE(omap_perseus2_io_desc));
-}
-
-MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
- /* Maintainer: Kevin Hilman <kjh@hilman.org> */
- .atag_offset = 0x100,
- .map_io = omap_perseus2_map_io,
- .init_early = omap1_init_early,
- .init_irq = omap1_init_irq,
- .handle_irq = omap1_handle_irq,
- .init_machine = omap_perseus2_init,
- .init_late = omap1_init_late,
- .init_time = omap1_timer_init,
- .restart = omap1_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index 6192b1da75cb..f1c160924dfe 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -12,9 +12,8 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
-#include <mach/hardware.h>
+#include "hardware.h"
#include "board-sx1.h"
-
#include "mmc.h"
#if IS_ENABLED(CONFIG_MMC_OMAP)
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0965b1b689ec..0c0cdd5e77c7 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -26,20 +26,18 @@
#include <linux/export.h>
#include <linux/omapfb.h>
#include <linux/platform_data/keypad-omap.h>
+#include <linux/omap-dma.h>
+#include "tc.h"
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "flash.h"
-#include <mach/mux.h>
-#include <linux/omap-dma.h>
-#include <mach/tc.h>
+#include "mux.h"
#include "board-sx1.h"
-
-#include <mach/hardware.h>
+#include "hardware.h"
#include "usb.h"
-
#include "common.h"
/* Write to I2C device */
@@ -337,7 +335,7 @@ static void __init omap_sx1_init(void)
MACHINE_START(SX1, "OMAP310 based Siemens SX1")
.atag_offset = 0x100,
- .map_io = omap15xx_map_io,
+ .map_io = omap1_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
diff --git a/arch/arm/mach-omap1/board-sx1.h b/arch/arm/mach-omap1/board-sx1.h
index 355adbdaae33..fafe54a2e444 100644
--- a/arch/arm/mach-omap1/board-sx1.h
+++ b/arch/arm/mach-omap1/board-sx1.h
@@ -1,15 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Siemens SX1 board definitions
*
* Copyright: Vovan888 at gmail com
- *
- * This package is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 9d4a0ab50a46..83381e23fab9 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -16,11 +16,13 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/soc/ti/omap1-io.h>
+#include <linux/spinlock.h>
#include <asm/mach-types.h>
-#include <mach/hardware.h>
-
+#include "hardware.h"
#include "soc.h"
#include "iomap.h"
#include "clock.h"
@@ -28,33 +30,37 @@
#include "sram.h"
__u32 arm_idlect1_mask;
-struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
+/* provide direct internal access (not via clk API) to some clocks */
+struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clockfw_lock);
+/* protect registeres shared among clk_enable/disable() and clk_set_rate() operations */
+static DEFINE_SPINLOCK(arm_ckctl_lock);
+static DEFINE_SPINLOCK(arm_idlect2_lock);
+static DEFINE_SPINLOCK(mod_conf_ctrl_0_lock);
+static DEFINE_SPINLOCK(mod_conf_ctrl_1_lock);
+static DEFINE_SPINLOCK(swd_clk_div_ctrl_sel_lock);
/*
* Omap1 specific clock functions
*/
-unsigned long omap1_uart_recalc(struct clk *clk)
+unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate)
{
unsigned int val = __raw_readl(clk->enable_reg);
- return val & clk->enable_bit ? 48000000 : 12000000;
+ return val & 1 << clk->enable_bit ? 48000000 : 12000000;
}
-unsigned long omap1_sossi_recalc(struct clk *clk)
+unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate)
{
u32 div = omap_readl(MOD_CONF_CTRL_1);
div = (div >> 17) & 0x7;
div++;
- return clk->parent->rate / div;
+ return p_rate / div;
}
-static void omap1_clk_allow_idle(struct clk *clk)
+static void omap1_clk_allow_idle(struct omap1_clk *clk)
{
struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
@@ -65,7 +71,7 @@ static void omap1_clk_allow_idle(struct clk *clk)
arm_idlect1_mask |= 1 << iclk->idlect_shift;
}
-static void omap1_clk_deny_idle(struct clk *clk)
+static void omap1_clk_deny_idle(struct omap1_clk *clk)
{
struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
@@ -129,7 +135,7 @@ static __u16 verify_ckctl_value(__u16 newval)
return newval;
}
-static int calc_dsor_exp(struct clk *clk, unsigned long rate)
+static int calc_dsor_exp(unsigned long rate, unsigned long realrate)
{
/* Note: If target frequency is too low, this function will return 4,
* which is invalid value. Caller must check for this value and act
@@ -142,15 +148,11 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
* DSP_CK >= TC_CK
* DSPMMU_CK >= TC_CK
*/
- unsigned long realrate;
- struct clk * parent;
unsigned dsor_exp;
- parent = clk->parent;
- if (unlikely(parent == NULL))
+ if (unlikely(realrate == 0))
return -EIO;
- realrate = parent->rate;
for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
if (realrate <= rate)
break;
@@ -161,16 +163,50 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
return dsor_exp;
}
-unsigned long omap1_ckctl_recalc(struct clk *clk)
+unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate)
{
/* Calculate divisor encoded as 2-bit exponent */
int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
- return clk->parent->rate / dsor;
+ /* update locally maintained rate, required by arm_ck for omap1_show_rates() */
+ clk->rate = p_rate / dsor;
+ return clk->rate;
+}
+
+static int omap1_clk_is_enabled(struct clk_hw *hw)
+{
+ struct omap1_clk *clk = to_omap1_clk(hw);
+ bool api_ck_was_enabled = true;
+ __u32 regval32;
+ int ret;
+
+ if (!clk->ops) /* no gate -- always enabled */
+ return 1;
+
+ if (clk->ops == &clkops_dspck) {
+ api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw);
+ if (!api_ck_was_enabled)
+ if (api_ck_p->ops->enable(api_ck_p) < 0)
+ return 0;
+ }
+
+ if (clk->flags & ENABLE_REG_32BIT)
+ regval32 = __raw_readl(clk->enable_reg);
+ else
+ regval32 = __raw_readw(clk->enable_reg);
+
+ ret = regval32 & (1 << clk->enable_bit);
+
+ if (!api_ck_was_enabled)
+ api_ck_p->ops->disable(api_ck_p);
+
+ return ret;
}
-unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
+
+unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate)
{
+ bool api_ck_was_enabled;
int dsor;
/* Calculate divisor encoded as 2-bit exponent
@@ -180,15 +216,18 @@ unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
* Note that DSP_CKCTL virt addr = phys addr, so
* we must use __raw_readw() instead of omap_readw().
*/
- omap1_clk_enable(api_ck_p);
+ api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw);
+ if (!api_ck_was_enabled)
+ api_ck_p->ops->enable(api_ck_p);
dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
- omap1_clk_disable(api_ck_p);
+ if (!api_ck_was_enabled)
+ api_ck_p->ops->disable(api_ck_p);
- return clk->parent->rate / dsor;
+ return p_rate / dsor;
}
/* MPU virtual clock functions */
-int omap1_select_table_rate(struct clk *clk, unsigned long rate)
+int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate)
{
/* Find the highest supported frequency <= rate and switch to it */
struct mpu_rate * ptr;
@@ -223,12 +262,12 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
return 0;
}
-int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate)
{
int dsor_exp;
u16 regval;
- dsor_exp = calc_dsor_exp(clk, rate);
+ dsor_exp = calc_dsor_exp(rate, p_rate);
if (dsor_exp > 3)
dsor_exp = -EINVAL;
if (dsor_exp < 0)
@@ -238,42 +277,51 @@ int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
regval &= ~(3 << clk->rate_offset);
regval |= dsor_exp << clk->rate_offset;
__raw_writew(regval, DSP_CKCTL);
- clk->rate = clk->parent->rate / (1 << dsor_exp);
+ clk->rate = p_rate / (1 << dsor_exp);
return 0;
}
-long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate,
+ unsigned long *p_rate)
{
- int dsor_exp = calc_dsor_exp(clk, rate);
+ int dsor_exp = calc_dsor_exp(rate, *p_rate);
+
if (dsor_exp < 0)
return dsor_exp;
if (dsor_exp > 3)
dsor_exp = 3;
- return clk->parent->rate / (1 << dsor_exp);
+ return *p_rate / (1 << dsor_exp);
}
-int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate)
{
+ unsigned long flags;
int dsor_exp;
u16 regval;
- dsor_exp = calc_dsor_exp(clk, rate);
+ dsor_exp = calc_dsor_exp(rate, p_rate);
if (dsor_exp > 3)
dsor_exp = -EINVAL;
if (dsor_exp < 0)
return dsor_exp;
+ /* protect ARM_CKCTL register from concurrent access via clk_enable/disable() */
+ spin_lock_irqsave(&arm_ckctl_lock, flags);
+
regval = omap_readw(ARM_CKCTL);
regval &= ~(3 << clk->rate_offset);
regval |= dsor_exp << clk->rate_offset;
regval = verify_ckctl_value(regval);
omap_writew(regval, ARM_CKCTL);
- clk->rate = clk->parent->rate / (1 << dsor_exp);
+ clk->rate = p_rate / (1 << dsor_exp);
+
+ spin_unlock_irqrestore(&arm_ckctl_lock, flags);
+
return 0;
}
-long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
+long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate)
{
/* Find the highest supported frequency <= rate */
struct mpu_rate * ptr;
@@ -324,26 +372,40 @@ static unsigned calc_ext_dsor(unsigned long rate)
}
/* XXX Only needed on 1510 */
-int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
+long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate)
+{
+ return rate > 24000000 ? 48000000 : 12000000;
+}
+
+int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate)
{
+ unsigned long flags;
unsigned int val;
- val = __raw_readl(clk->enable_reg);
if (rate == 12000000)
- val &= ~(1 << clk->enable_bit);
+ val = 0;
else if (rate == 48000000)
- val |= (1 << clk->enable_bit);
+ val = 1 << clk->enable_bit;
else
return -EINVAL;
+
+ /* protect MOD_CONF_CTRL_0 register from concurrent access via clk_enable/disable() */
+ spin_lock_irqsave(&mod_conf_ctrl_0_lock, flags);
+
+ val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit);
__raw_writel(val, clk->enable_reg);
+
+ spin_unlock_irqrestore(&mod_conf_ctrl_0_lock, flags);
+
clk->rate = rate;
return 0;
}
/* External clock (MCLK & BCLK) functions */
-int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
+int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate)
{
+ unsigned long flags;
unsigned dsor;
__u16 ratio_bits;
@@ -354,25 +416,53 @@ int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
else
ratio_bits = (dsor - 2) << 2;
+ /* protect SWD_CLK_DIV_CTRL_SEL register from concurrent access via clk_enable/disable() */
+ spin_lock_irqsave(&swd_clk_div_ctrl_sel_lock, flags);
+
ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
__raw_writew(ratio_bits, clk->enable_reg);
+ spin_unlock_irqrestore(&swd_clk_div_ctrl_sel_lock, flags);
+
return 0;
}
-int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
+static int calc_div_sossi(unsigned long rate, unsigned long p_rate)
{
- u32 l;
int div;
- unsigned long p_rate;
- p_rate = clk->parent->rate;
/* Round towards slower frequency */
div = (p_rate + rate - 1) / rate;
- div--;
+
+ return --div;
+}
+
+long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate)
+{
+ int div;
+
+ div = calc_div_sossi(rate, *p_rate);
+ if (div < 0)
+ div = 0;
+ else if (div > 7)
+ div = 7;
+
+ return *p_rate / (div + 1);
+}
+
+int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate)
+{
+ unsigned long flags;
+ u32 l;
+ int div;
+
+ div = calc_div_sossi(rate, p_rate);
if (div < 0 || div > 7)
return -EINVAL;
+ /* protect MOD_CONF_CTRL_1 register from concurrent access via clk_enable/disable() */
+ spin_lock_irqsave(&mod_conf_ctrl_1_lock, flags);
+
l = omap_readl(MOD_CONF_CTRL_1);
l &= ~(7 << 17);
l |= div << 17;
@@ -380,15 +470,17 @@ int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
clk->rate = p_rate / (div + 1);
+ spin_unlock_irqrestore(&mod_conf_ctrl_1_lock, flags);
+
return 0;
}
-long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
+long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate)
{
return 96000000 / calc_ext_dsor(rate);
}
-void omap1_init_ext_clk(struct clk *clk)
+int omap1_init_ext_clk(struct omap1_clk *clk)
{
unsigned dsor;
__u16 ratio_bits;
@@ -404,59 +496,59 @@ void omap1_init_ext_clk(struct clk *clk)
dsor = ratio_bits + 2;
clk-> rate = 96000000 / dsor;
+
+ return 0;
}
-int omap1_clk_enable(struct clk *clk)
+static int omap1_clk_enable(struct clk_hw *hw)
{
+ struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw));
int ret = 0;
- if (clk->usecount++ == 0) {
- if (clk->parent) {
- ret = omap1_clk_enable(clk->parent);
- if (ret)
- goto err;
-
- if (clk->flags & CLOCK_NO_IDLE_PARENT)
- omap1_clk_deny_idle(clk->parent);
- }
+ if (parent && clk->flags & CLOCK_NO_IDLE_PARENT)
+ omap1_clk_deny_idle(parent);
+ if (clk->ops && !(WARN_ON(!clk->ops->enable)))
ret = clk->ops->enable(clk);
- if (ret) {
- if (clk->parent)
- omap1_clk_disable(clk->parent);
- goto err;
- }
- }
- return ret;
-err:
- clk->usecount--;
return ret;
}
-void omap1_clk_disable(struct clk *clk)
+static void omap1_clk_disable(struct clk_hw *hw)
{
- if (clk->usecount > 0 && !(--clk->usecount)) {
+ struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw));
+
+ if (clk->ops && !(WARN_ON(!clk->ops->disable)))
clk->ops->disable(clk);
- if (likely(clk->parent)) {
- omap1_clk_disable(clk->parent);
- if (clk->flags & CLOCK_NO_IDLE_PARENT)
- omap1_clk_allow_idle(clk->parent);
- }
- }
+
+ if (likely(parent) && clk->flags & CLOCK_NO_IDLE_PARENT)
+ omap1_clk_allow_idle(parent);
}
-static int omap1_clk_enable_generic(struct clk *clk)
+static int omap1_clk_enable_generic(struct omap1_clk *clk)
{
+ unsigned long flags;
__u16 regval16;
__u32 regval32;
if (unlikely(clk->enable_reg == NULL)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
- clk->name);
+ clk_hw_get_name(&clk->hw));
return -EINVAL;
}
+ /* protect clk->enable_reg from concurrent access via clk_set_rate() */
+ if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL))
+ spin_lock_irqsave(&arm_ckctl_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2))
+ spin_lock_irqsave(&arm_idlect2_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0))
+ spin_lock_irqsave(&mod_conf_ctrl_0_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1))
+ spin_lock_irqsave(&mod_conf_ctrl_1_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL))
+ spin_lock_irqsave(&swd_clk_div_ctrl_sel_lock, flags);
+
if (clk->flags & ENABLE_REG_32BIT) {
regval32 = __raw_readl(clk->enable_reg);
regval32 |= (1 << clk->enable_bit);
@@ -467,17 +559,41 @@ static int omap1_clk_enable_generic(struct clk *clk)
__raw_writew(regval16, clk->enable_reg);
}
+ if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL))
+ spin_unlock_irqrestore(&arm_ckctl_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2))
+ spin_unlock_irqrestore(&arm_idlect2_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0))
+ spin_unlock_irqrestore(&mod_conf_ctrl_0_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1))
+ spin_unlock_irqrestore(&mod_conf_ctrl_1_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL))
+ spin_unlock_irqrestore(&swd_clk_div_ctrl_sel_lock, flags);
+
return 0;
}
-static void omap1_clk_disable_generic(struct clk *clk)
+static void omap1_clk_disable_generic(struct omap1_clk *clk)
{
+ unsigned long flags;
__u16 regval16;
__u32 regval32;
if (clk->enable_reg == NULL)
return;
+ /* protect clk->enable_reg from concurrent access via clk_set_rate() */
+ if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL))
+ spin_lock_irqsave(&arm_ckctl_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2))
+ spin_lock_irqsave(&arm_idlect2_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0))
+ spin_lock_irqsave(&mod_conf_ctrl_0_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1))
+ spin_lock_irqsave(&mod_conf_ctrl_1_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL))
+ spin_lock_irqsave(&swd_clk_div_ctrl_sel_lock, flags);
+
if (clk->flags & ENABLE_REG_32BIT) {
regval32 = __raw_readl(clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit);
@@ -487,6 +603,17 @@ static void omap1_clk_disable_generic(struct clk *clk)
regval16 &= ~(1 << clk->enable_bit);
__raw_writew(regval16, clk->enable_reg);
}
+
+ if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL))
+ spin_unlock_irqrestore(&arm_ckctl_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2))
+ spin_unlock_irqrestore(&arm_idlect2_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0))
+ spin_unlock_irqrestore(&mod_conf_ctrl_0_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1))
+ spin_unlock_irqrestore(&mod_conf_ctrl_1_lock, flags);
+ else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL))
+ spin_unlock_irqrestore(&swd_clk_div_ctrl_sel_lock, flags);
}
const struct clkops clkops_generic = {
@@ -494,25 +621,38 @@ const struct clkops clkops_generic = {
.disable = omap1_clk_disable_generic,
};
-static int omap1_clk_enable_dsp_domain(struct clk *clk)
+static int omap1_clk_enable_dsp_domain(struct omap1_clk *clk)
{
- int retval;
+ bool api_ck_was_enabled;
+ int retval = 0;
+
+ api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw);
+ if (!api_ck_was_enabled)
+ retval = api_ck_p->ops->enable(api_ck_p);
- retval = omap1_clk_enable(api_ck_p);
if (!retval) {
retval = omap1_clk_enable_generic(clk);
- omap1_clk_disable(api_ck_p);
+
+ if (!api_ck_was_enabled)
+ api_ck_p->ops->disable(api_ck_p);
}
return retval;
}
-static void omap1_clk_disable_dsp_domain(struct clk *clk)
+static void omap1_clk_disable_dsp_domain(struct omap1_clk *clk)
{
- if (omap1_clk_enable(api_ck_p) == 0) {
- omap1_clk_disable_generic(clk);
- omap1_clk_disable(api_ck_p);
- }
+ bool api_ck_was_enabled;
+
+ api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw);
+ if (!api_ck_was_enabled)
+ if (api_ck_p->ops->enable(api_ck_p) < 0)
+ return;
+
+ omap1_clk_disable_generic(clk);
+
+ if (!api_ck_was_enabled)
+ api_ck_p->ops->disable(api_ck_p);
}
const struct clkops clkops_dspck = {
@@ -521,7 +661,7 @@ const struct clkops clkops_dspck = {
};
/* XXX SYSC register handling does not belong in the clock framework */
-static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
+static int omap1_clk_enable_uart_functional_16xx(struct omap1_clk *clk)
{
int ret;
struct uart_clk *uclk;
@@ -538,7 +678,7 @@ static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
}
/* XXX SYSC register handling does not belong in the clock framework */
-static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
+static void omap1_clk_disable_uart_functional_16xx(struct omap1_clk *clk)
{
struct uart_clk *uclk;
@@ -555,20 +695,33 @@ const struct clkops clkops_uart_16xx = {
.disable = omap1_clk_disable_uart_functional_16xx,
};
-long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long omap1_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
{
- if (clk->round_rate != NULL)
- return clk->round_rate(clk, rate);
+ struct omap1_clk *clk = to_omap1_clk(hw);
+
+ if (clk->recalc)
+ return clk->recalc(clk, p_rate);
return clk->rate;
}
-int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
+static long omap1_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *p_rate)
+{
+ struct omap1_clk *clk = to_omap1_clk(hw);
+
+ if (clk->round_rate != NULL)
+ return clk->round_rate(clk, rate, p_rate);
+
+ return omap1_clk_recalc_rate(hw, *p_rate);
+}
+
+static int omap1_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
{
+ struct omap1_clk *clk = to_omap1_clk(hw);
int ret = -EINVAL;
if (clk->set_rate)
- ret = clk->set_rate(clk, rate);
+ ret = clk->set_rate(clk, rate, p_rate);
return ret;
}
@@ -576,340 +729,105 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
* Omap1 clock reset and init functions
*/
+static int omap1_clk_init_op(struct clk_hw *hw)
+{
+ struct omap1_clk *clk = to_omap1_clk(hw);
+
+ if (clk->init)
+ return clk->init(clk);
+
+ return 0;
+}
+
#ifdef CONFIG_OMAP_RESET_CLOCKS
-void omap1_clk_disable_unused(struct clk *clk)
+static void omap1_clk_disable_unused(struct clk_hw *hw)
{
- __u32 regval32;
+ struct omap1_clk *clk = to_omap1_clk(hw);
+ const char *name = clk_hw_get_name(hw);
/* Clocks in the DSP domain need api_ck. Just assume bootloader
* has not enabled any DSP clocks */
if (clk->enable_reg == DSP_IDLECT2) {
- pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
- clk->name);
+ pr_info("Skipping reset check for DSP domain clock \"%s\"\n", name);
return;
}
- /* Is the clock already disabled? */
- if (clk->flags & ENABLE_REG_32BIT)
- regval32 = __raw_readl(clk->enable_reg);
- else
- regval32 = __raw_readw(clk->enable_reg);
-
- if ((regval32 & (1 << clk->enable_bit)) == 0)
- return;
-
- printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
- clk->ops->disable(clk);
+ pr_info("Disabling unused clock \"%s\"... ", name);
+ omap1_clk_disable(hw);
printk(" done\n");
}
#endif
+const struct clk_ops omap1_clk_gate_ops = {
+ .enable = omap1_clk_enable,
+ .disable = omap1_clk_disable,
+ .is_enabled = omap1_clk_is_enabled,
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+ .disable_unused = omap1_clk_disable_unused,
+#endif
+};
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
- int ret;
-
- if (IS_ERR_OR_NULL(clk))
- return -EINVAL;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- ret = omap1_clk_enable(clk);
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- if (IS_ERR_OR_NULL(clk))
- return;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- if (clk->usecount == 0) {
- pr_err("Trying disable clock %s with 0 usecount\n",
- clk->name);
- WARN_ON(1);
- goto out;
- }
-
- omap1_clk_disable(clk);
-
-out:
- spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long flags;
- unsigned long ret;
-
- if (IS_ERR_OR_NULL(clk))
- return 0;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- ret = clk->rate;
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/*
- * Optional clock functions defined in include/linux/clk.h
- */
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- long ret;
-
- if (IS_ERR_OR_NULL(clk))
- return 0;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- ret = omap1_clk_round_rate(clk, rate);
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- int ret = -EINVAL;
-
- if (IS_ERR_OR_NULL(clk))
- return ret;
-
- spin_lock_irqsave(&clockfw_lock, flags);
- ret = omap1_clk_set_rate(clk, rate);
- if (ret == 0)
- propagate_rate(clk);
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n");
-
- return -EINVAL;
-}
-EXPORT_SYMBOL(clk_set_parent);
+const struct clk_ops omap1_clk_rate_ops = {
+ .recalc_rate = omap1_clk_recalc_rate,
+ .round_rate = omap1_clk_round_rate,
+ .set_rate = omap1_clk_set_rate,
+ .init = omap1_clk_init_op,
+};
-struct clk *clk_get_parent(struct clk *clk)
-{
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
+const struct clk_ops omap1_clk_full_ops = {
+ .enable = omap1_clk_enable,
+ .disable = omap1_clk_disable,
+ .is_enabled = omap1_clk_is_enabled,
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+ .disable_unused = omap1_clk_disable_unused,
+#endif
+ .recalc_rate = omap1_clk_recalc_rate,
+ .round_rate = omap1_clk_round_rate,
+ .set_rate = omap1_clk_set_rate,
+ .init = omap1_clk_init_op,
+};
/*
* OMAP specific clock functions shared between omap1 and omap2
*/
/* Used for clocks that always have same value as the parent clock */
-unsigned long followparent_recalc(struct clk *clk)
+unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate)
{
- return clk->parent->rate;
+ return p_rate;
}
/*
* Used for clocks that have the same value as the parent clock,
* divided by some factor
*/
-unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate)
{
WARN_ON(!clk->fixed_div);
- return clk->parent->rate / clk->fixed_div;
-}
-
-void clk_reparent(struct clk *child, struct clk *parent)
-{
- list_del_init(&child->sibling);
- if (parent)
- list_add(&child->sibling, &parent->children);
- child->parent = parent;
-
- /* now do the debugfs renaming to reattach the child
- to the proper parent */
+ return p_rate / clk->fixed_div;
}
/* Propagate rate to children */
-void propagate_rate(struct clk *tclk)
-{
- struct clk *clkp;
-
- list_for_each_entry(clkp, &tclk->children, sibling) {
- if (clkp->recalc)
- clkp->rate = clkp->recalc(clkp);
- propagate_rate(clkp);
- }
-}
-
-static LIST_HEAD(root_clks);
-
-/**
- * recalculate_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- * Called at init.
- */
-void recalculate_root_clocks(void)
+void propagate_rate(struct omap1_clk *tclk)
{
struct clk *clkp;
- list_for_each_entry(clkp, &root_clks, sibling) {
- if (clkp->recalc)
- clkp->rate = clkp->recalc(clkp);
- propagate_rate(clkp);
- }
-}
-
-/**
- * clk_preinit - initialize any fields in the struct clk before clk init
- * @clk: struct clk * to initialize
- *
- * Initialize any struct clk fields needed before normal clk initialization
- * can run. No return value.
- */
-void clk_preinit(struct clk *clk)
-{
- INIT_LIST_HEAD(&clk->children);
-}
-
-int clk_register(struct clk *clk)
-{
- if (IS_ERR_OR_NULL(clk))
- return -EINVAL;
-
- /*
- * trap out already registered clocks
- */
- if (clk->node.next || clk->node.prev)
- return 0;
-
- mutex_lock(&clocks_mutex);
- if (clk->parent)
- list_add(&clk->sibling, &clk->parent->children);
- else
- list_add(&clk->sibling, &root_clks);
-
- list_add(&clk->node, &clocks);
- if (clk->init)
- clk->init(clk);
- mutex_unlock(&clocks_mutex);
-
- return 0;
-}
-EXPORT_SYMBOL(clk_register);
-
-void clk_unregister(struct clk *clk)
-{
- if (IS_ERR_OR_NULL(clk))
+ /* depend on CCF ability to recalculate new rates across whole clock subtree */
+ if (WARN_ON(!(clk_hw_get_flags(&tclk->hw) & CLK_GET_RATE_NOCACHE)))
return;
- mutex_lock(&clocks_mutex);
- list_del(&clk->sibling);
- list_del(&clk->node);
- mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unregister);
-
-void clk_enable_init_clocks(void)
-{
- struct clk *clkp;
-
- list_for_each_entry(clkp, &clocks, node)
- if (clkp->flags & ENABLE_ON_INIT)
- clk_enable(clkp);
-}
-
-/**
- * omap_clk_get_by_name - locate OMAP struct clk by its name
- * @name: name of the struct clk to locate
- *
- * Locate an OMAP struct clk by its name. Assumes that struct clk
- * names are unique. Returns NULL if not found or a pointer to the
- * struct clk if found.
- */
-struct clk *omap_clk_get_by_name(const char *name)
-{
- struct clk *c;
- struct clk *ret = NULL;
-
- mutex_lock(&clocks_mutex);
-
- list_for_each_entry(c, &clocks, node) {
- if (!strcmp(c->name, name)) {
- ret = c;
- break;
- }
- }
-
- mutex_unlock(&clocks_mutex);
-
- return ret;
-}
-
-int omap_clk_enable_autoidle_all(void)
-{
- struct clk *c;
- unsigned long flags;
-
- spin_lock_irqsave(&clockfw_lock, flags);
-
- list_for_each_entry(c, &clocks, node)
- if (c->ops->allow_idle)
- c->ops->allow_idle(c);
-
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return 0;
-}
-
-int omap_clk_disable_autoidle_all(void)
-{
- struct clk *c;
- unsigned long flags;
-
- spin_lock_irqsave(&clockfw_lock, flags);
-
- list_for_each_entry(c, &clocks, node)
- if (c->ops->deny_idle)
- c->ops->deny_idle(c);
-
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return 0;
-}
-
-/*
- * Low level helpers
- */
-static int clkll_enable_null(struct clk *clk)
-{
- return 0;
-}
+ clkp = clk_get_sys(NULL, clk_hw_get_name(&tclk->hw));
+ if (WARN_ON(!clkp))
+ return;
-static void clkll_disable_null(struct clk *clk)
-{
+ clk_get_rate(clkp);
+ clk_put(clkp);
}
-const struct clkops clkops_null = {
- .enable = clkll_enable_null,
- .disable = clkll_disable_null,
+const struct clk_ops omap1_clk_null_ops = {
};
/*
@@ -917,115 +835,6 @@ const struct clkops clkops_null = {
*
* Used for clock aliases that are needed on some OMAPs, but not others
*/
-struct clk dummy_ck = {
- .name = "dummy",
- .ops = &clkops_null,
+struct omap1_clk dummy_ck __refdata = {
+ .hw.init = CLK_HW_INIT_NO_PARENT("dummy", &omap1_clk_null_ops, 0),
};
-
-/*
- *
- */
-
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-/*
- * Disable any unused clocks left on by the bootloader
- */
-static int __init clk_disable_unused(void)
-{
- struct clk *ck;
- unsigned long flags;
-
- pr_info("clock: disabling unused clocks to save power\n");
-
- spin_lock_irqsave(&clockfw_lock, flags);
- list_for_each_entry(ck, &clocks, node) {
- if (ck->ops == &clkops_null)
- continue;
-
- if (ck->usecount > 0 || !ck->enable_reg)
- continue;
-
- omap1_clk_disable_unused(ck);
- }
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
- return 0;
-}
-late_initcall(clk_disable_unused);
-late_initcall(omap_clk_enable_autoidle_all);
-#endif
-
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-/*
- * debugfs support to trace clock tree hierarchy and attributes
- */
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-static struct dentry *clk_debugfs_root;
-
-static int debug_clock_show(struct seq_file *s, void *unused)
-{
- struct clk *c;
- struct clk *pa;
-
- mutex_lock(&clocks_mutex);
- seq_printf(s, "%-30s %-30s %-10s %s\n",
- "clock-name", "parent-name", "rate", "use-count");
-
- list_for_each_entry(c, &clocks, node) {
- pa = c->parent;
- seq_printf(s, "%-30s %-30s %-10lu %d\n",
- c->name, pa ? pa->name : "none", c->rate,
- c->usecount);
- }
- mutex_unlock(&clocks_mutex);
-
- return 0;
-}
-
-DEFINE_SHOW_ATTRIBUTE(debug_clock);
-
-static void clk_debugfs_register_one(struct clk *c)
-{
- struct dentry *d;
- struct clk *pa = c->parent;
-
- d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
- c->dent = d;
-
- debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount);
- debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);
- debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags);
-}
-
-static void clk_debugfs_register(struct clk *c)
-{
- struct clk *pa = c->parent;
-
- if (pa && !pa->dent)
- clk_debugfs_register(pa);
-
- if (!c->dent)
- clk_debugfs_register_one(c);
-}
-
-static int __init clk_debugfs_init(void)
-{
- struct clk *c;
- struct dentry *d;
-
- d = debugfs_create_dir("clock", NULL);
- clk_debugfs_root = d;
-
- list_for_each_entry(c, &clocks, node)
- clk_debugfs_register(c);
-
- debugfs_create_file("summary", S_IRUGO, d, NULL, &debug_clock_fops);
-
- return 0;
-}
-late_initcall(clk_debugfs_init);
-
-#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index f3b8811f5ac0..16cfb2e86ee4 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -11,12 +11,11 @@
#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
#include <linux/clk.h>
-#include <linux/list.h>
-
#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
struct module;
-struct clk;
+struct omap1_clk;
struct omap_clk {
u16 cpu;
@@ -29,7 +28,7 @@ struct omap_clk {
.lk = { \
.dev_id = dev, \
.con_id = con, \
- .clk = ck, \
+ .clk_hw = ck, \
}, \
}
@@ -40,68 +39,30 @@ struct omap_clk {
#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
#define CK_1710 (1 << 4) /* 1710 extra for rate selection */
-
-/* Temporary, needed during the common clock framework conversion */
-#define __clk_get_name(clk) (clk->name)
-#define __clk_get_parent(clk) (clk->parent)
-#define __clk_get_rate(clk) (clk->rate)
-
/**
* struct clkops - some clock function pointers
* @enable: fn ptr that enables the current clock in hardware
* @disable: fn ptr that enables the current clock in hardware
- * @find_idlest: function returning the IDLEST register for the clock's IP blk
- * @find_companion: function returning the "companion" clk reg for the clock
* @allow_idle: fn ptr that enables autoidle for the current clock in hardware
- * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
- *
- * A "companion" clk is an accompanying clock to the one being queried
- * that must be enabled for the IP module connected to the clock to
- * become accessible by the hardware. Neither @find_idlest nor
- * @find_companion should be needed; that information is IP
- * block-specific; the hwmod code has been created to handle this, but
- * until hwmod data is ready and drivers have been converted to use PM
- * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
- * @find_companion must, unfortunately, remain.
*/
struct clkops {
- int (*enable)(struct clk *);
- void (*disable)(struct clk *);
- void (*find_idlest)(struct clk *, void __iomem **,
- u8 *, u8 *);
- void (*find_companion)(struct clk *, void __iomem **,
- u8 *);
- void (*allow_idle)(struct clk *);
- void (*deny_idle)(struct clk *);
+ int (*enable)(struct omap1_clk *clk);
+ void (*disable)(struct omap1_clk *clk);
};
/*
* struct clk.flags possibilities
*
* XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- * bits share the same register. This flag allows the
- * omap4_dpllmx*() code to determine which GATE_CTRL bit field
- * should be used. This is a temporary solution - a better approach
- * would be to associate clock type-specific data with the clock,
- * similar to the struct dpll_data approach.
*/
#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
#define CLOCK_IDLE_CONTROL (1 << 1)
#define CLOCK_NO_IDLE_PARENT (1 << 2)
-#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
-#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2 (1 << 5)
/**
- * struct clk - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
+ * struct omap1_clk - OMAP1 struct clk
+ * @hw: struct clk_hw for common clock framework integration
* @ops: struct clkops * for this clock
- * @name: the name of the clock in the hardware (used in hwmod data and debug)
- * @parent: pointer to this clock's parent struct clk
- * @children: list_head connecting to the child clks' @sibling list_heads
- * @sibling: list_head connecting this clk to its parent clk's @children
* @rate: current clock rate
* @enable_reg: register to write to enable the clock (see @enable_bit)
* @recalc: fn ptr that returns the clock's current rate
@@ -109,123 +70,65 @@ struct clkops {
* @round_rate: fn ptr that can round the clock's current rate
* @init: fn ptr to do clock-specific initialization
* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @usecount: number of users that have requested this clock to be enabled
* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
* @flags: see "struct clk.flags possibilities" above
* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- * XXX @usecount is poorly named. It should be "enable_count" or
- * something similar. "users" in the description refers to kernel
- * code (core code or drivers) that have called clk_enable() and not
- * yet called clk_disable(); the usecount of parent clocks is also
- * incremented by the clock code when clk_enable() is called on child
- * clocks and decremented by the clock code when clk_disable() is
- * called on child clocks.
- *
- * XXX @clkdm, @usecount, @children, @sibling should be marked for
- * internal use only.
- *
- * @children and @sibling are used to optimize parent-to-child clock
- * tree traversals. (child-to-parent traversals use @parent.)
- *
- * XXX The notion of the clock's current rate probably needs to be
- * separated from the clock's target rate.
*/
-struct clk {
- struct list_head node;
+struct omap1_clk {
+ struct clk_hw hw;
const struct clkops *ops;
- const char *name;
- struct clk *parent;
- struct list_head children;
- struct list_head sibling; /* node for children */
unsigned long rate;
void __iomem *enable_reg;
- unsigned long (*recalc)(struct clk *);
- int (*set_rate)(struct clk *, unsigned long);
- long (*round_rate)(struct clk *, unsigned long);
- void (*init)(struct clk *);
+ unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate);
+ int (*set_rate)(struct omap1_clk *clk, unsigned long rate,
+ unsigned long p_rate);
+ long (*round_rate)(struct omap1_clk *clk, unsigned long rate,
+ unsigned long *p_rate);
+ int (*init)(struct omap1_clk *clk);
u8 enable_bit;
- s8 usecount;
u8 fixed_div;
u8 flags;
u8 rate_offset;
- u8 src_offset;
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
- struct dentry *dent; /* For visible tree hierarchy */
-#endif
-};
-
-struct clk_functions {
- int (*clk_enable)(struct clk *clk);
- void (*clk_disable)(struct clk *clk);
- long (*clk_round_rate)(struct clk *clk, unsigned long rate);
- int (*clk_set_rate)(struct clk *clk, unsigned long rate);
- int (*clk_set_parent)(struct clk *clk, struct clk *parent);
- void (*clk_allow_idle)(struct clk *clk);
- void (*clk_deny_idle)(struct clk *clk);
- void (*clk_disable_unused)(struct clk *clk);
};
+#define to_omap1_clk(_hw) container_of(_hw, struct omap1_clk, hw)
-extern int clk_init(struct clk_functions *custom_clocks);
-extern void clk_preinit(struct clk *clk);
-extern int clk_register(struct clk *clk);
-extern void clk_reparent(struct clk *child, struct clk *parent);
-extern void clk_unregister(struct clk *clk);
-extern void propagate_rate(struct clk *clk);
-extern void recalculate_root_clocks(void);
-extern unsigned long followparent_recalc(struct clk *clk);
-extern void clk_enable_init_clocks(void);
-unsigned long omap_fixed_divisor_recalc(struct clk *clk);
-extern struct clk *omap_clk_get_by_name(const char *name);
-extern int omap_clk_enable_autoidle_all(void);
-extern int omap_clk_disable_autoidle_all(void);
+void propagate_rate(struct omap1_clk *clk);
+unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate);
+unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate);
-extern const struct clkops clkops_null;
-
-extern struct clk dummy_ck;
+extern struct omap1_clk dummy_ck;
int omap1_clk_init(void);
void omap1_clk_late_init(void);
-extern int omap1_clk_enable(struct clk *clk);
-extern void omap1_clk_disable(struct clk *clk);
-extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
-extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
-extern unsigned long omap1_ckctl_recalc(struct clk *clk);
-extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
-extern unsigned long omap1_sossi_recalc(struct clk *clk);
-extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
-extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
-extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
-extern unsigned long omap1_uart_recalc(struct clk *clk);
-extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
-extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
-extern void omap1_init_ext_clk(struct clk *clk);
-extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
-extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
-extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
-extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
-extern unsigned long omap1_watchdog_recalc(struct clk *clk);
-
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-extern void omap1_clk_disable_unused(struct clk *clk);
-#else
-#define omap1_clk_disable_unused NULL
-#endif
+unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate);
+long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
+int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
+unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate);
+unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate);
+int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate,
+ unsigned long p_rate);
+long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
+int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
+unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate);
+int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
+long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
+int omap1_init_ext_clk(struct omap1_clk *clk);
+int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
+long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
+int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
+long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate,
+ unsigned long *p_rate);
struct uart_clk {
- struct clk clk;
- unsigned long sysc_addr;
+ struct omap1_clk clk;
+ unsigned long sysc_addr;
};
/* Provide a method for preventing idling some ARM IDLECT clocks */
struct arm_idlect1_clk {
- struct clk clk;
- unsigned long no_idle_count;
- __u8 idlect_shift;
+ struct omap1_clk clk;
+ unsigned long no_idle_count;
+ __u8 idlect_shift;
};
/* ARM_CKCTL bit shifts */
@@ -275,14 +178,18 @@ struct arm_idlect1_clk {
#define SOFT_REQ_REG2 0xfffe0880
extern __u32 arm_idlect1_mask;
-extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
+extern struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
extern const struct clkops clkops_dspck;
-extern const struct clkops clkops_dummy;
extern const struct clkops clkops_uart_16xx;
extern const struct clkops clkops_generic;
/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
extern u32 cpu_mask;
+extern const struct clk_ops omap1_clk_null_ops;
+extern const struct clk_ops omap1_clk_gate_ops;
+extern const struct clk_ops omap1_clk_rate_ops;
+extern const struct clk_ops omap1_clk_full_ops;
+
#endif
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index ef46c5f67cf9..c58d200e4816 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -14,16 +14,17 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
+#include <linux/soc/ti/omap1-io.h>
#include <asm/mach-types.h> /* for machine_is_* */
#include "soc.h"
-
-#include <mach/hardware.h>
+#include "hardware.h"
#include "usb.h" /* for OTG_BASE */
-
#include "iomap.h"
#include "clock.h"
#include "sram.h"
@@ -72,16 +73,18 @@
* Omap1 clocks
*/
-static struct clk ck_ref = {
- .name = "ck_ref",
- .ops = &clkops_null,
+static struct omap1_clk ck_ref = {
+ .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
.rate = 12000000,
};
-static struct clk ck_dpll1 = {
- .name = "ck_dpll1",
- .ops = &clkops_null,
- .parent = &ck_ref,
+static struct omap1_clk ck_dpll1 = {
+ .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
+ /*
+ * force recursive refresh of rates of the clock
+ * and its children when clk_get_rate() is called
+ */
+ CLK_GET_RATE_NOCACHE),
};
/*
@@ -90,33 +93,28 @@ static struct clk ck_dpll1 = {
*/
static struct arm_idlect1_clk ck_dpll1out = {
.clk = {
- .name = "ck_dpll1out",
+ .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
.ops = &clkops_generic,
- .parent = &ck_dpll1,
- .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
- ENABLE_ON_INIT,
+ .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_CKOUT_ARM,
- .recalc = &followparent_recalc,
},
.idlect_shift = IDL_CLKOUT_ARM_SHIFT,
};
-static struct clk sossi_ck = {
- .name = "ck_sossi",
+static struct omap1_clk sossi_ck = {
+ .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
.ops = &clkops_generic,
- .parent = &ck_dpll1out.clk,
.flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
.enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
.recalc = &omap1_sossi_recalc,
+ .round_rate = &omap1_round_sossi_rate,
.set_rate = &omap1_set_sossi_rate,
};
-static struct clk arm_ck = {
- .name = "arm_ck",
- .ops = &clkops_null,
- .parent = &ck_dpll1,
+static struct omap1_clk arm_ck = {
+ .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
.rate_offset = CKCTL_ARMDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
@@ -125,9 +123,9 @@ static struct clk arm_ck = {
static struct arm_idlect1_clk armper_ck = {
.clk = {
- .name = "armper_ck",
+ .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
+ CLK_IS_CRITICAL),
.ops = &clkops_generic,
- .parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_PERCK,
@@ -143,47 +141,41 @@ static struct arm_idlect1_clk armper_ck = {
* FIXME: This clock seems to be necessary but no-one has asked for its
* activation. [ GPIO code for 1510 ]
*/
-static struct clk arm_gpio_ck = {
- .name = "ick",
+static struct omap1_clk arm_gpio_ck = {
+ .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
.ops = &clkops_generic,
- .parent = &ck_dpll1,
- .flags = ENABLE_ON_INIT,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_GPIOCK,
- .recalc = &followparent_recalc,
};
static struct arm_idlect1_clk armxor_ck = {
.clk = {
- .name = "armxor_ck",
+ .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
+ CLK_IS_CRITICAL),
.ops = &clkops_generic,
- .parent = &ck_ref,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_XORPCK,
- .recalc = &followparent_recalc,
},
.idlect_shift = IDLXORP_ARM_SHIFT,
};
static struct arm_idlect1_clk armtim_ck = {
.clk = {
- .name = "armtim_ck",
+ .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
+ CLK_IS_CRITICAL),
.ops = &clkops_generic,
- .parent = &ck_ref,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_TIMCK,
- .recalc = &followparent_recalc,
},
.idlect_shift = IDLTIM_ARM_SHIFT,
};
static struct arm_idlect1_clk armwdt_ck = {
.clk = {
- .name = "armwdt_ck",
+ .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
.ops = &clkops_generic,
- .parent = &ck_ref,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_WDTCK,
@@ -193,11 +185,8 @@ static struct arm_idlect1_clk armwdt_ck = {
.idlect_shift = IDLWDT_ARM_SHIFT,
};
-static struct clk arminth_ck16xx = {
- .name = "arminth_ck",
- .ops = &clkops_null,
- .parent = &arm_ck,
- .recalc = &followparent_recalc,
+static struct omap1_clk arminth_ck16xx = {
+ .hw.init = CLK_HW_INIT("arminth_ck", "arm_ck", &omap1_clk_null_ops, 0),
/* Note: On 16xx the frequency can be divided by 2 by programming
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
*
@@ -205,10 +194,9 @@ static struct clk arminth_ck16xx = {
*/
};
-static struct clk dsp_ck = {
- .name = "dsp_ck",
+static struct omap1_clk dsp_ck = {
+ .hw.init = CLK_HW_INIT("dsp_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
.ops = &clkops_generic,
- .parent = &ck_dpll1,
.enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
.enable_bit = EN_DSPCK,
.rate_offset = CKCTL_DSPDIV_OFFSET,
@@ -217,20 +205,17 @@ static struct clk dsp_ck = {
.set_rate = omap1_clk_set_rate_ckctl_arm,
};
-static struct clk dspmmu_ck = {
- .name = "dspmmu_ck",
- .ops = &clkops_null,
- .parent = &ck_dpll1,
+static struct omap1_clk dspmmu_ck = {
+ .hw.init = CLK_HW_INIT("dspmmu_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
};
-static struct clk dspper_ck = {
- .name = "dspper_ck",
+static struct omap1_clk dspper_ck = {
+ .hw.init = CLK_HW_INIT("dspper_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
.ops = &clkops_dspck,
- .parent = &ck_dpll1,
.enable_reg = DSP_IDLECT2,
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
@@ -239,29 +224,23 @@ static struct clk dspper_ck = {
.set_rate = &omap1_clk_set_rate_dsp_domain,
};
-static struct clk dspxor_ck = {
- .name = "dspxor_ck",
+static struct omap1_clk dspxor_ck = {
+ .hw.init = CLK_HW_INIT("dspxor_ck", "ck_ref", &omap1_clk_gate_ops, 0),
.ops = &clkops_dspck,
- .parent = &ck_ref,
.enable_reg = DSP_IDLECT2,
.enable_bit = EN_XORPCK,
- .recalc = &followparent_recalc,
};
-static struct clk dsptim_ck = {
- .name = "dsptim_ck",
+static struct omap1_clk dsptim_ck = {
+ .hw.init = CLK_HW_INIT("dsptim_ck", "ck_ref", &omap1_clk_gate_ops, 0),
.ops = &clkops_dspck,
- .parent = &ck_ref,
.enable_reg = DSP_IDLECT2,
.enable_bit = EN_DSPTIMCK,
- .recalc = &followparent_recalc,
};
static struct arm_idlect1_clk tc_ck = {
.clk = {
- .name = "tc_ck",
- .ops = &clkops_null,
- .parent = &ck_dpll1,
+ .hw.init = CLK_HW_INIT("tc_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
.flags = CLOCK_IDLE_CONTROL,
.rate_offset = CKCTL_TCDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
@@ -271,117 +250,88 @@ static struct arm_idlect1_clk tc_ck = {
.idlect_shift = IDLIF_ARM_SHIFT,
};
-static struct clk arminth_ck1510 = {
- .name = "arminth_ck",
- .ops = &clkops_null,
- .parent = &tc_ck.clk,
- .recalc = &followparent_recalc,
+static struct omap1_clk arminth_ck1510 = {
+ .hw.init = CLK_HW_INIT("arminth_ck", "tc_ck", &omap1_clk_null_ops, 0),
/* Note: On 1510 the frequency follows TC_CK
*
* 16xx version is in MPU clocks.
*/
};
-static struct clk tipb_ck = {
+static struct omap1_clk tipb_ck = {
/* No-idle controlled by "tc_ck" */
- .name = "tipb_ck",
- .ops = &clkops_null,
- .parent = &tc_ck.clk,
- .recalc = &followparent_recalc,
+ .hw.init = CLK_HW_INIT("tipb_ck", "tc_ck", &omap1_clk_null_ops, 0),
};
-static struct clk l3_ocpi_ck = {
+static struct omap1_clk l3_ocpi_ck = {
/* No-idle controlled by "tc_ck" */
- .name = "l3_ocpi_ck",
+ .hw.init = CLK_HW_INIT("l3_ocpi_ck", "tc_ck", &omap1_clk_gate_ops, 0),
.ops = &clkops_generic,
- .parent = &tc_ck.clk,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_OCPI_CK,
- .recalc = &followparent_recalc,
};
-static struct clk tc1_ck = {
- .name = "tc1_ck",
+static struct omap1_clk tc1_ck = {
+ .hw.init = CLK_HW_INIT("tc1_ck", "tc_ck", &omap1_clk_gate_ops, 0),
.ops = &clkops_generic,
- .parent = &tc_ck.clk,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_TC1_CK,
- .recalc = &followparent_recalc,
};
/*
* FIXME: This clock seems to be necessary but no-one has asked for its
* activation. [ pm.c (SRAM), CCP, Camera ]
*/
-static struct clk tc2_ck = {
- .name = "tc2_ck",
+
+static struct omap1_clk tc2_ck = {
+ .hw.init = CLK_HW_INIT("tc2_ck", "tc_ck", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
.ops = &clkops_generic,
- .parent = &tc_ck.clk,
- .flags = ENABLE_ON_INIT,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_TC2_CK,
- .recalc = &followparent_recalc,
};
-static struct clk dma_ck = {
+static struct omap1_clk dma_ck = {
/* No-idle controlled by "tc_ck" */
- .name = "dma_ck",
- .ops = &clkops_null,
- .parent = &tc_ck.clk,
- .recalc = &followparent_recalc,
+ .hw.init = CLK_HW_INIT("dma_ck", "tc_ck", &omap1_clk_null_ops, 0),
};
-static struct clk dma_lcdfree_ck = {
- .name = "dma_lcdfree_ck",
- .ops = &clkops_null,
- .parent = &tc_ck.clk,
- .recalc = &followparent_recalc,
+static struct omap1_clk dma_lcdfree_ck = {
+ .hw.init = CLK_HW_INIT("dma_lcdfree_ck", "tc_ck", &omap1_clk_null_ops, 0),
};
static struct arm_idlect1_clk api_ck = {
.clk = {
- .name = "api_ck",
+ .hw.init = CLK_HW_INIT("api_ck", "tc_ck", &omap1_clk_gate_ops, 0),
.ops = &clkops_generic,
- .parent = &tc_ck.clk,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_APICK,
- .recalc = &followparent_recalc,
},
.idlect_shift = IDLAPI_ARM_SHIFT,
};
static struct arm_idlect1_clk lb_ck = {
.clk = {
- .name = "lb_ck",
+ .hw.init = CLK_HW_INIT("lb_ck", "tc_ck", &omap1_clk_gate_ops, 0),
.ops = &clkops_generic,
- .parent = &tc_ck.clk,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LBCK,
- .recalc = &followparent_recalc,
},
.idlect_shift = IDLLB_ARM_SHIFT,
};
-static struct clk rhea1_ck = {
- .name = "rhea1_ck",
- .ops = &clkops_null,
- .parent = &tc_ck.clk,
- .recalc = &followparent_recalc,
+static struct omap1_clk rhea1_ck = {
+ .hw.init = CLK_HW_INIT("rhea1_ck", "tc_ck", &omap1_clk_null_ops, 0),
};
-static struct clk rhea2_ck = {
- .name = "rhea2_ck",
- .ops = &clkops_null,
- .parent = &tc_ck.clk,
- .recalc = &followparent_recalc,
+static struct omap1_clk rhea2_ck = {
+ .hw.init = CLK_HW_INIT("rhea2_ck", "tc_ck", &omap1_clk_null_ops, 0),
};
-static struct clk lcd_ck_16xx = {
- .name = "lcd_ck",
+static struct omap1_clk lcd_ck_16xx = {
+ .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
.ops = &clkops_generic,
- .parent = &ck_dpll1,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
@@ -392,9 +342,8 @@ static struct clk lcd_ck_16xx = {
static struct arm_idlect1_clk lcd_ck_1510 = {
.clk = {
- .name = "lcd_ck",
+ .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
.ops = &clkops_generic,
- .parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LCDCK,
@@ -406,37 +355,35 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
.idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
};
+
/*
* XXX The enable_bit here is misused - it simply switches between 12MHz
- * and 48MHz. Reimplement with clksel.
+ * and 48MHz. Reimplement with clk_mux.
*
* XXX does this need SYSC register handling?
*/
-static struct clk uart1_1510 = {
- .name = "uart1_ck",
- .ops = &clkops_null,
+static struct omap1_clk uart1_1510 = {
/* Direct from ULPD, no real parent */
- .parent = &armper_ck.clk,
- .rate = 12000000,
+ .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = CONF_MOD_UART1_CLK_MODE_R,
+ .round_rate = &omap1_round_uart_rate,
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
};
/*
* XXX The enable_bit here is misused - it simply switches between 12MHz
- * and 48MHz. Reimplement with clksel.
+ * and 48MHz. Reimplement with clk_mux.
*
* XXX SYSC register handling does not belong in the clock framework
*/
static struct uart_clk uart1_16xx = {
.clk = {
- .name = "uart1_ck",
.ops = &clkops_uart_16xx,
/* Direct from ULPD, no real parent */
- .parent = &armper_ck.clk,
+ .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
.rate = 48000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
@@ -447,54 +394,49 @@ static struct uart_clk uart1_16xx = {
/*
* XXX The enable_bit here is misused - it simply switches between 12MHz
- * and 48MHz. Reimplement with clksel.
+ * and 48MHz. Reimplement with clk_mux.
*
* XXX does this need SYSC register handling?
*/
-static struct clk uart2_ck = {
- .name = "uart2_ck",
- .ops = &clkops_null,
+static struct omap1_clk uart2_ck = {
/* Direct from ULPD, no real parent */
- .parent = &armper_ck.clk,
- .rate = 12000000,
+ .hw.init = CLK_HW_INIT("uart2_ck", "armper_ck", &omap1_clk_full_ops, 0),
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = CONF_MOD_UART2_CLK_MODE_R,
+ .round_rate = &omap1_round_uart_rate,
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
};
/*
* XXX The enable_bit here is misused - it simply switches between 12MHz
- * and 48MHz. Reimplement with clksel.
+ * and 48MHz. Reimplement with clk_mux.
*
* XXX does this need SYSC register handling?
*/
-static struct clk uart3_1510 = {
- .name = "uart3_ck",
- .ops = &clkops_null,
+static struct omap1_clk uart3_1510 = {
/* Direct from ULPD, no real parent */
- .parent = &armper_ck.clk,
- .rate = 12000000,
+ .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = CONF_MOD_UART3_CLK_MODE_R,
+ .round_rate = &omap1_round_uart_rate,
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
};
/*
* XXX The enable_bit here is misused - it simply switches between 12MHz
- * and 48MHz. Reimplement with clksel.
+ * and 48MHz. Reimplement with clk_mux.
*
* XXX SYSC register handling does not belong in the clock framework
*/
static struct uart_clk uart3_16xx = {
.clk = {
- .name = "uart3_ck",
.ops = &clkops_uart_16xx,
/* Direct from ULPD, no real parent */
- .parent = &armper_ck.clk,
+ .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
.rate = 48000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
@@ -503,30 +445,30 @@ static struct uart_clk uart3_16xx = {
.sysc_addr = 0xfffb9854,
};
-static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
- .name = "usb_clko",
+static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
+ .hw.init = CLK_HW_INIT_NO_PARENT("usb_clko", &omap1_clk_full_ops, 0),
.rate = 6000000,
.flags = ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
.enable_bit = USB_MCLK_EN_BIT,
};
-static struct clk usb_hhc_ck1510 = {
- .name = "usb_hhc_ck",
+static struct omap1_clk usb_hhc_ck1510 = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
+ .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
.flags = ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = USB_HOST_HHC_UHOST_EN,
};
-static struct clk usb_hhc_ck16xx = {
- .name = "usb_hhc_ck",
+static struct omap1_clk usb_hhc_ck16xx = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
+ .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
.rate = 48000000,
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
.flags = ENABLE_REG_32BIT,
@@ -534,46 +476,46 @@ static struct clk usb_hhc_ck16xx = {
.enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
};
-static struct clk usb_dc_ck = {
- .name = "usb_dc_ck",
+static struct omap1_clk usb_dc_ck = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
+ .hw.init = CLK_HW_INIT_NO_PARENT("usb_dc_ck", &omap1_clk_full_ops, 0),
.rate = 48000000,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
};
-static struct clk uart1_7xx = {
- .name = "uart1_ck",
+static struct omap1_clk uart1_7xx = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
+ .hw.init = CLK_HW_INIT_NO_PARENT("uart1_ck", &omap1_clk_full_ops, 0),
.rate = 12000000,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 9,
};
-static struct clk uart2_7xx = {
- .name = "uart2_ck",
+static struct omap1_clk uart2_7xx = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
+ .hw.init = CLK_HW_INIT_NO_PARENT("uart2_ck", &omap1_clk_full_ops, 0),
.rate = 12000000,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 11,
};
-static struct clk mclk_1510 = {
- .name = "mclk",
+static struct omap1_clk mclk_1510 = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
+ .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
.rate = 12000000,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
};
-static struct clk mclk_16xx = {
- .name = "mclk",
+static struct omap1_clk mclk_16xx = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
+ .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
.enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
.enable_bit = COM_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
@@ -581,17 +523,16 @@ static struct clk mclk_16xx = {
.init = &omap1_init_ext_clk,
};
-static struct clk bclk_1510 = {
- .name = "bclk",
- .ops = &clkops_generic,
+static struct omap1_clk bclk_1510 = {
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
+ .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_rate_ops, 0),
.rate = 12000000,
};
-static struct clk bclk_16xx = {
- .name = "bclk",
+static struct omap1_clk bclk_16xx = {
.ops = &clkops_generic,
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
+ .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_full_ops, 0),
.enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
.enable_bit = SWD_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
@@ -599,11 +540,10 @@ static struct clk bclk_16xx = {
.init = &omap1_init_ext_clk,
};
-static struct clk mmc1_ck = {
- .name = "mmc1_ck",
+static struct omap1_clk mmc1_ck = {
.ops = &clkops_generic,
/* Functional clock is direct from ULPD, interface clock is ARMPER */
- .parent = &armper_ck.clk,
+ .hw.init = CLK_HW_INIT("mmc1_ck", "armper_ck", &omap1_clk_full_ops, 0),
.rate = 48000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
@@ -614,32 +554,29 @@ static struct clk mmc1_ck = {
* XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
* CONF_MOD_MCBSP3_AUXON ??
*/
-static struct clk mmc2_ck = {
- .name = "mmc2_ck",
+static struct omap1_clk mmc2_ck = {
.ops = &clkops_generic,
/* Functional clock is direct from ULPD, interface clock is ARMPER */
- .parent = &armper_ck.clk,
+ .hw.init = CLK_HW_INIT("mmc2_ck", "armper_ck", &omap1_clk_full_ops, 0),
.rate = 48000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 20,
};
-static struct clk mmc3_ck = {
- .name = "mmc3_ck",
+static struct omap1_clk mmc3_ck = {
.ops = &clkops_generic,
/* Functional clock is direct from ULPD, interface clock is ARMPER */
- .parent = &armper_ck.clk,
+ .hw.init = CLK_HW_INIT("mmc3_ck", "armper_ck", &omap1_clk_full_ops, 0),
.rate = 48000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
};
-static struct clk virtual_ck_mpu = {
- .name = "mpu",
- .ops = &clkops_null,
- .parent = &arm_ck, /* Is smarter alias for */
+static struct omap1_clk virtual_ck_mpu = {
+ /* Is smarter alias for arm_ck */
+ .hw.init = CLK_HW_INIT("mpu", "arm_ck", &omap1_clk_rate_ops, 0),
.recalc = &followparent_recalc,
.set_rate = &omap1_select_table_rate,
.round_rate = &omap1_round_to_table_rate,
@@ -647,20 +584,14 @@ static struct clk virtual_ck_mpu = {
/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
remains active during MPU idle whenever this is enabled */
-static struct clk i2c_fck = {
- .name = "i2c_fck",
- .ops = &clkops_null,
+static struct omap1_clk i2c_fck = {
+ .hw.init = CLK_HW_INIT("i2c_fck", "armxor_ck", &omap1_clk_gate_ops, 0),
.flags = CLOCK_NO_IDLE_PARENT,
- .parent = &armxor_ck.clk,
- .recalc = &followparent_recalc,
};
-static struct clk i2c_ick = {
- .name = "i2c_ick",
- .ops = &clkops_null,
+static struct omap1_clk i2c_ick = {
+ .hw.init = CLK_HW_INIT("i2c_ick", "armper_ck", &omap1_clk_gate_ops, 0),
.flags = CLOCK_NO_IDLE_PARENT,
- .parent = &armper_ck.clk,
- .recalc = &followparent_recalc,
};
/*
@@ -669,81 +600,81 @@ static struct clk i2c_ick = {
static struct omap_clk omap_clks[] = {
/* non-ULPD clocks */
- CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
- CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK(NULL, "ck_ref", &ck_ref.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK(NULL, "ck_dpll1", &ck_dpll1.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
/* CK_GEN1 clocks */
- CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
- CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
- CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
- CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
- CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
- CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
- CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
- CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
- CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
- CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
- CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
+ CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk.hw, CK_16XX),
+ CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
+ CLK(NULL, "arm_ck", &arm_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "armper_ck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("omap_gpio.0", "ick", &arm_gpio_ck.hw, CK_1510 | CK_310),
+ CLK(NULL, "armxor_ck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK(NULL, "armtim_ck", &armtim_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("omap_wdt", "fck", &armwdt_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("omap_wdt", "ick", &armper_ck.clk.hw, CK_16XX),
+ CLK("omap_wdt", "ick", &dummy_ck.hw, CK_1510 | CK_310),
+ CLK(NULL, "arminth_ck", &arminth_ck1510.hw, CK_1510 | CK_310),
+ CLK(NULL, "arminth_ck", &arminth_ck16xx.hw, CK_16XX),
/* CK_GEN2 clocks */
- CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "dsp_ck", &dsp_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "dspmmu_ck", &dspmmu_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "dspper_ck", &dspper_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "dspxor_ck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "dsptim_ck", &dsptim_ck.hw, CK_16XX | CK_1510 | CK_310),
/* CK_GEN3 clocks */
- CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
- CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
- CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
- CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
- CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
- CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
- CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
- CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
- CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
- CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
- CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
- CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
+ CLK(NULL, "tc_ck", &tc_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK(NULL, "tipb_ck", &tipb_ck.hw, CK_1510 | CK_310),
+ CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck.hw, CK_16XX | CK_7XX),
+ CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
+ CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
+ CLK(NULL, "dma_ck", &dma_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck.hw, CK_16XX),
+ CLK(NULL, "api_ck", &api_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK(NULL, "lb_ck", &lb_ck.clk.hw, CK_1510 | CK_310),
+ CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
+ CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
+ CLK(NULL, "lcd_ck", &lcd_ck_16xx.hw, CK_16XX | CK_7XX),
+ CLK(NULL, "lcd_ck", &lcd_ck_1510.clk.hw, CK_1510 | CK_310),
/* ULPD clocks */
- CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
- CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
- CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
- CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
- CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
- CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
- CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
- CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
- CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
- CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
- CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
- CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
- CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
- CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
- CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
- CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
- CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
- CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
- CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
+ CLK(NULL, "uart1_ck", &uart1_1510.hw, CK_1510 | CK_310),
+ CLK(NULL, "uart1_ck", &uart1_16xx.clk.hw, CK_16XX),
+ CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
+ CLK(NULL, "uart2_ck", &uart2_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
+ CLK(NULL, "uart3_ck", &uart3_1510.hw, CK_1510 | CK_310),
+ CLK(NULL, "uart3_ck", &uart3_16xx.clk.hw, CK_16XX),
+ CLK(NULL, "usb_clko", &usb_clko.hw, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510.hw, CK_1510 | CK_310),
+ CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx.hw, CK_16XX),
+ CLK(NULL, "usb_dc_ck", &usb_dc_ck.hw, CK_16XX | CK_7XX),
+ CLK(NULL, "mclk", &mclk_1510.hw, CK_1510 | CK_310),
+ CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
+ CLK(NULL, "bclk", &bclk_1510.hw, CK_1510 | CK_310),
+ CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
+ CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
+ CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
+ CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
/* Virtual clocks */
- CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
- CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
- CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
- CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
- CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
- CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
- CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
- CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
- CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
- CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
- CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
- CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
- CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
- CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
- CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
- CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
- CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
- CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
+ CLK(NULL, "mpu", &virtual_ck_mpu.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("omap_i2c.1", "fck", &i2c_fck.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+ CLK("omap_i2c.1", "ick", &i2c_ick.hw, CK_16XX),
+ CLK("omap_i2c.1", "ick", &dummy_ck.hw, CK_1510 | CK_310 | CK_7XX),
+ CLK("omap1_spi100k.1", "fck", &dummy_ck.hw, CK_7XX),
+ CLK("omap1_spi100k.1", "ick", &dummy_ck.hw, CK_7XX),
+ CLK("omap1_spi100k.2", "fck", &dummy_ck.hw, CK_7XX),
+ CLK("omap1_spi100k.2", "ick", &dummy_ck.hw, CK_7XX),
+ CLK("omap_uwire", "fck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
+ CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
+ CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
+ CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
+ CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
+ CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
+ CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
+ CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
};
/*
@@ -763,15 +694,14 @@ u32 cpu_mask;
int __init omap1_clk_init(void)
{
struct omap_clk *c;
- int crystal_type = 0; /* Default 12 MHz */
u32 reg;
#ifdef CONFIG_DEBUG_LL
- /*
- * Resets some clocks that may be left on from bootloader,
- * but leaves serial clocks on.
- */
- omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
+ /* Make sure UART clocks are enabled early */
+ if (cpu_is_omap16xx())
+ omap_writel(omap_readl(MOD_CONF_CTRL_0) |
+ CONF_MOD_UART1_CLK_MODE_R |
+ CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0);
#endif
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
@@ -783,9 +713,6 @@ int __init omap1_clk_init(void)
/* By default all idlect1 clocks are allowed to idle */
arm_idlect1_mask = ~0;
- for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
- clk_preinit(c->lk.clk);
-
cpu_mask = 0;
if (cpu_is_omap1710())
cpu_mask |= CK_1710;
@@ -793,32 +720,19 @@ int __init omap1_clk_init(void)
cpu_mask |= CK_16XX;
if (cpu_is_omap1510())
cpu_mask |= CK_1510;
- if (cpu_is_omap7xx())
- cpu_mask |= CK_7XX;
if (cpu_is_omap310())
cpu_mask |= CK_310;
- for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
- if (c->cpu & cpu_mask) {
- clkdev_add(&c->lk);
- clk_register(c->lk.clk);
- }
-
/* Pointers to these clocks are needed by code in clock.c */
- api_ck_p = clk_get(NULL, "api_ck");
- ck_dpll1_p = clk_get(NULL, "ck_dpll1");
- ck_ref_p = clk_get(NULL, "ck_ref");
-
- if (cpu_is_omap7xx())
- ck_ref.rate = 13000000;
- if (cpu_is_omap16xx() && crystal_type == 2)
- ck_ref.rate = 19200000;
+ api_ck_p = &api_ck.clk;
+ ck_dpll1_p = &ck_dpll1;
+ ck_ref_p = &ck_ref;
pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
omap_readw(ARM_CKCTL));
- /* We want to be in syncronous scalable mode */
+ /* We want to be in synchronous scalable mode */
omap_writew(0x1000, ARM_SYSST);
@@ -851,15 +765,6 @@ int __init omap1_clk_init(void)
}
}
}
- propagate_rate(&ck_dpll1);
- /* Cache rates for clocks connected to ck_ref (not dpll1) */
- propagate_rate(&ck_ref);
- omap1_show_rates();
- if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
- /* Select slicer output as OMAP input clock */
- omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
- OMAP7XX_PCC_UPLD_CTRL);
- }
/* Amstrad Delta wants BCLK high when inactive */
if (machine_is_ams_delta())
@@ -868,11 +773,7 @@ int __init omap1_clk_init(void)
ULPD_CLOCK_CTRL);
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
- /* (on 730, bit 13 must not be cleared) */
- if (cpu_is_omap7xx())
- omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
- else
- omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
+ omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
/* Put DSP/MPUI into reset until needed */
omap_writew(0, ARM_RSTCT1);
@@ -886,16 +787,28 @@ int __init omap1_clk_init(void)
*/
omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
- clk_enable(&armper_ck.clk);
- clk_enable(&armxor_ck.clk);
- clk_enable(&armtim_ck.clk); /* This should be done by timer code */
+ for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) {
+ if (!(c->cpu & cpu_mask))
+ continue;
+
+ if (c->lk.clk_hw->init) { /* NULL if provider already registered */
+ const struct clk_init_data *init = c->lk.clk_hw->init;
+ const char *name = c->lk.clk_hw->init->name;
+ int err;
+
+ err = clk_hw_register(NULL, c->lk.clk_hw);
+ if (err < 0) {
+ pr_err("failed to register clock \"%s\"! (%d)\n", name, err);
+ /* may be tried again, restore init data */
+ c->lk.clk_hw->init = init;
+ continue;
+ }
+ }
- if (cpu_is_omap15xx())
- clk_enable(&arm_gpio_ck);
+ clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id);
+ }
+
+ omap1_show_rates();
return 0;
}
@@ -907,7 +820,7 @@ void __init omap1_clk_late_init(void)
unsigned long rate = ck_dpll1.rate;
/* Find the highest supported frequency and enable it */
- if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
+ if (omap1_select_table_rate(&virtual_ck_mpu, ~0, arm_ck.rate)) {
pr_err("System frequencies not set, using default. Check your config.\n");
/*
* Reprogramming the DPLL is tricky, it must be done from SRAM.
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index 504b959ba5cf..7a7c3d9eb84a 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -31,39 +31,10 @@
#include <asm/exception.h>
-#include <mach/irqs.h>
-
+#include "irqs.h"
#include "soc.h"
#include "i2c.h"
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-void omap7xx_map_io(void);
-#else
-static inline void omap7xx_map_io(void)
-{
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
-void omap1510_fpga_init_irq(void);
-void omap15xx_map_io(void);
-#else
-static inline void omap1510_fpga_init_irq(void)
-{
-}
-static inline void omap15xx_map_io(void)
-{
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP16XX
-void omap16xx_map_io(void);
-#else
-static inline void omap16xx_map_io(void)
-{
-}
-#endif
-
#ifdef CONFIG_OMAP_SERIAL_WAKE
int omap_serial_wakeup_init(void);
#else
@@ -73,6 +44,7 @@ static inline int omap_serial_wakeup_init(void)
}
#endif
+void omap1_map_io(void);
void omap1_init_early(void);
void omap1_init_irq(void);
void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 6bc32ebda7a7..5304699c7a97 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -14,15 +14,14 @@
#include <linux/spi/spi.h>
#include <linux/platform_data/omap-wd-timer.h>
+#include <linux/soc/ti/omap1-io.h>
#include <asm/mach/map.h>
-#include <mach/tc.h>
-#include <mach/mux.h>
-
-#include <mach/omap7xx.h>
-#include <mach/hardware.h>
+#include "tc.h"
+#include "mux.h"
+#include "hardware.h"
#include "common.h"
#include "clock.h"
#include "mmc.h"
@@ -63,8 +62,6 @@ static void omap_init_rtc(void)
static inline void omap_init_rtc(void) {}
#endif
-static inline void omap_init_mbox(void) { }
-
/*-------------------------------------------------------------------------*/
#if IS_ENABLED(CONFIG_MMC_OMAP)
@@ -73,22 +70,16 @@ static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
if (controller_nr == 0) {
- if (cpu_is_omap7xx()) {
- omap_cfg_reg(MMC_7XX_CMD);
- omap_cfg_reg(MMC_7XX_CLK);
- omap_cfg_reg(MMC_7XX_DAT0);
- } else {
- omap_cfg_reg(MMC_CMD);
- omap_cfg_reg(MMC_CLK);
- omap_cfg_reg(MMC_DAT0);
- }
+ omap_cfg_reg(MMC_CMD);
+ omap_cfg_reg(MMC_CLK);
+ omap_cfg_reg(MMC_DAT0);
if (cpu_is_omap1710()) {
omap_cfg_reg(M15_1710_MMC_CLKI);
omap_cfg_reg(P19_1710_MMC_CMDDIR);
omap_cfg_reg(P20_1710_MMC_DATDIR0);
}
- if (mmc_controller->slots[0].wires == 4 && !cpu_is_omap7xx()) {
+ if (mmc_controller->slots[0].wires == 4) {
omap_cfg_reg(MMC_DAT1);
/* NOTE: DAT2 can be on W10 (here) or M15 */
if (!mmc_controller->slots[0].nomux)
@@ -154,8 +145,6 @@ static int __init omap_mmc_add(const char *name, int id, unsigned long base,
res[3].name = "tx";
res[3].flags = IORESOURCE_DMA;
- if (cpu_is_omap7xx())
- data->slots[0].features = MMC_OMAP7XX;
if (cpu_is_omap15xx())
data->slots[0].features = MMC_OMAP15XX;
if (cpu_is_omap16xx())
@@ -224,43 +213,6 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
/*-------------------------------------------------------------------------*/
-/* OMAP7xx SPI support */
-#if IS_ENABLED(CONFIG_SPI_OMAP_100K)
-
-struct platform_device omap_spi1 = {
- .name = "omap1_spi100k",
- .id = 1,
-};
-
-struct platform_device omap_spi2 = {
- .name = "omap1_spi100k",
- .id = 2,
-};
-
-static void omap_init_spi100k(void)
-{
- if (!cpu_is_omap7xx())
- return;
-
- omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff);
- if (omap_spi1.dev.platform_data)
- platform_device_register(&omap_spi1);
-
- omap_spi2.dev.platform_data = ioremap(OMAP7XX_SPI2_BASE, 0x7ff);
- if (omap_spi2.dev.platform_data)
- platform_device_register(&omap_spi2);
-}
-
-#else
-static inline void omap_init_spi100k(void)
-{
-}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-static inline void omap_init_sti(void) {}
-
/* Numbering for the SPI-capable controllers when used for SPI:
* spi = 1
* uwire = 2
@@ -363,10 +315,7 @@ static int __init omap1_init_devices(void)
* in alphabetical order so they're easier to sort through.
*/
- omap_init_mbox();
omap_init_rtc();
- omap_init_spi100k();
- omap_init_sti();
omap_init_uwire();
omap1_init_rng();
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 2bf659fb6099..756966cb715f 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -24,7 +24,7 @@
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
-#include <mach/tc.h>
+#include "tc.h"
#include "soc.h"
@@ -261,22 +261,6 @@ static const struct platform_device_info omap_dma_dev_info = {
.num_res = 1,
};
-/* OMAP730, OMAP850 */
-static const struct dma_slave_map omap7xx_sdma_map[] = {
- { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
- { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
- { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) },
- { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) },
- { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
- { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
- { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
- { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
- { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
- { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
- { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
- { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
-};
-
/* OMAP1510, OMAP1610*/
static const struct dma_slave_map omap1xxx_sdma_map[] = {
{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
@@ -371,13 +355,8 @@ static int __init omap1_system_dma_init(void)
p.dma_attr = d;
p.errata = configure_dma_errata();
- if (cpu_is_omap7xx()) {
- p.slave_map = omap7xx_sdma_map;
- p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map);
- } else {
- p.slave_map = omap1xxx_sdma_map;
- p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
- }
+ p.slave_map = omap1xxx_sdma_map;
+ p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
ret = platform_device_add_data(pdev, &p, sizeof(p));
if (ret) {
diff --git a/arch/arm/mach-omap1/fb.c b/arch/arm/mach-omap1/fb.c
index b093375afc27..b6e952b03838 100644
--- a/arch/arm/mach-omap1/fb.c
+++ b/arch/arm/mach-omap1/fb.c
@@ -21,7 +21,7 @@
#include <asm/mach/map.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#if IS_ENABLED(CONFIG_FB_OMAP)
@@ -30,7 +30,7 @@ static struct omapfb_platform_data omapfb_config;
static u64 omap_fb_dma_mask = ~(u32)0;
-struct resource omap_fb_resources[] = {
+static struct resource omap_fb_resources[] = {
{
.name = "irq",
.start = INT_LCD_CTRL,
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 40e43ce5329f..0a3ddb3b66eb 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -6,11 +6,12 @@
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
+#include <linux/soc/ti/omap1-io.h>
+
+#include "tc.h"
-#include <mach/tc.h>
#include "flash.h"
-#include <mach/hardware.h>
void omap1_set_vpp(struct platform_device *pdev, int enable)
{
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
deleted file mode 100644
index f03ed523f20f..000000000000
--- a/arch/arm/mach-omap1/fpga.c
+++ /dev/null
@@ -1,187 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap1/fpga.c
- *
- * Interrupt handler for OMAP-1510 Innovator FPGA
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- */
-
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-
-#include "iomap.h"
-#include "common.h"
-#include "fpga.h"
-
-static void fpga_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
-
- if (irq < 8)
- __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
- & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
- else if (irq < 16)
- __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
- & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
- else
- __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
- & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
-}
-
-
-static inline u32 get_fpga_unmasked_irqs(void)
-{
- return
- ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
- __raw_readb(OMAP1510_FPGA_IMR_LO))) |
- ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
- __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
- ((__raw_readb(INNOVATOR_FPGA_ISR2) &
- __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
-}
-
-
-static void fpga_ack_irq(struct irq_data *d)
-{
- /* Don't need to explicitly ACK FPGA interrupts */
-}
-
-static void fpga_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
-
- if (irq < 8)
- __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
- OMAP1510_FPGA_IMR_LO);
- else if (irq < 16)
- __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
- | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
- else
- __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
- | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
-}
-
-static void fpga_mask_ack_irq(struct irq_data *d)
-{
- fpga_mask_irq(d);
- fpga_ack_irq(d);
-}
-
-static void innovator_fpga_IRQ_demux(struct irq_desc *desc)
-{
- u32 stat;
- int fpga_irq;
-
- stat = get_fpga_unmasked_irqs();
-
- if (!stat)
- return;
-
- for (fpga_irq = OMAP_FPGA_IRQ_BASE;
- (fpga_irq < OMAP_FPGA_IRQ_END) && stat;
- fpga_irq++, stat >>= 1) {
- if (stat & 1) {
- generic_handle_irq(fpga_irq);
- }
- }
-}
-
-static struct irq_chip omap_fpga_irq_ack = {
- .name = "FPGA-ack",
- .irq_ack = fpga_mask_ack_irq,
- .irq_mask = fpga_mask_irq,
- .irq_unmask = fpga_unmask_irq,
-};
-
-
-static struct irq_chip omap_fpga_irq = {
- .name = "FPGA",
- .irq_ack = fpga_ack_irq,
- .irq_mask = fpga_mask_irq,
- .irq_unmask = fpga_unmask_irq,
-};
-
-/*
- * All of the FPGA interrupt request inputs except for the touchscreen are
- * edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive
- * interrupts are acknowledged as a side-effect of reading the interrupt
- * status register from the FPGA. The edge-sensitive interrupt inputs
- * cause a problem with level interrupt requests, such as Ethernet. The
- * problem occurs when a level interrupt request is asserted while its
- * interrupt input is masked in the FPGA, which results in a missed
- * interrupt.
- *
- * In an attempt to workaround the problem with missed interrupts, the
- * mask_ack routine for all of the FPGA interrupts has been changed from
- * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
- * being serviced is left unmasked. We can do this because the FPGA cascade
- * interrupt is run with all interrupts masked.
- *
- * Limited testing indicates that this workaround appears to be effective
- * for the smc9194 Ethernet driver used on the Innovator. It should work
- * on other FPGA interrupts as well, but any drivers that explicitly mask
- * interrupts at the interrupt controller via disable_irq/enable_irq
- * could pose a problem.
- */
-void omap1510_fpga_init_irq(void)
-{
- int i, res;
-
- __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
- __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
- __raw_writeb(0, INNOVATOR_FPGA_IMR2);
-
- for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
-
- if (i == OMAP1510_INT_FPGA_TS) {
- /*
- * The touchscreen interrupt is level-sensitive, so
- * we'll use the regular mask_ack routine for it.
- */
- irq_set_chip(i, &omap_fpga_irq_ack);
- }
- else {
- /*
- * All FPGA interrupts except the touchscreen are
- * edge-sensitive, so we won't mask them.
- */
- irq_set_chip(i, &omap_fpga_irq);
- }
-
- irq_set_handler(i, handle_edge_irq);
- irq_clear_status_flags(i, IRQ_NOREQUEST);
- }
-
- /*
- * The FPGA interrupt line is connected to GPIO13. Claim this pin for
- * the ARM.
- *
- * NOTE: For general GPIO/MPUIO access and interrupts, please see
- * gpio.[ch]
- */
- res = gpio_request(13, "FPGA irq");
- if (res) {
- pr_err("%s failed to get gpio\n", __func__);
- return;
- }
- gpio_direction_input(13);
- irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
- irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
-}
diff --git a/arch/arm/mach-omap1/fpga.h b/arch/arm/mach-omap1/fpga.h
deleted file mode 100644
index 7e7450edacc1..000000000000
--- a/arch/arm/mach-omap1/fpga.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Interrupt handler for OMAP-1510 FPGA
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- */
-
-#ifndef __ASM_ARCH_OMAP_FPGA_H
-#define __ASM_ARCH_OMAP_FPGA_H
-
-/*
- * ---------------------------------------------------------------------------
- * H2/P2 Debug board FPGA
- * ---------------------------------------------------------------------------
- */
-/* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
-#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
-#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
-
-#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
-#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
-#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
-#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
-#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
-#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
-#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
-
-/* LEDs definition on debug board (16 LEDs, all physically green) */
-#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
-#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
-#define H2P2_DBG_FPGA_LED_RED (1 << 13)
-#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
-/* cpu0 load-meter LEDs */
-#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
-#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
-#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
-
-#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
-#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
-
-#endif
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 3ec08bd5d8a0..61fa26efd865 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP15xx specific gpio init
*
@@ -5,21 +6,14 @@
*
* Author:
* Charulatha V <charu@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>
+#include <linux/soc/ti/omap1-soc.h>
+#include <asm/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
#define OMAP1510_GPIO_BASE 0xFFFCE000
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 500cfd416c42..cf052714b3f8 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP16xx specific gpio init
*
@@ -5,22 +6,14 @@
*
* Author:
* Charulatha V <charu@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>
+#include <linux/soc/ti/omap1-io.h>
-#include <mach/irqs.h>
-
+#include "hardware.h"
+#include "irqs.h"
#include "soc.h"
#define OMAP1610_GPIO1_BASE 0xfffbe400
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
deleted file mode 100644
index aeb81c18ffcc..000000000000
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * OMAP7xx specific gpio init
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Author:
- * Charulatha V <charu@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/gpio-omap.h>
-
-#include <mach/irqs.h>
-
-#include "soc.h"
-
-#define OMAP7XX_GPIO1_BASE 0xfffbc000
-#define OMAP7XX_GPIO2_BASE 0xfffbc800
-#define OMAP7XX_GPIO3_BASE 0xfffbd000
-#define OMAP7XX_GPIO4_BASE 0xfffbd800
-#define OMAP7XX_GPIO5_BASE 0xfffbe000
-#define OMAP7XX_GPIO6_BASE 0xfffbe800
-#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
-
-/* mpu gpio */
-static struct resource omap7xx_mpu_gpio_resources[] = {
- {
- .start = OMAP1_MPUIO_VBASE,
- .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_7XX_MPUIO,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
- .revision = USHRT_MAX,
- .direction = OMAP_MPUIO_IO_CNTL / 2,
- .datain = OMAP_MPUIO_INPUT_LATCH / 2,
- .dataout = OMAP_MPUIO_OUTPUT / 2,
- .irqstatus = OMAP_MPUIO_GPIO_INT / 2,
- .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
- .irqenable_inv = true,
- .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
-};
-
-static struct omap_gpio_platform_data omap7xx_mpu_gpio_config = {
- .is_mpuio = true,
- .bank_width = 16,
- .bank_stride = 2,
- .regs = &omap7xx_mpuio_regs,
-};
-
-static struct platform_device omap7xx_mpu_gpio = {
- .name = "omap_gpio",
- .id = 0,
- .dev = {
- .platform_data = &omap7xx_mpu_gpio_config,
- },
- .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources),
- .resource = omap7xx_mpu_gpio_resources,
-};
-
-/* gpio1 */
-static struct resource omap7xx_gpio1_resources[] = {
- {
- .start = OMAP7XX_GPIO1_BASE,
- .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_7XX_GPIO_BANK1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
- .revision = USHRT_MAX,
- .direction = OMAP7XX_GPIO_DIR_CONTROL,
- .datain = OMAP7XX_GPIO_DATA_INPUT,
- .dataout = OMAP7XX_GPIO_DATA_OUTPUT,
- .irqstatus = OMAP7XX_GPIO_INT_STATUS,
- .irqenable = OMAP7XX_GPIO_INT_MASK,
- .irqenable_inv = true,
- .irqctrl = OMAP7XX_GPIO_INT_CONTROL,
-};
-
-static struct omap_gpio_platform_data omap7xx_gpio1_config = {
- .bank_width = 32,
- .regs = &omap7xx_gpio_regs,
-};
-
-static struct platform_device omap7xx_gpio1 = {
- .name = "omap_gpio",
- .id = 1,
- .dev = {
- .platform_data = &omap7xx_gpio1_config,
- },
- .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources),
- .resource = omap7xx_gpio1_resources,
-};
-
-/* gpio2 */
-static struct resource omap7xx_gpio2_resources[] = {
- {
- .start = OMAP7XX_GPIO2_BASE,
- .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_7XX_GPIO_BANK2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct omap_gpio_platform_data omap7xx_gpio2_config = {
- .bank_width = 32,
- .regs = &omap7xx_gpio_regs,
-};
-
-static struct platform_device omap7xx_gpio2 = {
- .name = "omap_gpio",
- .id = 2,
- .dev = {
- .platform_data = &omap7xx_gpio2_config,
- },
- .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources),
- .resource = omap7xx_gpio2_resources,
-};
-
-/* gpio3 */
-static struct resource omap7xx_gpio3_resources[] = {
- {
- .start = OMAP7XX_GPIO3_BASE,
- .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_7XX_GPIO_BANK3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct omap_gpio_platform_data omap7xx_gpio3_config = {
- .bank_width = 32,
- .regs = &omap7xx_gpio_regs,
-};
-
-static struct platform_device omap7xx_gpio3 = {
- .name = "omap_gpio",
- .id = 3,
- .dev = {
- .platform_data = &omap7xx_gpio3_config,
- },
- .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources),
- .resource = omap7xx_gpio3_resources,
-};
-
-/* gpio4 */
-static struct resource omap7xx_gpio4_resources[] = {
- {
- .start = OMAP7XX_GPIO4_BASE,
- .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_7XX_GPIO_BANK4,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct omap_gpio_platform_data omap7xx_gpio4_config = {
- .bank_width = 32,
- .regs = &omap7xx_gpio_regs,
-};
-
-static struct platform_device omap7xx_gpio4 = {
- .name = "omap_gpio",
- .id = 4,
- .dev = {
- .platform_data = &omap7xx_gpio4_config,
- },
- .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources),
- .resource = omap7xx_gpio4_resources,
-};
-
-/* gpio5 */
-static struct resource omap7xx_gpio5_resources[] = {
- {
- .start = OMAP7XX_GPIO5_BASE,
- .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_7XX_GPIO_BANK5,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct omap_gpio_platform_data omap7xx_gpio5_config = {
- .bank_width = 32,
- .regs = &omap7xx_gpio_regs,
-};
-
-static struct platform_device omap7xx_gpio5 = {
- .name = "omap_gpio",
- .id = 5,
- .dev = {
- .platform_data = &omap7xx_gpio5_config,
- },
- .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources),
- .resource = omap7xx_gpio5_resources,
-};
-
-/* gpio6 */
-static struct resource omap7xx_gpio6_resources[] = {
- {
- .start = OMAP7XX_GPIO6_BASE,
- .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = INT_7XX_GPIO_BANK6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct omap_gpio_platform_data omap7xx_gpio6_config = {
- .bank_width = 32,
- .regs = &omap7xx_gpio_regs,
-};
-
-static struct platform_device omap7xx_gpio6 = {
- .name = "omap_gpio",
- .id = 6,
- .dev = {
- .platform_data = &omap7xx_gpio6_config,
- },
- .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources),
- .resource = omap7xx_gpio6_resources,
-};
-
-static struct platform_device *omap7xx_gpio_dev[] __initdata = {
- &omap7xx_mpu_gpio,
- &omap7xx_gpio1,
- &omap7xx_gpio2,
- &omap7xx_gpio3,
- &omap7xx_gpio4,
- &omap7xx_gpio5,
- &omap7xx_gpio6,
-};
-
-/*
- * omap7xx_gpio_init needs to be done before
- * machine_init functions access gpio APIs.
- * Hence omap7xx_gpio_init is a postcore_initcall.
- */
-static int __init omap7xx_gpio_init(void)
-{
- int i;
-
- if (!cpu_is_omap7xx())
- return -EINVAL;
-
- for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
- platform_device_register(omap7xx_gpio_dev[i]);
-
- return 0;
-}
-postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/hardware.h
index 2dc2d759a8f0..0aa571c9e0eb 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/hardware.h
@@ -1,6 +1,4 @@
/*
- * arch/arm/mach-omap1/include/mach/hardware.h
- *
* Hardware definitions for TI OMAP processors and boards
*
* NOTE: Please put device driver specific defines into a separate header
@@ -42,7 +40,7 @@
#include <asm/types.h>
#include <linux/soc/ti/omap1-soc.h>
-#include <mach/tc.h>
+#include "tc.h"
/* Almost all documentation for chip and board memory maps assumes
* BM is clear. Most devel boards have a switch to control booting
@@ -66,7 +64,7 @@ static inline u32 omap_cs3_phys(void)
#define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */
#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
-#include <mach/serial.h>
+#include "serial.h"
/*
* ---------------------------------------------------------------------------
@@ -116,6 +114,10 @@ static inline u32 omap_cs3_phys(void)
#define OMAP_IH1_BASE 0xfffecb00
#define OMAP_IH2_BASE 0xfffe0000
+#define OMAP_IH2_0_BASE (0xfffe0000)
+#define OMAP_IH2_1_BASE (0xfffe0100)
+#define OMAP_IH2_2_BASE (0xfffe0200)
+#define OMAP_IH2_3_BASE (0xfffe0300)
#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
@@ -133,6 +135,38 @@ static inline u32 omap_cs3_phys(void)
#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
+#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
+#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
+#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
+#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
+#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
+#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
+#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
+
+#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
+#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
+#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
+#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
+#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
+#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
+#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
+
+#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
+#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
+#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
+#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
+#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
+#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
+#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
+
+#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
+#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
+#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
+#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
+#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
+#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
+#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
+
#define IRQ_ITR_REG_OFFSET 0x00
#define IRQ_MIR_REG_OFFSET 0x04
#define IRQ_SIR_IRQ_REG_OFFSET 0x10
@@ -186,12 +220,16 @@ static inline u32 omap_cs3_phys(void)
/*
* ---------------------------------------------------------------------------
- * Processor specific defines
+ * DSP
* ---------------------------------------------------------------------------
*/
-#include "omap7xx.h"
-#include "omap1510.h"
-#include "omap16xx.h"
+#define OMAP1_DSP_BASE 0xE0000000
+#define OMAP1_DSP_SIZE 0x28000
+#define OMAP1_DSP_START 0xE0000000
+
+#define OMAP1_DSPREG_BASE 0xE1000000
+#define OMAP1_DSPREG_SIZE SZ_128K
+#define OMAP1_DSPREG_START 0xE1000000
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index 5e6d81b1624c..94d3e7883e02 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -7,8 +7,10 @@
#include <linux/i2c.h>
#include <linux/platform_data/i2c-omap.h>
-#include <mach/mux.h>
+
+#include "mux.h"
#include "soc.h"
+#include "i2c.h"
#define OMAP_I2C_SIZE 0x3f
#define OMAP1_I2C_BASE 0xfffb3800
@@ -23,13 +25,8 @@ static struct platform_device omap_i2c_devices[1] = {
static void __init omap1_i2c_mux_pins(int bus_id)
{
- if (cpu_is_omap7xx()) {
- omap_cfg_reg(I2C_7XX_SDA);
- omap_cfg_reg(I2C_7XX_SCL);
- } else {
- omap_cfg_reg(I2C_SDA);
- omap_cfg_reg(I2C_SCL);
- }
+ omap_cfg_reg(I2C_SDA);
+ omap_cfg_reg(I2C_SCL);
}
int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
@@ -66,10 +63,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
/* how the cpu bus is wired up differs for 7xx only */
- if (cpu_is_omap7xx())
- pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
- else
- pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
+ pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
pdev->dev.platform_data = pdata;
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index 91556e374152..c3bb1b71fdf3 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -12,12 +12,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/soc/ti/omap1-io.h>
#include <asm/system_info.h>
#include "soc.h"
-
-#include <mach/hardware.h>
-
+#include "hardware.h"
#include "common.h"
#define OMAP_DIE_ID_0 0xfffe1800
diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h
deleted file mode 100644
index ce4f8005b26f..000000000000
--- a/arch/arm/mach-omap1/include/mach/io.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/io.h
- *
- * IO definitions for TI OMAP processors and boards
- *
- * Copied from arch/arm/mach-sa1100/include/mach/io.h
- * Copyright (C) 1997-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Modifications:
- * 06-12-1997 RMK Created.
- * 07-04-1999 RMK Major cleanup
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a) __typesafe_io(a)
-
-#endif
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
deleted file mode 100644
index ee91a6cb548d..000000000000
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-omap1/include/mach/memory.h
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/* REVISIT: omap1 legacy drivers still rely on this */
-#include <mach/hardware.h>
-
-#endif
diff --git a/arch/arm/mach-omap1/include/mach/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h
deleted file mode 100644
index 3d235244bf5c..000000000000
--- a/arch/arm/mach-omap1/include/mach/omap1510.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Hardware definitions for TI OMAP1510 processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_H
-#define __ASM_ARCH_OMAP15XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP1510_DSP_BASE 0xE0000000
-#define OMAP1510_DSP_SIZE 0x28000
-#define OMAP1510_DSP_START 0xE0000000
-
-#define OMAP1510_DSPREG_BASE 0xE1000000
-#define OMAP1510_DSPREG_SIZE SZ_128K
-#define OMAP1510_DSPREG_START 0xE1000000
-
-#define OMAP1510_DSP_MMU_BASE (0xfffed200)
-
-/*
- * ---------------------------------------------------------------------------
- * OMAP-1510 FPGA
- * ---------------------------------------------------------------------------
- */
-#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
-#define OMAP1510_FPGA_SIZE SZ_4K
-#define OMAP1510_FPGA_START 0x08000000 /* PA */
-
-/* Revision */
-#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
-
-/* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
-
-/* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
-
-/* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
-
-#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c)
-#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102)
-
-#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204)
-
-#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210)
-
-#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
-
-/*
- * Power up Giga UART driver, turn on HID clock.
- * Turn off BT power, since we're not using it and it
- * draws power.
- */
-#define OMAP1510_FPGA_RESET_VALUE 0x42
-
-#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
-#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
-#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
-#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
-#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
-#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
-#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
-#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
-
-/*
- * Innovator/OMAP1510 FPGA HID register bit definitions
- */
-#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
-#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
-#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
-#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
-#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
-#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
-#define OMAP1510_FPGA_HID_rsrvd (1<<6)
-#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
-
-/* The FPGA IRQ is cascaded through GPIO_13 */
-#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
-
-/* IRQ Numbers for interrupts muxed through the FPGA */
-#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
-#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
-#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
-#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
-#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
-#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
-#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
-#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
-#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
-#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
-#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
-#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
-#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
-#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
-#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
-#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
-#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
-#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
-#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
-#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
-#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
-#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
-#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
-#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
-
-#endif /* __ASM_ARCH_OMAP15XX_H */
-
diff --git a/arch/arm/mach-omap1/include/mach/omap16xx.h b/arch/arm/mach-omap1/include/mach/omap16xx.h
deleted file mode 100644
index cd1c724869c7..000000000000
--- a/arch/arm/mach-omap1/include/mach/omap16xx.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Hardware definitions for TI OMAP1610/5912/1710 processors.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP16XX_H
-#define __ASM_ARCH_OMAP16XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP16XX_DSP_BASE 0xE0000000
-#define OMAP16XX_DSP_SIZE 0x28000
-#define OMAP16XX_DSP_START 0xE0000000
-
-#define OMAP16XX_DSPREG_BASE 0xE1000000
-#define OMAP16XX_DSPREG_SIZE SZ_128K
-#define OMAP16XX_DSPREG_START 0xE1000000
-
-#define OMAP16XX_SEC_BASE 0xFFFE4000
-#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
-#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
-#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
-
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#define OMAP_IH2_0_BASE (0xfffe0000)
-#define OMAP_IH2_1_BASE (0xfffe0100)
-#define OMAP_IH2_2_BASE (0xfffe0200)
-#define OMAP_IH2_3_BASE (0xfffe0300)
-
-#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
-#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
-#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
-#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
-#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
-#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
-#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
-
-#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
-#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
-#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
-#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
-#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
-#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
-#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
-
-#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
-#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
-#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
-#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
-#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
-#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
-#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
-
-#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
-#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
-#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
-#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
-#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
-#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
-#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
-
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
-
-/*
- * ----------------------------------------------------------------------------
- * Pin configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
-#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
-
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP1610_RESET_CONTROL 0xfffe1140
-
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_SWITCH_BASE (0xfffbc800)
-#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
-
-/* UART3 Registers Mapping through MPU bus */
-#define UART3_RHR (OMAP1_UART3_BASE + 0)
-#define UART3_THR (OMAP1_UART3_BASE + 0)
-#define UART3_DLL (OMAP1_UART3_BASE + 0)
-#define UART3_IER (OMAP1_UART3_BASE + 4)
-#define UART3_DLH (OMAP1_UART3_BASE + 4)
-#define UART3_IIR (OMAP1_UART3_BASE + 8)
-#define UART3_FCR (OMAP1_UART3_BASE + 8)
-#define UART3_EFR (OMAP1_UART3_BASE + 8)
-#define UART3_LCR (OMAP1_UART3_BASE + 0x0C)
-#define UART3_MCR (OMAP1_UART3_BASE + 0x10)
-#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10)
-#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14)
-#define UART3_LSR (OMAP1_UART3_BASE + 0x14)
-#define UART3_TCR (OMAP1_UART3_BASE + 0x18)
-#define UART3_MSR (OMAP1_UART3_BASE + 0x18)
-#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18)
-#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C)
-#define UART3_SPR (OMAP1_UART3_BASE + 0x1C)
-#define UART3_TLR (OMAP1_UART3_BASE + 0x1C)
-#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20)
-#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24)
-#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28)
-#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28)
-#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C)
-#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C)
-#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30)
-#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30)
-#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34)
-#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34)
-#define UART3_BLR (OMAP1_UART3_BASE + 0x38)
-#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C)
-#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C)
-#define UART3_SCR (OMAP1_UART3_BASE + 0x40)
-#define UART3_SSR (OMAP1_UART3_BASE + 0x44)
-#define UART3_EBLR (OMAP1_UART3_BASE + 0x48)
-#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C)
-#define UART3_MVR (OMAP1_UART3_BASE + 0x50)
-
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-
-/* 32-bit Watchdog timer in OMAP 16XX */
-#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
-#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
-#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
-#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
-#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
-#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
-#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
-#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
-#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
-#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
-
-#define WCLR_PRE_SHIFT 5
-#define WCLR_PTV_SHIFT 2
-
-#define WWPS_W_PEND_WSPR (1 << 4)
-#define WWPS_W_PEND_WTGR (1 << 3)
-#define WWPS_W_PEND_WLDR (1 << 2)
-#define WWPS_W_PEND_WCRR (1 << 1)
-#define WWPS_W_PEND_WCLR (1 << 0)
-
-#define WSPR_ENABLE_0 (0x0000bbbb)
-#define WSPR_ENABLE_1 (0x00004444)
-#define WSPR_DISABLE_0 (0x0000aaaa)
-#define WSPR_DISABLE_1 (0x00005555)
-
-#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
-#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
-
-#endif /* __ASM_ARCH_OMAP16XX_H */
-
diff --git a/arch/arm/mach-omap1/include/mach/omap7xx.h b/arch/arm/mach-omap1/include/mach/omap7xx.h
deleted file mode 100644
index 63da994bc609..000000000000
--- a/arch/arm/mach-omap1/include/mach/omap7xx.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Hardware definitions for TI OMAP7XX processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
- * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP7XX_H
-#define __ASM_ARCH_OMAP7XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP7XX_DSP_BASE 0xE0000000
-#define OMAP7XX_DSP_SIZE 0x50000
-#define OMAP7XX_DSP_START 0xE0000000
-
-#define OMAP7XX_DSPREG_BASE 0xE1000000
-#define OMAP7XX_DSPREG_SIZE SZ_128K
-#define OMAP7XX_DSPREG_START 0xE1000000
-
-#define OMAP7XX_SPI1_BASE 0xfffc0800
-#define OMAP7XX_SPI2_BASE 0xfffc1000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_CONFIG_BASE 0xfffe1000
-#define OMAP7XX_IO_CONF_0 0xfffe1070
-#define OMAP7XX_IO_CONF_1 0xfffe1074
-#define OMAP7XX_IO_CONF_2 0xfffe1078
-#define OMAP7XX_IO_CONF_3 0xfffe107c
-#define OMAP7XX_IO_CONF_4 0xfffe1080
-#define OMAP7XX_IO_CONF_5 0xfffe1084
-#define OMAP7XX_IO_CONF_6 0xfffe1088
-#define OMAP7XX_IO_CONF_7 0xfffe108c
-#define OMAP7XX_IO_CONF_8 0xfffe1090
-#define OMAP7XX_IO_CONF_9 0xfffe1094
-#define OMAP7XX_IO_CONF_10 0xfffe1098
-#define OMAP7XX_IO_CONF_11 0xfffe109c
-#define OMAP7XX_IO_CONF_12 0xfffe10a0
-#define OMAP7XX_IO_CONF_13 0xfffe10a4
-
-#define OMAP7XX_MODE_1 0xfffe1010
-#define OMAP7XX_MODE_2 0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP7XX_MODE2_OFFSET 0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_FLASH_CFG_0 0xfffecc10
-#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
-#define OMAP7XX_FLASH_CFG_1 0xfffecc14
-#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_ICR_BASE 0xfffbb800
-#define OMAP7XX_DSP_M_CTL 0xfffbb804
-#define OMAP7XX_DSP_MMU_BASE 0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
-#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /* __ASM_ARCH_OMAP7XX_H */
-
diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h
deleted file mode 100644
index 9cca6a56788f..000000000000
--- a/arch/arm/mach-omap1/include/mach/uncompress.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-
-#include "serial.h"
-
-#define MDR1_MODE_MASK 0x07
-
-volatile u8 *uart_base;
-int uart_shift;
-
-/*
- * Store the DEBUG_LL uart number into memory.
- * See also debug-macro.S, and serial.c for related code.
- */
-static void set_omap_uart_info(unsigned char port)
-{
- /*
- * Get address of some.bss variable and round it down
- * a la CONFIG_AUTO_ZRELADDR.
- */
- u32 ram_start = (u32)&uart_shift & 0xf8000000;
- u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
- *uart_info = port;
-}
-
-static inline void putc(int c)
-{
- if (!uart_base)
- return;
-
- /* Check for UART 16x mode */
- if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
- return;
-
- while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
- barrier();
- uart_base[UART_TX << uart_shift] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * Macros to configure UART1 and debug UART
- */
-#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
- if (machine_is_##mach()) { \
- uart_base = (volatile u8 *)(dbg_uart); \
- uart_shift = (dbg_shft); \
- port = (dbg_id); \
- set_omap_uart_info(port); \
- break; \
- }
-
-#define DEBUG_LL_OMAP7XX(p, mach) \
- _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
- OMAP1UART##p)
-
-#define DEBUG_LL_OMAP1(p, mach) \
- _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \
- OMAP1UART##p)
-
-static inline void arch_decomp_setup(void)
-{
- int port = 0;
-
- /*
- * Initialize the port based on the machine ID from the bootloader.
- * Note that we're using macros here instead of switch statement
- * as machine_is functions are optimized out for the boards that
- * are not selected.
- */
- do {
- /* omap7xx/8xx based boards using UART1 with shift 0 */
- DEBUG_LL_OMAP7XX(1, herald);
- DEBUG_LL_OMAP7XX(1, omap_perseus2);
-
- /* omap15xx/16xx based boards using UART1 */
- DEBUG_LL_OMAP1(1, ams_delta);
- DEBUG_LL_OMAP1(1, nokia770);
- DEBUG_LL_OMAP1(1, omap_h2);
- DEBUG_LL_OMAP1(1, omap_h3);
- DEBUG_LL_OMAP1(1, omap_innovator);
- DEBUG_LL_OMAP1(1, omap_osk);
- DEBUG_LL_OMAP1(1, omap_palmte);
- DEBUG_LL_OMAP1(1, omap_palmz71);
-
- /* omap15xx/16xx based boards using UART2 */
- DEBUG_LL_OMAP1(2, omap_palmtt);
-
- /* omap15xx/16xx based boards using UART3 */
- DEBUG_LL_OMAP1(3, sx1);
- } while (0);
-}
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 5a173fc2a1ca..1f20fe99be57 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -9,111 +9,46 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/omap-dma.h>
#include <asm/tlb.h>
#include <asm/mach/map.h>
-#include <mach/mux.h>
-#include <mach/tc.h>
-#include <linux/omap-dma.h>
-
+#include "tc.h"
#include "iomap.h"
#include "common.h"
-#include "clock.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
-static struct map_desc omap_io_desc[] __initdata = {
+static struct map_desc omap1_io_desc[] __initdata = {
{
.virtual = OMAP1_IO_VIRT,
.pfn = __phys_to_pfn(OMAP1_IO_PHYS),
.length = OMAP1_IO_SIZE,
.type = MT_DEVICE
- }
-};
-
-#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
-static struct map_desc omap7xx_io_desc[] __initdata = {
- {
- .virtual = OMAP7XX_DSP_BASE,
- .pfn = __phys_to_pfn(OMAP7XX_DSP_START),
- .length = OMAP7XX_DSP_SIZE,
- .type = MT_DEVICE
}, {
- .virtual = OMAP7XX_DSPREG_BASE,
- .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START),
- .length = OMAP7XX_DSPREG_SIZE,
- .type = MT_DEVICE
- }
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
-static struct map_desc omap1510_io_desc[] __initdata = {
- {
- .virtual = OMAP1510_DSP_BASE,
- .pfn = __phys_to_pfn(OMAP1510_DSP_START),
- .length = OMAP1510_DSP_SIZE,
+ .virtual = OMAP1_DSP_BASE,
+ .pfn = __phys_to_pfn(OMAP1_DSP_START),
+ .length = OMAP1_DSP_SIZE,
.type = MT_DEVICE
}, {
- .virtual = OMAP1510_DSPREG_BASE,
- .pfn = __phys_to_pfn(OMAP1510_DSPREG_START),
- .length = OMAP1510_DSPREG_SIZE,
+ .virtual = OMAP1_DSPREG_BASE,
+ .pfn = __phys_to_pfn(OMAP1_DSPREG_START),
+ .length = OMAP1_DSPREG_SIZE,
.type = MT_DEVICE
}
};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-static struct map_desc omap16xx_io_desc[] __initdata = {
- {
- .virtual = OMAP16XX_DSP_BASE,
- .pfn = __phys_to_pfn(OMAP16XX_DSP_START),
- .length = OMAP16XX_DSP_SIZE,
- .type = MT_DEVICE
- }, {
- .virtual = OMAP16XX_DSPREG_BASE,
- .pfn = __phys_to_pfn(OMAP16XX_DSPREG_START),
- .length = OMAP16XX_DSPREG_SIZE,
- .type = MT_DEVICE
- }
-};
-#endif
/*
* Maps common IO regions for omap1
*/
-static void __init omap1_map_common_io(void)
+void __init omap1_map_io(void)
{
- iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
+ iotable_init(omap1_io_desc, ARRAY_SIZE(omap1_io_desc));
}
-#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
-void __init omap7xx_map_io(void)
-{
- omap1_map_common_io();
- iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
-void __init omap15xx_map_io(void)
-{
- omap1_map_common_io();
- iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-void __init omap16xx_map_io(void)
-{
- omap1_map_common_io();
- iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
-}
-#endif
-
/*
* Common low-level hardware init for omap1.
*/
@@ -126,11 +61,6 @@ void __init omap1_init_early(void)
*/
omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
-
- /* Must init clocks early to assure that timer interrupt works
- */
- omap1_clk_init();
- omap1_mux_init();
}
void __init omap1_init_late(void)
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index ee6a93083154..bfc7ab010ae2 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -41,15 +41,14 @@
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/irqdomain.h>
#include <asm/irq.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "soc.h"
-
-#include <mach/hardware.h>
-
+#include "hardware.h"
#include "common.h"
#define IRQ_BANK(irq) ((irq) >> 5)
@@ -112,14 +111,6 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
irq_bank_writel(val, bank, offset);
}
-#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
-static struct omap_irq_bank omap7xx_irq_banks[] = {
- { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
- { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
- { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
-};
-#endif
-
#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_irq_bank omap1510_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
@@ -196,12 +187,6 @@ void __init omap1_init_irq(void)
int i, j, irq_base;
unsigned long nr_irqs;
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
- if (cpu_is_omap7xx()) {
- irq_banks = omap7xx_irq_banks;
- irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
- }
-#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
irq_banks = omap1510_irq_banks;
@@ -232,7 +217,7 @@ void __init omap1_init_irq(void)
pr_warn("Couldn't allocate IRQ numbers\n");
irq_base = 0;
}
- omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base;
+ omap_l2_irq = irq_base;
omap_l2_irq -= NR_IRQS_LEGACY;
domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0,
@@ -251,10 +236,6 @@ void __init omap1_init_irq(void)
irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
- /* Enable interrupts in global mask */
- if (cpu_is_omap7xx())
- irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
-
/* Install the interrupt handlers for each bank */
for (i = 0; i < irq_bank_count; i++) {
for (j = i * 32; j < (i + 1) * 32; j++) {
diff --git a/arch/arm/mach-omap1/include/mach/irqs.h b/arch/arm/mach-omap1/irqs.h
index 30bf007700cf..3ab7050b1b6b 100644
--- a/arch/arm/mach-omap1/include/mach/irqs.h
+++ b/arch/arm/mach-omap1/irqs.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * arch/arm/plat-omap/include/mach/irqs.h
- *
* Copyright (C) Greg Lonnon 2001
* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
*
@@ -233,15 +231,6 @@
#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
-/* External FPGA handles interrupts on Innovator boards */
-#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
-#ifdef CONFIG_MACH_OMAP_INNOVATOR
-#define OMAP_FPGA_NR_IRQS 24
-#else
-#define OMAP_FPGA_NR_IRQS 0
-#endif
-#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
-
#define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32))
#ifdef CONFIG_FIQ
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index f36c34f47f11..37863bdce9ea 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -15,14 +15,13 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
-
#include <linux/omap-dma.h>
-#include <mach/mux.h>
-#include "soc.h"
+#include <linux/soc/ti/omap1-io.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <mach/irqs.h>
-
+#include "mux.h"
+#include "soc.h"
+#include "irqs.h"
#include "iomap.h"
#define DPS_RSTCT2_PER_EN (1 << 0)
@@ -44,8 +43,8 @@ static void omap1_mcbsp_request(unsigned int id)
api_clk = clk_get(NULL, "api_ck");
dsp_clk = clk_get(NULL, "dsp_ck");
if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
- clk_enable(api_clk);
- clk_enable(dsp_clk);
+ clk_prepare_enable(api_clk);
+ clk_prepare_enable(dsp_clk);
/*
* DSP external peripheral reset
@@ -63,11 +62,11 @@ static void omap1_mcbsp_free(unsigned int id)
if (id == 0 || id == 2) {
if (--dsp_use == 0) {
if (!IS_ERR(api_clk)) {
- clk_disable(api_clk);
+ clk_disable_unprepare(api_clk);
clk_put(api_clk);
}
if (!IS_ERR(dsp_clk)) {
- clk_disable(dsp_clk);
+ clk_disable_unprepare(dsp_clk);
clk_put(dsp_clk);
}
}
@@ -90,84 +89,6 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
#define OMAP1610_MCBSP2_BASE 0xfffb1000
#define OMAP1610_MCBSP3_BASE 0xe1017000
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-struct resource omap7xx_mcbsp_res[][6] = {
- {
- {
- .start = OMAP7XX_MCBSP1_BASE,
- .end = OMAP7XX_MCBSP1_BASE + SZ_256,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "rx",
- .start = INT_7XX_McBSP1RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "tx",
- .start = INT_7XX_McBSP1TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "rx",
- .start = 9,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "tx",
- .start = 8,
- .flags = IORESOURCE_DMA,
- },
- },
- {
- {
- .start = OMAP7XX_MCBSP2_BASE,
- .end = OMAP7XX_MCBSP2_BASE + SZ_256,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "rx",
- .start = INT_7XX_McBSP2RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "tx",
- .start = INT_7XX_McBSP2TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "rx",
- .start = 11,
- .flags = IORESOURCE_DMA,
- },
- {
- .name = "tx",
- .start = 10,
- .flags = IORESOURCE_DMA,
- },
- },
-};
-
-#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
-
-static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
- {
- .ops = &omap1_mcbsp_ops,
- },
- {
- .ops = &omap1_mcbsp_ops,
- },
-};
-#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
-#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
-#else
-#define omap7xx_mcbsp_res_0 NULL
-#define omap7xx_mcbsp_pdata NULL
-#define OMAP7XX_MCBSP_RES_SZ 0
-#define OMAP7XX_MCBSP_COUNT 0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
struct resource omap15xx_mcbsp_res[][6] = {
{
{
@@ -267,14 +188,7 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
};
#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
-#else
-#define omap15xx_mcbsp_res_0 NULL
-#define omap15xx_mcbsp_pdata NULL
-#define OMAP15XX_MCBSP_RES_SZ 0
-#define OMAP15XX_MCBSP_COUNT 0
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
struct resource omap16xx_mcbsp_res[][6] = {
{
{
@@ -374,12 +288,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
};
#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
-#else
-#define omap16xx_mcbsp_res_0 NULL
-#define omap16xx_mcbsp_pdata NULL
-#define OMAP16XX_MCBSP_RES_SZ 0
-#define OMAP16XX_MCBSP_COUNT 0
-#endif
static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
struct omap_mcbsp_platform_data *config, int size)
@@ -419,12 +327,6 @@ static int __init omap1_mcbsp_init(void)
if (!cpu_class_is_omap1())
return -ENODEV;
- if (cpu_is_omap7xx())
- omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
- OMAP7XX_MCBSP_RES_SZ,
- omap7xx_mcbsp_pdata,
- OMAP7XX_MCBSP_COUNT);
-
if (cpu_is_omap15xx())
omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
OMAP15XX_MCBSP_RES_SZ,
diff --git a/arch/arm/mach-omap1/include/mach/mtd-xip.h b/arch/arm/mach-omap1/mtd-xip.h
index d09b2bc4920f..cbeda46dd526 100644
--- a/arch/arm/mach-omap1/include/mach/mtd-xip.h
+++ b/arch/arm/mach-omap1/mtd-xip.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MTD primitives for XIP support. Architecture specific functions.
*
@@ -5,16 +6,14 @@
*
* Author: Vladimir Barinov <vbarinov@embeddedalley.com>
*
- * (c) 2005 MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express or
- * implied.
+ * (c) 2005 MontaVista Software, Inc.
*/
#ifndef __ARCH_OMAP_MTD_XIP_H__
#define __ARCH_OMAP_MTD_XIP_H__
-#include <mach/hardware.h>
+#include "hardware.h"
+#include <linux/soc/ti/omap1-io.h>
#define OMAP_MPU_TIMER_BASE (0xfffec500)
#define OMAP_MPU_TIMER_OFFSET 0x100
@@ -43,11 +42,7 @@ static inline unsigned long xip_omap_mpu_timer_read(int nr)
* (see linux/mtd/xip.h)
*/
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
-#else
#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
-#endif
/*
* xip_cpu_idle() is used when waiting for a delay equal or larger than
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 972665bf52d6..4456fbc8aa3d 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -12,61 +12,15 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
+#include <linux/soc/ti/omap1-io.h>
-#include <mach/hardware.h>
-
-#include <mach/mux.h>
+#include "hardware.h"
+#include "mux.h"
#ifdef CONFIG_OMAP_MUX
static struct omap_mux_cfg arch_mux_cfg;
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-static struct pin_config omap7xx_pins[] = {
-MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
-MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
-MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
-MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
-MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
-MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
-MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
-MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0)
-MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
-MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
-
-MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
-MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
-MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0)
-MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0)
-MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0)
-
-/* MMC Pins */
-MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0)
-MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0)
-MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0)
-
-/* I2C interface */
-MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0)
-MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0)
-
-/* SPI pins */
-MUX_CFG_7XX("SPI_7XX_1", 6, 5, 4, 4, 1, 0)
-MUX_CFG_7XX("SPI_7XX_2", 6, 9, 4, 8, 1, 0)
-MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0)
-MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0)
-MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0)
-MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0)
-
-/* UART pins */
-MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0)
-MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0)
-};
-#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
-#else
-#define omap7xx_pins NULL
-#define OMAP7XX_PINS_SZ 0
-#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
-
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static struct pin_config omap1xxx_pins[] = {
/*
@@ -489,12 +443,6 @@ EXPORT_SYMBOL(omap_cfg_reg);
int __init omap1_mux_init(void)
{
- if (cpu_is_omap7xx()) {
- arch_mux_cfg.pins = omap7xx_pins;
- arch_mux_cfg.size = OMAP7XX_PINS_SZ;
- arch_mux_cfg.cfg_reg = omap1_cfg_reg;
- }
-
if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
arch_mux_cfg.pins = omap1xxx_pins;
arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
diff --git a/arch/arm/mach-omap1/include/mach/mux.h b/arch/arm/mach-omap1/mux.h
index a78282d1294c..3e7ed3348a55 100644
--- a/arch/arm/mach-omap1/include/mach/mux.h
+++ b/arch/arm/mach-omap1/mux.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * arch/arm/plat-omap/include/mach/mux.h
- *
* Table of the Omap register configurations for the FUNC_MUX and
* PULL_DWN combinations.
*
diff --git a/arch/arm/mach-omap1/ocpi.c b/arch/arm/mach-omap1/ocpi.c
index 380ea2de58c1..d48f726571a4 100644
--- a/arch/arm/mach-omap1/ocpi.c
+++ b/arch/arm/mach-omap1/ocpi.c
@@ -20,9 +20,9 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/soc/ti/omap1-io.h>
-#include <mach/hardware.h>
-
+#include "hardware.h"
#include "common.h"
#define OCPI_BASE 0xfffec320
@@ -73,7 +73,7 @@ static int __init omap_ocpi_init(void)
if (IS_ERR(ocpi_ck))
return PTR_ERR(ocpi_ck);
- clk_enable(ocpi_ck);
+ clk_prepare_enable(ocpi_ck);
ocpi_enable();
pr_info("OMAP OCPI interconnect driver loaded\n");
@@ -87,7 +87,7 @@ static void __exit omap_ocpi_exit(void)
if (!cpu_is_omap16xx())
return;
- clk_disable(ocpi_ck);
+ clk_disable_unprepare(ocpi_ck);
clk_put(ocpi_ck);
}
diff --git a/arch/arm/mach-omap1/omap-dma.c b/arch/arm/mach-omap1/omap-dma.c
index eb14528f133c..9ee472f8ead1 100644
--- a/arch/arm/mach-omap1/omap-dma.c
+++ b/arch/arm/mach-omap1/omap-dma.c
@@ -34,10 +34,11 @@
#include <linux/omap-dma.h>
-#include <mach/hardware.h>
#include <linux/soc/ti/omap1-io.h>
#include <linux/soc/ti/omap1-soc.h>
+#include "tc.h"
+
/*
* MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
* channels that an instance of the SDMA IP block can support. Used
@@ -98,7 +99,7 @@ static inline void set_gdma_dev(int req, int dev)
omap_writel(l, reg);
}
-#ifdef CONFIG_ARCH_OMAP1
+#if IS_ENABLED(CONFIG_FB_OMAP)
void omap_set_dma_priority(int lch, int dst_port, int priority)
{
unsigned long reg;
@@ -128,22 +129,8 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
omap_writel(l, reg);
}
}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
-void omap_set_dma_priority(int lch, int dst_port, int priority)
-{
- u32 ccr;
-
- ccr = p->dma_read(CCR, lch);
- if (priority)
- ccr |= (1 << 6);
- else
- ccr &= ~(1 << 6);
- p->dma_write(ccr, CCR, lch);
-}
-#endif
EXPORT_SYMBOL(omap_set_dma_priority);
+#endif
#if IS_ENABLED(CONFIG_USB_OMAP)
#ifdef CONFIG_ARCH_OMAP15XX
@@ -846,7 +833,7 @@ exit_dma_irq_fail:
return ret;
}
-static int omap_system_dma_remove(struct platform_device *pdev)
+static void omap_system_dma_remove(struct platform_device *pdev)
{
int dma_irq, irq_rel = 0;
@@ -854,13 +841,11 @@ static int omap_system_dma_remove(struct platform_device *pdev)
dma_irq = platform_get_irq(pdev, irq_rel);
free_irq(dma_irq, (void *)(irq_rel + 1));
}
-
- return 0;
}
static struct platform_driver omap_system_dma_driver = {
.probe = omap_system_dma_probe,
- .remove = omap_system_dma_remove,
+ .remove_new = omap_system_dma_remove,
.driver = {
.name = "omap_dma_system"
},
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index a745d64d4699..9761d8404949 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -52,13 +52,14 @@
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
-#include <mach/tc.h>
-#include <mach/mux.h>
+#include <linux/soc/ti/omap1-io.h>
+#include "tc.h"
#include <linux/omap-dma.h>
#include <clocksource/timer-ti-dm.h>
-#include <mach/irqs.h>
-
+#include "hardware.h"
+#include "mux.h"
+#include "irqs.h"
#include "iomap.h"
#include "clock.h"
#include "pm.h"
@@ -68,7 +69,6 @@
static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
-static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
@@ -165,10 +165,7 @@ static void omap_pm_wakeup_setup(void)
* drivers must still separately call omap_set_gpio_wakeup() to
* wake up to a GPIO interrupt.
*/
- if (cpu_is_omap7xx())
- level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
- OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
- else if (cpu_is_omap15xx())
+ if (cpu_is_omap15xx())
level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
@@ -177,12 +174,7 @@ static void omap_pm_wakeup_setup(void)
omap_writel(~level1_wake, OMAP_IH1_MIR);
- if (cpu_is_omap7xx()) {
- omap_writel(~level2_wake, OMAP_IH2_0_MIR);
- omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
- OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
- OMAP_IH2_1_MIR);
- } else if (cpu_is_omap15xx()) {
+ if (cpu_is_omap15xx()) {
level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
omap_writel(~level2_wake, OMAP_IH2_MIR);
} else if (cpu_is_omap16xx()) {
@@ -235,17 +227,7 @@ void omap1_pm_suspend(void)
* Save interrupt, MPUI, ARM and UPLD control registers.
*/
- if (cpu_is_omap7xx()) {
- MPUI7XX_SAVE(OMAP_IH1_MIR);
- MPUI7XX_SAVE(OMAP_IH2_0_MIR);
- MPUI7XX_SAVE(OMAP_IH2_1_MIR);
- MPUI7XX_SAVE(MPUI_CTRL);
- MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
- MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
- MPUI7XX_SAVE(EMIFS_CONFIG);
- MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
-
- } else if (cpu_is_omap15xx()) {
+ if (cpu_is_omap15xx()) {
MPUI1510_SAVE(OMAP_IH1_MIR);
MPUI1510_SAVE(OMAP_IH2_MIR);
MPUI1510_SAVE(MPUI_CTRL);
@@ -287,9 +269,8 @@ void omap1_pm_suspend(void)
/* stop DSP */
omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
- /* shut down dsp_ck */
- if (!cpu_is_omap7xx())
- omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
+ /* shut down dsp_ck */
+ omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
/* temporarily enabling api_ck to access DSP registers */
omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
@@ -365,13 +346,7 @@ void omap1_pm_suspend(void)
ULPD_RESTORE(ULPD_CLOCK_CTRL);
ULPD_RESTORE(ULPD_STATUS_REQ);
- if (cpu_is_omap7xx()) {
- MPUI7XX_RESTORE(EMIFS_CONFIG);
- MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
- MPUI7XX_RESTORE(OMAP_IH1_MIR);
- MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
- MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
- } else if (cpu_is_omap15xx()) {
+ if (cpu_is_omap15xx()) {
MPUI1510_RESTORE(MPUI_CTRL);
MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
@@ -432,14 +407,7 @@ static int omap_pm_debug_show(struct seq_file *m, void *v)
ULPD_SAVE(ULPD_DPLL_CTRL);
ULPD_SAVE(ULPD_POWER_CTRL);
- if (cpu_is_omap7xx()) {
- MPUI7XX_SAVE(MPUI_CTRL);
- MPUI7XX_SAVE(MPUI_DSP_STATUS);
- MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
- MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
- MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
- MPUI7XX_SAVE(EMIFS_CONFIG);
- } else if (cpu_is_omap15xx()) {
+ if (cpu_is_omap15xx()) {
MPUI1510_SAVE(MPUI_CTRL);
MPUI1510_SAVE(MPUI_DSP_STATUS);
MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
@@ -485,21 +453,7 @@ static int omap_pm_debug_show(struct seq_file *m, void *v)
ULPD_SHOW(ULPD_STATUS_REQ),
ULPD_SHOW(ULPD_POWER_CTRL));
- if (cpu_is_omap7xx()) {
- seq_printf(m,
- "MPUI7XX_CTRL_REG 0x%-8x \n"
- "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
- "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
- "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
- "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
- "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
- MPUI7XX_SHOW(MPUI_CTRL),
- MPUI7XX_SHOW(MPUI_DSP_STATUS),
- MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
- MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
- MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
- MPUI7XX_SHOW(EMIFS_CONFIG));
- } else if (cpu_is_omap15xx()) {
+ if (cpu_is_omap15xx()) {
seq_printf(m,
"MPUI1510_CTRL_REG 0x%-8x \n"
"MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
@@ -633,10 +587,7 @@ static int __init omap_pm_init(void)
* These routines need to be in SRAM as that's the only
* memory the MPU can see when it wakes up.
*/
- if (cpu_is_omap7xx()) {
- omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
- omap7xx_cpu_suspend_sz);
- } else if (cpu_is_omap15xx()) {
+ if (cpu_is_omap15xx()) {
omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
omap1510_cpu_suspend_sz);
} else if (cpu_is_omap16xx()) {
@@ -651,9 +602,7 @@ static int __init omap_pm_init(void)
arm_pm_idle = omap1_pm_idle;
- if (cpu_is_omap7xx())
- irq = INT_7XX_WAKE_UP_REQ;
- else if (cpu_is_omap16xx())
+ if (cpu_is_omap16xx())
irq = INT_1610_WAKE_UP_REQ;
else
irq = -1;
@@ -672,9 +621,7 @@ static int __init omap_pm_init(void)
omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
/* Configure IDLECT3 */
- if (cpu_is_omap7xx())
- omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
- else if (cpu_is_omap16xx())
+ if (cpu_is_omap16xx())
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h
index cd926dcb5e7f..d4373a5c4697 100644
--- a/arch/arm/mach-omap1/pm.h
+++ b/arch/arm/mach-omap1/pm.h
@@ -34,6 +34,8 @@
#ifndef __ARCH_ARM_MACH_OMAP1_PM_H
#define __ARCH_ARM_MACH_OMAP1_PM_H
+#include <linux/soc/ti/omap1-io.h>
+
/*
* ----------------------------------------------------------------------------
* Register and offset definitions to be used in PM assembler code
@@ -98,19 +100,6 @@
#define OMAP1610_IDLECT3 0xfffece24
#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
-#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7
-#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7
-#define OMAP7XX_IDLECT3_VAL 0x3f
-#define OMAP7XX_IDLECT3 0xfffece24
-#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00
-
-#if !defined(CONFIG_ARCH_OMAP730) && \
- !defined(CONFIG_ARCH_OMAP850) && \
- !defined(CONFIG_ARCH_OMAP15XX) && \
- !defined(CONFIG_ARCH_OMAP16XX)
-#warning "Power management for this processor not implemented yet"
-#endif
-
#ifndef __ASSEMBLER__
#include <linux/clk.h>
@@ -123,17 +112,13 @@ extern void allow_idle_sleep(void);
extern void omap1_pm_idle(void);
extern void omap1_pm_suspend(void);
-extern void omap7xx_cpu_suspend(unsigned long, unsigned long);
extern void omap1510_cpu_suspend(unsigned long, unsigned long);
extern void omap1610_cpu_suspend(unsigned long, unsigned long);
-extern void omap7xx_idle_loop_suspend(void);
extern void omap1510_idle_loop_suspend(void);
extern void omap1610_idle_loop_suspend(void);
-extern unsigned int omap7xx_cpu_suspend_sz;
extern unsigned int omap1510_cpu_suspend_sz;
extern unsigned int omap1610_cpu_suspend_sz;
-extern unsigned int omap7xx_idle_loop_suspend_sz;
extern unsigned int omap1510_idle_loop_suspend_sz;
extern unsigned int omap1610_idle_loop_suspend_sz;
@@ -156,10 +141,6 @@ extern void omap_serial_wake_trigger(int enable);
#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
-#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
-#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
-#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
-
#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
@@ -233,27 +214,6 @@ enum mpui1510_save_state {
#endif
};
-enum mpui7xx_save_state {
- MPUI7XX_SLEEP_SAVE_START = 0,
- /*
- * MPUI registers 32 bits
- */
- MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
- MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
- MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
- MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
- MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
- MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
- MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
- MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
- MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
- MPUI7XX_SLEEP_SAVE_SIZE
-#else
- MPUI7XX_SLEEP_SAVE_SIZE = 0
-#endif
-};
-
enum mpui1610_save_state {
MPUI1610_SLEEP_SAVE_START = 0,
/*
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
index 667c1637ff91..c04619ac0631 100644
--- a/arch/arm/mach-omap1/pm_bus.c
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Runtime PM support code for OMAP1
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
* Copyright (C) 2010 Texas Instruments, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/kernel.h>
@@ -43,4 +40,3 @@ static int __init omap1_pm_runtime_init(void)
return 0;
}
core_initcall(omap1_pm_runtime_init);
-
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index af2c120b0c4e..2eee6a6965ff 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -6,8 +6,7 @@
#include <linux/io.h>
#include <linux/reboot.h>
-#include <mach/hardware.h>
-
+#include "hardware.h"
#include "iomap.h"
#include "common.h"
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 9eb591fbfd89..c7f590645774 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -19,8 +19,8 @@
#include <asm/mach-types.h>
-#include <mach/mux.h>
-
+#include "serial.h"
+#include "mux.h"
#include "pm.h"
#include "soc.h"
@@ -106,13 +106,6 @@ void __init omap_serial_init(void)
{
int i;
- if (cpu_is_omap7xx()) {
- serial_platform_data[0].regshift = 0;
- serial_platform_data[1].regshift = 0;
- serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
- serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
- }
-
if (cpu_is_omap15xx()) {
serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
@@ -120,14 +113,6 @@ void __init omap_serial_init(void)
}
for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) {
-
- /* Don't look at UARTs higher than 2 for omap7xx */
- if (cpu_is_omap7xx() && i > 1) {
- serial_platform_data[i].membase = NULL;
- serial_platform_data[i].mapbase = 0;
- continue;
- }
-
/* Static mapping, never released */
serial_platform_data[i].membase =
ioremap(serial_platform_data[i].mapbase, SZ_2K);
@@ -141,7 +126,7 @@ void __init omap_serial_init(void)
if (IS_ERR(uart1_ck))
printk("Could not get uart1_ck\n");
else {
- clk_enable(uart1_ck);
+ clk_prepare_enable(uart1_ck);
if (cpu_is_omap15xx())
clk_set_rate(uart1_ck, 12000000);
}
@@ -151,7 +136,7 @@ void __init omap_serial_init(void)
if (IS_ERR(uart2_ck))
printk("Could not get uart2_ck\n");
else {
- clk_enable(uart2_ck);
+ clk_prepare_enable(uart2_ck);
if (cpu_is_omap15xx())
clk_set_rate(uart2_ck, 12000000);
else
@@ -163,7 +148,7 @@ void __init omap_serial_init(void)
if (IS_ERR(uart3_ck))
printk("Could not get uart3_ck\n");
else {
- clk_enable(uart3_ck);
+ clk_prepare_enable(uart3_ck);
if (cpu_is_omap15xx())
clk_set_rate(uart3_ck, 12000000);
}
diff --git a/arch/arm/mach-omap1/include/mach/serial.h b/arch/arm/mach-omap1/serial.h
index 4700e384c3d9..4700e384c3d9 100644
--- a/arch/arm/mach-omap1/include/mach/serial.h
+++ b/arch/arm/mach-omap1/serial.h
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index a908c51839a4..6192f52d531a 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -36,7 +36,7 @@
#include <asm/assembler.h>
-#include <mach/hardware.h>
+#include "hardware.h"
#include "iomap.h"
#include "pm.h"
@@ -61,86 +61,6 @@
*
*/
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
- .align 3
-ENTRY(omap7xx_cpu_suspend)
-
- @ save registers on stack
- stmfd sp!, {r0 - r12, lr}
-
- @ Drain write cache
- mov r4, #0
- mcr p15, 0, r0, c7, c10, 4
- nop
-
- @ load base address of Traffic Controller
- mov r6, #TCMIF_ASM_BASE & 0xff000000
- orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
- orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
-
- @ prepare to put SDRAM into self-refresh manually
- ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
- orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
- orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
- str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
-
- @ prepare to put EMIFS to Sleep
- ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
- orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
- str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-
- @ load base address of ARM_IDLECT1 and ARM_IDLECT2
- mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
- orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
- orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
-
- @ turn off clock domains
- @ do not disable PERCK (0x04)
- mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
- orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
- strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
-
- @ request ARM idle
- mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
- orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
- strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
- @ disable instruction cache
- mrc p15, 0, r9, c1, c0, 0
- bic r2, r9, #0x1000
- mcr p15, 0, r2, c1, c0, 0
- nop
-
-/*
- * Let's wait for the next wake up event to wake us up. r0 can't be
- * used here because r0 holds ARM_IDLECT1
- */
- mov r2, #0
- mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
-/*
- * omap7xx_cpu_suspend()'s resume point.
- *
- * It will just start executing here, so we'll restore stuff from the
- * stack.
- */
- @ re-enable Icache
- mcr p15, 0, r9, c1, c0, 0
-
- @ reset the ARM_IDLECT1 and ARM_IDLECT2.
- strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
- strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
-
- @ Restore EMIFF controls
- str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
- str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
-
- @ restore regs and return
- ldmfd sp!, {r0 - r12, pc}
-
-ENTRY(omap7xx_cpu_suspend_sz)
- .word . - omap7xx_cpu_suspend
-#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
-
#ifdef CONFIG_ARCH_OMAP15XX
.align 3
ENTRY(omap1510_cpu_suspend)
diff --git a/arch/arm/mach-omap1/soc.h b/arch/arm/mach-omap1/soc.h
index 22931839a666..5fb57fdd9c2b 100644
--- a/arch/arm/mach-omap1/soc.h
+++ b/arch/arm/mach-omap1/soc.h
@@ -1,6 +1,6 @@
/*
* We can move linux/soc/ti/omap1-soc.h here once the drivers are fixed
*/
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include "hardware.h"
+#include "irqs.h"
#include <asm/irq.h>
diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c
index 0e3ec32a008e..26427d6be896 100644
--- a/arch/arm/mach-omap1/sram-init.c
+++ b/arch/arm/mach-omap1/sram-init.c
@@ -10,11 +10,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/set_memory.h>
#include <asm/fncpy.h>
#include <asm/tlb.h>
#include <asm/cacheflush.h>
-#include <asm/set_memory.h>
#include <asm/mach/map.h>
@@ -53,7 +53,7 @@ static void *omap_sram_push_address(unsigned long size)
new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
omap_sram_ceil = IOMEM(new_ceil);
- return (void *)omap_sram_ceil;
+ return (void __force *)omap_sram_ceil;
}
void *omap_sram_push(void *funcp, unsigned long size)
@@ -74,8 +74,7 @@ void *omap_sram_push(void *funcp, unsigned long size)
dst = fncpy(sram, funcp, size);
- set_memory_ro(base, pages);
- set_memory_x(base, pages);
+ set_memory_rox(base, pages);
return dst;
}
@@ -95,9 +94,7 @@ static void __init omap_detect_and_map_sram(void)
omap_sram_skip = SRAM_BOOTLOADER_SZ;
omap_sram_start = OMAP1_SRAM_PA;
- if (cpu_is_omap7xx())
- omap_sram_size = 0x32000; /* 200K */
- else if (cpu_is_omap15xx())
+ if (cpu_is_omap15xx())
omap_sram_size = 0x30000; /* 192K */
else if (cpu_is_omap1610() || cpu_is_omap1611() ||
cpu_is_omap1621() || cpu_is_omap1710())
@@ -126,8 +123,7 @@ static void __init omap_detect_and_map_sram(void)
base = (unsigned long)omap_sram_base;
pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE;
- set_memory_ro(base, pages);
- set_memory_x(base, pages);
+ set_memory_rox(base, pages);
}
static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
@@ -135,9 +131,6 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
{
BUG_ON(!_omap_sram_reprogram_clock);
- /* On 730, bit 13 must always be 1 */
- if (cpu_is_omap7xx())
- ckctl |= 0x2000;
_omap_sram_reprogram_clock(dpllctl, ckctl);
}
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 37f34fcd65fb..89f4dc1b70f0 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -6,11 +6,11 @@
*/
#include <linux/linkage.h>
+#include <linux/soc/ti/omap1-io.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
-
+#include "hardware.h"
#include "iomap.h"
.text
diff --git a/arch/arm/mach-omap1/include/mach/tc.h b/arch/arm/mach-omap1/tc.h
index adaab6a0bd08..243454bc0684 100644
--- a/arch/arm/mach-omap1/include/mach/tc.h
+++ b/arch/arm/mach-omap1/tc.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * arch/arm/plat-omap/include/mach/tc.h
- *
* OMAP Traffic Controller
*
* Copyright (C) 2004 Nokia Corporation
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index de590a85a42b..d5e127851dc7 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -47,12 +47,14 @@
#include <asm/irq.h>
-#include <mach/hardware.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
+#include "hardware.h"
+#include "mux.h"
#include "iomap.h"
#include "common.h"
+#include "clock.h"
#ifdef CONFIG_OMAP_MPU_TIMER
@@ -224,6 +226,9 @@ static inline void omap_mpu_timer_init(void)
*/
void __init omap1_timer_init(void)
{
+ omap1_clk_init();
+ omap1_mux_init();
+
if (omap_32k_timer_init() != 0)
omap_mpu_timer_init();
}
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 0411d5508d63..81a912c1145a 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP1 Dual-Mode Timers - platform device registration
*
@@ -9,15 +10,6 @@
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
* Tarun Kanti DebBarma <tarun.kanti@ti.com>
* Thara Gopinath <thara@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk.h>
@@ -26,6 +18,7 @@
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
+#include <linux/soc/ti/omap1-io.h>
#include <clocksource/timer-ti-dm.h>
@@ -165,7 +158,7 @@ err_free_pdata:
kfree(pdata);
err_free_pdev:
- platform_device_unregister(pdev);
+ platform_device_put(pdev);
return ret;
}
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 11958ccd894d..410d17d1d443 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -51,7 +51,7 @@
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
+#include "hardware.h"
#include "common.h"
/*
@@ -212,7 +212,7 @@ static void omap_read_persistent_clock64(struct timespec64 *ts)
* Returns 0 upon success or negative error code upon failure.
*
*/
-int __init omap_init_clocksource_32k(void __iomem *vbase)
+static int __init omap_init_clocksource_32k(void __iomem *vbase)
{
int ret;
@@ -270,7 +270,7 @@ int __init omap_32k_timer_init(void)
sync32k_ick = clk_get(NULL, "omap_32ksync_ick");
if (!IS_ERR(sync32k_ick))
- clk_enable(sync32k_ick);
+ clk_prepare_enable(sync32k_ick);
ret = omap_init_clocksource_32k(base);
}
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index fa658054fc57..08d42abc4a0f 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -12,13 +12,13 @@
#include <linux/dma-map-ops.h>
#include <linux/io.h>
#include <linux/delay.h>
+#include <linux/soc/ti/omap1-io.h>
#include <asm/irq.h>
-#include <mach/mux.h>
-
+#include "hardware.h"
+#include "mux.h"
#include "usb.h"
-
#include "common.h"
/* These routines should handle the standard chip-specific modes
@@ -190,12 +190,6 @@ static struct platform_device udc_device = {
static inline void udc_device_init(struct omap_usb_config *pdata)
{
- /* IRQ numbers for omap7xx */
- if(cpu_is_omap7xx()) {
- udc_resources[1].start = INT_7XX_USB_GENI;
- udc_resources[2].start = INT_7XX_USB_NON_ISO;
- udc_resources[3].start = INT_7XX_USB_ISO;
- }
pdata->udc_device = &udc_device;
}
@@ -238,8 +232,6 @@ static inline void ohci_device_init(struct omap_usb_config *pdata)
if (!IS_ENABLED(CONFIG_USB_OHCI_HCD))
return;
- if (cpu_is_omap7xx())
- ohci_resources[1].start = INT_7XX_USB_HHC_1;
pdata->ohci_device = &ohci_device;
pdata->ocpi_enable = &ocpi_enable;
}
@@ -267,8 +259,6 @@ static struct platform_device otg_device = {
static inline void otg_device_init(struct omap_usb_config *pdata)
{
- if (cpu_is_omap7xx())
- otg_resources[1].start = INT_7XX_USB_OTG;
pdata->otg_device = &otg_device;
}
@@ -297,14 +287,7 @@ static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
}
if (is_device) {
- if (cpu_is_omap7xx()) {
- omap_cfg_reg(AA17_7XX_USB_DM);
- omap_cfg_reg(W16_7XX_USB_PU_EN);
- omap_cfg_reg(W17_7XX_USB_VBUSI);
- omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
- omap_cfg_reg(W19_7XX_USB_DCRST);
- } else
- omap_cfg_reg(W4_USB_PUEN);
+ omap_cfg_reg(W4_USB_PUEN);
}
if (nwires == 2) {
@@ -324,14 +307,11 @@ static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
* - OTG support on this port not yet written
*/
- /* Don't do this for omap7xx -- it causes USB to not work correctly */
- if (!cpu_is_omap7xx()) {
- l = omap_readl(USB_TRANSCEIVER_CTRL);
- l &= ~(7 << 4);
- if (!is_device)
- l |= (3 << 1);
- omap_writel(l, USB_TRANSCEIVER_CTRL);
- }
+ l = omap_readl(USB_TRANSCEIVER_CTRL);
+ l &= ~(7 << 4);
+ if (!is_device)
+ l |= (3 << 1);
+ omap_writel(l, USB_TRANSCEIVER_CTRL);
return 3 << 16;
}
@@ -698,7 +678,7 @@ void __init omap1_usb_init(struct omap_usb_config *_pdata)
ohci_device_init(pdata);
otg_device_init(pdata);
- if (cpu_is_omap7xx() || cpu_is_omap16xx())
+ if (cpu_is_omap16xx())
omap_otg_init(pdata);
else if (cpu_is_omap15xx())
omap_1510_usb_init(pdata);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a8adbb4d478a..821727eefd5a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -105,6 +105,7 @@ config ARCH_OMAP2PLUS
select MACH_OMAP_GENERIC
select MEMORY
select MFD_SYSCON
+ select OMAP_DM_SYSTIMER
select OMAP_DM_TIMER
select OMAP_GPMC
select PINCTRL
@@ -122,7 +123,7 @@ config ARCH_OMAP2PLUS
config OMAP_INTERCONNECT_BARRIER
bool
select ARM_HEAVY_MB
-
+
config ARCH_OMAP
bool
@@ -209,6 +210,7 @@ config SOC_OMAP2420
bool "OMAP2420 support"
depends on ARCH_OMAP2
default y
+ select OMAP_DM_SYSTIMER
select OMAP_DM_TIMER
select SOC_HAS_OMAP2_SDRC
@@ -241,10 +243,10 @@ config MACH_OMAP2_TUSB6010
default y if MACH_NOKIA_N8X0
config MACH_NOKIA_N810
- bool
+ bool
config MACH_NOKIA_N810_WIMAX
- bool
+ bool
config MACH_NOKIA_N8X0
bool "Nokia N800/N810"
@@ -253,17 +255,6 @@ config MACH_NOKIA_N8X0
select MACH_NOKIA_N810
select MACH_NOKIA_N810_WIMAX
-config OMAP3_SDRC_AC_TIMING
- bool "Enable SDRC AC timing register changes"
- depends on ARCH_OMAP3
- help
- If you know that none of your system initiators will attempt to
- access SDRAM during CORE DVFS, select Y here. This should boost
- SDRAM performance at lower CORE OPPs. There are relatively few
- users who will wish to say yes at this point - almost everyone will
- wish to say no. Selecting yes without understanding what is
- going on could result in system crashes;
-
endmenu
endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8306ad686bc8..daf21127c82f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,14 +3,11 @@
# Makefile for the linux kernel.
#
-ccflags-y := -I$(srctree)/$(src)/include \
- -I$(srctree)/arch/arm/plat-omap/include
-
# Common support
obj-y := id.o io.o control.o devices.o fb.o pm.o \
common.o dma.o omap-headsmp.o sram.o
-hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
+hwmod-common = omap_hwmod.o \
omap_hwmod_common_data.o \
omap_hwmod_common_ipblock_data.o \
omap_device.o display.o hdq1w.o \
@@ -83,7 +80,6 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
omap-4-5-pm-common += pm44xx.o
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index bf2b5f87e404..32bcfcf34817 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file contains the address info for various AM33XX modules.
*
* Copyright (C) 2011 Texas Instruments, Inc. - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_AM33XX_H
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 5e86145db0e2..3353b0a923d9 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -22,7 +22,6 @@
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/mmc-omap.h>
#include <linux/mfd/menelaus.h>
-#include <sound/tlv320aic3x.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -505,7 +504,7 @@ static void __init n8x0_mmc_init(void)
}
#else
static struct omap_mmc_platform_data mmc1_data;
-void __init n8x0_mmc_init(void)
+static void __init n8x0_mmc_init(void)
{
}
#endif /* CONFIG_MMC_OMAP */
@@ -567,10 +566,6 @@ struct menelaus_platform_data n8x0_menelaus_platform_data = {
.late_init = n8x0_menelaus_late_init,
};
-struct aic3x_pdata n810_aic33_data = {
- .gpio_reset = 118,
-};
-
static int __init n8x0_late_initcall(void)
{
if (!board_caps)
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 8a9983cb4733..93f6d3cd9525 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -20,6 +20,7 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
+#include <linux/clk/ti.h>
#include <linux/io.h>
#include "clock.h"
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index edf046b470ba..be4557d1fdac 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -39,6 +39,8 @@
#include "sdrc.h"
#include "sram.h"
+static u16 cpu_mask;
+
const struct prcm_config *curr_prcm_set;
const struct prcm_config *rate_table;
@@ -55,7 +57,7 @@ static unsigned long sys_ck_rate;
*
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
*/
-unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
+static unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
unsigned long parent_rate)
{
return curr_prcm_set->mpu_speed;
@@ -68,7 +70,7 @@ unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
* just uses the ARM rates.
*/
-long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
+static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
const struct prcm_config *ptr;
@@ -92,8 +94,8 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
}
/* Sets basic clocks based on the specified rate */
-int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
+static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
{
u32 cur_rate, done_rate, bypass = 0;
const struct prcm_config *prcm;
@@ -167,7 +169,7 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
* global to point to the active rate set when found; otherwise, sets
* it to NULL. No return value;
*/
-void omap2xxx_clkt_vps_check_bootloader_rates(void)
+static void omap2xxx_clkt_vps_check_bootloader_rates(void)
{
const struct prcm_config *prcm = NULL;
unsigned long rate;
@@ -193,7 +195,7 @@ void omap2xxx_clkt_vps_check_bootloader_rates(void)
* sys_ck rate, but before the virt_prcm_set clock rate is
* recalculated. No return value.
*/
-void omap2xxx_clkt_vps_late_init(void)
+static void omap2xxx_clkt_vps_late_init(void)
{
struct clk *c;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 3c1d12dc8ff3..83fae51722a9 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -36,8 +36,6 @@
#include "cm-regbits-34xx.h"
#include "common.h"
-u16 cpu_mask;
-
/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index bbe4b32891bb..41391fa1418a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -63,13 +63,6 @@
extern struct ti_clk_ll_ops omap_clk_ll_ops;
-extern u16 cpu_mask;
-
-extern const struct clkops clkops_omap2_dflt_wait;
-extern const struct clkops clkops_omap2_dflt;
-
-extern struct clk_functions omap2_clk_functions;
-
int __init omap2_clk_setup_ll_ops(void);
void __init ti_clk_init_features(void);
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index a8408f9d0f33..73c011dadfd2 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -12,35 +12,6 @@
#include <linux/clk-provider.h>
#include "clock.h"
-unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
- unsigned long parent_rate);
-int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate);
-long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate);
-unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
- unsigned long parent_rate);
-unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
- unsigned long parent_rate);
-void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
unsigned long omap2xxx_clk_get_core_rate(void);
-u32 omap2xxx_get_sysclkdiv(void);
-void omap2xxx_clk_prepare_for_reboot(void);
-void omap2xxx_clkt_vps_check_bootloader_rates(void);
-void omap2xxx_clkt_vps_late_init(void);
-
-#ifdef CONFIG_SOC_OMAP2420
-int omap2420_clk_init(void);
-#else
-#define omap2420_clk_init() do { } while(0)
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-int omap2430_clk_init(void);
-#else
-#define omap2430_clk_init() do { } while(0)
-#endif
-
-extern struct clk_hw *dclk_hw;
#endif
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
deleted file mode 100644
index 10a9f577dc1a..000000000000
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * OMAP3-common clock function prototypes and macros
- *
- * Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
-
-int omap3xxx_clk_init(void);
-int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
- unsigned long parent_rate);
-
-extern struct clk *sdrc_ick_p;
-extern struct clk *arm_fck_p;
-
-extern const struct clkops clkops_noncore_dpll_ops;
-
-#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 1feb0098705e..d145e7ac709b 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -831,7 +831,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
* -EINVAL if @clkdm is NULL or if clockdomain does not support
* software-initiated sleep; 0 upon success.
*/
-int clkdm_sleep_nolock(struct clockdomain *clkdm)
+static int clkdm_sleep_nolock(struct clockdomain *clkdm)
{
int ret;
@@ -885,7 +885,7 @@ int clkdm_sleep(struct clockdomain *clkdm)
* -EINVAL if @clkdm is NULL or if the clockdomain does not support
* software-controlled wakeup; 0 upon success.
*/
-int clkdm_wakeup_nolock(struct clockdomain *clkdm)
+static int clkdm_wakeup_nolock(struct clockdomain *clkdm)
{
int ret;
@@ -1043,46 +1043,6 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
pwrdm_unlock(clkdm->pwrdm.ptr);
}
-/**
- * clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
- * @clkdm: struct clockdomain *
- *
- * Returns true if clockdomain @clkdm currently has
- * hardware-supervised idle enabled, or false if it does not or if
- * @clkdm is NULL. It is only valid to call this function after
- * clkdm_init() has been called. This function does not actually read
- * bits from the hardware; it instead tests an in-memory flag that is
- * changed whenever the clockdomain code changes the auto-idle mode.
- */
-bool clkdm_in_hwsup(struct clockdomain *clkdm)
-{
- bool ret;
-
- if (!clkdm)
- return false;
-
- ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
-
- return ret;
-}
-
-/**
- * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
- * @clkdm: struct clockdomain *
- *
- * Returns true if clockdomain @clkdm has the
- * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
- * null. More information is available in the documentation for the
- * CLKDM_MISSING_IDLE_REPORTING macro.
- */
-bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
-{
- if (!clkdm)
- return false;
-
- return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
-}
-
/* Public autodep handling functions (deprecated) */
/**
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 68550b23c938..c36fb2721261 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -203,12 +203,8 @@ void clkdm_allow_idle_nolock(struct clockdomain *clkdm);
void clkdm_allow_idle(struct clockdomain *clkdm);
void clkdm_deny_idle_nolock(struct clockdomain *clkdm);
void clkdm_deny_idle(struct clockdomain *clkdm);
-bool clkdm_in_hwsup(struct clockdomain *clkdm);
-bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
-int clkdm_wakeup_nolock(struct clockdomain *clkdm);
int clkdm_wakeup(struct clockdomain *clkdm);
-int clkdm_sleep_nolock(struct clockdomain *clkdm);
int clkdm_sleep(struct clockdomain *clkdm);
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
index b4d5144df445..87f4e927eb18 100644
--- a/arch/arm/mach-omap2/clockdomains33xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* AM33XX Clock Domain data.
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 127dc7ace71f..549cf61487a5 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* TI81XX Clock Domain data.
*
* Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index e7ae2bb515e3..1b97219aaba4 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AM33XX Power Management register bits
*
@@ -5,15 +6,6 @@
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 0827acb60584..1c6d69f4bf49 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -95,103 +95,6 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
}
-/*
- * APLL control
- */
-
-static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
- v &= ~mask;
- v |= m << __ffs(mask);
- omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
-}
-
-void omap2xxx_cm_set_apll54_disable_autoidle(void)
-{
- _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
- OMAP24XX_AUTO_54M_MASK);
-}
-
-void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
-{
- _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
- OMAP24XX_AUTO_54M_MASK);
-}
-
-void omap2xxx_cm_set_apll96_disable_autoidle(void)
-{
- _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
- OMAP24XX_AUTO_96M_MASK);
-}
-
-void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
-{
- _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
- OMAP24XX_AUTO_96M_MASK);
-}
-
-/* Enable an APLL if off */
-static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
-{
- u32 v, m;
-
- m = EN_APLL_LOCKED << enable_bit;
-
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
- if (v & m)
- return 0; /* apll already enabled */
-
- v |= m;
- omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
-
- omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit);
-
- /*
- * REVISIT: Should we return an error code if
- * omap2xxx_cm_wait_module_ready() fails?
- */
- return 0;
-}
-
-/* Stop APLL */
-static void _omap2xxx_apll_disable(u8 enable_bit)
-{
- u32 v;
-
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
- v &= ~(EN_APLL_LOCKED << enable_bit);
- omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
-}
-
-/* Enable an APLL if off */
-int omap2xxx_cm_apll54_enable(void)
-{
- return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT,
- OMAP24XX_ST_54M_APLL_SHIFT);
-}
-
-/* Enable an APLL if off */
-int omap2xxx_cm_apll96_enable(void)
-{
- return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT,
- OMAP24XX_ST_96M_APLL_SHIFT);
-}
-
-/* Stop APLL */
-void omap2xxx_cm_apll54_disable(void)
-{
- _omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT);
-}
-
-/* Stop APLL */
-void omap2xxx_cm_apll96_disable(void)
-{
- _omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT);
-}
-
/**
* omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
* @idlest_reg: CM_IDLEST* virtual address
@@ -242,8 +145,8 @@ static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
* (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
* success or -EBUSY if the module doesn't enable in time.
*/
-int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
- u8 idlest_shift)
+static int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
+ u8 idlest_shift)
{
int ena = 0, i = 0;
u8 cm_idlest_reg;
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 004016d7459e..7cbeff15ffb0 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -46,13 +46,6 @@
extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
-extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
-extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
-extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
-extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
-
-int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
- u8 idlest_shift);
extern int omap2xxx_cm_fclks_active(void);
extern int omap2xxx_cm_mpu_retention_allowed(void);
extern u32 omap2xxx_cm_get_core_clk_src(void);
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 70944b94cc09..6dfc09383160 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -93,11 +93,6 @@ static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}
-extern int omap2xxx_cm_apll54_enable(void);
-extern void omap2xxx_cm_apll54_disable(void);
-extern int omap2xxx_cm_apll96_enable(void);
-extern void omap2xxx_cm_apll96_disable(void);
-
#endif
/* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index ac4882ebdca3..c824d4e3db63 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -1,19 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* AM33XX CM functions
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
- * Reference taken from from OMAP4 cminst44xx.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * Reference taken from OMAP4 cminst44xx.c
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index af63d1892c33..456267a7af71 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -1,17 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AM33XX CM offset macros
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
index bd91223e838e..ffcde1812c6c 100644
--- a/arch/arm/mach-omap2/cm81xx.h
+++ b/arch/arm/mach-omap2/cm81xx.h
@@ -1,17 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Clock domain register offsets for TI81XX.
*
* Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index e2d069fe67f1..87f2c2d2d754 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -320,8 +320,10 @@ int __init omap2_cm_base_init(void)
data = (struct omap_prcm_init_data *)match->data;
ret = of_address_to_resource(np, 0, &res);
- if (ret)
+ if (ret) {
+ of_node_put(np);
return ret;
+ }
if (data->index == TI_CLKM_CM)
mem = &cm_base;
@@ -367,8 +369,10 @@ int __init omap_cm_init(void)
continue;
ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
- if (ret)
+ if (ret) {
+ of_node_put(np);
return ret;
+ }
}
return 0;
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index b23962c38fb2..69694af71475 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -2,12 +2,10 @@
#ifndef __OMAP_COMMON_BOARD_DEVICES__
#define __OMAP_COMMON_BOARD_DEVICES__
-#include <sound/tlv320aic3x.h>
#include <linux/mfd/menelaus.h>
void *n8x0_legacy_init(void);
extern struct menelaus_platform_data n8x0_menelaus_platform_data;
-extern struct aic3x_pdata n810_aic33_data;
#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 32f58f58515e..9d60799e9752 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -38,24 +38,12 @@
#include <asm/hardware/cache-l2x0.h>
#include "i2c.h"
-#include "serial.h"
-
-#include "usb.h"
#define OMAP_INTC_START NR_IRQS
extern int (*omap_pm_soc_init)(void);
int omap_pm_nop_init(void);
-#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
-int omap2_pm_init(void);
-#else
-static inline int omap2_pm_init(void)
-{
- return 0;
-}
-#endif
-
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
int omap3_pm_init(void);
#else
@@ -90,12 +78,6 @@ static inline int amx3_common_pm_init(void)
}
#endif
-extern void omap2_init_common_infrastructure(void);
-
-extern void omap_init_time(void);
-extern void omap3_secure_sync32k_timer_init(void);
-extern void omap3_gptimer_timer_init(void);
-extern void omap4_local_timer_init(void);
#ifdef CONFIG_CACHE_L2X0
int omap_l2_cache_init(void);
#define OMAP_L2C_AUX_CTRL (L2C_AUX_CTRL_SHARED_OVERRIDE | \
@@ -123,9 +105,7 @@ static inline void omap5_realtime_timer_init(void)
void omap2420_init_early(void);
void omap2430_init_early(void);
void omap3430_init_early(void);
-void omap35xx_init_early(void);
void omap3630_init_early(void);
-void omap3_init_early(void); /* Do not use this one */
void am33xx_init_early(void);
void am35xx_init_early(void);
void ti814x_init_early(void);
@@ -136,12 +116,9 @@ void omap4430_init_early(void);
void omap5_init_early(void);
void omap3_init_late(void);
void omap4430_init_late(void);
-void omap2420_init_late(void);
-void omap2430_init_late(void);
void ti81xx_init_late(void);
void am33xx_init_late(void);
void omap5_init_late(void);
-int omap2_common_pm_late_init(void);
void dra7xx_init_early(void);
void dra7xx_init_late(void);
@@ -235,11 +212,6 @@ void __init ti81xx_map_io(void);
} \
})
-extern struct device *omap2_get_mpuss_device(void);
-extern struct device *omap2_get_iva_device(void);
-extern struct device *omap2_get_l3_device(void);
-extern struct device *omap4_get_dsp_device(void);
-
void omap_gic_of_init(void);
#ifdef CONFIG_CACHE_L2X0
@@ -266,7 +238,7 @@ extern void omap4_sar_ram_init(void);
extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap4_mpuss_early_init(void);
extern void omap_do_wfi(void);
-
+extern void omap_interconnect_sync(void);
#ifdef CONFIG_SMP
/* Needed for secondary core boot */
@@ -284,11 +256,13 @@ extern u32 omap4_get_cpu1_ns_pa_addr(void);
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
extern int omap4_mpuss_init(void);
-extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state,
+ bool rcuidle);
extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
#else
static inline int omap4_enter_lowpower(unsigned int cpu,
- unsigned int power_state)
+ unsigned int power_state,
+ bool rcuidle)
{
cpu_do_idle();
return 0;
@@ -360,5 +334,16 @@ extern int omap_dss_reset(struct omap_hwmod *);
/* SoC specific clock initializer */
int omap_clk_init(void);
+#if IS_ENABLED(CONFIG_OMAP_IOMMU)
+int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
+ u8 *pwrst);
+#else
+static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev,
+ bool request, u8 *pwrst)
+{
+ return 0;
+}
+#endif
+
#endif /* __ASSEMBLER__ */
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 062d431fc33a..79860b23030d 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -226,68 +226,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
#endif
-/**
- * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
- * @bootaddr: physical address of the boot loader
- *
- * Set boot address for the boot loader of a supported processor
- * when a power ON sequence occurs.
- */
-void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
-{
- u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
- cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
- cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
- soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
- 0;
-
- if (!offset) {
- pr_err("%s: unsupported omap type\n", __func__);
- return;
- }
-
- omap_ctrl_writel(bootaddr, offset);
-}
-
-/**
- * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
- * @bootmode: 8-bit value to pass to some boot code
- *
- * Sets boot mode for the boot loader of a supported processor
- * when a power ON sequence occurs.
- */
-void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
-{
- u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
- cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
- 0;
-
- if (!offset) {
- pr_err("%s: unsupported omap type\n", __func__);
- return;
- }
-
- omap_ctrl_writel(bootmode, offset);
-}
-
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
-/*
- * Clears the scratchpad contents in case of cold boot-
- * called during bootup
- */
-void omap3_clear_scratchpad_contents(void)
-{
- u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
- void __iomem *v_addr;
- u32 offset = 0;
-
- v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
- if (omap3xxx_prm_clear_global_cold_reset()) {
- for ( ; offset <= max_offset; offset += 0x4)
- writel_relaxed(0x0, (v_addr + offset));
- }
-}
-
/* Populate the scratchpad structure with restore structure */
void omap3_save_scratchpad_contents(void)
{
@@ -769,8 +708,10 @@ int __init omap2_control_base_init(void)
data = (struct control_init_data *)match->data;
mem = of_iomap(np, 0);
- if (!mem)
+ if (!mem) {
+ of_node_put(np);
return -ENOMEM;
+ }
if (data->index == TI_CLKM_CTRL) {
omap2_ctrl_base = mem;
@@ -810,22 +751,24 @@ int __init omap_control_init(void)
if (scm_conf) {
syscon = syscon_node_to_regmap(scm_conf);
- if (IS_ERR(syscon))
- return PTR_ERR(syscon);
+ if (IS_ERR(syscon)) {
+ ret = PTR_ERR(syscon);
+ goto of_node_put;
+ }
if (of_get_child_by_name(scm_conf, "clocks")) {
ret = omap2_clk_provider_init(scm_conf,
data->index,
syscon, NULL);
if (ret)
- return ret;
+ goto of_node_put;
}
} else {
/* No scm_conf found, direct access */
ret = omap2_clk_provider_init(np, data->index, NULL,
data->mem);
if (ret)
- return ret;
+ goto of_node_put;
}
}
@@ -836,16 +779,9 @@ int __init omap_control_init(void)
}
return 0;
-}
-/**
- * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
- *
- * Legacy iomap init for clock provider. Needed only by legacy boot mode,
- * where the base addresses are not parsed from DT, but still required
- * by the clock driver to be setup properly.
- */
-void __init omap3_control_legacy_iomap_init(void)
-{
- omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
+of_node_put:
+ of_node_put(np);
+ return ret;
+
}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index c4ca30ba1790..7e7440533bf9 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -512,8 +512,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
extern void omap_ctrl_writew(u16 val, u16 offset);
extern void omap_ctrl_writel(u32 val, u16 offset);
-extern void omap3_save_scratchpad_contents(void);
-extern void omap3_clear_scratchpad_contents(void);
extern void omap3_restore(void);
extern void omap3_restore_es3(void);
extern void omap3_restore_3630(void);
@@ -521,14 +519,11 @@ extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
extern void omap3_ctrl_write_boot_mode(u8 bootmode);
-extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
-extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
void omap3_ctrl_init(void);
int omap2_control_base_init(void);
int omap_control_init(void);
-void __init omap3_control_legacy_iomap_init(void);
#else
#define omap_ctrl_readb(x) 0
#define omap_ctrl_readw(x) 0
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 090a8aafb25e..2ab5dcbfb7f6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -133,7 +133,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
}
/* Execute ARM wfi */
- omap_sram_idle();
+ omap_sram_idle(true);
/*
* Call idle CPU PM enter notifier chain to restore
@@ -265,6 +265,7 @@ static struct cpuidle_driver omap3_idle_driver = {
.owner = THIS_MODULE,
.states = {
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 2 + 2,
.target_residency = 5,
@@ -272,6 +273,7 @@ static struct cpuidle_driver omap3_idle_driver = {
.desc = "MPU ON + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 10 + 10,
.target_residency = 30,
@@ -279,6 +281,7 @@ static struct cpuidle_driver omap3_idle_driver = {
.desc = "MPU ON + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 50 + 50,
.target_residency = 300,
@@ -286,6 +289,7 @@ static struct cpuidle_driver omap3_idle_driver = {
.desc = "MPU RET + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 1500 + 1800,
.target_residency = 4000,
@@ -293,6 +297,7 @@ static struct cpuidle_driver omap3_idle_driver = {
.desc = "MPU OFF + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 2500 + 7500,
.target_residency = 12000,
@@ -300,6 +305,7 @@ static struct cpuidle_driver omap3_idle_driver = {
.desc = "MPU RET + CORE RET",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 3000 + 8500,
.target_residency = 15000,
@@ -307,6 +313,7 @@ static struct cpuidle_driver omap3_idle_driver = {
.desc = "MPU OFF + CORE RET",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 10000 + 30000,
.target_residency = 30000,
@@ -328,6 +335,7 @@ static struct cpuidle_driver omap3430_idle_driver = {
.owner = THIS_MODULE,
.states = {
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 110 + 162,
.target_residency = 5,
@@ -335,6 +343,7 @@ static struct cpuidle_driver omap3430_idle_driver = {
.desc = "MPU ON + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 106 + 180,
.target_residency = 309,
@@ -342,6 +351,7 @@ static struct cpuidle_driver omap3430_idle_driver = {
.desc = "MPU ON + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 107 + 410,
.target_residency = 46057,
@@ -349,6 +359,7 @@ static struct cpuidle_driver omap3430_idle_driver = {
.desc = "MPU RET + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 121 + 3374,
.target_residency = 46057,
@@ -356,6 +367,7 @@ static struct cpuidle_driver omap3430_idle_driver = {
.desc = "MPU OFF + CORE ON",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 855 + 1146,
.target_residency = 46057,
@@ -363,6 +375,7 @@ static struct cpuidle_driver omap3430_idle_driver = {
.desc = "MPU RET + CORE RET",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 7580 + 4134,
.target_residency = 484329,
@@ -370,6 +383,7 @@ static struct cpuidle_driver omap3430_idle_driver = {
.desc = "MPU OFF + CORE RET",
},
{
+ .flags = CPUIDLE_FLAG_RCU_IDLE,
.enter = omap3_enter_idle_bm,
.exit_latency = 7505 + 15274,
.target_residency = 484329,
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index de37027ad758..df106524d695 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -105,7 +105,7 @@ static int omap_enter_idle_smp(struct cpuidle_device *dev,
}
raw_spin_unlock_irqrestore(&mpu_lock, flag);
- omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+ omap4_enter_lowpower(dev->cpu, cx->cpu_state, true);
raw_spin_lock_irqsave(&mpu_lock, flag);
if (cx->mpu_state_vote == num_online_cpus())
@@ -151,10 +151,10 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
(cx->mpu_logic_state == PWRDM_POWER_OFF);
/* Enter broadcast mode for periodic timers */
- RCU_NONIDLE(tick_broadcast_enable());
+ tick_broadcast_enable();
/* Enter broadcast mode for one-shot timers */
- RCU_NONIDLE(tick_broadcast_enter());
+ tick_broadcast_enter();
/*
* Call idle CPU PM enter notifier chain so that
@@ -166,7 +166,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
if (dev->cpu == 0) {
pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
- RCU_NONIDLE(omap_set_pwrdm_state(mpu_pd, cx->mpu_state));
+ omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
/*
* Call idle CPU cluster PM enter notifier chain
@@ -178,13 +178,13 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
index = 0;
cx = state_ptr + index;
pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
- RCU_NONIDLE(omap_set_pwrdm_state(mpu_pd, cx->mpu_state));
+ omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
mpuss_can_lose_context = 0;
}
}
}
- omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+ omap4_enter_lowpower(dev->cpu, cx->cpu_state, true);
cpu_done[dev->cpu] = true;
/* Wakeup CPU1 only if it is not offlined */
@@ -194,9 +194,9 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
mpuss_can_lose_context)
gic_dist_disable();
- RCU_NONIDLE(clkdm_deny_idle(cpu_clkdm[1]));
- RCU_NONIDLE(omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON));
- RCU_NONIDLE(clkdm_allow_idle(cpu_clkdm[1]));
+ clkdm_deny_idle(cpu_clkdm[1]);
+ omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
+ clkdm_allow_idle(cpu_clkdm[1]);
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
mpuss_can_lose_context) {
@@ -222,7 +222,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
cpu_pm_exit();
cpu_pm_out:
- RCU_NONIDLE(tick_broadcast_exit());
+ tick_broadcast_exit();
fail:
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
@@ -247,7 +247,8 @@ static struct cpuidle_driver omap4_idle_driver = {
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
.exit_latency = 328 + 440,
.target_residency = 960,
- .flags = CPUIDLE_FLAG_COUPLED,
+ .flags = CPUIDLE_FLAG_COUPLED |
+ CPUIDLE_FLAG_RCU_IDLE,
.enter = omap_enter_idle_coupled,
.name = "C2",
.desc = "CPUx OFF, MPUSS CSWR",
@@ -256,7 +257,8 @@ static struct cpuidle_driver omap4_idle_driver = {
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
.exit_latency = 460 + 518,
.target_residency = 1100,
- .flags = CPUIDLE_FLAG_COUPLED,
+ .flags = CPUIDLE_FLAG_COUPLED |
+ CPUIDLE_FLAG_RCU_IDLE,
.enter = omap_enter_idle_coupled,
.name = "C3",
.desc = "CPUx OFF, MPUSS OSWR",
@@ -282,7 +284,8 @@ static struct cpuidle_driver omap5_idle_driver = {
/* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
.exit_latency = 48 + 60,
.target_residency = 100,
- .flags = CPUIDLE_FLAG_TIMER_STOP,
+ .flags = CPUIDLE_FLAG_TIMER_STOP |
+ CPUIDLE_FLAG_RCU_IDLE,
.enter = omap_enter_idle_smp,
.name = "C2",
.desc = "CPUx CSWR, MPUSS CSWR",
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 5a2e198e7db1..8e6d4116d49c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -14,7 +14,6 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/of.h>
-#include <linux/pinctrl/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 21413a9b7b6c..dbec3bb9fbf4 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP2plus display device setup / initialization.
*
* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Senthilvadivu Guruswamy
* Sumit Semwal
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/string.h>
@@ -211,6 +203,7 @@ static int __init omapdss_init_fbdev(void)
node = of_find_node_by_name(NULL, "omap4_padconf_global");
if (node)
omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
+ of_node_put(node);
return 0;
}
@@ -259,11 +252,13 @@ static int __init omapdss_init_of(void)
if (!pdev) {
pr_err("Unable to find DSS platform device\n");
+ of_node_put(node);
return -ENODEV;
}
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
put_device(&pdev->dev);
+ of_node_put(node);
if (r) {
pr_err("Unable to populate DSS submodule devices\n");
return r;
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index dfc9b21ff19b..830cd4e7eb44 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -30,6 +30,7 @@
#include <linux/omap-dma.h>
#include "soc.h"
+#include "common.h"
static const struct omap_dma_reg reg_map[] = {
[REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 59755b5a1ad7..98999aa8cc0c 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -117,7 +117,7 @@ static struct omap_id omap_ids[] __initdata = {
static void __iomem *tap_base;
static u16 tap_prod_id;
-void omap_get_die_id(struct omap_die_id *odi)
+static void omap_get_die_id(struct omap_die_id *odi)
{
if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
diff --git a/arch/arm/mach-omap2/id.h b/arch/arm/mach-omap2/id.h
index d1735f4497e3..ded7392f0526 100644
--- a/arch/arm/mach-omap2/id.h
+++ b/arch/arm/mach-omap2/id.h
@@ -14,6 +14,4 @@ struct omap_die_id {
u32 id_3;
};
-void omap_get_die_id(struct omap_die_id *odi);
-
#endif
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h
deleted file mode 100644
index 54492dbf6973..000000000000
--- a/arch/arm/mach-omap2/include/mach/hardware.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/hardware.h
- */
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
deleted file mode 100644
index ba5282cafa42..000000000000
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/irqs.h
- */
diff --git a/arch/arm/mach-omap2/include/mach/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
deleted file mode 100644
index 7ca1fcff453b..000000000000
--- a/arch/arm/mach-omap2/include/mach/serial.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* OMAP2 serial ports */
-#define OMAP2_UART1_BASE 0x4806a000
-#define OMAP2_UART2_BASE 0x4806c000
-#define OMAP2_UART3_BASE 0x4806e000
-
-/* OMAP3 serial ports */
-#define OMAP3_UART1_BASE OMAP2_UART1_BASE
-#define OMAP3_UART2_BASE OMAP2_UART2_BASE
-#define OMAP3_UART3_BASE 0x49020000
-#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
-#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
-
-/* OMAP4 serial ports */
-#define OMAP4_UART1_BASE OMAP2_UART1_BASE
-#define OMAP4_UART2_BASE OMAP2_UART2_BASE
-#define OMAP4_UART3_BASE 0x48020000
-#define OMAP4_UART4_BASE 0x4806e000
-
-/* TI81XX serial ports */
-#define TI81XX_UART1_BASE 0x48020000
-#define TI81XX_UART2_BASE 0x48022000
-#define TI81XX_UART3_BASE 0x48024000
-
-/* AM3505/3517 UART4 */
-#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
-
-/* AM33XX serial port */
-#define AM33XX_UART1_BASE 0x44E09000
-
-/* OMAP5 serial ports */
-#define OMAP5_UART1_BASE OMAP2_UART1_BASE
-#define OMAP5_UART2_BASE OMAP2_UART2_BASE
-#define OMAP5_UART3_BASE OMAP4_UART3_BASE
-#define OMAP5_UART4_BASE OMAP4_UART4_BASE
-#define OMAP5_UART5_BASE 0x48066000
-#define OMAP5_UART6_BASE 0x48068000
-
-/* External port on Zoom2/3 */
-#define ZOOM_UART_BASE 0x10000000
-#define ZOOM_UART_VIRT 0xfa400000
-
-#define OMAP_PORT_SHIFT 2
-#define ZOOM_PORT_SHIFT 1
-
-#define OMAP24XX_BASE_BAUD (48000000/16)
-
-#ifndef __ASSEMBLER__
-
-struct omap_board_data;
-struct omap_uart_port_info;
-
-extern void omap_serial_init(void);
-extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
-extern void omap_serial_init_port(struct omap_board_data *bdata,
- struct omap_uart_port_info *platform_data);
-#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index fba0c7aa398c..14ec3f78000b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -32,11 +32,8 @@
#include "clockdomain.h"
#include "common.h"
#include "clock.h"
-#include "clock2xxx.h"
-#include "clock3xxx.h"
#include "sdrc.h"
#include "control.h"
-#include "serial.h"
#include "sram.h"
#include "cm2xxx.h"
#include "cm3xxx.h"
@@ -438,11 +435,6 @@ void __init omap2420_init_early(void)
omap_clk_soc_init = omap2420_dt_clk_init;
rate_table = omap2420_rate_table;
}
-
-void __init omap2420_init_late(void)
-{
- omap_pm_soc_init = omap2_pm_init;
-}
#endif
#ifdef CONFIG_SOC_OMAP2430
@@ -462,11 +454,6 @@ void __init omap2430_init_early(void)
omap_clk_soc_init = omap2430_dt_clk_init;
rate_table = omap2430_rate_table;
}
-
-void __init omap2430_init_late(void)
-{
- omap_pm_soc_init = omap2_pm_init;
-}
#endif
/*
@@ -474,7 +461,7 @@ void __init omap2430_init_late(void)
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
*/
#ifdef CONFIG_ARCH_OMAP3
-void __init omap3_init_early(void)
+static void __init omap3_init_early(void)
{
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
@@ -497,12 +484,6 @@ void __init omap3430_init_early(void)
omap_clk_soc_init = omap3430_dt_clk_init;
}
-void __init omap35xx_init_early(void)
-{
- omap3_init_early();
- omap_clk_soc_init = omap3430_dt_clk_init;
-}
-
void __init omap3630_init_early(void)
{
omap3_init_early();
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 93c20bbd7b7e..9c8a85198e16 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -13,6 +13,7 @@
#include "clockdomain.h"
#include "powerdomain.h"
+#include "common.h"
struct pwrdm_link {
struct device *dev;
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 9fba98c2313a..7ad74db951f6 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -33,6 +33,7 @@
* and first to wake-up when MPUSS low power states are excercised
*/
+#include <linux/cpuidle.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
@@ -214,6 +215,7 @@ static void __init save_l2x0_context(void)
* of OMAP4 MPUSS subsystem
* @cpu : CPU ID
* @power_state: Low power state.
+ * @rcuidle: RCU needs to be idled
*
* MPUSS states for the context save:
* save_state =
@@ -222,7 +224,8 @@ static void __init save_l2x0_context(void)
* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
*/
-int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
+__cpuidle int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state,
+ bool rcuidle)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
@@ -268,6 +271,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
cpu_clear_prev_logic_pwrst(cpu);
pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
+
+ if (rcuidle)
+ ct_cpuidle_enter();
+
set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
omap_pm_ops.scu_prepare(cpu, power_state);
l2x0_pwrst_prepare(cpu, save_state);
@@ -283,6 +290,9 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
gic_dist_enable();
+ if (rcuidle)
+ ct_cpuidle_exit();
+
/*
* Restore the CPUx power state to ON otherwise CPUx
* power domain can transitions to programmed low power
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index 11677fc2968f..29c7350b06ab 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -118,13 +118,8 @@ int __init omap_secure_ram_reserve_memblock(void)
return 0;
}
-phys_addr_t omap_secure_ram_mempool_base(void)
-{
- return omap_secure_memblock_base;
-}
-
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
-u32 omap3_save_secure_ram(void __iomem *addr, int size)
+u32 omap3_save_secure_ram(void *addr, int size)
{
static u32 param[5];
u32 ret;
@@ -157,7 +152,7 @@ u32 omap3_save_secure_ram(void __iomem *addr, int size)
* NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
* it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
*/
-u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
+static u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4)
{
static u32 param[5];
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 172069f31616..2517c4a5a0e2 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -70,13 +70,10 @@ extern void omap_smccc_smc(u32 fn, u32 arg);
extern void omap_smc1(u32 fn, u32 arg);
extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
-extern phys_addr_t omap_secure_ram_mempool_base(void);
extern int omap_secure_ram_reserve_memblock(void);
extern u32 save_secure_ram_context(u32 args_pa);
-extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size);
+extern u32 omap3_save_secure_ram(void *save_regs, int size);
-extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
- u32 arg1, u32 arg2, u32 arg3, u32 arg4);
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 5c3845730dbf..d9ed2a5dcd5e 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -139,7 +139,8 @@ static int __init omap4_sram_init(void)
pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
__func__);
else
- sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
+ sram_sync = (void __iomem *)gen_pool_alloc(sram_pool, PAGE_SIZE);
+ of_node_put(np);
return 0;
}
@@ -314,10 +315,12 @@ void __init omap_gic_of_init(void)
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
gic_dist_base_addr = of_iomap(np, 0);
+ of_node_put(np);
WARN_ON(!gic_dist_base_addr);
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
twd_base = of_iomap(np, 0);
+ of_node_put(np);
WARN_ON(!twd_base);
skip_errata_init:
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 56d6814bec26..4afa2f08e668 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -39,6 +39,12 @@
#include "omap_device.h"
#include "omap_hwmod.h"
+static struct omap_device *omap_device_alloc(struct platform_device *pdev,
+ struct omap_hwmod **ohs, int oh_cnt);
+static void omap_device_delete(struct omap_device *od);
+static struct dev_pm_domain omap_device_fail_pm_domain;
+static struct dev_pm_domain omap_device_pm_domain;
+
/* Private functions */
static void _add_clkdev(struct omap_device *od, const char *clk_alias,
@@ -96,9 +102,6 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
* omap_device, this function adds an entry in the clkdev table of the
* form <dev-id=dev_name, con-id=role> if it does not exist already.
*
- * The function is called from inside omap_device_build_ss(), after
- * omap_device_register.
- *
* This allows drivers to get a pointer to its optional clocks based on its role
* by calling clk_get(<dev*>, <role>).
* In the case of the main clock, a "fck" alias is used.
@@ -289,34 +292,6 @@ static int _omap_device_idle_hwmods(struct omap_device *od)
/* Public functions for use by core code */
/**
- * omap_device_get_context_loss_count - get lost context count
- * @pdev: The platform device to update.
- *
- * Using the primary hwmod, query the context loss count for this
- * device.
- *
- * Callers should consider context for this device lost any time this
- * function returns a value different than the value the caller got
- * the last time it called this function.
- *
- * If any hwmods exist for the omap_device associated with @pdev,
- * return the context loss counter for that hwmod, otherwise return
- * zero.
- */
-int omap_device_get_context_loss_count(struct platform_device *pdev)
-{
- struct omap_device *od;
- u32 ret = 0;
-
- od = to_omap_device(pdev);
-
- if (od->hwmods_cnt)
- ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
-
- return ret;
-}
-
-/**
* omap_device_alloc - allocate an omap_device
* @pdev: platform_device that will be included in this omap_device
* @ohs: ptr to the omap_hwmod for this omap_device
@@ -327,7 +302,7 @@ int omap_device_get_context_loss_count(struct platform_device *pdev)
*
* Returns an struct omap_device pointer or ERR_PTR() on error;
*/
-struct omap_device *omap_device_alloc(struct platform_device *pdev,
+static struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt)
{
int ret = -ENOMEM;
@@ -364,7 +339,7 @@ oda_exit1:
return ERR_PTR(ret);
}
-void omap_device_delete(struct omap_device *od)
+static void omap_device_delete(struct omap_device *od)
{
if (!od)
return;
@@ -456,14 +431,14 @@ static int _od_resume_noirq(struct device *dev)
#define _od_resume_noirq NULL
#endif
-struct dev_pm_domain omap_device_fail_pm_domain = {
+static struct dev_pm_domain omap_device_fail_pm_domain = {
.ops = {
SET_RUNTIME_PM_OPS(_od_fail_runtime_suspend,
_od_fail_runtime_resume, NULL)
}
};
-struct dev_pm_domain omap_device_pm_domain = {
+static struct dev_pm_domain omap_device_pm_domain = {
.ops = {
SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
NULL)
@@ -473,23 +448,6 @@ struct dev_pm_domain omap_device_pm_domain = {
}
};
-/**
- * omap_device_register - register an omap_device with one omap_hwmod
- * @pdev: the platform device (omap_device) to register.
- *
- * Register the omap_device structure. This currently just calls
- * platform_device_register() on the underlying platform_device.
- * Returns the return value of platform_device_register().
- */
-int omap_device_register(struct platform_device *pdev)
-{
- pr_debug("omap_device: %s: registering\n", pdev->name);
-
- dev_pm_domain_set(&pdev->dev, &omap_device_pm_domain);
- return platform_device_add(pdev);
-}
-
-
/* Public functions for use by device drivers through struct platform_data */
/**
@@ -612,38 +570,6 @@ int omap_device_deassert_hardreset(struct platform_device *pdev,
return ret;
}
-/**
- * omap_device_get_by_hwmod_name() - convert a hwmod name to
- * device pointer.
- * @oh_name: name of the hwmod device
- *
- * Returns back a struct device * pointer associated with a hwmod
- * device represented by a hwmod_name
- */
-struct device *omap_device_get_by_hwmod_name(const char *oh_name)
-{
- struct omap_hwmod *oh;
-
- if (!oh_name) {
- WARN(1, "%s: no hwmod name!\n", __func__);
- return ERR_PTR(-EINVAL);
- }
-
- oh = omap_hwmod_lookup(oh_name);
- if (!oh) {
- WARN(1, "%s: no hwmod for %s\n", __func__,
- oh_name);
- return ERR_PTR(-ENODEV);
- }
- if (!oh->od) {
- WARN(1, "%s: no omap_device for %s\n", __func__,
- oh_name);
- return ERR_PTR(-ENODEV);
- }
-
- return &oh->od->pdev->dev;
-}
-
static struct notifier_block platform_nb = {
.notifier_call = _omap_device_notifier_call,
};
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index f77e76a7841a..aa8096ecb23c 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -25,9 +25,6 @@
#include "omap_hwmod.h"
-extern struct dev_pm_domain omap_device_pm_domain;
-extern struct dev_pm_domain omap_device_fail_pm_domain;
-
/* omap_device._state values */
#define OMAP_DEVICE_STATE_UNKNOWN 0
#define OMAP_DEVICE_STATE_ENABLED 1
@@ -66,18 +63,6 @@ struct omap_device {
int omap_device_enable(struct platform_device *pdev);
int omap_device_idle(struct platform_device *pdev);
-/* Core code interface */
-
-struct omap_device *omap_device_alloc(struct platform_device *pdev,
- struct omap_hwmod **ohs, int oh_cnt);
-void omap_device_delete(struct omap_device *od);
-int omap_device_register(struct platform_device *pdev);
-
-struct device *omap_device_get_by_hwmod_name(const char *oh_name);
-
-/* OMAP PM interface */
-int omap_device_get_context_loss_count(struct platform_device *pdev);
-
/* Other */
int omap_device_assert_hardreset(struct platform_device *pdev,
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 31d1a21f6041..aac4c4ee2528 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -706,9 +706,7 @@ static const struct of_device_id ti_clkctrl_match_table[] __initconst = {
static int __init _setup_clkctrl_provider(struct device_node *np)
{
- const __be32 *addrp;
struct clkctrl_provider *provider;
- u64 size;
int i;
provider = memblock_alloc(sizeof(*provider), SMP_CACHE_BYTES);
@@ -717,8 +715,7 @@ static int __init _setup_clkctrl_provider(struct device_node *np)
provider->node = np;
- provider->num_addrs =
- of_property_count_elems_of_size(np, "reg", sizeof(u32)) / 2;
+ provider->num_addrs = of_address_count(np);
provider->addr =
memblock_alloc(sizeof(void *) * provider->num_addrs,
@@ -733,11 +730,11 @@ static int __init _setup_clkctrl_provider(struct device_node *np)
return -ENOMEM;
for (i = 0; i < provider->num_addrs; i++) {
- addrp = of_get_address(np, i, &size, NULL);
- provider->addr[i] = (u32)of_translate_address(np, addrp);
- provider->size[i] = size;
- pr_debug("%s: %pOF: %x...%x\n", __func__, np, provider->addr[i],
- provider->addr[i] + provider->size[i]);
+ struct resource res;
+ of_address_to_resource(np, i, &res);
+ provider->addr[i] = res.start;
+ provider->size[i] = resource_size(&res);
+ pr_debug("%s: %pOF: %pR\n", __func__, np, &res);
}
list_add(&provider->link, &clkctrl_providers);
@@ -2322,11 +2319,11 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
static void __init parse_module_flags(struct omap_hwmod *oh,
struct device_node *np)
{
- if (of_find_property(np, "ti,no-reset-on-init", NULL))
+ if (of_property_read_bool(np, "ti,no-reset-on-init"))
oh->flags |= HWMOD_INIT_NO_RESET;
- if (of_find_property(np, "ti,no-idle-on-init", NULL))
+ if (of_property_read_bool(np, "ti,no-idle-on-init"))
oh->flags |= HWMOD_INIT_NO_IDLE;
- if (of_find_property(np, "ti,no-idle", NULL))
+ if (of_property_read_bool(np, "ti,no-idle"))
oh->flags |= HWMOD_NO_IDLE;
}
@@ -3054,6 +3051,8 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
return 0;
}
+static int __init omap_hwmod_setup_one(const char *oh_name);
+
/**
* _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
* @oh: pointer to the hwmod currently being set up (usually not the MPU)
@@ -3084,7 +3083,7 @@ static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
* registered omap_hwmod. Also calls _setup() on each hwmod. Returns
* -EINVAL upon error or 0 upon success.
*/
-int __init omap_hwmod_setup_one(const char *oh_name)
+static int __init omap_hwmod_setup_one(const char *oh_name)
{
struct omap_hwmod *oh;
@@ -3455,7 +3454,7 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
}
if (list_empty(&oh->slave_ports)) {
- oi = kcalloc(1, sizeof(*oi), GFP_KERNEL);
+ oi = kzalloc(sizeof(*oi), GFP_KERNEL);
if (!oi)
goto out_free_class;
@@ -3764,55 +3763,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
*/
/**
- * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
- * @oh: struct omap_hwmod *
- *
- * Return the powerdomain pointer associated with the OMAP module
- * @oh's main clock. If @oh does not have a main clk, return the
- * powerdomain associated with the interface clock associated with the
- * module's MPU port. (XXX Perhaps this should use the SDMA port
- * instead?) Returns NULL on error, or a struct powerdomain * on
- * success.
- */
-struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
-{
- struct clk *c;
- struct omap_hwmod_ocp_if *oi;
- struct clockdomain *clkdm;
- struct clk_hw_omap *clk;
- struct clk_hw *hw;
-
- if (!oh)
- return NULL;
-
- if (oh->clkdm)
- return oh->clkdm->pwrdm.ptr;
-
- if (oh->_clk) {
- c = oh->_clk;
- } else {
- oi = _find_mpu_rt_port(oh);
- if (!oi)
- return NULL;
- c = oi->_clk;
- }
-
- hw = __clk_get_hw(c);
- if (!hw)
- return NULL;
-
- clk = to_clk_hw_omap(hw);
- if (!clk)
- return NULL;
-
- clkdm = clk->clkdm;
- if (!clkdm)
- return NULL;
-
- return clkdm->pwrdm.ptr;
-}
-
-/**
* omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
* @oh: struct omap_hwmod *
*
@@ -3978,32 +3928,6 @@ ohsps_unlock:
}
/**
- * omap_hwmod_get_context_loss_count - get lost context count
- * @oh: struct omap_hwmod *
- *
- * Returns the context loss count of associated @oh
- * upon success, or zero if no context loss data is available.
- *
- * On OMAP4, this queries the per-hwmod context loss register,
- * assuming one exists. If not, or on OMAP2/3, this queries the
- * enclosing powerdomain context loss count.
- */
-int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
-{
- struct powerdomain *pwrdm;
- int ret = 0;
-
- if (soc_ops.get_context_lost)
- return soc_ops.get_context_lost(oh);
-
- pwrdm = omap_hwmod_get_pwrdm(oh);
- if (pwrdm)
- ret = pwrdm_get_context_loss_count(pwrdm);
-
- return ret;
-}
-
-/**
* omap_hwmod_init - initialize the hwmod code
*
* Sets up some function pointers needed by the hwmod code to operate on the
@@ -4054,18 +3978,3 @@ void __init omap_hwmod_init(void)
inited = true;
}
-
-/**
- * omap_hwmod_get_main_clk - get pointer to main clock name
- * @oh: struct omap_hwmod *
- *
- * Returns the main clock name assocated with @oh upon success,
- * or NULL if @oh is NULL.
- */
-const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh)
-{
- if (!oh)
- return NULL;
-
- return oh->main_clk;
-}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 6962a8d267e7..dcab7a01c10e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -615,7 +615,6 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name);
int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
void *data);
-int __init omap_hwmod_setup_one(const char *name);
int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
struct device_node *np,
struct resource *res);
@@ -638,12 +637,6 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
int omap_hwmod_softreset(struct omap_hwmod *oh);
-int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
-int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
-int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
- const char *name, struct resource *res);
-
-struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
int omap_hwmod_for_each_by_class(const char *classname,
@@ -652,12 +645,9 @@ int omap_hwmod_for_each_by_class(const char *classname,
void *user);
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
-int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
extern void __init omap_hwmod_init(void);
-const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
-
#else /* CONFIG_OMAP_HWMOD */
static inline int
@@ -670,25 +660,14 @@ omap_hwmod_for_each_by_class(const char *classname,
#endif /* CONFIG_OMAP_HWMOD */
/*
- *
- */
-
-void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
-void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
-
-/*
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out
*/
extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
-extern int omap44xx_hwmod_init(void);
-extern int am33xx_hwmod_init(void);
extern int dm814x_hwmod_init(void);
extern int dm816x_hwmod_init(void);
-extern int dra7xx_hwmod_init(void);
-int am43xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 558fae4375ba..dbd9dc9f0962 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -22,7 +22,6 @@
#include "prm-regbits-24xx.h"
#include "i2c.h"
#include "mmc.h"
-#include "serial.h"
#include "wd_timer.h"
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 2581b8a5f866..67f1f38909d9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -62,7 +62,7 @@ struct omap_hwmod_class iva_hwmod_class = {
.name = "iva",
};
-struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
+static struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x14,
.syss_offs = 0x18,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 518e877bb2a1..761d34914ed9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -13,7 +13,6 @@
#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"
-#include "serial.h"
#include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 9156f2bfbc8d..4982e04ead53 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -30,7 +30,7 @@ static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
-struct omap_hwmod_class omap2_dispc_hwmod_class = {
+static struct omap_hwmod_class omap2_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2_dispc_sysc,
};
@@ -47,7 +47,7 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
-struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
+static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
.name = "timer",
.sysc = &omap2xxx_timer_sysc,
};
@@ -67,7 +67,7 @@ static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
-struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
+static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2xxx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
@@ -189,12 +189,6 @@ struct omap_hwmod omap2xxx_mpu_hwmod = {
.main_clk = "mpu_ck",
};
-/* IVA2 */
-struct omap_hwmod omap2xxx_iva_hwmod = {
- .name = "iva",
- .class = &iva_hwmod_class,
-};
-
/* timer3 */
struct omap_hwmod omap2xxx_timer3_hwmod = {
.name = "timer3",
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index b6c7d98a9eff..cb33f0382a90 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -27,7 +27,6 @@
#include "i2c.h"
#include "wd_timer.h"
-#include "serial.h"
/*
* OMAP3xxx hardware module integration data
@@ -1135,65 +1134,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
.class = &omap34xx_mcspi_class,
};
-/* usbhsotg */
-static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
- .rev_offs = 0x0400,
- .sysc_offs = 0x0404,
- .syss_offs = 0x0408,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class usbotg_class = {
- .name = "usbotg",
- .sysc = &omap3xxx_usbhsotg_sysc,
-};
-
-/* usb_otg_hs */
-
-static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
- .name = "usb_otg_hs",
- .main_clk = "hsotgusb_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
- },
- },
- .class = &usbotg_class,
-
- /*
- * Erratum ID: i479 idle_req / idle_ack mechanism potentially
- * broken when autoidle is enabled
- * workaround is to disable the autoidle bit at module level.
- *
- * Enabling the device in any other MIDLEMODE setting but force-idle
- * causes core_pwrdm not enter idle states at least on OMAP3630.
- * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
- * signal when MIDLEMODE is set to force-idle.
- */
- .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
- HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
-};
-
-/* usb_otg_hs */
-
-static struct omap_hwmod_class am35xx_usbotg_class = {
- .name = "am35xx_usbotg",
-};
-
-static struct omap_hwmod am35xx_usbhsotg_hwmod = {
- .name = "am35x_otg_hs",
- .main_clk = "hsotgusb_fck",
- .class = &am35xx_usbotg_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
/* MMC/SD/SDIO common */
static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
.rev_offs = 0x1fc,
@@ -1561,22 +1501,6 @@ static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3_core -> usbhsotg interface */
-static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
- .master = &omap3xxx_usbhsotg_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .clk = "core_l3_ick",
- .user = OCP_USER_MPU,
-};
-
-/* l3_core -> am35xx_usbhsotg interface */
-static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
- .master = &am35xx_usbhsotg_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .clk = "hsotgusb_ick",
- .user = OCP_USER_MPU,
-};
-
/* l3_core -> sad2d interface */
static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
.master = &omap3xxx_sad2d_hwmod,
@@ -1758,24 +1682,6 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
.user = OCP_USER_MPU,
};
-
-/* l4_core -> usbhsotg */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_usbhsotg_hwmod,
- .clk = "l4_ick",
- .user = OCP_USER_MPU,
-};
-
-
-/* l4_core -> usbhsotg */
-static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &am35xx_usbhsotg_hwmod,
- .clk = "hsotgusb_ick",
- .user = OCP_USER_MPU,
-};
-
/* L4_WKUP -> L4_SEC interface */
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
.master = &omap3xxx_l4_wkup_hwmod,
@@ -2465,8 +2371,6 @@ static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_dss__l3,
&omap3xxx_l4_core__dss,
- &omap3xxx_usbhsotg__l3,
- &omap3xxx_l4_core__usbhsotg,
&omap3xxx_usb_host_hs__l3_main_2,
&omap3xxx_l4_core__usb_host_hs,
&omap3xxx_l4_core__usb_tll_hs,
@@ -2509,8 +2413,6 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__dss,
&omap36xx_l4_core__sr1,
&omap36xx_l4_core__sr2,
- &omap3xxx_usbhsotg__l3,
- &omap3xxx_l4_core__usbhsotg,
&omap3xxx_l4_core__mailbox,
&omap3xxx_usb_host_hs__l3_main_2,
&omap3xxx_l4_core__usb_host_hs,
@@ -2528,8 +2430,6 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_dss__l3,
&omap3xxx_l4_core__dss,
- &am35xx_usbhsotg__l3,
- &am35xx_l4_core__usbhsotg,
&am35xx_l4_core__uart4,
&omap3xxx_usb_host_hs__l3_main_2,
&omap3xxx_l4_core__usb_host_hs,
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 450ab990c66a..9b5c728fb7da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -1,18 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* DM81xx hwmod data.
*
* Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <linux/types.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 0045e6680a63..69dddc53e1d8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -20,7 +20,6 @@ extern struct omap_hwmod omap2xxx_l3_main_hwmod;
extern struct omap_hwmod omap2xxx_l4_core_hwmod;
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
extern struct omap_hwmod omap2xxx_mpu_hwmod;
-extern struct omap_hwmod omap2xxx_iva_hwmod;
extern struct omap_hwmod omap2xxx_timer3_hwmod;
extern struct omap_hwmod omap2xxx_timer4_hwmod;
extern struct omap_hwmod omap2xxx_timer5_hwmod;
@@ -60,7 +59,6 @@ extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
-extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
@@ -86,14 +84,10 @@ extern struct omap_hwmod_class mpu_hwmod_class;
extern struct omap_hwmod_class iva_hwmod_class;
extern struct omap_hwmod_class omap2_uart_class;
extern struct omap_hwmod_class omap2_dss_hwmod_class;
-extern struct omap_hwmod_class omap2_dispc_hwmod_class;
extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
-extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc;
extern struct omap_hwmod_class omap2_hdq1w_class;
-extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
-extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;
diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c
deleted file mode 100644
index 143623bb056d..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_reset.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * OMAP IP block custom reset and preprogramming stubs
- *
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * A small number of IP blocks need custom reset and preprogramming
- * functions. The stubs in this file provide a standard way for the
- * hwmod code to call these functions, which are to be located under
- * drivers/.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-
-#include "omap_hwmod.h"
-#include "common.h"
-
-#define OMAP_RTC_STATUS_REG 0x44
-#define OMAP_RTC_KICK0_REG 0x6c
-#define OMAP_RTC_KICK1_REG 0x70
-
-#define OMAP_RTC_KICK0_VALUE 0x83E70B13
-#define OMAP_RTC_KICK1_VALUE 0x95A4F1E0
-#define OMAP_RTC_STATUS_BUSY BIT(0)
-#define OMAP_RTC_MAX_READY_TIME 50
-
-/**
- * omap_rtc_wait_not_busy - Wait for the RTC BUSY flag
- * @oh: struct omap_hwmod *
- *
- * For updating certain RTC registers, the MPU must wait
- * for the BUSY status in OMAP_RTC_STATUS_REG to become zero.
- * Once the BUSY status is zero, there is a 15 microseconds access
- * period in which the MPU can program.
- */
-static void omap_rtc_wait_not_busy(struct omap_hwmod *oh)
-{
- int i;
-
- /* BUSY may stay active for 1/32768 second (~30 usec) */
- omap_test_timeout(omap_hwmod_read(oh, OMAP_RTC_STATUS_REG)
- & OMAP_RTC_STATUS_BUSY, OMAP_RTC_MAX_READY_TIME, i);
- /* now we have ~15 microseconds to read/write various registers */
-}
-
-/**
- * omap_hwmod_rtc_unlock - Unlock the Kicker mechanism.
- * @oh: struct omap_hwmod *
- *
- * RTC IP have kicker feature. This prevents spurious writes to its registers.
- * In order to write into any of the RTC registers, KICK values has te be
- * written in respective KICK registers. This is needed for hwmod to write into
- * sysconfig register.
- */
-void omap_hwmod_rtc_unlock(struct omap_hwmod *oh)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- omap_rtc_wait_not_busy(oh);
- omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG);
- omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG);
- local_irq_restore(flags);
-}
-
-/**
- * omap_hwmod_rtc_lock - Lock the Kicker mechanism.
- * @oh: struct omap_hwmod *
- *
- * RTC IP have kicker feature. This prevents spurious writes to its registers.
- * Once the RTC registers are written, KICK mechanism needs to be locked,
- * in order to prevent any spurious writes. This function locks back the RTC
- * registers once hwmod completes its write into sysconfig register.
- */
-void omap_hwmod_rtc_lock(struct omap_hwmod *oh)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- omap_rtc_wait_not_busy(oh);
- omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG);
- omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG);
- local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index 533dd643069a..ed84fe95e857 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* OMAP SoC specific OPP Data helpers
*
@@ -6,15 +7,6 @@
* Kevin Hilman
* Copyright (C) 2010 Nokia Corporation.
* Eduardo Valentin
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
#define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
@@ -79,11 +71,6 @@ struct omap_opp_def {
.vp_errgain = _errgain \
}
-/* Use this to initialize the default table */
-extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
- u32 opp_def_size);
-
-
extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
extern struct omap_volt_data omap34xx_vddcore_volt_data[];
extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 6f6a6a66c981..21c6e7929d37 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -19,7 +19,6 @@
#include "soc.h"
#include "control.h"
-#include "usb.h"
#define CONTROL_DEV_CONF 0x300
#define PHY_PD 0x1
@@ -52,89 +51,3 @@ static int __init omap4430_phy_power_down(void)
return 0;
}
omap_early_initcall(omap4430_phy_power_down);
-
-void am35x_musb_reset(void)
-{
- u32 regval;
-
- /* Reset the musb interface */
- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
- regval |= AM35XX_USBOTGSS_SW_RST;
- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-
- regval &= ~AM35XX_USBOTGSS_SW_RST;
- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-
- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-}
-
-void am35x_musb_phy_power(u8 on)
-{
- unsigned long timeout = jiffies + msecs_to_jiffies(100);
- u32 devconf2;
-
- if (on) {
- /*
- * Start the on-chip PHY and its PLL.
- */
- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
-
- devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
- devconf2 |= CONF2_PHY_PLLON;
-
- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
-
- pr_info("Waiting for PHY clock good...\n");
- while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
- & CONF2_PHYCLKGD)) {
- cpu_relax();
-
- if (time_after(jiffies, timeout)) {
- pr_err("musb PHY clock good timed out\n");
- break;
- }
- }
- } else {
- /*
- * Power down the on-chip PHY.
- */
- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
-
- devconf2 &= ~CONF2_PHY_PLLON;
- devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
- }
-}
-
-void am35x_musb_clear_irq(void)
-{
- u32 regval;
-
- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
- regval |= AM35XX_USBOTGSS_INT_CLR;
- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-void am35x_set_mode(u8 musb_mode)
-{
- u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
-
- devconf2 &= ~CONF2_OTGMODE;
- switch (musb_mode) {
- case MUSB_HOST: /* Force VBUS valid, ID = 0 */
- devconf2 |= CONF2_FORCE_HOST;
- break;
- case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
- devconf2 |= CONF2_FORCE_DEVICE;
- break;
- case MUSB_OTG: /* Don't override the VBUS/ID comparators */
- devconf2 |= CONF2_NO_OVERRIDE;
- break;
- default:
- pr_info("Unsupported mode %u\n", musb_mode);
- }
-
- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
-}
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index b610c5fb423b..90257e2fb3d6 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP3 OPP table definitions.
*
@@ -7,15 +8,6 @@
* Copyright (C) 2010-2011 Nokia Corporation.
* Eduardo Valentin
* Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/module.h>
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index d937c5ef41c6..a9851886017d 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP4 OPP table definitions.
*
@@ -8,15 +9,6 @@
* Copyright (C) 2010-2011 Nokia Corporation.
* Eduardo Valentin
* Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/module.h>
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index e7fd29a502a0..04208cc52784 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -6,11 +6,11 @@
*/
#include <linux/clk.h>
#include <linux/davinci_emac.h>
+#include <linux/gpio/consumer.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
-#include <linux/wl12xx.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/power/smartreflex.h>
@@ -43,17 +43,6 @@ struct pdata_init {
static struct of_dev_auxdata omap_auxdata_lookup[];
static struct twl4030_gpio_platform_data twl_gpio_auxdata;
-#if IS_ENABLED(CONFIG_OMAP_IOMMU)
-int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
- u8 *pwrst);
-#else
-static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev,
- bool request, u8 *pwrst)
-{
- return 0;
-}
-#endif
-
#ifdef CONFIG_MACH_NOKIA_N8X0
static void __init omap2420_n8x0_legacy_init(void)
{
@@ -120,7 +109,7 @@ static int omap3_sbc_t3730_twl_callback(struct device *dev,
if (res)
return res;
- gpio_export(gpio, 0);
+ gpiod_export(gpio_to_desc(gpio), 0);
return 0;
}
@@ -135,7 +124,7 @@ static void __init omap3_sbc_t3x_usb_hub_init(int gpio, char *hub_name)
return;
}
- gpio_export(gpio, 0);
+ gpiod_export(gpio_to_desc(gpio), 0);
udelay(10);
gpio_set_value(gpio, 1);
@@ -212,8 +201,8 @@ static void __init omap3_sbc_t3517_wifi_init(void)
return;
}
- gpio_export(cm_t3517_wlan_gpios[0].gpio, 0);
- gpio_export(cm_t3517_wlan_gpios[1].gpio, 0);
+ gpiod_export(gpio_to_desc(cm_t3517_wlan_gpios[0].gpio), 0);
+ gpiod_export(gpio_to_desc(cm_t3517_wlan_gpios[1].gpio), 0);
msleep(100);
gpio_set_value(cm_t3517_wlan_gpios[1].gpio, 0);
@@ -451,7 +440,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
#ifdef CONFIG_MACH_NOKIA_N8X0
OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
- OF_DEV_AUXDATA("tlv320aic3x", 0x18, "2-0018", &n810_aic33_data),
#endif
#ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
@@ -551,6 +539,8 @@ pdata_quirks_init_clocks(const struct of_device_id *omap_dt_match_table)
of_platform_populate(np, omap_dt_match_table,
omap_auxdata_lookup, NULL);
+
+ of_node_put(np);
}
}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index da829a90fe8c..700869c9eae1 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -54,12 +54,6 @@ static struct omap2_oscillator oscillator = {
.shutdown_time = ULONG_MAX,
};
-void omap_pm_setup_oscillator(u32 tstart, u32 tshut)
-{
- oscillator.startup_time = tstart;
- oscillator.shutdown_time = tshut;
-}
-
void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
{
if (!tstart || !tshut)
@@ -140,7 +134,7 @@ int __maybe_unused omap_pm_nop_init(void)
int (*omap_pm_soc_init)(void);
-int __init omap2_common_pm_late_init(void)
+static int __init omap2_common_pm_late_init(void)
{
int error;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 80e84ae66aee..f97ff93f2fb4 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -29,23 +29,9 @@ static inline int omap4_idle_init(void)
extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
-extern void omap_sram_idle(void);
+extern void omap_sram_idle(bool rcuidle);
extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
-#if defined(CONFIG_PM_OPP)
-extern int omap3_opp_init(void);
-extern int omap4_opp_init(void);
-#else
-static inline int omap3_opp_init(void)
-{
- return -EINVAL;
-}
-static inline int omap4_opp_init(void)
-{
- return -EINVAL;
-}
-#endif
-
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
@@ -58,9 +44,6 @@ extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
#endif /* CONFIG_PM_DEBUG */
/* 24xx */
-extern void omap24xx_idle_loop_suspend(void);
-extern unsigned int omap24xx_idle_loop_suspend_sz;
-
extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
void __iomem *sdrc_power);
extern unsigned int omap24xx_cpu_suspend_sz;
@@ -110,20 +93,16 @@ extern u16 pm44xx_errata;
#ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void);
-extern void omap_enable_smartreflex_on_init(void);
#else
static inline int omap_devinit_smartreflex(void)
{
return -EINVAL;
}
-
-static inline void omap_enable_smartreflex_on_init(void) {}
#endif
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
-extern int omap3_twl_set_sr_bit(bool enable);
#else
static inline int omap3_twl_init(void)
{
@@ -145,13 +124,9 @@ static inline int omap4_cpcap_init(void)
#endif
#ifdef CONFIG_PM
-extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
-extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
#else
-static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; }
-static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
#endif
#ifdef CONFIG_SUSPEND
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
deleted file mode 100644
index 6953c47d8dc6..000000000000
--- a/arch/arm/mach-omap2/pm24xx.c
+++ /dev/null
@@ -1,312 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * OMAP2 Power Management Routines
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- * Copyright (C) 2006-2008 Nokia Corporation
- *
- * Written by:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Tony Lindgren
- * Juha Yrjola
- * Amit Kucheria <amit.kucheria@nokia.com>
- * Igor Stoppa <igor.stoppa@nokia.com>
- *
- * Based on pm.c for omap1
- */
-
-#include <linux/cpu_pm.h>
-#include <linux/suspend.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/interrupt.h>
-#include <linux/sysfs.h>
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/irq.h>
-#include <linux/time.h>
-
-#include <asm/fncpy.h>
-
-#include <asm/mach/time.h>
-#include <asm/mach/irq.h>
-#include <asm/mach-types.h>
-#include <asm/system_misc.h>
-
-#include <linux/omap-dma.h>
-
-#include "soc.h"
-#include "common.h"
-#include "clock.h"
-#include "prm2xxx.h"
-#include "prm-regbits-24xx.h"
-#include "cm2xxx.h"
-#include "cm-regbits-24xx.h"
-#include "sdrc.h"
-#include "sram.h"
-#include "pm.h"
-#include "control.h"
-#include "powerdomain.h"
-#include "clockdomain.h"
-
-static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
- void __iomem *sdrc_power);
-
-static struct powerdomain *mpu_pwrdm, *core_pwrdm;
-static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
-
-static struct clk *osc_ck, *emul_ck;
-
-static int omap2_enter_full_retention(void)
-{
- u32 l;
-
- /* There is 1 reference hold for all children of the oscillator
- * clock, the following will remove it. If no one else uses the
- * oscillator itself it will be disabled if/when we enter retention
- * mode.
- */
- clk_disable(osc_ck);
-
- /* Clear old wake-up events */
- /* REVISIT: These write to reserved bits? */
- omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
- omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
- omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
-
- pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
- pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
-
- /* Workaround to kill USB */
- l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
- omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
-
- /* One last check for pending IRQs to avoid extra latency due
- * to sleeping unnecessarily. */
- if (omap_irq_pending())
- goto no_sleep;
-
- /* Jump to SRAM suspend code */
- omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
- OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
- OMAP_SDRC_REGADDR(SDRC_POWER));
-
-no_sleep:
- clk_enable(osc_ck);
-
- /* clear CORE wake-up events */
- omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
- omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
-
- /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
- omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
-
- /* MPU domain wake events */
- omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
-
- omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
-
- pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
- pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
-
- return 0;
-}
-
-static int sti_console_enabled;
-
-static int omap2_allow_mpu_retention(void)
-{
- if (!omap2xxx_cm_mpu_retention_allowed())
- return 0;
- if (sti_console_enabled)
- return 0;
-
- return 1;
-}
-
-static void omap2_enter_mpu_retention(void)
-{
- const int zero = 0;
-
- /* The peripherals seem not to be able to wake up the MPU when
- * it is in retention mode. */
- if (omap2_allow_mpu_retention()) {
- /* REVISIT: These write to reserved bits? */
- omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
- omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
- omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
-
- /* Try to enter MPU retention */
- pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
-
- } else {
- /* Block MPU retention */
- pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
- }
-
- /* WFI */
- asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
-
- pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
-}
-
-static int omap2_can_sleep(void)
-{
- if (omap2xxx_cm_fclks_active())
- return 0;
- if (__clk_is_enabled(osc_ck))
- return 0;
-
- return 1;
-}
-
-static void omap2_pm_idle(void)
-{
- int error;
-
- if (omap_irq_pending())
- return;
-
- error = cpu_cluster_pm_enter();
- if (error || !omap2_can_sleep()) {
- omap2_enter_mpu_retention();
- goto out_cpu_cluster_pm;
- }
-
- omap2_enter_full_retention();
-
-out_cpu_cluster_pm:
- cpu_cluster_pm_exit();
-}
-
-static void __init prcm_setup_regs(void)
-{
- int i, num_mem_banks;
- struct powerdomain *pwrdm;
-
- /*
- * Enable autoidle
- * XXX This should be handled by hwmod code or PRCM init code
- */
- omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
- OMAP2_PRCM_SYSCONFIG_OFFSET);
-
- /*
- * Set CORE powerdomain memory banks to retain their contents
- * during RETENTION
- */
- num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
- for (i = 0; i < num_mem_banks; i++)
- pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
-
- pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
-
- pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
-
- /* Force-power down DSP, GFX powerdomains */
-
- pwrdm = clkdm_get_pwrdm(dsp_clkdm);
- pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
-
- pwrdm = clkdm_get_pwrdm(gfx_clkdm);
- pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
-
- /* Enable hardware-supervised idle for all clkdms */
- clkdm_for_each(omap_pm_clkdms_setup, NULL);
- clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
-
- omap_common_suspend_init(omap2_enter_full_retention);
-
- /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
- * stabilisation */
- omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
- OMAP2_PRCM_CLKSSETUP_OFFSET);
-
- /* Configure automatic voltage transition */
- omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
- OMAP2_PRCM_VOLTSETUP_OFFSET);
- omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
- (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
- OMAP24XX_MEMRETCTRL_MASK |
- (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
- (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
- OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
-
- /* Enable wake-up events */
- omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
- WKUP_MOD, PM_WKEN);
-
- /* Enable SYS_CLKEN control when all domains idle */
- omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
- OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
-}
-
-int __init omap2_pm_init(void)
-{
- u32 l;
-
- printk(KERN_INFO "Power Management for OMAP2 initializing\n");
- l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
- printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-
- /* Look up important powerdomains */
-
- mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
- if (!mpu_pwrdm)
- pr_err("PM: mpu_pwrdm not found\n");
-
- core_pwrdm = pwrdm_lookup("core_pwrdm");
- if (!core_pwrdm)
- pr_err("PM: core_pwrdm not found\n");
-
- /* Look up important clockdomains */
-
- mpu_clkdm = clkdm_lookup("mpu_clkdm");
- if (!mpu_clkdm)
- pr_err("PM: mpu_clkdm not found\n");
-
- wkup_clkdm = clkdm_lookup("wkup_clkdm");
- if (!wkup_clkdm)
- pr_err("PM: wkup_clkdm not found\n");
-
- dsp_clkdm = clkdm_lookup("dsp_clkdm");
- if (!dsp_clkdm)
- pr_err("PM: dsp_clkdm not found\n");
-
- gfx_clkdm = clkdm_lookup("gfx_clkdm");
- if (!gfx_clkdm)
- pr_err("PM: gfx_clkdm not found\n");
-
-
- osc_ck = clk_get(NULL, "osc_ck");
- if (IS_ERR(osc_ck)) {
- printk(KERN_ERR "could not get osc_ck\n");
- return -ENODEV;
- }
-
- if (cpu_is_omap242x()) {
- emul_ck = clk_get(NULL, "emul_ck");
- if (IS_ERR(emul_ck)) {
- printk(KERN_ERR "could not get emul_ck\n");
- clk_put(osc_ck);
- return -ENODEV;
- }
- }
-
- prcm_setup_regs();
-
- /*
- * We copy the assembler sleep/wakeup routines to SRAM.
- * These routines need to be in SRAM as that's the only
- * memory the MPU can see when it wakes up after the entire
- * chip enters idle.
- */
- omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
- omap24xx_cpu_suspend_sz);
-
- arm_pm_idle = omap2_pm_idle;
-
- return 0;
-}
diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c
index bf0d25fd2cea..c907478be196 100644
--- a/arch/arm/mach-omap2/pm33xx-core.c
+++ b/arch/arm/mach-omap2/pm33xx-core.c
@@ -16,7 +16,6 @@
#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/platform_data/gpio-omap.h>
-#include <linux/pinctrl/pinmux.h>
#include <linux/wkup_m3_ipc.h>
#include <linux/of.h>
#include <linux/rtc.h>
@@ -105,8 +104,6 @@ static int amx3_common_init(int (*idle)(u32 wfi_flags))
static int am33xx_suspend_init(int (*idle)(u32 wfi_flags))
{
- int ret;
-
gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
if (!gfx_l4ls_clkdm) {
@@ -114,9 +111,7 @@ static int am33xx_suspend_init(int (*idle)(u32 wfi_flags))
return -ENODEV;
}
- ret = amx3_common_init(idle);
-
- return ret;
+ return amx3_common_init(idle);
}
static int am43xx_suspend_init(int (*idle)(u32 wfi_flags))
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index d73c7b692116..68975771e633 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -26,6 +26,7 @@
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/of.h>
+#include <linux/cpuidle.h>
#include <trace/events/power.h>
@@ -174,7 +175,7 @@ static int omap34xx_do_sram_idle(unsigned long save_state)
return 0;
}
-void omap_sram_idle(void)
+__cpuidle void omap_sram_idle(bool rcuidle)
{
/* Variable to tell what needs to be saved and restored
* in omap_sram_idle*/
@@ -254,11 +255,18 @@ void omap_sram_idle(void)
*/
if (save_state)
omap34xx_save_context(omap3_arm_context);
+
+ if (rcuidle)
+ ct_cpuidle_enter();
+
if (save_state == 1 || save_state == 3)
cpu_suspend(save_state, omap34xx_do_sram_idle);
else
omap34xx_do_sram_idle(save_state);
+ if (rcuidle)
+ ct_cpuidle_exit();
+
/* Restore normal SDRC POWER settings */
if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
(omap_type() == OMAP2_DEVICE_TYPE_EMU ||
@@ -294,7 +302,7 @@ static void omap3_pm_idle(void)
if (omap_irq_pending())
return;
- omap_sram_idle();
+ omap3_do_wfi();
}
#ifdef CONFIG_SUSPEND
@@ -316,7 +324,7 @@ static int omap3_pm_suspend(void)
omap3_intc_suspend();
- omap_sram_idle();
+ omap_sram_idle(false);
restore:
/* Restore next_pwrsts */
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 5a7a949ae965..f57802f3ee3a 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -76,7 +76,7 @@ static int omap4_pm_suspend(void)
* domain CSWR is not supported by hardware.
* More details can be found in OMAP4430 TRM section 4.3.4.2.
*/
- omap4_enter_lowpower(cpu_id, cpu_suspend_state);
+ omap4_enter_lowpower(cpu_id, cpu_suspend_state, false);
/* Restore next powerdomain state */
list_for_each_entry(pwrst, &pwrst_list, node) {
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 2d747f6cffe8..777f9f8e7cd8 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -37,8 +37,8 @@
#define PWRDM_TRACE_STATES_FLAG (1<<31)
-void pwrdms_save_context(void);
-void pwrdms_restore_context(void);
+static void pwrdms_save_context(void);
+static void pwrdms_restore_context(void);
enum {
PWRDM_STATE_NOW = 0,
@@ -187,9 +187,9 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
trace_state = (PWRDM_TRACE_STATES_FLAG |
((next & OMAP_POWERSTATE_MASK) << 8) |
((prev & OMAP_POWERSTATE_MASK) << 0));
- trace_power_domain_target_rcuidle(pwrdm->name,
- trace_state,
- raw_smp_processor_id());
+ trace_power_domain_target(pwrdm->name,
+ trace_state,
+ raw_smp_processor_id());
}
break;
default:
@@ -541,8 +541,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
/* Trace the pwrdm desired target state */
- trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
- raw_smp_processor_id());
+ trace_power_domain_target(pwrdm->name, pwrst,
+ raw_smp_processor_id());
/* Program the pwrdm desired target state */
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
}
@@ -1149,82 +1149,6 @@ osps_out:
}
/**
- * pwrdm_get_context_loss_count - get powerdomain's context loss count
- * @pwrdm: struct powerdomain * to wait for
- *
- * Context loss count is the sum of powerdomain off-mode counter, the
- * logic off counter and the per-bank memory off counter. Returns negative
- * (and WARNs) upon error, otherwise, returns the context loss count.
- */
-int pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
-{
- int i, count;
-
- if (!pwrdm) {
- WARN(1, "powerdomain: %s: pwrdm is null\n", __func__);
- return -ENODEV;
- }
-
- count = pwrdm->state_counter[PWRDM_POWER_OFF];
- count += pwrdm->ret_logic_off_counter;
-
- for (i = 0; i < pwrdm->banks; i++)
- count += pwrdm->ret_mem_off_counter[i];
-
- /*
- * Context loss count has to be a non-negative value. Clear the sign
- * bit to get a value range from 0 to INT_MAX.
- */
- count &= INT_MAX;
-
- pr_debug("powerdomain: %s: context loss count = %d\n",
- pwrdm->name, count);
-
- return count;
-}
-
-/**
- * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
- * @pwrdm: struct powerdomain *
- *
- * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
- * can lose either memory or logic context or if @pwrdm is invalid, or
- * returns 0 otherwise. This function is not concerned with how the
- * powerdomain registers are programmed (i.e., to go off or not); it's
- * concerned with whether it's ever possible for this powerdomain to
- * go off while some other part of the chip is active. This function
- * assumes that every powerdomain can go to either ON or INACTIVE.
- */
-bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
-{
- int i;
-
- if (!pwrdm) {
- pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
- __func__);
- return true;
- }
-
- if (pwrdm->pwrsts & PWRSTS_OFF)
- return true;
-
- if (pwrdm->pwrsts & PWRSTS_RET) {
- if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
- return true;
-
- for (i = 0; i < pwrdm->banks; i++)
- if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
- return true;
- }
-
- for (i = 0; i < pwrdm->banks; i++)
- if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
- return true;
-
- return false;
-}
-
-/**
* pwrdm_save_context - save powerdomain registers
*
* Register state is going to be lost due to a suspend or hibernate
@@ -1250,36 +1174,12 @@ static int pwrdm_restore_context(struct powerdomain *pwrdm, void *unused)
return 0;
}
-static int pwrdm_lost_power(struct powerdomain *pwrdm, void *unused)
-{
- int state;
-
- /*
- * Power has been lost across all powerdomains, increment the
- * counter.
- */
-
- state = pwrdm_read_pwrst(pwrdm);
- if (state != PWRDM_POWER_OFF) {
- pwrdm->state_counter[state]++;
- pwrdm->state_counter[PWRDM_POWER_OFF]++;
- }
- pwrdm->state = state;
-
- return 0;
-}
-
-void pwrdms_save_context(void)
+static void pwrdms_save_context(void)
{
pwrdm_for_each(pwrdm_save_context, NULL);
}
-void pwrdms_restore_context(void)
+static void pwrdms_restore_context(void)
{
pwrdm_for_each(pwrdm_restore_context, NULL);
}
-
-void pwrdms_lost_power(void)
-{
- pwrdm_for_each(pwrdm_lost_power, NULL);
-}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 907cc659f47a..fbc89999460b 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -208,8 +208,6 @@ struct powerdomain *pwrdm_lookup(const char *name);
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
void *user);
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
- void *user);
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
@@ -243,8 +241,6 @@ int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
int pwrdm_state_switch(struct powerdomain *pwrdm);
int pwrdm_pre_transition(struct powerdomain *pwrdm);
int pwrdm_post_transition(struct powerdomain *pwrdm);
-int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
-bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
@@ -273,8 +269,4 @@ extern struct powerdomain gfx_omap2_pwrdm;
extern void pwrdm_lock(struct powerdomain *pwrdm);
extern void pwrdm_unlock(struct powerdomain *pwrdm);
-extern void pwrdms_save_context(void);
-extern void pwrdms_restore_context(void);
-
-extern void pwrdms_lost_power(void);
#endif
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
index 626055e59aed..1d58fd1a2dce 100644
--- a/arch/arm/mach-omap2/powerdomains33xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* AM33XX Power domain data
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 48e804c93caf..5e3544a63526 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -550,7 +550,6 @@ struct omap_prcm_init_data {
struct device_node *np;
};
-extern void omap_prcm_irq_cleanup(void);
extern int omap_prcm_register_chain_handler(
struct omap_prcm_irq_setup *irq_setup);
extern int omap_prcm_event_to_irq(const char *event);
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index b65cccab6ad9..38ed69b150cb 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AM43x PRCM defines
*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index 5add541e3b41..7236c50388a8 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -35,18 +35,6 @@ void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}
-u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
-{
- u32 v;
-
- v = omap4_prcm_mpu_read_inst_reg(inst, reg);
- v &= ~mask;
- v |= bits;
- omap4_prcm_mpu_write_inst_reg(v, inst, reg);
-
- return v;
-}
-
/**
* omap2_set_globals_prcm_mpu - set the MPU PRCM base address (for early use)
* @prcm_mpu: PRCM_MPU base virtual address
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
index 7c6377566f33..0c519447e790 100644
--- a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -26,8 +26,6 @@ extern struct omap_domain_base prcm_mpu_base;
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
- s16 idx);
extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
index 7dfdff09ddeb..3748c5266ae1 100644
--- a/arch/arm/mach-omap2/prm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AM33XX PRM_XXX register bits
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 08df78810a5e..fc45a7ed09bb 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -15,9 +15,7 @@
# ifndef __ASSEMBLER__
extern struct omap_domain_base prm_base;
extern u16 prm_features;
-extern void omap2_set_globals_prm(void __iomem *prm);
int omap_prcm_init(void);
-int omap2_prm_base_init(void);
int omap2_prcm_base_init(void);
# endif
@@ -156,12 +154,10 @@ int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
u16 offset, u16 st_offset);
int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
-extern u32 prm_read_reset_sources(void);
extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
void omap_prm_reset_system(void);
-void omap_prm_reconfigure_io_chain(void);
int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
/*
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 3d803f7182b9..bc263d564acc 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -104,9 +104,6 @@ int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
s16 prm_mod, u16 reset_offset,
u16 st_offset);
-extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
-extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
-extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
u8 pwrst);
extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 9144cc0479af..4b65a0f9cf7d 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* AM33XX PRM functions
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index a469a36c00d8..3081f3deb650 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AM33XX PRM instance offset macros
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 1b442b128569..1b5d08f594aa 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -32,6 +32,7 @@ static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
static void omap3xxx_prm_ocp_barrier(void);
static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
static void omap3xxx_prm_restore_irqen(u32 *saved_mask);
+static void omap3xxx_prm_iva_idle(void);
static const struct omap_prcm_irq omap3_prcm_irqs[] = {
OMAP_PRCM_IRQ("wkup", 0, 0),
@@ -268,7 +269,7 @@ static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
* Toggles the reset signal to modem IP block. Required to allow
* OMAP3430 without stacked modem to idle properly.
*/
-void __init omap3_prm_reset_modem(void)
+static void __init omap3_prm_reset_modem(void)
{
omap2_prm_write_mod_reg(
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
@@ -469,7 +470,7 @@ static u32 omap3xxx_prm_read_reset_sources(void)
* function forces the IVA2 into idle state so it can go
* into retention/off and thus allow full-chip retention/off.
*/
-void omap3xxx_prm_iva_idle(void)
+static void omap3xxx_prm_iva_idle(void)
{
/* ensure IVA2 clock is disabled */
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
@@ -708,6 +709,7 @@ static int omap3xxx_prm_late_init(void)
}
irq_num = of_irq_get(np, 0);
+ of_node_put(np);
if (irq_num == -EPROBE_DEFER)
return irq_num;
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ed7c389aa5a7..ab899e461c62 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -138,8 +138,6 @@ extern void omap3_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
-void omap3xxx_prm_iva_idle(void);
-void omap3_prm_reset_modem(void);
int omap3xxx_prm_clear_global_cold_reset(void);
void omap3_prm_save_scratchpad_contents(u32 *ptr);
void omap3_prm_init_pm(bool has_uart4, bool has_iva);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 65b2d82efa27..fd896f2295a1 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -187,7 +187,7 @@ int omap_prcm_event_to_irq(const char *name)
*
* No return value.
*/
-void omap_prcm_irq_cleanup(void)
+static void omap_prcm_irq_cleanup(void)
{
unsigned int irq;
int i;
@@ -345,41 +345,6 @@ err:
}
/**
- * omap2_set_globals_prm - set the PRM base address (for early use)
- * @prm: PRM base virtual address
- *
- * XXX Will be replaced when the PRM/CM drivers are completed.
- */
-void __init omap2_set_globals_prm(void __iomem *prm)
-{
- prm_base.va = prm;
-}
-
-/**
- * prm_read_reset_sources - return the sources of the SoC's last reset
- *
- * Return a u32 bitmask representing the reset sources that caused the
- * SoC to reset. The low-level per-SoC functions called by this
- * function remap the SoC-specific reset source bits into an
- * OMAP-common set of reset source bits, defined in
- * arch/arm/mach-omap2/prm.h. Returns the standardized reset source
- * u32 bitmask from the hardware upon success, or returns (1 <<
- * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
- * function was registered.
- */
-u32 prm_read_reset_sources(void)
-{
- u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
-
- if (prm_ll_data->read_reset_sources)
- ret = prm_ll_data->read_reset_sources();
- else
- WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
-
- return ret;
-}
-
-/**
* prm_was_any_context_lost_old - was device context lost? (old API)
* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
@@ -489,22 +454,6 @@ int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
}
/**
- * omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
- *
- * Clear any previously-latched I/O wakeup events and ensure that the
- * I/O wakeup gates are aligned with the current mux settings.
- * Calls SoC specific I/O chain reconfigure function if available,
- * otherwise does nothing.
- */
-void omap_prm_reconfigure_io_chain(void)
-{
- if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
- return;
-
- prcm_irq_setup->reconfigure_io_chain();
-}
-
-/**
* omap_prm_reset_system - trigger global SW reset
*
* Triggers SoC specific global warm reset to reboot the device.
@@ -740,7 +689,7 @@ static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
* on the DT data. Returns 0 in success, negative error value
* otherwise.
*/
-int __init omap2_prm_base_init(void)
+static int __init omap2_prm_base_init(void)
{
struct device_node *np;
const struct of_device_id *match;
@@ -752,8 +701,10 @@ int __init omap2_prm_base_init(void)
data = (struct omap_prcm_init_data *)match->data;
ret = of_address_to_resource(np, 0, &res);
- if (ret)
+ if (ret) {
+ of_node_put(np);
return ret;
+ }
data->mem = ioremap(res.start, resource_size(&res));
@@ -799,8 +750,10 @@ int __init omap_prcm_init(void)
data = match->data;
ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
- if (ret)
+ if (ret) {
+ of_node_put(np);
return ret;
+ }
}
omap_cm_init();
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 2be4106d0dd6..b1bf9e24d442 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -45,7 +45,7 @@ static struct omap2_sms_regs sms_context;
*
* Save SMS registers that need to be restored after off mode.
*/
-void omap2_sms_save_context(void)
+static void omap2_sms_save_context(void)
{
sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
}
@@ -60,55 +60,6 @@ void omap2_sms_restore_context(void)
sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
}
-/**
- * omap2_sdrc_get_params - return SDRC register values for a given clock rate
- * @r: SDRC clock rate (in Hz)
- * @sdrc_cs0: chip select 0 ram timings **
- * @sdrc_cs1: chip select 1 ram timings **
- *
- * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
- * structs,for a given SDRC clock rate 'r'.
- * These parameters control various timing delays in the SDRAM controller
- * that are expressed in terms of the number of SDRC clock cycles to
- * wait; hence the clock rate dependency.
- *
- * Supports 2 different timing parameters for both chip selects.
- *
- * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
- * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
- * as sdrc_init_params_cs_0.
- *
- * Fills in the struct omap_sdrc_params * for each chip select.
- * Returns 0 upon success or -1 upon failure.
- */
-int omap2_sdrc_get_params(unsigned long r,
- struct omap_sdrc_params **sdrc_cs0,
- struct omap_sdrc_params **sdrc_cs1)
-{
- struct omap_sdrc_params *sp0, *sp1;
-
- if (!sdrc_init_params_cs0)
- return -1;
-
- sp0 = sdrc_init_params_cs0;
- sp1 = sdrc_init_params_cs1;
-
- while (sp0->rate && sp0->rate != r) {
- sp0++;
- if (sdrc_init_params_cs1)
- sp1++;
- }
-
- if (!sp0->rate)
- return -1;
-
- *sdrc_cs0 = sp0;
- *sdrc_cs1 = sp1;
- return 0;
-}
-
-
void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
{
omap2_sdrc_base = sdrc;
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 5bdb832665c0..45b35422b587 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -80,10 +80,6 @@ static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1) {};
#endif
-int omap2_sdrc_get_params(unsigned long r,
- struct omap_sdrc_params **sdrc_cs0,
- struct omap_sdrc_params **sdrc_cs1);
-void omap2_sms_save_context(void);
void omap2_sms_restore_context(void);
struct memory_timings {
@@ -95,7 +91,6 @@ struct memory_timings {
};
extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
-struct omap_sdrc_params *rx51_get_sdram_timings(void);
u32 omap2xxx_sdrc_dll_is_unlocked(void);
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
diff --git a/arch/arm/mach-omap2/serial.h b/arch/arm/mach-omap2/serial.h
deleted file mode 100644
index c4014f013df0..000000000000
--- a/arch/arm/mach-omap2/serial.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach/serial.h>
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index c4e97d35c310..781a131b40a6 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -465,7 +465,7 @@ l2_inv_gp:
mov r12, #0x2
smc #0 @ Call SMI monitor (smieq)
logic_l1_restore:
- adr r0, l2dis_3630_offset @ adress for offset
+ adr r0, l2dis_3630_offset @ address for offset
ldr r1, [r0] @ value for offset
ldr r1, [r0, r1] @ value at l2dis_3630
cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index db672cf19a51..d2133423b0c9 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -26,8 +26,6 @@
#include "control.h"
#include "pm.h"
-static bool sr_enable_on_init;
-
/* Read EFUSE values from control registers for OMAP3430 */
static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
struct omap_sr_data *sr_data)
@@ -144,8 +142,6 @@ static int __init sr_init_by_name(const char *name, const char *voltdm)
sr_set_nvalues(volt_data, sr_data);
- sr_data->enable_on_init = sr_enable_on_init;
-
exit:
i++;
@@ -173,15 +169,6 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
}
#endif
-/*
- * API to be called from board files to enable smartreflex
- * autocompensation at init.
- */
-void __init omap_enable_smartreflex_on_init(void)
-{
- sr_enable_on_init = true;
-}
-
static const char * const omap4_sr_instances[] = {
"mpu",
"iva",
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index c685afb8bd03..815d390109d2 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -14,11 +14,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/set_memory.h>
#include <asm/fncpy.h>
#include <asm/tlb.h>
#include <asm/cacheflush.h>
-#include <asm/set_memory.h>
#include <asm/mach/map.h>
@@ -75,7 +75,7 @@ static void *omap_sram_push_address(unsigned long size)
new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
omap_sram_ceil = IOMEM(new_ceil);
- return (void *)omap_sram_ceil;
+ return (void __force *)omap_sram_ceil;
}
void *omap_sram_push(void *funcp, unsigned long size)
@@ -96,8 +96,7 @@ void *omap_sram_push(void *funcp, unsigned long size)
dst = fncpy(sram, funcp, size);
- set_memory_ro(base, pages);
- set_memory_x(base, pages);
+ set_memory_rox(base, pages);
return dst;
}
@@ -217,8 +216,7 @@ static void __init omap2_map_sram(void)
base = (unsigned long)omap_sram_base;
pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE;
- set_memory_ro(base, pages);
- set_memory_x(base, pages);
+ set_memory_rox(base, pages);
}
static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
diff --git a/arch/arm/mach-omap2/sram.h b/arch/arm/mach-omap2/sram.h
index 271062f23482..030cabc39821 100644
--- a/arch/arm/mach-omap2/sram.h
+++ b/arch/arm/mach-omap2/sram.h
@@ -17,10 +17,6 @@ extern int __init omap_sram_init(void);
extern void *omap_sram_push(void *funcp, unsigned long size);
-/* Do not use these */
-extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long omap24xx_sram_reprogram_clock_sz;
-
extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
extern unsigned long omap242x_sram_ddr_init_sz;
diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
index 192b0e7d3eb4..fe9f7f388cbd 100644
--- a/arch/arm/mach-omap2/ti81xx.h
+++ b/arch/arm/mach-omap2/ti81xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file contains the address data for various TI81XX modules.
*
* Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_TI81XX_H
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 620ba69c8f11..5677c4a08f37 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -76,6 +76,7 @@ static void __init realtime_counter_init(void)
}
rate = clk_get_rate(sys_clk);
+ clk_put(sys_clk);
if (soc_is_dra7xx()) {
/*
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index a0c4c42e56b9..18fa52f828dc 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -97,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
}
/* tusb driver calls this when it changes the chip's clocking */
-int tusb6010_platform_retime(unsigned is_refclk)
+static int tusb6010_platform_retime(unsigned is_refclk)
{
static const char error[] =
KERN_ERR "tusb6010 %s retime error %d\n";
@@ -121,7 +121,6 @@ int tusb6010_platform_retime(unsigned is_refclk)
done:
return status;
}
-EXPORT_SYMBOL_GPL(tusb6010_platform_retime);
static struct resource tusb_resources[] = {
/* Order is significant! The start/end fields
@@ -154,8 +153,7 @@ static struct platform_device tusb_device = {
/* this may be called only from board-*.c setup code */
-int __init
-tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
+int __init tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
unsigned ps_refclk, unsigned waitpin,
unsigned async, unsigned sync,
unsigned irq, unsigned dmachan)
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
deleted file mode 100644
index 740a499befce..000000000000
--- a/arch/arm/mach-omap2/usb.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/platform_data/usb-omap.h>
-
-/* AM35x */
-/* USB 2.0 PHY Control */
-#define CONF2_PHY_GPIOMODE (1 << 23)
-#define CONF2_OTGMODE (3 << 14)
-#define CONF2_NO_OVERRIDE (0 << 14)
-#define CONF2_FORCE_HOST (1 << 14)
-#define CONF2_FORCE_DEVICE (2 << 14)
-#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
-#define CONF2_SESENDEN (1 << 13)
-#define CONF2_VBDTCTEN (1 << 12)
-#define CONF2_REFFREQ_24MHZ (2 << 8)
-#define CONF2_REFFREQ_26MHZ (7 << 8)
-#define CONF2_REFFREQ_13MHZ (6 << 8)
-#define CONF2_REFFREQ (0xf << 8)
-#define CONF2_PHYCLKGD (1 << 7)
-#define CONF2_VBUSSENSE (1 << 6)
-#define CONF2_PHY_PLLON (1 << 5)
-#define CONF2_RESET (1 << 4)
-#define CONF2_PHYPWRDN (1 << 3)
-#define CONF2_OTGPWRDN (1 << 2)
-#define CONF2_DATPOL (1 << 1)
-
-/* TI81XX specific definitions */
-#define USBCTRL0 0x620
-#define USBSTAT0 0x624
-
-/* TI816X PHY controls bits */
-#define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
-#define TI816X_USBPHY_REFCLK_OSC (1 << 8)
-
-/* TI814X PHY controls bits */
-#define USBPHY_CM_PWRDN (1 << 0)
-#define USBPHY_OTG_PWRDN (1 << 1)
-#define USBPHY_CHGDET_DIS (1 << 2)
-#define USBPHY_CHGDET_RSTRT (1 << 3)
-#define USBPHY_SRCONDM (1 << 4)
-#define USBPHY_SINKONDP (1 << 5)
-#define USBPHY_CHGISINK_EN (1 << 6)
-#define USBPHY_CHGVSRC_EN (1 << 7)
-#define USBPHY_DMPULLUP (1 << 8)
-#define USBPHY_DPPULLUP (1 << 9)
-#define USBPHY_CDET_EXTCTL (1 << 10)
-#define USBPHY_GPIO_MODE (1 << 12)
-#define USBPHY_DPOPBUFCTL (1 << 13)
-#define USBPHY_DMOPBUFCTL (1 << 14)
-#define USBPHY_DPINPUT (1 << 15)
-#define USBPHY_DMINPUT (1 << 16)
-#define USBPHY_DPGPIO_PD (1 << 17)
-#define USBPHY_DMGPIO_PD (1 << 18)
-#define USBPHY_OTGVDET_EN (1 << 19)
-#define USBPHY_OTGSESSEND_EN (1 << 20)
-#define USBPHY_DATA_POLARITY (1 << 23)
-
-struct usbhs_phy_data {
- int port; /* 1 indexed port number */
- int reset_gpio;
- int vcc_gpio;
- bool vcc_polarity; /* 1 active high, 0 active low */
-};
-
-extern void usb_musb_init(struct omap_musb_board_data *board_data);
-extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
-extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys);
-
-extern void am35x_musb_reset(void);
-extern void am35x_musb_phy_power(u8 on);
-extern void am35x_musb_clear_irq(void);
-extern void am35x_set_mode(u8 musb_mode);
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 86f1ac4c2412..fc26b96a20cc 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP Voltage Controller (VC) interface
*
* Copyright (C) 2011 Texas Instruments, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/delay.h>
@@ -805,21 +802,6 @@ static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
return voltdm->pmic->uv_to_vsel(uvolt);
}
-#ifdef CONFIG_PM
-/**
- * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
- * @mm: length of the PCB trace in millimetres
- *
- * Sets the PCB trace length for the I2C channel. By default uses 63mm.
- * This is needed for properly calculating the capacitance value for
- * the PCB trace, and for setting the SR I2C channel timing parameters.
- */
-void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
-{
- sr_i2c_pcb_length = mm;
-}
-#endif
-
void __init omap_vc_init_channel(struct voltagedomain *voltdm)
{
struct omap_vc_channel *vc = voltdm->vc;
@@ -895,4 +877,3 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
else if (cpu_is_omap44xx())
omap4_vc_init_channel(voltdm);
}
-
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 0a0c771dbb0a..49e8bc69abdd 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -67,7 +67,7 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
* This API should be called by the kernel to do the voltage scaling
* for a particular voltage domain during DVFS.
*/
-int voltdm_scale(struct voltagedomain *voltdm,
+static int voltdm_scale(struct voltagedomain *voltdm,
unsigned long target_volt)
{
int ret, i;
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 4a225f9559a5..e610f63a020d 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -163,8 +163,6 @@ extern void omap54xx_voltagedomains_init(void);
struct voltagedomain *voltdm_lookup(const char *name);
void voltdm_init(struct voltagedomain **voltdm_list);
-int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
-int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
void voltdm_reset(struct voltagedomain *voltdm);
unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
#endif
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index c77f3b4e287b..ee449ca032d2 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -2,10 +2,12 @@
menuconfig ARCH_ORION5X
bool "Marvell Orion"
depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
select CPU_FEROCEON
select GPIOLIB
select MVEBU_MBUS
select FORCE_PCI
+ select PCI_QUIRKS
select PHYLIB if NETDEVICES
select PLAT_ORION_LEGACY
help
@@ -26,20 +28,6 @@ config ARCH_ORION5X_DT
Say 'Y' here if you want your kernel to support the
Marvell Orion5x using flattened device tree.
-config MACH_DB88F5281
- bool "Marvell Orion-2 Development Board"
- select I2C_BOARDINFO if I2C
- help
- Say 'Y' here if you want your kernel to support the
- Marvell Orion-2 (88F5281) Development Board
-
-config MACH_RD88F5182
- bool "Marvell Orion-NAS Reference Design"
- select I2C_BOARDINFO if I2C
- help
- Say 'Y' here if you want your kernel to support the
- Marvell Orion-NAS (88F5182) RD2
-
config MACH_RD88F5182_DT
bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)"
select ARCH_ORION5X_DT
@@ -51,6 +39,7 @@ config MACH_RD88F5182_DT
config MACH_KUROBOX_PRO
bool "KuroBox Pro"
select I2C_BOARDINFO if I2C
+ depends on ATAGS
help
Say 'Y' here if you want your kernel to support the
KuroBox Pro platform.
@@ -58,24 +47,28 @@ config MACH_KUROBOX_PRO
config MACH_DNS323
bool "D-Link DNS-323"
select I2C_BOARDINFO if I2C
+ depends on ATAGS
help
Say 'Y' here if you want your kernel to support the
D-Link DNS-323 platform.
config MACH_TS209
bool "QNAP TS-109/TS-209"
+ depends on ATAGS
help
Say 'Y' here if you want your kernel to support the
QNAP TS-109/TS-209 platform.
config MACH_TERASTATION_PRO2
bool "Buffalo Terastation Pro II/Live"
+ depends on ATAGS
help
Say 'Y' here if you want your kernel to support the
Buffalo Terastation Pro II/Live platform.
config MACH_LINKSTATION_PRO
bool "Buffalo Linkstation Pro/Live"
+ depends on ATAGS
select I2C_BOARDINFO if I2C
help
Say 'Y' here if you want your kernel to support the
@@ -89,33 +82,23 @@ config MACH_LINKSTATION_MINI
Say 'Y' here if you want your kernel to support the
Buffalo Linkstation Mini (LS-WSGL) platform.
-config MACH_LINKSTATION_LS_HGL
- bool "Buffalo Linkstation LS-HGL"
- select I2C_BOARDINFO if I2C
- help
- Say 'Y' here if you want your kernel to support the
- Buffalo Linkstation LS-HGL platform.
-
config MACH_TS409
bool "QNAP TS-409"
+ depends on ATAGS
help
Say 'Y' here if you want your kernel to support the
QNAP TS-409 platform.
-config MACH_WRT350N_V2
- bool "Linksys WRT350N v2"
- help
- Say 'Y' here if you want your kernel to support the
- Linksys WRT350N v2 platform.
-
config MACH_TS78XX
bool "Technologic Systems TS-78xx"
+ depends on ATAGS
help
Say 'Y' here if you want your kernel to support the
Technologic Systems TS-78xx platform.
config MACH_MV2120
bool "HP Media Vault mv2120"
+ depends on ATAGS
help
Say 'Y' here if you want your kernel to support the
HP Media Vault mv2120 or mv5100.
@@ -129,6 +112,7 @@ config MACH_D2NET_DT
config MACH_NET2BIG
bool "LaCie 2Big Network"
+ depends on ATAGS
select I2C_BOARDINFO if I2C
help
Say 'Y' here if you want your kernel to support the
@@ -141,28 +125,4 @@ config MACH_MSS2_DT
Say 'Y' here if you want your kernel to support the
Maxtor Shared Storage II platform.
-config MACH_WNR854T
- bool "Netgear WNR854T"
- help
- Say 'Y' here if you want your kernel to support the
- Netgear WNR854T platform.
-
-config MACH_RD88F5181L_GE
- bool "Marvell Orion-VoIP GE Reference Design"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell Orion-VoIP GE (88F5181L) RD.
-
-config MACH_RD88F5181L_FXO
- bool "Marvell Orion-VoIP FXO Reference Design"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell Orion-VoIP FXO (88F5181L) RD.
-
-config MACH_RD88F6183AP_GE
- bool "Marvell Orion-1-90 AP GE Reference Design"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell Orion-1-90 (88F6183) AP GE RD.
-
endif
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 1a585a62d5e6..6f54d7fef27a 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,24 +1,16 @@
# SPDX-License-Identifier: GPL-2.0
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include
+ccflags-y := -I$(srctree)/arch/arm/plat-orion/include
obj-y += common.o pci.o irq.o mpp.o
-obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
-obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o
obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
-obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o
obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o
obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o
-obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o
obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o
obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o
obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o
-obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o
-obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o
-obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o
-obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o
obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o
obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o
diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c
index a89376a5cd92..0297e302d7bc 100644
--- a/arch/arm/mach-orion5x/board-d2net.c
+++ b/arch/arm/mach-orion5x/board-d2net.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/board-d2net.c
*
* LaCie d2Network and Big Disk Network NAS setup
*
* Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index 3d36f1d95196..e3736ffc8347 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2012 (C), Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* arch/arm/mach-orion5x/board-dt.c
*
* Flattened Device Tree board initialization
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c
index b7b0f52f4c0a..1c14e49a90a6 100644
--- a/arch/arm/mach-orion5x/board-rd88f5182.c
+++ b/arch/arm/mach-orion5x/board-rd88f5182.c
@@ -1,17 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/rd88f5182-setup.c
*
* Marvell Orion-NAS Reference Design Setup
*
* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
diff --git a/arch/arm/mach-orion5x/bridge-regs.h b/arch/arm/mach-orion5x/bridge-regs.h
index 305598eaaee1..fe85bc5b131f 100644
--- a/arch/arm/mach-orion5x/bridge-regs.h
+++ b/arch/arm/mach-orion5x/bridge-regs.h
@@ -1,10 +1,5 @@
-/*
- * Orion CPU Bridge Registers
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Orion CPU Bridge Registers */
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 7bcb41137bbf..df056d60b675 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/common.c
*
* Core functions for Marvell Orion 5x SoCs
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
@@ -21,7 +18,6 @@
#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
-#include <linux/platform_data/dsa.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/system_misc.h>
@@ -104,15 +100,6 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
/*****************************************************************************
- * Ethernet switch
- ****************************************************************************/
-void __init orion5x_eth_switch_init(struct dsa_chip_data *d)
-{
- orion_ge00_switch_init(d);
-}
-
-
-/*****************************************************************************
* I2C
****************************************************************************/
void __init orion5x_i2c_init(void)
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index eb96009e21c4..f2e0577bf50f 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -4,7 +4,6 @@
#include <linux/reboot.h>
-struct dsa_chip_data;
struct mv643xx_eth_platform_data;
struct mv_sata_platform_data;
@@ -42,7 +41,6 @@ void orion5x_setup_wins(void);
void orion5x_ehci0_init(void);
void orion5x_ehci1_init(void);
void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
-void orion5x_eth_switch_init(struct dsa_chip_data *d);
void orion5x_i2c_init(void);
void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
void orion5x_spi_init(void);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
deleted file mode 100644
index 39eae10ac8de..000000000000
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * arch/arm/mach-orion5x/db88f5281-setup.c
- *
- * Marvell Orion-2 Development Board Setup
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/timer.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <linux/platform_data/mtd-orion_nand.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * DB-88F5281 on board devices
- ****************************************************************************/
-
-/*
- * 512K NOR flash Device bus boot chip select
- */
-
-#define DB88F5281_NOR_BOOT_BASE 0xf4000000
-#define DB88F5281_NOR_BOOT_SIZE SZ_512K
-
-/*
- * 7-Segment on Device bus chip select 0
- */
-
-#define DB88F5281_7SEG_BASE 0xfa000000
-#define DB88F5281_7SEG_SIZE SZ_1K
-
-/*
- * 32M NOR flash on Device bus chip select 1
- */
-
-#define DB88F5281_NOR_BASE 0xfc000000
-#define DB88F5281_NOR_SIZE SZ_32M
-
-/*
- * 32M NAND flash on Device bus chip select 2
- */
-
-#define DB88F5281_NAND_BASE 0xfa800000
-#define DB88F5281_NAND_SIZE SZ_1K
-
-/*
- * PCI
- */
-
-#define DB88F5281_PCI_SLOT0_OFFS 7
-#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
-#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
-
-/*****************************************************************************
- * 512M NOR Flash on Device bus Boot CS
- ****************************************************************************/
-
-static struct physmap_flash_data db88f5281_boot_flash_data = {
- .width = 1, /* 8 bit bus width */
-};
-
-static struct resource db88f5281_boot_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = DB88F5281_NOR_BOOT_BASE,
- .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device db88f5281_boot_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &db88f5281_boot_flash_data,
- },
- .num_resources = 1,
- .resource = &db88f5281_boot_flash_resource,
-};
-
-/*****************************************************************************
- * 32M NOR Flash on Device bus CS1
- ****************************************************************************/
-
-static struct physmap_flash_data db88f5281_nor_flash_data = {
- .width = 4, /* 32 bit bus width */
-};
-
-static struct resource db88f5281_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = DB88F5281_NOR_BASE,
- .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
-};
-
-static struct platform_device db88f5281_nor_flash = {
- .name = "physmap-flash",
- .id = 1,
- .dev = {
- .platform_data = &db88f5281_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &db88f5281_nor_flash_resource,
-};
-
-/*****************************************************************************
- * 32M NAND Flash on Device bus CS2
- ****************************************************************************/
-
-static struct mtd_partition db88f5281_nand_parts[] = {
- {
- .name = "kernel",
- .offset = 0,
- .size = SZ_2M,
- }, {
- .name = "root",
- .offset = SZ_2M,
- .size = (SZ_16M - SZ_2M),
- }, {
- .name = "user",
- .offset = SZ_16M,
- .size = SZ_8M,
- }, {
- .name = "recovery",
- .offset = (SZ_16M + SZ_8M),
- .size = SZ_8M,
- },
-};
-
-static struct resource db88f5281_nand_resource = {
- .flags = IORESOURCE_MEM,
- .start = DB88F5281_NAND_BASE,
- .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
-};
-
-static struct orion_nand_data db88f5281_nand_data = {
- .parts = db88f5281_nand_parts,
- .nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
- .cle = 0,
- .ale = 1,
- .width = 8,
-};
-
-static struct platform_device db88f5281_nand_flash = {
- .name = "orion_nand",
- .id = -1,
- .dev = {
- .platform_data = &db88f5281_nand_data,
- },
- .resource = &db88f5281_nand_resource,
- .num_resources = 1,
-};
-
-/*****************************************************************************
- * 7-Segment on Device bus CS0
- * Dummy counter every 2 sec
- ****************************************************************************/
-
-static void __iomem *db88f5281_7seg;
-static struct timer_list db88f5281_timer;
-
-static void db88f5281_7seg_event(struct timer_list *unused)
-{
- static int count = 0;
- writel(0, db88f5281_7seg + (count << 4));
- count = (count + 1) & 7;
- mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
-}
-
-static int __init db88f5281_7seg_init(void)
-{
- if (machine_is_db88f5281()) {
- db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
- DB88F5281_7SEG_SIZE);
- if (!db88f5281_7seg) {
- printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
- return -EIO;
- }
- timer_setup(&db88f5281_timer, db88f5281_7seg_event, 0);
- mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
- }
-
- return 0;
-}
-
-__initcall(db88f5281_7seg_init);
-
-/*****************************************************************************
- * PCI
- ****************************************************************************/
-
-static void __init db88f5281_pci_preinit(void)
-{
- int pin;
-
- /*
- * Configure PCI GPIO IRQ pins
- */
- pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
- if (gpio_request(pin, "PCI Int1") == 0) {
- if (gpio_direction_input(pin) == 0) {
- irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
- } else {
- printk(KERN_ERR "db88f5281_pci_preinit failed to "
- "set_irq_type pin %d\n", pin);
- gpio_free(pin);
- }
- } else {
- printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
- }
-
- pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
- if (gpio_request(pin, "PCI Int2") == 0) {
- if (gpio_direction_input(pin) == 0) {
- irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
- } else {
- printk(KERN_ERR "db88f5281_pci_preinit failed "
- "to set_irq_type pin %d\n", pin);
- gpio_free(pin);
- }
- } else {
- printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
- }
-}
-
-static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * PCI IRQs are connected via GPIOs.
- */
- switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
- case 0:
- return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
- case 1:
- case 2:
- return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
- default:
- return -1;
- }
-}
-
-static struct hw_pci db88f5281_pci __initdata = {
- .nr_controllers = 2,
- .preinit = db88f5281_pci_preinit,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = db88f5281_pci_map_irq,
-};
-
-static int __init db88f5281_pci_init(void)
-{
- if (machine_is_db88f5281())
- pci_common_init(&db88f5281_pci);
-
- return 0;
-}
-
-subsys_initcall(db88f5281_pci_init);
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-static struct mv643xx_eth_platform_data db88f5281_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-/*****************************************************************************
- * RTC DS1339 on I2C bus
- ****************************************************************************/
-static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
- I2C_BOARD_INFO("ds1339", 0x68),
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int db88f5281_mpp_modes[] __initdata = {
- MPP0_GPIO, /* USB Over Current */
- MPP1_GPIO, /* USB Vbat input */
- MPP2_PCI_ARB, /* PCI_REQn[2] */
- MPP3_PCI_ARB, /* PCI_GNTn[2] */
- MPP4_PCI_ARB, /* PCI_REQn[3] */
- MPP5_PCI_ARB, /* PCI_GNTn[3] */
- MPP6_GPIO, /* JP0, CON17.2 */
- MPP7_GPIO, /* JP1, CON17.1 */
- MPP8_GPIO, /* JP2, CON11.2 */
- MPP9_GPIO, /* JP3, CON11.3 */
- MPP10_GPIO, /* RTC int */
- MPP11_GPIO, /* Baud Rate Generator */
- MPP12_GPIO, /* PCI int 1 */
- MPP13_GPIO, /* PCI int 2 */
- MPP14_NAND, /* NAND_REn[2] */
- MPP15_NAND, /* NAND_WEn[2] */
- MPP16_UART, /* UART1_RX */
- MPP17_UART, /* UART1_TX */
- MPP18_UART, /* UART1_CTSn */
- MPP19_UART, /* UART1_RTSn */
- 0,
-};
-
-static void __init db88f5281_init(void)
-{
- /*
- * Basic Orion setup. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(db88f5281_mpp_modes);
- writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_eth_init(&db88f5281_eth_data);
- orion5x_i2c_init();
- orion5x_uart0_init();
- orion5x_uart1_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- DB88F5281_NOR_BOOT_BASE,
- DB88F5281_NOR_BOOT_SIZE);
- platform_device_register(&db88f5281_boot_flash);
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
- ORION_MBUS_DEVBUS_ATTR(0),
- DB88F5281_7SEG_BASE,
- DB88F5281_7SEG_SIZE);
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
- ORION_MBUS_DEVBUS_ATTR(1),
- DB88F5281_NOR_BASE,
- DB88F5281_NOR_SIZE);
- platform_device_register(&db88f5281_nor_flash);
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
- ORION_MBUS_DEVBUS_ATTR(2),
- DB88F5281_NAND_BASE,
- DB88F5281_NAND_SIZE);
- platform_device_register(&db88f5281_nand_flash);
-
- i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
-}
-
-MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
- /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = db88f5281_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 87cb47220e82..d69259b6b60d 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -696,12 +696,12 @@ static void __init dns323_init(void)
pr_err("DNS-323: failed to setup power-off GPIO\n");
pm_power_off = dns323c_power_off;
- /* Now, -this- should theorically be done by the sata_mv driver
+ /* Now, -this- should theoretically be done by the sata_mv driver
* once I figure out what's going on there. Maybe the behaviour
* of the LEDs should be somewhat passed via the platform_data.
* for now, just whack the register and make the LEDs happy
*
- * Note: AFAIK, rev B1 needs the same treatement but I'll let
+ * Note: AFAIK, rev B1 needs the same treatment but I'll let
* somebody else test it.
*/
writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 1ae775d02d90..e17727e53cb4 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/irq.c
*
* Core IRQ functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/irqs.h b/arch/arm/mach-orion5x/irqs.h
index 506c8e0b30c4..a70c47cfa6bc 100644
--- a/arch/arm/mach-orion5x/irqs.h
+++ b/arch/arm/mach-orion5x/irqs.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* IRQ definitions for Orion SoC
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IRQS_H
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 83d43cff4bd7..acba06618080 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/kurobox_pro-setup.c
*
* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
deleted file mode 100644
index 47ba6e0502f5..000000000000
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * arch/arm/mach-orion5x/ls_hgl-setup.c
- *
- * Maintainer: Zhu Qingsen <zhuqs@cn.fujitsu.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * Linkstation LS-HGL Info
- ****************************************************************************/
-
-/*
- * 256K NOR flash Device bus boot chip select
- */
-
-#define LS_HGL_NOR_BOOT_BASE 0xf4000000
-#define LS_HGL_NOR_BOOT_SIZE SZ_256K
-
-/*****************************************************************************
- * 256KB NOR Flash on BOOT Device
- ****************************************************************************/
-
-static struct physmap_flash_data ls_hgl_nor_flash_data = {
- .width = 1,
-};
-
-static struct resource ls_hgl_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = LS_HGL_NOR_BOOT_BASE,
- .end = LS_HGL_NOR_BOOT_BASE + LS_HGL_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device ls_hgl_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ls_hgl_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &ls_hgl_nor_flash_resource,
-};
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data ls_hgl_eth_data = {
- .phy_addr = 8,
-};
-
-/*****************************************************************************
- * RTC 5C372a on I2C bus
- ****************************************************************************/
-
-static struct i2c_board_info __initdata ls_hgl_i2c_rtc = {
- I2C_BOARD_INFO("rs5c372a", 0x32),
-};
-
-/*****************************************************************************
- * LEDs attached to GPIO
- ****************************************************************************/
-
-#define LS_HGL_GPIO_LED_ALARM 2
-#define LS_HGL_GPIO_LED_INFO 3
-#define LS_HGL_GPIO_LED_FUNC 17
-#define LS_HGL_GPIO_LED_PWR 0
-
-
-static struct gpio_led ls_hgl_led_pins[] = {
- {
- .name = "alarm:red",
- .gpio = LS_HGL_GPIO_LED_ALARM,
- .active_low = 1,
- }, {
- .name = "info:amber",
- .gpio = LS_HGL_GPIO_LED_INFO,
- .active_low = 1,
- }, {
- .name = "func:blue:top",
- .gpio = LS_HGL_GPIO_LED_FUNC,
- .active_low = 1,
- }, {
- .name = "power:blue:bottom",
- .gpio = LS_HGL_GPIO_LED_PWR,
- },
-};
-
-static struct gpio_led_platform_data ls_hgl_led_data = {
- .leds = ls_hgl_led_pins,
- .num_leds = ARRAY_SIZE(ls_hgl_led_pins),
-};
-
-static struct platform_device ls_hgl_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &ls_hgl_led_data,
- },
-};
-
-/****************************************************************************
- * GPIO Attached Keys
- ****************************************************************************/
-#define LS_HGL_GPIO_KEY_FUNC 15
-#define LS_HGL_GPIO_KEY_POWER 8
-#define LS_HGL_GPIO_KEY_AUTOPOWER 10
-
-#define LS_HGL_SW_POWER 0x00
-#define LS_HGL_SW_AUTOPOWER 0x01
-
-static struct gpio_keys_button ls_hgl_buttons[] = {
- {
- .code = KEY_OPTION,
- .gpio = LS_HGL_GPIO_KEY_FUNC,
- .desc = "Function Button",
- .active_low = 1,
- }, {
- .type = EV_SW,
- .code = LS_HGL_SW_POWER,
- .gpio = LS_HGL_GPIO_KEY_POWER,
- .desc = "Power-on Switch",
- .active_low = 1,
- }, {
- .type = EV_SW,
- .code = LS_HGL_SW_AUTOPOWER,
- .gpio = LS_HGL_GPIO_KEY_AUTOPOWER,
- .desc = "Power-auto Switch",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data ls_hgl_button_data = {
- .buttons = ls_hgl_buttons,
- .nbuttons = ARRAY_SIZE(ls_hgl_buttons),
-};
-
-static struct platform_device ls_hgl_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &ls_hgl_button_data,
- },
-};
-
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-static struct mv_sata_platform_data ls_hgl_sata_data = {
- .n_ports = 2,
-};
-
-
-/*****************************************************************************
- * Linkstation LS-HGL specific power off method: reboot
- ****************************************************************************/
-/*
- * On the Linkstation LS-HGL, the shutdown process is following:
- * - Userland monitors key events until the power switch goes to off position
- * - The board reboots
- * - U-boot starts and goes into an idle mode waiting for the user
- * to move the switch to ON position
- */
-
-static void ls_hgl_power_off(void)
-{
- orion5x_restart(REBOOT_HARD, NULL);
-}
-
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-
-#define LS_HGL_GPIO_USB_POWER 9
-#define LS_HGL_GPIO_AUTO_POWER 10
-#define LS_HGL_GPIO_POWER 8
-
-#define LS_HGL_GPIO_HDD_POWER 1
-
-static unsigned int ls_hgl_mpp_modes[] __initdata = {
- MPP0_GPIO, /* LED_PWR */
- MPP1_GPIO, /* HDD_PWR */
- MPP2_GPIO, /* LED_ALARM */
- MPP3_GPIO, /* LED_INFO */
- MPP4_UNUSED,
- MPP5_UNUSED,
- MPP6_GPIO, /* FAN_LCK */
- MPP7_GPIO, /* INIT */
- MPP8_GPIO, /* POWER */
- MPP9_GPIO, /* USB_PWR */
- MPP10_GPIO, /* AUTO_POWER */
- MPP11_UNUSED, /* LED_ETH (dummy) */
- MPP12_UNUSED,
- MPP13_UNUSED,
- MPP14_UNUSED,
- MPP15_GPIO, /* FUNC */
- MPP16_UNUSED,
- MPP17_GPIO, /* LED_FUNC */
- MPP18_UNUSED,
- MPP19_UNUSED,
- 0,
-};
-
-static void __init ls_hgl_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(ls_hgl_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_ehci1_init();
- orion5x_eth_init(&ls_hgl_eth_data);
- orion5x_i2c_init();
- orion5x_sata_init(&ls_hgl_sata_data);
- orion5x_uart0_init();
- orion5x_xor_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- LS_HGL_NOR_BOOT_BASE,
- LS_HGL_NOR_BOOT_SIZE);
- platform_device_register(&ls_hgl_nor_flash);
-
- platform_device_register(&ls_hgl_button_device);
-
- platform_device_register(&ls_hgl_leds);
-
- i2c_register_board_info(0, &ls_hgl_i2c_rtc, 1);
-
- /* enable USB power */
- gpio_set_value(LS_HGL_GPIO_USB_POWER, 1);
-
- /* register power-off method */
- pm_power_off = ls_hgl_power_off;
-
- pr_info("%s: finished\n", __func__);
-}
-
-MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
- /* Maintainer: Zhu Qingsen <zhuqs@cn.fujistu.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = ls_hgl_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 19ef18594415..b9855dce6ba0 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/mpp.c
*
* MPP functions for Marvell Orion 5x SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index bf6be4cfd238..695cc683cd83 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/net2big-setup.c
*
* LaCie 2Big Network NAS setup
*
* Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
@@ -432,4 +429,3 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
-
diff --git a/arch/arm/mach-orion5x/orion5x.h b/arch/arm/mach-orion5x/orion5x.h
index 2b66120fba86..26f1ccb8cb28 100644
--- a/arch/arm/mach-orion5x/orion5x.h
+++ b/arch/arm/mach-orion5x/orion5x.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Generic definitions of Orion SoC flavors:
* Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_ORION5X_H
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 92e938bba20d..3313bc5a63ea 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/pci.c
*
* PCI and PCIe functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
@@ -515,18 +512,24 @@ static int __init pci_setup(struct pci_sys_data *sys)
/*****************************************************************************
* General PCIe + PCI
****************************************************************************/
+
+/*
+ * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
+ * is operating as a root complex this needs to be switched to
+ * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
+ * the device. Decoding setup is handled by the orion code.
+ */
static void rc_pci_fixup(struct pci_dev *dev)
{
- /*
- * Prevent enumeration of root complex.
- */
if (dev->bus->parent == NULL && dev->devfn == 0) {
- int i;
-
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
+ struct resource *r;
+
+ dev->class &= 0xff;
+ dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
+ pci_dev_for_each_resource(dev, r) {
+ r->start = 0;
+ r->end = 0;
+ r->flags = 0;
}
}
}
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
deleted file mode 100644
index c65ab7db36ad..000000000000
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
- *
- * Marvell Orion-VoIP FXO Reference Design Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/platform_data/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * RD-88F5181L FXO Info
- ****************************************************************************/
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000
-#define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M
-
-
-/*****************************************************************************
- * 8M NOR Flash on Device bus Boot chip select
- ****************************************************************************/
-static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = {
- .width = 1,
-};
-
-static struct resource rd88f5181l_fxo_nor_boot_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = RD88F5181L_FXO_NOR_BOOT_BASE,
- .end = RD88F5181L_FXO_NOR_BOOT_BASE +
- RD88F5181L_FXO_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &rd88f5181l_fxo_nor_boot_flash_data,
- },
- .num_resources = 1,
- .resource = &rd88f5181l_fxo_nor_boot_flash_resource,
-};
-
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = {
- MPP0_GPIO, /* LED1 CardBus LED (front panel) */
- MPP1_GPIO, /* PCI_intA */
- MPP2_GPIO, /* Hard Reset / Factory Init*/
- MPP3_GPIO, /* FXS or DAA select */
- MPP4_GPIO, /* LED6 - phone LED (front panel) */
- MPP5_GPIO, /* LED5 - phone LED (front panel) */
- MPP6_PCI_CLK, /* CPU PCI refclk */
- MPP7_PCI_CLK, /* PCI/PCIe refclk */
- MPP8_GPIO, /* CardBus reset */
- MPP9_GPIO, /* GE_RXERR */
- MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */
- MPP11_GPIO, /* Lifeline control */
- MPP12_GIGE, /* GE_TXD[4] */
- MPP13_GIGE, /* GE_TXD[5] */
- MPP14_GIGE, /* GE_TXD[6] */
- MPP15_GIGE, /* GE_TXD[7] */
- MPP16_GIGE, /* GE_RXD[4] */
- MPP17_GIGE, /* GE_RXD[5] */
- MPP18_GIGE, /* GE_RXD[6] */
- MPP19_GIGE, /* GE_RXD[7] */
- 0,
-};
-
-static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_NONE,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
-};
-
-static struct dsa_chip_data rd88f5181l_fxo_switch_chip_data = {
- .port_names[0] = "lan2",
- .port_names[1] = "lan1",
- .port_names[2] = "wan",
- .port_names[3] = "cpu",
- .port_names[5] = "lan4",
- .port_names[7] = "lan3",
-};
-
-static void __init rd88f5181l_fxo_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_eth_init(&rd88f5181l_fxo_eth_data);
- orion5x_eth_switch_init(&rd88f5181l_fxo_switch_chip_data);
- orion5x_uart0_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- RD88F5181L_FXO_NOR_BOOT_BASE,
- RD88F5181L_FXO_NOR_BOOT_SIZE);
- platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
-}
-
-static int __init
-rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * Mini-PCI / Cardbus slot.
- */
- return gpio_to_irq(1);
-}
-
-static struct hw_pci rd88f5181l_fxo_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = rd88f5181l_fxo_pci_map_irq,
-};
-
-static int __init rd88f5181l_fxo_pci_init(void)
-{
- if (machine_is_rd88f5181l_fxo()) {
- orion5x_pci_set_cardbus_mode();
- pci_common_init(&rd88f5181l_fxo_pci);
- }
-
- return 0;
-}
-subsys_initcall(rd88f5181l_fxo_pci_init);
-
-MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
- /* Maintainer: Nicolas Pitre <nico@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = rd88f5181l_fxo_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
deleted file mode 100644
index 76b8138d9d79..000000000000
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
- *
- * Marvell Orion-VoIP GE Reference Design Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * RD-88F5181L GE Info
- ****************************************************************************/
-/*
- * 16M NOR flash Device bus boot chip select
- */
-#define RD88F5181L_GE_NOR_BOOT_BASE 0xff000000
-#define RD88F5181L_GE_NOR_BOOT_SIZE SZ_16M
-
-
-/*****************************************************************************
- * 16M NOR Flash on Device bus Boot chip select
- ****************************************************************************/
-static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
- .width = 1,
-};
-
-static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = RD88F5181L_GE_NOR_BOOT_BASE,
- .end = RD88F5181L_GE_NOR_BOOT_BASE +
- RD88F5181L_GE_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device rd88f5181l_ge_nor_boot_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &rd88f5181l_ge_nor_boot_flash_data,
- },
- .num_resources = 1,
- .resource = &rd88f5181l_ge_nor_boot_flash_resource,
-};
-
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
- MPP0_GPIO, /* LED1 */
- MPP1_GPIO, /* LED5 */
- MPP2_GPIO, /* LED4 */
- MPP3_GPIO, /* LED3 */
- MPP4_GPIO, /* PCI_intA */
- MPP5_GPIO, /* RTC interrupt */
- MPP6_PCI_CLK, /* CPU PCI refclk */
- MPP7_PCI_CLK, /* PCI/PCIe refclk */
- MPP8_GPIO, /* 88e6131 interrupt */
- MPP9_GPIO, /* GE_RXERR */
- MPP10_GPIO, /* PCI_intB */
- MPP11_GPIO, /* LED2 */
- MPP12_GIGE, /* GE_TXD[4] */
- MPP13_GIGE, /* GE_TXD[5] */
- MPP14_GIGE, /* GE_TXD[6] */
- MPP15_GIGE, /* GE_TXD[7] */
- MPP16_GIGE, /* GE_RXD[4] */
- MPP17_GIGE, /* GE_RXD[5] */
- MPP18_GIGE, /* GE_RXD[6] */
- MPP19_GIGE, /* GE_RXD[7] */
- 0,
-};
-
-static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_NONE,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
-};
-
-static struct dsa_chip_data rd88f5181l_ge_switch_chip_data = {
- .port_names[0] = "lan2",
- .port_names[1] = "lan1",
- .port_names[2] = "wan",
- .port_names[3] = "cpu",
- .port_names[5] = "lan4",
- .port_names[7] = "lan3",
-};
-
-static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
- I2C_BOARD_INFO("ds1338", 0x68),
-};
-
-static void __init rd88f5181l_ge_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_eth_init(&rd88f5181l_ge_eth_data);
- orion5x_eth_switch_init(&rd88f5181l_ge_switch_chip_data);
- orion5x_i2c_init();
- orion5x_uart0_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- RD88F5181L_GE_NOR_BOOT_BASE,
- RD88F5181L_GE_NOR_BOOT_SIZE);
- platform_device_register(&rd88f5181l_ge_nor_boot_flash);
-
- i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
-}
-
-static int __init
-rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * Cardbus slot.
- */
- if (pin == 1)
- return gpio_to_irq(4);
- else
- return gpio_to_irq(10);
-}
-
-static struct hw_pci rd88f5181l_ge_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = rd88f5181l_ge_pci_map_irq,
-};
-
-static int __init rd88f5181l_ge_pci_init(void)
-{
- if (machine_is_rd88f5181l_ge()) {
- orion5x_pci_set_cardbus_mode();
- pci_common_init(&rd88f5181l_ge_pci);
- }
-
- return 0;
-}
-subsys_initcall(rd88f5181l_ge_pci_init);
-
-MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
- /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = rd88f5181l_ge_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
deleted file mode 100644
index fe3e67c81fb8..000000000000
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * arch/arm/mach-orion5x/rd88f5182-setup.c
- *
- * Marvell Orion-NAS Reference Design Setup
- *
- * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ata_platform.h>
-#include <linux/i2c.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-#include "mpp.h"
-#include "orion5x.h"
-
-/*****************************************************************************
- * RD-88F5182 Info
- ****************************************************************************/
-
-/*
- * 512K NOR flash Device bus boot chip select
- */
-
-#define RD88F5182_NOR_BOOT_BASE 0xf4000000
-#define RD88F5182_NOR_BOOT_SIZE SZ_512K
-
-/*
- * 16M NOR flash on Device bus chip select 1
- */
-
-#define RD88F5182_NOR_BASE 0xfc000000
-#define RD88F5182_NOR_SIZE SZ_16M
-
-/*
- * PCI
- */
-
-#define RD88F5182_PCI_SLOT0_OFFS 7
-#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
-#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
-
-/*****************************************************************************
- * 16M NOR Flash on Device bus CS1
- ****************************************************************************/
-
-static struct physmap_flash_data rd88f5182_nor_flash_data = {
- .width = 1,
-};
-
-static struct resource rd88f5182_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = RD88F5182_NOR_BASE,
- .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
-};
-
-static struct platform_device rd88f5182_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &rd88f5182_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &rd88f5182_nor_flash_resource,
-};
-
-/*****************************************************************************
- * Use GPIO LED as CPU active indication
- ****************************************************************************/
-
-#define RD88F5182_GPIO_LED 0
-
-static struct gpio_led rd88f5182_gpio_led_pins[] = {
- {
- .name = "rd88f5182:cpu",
- .default_trigger = "cpu0",
- .gpio = RD88F5182_GPIO_LED,
- },
-};
-
-static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
- .leds = rd88f5182_gpio_led_pins,
- .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins),
-};
-
-static struct platform_device rd88f5182_gpio_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &rd88f5182_gpio_led_data,
- },
-};
-
-/*****************************************************************************
- * PCI
- ****************************************************************************/
-
-static void __init rd88f5182_pci_preinit(void)
-{
- int pin;
-
- /*
- * Configure PCI GPIO IRQ pins
- */
- pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
- if (gpio_request(pin, "PCI IntA") == 0) {
- if (gpio_direction_input(pin) == 0) {
- irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
- } else {
- printk(KERN_ERR "rd88f5182_pci_preinit failed to "
- "set_irq_type pin %d\n", pin);
- gpio_free(pin);
- }
- } else {
- printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
- }
-
- pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
- if (gpio_request(pin, "PCI IntB") == 0) {
- if (gpio_direction_input(pin) == 0) {
- irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
- } else {
- printk(KERN_ERR "rd88f5182_pci_preinit failed to "
- "set_irq_type pin %d\n", pin);
- gpio_free(pin);
- }
- } else {
- printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
- }
-}
-
-static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * PCI IRQs are connected via GPIOs
- */
- switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
- case 0:
- if (pin == 1)
- return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
- else
- return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
- default:
- return -1;
- }
-}
-
-static struct hw_pci rd88f5182_pci __initdata = {
- .nr_controllers = 2,
- .preinit = rd88f5182_pci_preinit,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = rd88f5182_pci_map_irq,
-};
-
-static int __init rd88f5182_pci_init(void)
-{
- if (machine_is_rd88f5182())
- pci_common_init(&rd88f5182_pci);
-
- return 0;
-}
-
-subsys_initcall(rd88f5182_pci_init);
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-/*****************************************************************************
- * RTC DS1338 on I2C bus
- ****************************************************************************/
-static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
- I2C_BOARD_INFO("ds1338", 0x68),
-};
-
-/*****************************************************************************
- * Sata
- ****************************************************************************/
-static struct mv_sata_platform_data rd88f5182_sata_data = {
- .n_ports = 2,
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int rd88f5182_mpp_modes[] __initdata = {
- MPP0_GPIO, /* Debug Led */
- MPP1_GPIO, /* Reset Switch */
- MPP2_UNUSED,
- MPP3_GPIO, /* RTC Int */
- MPP4_GPIO,
- MPP5_GPIO,
- MPP6_GPIO, /* PCI_intA */
- MPP7_GPIO, /* PCI_intB */
- MPP8_UNUSED,
- MPP9_UNUSED,
- MPP10_UNUSED,
- MPP11_UNUSED,
- MPP12_SATA_LED, /* SATA 0 presence */
- MPP13_SATA_LED, /* SATA 1 presence */
- MPP14_SATA_LED, /* SATA 0 active */
- MPP15_SATA_LED, /* SATA 1 active */
- MPP16_UNUSED,
- MPP17_UNUSED,
- MPP18_UNUSED,
- MPP19_UNUSED,
- 0,
-};
-
-static void __init rd88f5182_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(rd88f5182_mpp_modes);
-
- /*
- * MPP[20] PCI Clock to MV88F5182
- * MPP[21] PCI Clock to mini PCI CON11
- * MPP[22] USB 0 over current indication
- * MPP[23] USB 1 over current indication
- * MPP[24] USB 1 over current enable
- * MPP[25] USB 0 over current enable
- */
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_ehci1_init();
- orion5x_eth_init(&rd88f5182_eth_data);
- orion5x_i2c_init();
- orion5x_sata_init(&rd88f5182_sata_data);
- orion5x_uart0_init();
- orion5x_xor_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- RD88F5182_NOR_BOOT_BASE,
- RD88F5182_NOR_BOOT_SIZE);
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
- ORION_MBUS_DEVBUS_ATTR(1),
- RD88F5182_NOR_BASE,
- RD88F5182_NOR_SIZE);
- platform_device_register(&rd88f5182_nor_flash);
- platform_device_register(&rd88f5182_gpio_leds);
-
- i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
-}
-
-MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
- /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = rd88f5182_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
deleted file mode 100644
index 5f388a1ed1e4..000000000000
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c
- *
- * Marvell Orion-1-90 AP GE Reference Design Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/ethtool.h>
-#include <linux/platform_data/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-#include "orion5x.h"
-
-static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
- .phy_addr = -1,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
-};
-
-static struct dsa_chip_data rd88f6183ap_ge_switch_chip_data = {
- .port_names[0] = "lan1",
- .port_names[1] = "lan2",
- .port_names[2] = "lan3",
- .port_names[3] = "lan4",
- .port_names[4] = "wan",
- .port_names[5] = "cpu",
-};
-
-static struct mtd_partition rd88f6183ap_ge_partitions[] = {
- {
- .name = "kernel",
- .offset = 0x00000000,
- .size = 0x00200000,
- }, {
- .name = "rootfs",
- .offset = 0x00200000,
- .size = 0x00500000,
- }, {
- .name = "nvram",
- .offset = 0x00700000,
- .size = 0x00080000,
- },
-};
-
-static struct flash_platform_data rd88f6183ap_ge_spi_slave_data = {
- .type = "m25p64",
- .nr_parts = ARRAY_SIZE(rd88f6183ap_ge_partitions),
- .parts = rd88f6183ap_ge_partitions,
-};
-
-static struct spi_board_info __initdata rd88f6183ap_ge_spi_slave_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &rd88f6183ap_ge_spi_slave_data,
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-static void __init rd88f6183ap_ge_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_eth_init(&rd88f6183ap_ge_eth_data);
- orion5x_eth_switch_init(&rd88f6183ap_ge_switch_chip_data);
- spi_register_board_info(rd88f6183ap_ge_spi_slave_info,
- ARRAY_SIZE(rd88f6183ap_ge_spi_slave_info));
- orion5x_spi_init();
- orion5x_uart0_init();
-}
-
-static struct hw_pci rd88f6183ap_ge_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = orion5x_pci_map_irq,
-};
-
-static int __init rd88f6183ap_ge_pci_init(void)
-{
- if (machine_is_rd88f6183ap_ge()) {
- orion5x_pci_disable();
- pci_common_init(&rd88f6183ap_ge_pci);
- }
-
- return 0;
-}
-subsys_initcall(rd88f6183ap_ge_pci_init);
-
-MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
- /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = rd88f6183ap_ge_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index a39764faf2a0..af810e7ccd79 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/ts78xx-setup.c
*
* Maintainer: Alexander Clouter <alex@digriz.org.uk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
deleted file mode 100644
index 83589a28a491..000000000000
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/arm/mach-orion5x/wnr854t-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/platform_data/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int wnr854t_mpp_modes[] __initdata = {
- MPP0_GPIO, /* Power LED green (0=on) */
- MPP1_GPIO, /* Reset Button (0=off) */
- MPP2_GPIO, /* Power LED blink (0=off) */
- MPP3_GPIO, /* WAN Status LED amber (0=off) */
- MPP4_GPIO, /* PCI int */
- MPP5_GPIO, /* ??? */
- MPP6_GPIO, /* ??? */
- MPP7_GPIO, /* ??? */
- MPP8_UNUSED, /* ??? */
- MPP9_GIGE, /* GE_RXERR */
- MPP10_UNUSED, /* ??? */
- MPP11_UNUSED, /* ??? */
- MPP12_GIGE, /* GE_TXD[4] */
- MPP13_GIGE, /* GE_TXD[5] */
- MPP14_GIGE, /* GE_TXD[6] */
- MPP15_GIGE, /* GE_TXD[7] */
- MPP16_GIGE, /* GE_RXD[4] */
- MPP17_GIGE, /* GE_RXD[5] */
- MPP18_GIGE, /* GE_RXD[6] */
- MPP19_GIGE, /* GE_RXD[7] */
- 0,
-};
-
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define WNR854T_NOR_BOOT_BASE 0xf4000000
-#define WNR854T_NOR_BOOT_SIZE SZ_8M
-
-static struct mtd_partition wnr854t_nor_flash_partitions[] = {
- {
- .name = "kernel",
- .offset = 0x00000000,
- .size = 0x00100000,
- }, {
- .name = "rootfs",
- .offset = 0x00100000,
- .size = 0x00660000,
- }, {
- .name = "uboot",
- .offset = 0x00760000,
- .size = 0x00040000,
- },
-};
-
-static struct physmap_flash_data wnr854t_nor_flash_data = {
- .width = 2,
- .parts = wnr854t_nor_flash_partitions,
- .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions),
-};
-
-static struct resource wnr854t_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = WNR854T_NOR_BOOT_BASE,
- .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device wnr854t_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &wnr854t_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &wnr854t_nor_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data wnr854t_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_NONE,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
-};
-
-static struct dsa_chip_data wnr854t_switch_chip_data = {
- .port_names[0] = "lan3",
- .port_names[1] = "lan4",
- .port_names[2] = "wan",
- .port_names[3] = "cpu",
- .port_names[5] = "lan1",
- .port_names[7] = "lan2",
-};
-
-static void __init wnr854t_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(wnr854t_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_eth_init(&wnr854t_eth_data);
- orion5x_eth_switch_init(&wnr854t_switch_chip_data);
- orion5x_uart0_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- WNR854T_NOR_BOOT_BASE,
- WNR854T_NOR_BOOT_SIZE);
- platform_device_register(&wnr854t_nor_flash);
-}
-
-static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * Mini-PCI slot.
- */
- if (slot == 7)
- return gpio_to_irq(4);
-
- return -1;
-}
-
-static struct hw_pci wnr854t_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = wnr854t_pci_map_irq,
-};
-
-static int __init wnr854t_pci_init(void)
-{
- if (machine_is_wnr854t())
- pci_common_init(&wnr854t_pci);
-
- return 0;
-}
-subsys_initcall(wnr854t_pci_init);
-
-MACHINE_START(WNR854T, "Netgear WNR854T")
- /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = wnr854t_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
deleted file mode 100644
index cea08d4a2597..000000000000
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * arch/arm/mach-orion5x/wrt350n-v2-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/platform_data/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-/*
- * LEDs attached to GPIO
- */
-static struct gpio_led wrt350n_v2_led_pins[] = {
- {
- .name = "wrt350nv2:green:power",
- .gpio = 0,
- .active_low = 1,
- }, {
- .name = "wrt350nv2:green:security",
- .gpio = 1,
- .active_low = 1,
- }, {
- .name = "wrt350nv2:orange:power",
- .gpio = 5,
- .active_low = 1,
- }, {
- .name = "wrt350nv2:green:usb",
- .gpio = 6,
- .active_low = 1,
- }, {
- .name = "wrt350nv2:green:wireless",
- .gpio = 7,
- .active_low = 1,
- },
-};
-
-static struct gpio_led_platform_data wrt350n_v2_led_data = {
- .leds = wrt350n_v2_led_pins,
- .num_leds = ARRAY_SIZE(wrt350n_v2_led_pins),
-};
-
-static struct platform_device wrt350n_v2_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &wrt350n_v2_led_data,
- },
-};
-
-/*
- * Buttons attached to GPIO
- */
-static struct gpio_keys_button wrt350n_v2_buttons[] = {
- {
- .code = KEY_RESTART,
- .gpio = 3,
- .desc = "Reset Button",
- .active_low = 1,
- }, {
- .code = KEY_WPS_BUTTON,
- .gpio = 2,
- .desc = "WPS Button",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data wrt350n_v2_button_data = {
- .buttons = wrt350n_v2_buttons,
- .nbuttons = ARRAY_SIZE(wrt350n_v2_buttons),
-};
-
-static struct platform_device wrt350n_v2_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &wrt350n_v2_button_data,
- },
-};
-
-/*
- * General setup
- */
-static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
- MPP0_GPIO, /* Power LED green (0=on) */
- MPP1_GPIO, /* Security LED (0=on) */
- MPP2_GPIO, /* Internal Button (0=on) */
- MPP3_GPIO, /* Reset Button (0=on) */
- MPP4_GPIO, /* PCI int */
- MPP5_GPIO, /* Power LED orange (0=on) */
- MPP6_GPIO, /* USB LED (0=on) */
- MPP7_GPIO, /* Wireless LED (0=on) */
- MPP8_UNUSED, /* ??? */
- MPP9_GIGE, /* GE_RXERR */
- MPP10_UNUSED, /* ??? */
- MPP11_UNUSED, /* ??? */
- MPP12_GIGE, /* GE_TXD[4] */
- MPP13_GIGE, /* GE_TXD[5] */
- MPP14_GIGE, /* GE_TXD[6] */
- MPP15_GIGE, /* GE_TXD[7] */
- MPP16_GIGE, /* GE_RXD[4] */
- MPP17_GIGE, /* GE_RXD[5] */
- MPP18_GIGE, /* GE_RXD[6] */
- MPP19_GIGE, /* GE_RXD[7] */
- 0,
-};
-
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000
-#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M
-
-static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
- {
- .name = "kernel",
- .offset = 0x00000000,
- .size = 0x00760000,
- }, {
- .name = "rootfs",
- .offset = 0x001a0000,
- .size = 0x005c0000,
- }, {
- .name = "lang",
- .offset = 0x00760000,
- .size = 0x00040000,
- }, {
- .name = "nvram",
- .offset = 0x007a0000,
- .size = 0x00020000,
- }, {
- .name = "u-boot",
- .offset = 0x007c0000,
- .size = 0x00040000,
- },
-};
-
-static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
- .width = 1,
- .parts = wrt350n_v2_nor_flash_partitions,
- .nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
-};
-
-static struct resource wrt350n_v2_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = WRT350N_V2_NOR_BOOT_BASE,
- .end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device wrt350n_v2_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &wrt350n_v2_nor_flash_data,
- },
- .num_resources = 1,
- .resource = &wrt350n_v2_nor_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
- .phy_addr = MV643XX_ETH_PHY_NONE,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
-};
-
-static struct dsa_chip_data wrt350n_v2_switch_chip_data = {
- .port_names[0] = "lan2",
- .port_names[1] = "lan1",
- .port_names[2] = "wan",
- .port_names[3] = "cpu",
- .port_names[5] = "lan3",
- .port_names[7] = "lan4",
-};
-
-static void __init wrt350n_v2_init(void)
-{
- /*
- * Setup basic Orion functions. Need to be called early.
- */
- orion5x_init();
-
- orion5x_mpp_conf(wrt350n_v2_mpp_modes);
-
- /*
- * Configure peripherals.
- */
- orion5x_ehci0_init();
- orion5x_eth_init(&wrt350n_v2_eth_data);
- orion5x_eth_switch_init(&wrt350n_v2_switch_chip_data);
- orion5x_uart0_init();
-
- mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
- ORION_MBUS_DEVBUS_BOOT_ATTR,
- WRT350N_V2_NOR_BOOT_BASE,
- WRT350N_V2_NOR_BOOT_SIZE);
- platform_device_register(&wrt350n_v2_nor_flash);
- platform_device_register(&wrt350n_v2_leds);
- platform_device_register(&wrt350n_v2_button_device);
-}
-
-static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot,
- u8 pin)
-{
- int irq;
-
- /*
- * Check for devices with hard-wired IRQs.
- */
- irq = orion5x_pci_map_irq(dev, slot, pin);
- if (irq != -1)
- return irq;
-
- /*
- * Mini-PCI slot.
- */
- if (slot == 7)
- return gpio_to_irq(4);
-
- return -1;
-}
-
-static struct hw_pci wrt350n_v2_pci __initdata = {
- .nr_controllers = 2,
- .setup = orion5x_pci_sys_setup,
- .scan = orion5x_pci_sys_scan_bus,
- .map_irq = wrt350n_v2_pci_map_irq,
-};
-
-static int __init wrt350n_v2_pci_init(void)
-{
- if (machine_is_wrt350n_v2())
- pci_common_init(&wrt350n_v2_pci);
-
- return 0;
-}
-subsys_initcall(wrt350n_v2_pci_init);
-
-MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
- /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
- .atag_offset = 0x100,
- .nr_irqs = ORION5X_NR_IRQS,
- .init_machine = wrt350n_v2_init,
- .map_io = orion5x_map_io,
- .init_early = orion5x_init_early,
- .init_irq = orion5x_init_irq,
- .init_time = orion5x_timer_init,
- .fixup = tag_fixup_mem32,
- .restart = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-oxnas/Kconfig b/arch/arm/mach-oxnas/Kconfig
deleted file mode 100644
index bee5f64c2e5f..000000000000
--- a/arch/arm/mach-oxnas/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-menuconfig ARCH_OXNAS
- bool "Oxford Semiconductor OXNAS Family SoCs"
- select ARCH_HAS_RESET_CONTROLLER
- select COMMON_CLK_OXNAS
- select GPIOLIB
- select MFD_SYSCON
- select OXNAS_RPS_TIMER
- select PINCTRL_OXNAS
- select RESET_CONTROLLER
- select RESET_OXNAS
- select VERSATILE_FPGA_IRQ
- select PINCTRL
- depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
- help
- Support for OxNas SoC family developed by Oxford Semiconductor.
-
-if ARCH_OXNAS
-
-config MACH_OX810SE
- bool "Support OX810SE Based Products"
- depends on ARCH_MULTI_V5
- select CPU_ARM926T
- help
- Include Support for the Oxford Semiconductor OX810SE SoC Based Products.
-
-config MACH_OX820
- bool "Support OX820 Based Products"
- depends on ARCH_MULTI_V6
- select ARM_GIC
- select DMA_CACHE_RWFO if SMP
- select HAVE_SMP
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
- help
- Include Support for the Oxford Semiconductor OX820 SoC Based Products.
-
-endif
diff --git a/arch/arm/mach-oxnas/Makefile b/arch/arm/mach-oxnas/Makefile
deleted file mode 100644
index 0e78ecfe6c49..000000000000
--- a/arch/arm/mach-oxnas/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-oxnas/headsmp.S b/arch/arm/mach-oxnas/headsmp.S
deleted file mode 100644
index 9c0f1479f33a..000000000000
--- a/arch/arm/mach-oxnas/headsmp.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
- * Copyright (c) 2003 ARM Limited
- * All Rights Reserved
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
- __INIT
-
-/*
- * OX820 specific entry point for secondary CPUs.
- */
-ENTRY(ox820_secondary_startup)
- mov r4, #0
- /* invalidate both caches and branch target cache */
- mcr p15, 0, r4, c7, c7, 0
- /*
- * we've been released from the holding pen: secondary_stack
- * should now contain the SVC stack for this core
- */
- b secondary_startup
diff --git a/arch/arm/mach-oxnas/platsmp.c b/arch/arm/mach-oxnas/platsmp.c
deleted file mode 100644
index f0a50b9e61df..000000000000
--- a/arch/arm/mach-oxnas/platsmp.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- */
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include <asm/cacheflush.h>
-#include <asm/cp15.h>
-#include <asm/smp_plat.h>
-#include <asm/smp_scu.h>
-
-extern void ox820_secondary_startup(void);
-
-static void __iomem *cpu_ctrl;
-static void __iomem *gic_cpu_ctrl;
-
-#define HOLDINGPEN_CPU_OFFSET 0xc8
-#define HOLDINGPEN_LOCATION_OFFSET 0xc4
-
-#define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100)
-#define GIC_CPU_CTRL 0x00
-#define GIC_CPU_CTRL_ENABLE 1
-
-static int __init ox820_boot_secondary(unsigned int cpu,
- struct task_struct *idle)
-{
- /*
- * Write the address of secondary startup into the
- * system-wide flags register. The BootMonitor waits
- * until it receives a soft interrupt, and then the
- * secondary CPU branches to this address.
- */
- writel(virt_to_phys(ox820_secondary_startup),
- cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
-
- writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
-
- /*
- * Enable GIC cpu interface in CPU Interface Control Register
- */
- writel(GIC_CPU_CTRL_ENABLE,
- gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
-
- /*
- * Send the secondary CPU a soft interrupt, thereby causing
- * the boot monitor to read the system wide flags register,
- * and branch to the address found there.
- */
- arch_send_wakeup_ipi_mask(cpumask_of(cpu));
-
- return 0;
-}
-
-static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
-{
- struct device_node *np;
- void __iomem *scu_base;
-
- np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
- scu_base = of_iomap(np, 0);
- of_node_put(np);
- if (!scu_base)
- return;
-
- /* Remap CPU Interrupt Interface Registers */
- np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
- gic_cpu_ctrl = of_iomap(np, 1);
- of_node_put(np);
- if (!gic_cpu_ctrl)
- goto unmap_scu;
-
- np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
- cpu_ctrl = of_iomap(np, 0);
- of_node_put(np);
- if (!cpu_ctrl)
- goto unmap_scu;
-
- scu_enable(scu_base);
- flush_cache_all();
-
-unmap_scu:
- iounmap(scu_base);
-}
-
-static const struct smp_operations ox820_smp_ops __initconst = {
- .smp_prepare_cpus = ox820_smp_prepare_cpus,
- .smp_boot_secondary = ox820_boot_secondary,
-};
-
-CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 57f0be4065c1..10e472f4fa43 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -1,9 +1,20 @@
# SPDX-License-Identifier: GPL-2.0-only
-if ARCH_PXA
-
-menu "Intel PXA2xx/PXA3xx Implementations"
+menuconfig ARCH_PXA
+ bool "PXA2xx/PXA3xx-based"
+ depends on ARCH_MULTI_V5
+ depends on CPU_LITTLE_ENDIAN
+ select ARM_CPU_SUSPEND if PM
+ select CLKSRC_PXA
+ select CLKSRC_MMIO
+ select TIMER_OF
+ select CPU_XSCALE if !CPU_XSC3
+ select GPIO_PXA
+ select GPIOLIB
+ select PLAT_PXA
+ help
+ Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
-comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
+if ARCH_PXA
config MACH_PXA25X_DT
bool "Support PXA25x platforms from device tree"
@@ -30,6 +41,8 @@ config MACH_PXA27X_DT
config MACH_PXA3XX_DT
bool "Support PXA3xx platforms from device tree"
select CPU_PXA300
+ select CPU_PXA310
+ select CPU_PXA320
select PINCTRL
select POWER_SUPPLY
select PXA3xx
@@ -39,100 +52,9 @@ config MACH_PXA3XX_DT
the device tree. Needn't select any other machine while
MACH_PXA3XX_DT is enabled.
-config ARCH_LUBBOCK
- bool "Intel DBPXA250 Development Platform (aka Lubbock)"
- select GPIO_REG
- select PXA25x
- select SA1111
-
-config MACH_MAINSTONE
- bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
- select GPIO_REG
- select PXA27x
-
-config MACH_ZYLONITE
- bool
- select PXA3xx
-
-config MACH_ZYLONITE300
- bool "PXA3xx Development Platform (aka Zylonite) PXA300/310"
- select CPU_PXA300
- select CPU_PXA310
- select MACH_ZYLONITE
-
-config MACH_ZYLONITE320
- bool "PXA3xx Development Platform (aka Zylonite) PXA320"
- select CPU_PXA320
- select MACH_ZYLONITE
-
-config MACH_LITTLETON
- bool "PXA3xx Form Factor Platform (aka Littleton)"
- select CPU_PXA300
- select CPU_PXA310
- select PXA3xx
-
-config MACH_TAVOREVB
- bool "PXA930 Evaluation Board (aka TavorEVB)"
- select CPU_PXA930
- select CPU_PXA935
- select PXA3xx
- select FB
- select FB_PXA
-
-config MACH_SAAR
- bool "PXA930 Handheld Platform (aka SAAR)"
- select CPU_PXA930
- select CPU_PXA935
- select PXA3xx
- select FB
- select FB_PXA
-
-comment "Third Party Dev Platforms (sorted by vendor name)"
-
-config ARCH_PXA_IDP
- bool "Accelent Xscale IDP"
- select PXA25x
-
-config ARCH_VIPER
- bool "Arcom/Eurotech VIPER SBC"
- select ARCOM_PCMCIA
- select I2C_GPIO if I2C=y
- select ISA
- select PXA25x
-
-config MACH_ARCOM_ZEUS
- bool "Arcom/Eurotech ZEUS SBC"
- select ARCOM_PCMCIA
- select ISA
- select PXA27x
-
-config MACH_BALLOON3
- bool "Balloon 3 board"
- select IWMMXT
- select PXA27x
-
-config MACH_CSB726
- bool "Enable Cogent CSB726 System On a Module"
- select IWMMXT
- select PXA27x
- help
- Say Y here if you intend to run this kernel on a Cogent
- CSB726 System On Module.
-
-config CSB726_CSB701
- bool "Enable support for CSB701 baseboard"
- depends on MACH_CSB726
-
-config MACH_CM_X300
- bool "CompuLab CM-X300 modules"
- select CPU_PXA300
- select CPU_PXA310
- select PXA3xx
+if ATAGS
-config MACH_CAPC7117
- bool "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM"
- select CPU_PXA320
- select PXA3xx
+comment "Legacy board files"
config ARCH_GUMSTIX
bool "Gumstix XScale 255 boards"
@@ -153,281 +75,6 @@ config GUMSTIX_AM300EPD
endchoice
-config MACH_XCEP
- bool "Iskratel Electronics XCEP"
- select MTD
- select MTD_CFI
- select MTD_CFI_INTELEXT
- select MTD_PHYSMAP
- select PXA25x
- help
- PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
- Tuned for usage in Libera instruments for particle accelerators.
-
-config TRIZEPS_PXA
- bool "PXA based Keith und Koep Trizeps DIMM-Modules"
-
-config MACH_TRIZEPS4
- bool "Keith und Koep Trizeps4 DIMM-Module"
- depends on TRIZEPS_PXA
- select PXA27x
- select TRIZEPS_PCMCIA
-
-config MACH_TRIZEPS4WL
- bool "Keith und Koep Trizeps4-WL DIMM-Module"
- depends on TRIZEPS_PXA
- select MACH_TRIZEPS4
- select PXA27x
- select TRIZEPS_PCMCIA
-
-choice
- prompt "Select base board for Trizeps module"
- depends on TRIZEPS_PXA
-
-config MACH_TRIZEPS_CONXS
- bool "ConXS Eval Board"
-
-config MACH_TRIZEPS_UCONXS
- bool "uConXS Eval Board"
-
-config MACH_TRIZEPS_ANY
- bool "another Board"
-
-endchoice
-
-config ARCOM_PCMCIA
- bool
- help
- Generic option for Arcom Viper/Zeus PCMCIA
-
-config TRIZEPS_PCMCIA
- bool
- help
- Enable PCMCIA support for Trizeps modules
-
-config MACH_LOGICPD_PXA270
- bool "LogicPD PXA270 Card Engine Development Platform"
- select PXA27x
-
-config MACH_PCM027
- bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
- select IWMMXT
- select PXA27x
-
-config MACH_PCM990_BASEBOARD
- bool "PHYTEC PCM-990 development board"
- depends on MACH_PCM027
-
-choice
- prompt "display on pcm990"
- depends on MACH_PCM990_BASEBOARD
-
-config PCM990_DISPLAY_SHARP
- bool "sharp lq084v1dg21 stn display"
-
-config PCM990_DISPLAY_NEC
- bool "nec nl6448bc20_18d tft display"
-
-config PCM990_DISPLAY_NONE
- bool "no display"
-
-endchoice
-
-config MACH_COLIBRI
- bool "Toradex Colibri PXA270"
- select PXA27x
-
-config MACH_COLIBRI_PXA270_INCOME
- bool "Income s.r.o. PXA270 SBC"
- depends on MACH_COLIBRI
- select PXA27x
-
-config MACH_COLIBRI300
- bool "Toradex Colibri PXA300/310"
- select CPU_PXA300
- select CPU_PXA310
- select PXA3xx
-
-config MACH_COLIBRI320
- bool "Toradex Colibri PXA320"
- select CPU_PXA320
- select PXA3xx
-
-config MACH_COLIBRI_EVALBOARD
- bool "Toradex Colibri Evaluation Carrier Board support"
- depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320
-
-config MACH_VPAC270
- bool "Voipac PXA270"
- select HAVE_PATA_PLATFORM
- select PXA27x
- help
- PXA270 based Single Board Computer.
-
-comment "End-user Products (sorted by vendor name)"
-
-config MACH_H4700
- bool "HP iPAQ hx4700"
- select IWMMXT
- select PXA27x
-
-config MACH_H5000
- bool "HP iPAQ h5000"
- select PXA25x
-
-config MACH_HIMALAYA
- bool "HTC Himalaya Support"
- select CPU_PXA26x
-
-config MACH_MAGICIAN
- bool "Enable HTC Magician Support"
- select IWMMXT
- select PXA27x
-
-config MACH_MIOA701
- bool "Mitac Mio A701 Support"
- select IWMMXT
- select PXA27x
- help
- Say Y here if you intend to run this kernel on a
- MIO A701. Currently there is only basic support
- for this PDA.
-
-config PXA_EZX
- bool "Motorola EZX Platform"
- select IWMMXT
- select PXA27x
-
-config MACH_EZX_A780
- bool "Motorola EZX A780"
- default y
- depends on PXA_EZX
-
-config MACH_EZX_E680
- bool "Motorola EZX E680"
- default y
- depends on PXA_EZX
-
-config MACH_EZX_A1200
- bool "Motorola EZX A1200"
- default y
- depends on PXA_EZX
-
-config MACH_EZX_A910
- bool "Motorola EZX A910"
- default y
- depends on PXA_EZX
-
-config MACH_EZX_E6
- bool "Motorola EZX E6"
- default y
- depends on PXA_EZX
-
-config MACH_EZX_E2
- bool "Motorola EZX E2"
- default y
- depends on PXA_EZX
-
-config MACH_MP900C
- bool "Nec Mobilepro 900/c"
- select PXA25x
-
-config ARCH_PXA_PALM
- bool "PXA based Palm PDAs"
-
-config MACH_PALM27X
- bool
-
-config MACH_PALMTE2
- bool "Palm Tungsten|E2"
- default y
- depends on ARCH_PXA_PALM
- select PXA25x
- help
- Say Y here if you intend to run this kernel on a Palm Tungsten|E2
- handheld computer.
-
-config MACH_PALMTC
- bool "Palm Tungsten|C"
- default y
- depends on ARCH_PXA_PALM
- select PXA25x
- help
- Say Y here if you intend to run this kernel on a Palm Tungsten|C
- handheld computer.
-
-config MACH_PALMT5
- bool "Palm Tungsten|T5"
- default y
- depends on ARCH_PXA_PALM
- select IWMMXT
- select MACH_PALM27X
- select PXA27x
- help
- Say Y here if you intend to run this kernel on a Palm Tungsten|T5
- handheld computer.
-
-config MACH_PALMTX
- bool "Palm T|X"
- default y
- depends on ARCH_PXA_PALM
- select IWMMXT
- select MACH_PALM27X
- select PXA27x
- help
- Say Y here if you intend to run this kernel on a Palm T|X
- handheld computer.
-
-config MACH_PALMZ72
- bool "Palm Zire 72"
- default y
- depends on ARCH_PXA_PALM
- select IWMMXT
- select MACH_PALM27X
- select PXA27x
- help
- Say Y here if you intend to run this kernel on Palm Zire 72
- handheld computer.
-
-config MACH_PALMLD
- bool "Palm LifeDrive"
- default y
- depends on ARCH_PXA_PALM
- select IWMMXT
- select MACH_PALM27X
- select PXA27x
- help
- Say Y here if you intend to run this kernel on a Palm LifeDrive
- handheld computer.
-
-config PALM_TREO
- bool
- depends on ARCH_PXA_PALM
-
-config MACH_CENTRO
- bool "Palm Centro 685 (GSM)"
- default y
- depends on ARCH_PXA_PALM
- select IWMMXT
- select MACH_PALM27X
- select PALM_TREO
- select PXA27x
- help
- Say Y here if you intend to run this kernel on Palm Centro 685 (GSM)
- smartphone.
-
-config MACH_TREO680
- bool "Palm Treo 680"
- default y
- depends on ARCH_PXA_PALM
- select IWMMXT
- select MACH_PALM27X
- select PALM_TREO
- select PXA27x
- help
- Say Y here if you intend to run this kernel on Palm Treo 680
- smartphone.
-
config PXA_SHARPSL
bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
select SHARP_PARAM
@@ -447,30 +94,6 @@ config PXA_SHARPSL_DETECT_MACH_ID
the Zaurus machine ID at run-time. For latest kexec-based
boot loader, this is not necessary.
-config MACH_POODLE
- bool "Enable Sharp SL-5600 (Poodle) Support"
- depends on PXA_SHARPSL
- select PXA25x
- select SHARP_LOCOMO
-
-config MACH_CORGI
- bool "Enable Sharp SL-C700 (Corgi) Support"
- depends on PXA_SHARPSL
- select PXA25x
- select PXA_SHARP_C7xx
-
-config MACH_SHEPHERD
- bool "Enable Sharp SL-C750 (Shepherd) Support"
- depends on PXA_SHARPSL
- select PXA25x
- select PXA_SHARP_C7xx
-
-config MACH_HUSKY
- bool "Enable Sharp SL-C760 (Husky) Support"
- depends on PXA_SHARPSL
- select PXA25x
- select PXA_SHARP_C7xx
-
config MACH_AKITA
bool "Enable Sharp SL-1000 (Akita) Support"
depends on PXA_SHARPSL
@@ -492,92 +115,7 @@ config MACH_BORZOI
select PXA27x
select PXA_SHARP_Cxx00
-config MACH_TOSA
- bool "Enable Sharp SL-6000x (Tosa) Support"
- depends on PXA_SHARPSL
- select PXA25x
-
-config TOSA_BT
- tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
- depends on MACH_TOSA && NET
- select RFKILL
- help
- This is a simple driver that is able to control
- the state of built in bluetooth chip on tosa.
-
-config TOSA_USE_EXT_KEYCODES
- bool "Tosa keyboard: use extended keycodes"
- depends on MACH_TOSA
- help
- Say Y here to enable the tosa keyboard driver to generate extended
- (>= 127) keycodes. Be aware, that they can't be correctly interpreted
- by either console keyboard driver or by Kdrive keybd driver.
-
- Say Y only if you know, what you are doing!
-
-config MACH_ICONTROL
- bool "TMT iControl/SafeTCam based on the MXM-8x10 CoM"
- select CPU_PXA320
- select PXA3xx
-
-config ARCH_PXA_ESERIES
- bool "PXA based Toshiba e-series PDAs"
- select FB_W100
- select FB
- select PXA25x
-
-config MACH_E330
- bool "Toshiba e330"
- default y
- depends on ARCH_PXA_ESERIES
- help
- Say Y here if you intend to run this kernel on a Toshiba
- e330 family PDA.
-
-config MACH_E350
- bool "Toshiba e350"
- default y
- depends on ARCH_PXA_ESERIES
- help
- Say Y here if you intend to run this kernel on a Toshiba
- e350 family PDA.
-
-config MACH_E740
- bool "Toshiba e740"
- default y
- depends on ARCH_PXA_ESERIES
- help
- Say Y here if you intend to run this kernel on a Toshiba
- e740 family PDA.
-
-config MACH_E750
- bool "Toshiba e750"
- default y
- depends on ARCH_PXA_ESERIES
- help
- Say Y here if you intend to run this kernel on a Toshiba
- e750 family PDA.
-
-config MACH_E400
- bool "Toshiba e400"
- default y
- depends on ARCH_PXA_ESERIES
- help
- Say Y here if you intend to run this kernel on a Toshiba
- e400 family PDA.
-
-config MACH_E800
- bool "Toshiba e800"
- default y
- depends on ARCH_PXA_ESERIES
- help
- Say Y here if you intend to run this kernel on a Toshiba
- e800 family PDA.
-
-config MACH_ZIPIT2
- bool "Zipit Z2 Handheld"
- select PXA27x
-endmenu
+endif # ATAGS
config PXA25x
bool
@@ -591,12 +129,6 @@ config PXA27x
help
Select code specific to PXA27x variants
-config CPU_PXA26x
- bool
- select PXA25x
- help
- Select code specific to PXA26x (codename Dalhart)
-
config PXA3xx
bool
select CPU_XSC3
@@ -612,7 +144,6 @@ config CPU_PXA300
config CPU_PXA310
bool
select CPU_PXA300
- select PXA310_ULPI if USB_ULPI
help
PXA310 (codename Monahans-LV)
@@ -622,24 +153,6 @@ config CPU_PXA320
help
PXA320 (codename Monahans-P)
-config CPU_PXA930
- bool
- select PXA3xx
- help
- PXA930 (codename Tavor-P)
-
-config CPU_PXA935
- bool
- select CPU_PXA930
- help
- PXA935 (codename Tavor-P65)
-
-config PXA_SHARP_C7xx
- bool
- select SHARPSL_PM
- help
- Enable support for all Sharp C7xx models
-
config PXA_SHARP_Cxx00
bool
select SHARPSL_PM
@@ -658,16 +171,4 @@ config SHARPSL_PM_MAX1111
select SPI
select SPI_MASTER
-config PXA310_ULPI
- bool
-
-config PXA_SYSTEMS_CPLDS
- tristate "Motherboard cplds"
- default ARCH_LUBBOCK || MACH_MAINSTONE
- help
- This driver supports the Lubbock and Mainstone multifunction chip
- found on the pxa25x development platform system (Lubbock) and pxa27x
- development platform system (Mainstone). This IO board supports the
- interrupts handling, ethernet controller, flash chips, etc ...
-
endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 68730ceb8b7c..faccdd356482 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -12,10 +12,9 @@ obj-$(CONFIG_PM) += pm.o sleep.o standby.o
# SoC-specific code
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
-obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
+obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o
obj-$(CONFIG_CPU_PXA300) += pxa300.o
obj-$(CONFIG_CPU_PXA320) += pxa320.o
-obj-$(CONFIG_CPU_PXA930) += pxa930.o
# NOTE: keep the order of boards in accordance to their order in Kconfig
@@ -24,62 +23,10 @@ obj-$(CONFIG_MACH_PXA25X_DT) += pxa-dt.o
obj-$(CONFIG_MACH_PXA27X_DT) += pxa-dt.o
obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o
-# Intel/Marvell Dev Platforms
-obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
-obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
-obj-$(CONFIG_MACH_ZYLONITE300) += zylonite.o zylonite_pxa300.o
-obj-$(CONFIG_MACH_ZYLONITE320) += zylonite.o zylonite_pxa320.o
-obj-$(CONFIG_MACH_LITTLETON) += littleton.o
-obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
-obj-$(CONFIG_MACH_SAAR) += saar.o
-
# 3rd Party Dev Platforms
-obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
-obj-$(CONFIG_ARCH_VIPER) += viper.o
-obj-$(CONFIG_MACH_ARCOM_ZEUS) += zeus.o
-obj-$(CONFIG_MACH_BALLOON3) += balloon3.o
-obj-$(CONFIG_MACH_CSB726) += csb726.o
-obj-$(CONFIG_CSB726_CSB701) += csb701.o
-obj-$(CONFIG_MACH_CM_X300) += cm-x300.o
-obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o
obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o
obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o
-obj-$(CONFIG_MACH_XCEP) += xcep.o
-obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
-obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
-obj-$(CONFIG_MACH_PCM027) += pcm027.o
-obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
-obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o
-obj-$(CONFIG_MACH_COLIBRI_EVALBOARD) += colibri-evalboard.o
-obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o
-obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o
-obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o
-obj-$(CONFIG_MACH_VPAC270) += vpac270.o
# End-user Products
-obj-$(CONFIG_MACH_H4700) += hx4700.o
-obj-$(CONFIG_MACH_H5000) += h5000.o
-obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o
-obj-$(CONFIG_MACH_MAGICIAN) += magician.o
-obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o
-obj-$(CONFIG_PXA_EZX) += ezx.o
-obj-$(CONFIG_MACH_MP900C) += mp900.o
-obj-$(CONFIG_MACH_PALMTE2) += palmte2.o
-obj-$(CONFIG_MACH_PALMTC) += palmtc.o
-obj-$(CONFIG_MACH_PALM27X) += palm27x.o
-obj-$(CONFIG_MACH_PALMT5) += palmt5.o
-obj-$(CONFIG_MACH_PALMTX) += palmtx.o
-obj-$(CONFIG_MACH_PALMZ72) += palmz72.o
-obj-$(CONFIG_MACH_PALMLD) += palmld.o
-obj-$(CONFIG_PALM_TREO) += palmtreo.o
-obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
-obj-$(CONFIG_MACH_POODLE) += poodle.o
-obj-$(CONFIG_MACH_TOSA) += tosa.o
-obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o
-obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o
-obj-$(CONFIG_MACH_ZIPIT2) += z2.o
-
-obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o
-obj-$(CONFIG_TOSA_BT) += tosa-bt.o
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/addr-map.h
index 93cfe7dbfec6..93cfe7dbfec6 100644
--- a/arch/arm/mach-pxa/include/mach/addr-map.h
+++ b/arch/arm/mach-pxa/addr-map.h
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index 17d08abeeb17..4b55bc89db8f 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -30,7 +30,7 @@
#include "gumstix.h"
#include "mfp-pxa25x.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include <linux/platform_data/video-pxafb.h>
#include "generic.h"
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
deleted file mode 100644
index 26140249c784..000000000000
--- a/arch/arm/mach-pxa/balloon3.c
+++ /dev/null
@@ -1,821 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/balloon3.c
- *
- * Support for Balloonboard.org Balloon3 board.
- *
- * Author: Nick Bane, Wookey, Jonathan McDowell
- * Created: June, 2006
- * Copyright: Toby Churchill Ltd
- * Derived from mainstone.c, by Nico Pitre
- */
-
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/sched.h>
-#include <linux/bitops.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <linux/ioport.h>
-#include <linux/ucb1400.h>
-#include <linux/mtd/mtd.h>
-#include <linux/types.h>
-#include <linux/platform_data/pcf857x.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/mtd/platnand.h>
-#include <linux/mtd/physmap.h>
-#include <linux/regulator/max1586.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <linux/sizes.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/flash.h>
-
-#include "pxa27x.h"
-#include <mach/balloon3.h>
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include "udc.h"
-#include "pxa27x-udc.h"
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long balloon3_pin_config[] __initdata = {
- /* Select BTUART 'COM1/ttyS0' as IO option for pins 42/43/44/45 */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* Reset, configured as GPIO wakeup source */
- GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
-};
-
-/******************************************************************************
- * Compatibility: Parameter parsing
- ******************************************************************************/
-static unsigned long balloon3_irq_enabled;
-
-static unsigned long balloon3_features_present =
- (1 << BALLOON3_FEATURE_OHCI) | (1 << BALLOON3_FEATURE_CF) |
- (1 << BALLOON3_FEATURE_AUDIO) |
- (1 << BALLOON3_FEATURE_TOPPOLY);
-
-int balloon3_has(enum balloon3_features feature)
-{
- return (balloon3_features_present & (1 << feature)) ? 1 : 0;
-}
-EXPORT_SYMBOL_GPL(balloon3_has);
-
-int __init parse_balloon3_features(char *arg)
-{
- if (!arg)
- return 0;
-
- return kstrtoul(arg, 0, &balloon3_features_present);
-}
-early_param("balloon3_features", parse_balloon3_features);
-
-/******************************************************************************
- * Compact Flash slot
- ******************************************************************************/
-#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
-static unsigned long balloon3_cf_pin_config[] __initdata = {
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO79_PSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-};
-
-static void __init balloon3_cf_init(void)
-{
- if (!balloon3_has(BALLOON3_FEATURE_CF))
- return;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_cf_pin_config));
-}
-#else
-static inline void balloon3_cf_init(void) {}
-#endif
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition balloon3_nor_partitions[] = {
- {
- .name = "Flash",
- .offset = 0x00000000,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct physmap_flash_data balloon3_flash_data[] = {
- {
- .width = 2, /* bankwidth in bytes */
- .parts = balloon3_nor_partitions,
- .nr_parts = ARRAY_SIZE(balloon3_nor_partitions)
- }
-};
-
-static struct resource balloon3_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device balloon3_flash = {
- .name = "physmap-flash",
- .id = 0,
- .resource = &balloon3_flash_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = balloon3_flash_data,
- },
-};
-static void __init balloon3_nor_init(void)
-{
- platform_device_register(&balloon3_flash);
-}
-#else
-static inline void balloon3_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * Audio and Touchscreen
- ******************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \
- defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
-static unsigned long balloon3_ac97_pin_config[] __initdata = {
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO113_AC97_nRESET,
- GPIO95_GPIO,
-};
-
-static struct ucb1400_pdata vpac270_ucb1400_pdata = {
- .irq = PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ),
-};
-
-
-static struct platform_device balloon3_ucb1400_device = {
- .name = "ucb1400_core",
- .id = -1,
- .dev = {
- .platform_data = &vpac270_ucb1400_pdata,
- },
-};
-
-static void __init balloon3_ts_init(void)
-{
- if (!balloon3_has(BALLOON3_FEATURE_AUDIO))
- return;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config));
- pxa_set_ac97_info(NULL);
- platform_device_register(&balloon3_ucb1400_device);
-}
-#else
-static inline void balloon3_ts_init(void) {}
-#endif
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static unsigned long balloon3_lcd_pin_config[] __initdata = {
- GPIOxx_LCD_TFT_16BPP,
- GPIO99_GPIO,
-};
-
-static struct pxafb_mode_info balloon3_lcd_modes[] = {
- {
- .pixclock = 38000,
- .xres = 480,
- .yres = 640,
- .bpp = 16,
- .hsync_len = 8,
- .left_margin = 8,
- .right_margin = 8,
- .vsync_len = 2,
- .upper_margin = 4,
- .lower_margin = 5,
- .sync = 0,
- },
-};
-
-static struct pxafb_mach_info balloon3_lcd_screen = {
- .modes = balloon3_lcd_modes,
- .num_modes = ARRAY_SIZE(balloon3_lcd_modes),
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static void balloon3_backlight_power(int on)
-{
- gpio_set_value(BALLOON3_GPIO_RUN_BACKLIGHT, on);
-}
-
-static void __init balloon3_lcd_init(void)
-{
- int ret;
-
- if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY))
- return;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config));
-
- ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON");
- if (ret) {
- pr_err("Requesting BKL-ON GPIO failed!\n");
- goto err;
- }
-
- ret = gpio_direction_output(BALLOON3_GPIO_RUN_BACKLIGHT, 1);
- if (ret) {
- pr_err("Setting BKL-ON GPIO direction failed!\n");
- goto err2;
- }
-
- balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power;
- pxa_set_fb_info(NULL, &balloon3_lcd_screen);
- return;
-
-err2:
- gpio_free(BALLOON3_GPIO_RUN_BACKLIGHT);
-err:
- return;
-}
-#else
-static inline void balloon3_lcd_init(void) {}
-#endif
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static unsigned long balloon3_mmc_pin_config[] __initdata = {
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
-};
-
-static struct pxamci_platform_data balloon3_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 200,
-};
-
-static void __init balloon3_mmc_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config));
- pxa_set_mci_info(&balloon3_mci_platform_data);
-}
-#else
-static inline void balloon3_mmc_init(void) {}
-#endif
-
-/******************************************************************************
- * USB Gadget
- ******************************************************************************/
-#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
-static void balloon3_udc_command(int cmd)
-{
- if (cmd == PXA2XX_UDC_CMD_CONNECT)
- UP2OCR |= UP2OCR_DPPUE | UP2OCR_DPPUBE;
- else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
- UP2OCR &= ~UP2OCR_DPPUE;
-}
-
-static int balloon3_udc_is_connected(void)
-{
- return 1;
-}
-
-static struct pxa2xx_udc_mach_info balloon3_udc_info __initdata = {
- .udc_command = balloon3_udc_command,
- .udc_is_connected = balloon3_udc_is_connected,
- .gpio_pullup = -1,
-};
-
-static void __init balloon3_udc_init(void)
-{
- pxa_set_udc_info(&balloon3_udc_info);
-}
-#else
-static inline void balloon3_udc_init(void) {}
-#endif
-
-/******************************************************************************
- * IrDA
- ******************************************************************************/
-#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE)
-static struct pxaficp_platform_data balloon3_ficp_platform_data = {
- .transceiver_cap = IR_FIRMODE | IR_SIRMODE | IR_OFF,
-};
-
-static void __init balloon3_irda_init(void)
-{
- pxa_set_ficp_info(&balloon3_ficp_platform_data);
-}
-#else
-static inline void balloon3_irda_init(void) {}
-#endif
-
-/******************************************************************************
- * USB Host
- ******************************************************************************/
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static unsigned long balloon3_uhc_pin_config[] __initdata = {
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
-};
-
-static struct pxaohci_platform_data balloon3_ohci_info = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-static void __init balloon3_uhc_init(void)
-{
- if (!balloon3_has(BALLOON3_FEATURE_OHCI))
- return;
- pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_uhc_pin_config));
- pxa_set_ohci_info(&balloon3_ohci_info);
-}
-#else
-static inline void balloon3_uhc_init(void) {}
-#endif
-
-/******************************************************************************
- * LEDs
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-static unsigned long balloon3_led_pin_config[] __initdata = {
- GPIO9_GPIO, /* NAND activity LED */
- GPIO10_GPIO, /* Heartbeat LED */
-};
-
-struct gpio_led balloon3_gpio_leds[] = {
- {
- .name = "balloon3:green:idle",
- .default_trigger = "heartbeat",
- .gpio = BALLOON3_GPIO_LED_IDLE,
- .active_low = 1,
- }, {
- .name = "balloon3:green:nand",
- .default_trigger = "nand-disk",
- .gpio = BALLOON3_GPIO_LED_NAND,
- .active_low = 1,
- },
-};
-
-static struct gpio_led_platform_data balloon3_gpio_led_info = {
- .leds = balloon3_gpio_leds,
- .num_leds = ARRAY_SIZE(balloon3_gpio_leds),
-};
-
-static struct platform_device balloon3_leds = {
- .name = "leds-gpio",
- .id = 0,
- .dev = {
- .platform_data = &balloon3_gpio_led_info,
- }
-};
-
-struct gpio_led balloon3_pcf_gpio_leds[] = {
- {
- .name = "balloon3:green:led0",
- .gpio = BALLOON3_PCF_GPIO_LED0,
- .active_low = 1,
- }, {
- .name = "balloon3:green:led1",
- .gpio = BALLOON3_PCF_GPIO_LED1,
- .active_low = 1,
- }, {
- .name = "balloon3:orange:led2",
- .gpio = BALLOON3_PCF_GPIO_LED2,
- .active_low = 1,
- }, {
- .name = "balloon3:orange:led3",
- .gpio = BALLOON3_PCF_GPIO_LED3,
- .active_low = 1,
- }, {
- .name = "balloon3:orange:led4",
- .gpio = BALLOON3_PCF_GPIO_LED4,
- .active_low = 1,
- }, {
- .name = "balloon3:orange:led5",
- .gpio = BALLOON3_PCF_GPIO_LED5,
- .active_low = 1,
- }, {
- .name = "balloon3:red:led6",
- .gpio = BALLOON3_PCF_GPIO_LED6,
- .active_low = 1,
- }, {
- .name = "balloon3:red:led7",
- .gpio = BALLOON3_PCF_GPIO_LED7,
- .active_low = 1,
- },
-};
-
-static struct gpio_led_platform_data balloon3_pcf_gpio_led_info = {
- .leds = balloon3_pcf_gpio_leds,
- .num_leds = ARRAY_SIZE(balloon3_pcf_gpio_leds),
-};
-
-static struct platform_device balloon3_pcf_leds = {
- .name = "leds-gpio",
- .id = 1,
- .dev = {
- .platform_data = &balloon3_pcf_gpio_led_info,
- }
-};
-
-static void __init balloon3_leds_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_led_pin_config));
- platform_device_register(&balloon3_leds);
- platform_device_register(&balloon3_pcf_leds);
-}
-#else
-static inline void balloon3_leds_init(void) {}
-#endif
-
-/******************************************************************************
- * FPGA IRQ
- ******************************************************************************/
-static void balloon3_mask_irq(struct irq_data *d)
-{
- int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
- balloon3_irq_enabled &= ~(1 << balloon3_irq);
- __raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
-}
-
-static void balloon3_unmask_irq(struct irq_data *d)
-{
- int balloon3_irq = (d->irq - BALLOON3_IRQ(0));
- balloon3_irq_enabled |= (1 << balloon3_irq);
- __raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
-}
-
-static struct irq_chip balloon3_irq_chip = {
- .name = "FPGA",
- .irq_ack = balloon3_mask_irq,
- .irq_mask = balloon3_mask_irq,
- .irq_unmask = balloon3_unmask_irq,
-};
-
-static void balloon3_irq_handler(struct irq_desc *desc)
-{
- unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
- balloon3_irq_enabled;
- do {
- struct irq_data *d = irq_desc_get_irq_data(desc);
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int irq;
-
- /* clear useless edge notification */
- if (chip->irq_ack)
- chip->irq_ack(d);
-
- while (pending) {
- irq = BALLOON3_IRQ(0) + __ffs(pending);
- generic_handle_irq(irq);
- pending &= pending - 1;
- }
- pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
- balloon3_irq_enabled;
- } while (pending);
-}
-
-static void __init balloon3_init_irq(void)
-{
- int irq;
-
- pxa27x_init_irq();
- /* setup extra Balloon3 irqs */
- for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
- irq_set_chip_and_handler(irq, &balloon3_irq_chip,
- handle_level_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-
- irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
- irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
-
- pr_debug("%s: chained handler installed - irq %d automatically "
- "enabled\n", __func__, BALLOON3_AUX_NIRQ);
-}
-
-/******************************************************************************
- * GPIO expander
- ******************************************************************************/
-#if defined(CONFIG_GPIO_PCF857X) || defined(CONFIG_GPIO_PCF857X_MODULE)
-static struct pcf857x_platform_data balloon3_pcf857x_pdata = {
- .gpio_base = BALLOON3_PCF_GPIO_BASE,
- .n_latch = 0,
- .setup = NULL,
- .teardown = NULL,
- .context = NULL,
-};
-
-static struct i2c_board_info __initdata balloon3_i2c_devs[] = {
- {
- I2C_BOARD_INFO("pcf8574a", 0x38),
- .platform_data = &balloon3_pcf857x_pdata,
- },
-};
-
-static void __init balloon3_i2c_init(void)
-{
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(balloon3_i2c_devs));
-}
-#else
-static inline void balloon3_i2c_init(void) {}
-#endif
-
-/******************************************************************************
- * NAND
- ******************************************************************************/
-#if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-static void balloon3_nand_cmd_ctl(struct nand_chip *this, int cmd,
- unsigned int ctrl)
-{
- uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if (ctrl & NAND_CLE)
- balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE;
- else
- balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE;
-
- if (ctrl & NAND_ALE)
- balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE;
- else
- balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE;
-
- if (balloon3_ctl_clr)
- __raw_writel(balloon3_ctl_clr,
- BALLOON3_NAND_CONTROL_REG);
- if (balloon3_ctl_set)
- __raw_writel(balloon3_ctl_set,
- BALLOON3_NAND_CONTROL_REG +
- BALLOON3_FPGA_SETnCLR);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->legacy.IO_ADDR_W);
-}
-
-static void balloon3_nand_select_chip(struct nand_chip *this, int chip)
-{
- if (chip < 0 || chip > 3)
- return;
-
- /* Assert all nCE lines */
- __raw_writew(
- BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
- BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
- BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
-
- /* Deassert correct nCE line */
- __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
- BALLOON3_NAND_CONTROL_REG);
-}
-
-static int balloon3_nand_dev_ready(struct nand_chip *this)
-{
- return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB;
-}
-
-static int balloon3_nand_probe(struct platform_device *pdev)
-{
- uint16_t ver;
- int ret;
-
- __raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
- BALLOON3_NAND_CONTROL2_REG + BALLOON3_FPGA_SETnCLR);
-
- ver = __raw_readw(BALLOON3_FPGA_VER);
- if (ver < 0x4f08)
- pr_warn("The FPGA code, version 0x%04x, is too old. "
- "NAND support might be broken in this version!", ver);
-
- /* Power up the NAND chips */
- ret = gpio_request(BALLOON3_GPIO_RUN_NAND, "NAND");
- if (ret)
- goto err1;
-
- ret = gpio_direction_output(BALLOON3_GPIO_RUN_NAND, 1);
- if (ret)
- goto err2;
-
- gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1);
-
- /* Deassert all nCE lines and write protect line */
- __raw_writel(
- BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
- BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
- BALLOON3_NAND_CONTROL_FLWP,
- BALLOON3_NAND_CONTROL_REG + BALLOON3_FPGA_SETnCLR);
- return 0;
-
-err2:
- gpio_free(BALLOON3_GPIO_RUN_NAND);
-err1:
- return ret;
-}
-
-static void balloon3_nand_remove(struct platform_device *pdev)
-{
- /* Power down the NAND chips */
- gpio_set_value(BALLOON3_GPIO_RUN_NAND, 0);
- gpio_free(BALLOON3_GPIO_RUN_NAND);
-}
-
-static struct mtd_partition balloon3_partition_info[] = {
- [0] = {
- .name = "Boot",
- .offset = 0,
- .size = SZ_4M,
- },
- [1] = {
- .name = "RootFS",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL
- },
-};
-
-struct platform_nand_data balloon3_nand_pdata = {
- .chip = {
- .nr_chips = 4,
- .chip_offset = 0,
- .nr_partitions = ARRAY_SIZE(balloon3_partition_info),
- .partitions = balloon3_partition_info,
- .chip_delay = 50,
- },
- .ctrl = {
- .dev_ready = balloon3_nand_dev_ready,
- .select_chip = balloon3_nand_select_chip,
- .cmd_ctrl = balloon3_nand_cmd_ctl,
- .probe = balloon3_nand_probe,
- .remove = balloon3_nand_remove,
- },
-};
-
-static struct resource balloon3_nand_resource[] = {
- [0] = {
- .start = BALLOON3_NAND_BASE,
- .end = BALLOON3_NAND_BASE + 0x4,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device balloon3_nand = {
- .name = "gen_nand",
- .num_resources = ARRAY_SIZE(balloon3_nand_resource),
- .resource = balloon3_nand_resource,
- .id = -1,
- .dev = {
- .platform_data = &balloon3_nand_pdata,
- }
-};
-
-static void __init balloon3_nand_init(void)
-{
- platform_device_register(&balloon3_nand);
-}
-#else
-static inline void balloon3_nand_init(void) {}
-#endif
-
-/******************************************************************************
- * Core power regulator
- ******************************************************************************/
-#if defined(CONFIG_REGULATOR_MAX1586) || \
- defined(CONFIG_REGULATOR_MAX1586_MODULE)
-static struct regulator_consumer_supply balloon3_max1587a_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data balloon3_max1587a_v3_info = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 900000,
- .max_uV = 1705000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .consumer_supplies = balloon3_max1587a_consumers,
- .num_consumer_supplies = ARRAY_SIZE(balloon3_max1587a_consumers),
-};
-
-static struct max1586_subdev_data balloon3_max1587a_subdevs[] = {
- {
- .name = "vcc_core",
- .id = MAX1586_V3,
- .platform_data = &balloon3_max1587a_v3_info,
- }
-};
-
-static struct max1586_platform_data balloon3_max1587a_info = {
- .subdevs = balloon3_max1587a_subdevs,
- .num_subdevs = ARRAY_SIZE(balloon3_max1587a_subdevs),
- .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
-};
-
-static struct i2c_board_info __initdata balloon3_pi2c_board_info[] = {
- {
- I2C_BOARD_INFO("max1586", 0x14),
- .platform_data = &balloon3_max1587a_info,
- },
-};
-
-static void __init balloon3_pmic_init(void)
-{
- pxa27x_set_i2c_power_info(NULL);
- i2c_register_board_info(1, ARRAY_AND_SIZE(balloon3_pi2c_board_info));
-}
-#else
-static inline void balloon3_pmic_init(void) {}
-#endif
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void __init balloon3_init(void)
-{
- ARB_CNTRL = ARB_CORE_PARK | 0x234;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- balloon3_i2c_init();
- balloon3_irda_init();
- balloon3_lcd_init();
- balloon3_leds_init();
- balloon3_mmc_init();
- balloon3_nand_init();
- balloon3_nor_init();
- balloon3_pmic_init();
- balloon3_ts_init();
- balloon3_udc_init();
- balloon3_uhc_init();
- balloon3_cf_init();
-}
-
-static struct map_desc balloon3_io_desc[] __initdata = {
- { /* CPLD/FPGA */
- .virtual = (unsigned long)BALLOON3_FPGA_VIRT,
- .pfn = __phys_to_pfn(BALLOON3_FPGA_PHYS),
- .length = BALLOON3_FPGA_LENGTH,
- .type = MT_DEVICE,
- },
-};
-
-static void __init balloon3_map_io(void)
-{
- pxa27x_map_io();
- iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc));
-}
-
-MACHINE_START(BALLOON3, "Balloon3")
- /* Maintainer: Nick Bane. */
- .map_io = balloon3_map_io,
- .nr_irqs = BALLOON3_NR_IRQS,
- .init_irq = balloon3_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = balloon3_init,
- .atag_offset = 0x100,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
deleted file mode 100644
index 7712327f56a8..000000000000
--- a/arch/arm/mach-pxa/capc7117.c
+++ /dev/null
@@ -1,159 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/capc7117.c
- *
- * Support for the Embedian CAPC-7117 Evaluation Kit
- * based on the Embedian MXM-8x10 Computer on Module
- *
- * Copyright (C) 2009 Embedian Inc.
- * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd.
- *
- * 2007-09-04: eric miao <eric.y.miao@gmail.com>
- * rewrite to align with latest kernel
- *
- * 2010-01-09: Edwin Peer <epeer@tmtservices.co.za>
- * Hennie van der Merwe <hvdmerwe@tmtservices.co.za>
- * rework for upstream merge
- */
-
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/serial_8250.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa320.h"
-#include "mxm8x10.h"
-
-#include "generic.h"
-
-/* IDE (PATA) Support */
-static struct pata_platform_info pata_platform_data = {
- .ioport_shift = 1
-};
-
-static struct resource capc7117_ide_resources[] = {
- [0] = {
- .start = 0x11000020,
- .end = 0x1100003f,
- .flags = IORESOURCE_MEM
- },
- [1] = {
- .start = 0x1100001c,
- .end = 0x1100001c,
- .flags = IORESOURCE_MEM
- },
- [2] = {
- .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)),
- .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)),
- .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING
- }
-};
-
-static struct platform_device capc7117_ide_device = {
- .name = "pata_platform",
- .num_resources = ARRAY_SIZE(capc7117_ide_resources),
- .resource = capc7117_ide_resources,
- .dev = {
- .platform_data = &pata_platform_data,
- .coherent_dma_mask = ~0 /* grumble */
- }
-};
-
-static void __init capc7117_ide_init(void)
-{
- platform_device_register(&capc7117_ide_device);
-}
-
-/* TI16C752 UART support */
-#define TI16C752_FLAGS (UPF_BOOT_AUTOCONF | \
- UPF_IOREMAP | \
- UPF_BUGGY_UART | \
- UPF_SKIP_TEST)
-#define TI16C752_UARTCLK (22118400)
-static struct plat_serial8250_port ti16c752_platform_data[] = {
- [0] = {
- .mapbase = 0x14000000,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO78)),
- .irqflags = IRQF_TRIGGER_RISING,
- .flags = TI16C752_FLAGS,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = TI16C752_UARTCLK
- },
- [1] = {
- .mapbase = 0x14000040,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO79)),
- .irqflags = IRQF_TRIGGER_RISING,
- .flags = TI16C752_FLAGS,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = TI16C752_UARTCLK
- },
- [2] = {
- .mapbase = 0x14000080,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO80)),
- .irqflags = IRQF_TRIGGER_RISING,
- .flags = TI16C752_FLAGS,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = TI16C752_UARTCLK
- },
- [3] = {
- .mapbase = 0x140000c0,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO81)),
- .irqflags = IRQF_TRIGGER_RISING,
- .flags = TI16C752_FLAGS,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = TI16C752_UARTCLK
- },
- [4] = {
- /* end of array */
- }
-};
-
-static struct platform_device ti16c752_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = ti16c752_platform_data
- }
-};
-
-static void __init capc7117_uarts_init(void)
-{
- platform_device_register(&ti16c752_device);
-}
-
-static void __init capc7117_init(void)
-{
- /* Init CoM */
- mxm_8x10_barebones_init();
-
- /* Init evaluation board peripherals */
- mxm_8x10_ac97_init();
- mxm_8x10_usb_host_init();
- mxm_8x10_mmc_init();
-
- capc7117_uarts_init();
- capc7117_ide_init();
-
- regulator_has_full_constraints();
-}
-
-MACHINE_START(CAPC7117,
- "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = capc7117_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
deleted file mode 100644
index 2e35354b61f5..000000000000
--- a/arch/arm/mach-pxa/cm-x300.c
+++ /dev/null
@@ -1,881 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/cm-x300.c
- *
- * Support for the CompuLab CM-X300 modules
- *
- * Copyright (C) 2008,2009 CompuLab Ltd.
- *
- * Mike Rapoport <mike@compulab.co.il>
- * Igor Grinberg <grinberg@compulab.co.il>
- */
-#define pr_fmt(fmt) "%s: " fmt, __func__
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/dm9000.h>
-#include <linux/leds.h>
-#include <linux/platform_data/rtc-v3020.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-
-#include <linux/i2c.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <linux/mfd/da903x.h>
-#include <linux/regulator/machine.h>
-#include <linux/power_supply.h>
-#include <linux/apm-emulation.h>
-
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/spi/tdo24m.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-#include <asm/system_info.h>
-
-#include "pxa300.h"
-#include "pxa27x-udc.h"
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-#include <mach/audio.h>
-#include <linux/platform_data/usb-pxa3xx-ulpi.h>
-
-#include <asm/mach/map.h>
-
-#include "generic.h"
-#include "devices.h"
-
-#define CM_X300_ETH_PHYS 0x08000010
-
-#define GPIO82_MMC_IRQ (82)
-#define GPIO85_MMC_WP (85)
-
-#define CM_X300_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO82_MMC_IRQ)
-
-#define GPIO95_RTC_CS (95)
-#define GPIO96_RTC_WR (96)
-#define GPIO97_RTC_RD (97)
-#define GPIO98_RTC_IO (98)
-
-#define GPIO_ULPI_PHY_RST (127)
-
-static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
- /* LCD */
- GPIO54_LCD_LDD_0,
- GPIO55_LCD_LDD_1,
- GPIO56_LCD_LDD_2,
- GPIO57_LCD_LDD_3,
- GPIO58_LCD_LDD_4,
- GPIO59_LCD_LDD_5,
- GPIO60_LCD_LDD_6,
- GPIO61_LCD_LDD_7,
- GPIO62_LCD_LDD_8,
- GPIO63_LCD_LDD_9,
- GPIO64_LCD_LDD_10,
- GPIO65_LCD_LDD_11,
- GPIO66_LCD_LDD_12,
- GPIO67_LCD_LDD_13,
- GPIO68_LCD_LDD_14,
- GPIO69_LCD_LDD_15,
- GPIO72_LCD_FCLK,
- GPIO73_LCD_LCLK,
- GPIO74_LCD_PCLK,
- GPIO75_LCD_BIAS,
-
- /* BTUART */
- GPIO111_UART2_RTS,
- GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL,
- GPIO113_UART2_TXD,
- GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH,
-
- /* STUART */
- GPIO109_UART3_TXD,
- GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL,
-
- /* AC97 */
- GPIO23_AC97_nACRESET,
- GPIO24_AC97_SYSCLK,
- GPIO29_AC97_BITCLK,
- GPIO25_AC97_SDATA_IN_0,
- GPIO27_AC97_SDATA_OUT,
- GPIO28_AC97_SYNC,
-
- /* Keypad */
- GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
- GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
- GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
- GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
- GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
- GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
- GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
- GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
- GPIO121_KP_MKOUT_0,
- GPIO122_KP_MKOUT_1,
- GPIO123_KP_MKOUT_2,
- GPIO124_KP_MKOUT_3,
- GPIO125_KP_MKOUT_4,
- GPIO4_2_KP_MKOUT_5,
-
- /* MMC1 */
- GPIO3_MMC1_DAT0,
- GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
- GPIO5_MMC1_DAT2,
- GPIO6_MMC1_DAT3,
- GPIO7_MMC1_CLK,
- GPIO8_MMC1_CMD, /* CMD0 for slot 0 */
-
- /* MMC2 */
- GPIO9_MMC2_DAT0,
- GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
- GPIO11_MMC2_DAT2,
- GPIO12_MMC2_DAT3,
- GPIO13_MMC2_CLK,
- GPIO14_MMC2_CMD,
-
- /* FFUART */
- GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL,
- GPIO31_UART1_TXD,
- GPIO32_UART1_CTS,
- GPIO37_UART1_RTS,
- GPIO33_UART1_DCD,
- GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL,
- GPIO35_UART1_RI,
- GPIO36_UART1_DTR,
-
- /* GPIOs */
- GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */
- GPIO85_GPIO, /* MMC WP */
- GPIO99_GPIO, /* Ethernet IRQ */
-
- /* RTC GPIOs */
- GPIO95_GPIO | MFP_LPM_DRIVE_HIGH, /* RTC CS */
- GPIO96_GPIO | MFP_LPM_DRIVE_HIGH, /* RTC WR */
- GPIO97_GPIO | MFP_LPM_DRIVE_HIGH, /* RTC RD */
- GPIO98_GPIO, /* RTC IO */
-
- /* Standard I2C */
- GPIO21_I2C_SCL,
- GPIO22_I2C_SDA,
-
- /* PWM Backlight */
- GPIO19_PWM2_OUT,
-};
-
-static mfp_cfg_t cm_x3xx_rev_lt130_mfp_cfg[] __initdata = {
- /* GPIOs */
- GPIO79_GPIO, /* LED */
- GPIO77_GPIO, /* WiFi reset */
- GPIO78_GPIO, /* BT reset */
-};
-
-static mfp_cfg_t cm_x3xx_rev_ge130_mfp_cfg[] __initdata = {
- /* GPIOs */
- GPIO76_GPIO, /* LED */
- GPIO71_GPIO, /* WiFi reset */
- GPIO70_GPIO, /* BT reset */
-};
-
-static mfp_cfg_t cm_x310_mfp_cfg[] __initdata = {
- /* USB PORT 2 */
- ULPI_STP,
- ULPI_NXT,
- ULPI_DIR,
- GPIO30_ULPI_DATA_OUT_0,
- GPIO31_ULPI_DATA_OUT_1,
- GPIO32_ULPI_DATA_OUT_2,
- GPIO33_ULPI_DATA_OUT_3,
- GPIO34_ULPI_DATA_OUT_4,
- GPIO35_ULPI_DATA_OUT_5,
- GPIO36_ULPI_DATA_OUT_6,
- GPIO37_ULPI_DATA_OUT_7,
- GPIO38_ULPI_CLK,
- /* external PHY reset pin */
- GPIO127_GPIO,
-
- /* USB PORT 3 */
- GPIO77_USB_P3_1,
- GPIO78_USB_P3_2,
- GPIO79_USB_P3_3,
- GPIO80_USB_P3_4,
- GPIO81_USB_P3_5,
- GPIO82_USB_P3_6,
- GPIO0_2_USBH_PEN,
-};
-
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = CM_X300_ETH_PHYS,
- .end = CM_X300_ETH_PHYS + 0x3,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CM_X300_ETH_PHYS + 0x4,
- .end = CM_X300_ETH_PHYS + 0x4 + 500,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
- .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct dm9000_plat_data cm_x300_dm9000_platdata = {
- .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
- .dev = {
- .platform_data = &cm_x300_dm9000_platdata,
- }
-
-};
-
-static void __init cm_x300_init_dm9000(void)
-{
- platform_device_register(&dm9000_device);
-}
-#else
-static inline void cm_x300_init_dm9000(void) {}
-#endif
-
-/* LCD */
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info cm_x300_lcd_modes[] = {
- [0] = {
- .pixclock = 38250,
- .bpp = 16,
- .xres = 480,
- .yres = 640,
- .hsync_len = 8,
- .vsync_len = 2,
- .left_margin = 8,
- .upper_margin = 2,
- .right_margin = 24,
- .lower_margin = 4,
- .cmap_greyscale = 0,
- },
- [1] = {
- .pixclock = 153800,
- .bpp = 16,
- .xres = 240,
- .yres = 320,
- .hsync_len = 8,
- .vsync_len = 2,
- .left_margin = 8,
- .upper_margin = 2,
- .right_margin = 88,
- .lower_margin = 2,
- .cmap_greyscale = 0,
- },
-};
-
-static struct pxafb_mach_info cm_x300_lcd = {
- .modes = cm_x300_lcd_modes,
- .num_modes = ARRAY_SIZE(cm_x300_lcd_modes),
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static void __init cm_x300_init_lcd(void)
-{
- pxa_set_fb_info(NULL, &cm_x300_lcd);
-}
-#else
-static inline void cm_x300_init_lcd(void) {}
-#endif
-
-#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
-static struct pwm_lookup cm_x300_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 1, "pwm-backlight.0", NULL, 10000,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data cm_x300_backlight_data = {
- .max_brightness = 100,
- .dft_brightness = 100,
-};
-
-static struct platform_device cm_x300_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &cm_x300_backlight_data,
- },
-};
-
-static void cm_x300_init_bl(void)
-{
- pwm_add_table(cm_x300_pwm_lookup, ARRAY_SIZE(cm_x300_pwm_lookup));
- platform_device_register(&cm_x300_backlight_device);
-}
-#else
-static inline void cm_x300_init_bl(void) {}
-#endif
-
-#if defined(CONFIG_SPI_GPIO) || defined(CONFIG_SPI_GPIO_MODULE)
-#define GPIO_LCD_BASE (144)
-#define GPIO_LCD_DIN (GPIO_LCD_BASE + 8) /* aux_gpio3_0 */
-#define GPIO_LCD_DOUT (GPIO_LCD_BASE + 9) /* aux_gpio3_1 */
-#define GPIO_LCD_SCL (GPIO_LCD_BASE + 10) /* aux_gpio3_2 */
-#define GPIO_LCD_CS (GPIO_LCD_BASE + 11) /* aux_gpio3_3 */
-#define LCD_SPI_BUS_NUM (1)
-
-static struct spi_gpio_platform_data cm_x300_spi_gpio_pdata = {
- .num_chipselect = 1,
-};
-
-static struct platform_device cm_x300_spi_gpio = {
- .name = "spi_gpio",
- .id = LCD_SPI_BUS_NUM,
- .dev = {
- .platform_data = &cm_x300_spi_gpio_pdata,
- },
-};
-
-static struct gpiod_lookup_table cm_x300_spi_gpiod_table = {
- .dev_id = "spi_gpio",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_LCD_SCL,
- "sck", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DIN,
- "mosi", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DOUT,
- "miso", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_LCD_CS,
- "cs", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct tdo24m_platform_data cm_x300_tdo24m_pdata = {
- .model = TDO35S,
-};
-
-static struct spi_board_info cm_x300_spi_devices[] __initdata = {
- {
- .modalias = "tdo24m",
- .max_speed_hz = 1000000,
- .bus_num = LCD_SPI_BUS_NUM,
- .chip_select = 0,
- .platform_data = &cm_x300_tdo24m_pdata,
- },
-};
-
-static void __init cm_x300_init_spi(void)
-{
- spi_register_board_info(cm_x300_spi_devices,
- ARRAY_SIZE(cm_x300_spi_devices));
- gpiod_add_lookup_table(&cm_x300_spi_gpiod_table);
- platform_device_register(&cm_x300_spi_gpio);
-}
-#else
-static inline void cm_x300_init_spi(void) {}
-#endif
-
-#if defined(CONFIG_SND_PXA2XX_LIB_AC97)
-static void __init cm_x300_init_ac97(void)
-{
- pxa_set_ac97_info(NULL);
-}
-#else
-static inline void cm_x300_init_ac97(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
-static struct mtd_partition cm_x300_nand_partitions[] = {
- [0] = {
- .name = "OBM",
- .offset = 0,
- .size = SZ_256K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- [1] = {
- .name = "U-Boot",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_256K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- [2] = {
- .name = "Environment",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_256K,
- },
- [3] = {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_256K + SZ_1M,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- [4] = {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- },
- [5] = {
- .name = "fs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
- .keep_config = 1,
- .parts = cm_x300_nand_partitions,
- .nr_parts = ARRAY_SIZE(cm_x300_nand_partitions),
-};
-
-static void __init cm_x300_init_nand(void)
-{
- pxa3xx_set_nand_info(&cm_x300_nand_info);
-}
-#else
-static inline void cm_x300_init_nand(void) {}
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
-static struct pxamci_platform_data cm_x300_mci_platform_data = {
- .detect_delay_ms = 200,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table cm_x300_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on GPIO 82 */
- GPIO_LOOKUP("gpio-pxa", GPIO82_MMC_IRQ, "cd", GPIO_ACTIVE_LOW),
- /* Write protect on GPIO 85 */
- GPIO_LOOKUP("gpio-pxa", GPIO85_MMC_WP, "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/* The second MMC slot of CM-X300 is hardwired to Libertas card and has
- no detection/ro pins */
-static int cm_x300_mci2_init(struct device *dev,
- irq_handler_t cm_x300_detect_int,
- void *data)
-{
- return 0;
-}
-
-static void cm_x300_mci2_exit(struct device *dev, void *data)
-{
-}
-
-static struct pxamci_platform_data cm_x300_mci2_platform_data = {
- .detect_delay_ms = 200,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .init = cm_x300_mci2_init,
- .exit = cm_x300_mci2_exit,
-};
-
-static void __init cm_x300_init_mmc(void)
-{
- gpiod_add_lookup_table(&cm_x300_mci_gpio_table);
- pxa_set_mci_info(&cm_x300_mci_platform_data);
- pxa3xx_set_mci2_info(&cm_x300_mci2_platform_data);
-}
-#else
-static inline void cm_x300_init_mmc(void) {}
-#endif
-
-#if defined(CONFIG_PXA310_ULPI)
-static struct clk *pout_clk;
-
-static int cm_x300_ulpi_phy_reset(void)
-{
- int err;
-
- /* reset the PHY */
- err = gpio_request_one(GPIO_ULPI_PHY_RST, GPIOF_OUT_INIT_LOW,
- "ulpi reset");
- if (err) {
- pr_err("failed to request ULPI reset GPIO: %d\n", err);
- return err;
- }
-
- msleep(10);
- gpio_set_value(GPIO_ULPI_PHY_RST, 1);
- msleep(10);
-
- gpio_free(GPIO_ULPI_PHY_RST);
-
- return 0;
-}
-
-static int cm_x300_u2d_init(struct device *dev)
-{
- int err = 0;
-
- if (cpu_is_pxa310()) {
- /* CLK_POUT is connected to the ULPI PHY */
- pout_clk = clk_get(NULL, "CLK_POUT");
- if (IS_ERR(pout_clk)) {
- err = PTR_ERR(pout_clk);
- pr_err("failed to get CLK_POUT: %d\n", err);
- return err;
- }
- clk_prepare_enable(pout_clk);
-
- err = cm_x300_ulpi_phy_reset();
- if (err) {
- clk_disable(pout_clk);
- clk_put(pout_clk);
- }
- }
-
- return err;
-}
-
-static void cm_x300_u2d_exit(struct device *dev)
-{
- if (cpu_is_pxa310()) {
- clk_disable_unprepare(pout_clk);
- clk_put(pout_clk);
- }
-}
-
-static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = {
- .ulpi_mode = ULPI_SER_6PIN,
- .init = cm_x300_u2d_init,
- .exit = cm_x300_u2d_exit,
-};
-
-static void __init cm_x300_init_u2d(void)
-{
- pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
-}
-#else
-static inline void cm_x300_init_u2d(void) {}
-#endif
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static int cm_x300_ohci_init(struct device *dev)
-{
- if (cpu_is_pxa300())
- UP2OCR = UP2OCR_HXS
- | UP2OCR_HXOE | UP2OCR_DMPDE | UP2OCR_DPPDE;
-
- return 0;
-}
-
-static struct pxaohci_platform_data cm_x300_ohci_platform_data = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW,
- .init = cm_x300_ohci_init,
-};
-
-static void __init cm_x300_init_ohci(void)
-{
- pxa_set_ohci_info(&cm_x300_ohci_platform_data);
-}
-#else
-static inline void cm_x300_init_ohci(void) {}
-#endif
-
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-static struct gpio_led cm_x300_leds[] = {
- [0] = {
- .name = "cm-x300:green",
- .default_trigger = "heartbeat",
- .active_low = 1,
- },
-};
-
-static struct gpio_led_platform_data cm_x300_gpio_led_pdata = {
- .num_leds = ARRAY_SIZE(cm_x300_leds),
- .leds = cm_x300_leds,
-};
-
-static struct platform_device cm_x300_led_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &cm_x300_gpio_led_pdata,
- },
-};
-
-static void __init cm_x300_init_leds(void)
-{
- if (system_rev < 130)
- cm_x300_leds[0].gpio = 79;
- else
- cm_x300_leds[0].gpio = 76;
-
- platform_device_register(&cm_x300_led_device);
-}
-#else
-static inline void cm_x300_init_leds(void) {}
-#endif
-
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-/* PCA9555 */
-static struct pca953x_platform_data cm_x300_gpio_ext_pdata_0 = {
- .gpio_base = 128,
-};
-
-static struct pca953x_platform_data cm_x300_gpio_ext_pdata_1 = {
- .gpio_base = 144,
-};
-
-static struct i2c_board_info cm_x300_gpio_ext_info[] = {
- [0] = {
- I2C_BOARD_INFO("pca9555", 0x24),
- .platform_data = &cm_x300_gpio_ext_pdata_0,
- },
- [1] = {
- I2C_BOARD_INFO("pca9555", 0x25),
- .platform_data = &cm_x300_gpio_ext_pdata_1,
- },
-};
-
-static void __init cm_x300_init_i2c(void)
-{
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, cm_x300_gpio_ext_info,
- ARRAY_SIZE(cm_x300_gpio_ext_info));
-}
-#else
-static inline void cm_x300_init_i2c(void) {}
-#endif
-
-#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
-struct v3020_platform_data cm_x300_v3020_pdata = {
- .use_gpio = 1,
- .gpio_cs = GPIO95_RTC_CS,
- .gpio_wr = GPIO96_RTC_WR,
- .gpio_rd = GPIO97_RTC_RD,
- .gpio_io = GPIO98_RTC_IO,
-};
-
-static struct platform_device cm_x300_rtc_device = {
- .name = "v3020",
- .id = -1,
- .dev = {
- .platform_data = &cm_x300_v3020_pdata,
- }
-};
-
-static void __init cm_x300_init_rtc(void)
-{
- platform_device_register(&cm_x300_rtc_device);
-}
-#else
-static inline void cm_x300_init_rtc(void) {}
-#endif
-
-/* Battery */
-struct power_supply_info cm_x300_psy_info = {
- .name = "battery",
- .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
- .voltage_max_design = 4200000,
- .voltage_min_design = 3000000,
- .use_for_apm = 1,
-};
-
-static void cm_x300_battery_low(void)
-{
-#if defined(CONFIG_APM_EMULATION)
- apm_queue_event(APM_LOW_BATTERY);
-#endif
-}
-
-static void cm_x300_battery_critical(void)
-{
-#if defined(CONFIG_APM_EMULATION)
- apm_queue_event(APM_CRITICAL_SUSPEND);
-#endif
-}
-
-struct da9030_battery_info cm_x300_battery_info = {
- .battery_info = &cm_x300_psy_info,
-
- .charge_milliamp = 1000,
- .charge_millivolt = 4200,
-
- .vbat_low = 3600,
- .vbat_crit = 3400,
- .vbat_charge_start = 4100,
- .vbat_charge_stop = 4200,
- .vbat_charge_restart = 4000,
-
- .vcharge_min = 3200,
- .vcharge_max = 5500,
-
- .tbat_low = 197,
- .tbat_high = 78,
- .tbat_restart = 100,
-
- .batmon_interval = 0,
-
- .battery_low = cm_x300_battery_low,
- .battery_critical = cm_x300_battery_critical,
-};
-
-static struct regulator_consumer_supply buck2_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data buck2_data = {
- .constraints = {
- .min_uV = 1375000,
- .max_uV = 1375000,
- .state_mem = {
- .enabled = 0,
- },
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- .apply_uV = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(buck2_consumers),
- .consumer_supplies = buck2_consumers,
-};
-
-/* DA9030 */
-struct da903x_subdev_info cm_x300_da9030_subdevs[] = {
- {
- .name = "da903x-battery",
- .id = DA9030_ID_BAT,
- .platform_data = &cm_x300_battery_info,
- },
- {
- .name = "da903x-regulator",
- .id = DA9030_ID_BUCK2,
- .platform_data = &buck2_data,
- },
-};
-
-static struct da903x_platform_data cm_x300_da9030_info = {
- .num_subdevs = ARRAY_SIZE(cm_x300_da9030_subdevs),
- .subdevs = cm_x300_da9030_subdevs,
-};
-
-static struct i2c_board_info cm_x300_pmic_info = {
- I2C_BOARD_INFO("da9030", 0x49),
- .irq = IRQ_WAKEUP0,
- .platform_data = &cm_x300_da9030_info,
-};
-
-static struct i2c_pxa_platform_data cm_x300_pwr_i2c_info = {
- .use_pio = 1,
-};
-
-static void __init cm_x300_init_da9030(void)
-{
- pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
- i2c_register_board_info(1, &cm_x300_pmic_info, 1);
- irq_set_irq_wake(IRQ_WAKEUP0, 1);
-}
-
-/* wi2wi gpio setting for system_rev >= 130 */
-static struct gpio cm_x300_wi2wi_gpios[] __initdata = {
- { 71, GPIOF_OUT_INIT_HIGH, "wlan en" },
- { 70, GPIOF_OUT_INIT_HIGH, "bt reset" },
-};
-
-static void __init cm_x300_init_wi2wi(void)
-{
- int err;
-
- if (system_rev < 130) {
- cm_x300_wi2wi_gpios[0].gpio = 77; /* wlan en */
- cm_x300_wi2wi_gpios[1].gpio = 78; /* bt reset */
- }
-
- /* Libertas and CSR reset */
- err = gpio_request_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios));
- if (err) {
- pr_err("failed to request wifi/bt gpios: %d\n", err);
- return;
- }
-
- udelay(10);
- gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 0);
- udelay(10);
- gpio_set_value(cm_x300_wi2wi_gpios[1].gpio, 1);
-
- gpio_free_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios));
-}
-
-/* MFP */
-static void __init cm_x300_init_mfp(void)
-{
- /* board-processor specific GPIO initialization */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_mfp_cfg));
-
- if (system_rev < 130)
- pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_lt130_mfp_cfg));
- else
- pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_ge130_mfp_cfg));
-
- if (cpu_is_pxa310())
- pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x310_mfp_cfg));
-}
-
-static void __init cm_x300_init(void)
-{
- cm_x300_init_mfp();
-
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- if (cpu_is_pxa300())
- pxa_set_ffuart_info(NULL);
-
- cm_x300_init_da9030();
- cm_x300_init_dm9000();
- cm_x300_init_lcd();
- cm_x300_init_u2d();
- cm_x300_init_ohci();
- cm_x300_init_mmc();
- cm_x300_init_nand();
- cm_x300_init_leds();
- cm_x300_init_i2c();
- cm_x300_init_spi();
- cm_x300_init_rtc();
- cm_x300_init_ac97();
- cm_x300_init_wi2wi();
- cm_x300_init_bl();
-
- regulator_has_full_constraints();
-}
-
-static void __init cm_x300_fixup(struct tag *tags, char **cmdline)
-{
- /* Make sure that mi->bank[0].start = PHYS_ADDR */
- for (; tags->hdr.size; tags = tag_next(tags))
- if (tags->hdr.tag == ATAG_MEM &&
- tags->u.mem.start == 0x80000000) {
- tags->u.mem.start = 0xa0000000;
- break;
- }
-}
-
-MACHINE_START(CM_X300, "CM-X300 module")
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = cm_x300_init,
- .fixup = cm_x300_fixup,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c
deleted file mode 100644
index b9c173ede891..000000000000
--- a/arch/arm/mach-pxa/colibri-evalboard.c
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/colibri-evalboard.c
- *
- * Support for Toradex Colibri Evaluation Carrier Board
- * Daniel Mack <daniel@caiaq.de>
- * Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/gpio/machine.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/mach/arch.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <asm/io.h>
-
-#include "pxa27x.h"
-#include "colibri.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include "pxa27x-udc.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data colibri_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 200,
-};
-
-static struct gpiod_lookup_table colibri_pxa270_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO0_COLIBRI_PXA270_SD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpiod_lookup_table colibri_pxa300_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO13_COLIBRI_PXA300_SD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpiod_lookup_table colibri_pxa320_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO28_COLIBRI_PXA320_SD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init colibri_mmc_init(void)
-{
- if (machine_is_colibri()) /* PXA270 Colibri */
- gpiod_add_lookup_table(&colibri_pxa270_mci_gpio_table);
- if (machine_is_colibri300()) /* PXA300 Colibri */
- gpiod_add_lookup_table(&colibri_pxa300_mci_gpio_table);
- else /* PXA320 Colibri */
- gpiod_add_lookup_table(&colibri_pxa320_mci_gpio_table);
-
- pxa_set_mci_info(&colibri_mci_platform_data);
-}
-#else
-static inline void colibri_mmc_init(void) {}
-#endif
-
-/******************************************************************************
- * USB Host
- ******************************************************************************/
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static int colibri_ohci_init(struct device *dev)
-{
- UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
- return 0;
-}
-
-static struct pxaohci_platform_data colibri_ohci_info = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 |
- POWER_CONTROL_LOW | POWER_SENSE_LOW,
- .init = colibri_ohci_init,
-};
-
-static void __init colibri_uhc_init(void)
-{
- /* Colibri PXA270 has two usb ports, TBA for 320 */
- if (machine_is_colibri())
- colibri_ohci_info.flags |= ENABLE_PORT2;
-
- pxa_set_ohci_info(&colibri_ohci_info);
-}
-#else
-static inline void colibri_uhc_init(void) {}
-#endif
-
-/******************************************************************************
- * I2C RTC
- ******************************************************************************/
-#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
-static struct i2c_board_info __initdata colibri_i2c_devs[] = {
- {
- I2C_BOARD_INFO("m41t00", 0x68),
- },
-};
-
-static void __init colibri_rtc_init(void)
-{
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(colibri_i2c_devs));
-}
-#else
-static inline void colibri_rtc_init(void) {}
-#endif
-
-void __init colibri_evalboard_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- colibri_mmc_init();
- colibri_uhc_init();
- colibri_rtc_init();
-}
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
deleted file mode 100644
index e5879e8b0682..000000000000
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/income.c
- *
- * Support for Income s.r.o. SH-Dmaster PXA270 SBC
- *
- * Copyright (C) 2010
- * Marek Vasut <marek.vasut@gmail.com>
- * Pavel Revak <palo@bielyvlk.sk>
- */
-
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <mach/hardware.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include "pxa27x.h"
-#include "pxa27x-udc.h"
-#include <linux/platform_data/video-pxafb.h>
-
-#include "devices.h"
-#include "generic.h"
-
-#define GPIO114_INCOME_ETH_IRQ (114)
-#define GPIO0_INCOME_SD_DETECT (0)
-#define GPIO0_INCOME_SD_RO (1)
-#define GPIO54_INCOME_LED_A (54)
-#define GPIO55_INCOME_LED_B (55)
-#define GPIO113_INCOME_TS_IRQ (113)
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data income_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 200,
-};
-
-static struct gpiod_lookup_table income_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on GPIO 0 */
- GPIO_LOOKUP("gpio-pxa", GPIO0_INCOME_SD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- /* Write protect on GPIO 1 */
- GPIO_LOOKUP("gpio-pxa", GPIO0_INCOME_SD_RO,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init income_mmc_init(void)
-{
- gpiod_add_lookup_table(&income_mci_gpio_table);
- pxa_set_mci_info(&income_mci_platform_data);
-}
-#else
-static inline void income_mmc_init(void) {}
-#endif
-
-/******************************************************************************
- * USB Host
- ******************************************************************************/
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static struct pxaohci_platform_data income_ohci_info = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-static void __init income_uhc_init(void)
-{
- pxa_set_ohci_info(&income_ohci_info);
-}
-#else
-static inline void income_uhc_init(void) {}
-#endif
-
-/******************************************************************************
- * LED
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-struct gpio_led income_gpio_leds[] = {
- {
- .name = "income:green:leda",
- .default_trigger = "none",
- .gpio = GPIO54_INCOME_LED_A,
- .active_low = 1,
- },
- {
- .name = "income:green:ledb",
- .default_trigger = "none",
- .gpio = GPIO55_INCOME_LED_B,
- .active_low = 1,
- }
-};
-
-static struct gpio_led_platform_data income_gpio_led_info = {
- .leds = income_gpio_leds,
- .num_leds = ARRAY_SIZE(income_gpio_leds),
-};
-
-static struct platform_device income_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &income_gpio_led_info,
- }
-};
-
-static void __init income_led_init(void)
-{
- platform_device_register(&income_leds);
-}
-#else
-static inline void income_led_init(void) {}
-#endif
-
-/******************************************************************************
- * I2C
- ******************************************************************************/
-#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
-static struct i2c_board_info __initdata income_i2c_devs[] = {
- {
- I2C_BOARD_INFO("ds1340", 0x68),
- }, {
- I2C_BOARD_INFO("lm75", 0x4f),
- },
-};
-
-static void __init income_i2c_init(void)
-{
- pxa_set_i2c_info(NULL);
- pxa27x_set_i2c_power_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(income_i2c_devs));
-}
-#else
-static inline void income_i2c_init(void) {}
-#endif
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info income_lcd_modes[] = {
-{
- .pixclock = 144700,
- .xres = 320,
- .yres = 240,
- .bpp = 32,
- .depth = 18,
-
- .left_margin = 10,
- .right_margin = 10,
- .upper_margin = 7,
- .lower_margin = 8,
-
- .hsync_len = 20,
- .vsync_len = 2,
-
- .sync = FB_SYNC_VERT_HIGH_ACT,
-},
-};
-
-static struct pxafb_mach_info income_lcd_screen = {
- .modes = income_lcd_modes,
- .num_modes = ARRAY_SIZE(income_lcd_modes),
- .lcd_conn = LCD_COLOR_TFT_18BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static void __init income_lcd_init(void)
-{
- pxa_set_fb_info(NULL, &income_lcd_screen);
-}
-#else
-static inline void income_lcd_init(void) {}
-#endif
-
-/******************************************************************************
- * Backlight
- ******************************************************************************/
-#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
-static struct pwm_lookup income_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 1000000,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data income_backlight_data = {
- .max_brightness = 0x3ff,
- .dft_brightness = 0x1ff,
-};
-
-static struct platform_device income_backlight = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &income_backlight_data,
- },
-};
-
-static void __init income_pwm_init(void)
-{
- pwm_add_table(income_pwm_lookup, ARRAY_SIZE(income_pwm_lookup));
- platform_device_register(&income_backlight);
-}
-#else
-static inline void income_pwm_init(void) {}
-#endif
-
-void __init colibri_pxa270_income_boardinit(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- income_mmc_init();
- income_uhc_init();
- income_led_init();
- income_i2c_init();
- income_lcd_init();
- income_pwm_init();
-}
-
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
deleted file mode 100644
index 2f2cd2ae4187..000000000000
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ /dev/null
@@ -1,330 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/colibri-pxa270.c
- *
- * Support for Toradex PXA270 based Colibri module
- * Daniel Mack <daniel@caiaq.de>
- * Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/moduleparam.h>
-#include <linux/kernel.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/machine.h>
-#include <linux/ucb1400.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach-types.h>
-#include <linux/sizes.h>
-
-#include <mach/audio.h>
-#include "colibri.h"
-#include "pxa27x.h"
-
-#include "devices.h"
-#include "generic.h"
-
-/******************************************************************************
- * Evaluation board MFP
- ******************************************************************************/
-#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
-static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO0_GPIO, /* SD detect */
-
- /* FFUART */
- GPIO39_FFUART_TXD,
- GPIO34_FFUART_RXD,
-
- /* UHC */
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
- GPIO119_USBH2_PWR,
- GPIO120_USBH2_PEN,
-
- /* PCMCIA */
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO55_nPREG,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO49_nPWE,
- GPIO48_nPOE,
- GPIO57_nIOIS16,
- GPIO56_nPWAIT,
- GPIO104_PSKTSEL,
- GPIO53_GPIO, /* RESET */
- GPIO83_GPIO, /* BVD1 */
- GPIO82_GPIO, /* BVD2 */
- GPIO1_GPIO, /* READY */
- GPIO84_GPIO, /* DETECT */
- GPIO107_GPIO, /* PPEN */
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-};
-#else
-static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {};
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI_PXA270_INCOME
-static mfp_cfg_t income_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO0_GPIO, /* SD detect */
- GPIO1_GPIO, /* SD read-only */
-
- /* FFUART */
- GPIO39_FFUART_TXD,
- GPIO34_FFUART_RXD,
-
- /* BFUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO45_BTUART_RTS,
-
- /* STUART */
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* UHC */
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* PWM */
- GPIO16_PWM0_OUT,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* LED */
- GPIO54_GPIO, /* LED A */
- GPIO55_GPIO, /* LED B */
-};
-#else
-static mfp_cfg_t income_pin_config[] __initdata = {};
-#endif
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = {
- /* Ethernet */
- GPIO78_nCS_2, /* Ethernet CS */
- GPIO114_GPIO, /* Ethernet IRQ */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO95_AC97_nRESET,
- GPIO98_AC97_SYSCLK,
- GPIO113_GPIO, /* Touchscreen IRQ */
-};
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition colibri_partitions[] = {
- {
- .name = "Bootloader",
- .offset = 0x00000000,
- .size = 0x00040000,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- }, {
- .name = "Kernel",
- .offset = 0x00040000,
- .size = 0x00400000,
- .mask_flags = 0
- }, {
- .name = "Rootfs",
- .offset = 0x00440000,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data colibri_flash_data[] = {
- {
- .width = 4, /* bankwidth in bytes */
- .parts = colibri_partitions,
- .nr_parts = ARRAY_SIZE(colibri_partitions)
- }
-};
-
-static struct resource colibri_pxa270_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device colibri_pxa270_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = colibri_flash_data,
- },
- .resource = &colibri_pxa270_flash_resource,
- .num_resources = 1,
-};
-
-static void __init colibri_pxa270_nor_init(void)
-{
- platform_device_register(&colibri_pxa270_flash_device);
-}
-#else
-static inline void colibri_pxa270_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * Ethernet
- ******************************************************************************/
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
-static struct resource colibri_pxa270_dm9000_resources[] = {
- {
- .start = PXA_CS2_PHYS,
- .end = PXA_CS2_PHYS + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PXA_CS2_PHYS + 4,
- .end = PXA_CS2_PHYS + 4 + 500,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ),
- .end = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ),
- .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
- },
-};
-
-static struct platform_device colibri_pxa270_dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(colibri_pxa270_dm9000_resources),
- .resource = colibri_pxa270_dm9000_resources,
-};
-
-static void __init colibri_pxa270_eth_init(void)
-{
- platform_device_register(&colibri_pxa270_dm9000_device);
-}
-#else
-static inline void colibri_pxa270_eth_init(void) {}
-#endif
-
-/******************************************************************************
- * Audio and Touchscreen
- ******************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \
- defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
-static pxa2xx_audio_ops_t colibri_pxa270_ac97_pdata = {
- .reset_gpio = 95,
-};
-
-static struct ucb1400_pdata colibri_pxa270_ucb1400_pdata = {
- .irq = PXA_GPIO_TO_IRQ(GPIO113_COLIBRI_PXA270_TS_IRQ),
-};
-
-static struct platform_device colibri_pxa270_ucb1400_device = {
- .name = "ucb1400_core",
- .id = -1,
- .dev = {
- .platform_data = &colibri_pxa270_ucb1400_pdata,
- },
-};
-
-static void __init colibri_pxa270_tsc_init(void)
-{
- pxa_set_ac97_info(&colibri_pxa270_ac97_pdata);
- platform_device_register(&colibri_pxa270_ucb1400_device);
-}
-#else
-static inline void colibri_pxa270_tsc_init(void) {}
-#endif
-
-static int colibri_pxa270_baseboard;
-core_param(colibri_pxa270_baseboard, colibri_pxa270_baseboard, int, 0444);
-
-static void __init colibri_pxa270_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config));
-
- colibri_pxa270_nor_init();
- colibri_pxa270_eth_init();
- colibri_pxa270_tsc_init();
-
- switch (colibri_pxa270_baseboard) {
- case COLIBRI_EVALBOARD:
- pxa2xx_mfp_config(ARRAY_AND_SIZE(
- colibri_pxa270_evalboard_pin_config));
- colibri_evalboard_init();
- break;
- case COLIBRI_PXA270_INCOME:
- pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config));
- colibri_pxa270_income_boardinit();
- break;
- default:
- printk(KERN_ERR "Illegal colibri_pxa270_baseboard type %d\n",
- colibri_pxa270_baseboard);
- }
-
- regulator_has_full_constraints();
-}
-
-/* The "Income s.r.o. SH-Dmaster PXA270 SBC" board can be booted either
- * with the INCOME mach type or with COLIBRI and the kernel parameter
- * "colibri_pxa270_baseboard=1"
- */
-static void __init colibri_pxa270_income_init(void)
-{
- colibri_pxa270_baseboard = COLIBRI_PXA270_INCOME;
- colibri_pxa270_init();
-}
-
-MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
- .atag_offset = 0x100,
- .init_machine = colibri_pxa270_init,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-
-MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
- .atag_offset = 0x100,
- .init_machine = colibri_pxa270_income_init,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
deleted file mode 100644
index 82052dfd96b6..000000000000
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ /dev/null
@@ -1,192 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-pxa/colibri-pxa300.c
- *
- * Support for Toradex PXA300/310 based Colibri module
- *
- * Daniel Mack <daniel@caiaq.de>
- * Matthias Meier <matthias.j.meier@gmx.net>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-types.h>
-#include <linux/sizes.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-
-#include "pxa300.h"
-#include "colibri.h"
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <mach/audio.h>
-
-#include "generic.h"
-#include "devices.h"
-
-
-#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
-static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {
- /* MMC */
- GPIO7_MMC1_CLK,
- GPIO14_MMC1_CMD,
- GPIO3_MMC1_DAT0,
- GPIO4_MMC1_DAT1,
- GPIO5_MMC1_DAT2,
- GPIO6_MMC1_DAT3,
- GPIO13_GPIO, /* GPIO13_COLIBRI_PXA300_SD_DETECT */
-
- /* UHC */
- GPIO0_2_USBH_PEN,
- GPIO1_2_USBH_PWR,
- GPIO77_USB_P3_1,
- GPIO78_USB_P3_2,
- GPIO79_USB_P3_3,
- GPIO80_USB_P3_4,
- GPIO81_USB_P3_5,
- GPIO82_USB_P3_6,
-
- /* I2C */
- GPIO21_I2C_SCL,
- GPIO22_I2C_SDA,
-};
-#else
-static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {};
-#endif
-
-#if defined(CONFIG_AX88796)
-#define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO)
-/*
- * Asix AX88796 Ethernet
- */
-static struct ax_plat_data colibri_asix_platdata = {
- .flags = 0, /* defined later */
- .wordlength = 2,
-};
-
-static struct resource colibri_asix_resource[] = {
- [0] = {
- .start = PXA3xx_CS2_PHYS,
- .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
- .end = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
- .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
- }
-};
-
-static struct platform_device asix_device = {
- .name = "ax88796",
- .id = 0,
- .num_resources = ARRAY_SIZE(colibri_asix_resource),
- .resource = colibri_asix_resource,
- .dev = {
- .platform_data = &colibri_asix_platdata
- }
-};
-
-static mfp_cfg_t colibri_pxa300_eth_pin_config[] __initdata = {
- GPIO1_nCS2, /* AX88796 chip select */
- GPIO26_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */
-};
-
-static void __init colibri_pxa300_init_eth(void)
-{
- colibri_pxa3xx_init_eth(&colibri_asix_platdata);
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_eth_pin_config));
- platform_device_register(&asix_device);
-}
-#else
-static inline void __init colibri_pxa300_init_eth(void) {}
-#endif /* CONFIG_AX88796 */
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = {
- GPIO54_LCD_LDD_0,
- GPIO55_LCD_LDD_1,
- GPIO56_LCD_LDD_2,
- GPIO57_LCD_LDD_3,
- GPIO58_LCD_LDD_4,
- GPIO59_LCD_LDD_5,
- GPIO60_LCD_LDD_6,
- GPIO61_LCD_LDD_7,
- GPIO62_LCD_LDD_8,
- GPIO63_LCD_LDD_9,
- GPIO64_LCD_LDD_10,
- GPIO65_LCD_LDD_11,
- GPIO66_LCD_LDD_12,
- GPIO67_LCD_LDD_13,
- GPIO68_LCD_LDD_14,
- GPIO69_LCD_LDD_15,
- GPIO70_LCD_LDD_16,
- GPIO71_LCD_LDD_17,
- GPIO62_LCD_CS_N,
- GPIO72_LCD_FCLK,
- GPIO73_LCD_LCLK,
- GPIO74_LCD_PCLK,
- GPIO75_LCD_BIAS,
- GPIO76_LCD_VSYNC,
-};
-
-static void __init colibri_pxa300_init_lcd(void)
-{
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_lcd_pin_config));
-}
-
-#else
-static inline void colibri_pxa300_init_lcd(void) {}
-#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
-
-#if defined(CONFIG_SND_AC97_CODEC) || defined(CONFIG_SND_AC97_CODEC_MODULE)
-static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = {
- GPIO24_AC97_SYSCLK,
- GPIO23_AC97_nACRESET,
- GPIO25_AC97_SDATA_IN_0,
- GPIO27_AC97_SDATA_OUT,
- GPIO28_AC97_SYNC,
- GPIO29_AC97_BITCLK
-};
-
-static inline void __init colibri_pxa310_init_ac97(void)
-{
- /* no AC97 codec on Colibri PXA300 */
- if (!cpu_is_pxa310())
- return;
-
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa310_ac97_pin_config));
- pxa_set_ac97_info(NULL);
-}
-#else
-static inline void colibri_pxa310_init_ac97(void) {}
-#endif
-
-void __init colibri_pxa300_init(void)
-{
- colibri_pxa300_init_eth();
- colibri_pxa3xx_init_nand();
- colibri_pxa300_init_lcd();
- colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO));
- colibri_pxa310_init_ac97();
-
- /* Evalboard init */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_evalboard_pin_config));
- colibri_evalboard_init();
-}
-
-MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
- .atag_offset = 0x100,
- .init_machine = colibri_pxa300_init,
- .map_io = pxa3xx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
deleted file mode 100644
index 35dd3adb7712..000000000000
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ /dev/null
@@ -1,264 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-pxa/colibri-pxa320.c
- *
- * Support for Toradex PXA320/310 based Colibri module
- *
- * Daniel Mack <daniel@caiaq.de>
- * Matthias Meier <matthias.j.meier@gmx.net>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-types.h>
-#include <linux/sizes.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-
-#include "pxa320.h"
-#include "colibri.h"
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/audio.h>
-#include "pxa27x-udc.h"
-#include "udc.h"
-
-#include "generic.h"
-#include "devices.h"
-
-#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
-static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {
- /* MMC */
- GPIO22_MMC1_CLK,
- GPIO23_MMC1_CMD,
- GPIO18_MMC1_DAT0,
- GPIO19_MMC1_DAT1,
- GPIO20_MMC1_DAT2,
- GPIO21_MMC1_DAT3,
- GPIO28_GPIO, /* SD detect */
-
- /* UART 1 configuration (may be set by bootloader) */
- GPIO99_UART1_CTS,
- GPIO104_UART1_RTS,
- GPIO97_UART1_RXD,
- GPIO98_UART1_TXD,
- GPIO101_UART1_DTR,
- GPIO103_UART1_DSR,
- GPIO100_UART1_DCD,
- GPIO102_UART1_RI,
-
- /* UART 2 configuration */
- GPIO109_UART2_CTS,
- GPIO112_UART2_RTS,
- GPIO110_UART2_RXD,
- GPIO111_UART2_TXD,
-
- /* UART 3 configuration */
- GPIO30_UART3_RXD,
- GPIO31_UART3_TXD,
-
- /* UHC */
- GPIO2_2_USBH_PEN,
- GPIO3_2_USBH_PWR,
-
- /* I2C */
- GPIO32_I2C_SCL,
- GPIO33_I2C_SDA,
-
- /* PCMCIA */
- MFP_CFG(GPIO59, AF7), /* PRST ; AF7 to tristate */
- MFP_CFG(GPIO61, AF7), /* PCE1 ; AF7 to tristate */
- MFP_CFG(GPIO60, AF7), /* PCE2 ; AF7 to tristate */
- MFP_CFG(GPIO62, AF7), /* PCD ; AF7 to tristate */
- MFP_CFG(GPIO56, AF7), /* PSKTSEL ; AF7 to tristate */
- GPIO27_GPIO, /* RDnWR ; input/tristate */
- GPIO50_GPIO, /* PREG ; input/tristate */
- GPIO2_RDY,
- GPIO5_NPIOR,
- GPIO6_NPIOW,
- GPIO7_NPIOS16,
- GPIO8_NPWAIT,
- GPIO29_GPIO, /* PRDY (READY GPIO) */
- GPIO57_GPIO, /* PPEN (POWER GPIO) */
- GPIO81_GPIO, /* PCD (DETECT GPIO) */
- GPIO77_GPIO, /* PRST (RESET GPIO) */
- GPIO53_GPIO, /* PBVD1 */
- GPIO79_GPIO, /* PBVD2 */
- GPIO54_GPIO, /* POE */
-};
-#else
-static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {};
-#endif
-
-#if defined(CONFIG_AX88796)
-#define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO)
-/*
- * Asix AX88796 Ethernet
- */
-static struct ax_plat_data colibri_asix_platdata = {
- .flags = 0, /* defined later */
- .wordlength = 2,
-};
-
-static struct resource colibri_asix_resource[] = {
- [0] = {
- .start = PXA3xx_CS2_PHYS,
- .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
- .end = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
- .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
- }
-};
-
-static struct platform_device asix_device = {
- .name = "ax88796",
- .id = 0,
- .num_resources = ARRAY_SIZE(colibri_asix_resource),
- .resource = colibri_asix_resource,
- .dev = {
- .platform_data = &colibri_asix_platdata
- }
-};
-
-static mfp_cfg_t colibri_pxa320_eth_pin_config[] __initdata = {
- GPIO3_nCS2, /* AX88796 chip select */
- GPIO36_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */
-};
-
-static void __init colibri_pxa320_init_eth(void)
-{
- colibri_pxa3xx_init_eth(&colibri_asix_platdata);
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_eth_pin_config));
- platform_device_register(&asix_device);
-}
-#else
-static inline void __init colibri_pxa320_init_eth(void) {}
-#endif /* CONFIG_AX88796 */
-
-#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
-static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", MFP_PIN_GPIO96,
- "vbus", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device colibri_pxa320_gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-static void colibri_pxa320_udc_command(int cmd)
-{
- if (cmd == PXA2XX_UDC_CMD_CONNECT)
- UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
- else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
- UP2OCR = UP2OCR_HXOE;
-}
-
-static struct pxa2xx_udc_mach_info colibri_pxa320_udc_info __initdata = {
- .udc_command = colibri_pxa320_udc_command,
- .gpio_pullup = -1,
-};
-
-static void __init colibri_pxa320_init_udc(void)
-{
- pxa_set_udc_info(&colibri_pxa320_udc_info);
- gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
- platform_device_register(&colibri_pxa320_gpio_vbus);
-}
-#else
-static inline void colibri_pxa320_init_udc(void) {}
-#endif
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = {
- GPIO6_2_LCD_LDD_0,
- GPIO7_2_LCD_LDD_1,
- GPIO8_2_LCD_LDD_2,
- GPIO9_2_LCD_LDD_3,
- GPIO10_2_LCD_LDD_4,
- GPIO11_2_LCD_LDD_5,
- GPIO12_2_LCD_LDD_6,
- GPIO13_2_LCD_LDD_7,
- GPIO63_LCD_LDD_8,
- GPIO64_LCD_LDD_9,
- GPIO65_LCD_LDD_10,
- GPIO66_LCD_LDD_11,
- GPIO67_LCD_LDD_12,
- GPIO68_LCD_LDD_13,
- GPIO69_LCD_LDD_14,
- GPIO70_LCD_LDD_15,
- GPIO71_LCD_LDD_16,
- GPIO72_LCD_LDD_17,
- GPIO73_LCD_CS_N,
- GPIO74_LCD_VSYNC,
- GPIO14_2_LCD_FCLK,
- GPIO15_2_LCD_LCLK,
- GPIO16_2_LCD_PCLK,
- GPIO17_2_LCD_BIAS,
-};
-
-static void __init colibri_pxa320_init_lcd(void)
-{
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_lcd_pin_config));
-}
-#else
-static inline void colibri_pxa320_init_lcd(void) {}
-#endif
-
-#if defined(CONFIG_SND_AC97_CODEC) || \
- defined(CONFIG_SND_AC97_CODEC_MODULE)
-static mfp_cfg_t colibri_pxa320_ac97_pin_config[] __initdata = {
- GPIO34_AC97_SYSCLK,
- GPIO35_AC97_SDATA_IN_0,
- GPIO37_AC97_SDATA_OUT,
- GPIO38_AC97_SYNC,
- GPIO39_AC97_BITCLK,
- GPIO40_AC97_nACRESET
-};
-
-static inline void __init colibri_pxa320_init_ac97(void)
-{
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_ac97_pin_config));
- pxa_set_ac97_info(NULL);
-}
-#else
-static inline void colibri_pxa320_init_ac97(void) {}
-#endif
-
-void __init colibri_pxa320_init(void)
-{
- colibri_pxa320_init_eth();
- colibri_pxa3xx_init_nand();
- colibri_pxa320_init_lcd();
- colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO));
- colibri_pxa320_init_ac97();
- colibri_pxa320_init_udc();
-
- /* Evalboard init */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_evalboard_pin_config));
- colibri_evalboard_init();
-}
-
-MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
- .atag_offset = 0x100,
- .init_machine = colibri_pxa320_init,
- .map_io = pxa3xx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
deleted file mode 100644
index 3cead80a2b37..000000000000
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-pxa/colibri-pxa3xx.c
- *
- * Common functions for all Toradex PXA3xx modules
- *
- * Daniel Mack <daniel@caiaq.de>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/etherdevice.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <linux/sizes.h>
-#include <asm/system_info.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <mach/pxa3xx-regs.h>
-#include "mfp-pxa300.h"
-#include "colibri.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-
-#include "generic.h"
-#include "devices.h"
-
-#if defined(CONFIG_AX88796)
-#define ETHER_ADDR_LEN 6
-static u8 ether_mac_addr[ETHER_ADDR_LEN];
-
-void __init colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data)
-{
- int i;
- u64 serial = ((u64) system_serial_high << 32) | system_serial_low;
-
- /*
- * If the bootloader passed in a serial boot tag, which contains a
- * valid ethernet MAC, pass it to the interface. Toradex ships the
- * modules with their own bootloader which provides a valid MAC
- * this way.
- */
-
- for (i = 0; i < ETHER_ADDR_LEN; i++) {
- ether_mac_addr[i] = serial & 0xff;
- serial >>= 8;
- }
-
- if (is_valid_ether_addr(ether_mac_addr)) {
- plat_data->flags |= AXFLG_MAC_FROMPLATFORM;
- plat_data->mac_addr = ether_mac_addr;
- printk(KERN_INFO "%s(): taking MAC from serial boot tag\n",
- __func__);
- } else {
- plat_data->flags |= AXFLG_MAC_FROMDEV;
- printk(KERN_INFO "%s(): no valid serial boot tag found, "
- "taking MAC from device\n", __func__);
- }
-}
-#endif
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static int lcd_bl_pin;
-
-/*
- * LCD panel (Sharp LQ043T3DX02)
- */
-static void colibri_lcd_backlight(int on)
-{
- gpio_set_value(lcd_bl_pin, !!on);
-}
-
-static struct pxafb_mode_info sharp_lq43_mode = {
- .pixclock = 101936,
- .xres = 480,
- .yres = 272,
- .bpp = 32,
- .depth = 18,
- .hsync_len = 41,
- .left_margin = 2,
- .right_margin = 2,
- .vsync_len = 10,
- .upper_margin = 2,
- .lower_margin = 2,
- .sync = 0,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info sharp_lq43_info = {
- .modes = &sharp_lq43_mode,
- .num_modes = 1,
- .cmap_inverse = 0,
- .cmap_static = 0,
- .lcd_conn = LCD_COLOR_TFT_18BPP,
- .pxafb_backlight_power = colibri_lcd_backlight,
-};
-
-void __init colibri_pxa3xx_init_lcd(int bl_pin)
-{
- lcd_bl_pin = bl_pin;
- gpio_request(bl_pin, "lcd backlight");
- gpio_direction_output(bl_pin, 0);
- pxa_set_fb_info(NULL, &sharp_lq43_info);
-}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
-static struct mtd_partition colibri_nand_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_512K,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_4M,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_1M,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "fs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct pxa3xx_nand_platform_data colibri_nand_info = {
- .keep_config = 1,
- .parts = colibri_nand_partitions,
- .nr_parts = ARRAY_SIZE(colibri_nand_partitions),
-};
-
-void __init colibri_pxa3xx_init_nand(void)
-{
- pxa3xx_set_nand_info(&colibri_nand_info);
-}
-#endif
-
diff --git a/arch/arm/mach-pxa/colibri.h b/arch/arm/mach-pxa/colibri.h
deleted file mode 100644
index 85525d49e321..000000000000
--- a/arch/arm/mach-pxa/colibri.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _COLIBRI_H_
-#define _COLIBRI_H_
-
-#include <net/ax88796.h>
-#include <mach/mfp.h>
-
-/*
- * base board glue for PXA270 module
- */
-
-enum {
- COLIBRI_EVALBOARD = 0,
- COLIBRI_PXA270_INCOME,
-};
-
-#if defined(CONFIG_MACH_COLIBRI_EVALBOARD)
-extern void colibri_evalboard_init(void);
-#else
-static inline void colibri_evalboard_init(void) {}
-#endif
-
-#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME)
-extern void colibri_pxa270_income_boardinit(void);
-#else
-static inline void colibri_pxa270_income_boardinit(void) {}
-#endif
-
-/*
- * common settings for all modules
- */
-
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin);
-#else
-static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) {}
-#endif
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-extern void colibri_pxa3xx_init_lcd(int bl_pin);
-#else
-static inline void colibri_pxa3xx_init_lcd(int bl_pin) {}
-#endif
-
-#if defined(CONFIG_AX88796)
-extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data);
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
-extern void colibri_pxa3xx_init_nand(void);
-#else
-static inline void colibri_pxa3xx_init_nand(void) {}
-#endif
-
-/* physical memory regions */
-#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
-
-/* GPIO definitions for Colibri PXA270 */
-#define GPIO114_COLIBRI_PXA270_ETH_IRQ 114
-#define GPIO0_COLIBRI_PXA270_SD_DETECT 0
-#define GPIO113_COLIBRI_PXA270_TS_IRQ 113
-
-/* GPIO definitions for Colibri PXA300/310 */
-#define GPIO13_COLIBRI_PXA300_SD_DETECT 13
-
-/* GPIO definitions for Colibri PXA320 */
-#define GPIO28_COLIBRI_PXA320_SD_DETECT 28
-
-#endif /* _COLIBRI_H_ */
-
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
deleted file mode 100644
index 44659fbc37ba..000000000000
--- a/arch/arm/mach-pxa/corgi.c
+++ /dev/null
@@ -1,807 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for Sharp SL-C7xx PDAs
- * Models: SL-C700 (Corgi), SL-C750 (Shepherd), SL-C760 (Husky)
- *
- * Copyright (c) 2004-2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches/lubbock.c
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h> /* symbol_get ; symbol_put */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/major.h>
-#include <linux/fs.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/mmc/host.h>
-#include <linux/mtd/physmap.h>
-#include <linux/pm.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/backlight.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/io.h>
-#include <linux/regulator/machine.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/spi/corgi_lcd.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/mtd/sharpsl.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/gpio_keys.h>
-#include <linux/memblock.h>
-#include <video/w100fb.h>
-
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include "pxa25x.h"
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include "udc.h"
-#include <mach/corgi.h>
-#include "sharpsl_pm.h"
-
-#include <asm/mach/sharpsl_param.h>
-#include <asm/hardware/scoop.h>
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned long corgi_pin_config[] __initdata = {
- /* Static Memory I/O */
- GPIO78_nCS_2, /* w100fb */
- GPIO80_nCS_4, /* scoop */
-
- /* SSP1 */
- GPIO23_SSP1_SCLK,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
- GPIO24_GPIO, /* CORGI_GPIO_ADS7846_CS - SFRM as chip select */
-
- /* I2S */
- GPIO28_I2S_BITCLK_OUT,
- GPIO29_I2S_SDATA_IN,
- GPIO30_I2S_SDATA_OUT,
- GPIO31_I2S_SYNC,
- GPIO32_I2S_SYSCLK,
-
- /* Infra-Red */
- GPIO47_FICP_TXD,
- GPIO46_FICP_RXD,
-
- /* FFUART */
- GPIO40_FFUART_DTR,
- GPIO41_FFUART_RTS,
- GPIO39_FFUART_TXD,
- GPIO37_FFUART_DSR,
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
-
- /* PC Card */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO8_MMC_CS0,
-
- /* GPIO Matrix Keypad */
- GPIO66_GPIO | MFP_LPM_DRIVE_HIGH, /* column 0 */
- GPIO67_GPIO | MFP_LPM_DRIVE_HIGH, /* column 1 */
- GPIO68_GPIO | MFP_LPM_DRIVE_HIGH, /* column 2 */
- GPIO69_GPIO | MFP_LPM_DRIVE_HIGH, /* column 3 */
- GPIO70_GPIO | MFP_LPM_DRIVE_HIGH, /* column 4 */
- GPIO71_GPIO | MFP_LPM_DRIVE_HIGH, /* column 5 */
- GPIO72_GPIO | MFP_LPM_DRIVE_HIGH, /* column 6 */
- GPIO73_GPIO | MFP_LPM_DRIVE_HIGH, /* column 7 */
- GPIO74_GPIO | MFP_LPM_DRIVE_HIGH, /* column 8 */
- GPIO75_GPIO | MFP_LPM_DRIVE_HIGH, /* column 9 */
- GPIO76_GPIO | MFP_LPM_DRIVE_HIGH, /* column 10 */
- GPIO77_GPIO | MFP_LPM_DRIVE_HIGH, /* column 11 */
- GPIO58_GPIO, /* row 0 */
- GPIO59_GPIO, /* row 1 */
- GPIO60_GPIO, /* row 2 */
- GPIO61_GPIO, /* row 3 */
- GPIO62_GPIO, /* row 4 */
- GPIO63_GPIO, /* row 5 */
- GPIO64_GPIO, /* row 6 */
- GPIO65_GPIO, /* row 7 */
-
- /* GPIO */
- GPIO9_GPIO, /* CORGI_GPIO_nSD_DETECT */
- GPIO7_GPIO, /* CORGI_GPIO_nSD_WP */
- GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_MAIN_BAT_{LOW,COVER} */
- GPIO13_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_LED_ORANGE */
- GPIO21_GPIO, /* CORGI_GPIO_ADC_TEMP */
- GPIO22_GPIO, /* CORGI_GPIO_IR_ON */
- GPIO33_GPIO, /* CORGI_GPIO_SD_PWR */
- GPIO38_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_CHRG_ON */
- GPIO43_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_CHRG_UKN */
- GPIO44_GPIO, /* CORGI_GPIO_HSYNC */
-
- GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_KEY_INT */
- GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* CORGI_GPIO_AC_IN */
- GPIO3_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_WAKEUP */
-};
-
-/*
- * Corgi SCOOP Device
- */
-static struct resource corgi_scoop_resources[] = {
- [0] = {
- .start = 0x10800000,
- .end = 0x10800fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct scoop_config corgi_scoop_setup = {
- .io_dir = CORGI_SCOOP_IO_DIR,
- .io_out = CORGI_SCOOP_IO_OUT,
- .gpio_base = CORGI_SCOOP_GPIO_BASE,
-};
-
-struct platform_device corgiscoop_device = {
- .name = "sharp-scoop",
- .id = -1,
- .dev = {
- .platform_data = &corgi_scoop_setup,
- },
- .num_resources = ARRAY_SIZE(corgi_scoop_resources),
- .resource = corgi_scoop_resources,
-};
-
-static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = {
-{
- .dev = &corgiscoop_device.dev,
- .irq = CORGI_IRQ_GPIO_CF_IRQ,
- .cd_irq = CORGI_IRQ_GPIO_CF_CD,
- .cd_irq_str = "PCMCIA0 CD",
-},
-};
-
-static struct scoop_pcmcia_config corgi_pcmcia_config = {
- .devs = &corgi_pcmcia_scoop[0],
- .num_devs = 1,
-};
-
-static struct w100_mem_info corgi_fb_mem = {
- .ext_cntl = 0x00040003,
- .sdram_mode_reg = 0x00650021,
- .ext_timing_cntl = 0x10002a4a,
- .io_cntl = 0x7ff87012,
- .size = 0x1fffff,
-};
-
-static struct w100_gen_regs corgi_fb_regs = {
- .lcd_format = 0x00000003,
- .lcdd_cntl1 = 0x01CC0000,
- .lcdd_cntl2 = 0x0003FFFF,
- .genlcd_cntl1 = 0x00FFFF0D,
- .genlcd_cntl2 = 0x003F3003,
- .genlcd_cntl3 = 0x000102aa,
-};
-
-static struct w100_gpio_regs corgi_fb_gpio = {
- .init_data1 = 0x000000bf,
- .init_data2 = 0x00000000,
- .gpio_dir1 = 0x00000000,
- .gpio_oe1 = 0x03c0feff,
- .gpio_dir2 = 0x00000000,
- .gpio_oe2 = 0x00000000,
-};
-
-static struct w100_mode corgi_fb_modes[] = {
-{
- .xres = 480,
- .yres = 640,
- .left_margin = 0x56,
- .right_margin = 0x55,
- .upper_margin = 0x03,
- .lower_margin = 0x00,
- .crtc_ss = 0x82360056,
- .crtc_ls = 0xA0280000,
- .crtc_gs = 0x80280028,
- .crtc_vpos_gs = 0x02830002,
- .crtc_rev = 0x00400008,
- .crtc_dclk = 0xA0000000,
- .crtc_gclk = 0x8015010F,
- .crtc_goe = 0x80100110,
- .crtc_ps1_active = 0x41060010,
- .pll_freq = 75,
- .fast_pll_freq = 100,
- .sysclk_src = CLK_SRC_PLL,
- .sysclk_divider = 0,
- .pixclk_src = CLK_SRC_PLL,
- .pixclk_divider = 2,
- .pixclk_divider_rotated = 6,
-},{
- .xres = 240,
- .yres = 320,
- .left_margin = 0x27,
- .right_margin = 0x2e,
- .upper_margin = 0x01,
- .lower_margin = 0x00,
- .crtc_ss = 0x81170027,
- .crtc_ls = 0xA0140000,
- .crtc_gs = 0xC0140014,
- .crtc_vpos_gs = 0x00010141,
- .crtc_rev = 0x00400008,
- .crtc_dclk = 0xA0000000,
- .crtc_gclk = 0x8015010F,
- .crtc_goe = 0x80100110,
- .crtc_ps1_active = 0x41060010,
- .pll_freq = 0,
- .fast_pll_freq = 0,
- .sysclk_src = CLK_SRC_XTAL,
- .sysclk_divider = 0,
- .pixclk_src = CLK_SRC_XTAL,
- .pixclk_divider = 1,
- .pixclk_divider_rotated = 1,
-},
-
-};
-
-static struct w100fb_mach_info corgi_fb_info = {
- .init_mode = INIT_MODE_ROTATED,
- .mem = &corgi_fb_mem,
- .regs = &corgi_fb_regs,
- .modelist = &corgi_fb_modes[0],
- .num_modes = 2,
- .gpio = &corgi_fb_gpio,
- .xtal_freq = 12500000,
- .xtal_dbl = 0,
-};
-
-static struct resource corgi_fb_resources[] = {
- [0] = {
- .start = 0x08000000,
- .end = 0x08ffffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device corgifb_device = {
- .name = "w100fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(corgi_fb_resources),
- .resource = corgi_fb_resources,
- .dev = {
- .platform_data = &corgi_fb_info,
- },
-
-};
-
-/*
- * Corgi Keyboard Device
- */
-#define CORGI_KEY_CALENDER KEY_F1
-#define CORGI_KEY_ADDRESS KEY_F2
-#define CORGI_KEY_FN KEY_F3
-#define CORGI_KEY_CANCEL KEY_F4
-#define CORGI_KEY_OFF KEY_SUSPEND
-#define CORGI_KEY_EXOK KEY_F5
-#define CORGI_KEY_EXCANCEL KEY_F6
-#define CORGI_KEY_EXJOGDOWN KEY_F7
-#define CORGI_KEY_EXJOGUP KEY_F8
-#define CORGI_KEY_JAP1 KEY_LEFTCTRL
-#define CORGI_KEY_JAP2 KEY_LEFTALT
-#define CORGI_KEY_MAIL KEY_F10
-#define CORGI_KEY_OK KEY_F11
-#define CORGI_KEY_MENU KEY_F12
-
-static const uint32_t corgikbd_keymap[] = {
- KEY(0, 1, KEY_1),
- KEY(0, 2, KEY_3),
- KEY(0, 3, KEY_5),
- KEY(0, 4, KEY_6),
- KEY(0, 5, KEY_7),
- KEY(0, 6, KEY_9),
- KEY(0, 7, KEY_0),
- KEY(0, 8, KEY_BACKSPACE),
- KEY(1, 1, KEY_2),
- KEY(1, 2, KEY_4),
- KEY(1, 3, KEY_R),
- KEY(1, 4, KEY_Y),
- KEY(1, 5, KEY_8),
- KEY(1, 6, KEY_I),
- KEY(1, 7, KEY_O),
- KEY(1, 8, KEY_P),
- KEY(2, 0, KEY_TAB),
- KEY(2, 1, KEY_Q),
- KEY(2, 2, KEY_E),
- KEY(2, 3, KEY_T),
- KEY(2, 4, KEY_G),
- KEY(2, 5, KEY_U),
- KEY(2, 6, KEY_J),
- KEY(2, 7, KEY_K),
- KEY(3, 0, CORGI_KEY_CALENDER),
- KEY(3, 1, KEY_W),
- KEY(3, 2, KEY_S),
- KEY(3, 3, KEY_F),
- KEY(3, 4, KEY_V),
- KEY(3, 5, KEY_H),
- KEY(3, 6, KEY_M),
- KEY(3, 7, KEY_L),
- KEY(3, 9, KEY_RIGHTSHIFT),
- KEY(4, 0, CORGI_KEY_ADDRESS),
- KEY(4, 1, KEY_A),
- KEY(4, 2, KEY_D),
- KEY(4, 3, KEY_C),
- KEY(4, 4, KEY_B),
- KEY(4, 5, KEY_N),
- KEY(4, 6, KEY_DOT),
- KEY(4, 8, KEY_ENTER),
- KEY(4, 10, KEY_LEFTSHIFT),
- KEY(5, 0, CORGI_KEY_MAIL),
- KEY(5, 1, KEY_Z),
- KEY(5, 2, KEY_X),
- KEY(5, 3, KEY_MINUS),
- KEY(5, 4, KEY_SPACE),
- KEY(5, 5, KEY_COMMA),
- KEY(5, 7, KEY_UP),
- KEY(5, 11, CORGI_KEY_FN),
- KEY(6, 0, KEY_SYSRQ),
- KEY(6, 1, CORGI_KEY_JAP1),
- KEY(6, 2, CORGI_KEY_JAP2),
- KEY(6, 3, CORGI_KEY_CANCEL),
- KEY(6, 4, CORGI_KEY_OK),
- KEY(6, 5, CORGI_KEY_MENU),
- KEY(6, 6, KEY_LEFT),
- KEY(6, 7, KEY_DOWN),
- KEY(6, 8, KEY_RIGHT),
- KEY(7, 0, CORGI_KEY_OFF),
- KEY(7, 1, CORGI_KEY_EXOK),
- KEY(7, 2, CORGI_KEY_EXCANCEL),
- KEY(7, 3, CORGI_KEY_EXJOGDOWN),
- KEY(7, 4, CORGI_KEY_EXJOGUP),
-};
-
-static struct matrix_keymap_data corgikbd_keymap_data = {
- .keymap = corgikbd_keymap,
- .keymap_size = ARRAY_SIZE(corgikbd_keymap),
-};
-
-static const int corgikbd_row_gpios[] =
- { 58, 59, 60, 61, 62, 63, 64, 65 };
-static const int corgikbd_col_gpios[] =
- { 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77 };
-
-static struct matrix_keypad_platform_data corgikbd_pdata = {
- .keymap_data = &corgikbd_keymap_data,
- .row_gpios = corgikbd_row_gpios,
- .col_gpios = corgikbd_col_gpios,
- .num_row_gpios = ARRAY_SIZE(corgikbd_row_gpios),
- .num_col_gpios = ARRAY_SIZE(corgikbd_col_gpios),
- .col_scan_delay_us = 10,
- .debounce_ms = 10,
- .wakeup = 1,
-};
-
-static struct platform_device corgikbd_device = {
- .name = "matrix-keypad",
- .id = -1,
- .dev = {
- .platform_data = &corgikbd_pdata,
- },
-};
-
-static struct gpio_keys_button corgi_gpio_keys[] = {
- {
- .type = EV_SW,
- .code = SW_LID,
- .gpio = CORGI_GPIO_SWA,
- .desc = "Lid close switch",
- .debounce_interval = 500,
- },
- {
- .type = EV_SW,
- .code = SW_TABLET_MODE,
- .gpio = CORGI_GPIO_SWB,
- .desc = "Tablet mode switch",
- .debounce_interval = 500,
- },
- {
- .type = EV_SW,
- .code = SW_HEADPHONE_INSERT,
- .gpio = CORGI_GPIO_AK_INT,
- .desc = "HeadPhone insert",
- .debounce_interval = 500,
- },
-};
-
-static struct gpio_keys_platform_data corgi_gpio_keys_platform_data = {
- .buttons = corgi_gpio_keys,
- .nbuttons = ARRAY_SIZE(corgi_gpio_keys),
- .poll_interval = 250,
-};
-
-static struct platform_device corgi_gpio_keys_device = {
- .name = "gpio-keys-polled",
- .id = -1,
- .dev = {
- .platform_data = &corgi_gpio_keys_platform_data,
- },
-};
-
-/*
- * Corgi LEDs
- */
-static struct gpio_led corgi_gpio_leds[] = {
- {
- .name = "corgi:amber:charge",
- .default_trigger = "sharpsl-charge",
- .gpio = CORGI_GPIO_LED_ORANGE,
- },
- {
- .name = "corgi:green:mail",
- .default_trigger = "nand-disk",
- .gpio = CORGI_GPIO_LED_GREEN,
- },
-};
-
-static struct gpio_led_platform_data corgi_gpio_leds_info = {
- .leds = corgi_gpio_leds,
- .num_leds = ARRAY_SIZE(corgi_gpio_leds),
-};
-
-static struct platform_device corgiled_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &corgi_gpio_leds_info,
- },
-};
-
-/*
- * Corgi Audio
- */
-static struct platform_device corgi_audio_device = {
- .name = "corgi-audio",
- .id = -1,
-};
-
-/*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
- */
-static struct pxamci_platform_data corgi_mci_platform_data = {
- .detect_delay_ms = 250,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table corgi_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on GPIO 9 */
- GPIO_LOOKUP("gpio-pxa", CORGI_GPIO_nSD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- /* Write protect on GPIO 7 */
- GPIO_LOOKUP("gpio-pxa", CORGI_GPIO_nSD_WP,
- "wp", GPIO_ACTIVE_LOW),
- /* Power on GPIO 33 */
- GPIO_LOOKUP("gpio-pxa", CORGI_GPIO_SD_PWR,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/*
- * Irda
- */
-static struct pxaficp_platform_data corgi_ficp_platform_data = {
- .gpio_pwdown = CORGI_GPIO_IR_ON,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-
-/*
- * USB Device Controller
- */
-static struct pxa2xx_udc_mach_info udc_info __initdata = {
- /* no connect GPIO; corgi can't tell connection status */
- .gpio_pullup = CORGI_GPIO_USB_PULLUP,
-};
-
-#if IS_ENABLED(CONFIG_SPI_PXA2XX)
-static struct pxa2xx_spi_controller corgi_spi_info = {
- .num_chipselect = 3,
-};
-
-static struct gpiod_lookup_table corgi_spi_gpio_table = {
- .dev_id = "pxa2xx-spi.1",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", CORGI_GPIO_ADS7846_CS, "cs", 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("gpio-pxa", CORGI_GPIO_LCDCON_CS, "cs", 1, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("gpio-pxa", CORGI_GPIO_MAX1111_CS, "cs", 2, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void corgi_wait_for_hsync(void)
-{
- while (gpio_get_value(CORGI_GPIO_HSYNC))
- cpu_relax();
-
- while (!gpio_get_value(CORGI_GPIO_HSYNC))
- cpu_relax();
-}
-
-static struct ads7846_platform_data corgi_ads7846_info = {
- .model = 7846,
- .vref_delay_usecs = 100,
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .gpio_pendown = CORGI_GPIO_TP_INT,
- .wait_for_sync = corgi_wait_for_hsync,
-};
-
-static void corgi_bl_kick_battery(void)
-{
- void (*kick_batt)(void);
-
- kick_batt = symbol_get(sharpsl_battery_kick);
- if (kick_batt) {
- kick_batt();
- symbol_put(sharpsl_battery_kick);
- }
-}
-
-static struct gpiod_lookup_table corgi_lcdcon_gpio_table = {
- .dev_id = "spi1.1",
- .table = {
- GPIO_LOOKUP("gpio-pxa", CORGI_GPIO_BACKLIGHT_CONT,
- "BL_CONT", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct corgi_lcd_platform_data corgi_lcdcon_info = {
- .init_mode = CORGI_LCD_MODE_VGA,
- .max_intensity = 0x2f,
- .default_intensity = 0x1f,
- .limit_mask = 0x0b,
- .kick_battery = corgi_bl_kick_battery,
-};
-
-static struct spi_board_info corgi_spi_devices[] = {
- {
- .modalias = "ads7846",
- .max_speed_hz = 1200000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = &corgi_ads7846_info,
- .irq = PXA_GPIO_TO_IRQ(CORGI_GPIO_TP_INT),
- }, {
- .modalias = "corgi-lcd",
- .max_speed_hz = 50000,
- .bus_num = 1,
- .chip_select = 1,
- .platform_data = &corgi_lcdcon_info,
- }, {
- .modalias = "max1111",
- .max_speed_hz = 450000,
- .bus_num = 1,
- .chip_select = 2,
- },
-};
-
-static void __init corgi_init_spi(void)
-{
- gpiod_add_lookup_table(&corgi_spi_gpio_table);
- pxa2xx_set_spi_info(1, &corgi_spi_info);
- gpiod_add_lookup_table(&corgi_lcdcon_gpio_table);
- spi_register_board_info(ARRAY_AND_SIZE(corgi_spi_devices));
-}
-#else
-static inline void corgi_init_spi(void) {}
-#endif
-
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr sharpsl_bbt = {
- .options = 0,
- .offs = 4,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-static const char * const probes[] = {
- "cmdlinepart",
- "ofpart",
- "sharpslpart",
- NULL,
-};
-
-static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
- .badblock_pattern = &sharpsl_bbt,
- .part_parsers = probes,
-};
-
-static struct resource sharpsl_nand_resources[] = {
- {
- .start = 0x0C000000,
- .end = 0x0C000FFF,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device sharpsl_nand_device = {
- .name = "sharpsl-nand",
- .id = -1,
- .resource = sharpsl_nand_resources,
- .num_resources = ARRAY_SIZE(sharpsl_nand_resources),
- .dev.platform_data = &sharpsl_nand_platform_data,
-};
-
-static struct mtd_partition sharpsl_rom_parts[] = {
- {
- .name ="Boot PROM Filesystem",
- .offset = 0x00120000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data sharpsl_rom_data = {
- .width = 2,
- .nr_parts = ARRAY_SIZE(sharpsl_rom_parts),
- .parts = sharpsl_rom_parts,
-};
-
-static struct resource sharpsl_rom_resources[] = {
- {
- .start = 0x00000000,
- .end = 0x007fffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device sharpsl_rom_device = {
- .name = "physmap-flash",
- .id = -1,
- .resource = sharpsl_rom_resources,
- .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
- .dev.platform_data = &sharpsl_rom_data,
-};
-
-static struct platform_device *devices[] __initdata = {
- &corgiscoop_device,
- &corgifb_device,
- &corgi_gpio_keys_device,
- &corgikbd_device,
- &corgiled_device,
- &corgi_audio_device,
- &sharpsl_nand_device,
- &sharpsl_rom_device,
-};
-
-static struct i2c_board_info __initdata corgi_i2c_devices[] = {
- { I2C_BOARD_INFO("wm8731", 0x1b) },
-};
-
-static void corgi_poweroff(void)
-{
- if (!machine_is_corgi())
- /* Green LED off tells the bootloader to halt */
- gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
-
- pxa_restart(REBOOT_HARD, NULL);
-}
-
-static void corgi_restart(enum reboot_mode mode, const char *cmd)
-{
- if (!machine_is_corgi())
- /* Green LED on tells the bootloader to reboot */
- gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
-
- pxa_restart(REBOOT_HARD, cmd);
-}
-
-static void __init corgi_init(void)
-{
- pm_power_off = corgi_poweroff;
-
- /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
- PCFR |= PCFR_OPDE;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config));
-
- /* allow wakeup from various GPIOs */
- gpio_set_wake(CORGI_GPIO_KEY_INT, 1);
- gpio_set_wake(CORGI_GPIO_WAKEUP, 1);
- gpio_set_wake(CORGI_GPIO_AC_IN, 1);
- gpio_set_wake(CORGI_GPIO_CHRG_FULL, 1);
-
- if (!machine_is_corgi())
- gpio_set_wake(CORGI_GPIO_MAIN_BAT_LOW, 1);
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- corgi_init_spi();
-
- pxa_set_udc_info(&udc_info);
- gpiod_add_lookup_table(&corgi_mci_gpio_table);
- pxa_set_mci_info(&corgi_mci_platform_data);
- pxa_set_ficp_info(&corgi_ficp_platform_data);
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(corgi_i2c_devices));
-
- platform_scoop_config = &corgi_pcmcia_config;
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- regulator_has_full_constraints();
-}
-
-static void __init fixup_corgi(struct tag *tags, char **cmdline)
-{
- sharpsl_save_param();
- if (machine_is_corgi())
- memblock_add(0xa0000000, SZ_32M);
- else
- memblock_add(0xa0000000, SZ_64M);
-}
-
-#ifdef CONFIG_MACH_CORGI
-MACHINE_START(CORGI, "SHARP Corgi")
- .fixup = fixup_corgi,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_machine = corgi_init,
- .init_time = pxa_timer_init,
- .restart = corgi_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_SHEPHERD
-MACHINE_START(SHEPHERD, "SHARP Shepherd")
- .fixup = fixup_corgi,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_machine = corgi_init,
- .init_time = pxa_timer_init,
- .restart = corgi_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_HUSKY
-MACHINE_START(HUSKY, "SHARP Husky")
- .fixup = fixup_corgi,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_machine = corgi_init,
- .init_time = pxa_timer_init,
- .restart = corgi_restart,
-MACHINE_END
-#endif
-
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
deleted file mode 100644
index 092dcb9fced5..000000000000
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ /dev/null
@@ -1,222 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Battery and Power Management code for the Sharp SL-C7xx
- *
- * Copyright (c) 2005 Richard Purdie
- */
-
-#include <linux/module.h>
-#include <linux/stat.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/apm-emulation.h>
-#include <linux/io.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-
-#include <mach/corgi.h>
-#include <mach/pxa2xx-regs.h>
-#include "sharpsl_pm.h"
-
-#include "generic.h"
-
-#define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */
-#define SHARPSL_CHARGE_ON_TEMP 0xe0 /* 2.9V */
-#define SHARPSL_CHARGE_ON_ACIN_HIGH 0x9b /* 6V */
-#define SHARPSL_CHARGE_ON_ACIN_LOW 0x34 /* 2V */
-#define SHARPSL_FATAL_ACIN_VOLT 182 /* 3.45V */
-#define SHARPSL_FATAL_NOACIN_VOLT 170 /* 3.40V */
-
-static struct gpio charger_gpios[] = {
- { CORGI_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
- { CORGI_GPIO_CHRG_ON, GPIOF_OUT_INIT_LOW, "Charger On" },
- { CORGI_GPIO_CHRG_UKN, GPIOF_OUT_INIT_LOW, "Charger Unknown" },
- { CORGI_GPIO_AC_IN, GPIOF_IN, "Charger Detection" },
- { CORGI_GPIO_KEY_INT, GPIOF_IN, "Key Interrupt" },
- { CORGI_GPIO_WAKEUP, GPIOF_IN, "System wakeup notification" },
-};
-
-static void corgi_charger_init(void)
-{
- gpio_request_array(ARRAY_AND_SIZE(charger_gpios));
-}
-
-static void corgi_measure_temp(int on)
-{
- gpio_set_value(CORGI_GPIO_ADC_TEMP_ON, on);
-}
-
-static void corgi_charge(int on)
-{
- if (on) {
- if (machine_is_corgi() && (sharpsl_pm.flags & SHARPSL_SUSPENDED)) {
- gpio_set_value(CORGI_GPIO_CHRG_ON, 0);
- gpio_set_value(CORGI_GPIO_CHRG_UKN, 1);
- } else {
- gpio_set_value(CORGI_GPIO_CHRG_ON, 1);
- gpio_set_value(CORGI_GPIO_CHRG_UKN, 0);
- }
- } else {
- gpio_set_value(CORGI_GPIO_CHRG_ON, 0);
- gpio_set_value(CORGI_GPIO_CHRG_UKN, 0);
- }
-}
-
-static void corgi_discharge(int on)
-{
- gpio_set_value(CORGI_GPIO_DISCHARGE_ON, on);
-}
-
-static void corgi_presuspend(void)
-{
-}
-
-static void corgi_postsuspend(void)
-{
-}
-
-/*
- * Check what brought us out of the suspend.
- * Return: 0 to sleep, otherwise wake
- */
-static int corgi_should_wakeup(unsigned int resume_on_alarm)
-{
- int is_resume = 0;
-
- dev_dbg(sharpsl_pm.dev, "PEDR = %x, GPIO_AC_IN = %d, "
- "GPIO_CHRG_FULL = %d, GPIO_KEY_INT = %d, GPIO_WAKEUP = %d\n",
- PEDR, gpio_get_value(CORGI_GPIO_AC_IN),
- gpio_get_value(CORGI_GPIO_CHRG_FULL),
- gpio_get_value(CORGI_GPIO_KEY_INT),
- gpio_get_value(CORGI_GPIO_WAKEUP));
-
- if ((PEDR & GPIO_bit(CORGI_GPIO_AC_IN))) {
- if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
- /* charge on */
- dev_dbg(sharpsl_pm.dev, "ac insert\n");
- sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
- } else {
- /* charge off */
- dev_dbg(sharpsl_pm.dev, "ac remove\n");
- sharpsl_pm_led(SHARPSL_LED_OFF);
- sharpsl_pm.machinfo->charge(0);
- sharpsl_pm.charge_mode = CHRG_OFF;
- }
- }
-
- if ((PEDR & GPIO_bit(CORGI_GPIO_CHRG_FULL)))
- dev_dbg(sharpsl_pm.dev, "Charge full interrupt\n");
-
- if (PEDR & GPIO_bit(CORGI_GPIO_KEY_INT))
- is_resume |= GPIO_bit(CORGI_GPIO_KEY_INT);
-
- if (PEDR & GPIO_bit(CORGI_GPIO_WAKEUP))
- is_resume |= GPIO_bit(CORGI_GPIO_WAKEUP);
-
- if (resume_on_alarm && (PEDR & PWER_RTC))
- is_resume |= PWER_RTC;
-
- dev_dbg(sharpsl_pm.dev, "is_resume: %x\n",is_resume);
- return is_resume;
-}
-
-static bool corgi_charger_wakeup(void)
-{
- return !gpio_get_value(CORGI_GPIO_AC_IN) ||
- !gpio_get_value(CORGI_GPIO_KEY_INT) ||
- !gpio_get_value(CORGI_GPIO_WAKEUP);
-}
-
-unsigned long corgipm_read_devdata(int type)
-{
- switch(type) {
- case SHARPSL_STATUS_ACIN:
- return !gpio_get_value(CORGI_GPIO_AC_IN);
- case SHARPSL_STATUS_LOCK:
- return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock);
- case SHARPSL_STATUS_CHRGFULL:
- return gpio_get_value(sharpsl_pm.machinfo->gpio_batfull);
- case SHARPSL_STATUS_FATAL:
- return gpio_get_value(sharpsl_pm.machinfo->gpio_fatal);
- case SHARPSL_ACIN_VOLT:
- return sharpsl_pm_pxa_read_max1111(MAX1111_ACIN_VOLT);
- case SHARPSL_BATT_TEMP:
- return sharpsl_pm_pxa_read_max1111(MAX1111_BATT_TEMP);
- case SHARPSL_BATT_VOLT:
- default:
- return sharpsl_pm_pxa_read_max1111(MAX1111_BATT_VOLT);
- }
-}
-
-static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
- .init = corgi_charger_init,
- .exit = NULL,
- .gpio_batlock = CORGI_GPIO_BAT_COVER,
- .gpio_acin = CORGI_GPIO_AC_IN,
- .gpio_batfull = CORGI_GPIO_CHRG_FULL,
- .discharge = corgi_discharge,
- .charge = corgi_charge,
- .measure_temp = corgi_measure_temp,
- .presuspend = corgi_presuspend,
- .postsuspend = corgi_postsuspend,
- .read_devdata = corgipm_read_devdata,
- .charger_wakeup = corgi_charger_wakeup,
- .should_wakeup = corgi_should_wakeup,
-#if defined(CONFIG_LCD_CORGI)
- .backlight_limit = corgi_lcd_limit_intensity,
-#endif
- .charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
- .charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
- .charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
- .charge_acin_low = SHARPSL_CHARGE_ON_ACIN_LOW,
- .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT,
- .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT,
- .bat_levels = 40,
- .bat_levels_noac = sharpsl_battery_levels_noac,
- .bat_levels_acin = sharpsl_battery_levels_acin,
- .status_high_acin = 188,
- .status_low_acin = 178,
- .status_high_noac = 185,
- .status_low_noac = 175,
-};
-
-static struct platform_device *corgipm_device;
-
-static int corgipm_init(void)
-{
- int ret;
-
- if (!machine_is_corgi() && !machine_is_shepherd()
- && !machine_is_husky())
- return -ENODEV;
-
- corgipm_device = platform_device_alloc("sharpsl-pm", -1);
- if (!corgipm_device)
- return -ENOMEM;
-
- if (!machine_is_corgi())
- corgi_pm_machinfo.batfull_irq = 1;
-
- corgipm_device->dev.platform_data = &corgi_pm_machinfo;
- ret = platform_device_add(corgipm_device);
-
- if (ret)
- platform_device_put(corgipm_device);
-
- return ret;
-}
-
-static void corgipm_exit(void)
-{
- platform_device_unregister(corgipm_device);
-}
-
-module_init(corgipm_init);
-module_exit(corgipm_exit);
diff --git a/arch/arm/mach-pxa/csb701.c b/arch/arm/mach-pxa/csb701.c
deleted file mode 100644
index 527c9fdf9795..000000000000
--- a/arch/arm/mach-pxa/csb701.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-
-#include <asm/mach-types.h>
-
-static struct gpio_keys_button csb701_buttons[] = {
- {
- .code = 0x7,
- .gpio = 1,
- .active_low = 1,
- .desc = "SW2",
- .type = EV_SW,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data csb701_gpio_keys_data = {
- .buttons = csb701_buttons,
- .nbuttons = ARRAY_SIZE(csb701_buttons),
-};
-
-static struct gpio_led csb701_leds[] = {
- {
- .name = "csb701:yellow:heartbeat",
- .default_trigger = "heartbeat",
- .gpio = 11,
- .active_low = 1,
- },
-};
-
-static struct platform_device csb701_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev.platform_data = &csb701_gpio_keys_data,
-};
-
-static struct gpio_led_platform_data csb701_leds_gpio_data = {
- .leds = csb701_leds,
- .num_leds = ARRAY_SIZE(csb701_leds),
-};
-
-static struct platform_device csb701_leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev.platform_data = &csb701_leds_gpio_data,
-};
-
-static struct platform_device *devices[] __initdata = {
- &csb701_gpio_keys,
- &csb701_leds_gpio,
-};
-
-static int __init csb701_init(void)
-{
- if (!machine_is_csb726())
- return -ENODEV;
-
- return platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-module_init(csb701_init);
-
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
deleted file mode 100644
index 98fcdc6e2944..000000000000
--- a/arch/arm/mach-pxa/csb726.c
+++ /dev/null
@@ -1,290 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for Cogent CSB726
- *
- * Copyright (c) 2008 Dmitry Eremin-Solenikov
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sm501.h>
-#include <linux/smsc911x.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "csb726.h"
-#include "pxa27x.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/audio.h>
-#include <mach/smemc.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/*
- * n/a: 2, 5, 6, 7, 8, 23, 24, 25, 26, 27, 87, 88, 89,
- * nu: 58 -- 77, 90, 91, 93, 102, 105-108, 114-116,
- * XXX: 21,
- * XXX: 79 CS_3 for LAN9215 or PSKTSEL on R2, R3
- * XXX: 33 CS_5 for LAN9215 on R1
- */
-
-static unsigned long csb726_pin_config[] = {
- GPIO78_nCS_2, /* EXP_CS */
- GPIO79_nCS_3, /* SMSC9215 */
- GPIO80_nCS_4, /* SM501 */
-
- GPIO52_GPIO, /* #SMSC9251 int */
- GPIO53_GPIO, /* SM501 int */
-
- GPIO1_GPIO, /* GPIO0 */
- GPIO11_GPIO, /* GPIO1 */
- GPIO9_GPIO, /* GPIO2 */
- GPIO10_GPIO, /* GPIO3 */
- GPIO16_PWM0_OUT, /* or GPIO4 */
- GPIO17_PWM1_OUT, /* or GPIO5 */
- GPIO94_GPIO, /* GPIO6 */
- GPIO95_GPIO, /* GPIO7 */
- GPIO96_GPIO, /* GPIO8 */
- GPIO97_GPIO, /* GPIO9 */
- GPIO15_GPIO, /* EXP_IRQ */
- GPIO18_RDY, /* EXP_WAIT */
-
- GPIO0_GPIO, /* PWR_INT */
- GPIO104_GPIO, /* PWR_OFF */
-
- GPIO12_GPIO, /* touch irq */
-
- GPIO13_SSP2_TXD,
- GPIO14_SSP2_SFRM,
- MFP_CFG_OUT(GPIO19, AF1, DRIVE_LOW),/* SSP2_SYSCLK */
- GPIO22_SSP2_SCLK,
-
- GPIO81_SSP3_TXD,
- GPIO82_SSP3_RXD,
- GPIO83_SSP3_SFRM,
- GPIO84_SSP3_SCLK,
-
- GPIO20_GPIO, /* SDIO int */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO100_GPIO, /* SD CD */
- GPIO101_GPIO, /* SD WP */
-
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO113_AC97_nRESET,
-
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
- GPIO36_FFUART_DCD,
- GPIO37_FFUART_DSR,
- GPIO38_FFUART_RI,
- GPIO39_FFUART_TXD,
- GPIO40_FFUART_DTR,
- GPIO41_FFUART_RTS,
-
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO54_nPCE_2,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16, /* maybe unused */
- GPIO85_nPCE_1,
- GPIO98_GPIO, /* CF IRQ */
- GPIO99_GPIO, /* CF CD */
- GPIO103_GPIO, /* Reset */
-
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-};
-
-static struct pxamci_platform_data csb726_mci = {
- .detect_delay_ms = 500,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- /* FIXME setpower */
-};
-
-static struct gpiod_lookup_table csb726_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on GPIO 100 */
- GPIO_LOOKUP("gpio-pxa", CSB726_GPIO_MMC_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- /* Write protect on GPIO 101 */
- GPIO_LOOKUP("gpio-pxa", CSB726_GPIO_MMC_RO,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct pxaohci_platform_data csb726_ohci_platform_data = {
- .port_mode = PMM_NPS_MODE,
- .flags = ENABLE_PORT1 | NO_OC_PROTECTION,
-};
-
-static struct mtd_partition csb726_flash_partitions[] = {
- {
- .name = "Bootloader",
- .offset = 0,
- .size = CSB726_FLASH_uMON,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- },
- {
- .name = "root",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct physmap_flash_data csb726_flash_data = {
- .width = 2,
- .parts = csb726_flash_partitions,
- .nr_parts = ARRAY_SIZE(csb726_flash_partitions),
-};
-
-static struct resource csb726_flash_resources[] = {
- {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + CSB726_FLASH_SIZE - 1 ,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device csb726_flash = {
- .name = "physmap-flash",
- .dev = {
- .platform_data = &csb726_flash_data,
- },
- .resource = csb726_flash_resources,
- .num_resources = ARRAY_SIZE(csb726_flash_resources),
-};
-
-static struct resource csb726_sm501_resources[] = {
- {
- .start = PXA_CS4_PHYS,
- .end = PXA_CS4_PHYS + SZ_8M - 1,
- .flags = IORESOURCE_MEM,
- .name = "sm501-localmem",
- },
- {
- .start = PXA_CS4_PHYS + SZ_64M - SZ_2M,
- .end = PXA_CS4_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- .name = "sm501-regs",
- },
- {
- .start = CSB726_IRQ_SM501,
- .end = CSB726_IRQ_SM501,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct sm501_initdata csb726_sm501_initdata = {
-/* .devices = SM501_USE_USB_HOST, */
- .devices = SM501_USE_USB_HOST | SM501_USE_UART0 | SM501_USE_UART1,
-};
-
-static struct sm501_platdata csb726_sm501_platdata = {
- .init = &csb726_sm501_initdata,
-};
-
-static struct platform_device csb726_sm501 = {
- .name = "sm501",
- .id = 0,
- .num_resources = ARRAY_SIZE(csb726_sm501_resources),
- .resource = csb726_sm501_resources,
- .dev = {
- .platform_data = &csb726_sm501_platdata,
- },
-};
-
-static struct resource csb726_lan_resources[] = {
- {
- .start = PXA_CS3_PHYS,
- .end = PXA_CS3_PHYS + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CSB726_IRQ_LAN,
- .end = CSB726_IRQ_LAN,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-struct smsc911x_platform_config csb726_lan_config = {
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
- .flags = SMSC911X_USE_32BIT,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-
-static struct platform_device csb726_lan = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(csb726_lan_resources),
- .resource = csb726_lan_resources,
- .dev = {
- .platform_data = &csb726_lan_config,
- },
-};
-
-static struct platform_device *devices[] __initdata = {
- &csb726_flash,
- &csb726_sm501,
- &csb726_lan,
-};
-
-static void __init csb726_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config));
-/* __raw_writel(0x7ffc3ffc, MSC1); *//* LAN9215/EXP_CS */
-/* __raw_writel(0x06697ff4, MSC2); *//* none/SM501 */
- __raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- pxa_set_i2c_info(NULL);
- pxa27x_set_i2c_power_info(NULL);
- gpiod_add_lookup_table(&csb726_mci_gpio_table);
- pxa_set_mci_info(&csb726_mci);
- pxa_set_ohci_info(&csb726_ohci_platform_data);
- pxa_set_ac97_info(NULL);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-MACHINE_START(CSB726, "Cogent CSB726")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_machine = csb726_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/csb726.h b/arch/arm/mach-pxa/csb726.h
deleted file mode 100644
index 30d7cf926b84..000000000000
--- a/arch/arm/mach-pxa/csb726.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Support for Cogent CSB726
- *
- * Copyright (c) 2008 Dmitry Baryshkov
- */
-#ifndef CSB726_H
-#define CSB726_H
-
-#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
-
-#define CSB726_GPIO_IRQ_LAN 52
-#define CSB726_GPIO_IRQ_SM501 53
-#define CSB726_GPIO_MMC_DETECT 100
-#define CSB726_GPIO_MMC_RO 101
-
-#define CSB726_FLASH_SIZE (64 * 1024 * 1024)
-#define CSB726_FLASH_uMON (8 * 1024 * 1024)
-
-#define CSB726_IRQ_LAN PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN)
-#define CSB726_IRQ_SM501 PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501)
-
-#endif
-
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 09b8495f3fd9..661b3fc43275 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -9,21 +9,17 @@
#include <linux/dmaengine.h>
#include <linux/spi/pxa2xx_spi.h>
#include <linux/platform_data/i2c-pxa.h>
+#include <linux/soc/pxa/cpu.h>
#include "udc.h"
-#include <linux/platform_data/usb-pxa3xx-ulpi.h>
#include <linux/platform_data/video-pxafb.h>
#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/platform_data/media/camera-pxa.h>
-#include <mach/audio.h>
-#include <mach/hardware.h>
#include <linux/platform_data/mmp_dma.h>
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
+#include "regs-ost.h"
+#include "reset.h"
#include "devices.h"
#include "generic.h"
@@ -82,16 +78,10 @@ void __init pxa_set_mci_info(struct pxamci_platform_data *info)
pxa_register_device(&pxa_device_mci, info);
}
-
static struct pxa2xx_udc_mach_info pxa_udc_info = {
.gpio_pullup = -1,
};
-void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
-{
- memcpy(&pxa_udc_info, info, sizeof *info);
-}
-
static struct resource pxa2xx_udc_resources[] = {
[0] = {
.start = 0x40600000,
@@ -129,33 +119,6 @@ struct platform_device pxa27x_device_udc = {
}
};
-#ifdef CONFIG_PXA3xx
-static struct resource pxa3xx_u2d_resources[] = {
- [0] = {
- .start = 0x54100000,
- .end = 0x54100fff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_USB2,
- .end = IRQ_USB2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa3xx_device_u2d = {
- .name = "pxa3xx-u2d",
- .id = -1,
- .resource = pxa3xx_u2d_resources,
- .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
-};
-
-void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
-{
- pxa_register_device(&pxa3xx_device_u2d, info);
-}
-#endif /* CONFIG_PXA3xx */
-
static struct resource pxafb_resources[] = {
[0] = {
.start = 0x44000000,
@@ -376,47 +339,6 @@ struct platform_device pxa_device_asoc_platform = {
.id = -1,
};
-static u64 pxaficp_dmamask = ~(u32)0;
-
-static struct resource pxa_ir_resources[] = {
- [0] = {
- .start = IRQ_STUART,
- .end = IRQ_STUART,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .start = IRQ_ICP,
- .end = IRQ_ICP,
- .flags = IORESOURCE_IRQ,
- },
- [3] = {
- .start = 0x40800000,
- .end = 0x4080001b,
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = 0x40700000,
- .end = 0x40700023,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device pxa_device_ficp = {
- .name = "pxa2xx-ir",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa_ir_resources),
- .resource = pxa_ir_resources,
- .dev = {
- .dma_mask = &pxaficp_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
-void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
-{
- pxa_register_device(&pxa_device_ficp, info);
-}
-
static struct resource pxa_rtc_resources[] = {
[0] = {
.start = 0x40900000,
@@ -451,49 +373,6 @@ struct platform_device sa1100_device_rtc = {
.resource = pxa_rtc_resources,
};
-static struct resource pxa_ac97_resources[] = {
- [0] = {
- .start = 0x40500000,
- .end = 0x40500000 + 0xfff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_AC97,
- .end = IRQ_AC97,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 pxa_ac97_dmamask = 0xffffffffUL;
-
-struct platform_device pxa_device_ac97 = {
- .name = "pxa2xx-ac97",
- .id = -1,
- .dev = {
- .dma_mask = &pxa_ac97_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(pxa_ac97_resources),
- .resource = pxa_ac97_resources,
-};
-
-void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
-{
- int ret;
-
- ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:0", "AC97CLK",
- &pxa_device_ac97.dev);
- if (ret)
- pr_err("PXA AC97 clock1 alias error: %d\n", ret);
-
- ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:1", "AC97CLK",
- &pxa_device_ac97.dev);
- if (ret)
- pr_err("PXA AC97 clock2 alias error: %d\n", ret);
-
- pxa_register_device(&pxa_device_ac97, ops);
-}
-
#ifdef CONFIG_PXA25x
static struct resource pxa25x_resource_pwm0[] = {
@@ -607,44 +486,6 @@ struct platform_device pxa25x_device_assp = {
#endif /* CONFIG_PXA25x */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-static struct resource pxa27x_resource_camera[] = {
- [0] = {
- .start = 0x50000000,
- .end = 0x50000fff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_CAMERA,
- .end = IRQ_CAMERA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
-
-static struct platform_device pxa27x_device_camera = {
- .name = "pxa27x-camera",
- .id = 0, /* This is used to put cameras on this interface */
- .dev = {
- .dma_mask = &pxa27x_dma_mask_camera,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
- .resource = pxa27x_resource_camera,
-};
-
-void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
-{
- struct clk *mclk;
-
- /* Register a fixed-rate clock for camera sensors. */
- mclk = clk_register_fixed_rate(NULL, "pxa_camera_clk", NULL, 0,
- info->mclk_10khz * 10000);
- if (!IS_ERR(mclk))
- clkdev_create(mclk, "mclk", NULL);
- pxa_register_device(&pxa27x_device_camera, info);
-}
-
static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa27x_resource_ohci[] = {
@@ -678,31 +519,6 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-static struct resource pxa27x_resource_keypad[] = {
- [0] = {
- .start = 0x41500000,
- .end = 0x4150004c,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_KEYPAD,
- .end = IRQ_KEYPAD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa27x_device_keypad = {
- .name = "pxa27x-keypad",
- .id = -1,
- .resource = pxa27x_resource_keypad,
- .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
-};
-
-void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
-{
- pxa_register_device(&pxa27x_device_keypad, info);
-}
-
static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa27x_resource_ssp1[] = {
@@ -812,210 +628,6 @@ struct platform_device pxa27x_device_pwm1 = {
};
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
-#ifdef CONFIG_PXA3xx
-static struct resource pxa3xx_resources_mci2[] = {
- [0] = {
- .start = 0x42000000,
- .end = 0x42000fff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_MMC2,
- .end = IRQ_MMC2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa3xx_device_mci2 = {
- .name = "pxa2xx-mci",
- .id = 1,
- .dev = {
- .dma_mask = &pxamci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
- .resource = pxa3xx_resources_mci2,
-};
-
-void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
-{
- pxa_register_device(&pxa3xx_device_mci2, info);
-}
-
-static struct resource pxa3xx_resources_mci3[] = {
- [0] = {
- .start = 0x42500000,
- .end = 0x42500fff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_MMC3,
- .end = IRQ_MMC3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa3xx_device_mci3 = {
- .name = "pxa2xx-mci",
- .id = 2,
- .dev = {
- .dma_mask = &pxamci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
- .resource = pxa3xx_resources_mci3,
-};
-
-void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
-{
- pxa_register_device(&pxa3xx_device_mci3, info);
-}
-
-static struct resource pxa3xx_resources_gcu[] = {
- {
- .start = 0x54000000,
- .end = 0x54000fff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_GCU,
- .end = IRQ_GCU,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device pxa3xx_device_gcu = {
- .name = "pxa3xx-gcu",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
- .resource = pxa3xx_resources_gcu,
- .dev = {
- .dma_mask = &pxa3xx_gcu_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
-#endif /* CONFIG_PXA3xx */
-
-#if defined(CONFIG_PXA3xx)
-static struct resource pxa3xx_resources_i2c_power[] = {
- {
- .start = 0x40f500c0,
- .end = 0x40f500d3,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PWRI2C,
- .end = IRQ_PWRI2C,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device pxa3xx_device_i2c_power = {
- .name = "pxa3xx-pwri2c",
- .id = 1,
- .resource = pxa3xx_resources_i2c_power,
- .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
-};
-
-static struct resource pxa3xx_resources_nand[] = {
- [0] = {
- .start = 0x43100000,
- .end = 0x43100053,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_NAND,
- .end = IRQ_NAND,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device pxa3xx_device_nand = {
- .name = "pxa3xx-nand",
- .id = -1,
- .dev = {
- .dma_mask = &pxa3xx_nand_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
- .resource = pxa3xx_resources_nand,
-};
-
-void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
-{
- pxa_register_device(&pxa3xx_device_nand, info);
-}
-
-static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa3xx_resource_ssp4[] = {
- [0] = {
- .start = 0x41a00000,
- .end = 0x41a0003f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SSP4,
- .end = IRQ_SSP4,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/*
- * PXA3xx SSP is basically equivalent to PXA27x.
- * However, we need to register the device by the correct name in order to
- * make the driver set the correct internal type, hence we provide specific
- * platform_devices for each of them.
- */
-struct platform_device pxa3xx_device_ssp1 = {
- .name = "pxa3xx-ssp",
- .id = 0,
- .dev = {
- .dma_mask = &pxa27x_ssp1_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa27x_resource_ssp1,
- .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
-};
-
-struct platform_device pxa3xx_device_ssp2 = {
- .name = "pxa3xx-ssp",
- .id = 1,
- .dev = {
- .dma_mask = &pxa27x_ssp2_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa27x_resource_ssp2,
- .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
-};
-
-struct platform_device pxa3xx_device_ssp3 = {
- .name = "pxa3xx-ssp",
- .id = 2,
- .dev = {
- .dma_mask = &pxa27x_ssp3_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa27x_resource_ssp3,
- .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
-};
-
-struct platform_device pxa3xx_device_ssp4 = {
- .name = "pxa3xx-ssp",
- .id = 3,
- .dev = {
- .dma_mask = &pxa3xx_ssp4_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = pxa3xx_resource_ssp4,
- .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
-};
-#endif /* CONFIG_PXA3xx */
-
struct resource pxa_resource_gpio[] = {
{
.start = 0x40e00000,
@@ -1040,11 +652,7 @@ struct resource pxa_resource_gpio[] = {
};
struct platform_device pxa25x_device_gpio = {
-#ifdef CONFIG_CPU_PXA26x
- .name = "pxa26x-gpio",
-#else
.name = "pxa25x-gpio",
-#endif
.id = -1,
.num_resources = ARRAY_SIZE(pxa_resource_gpio),
.resource = pxa_resource_gpio,
@@ -1057,20 +665,6 @@ struct platform_device pxa27x_device_gpio = {
.resource = pxa_resource_gpio,
};
-struct platform_device pxa3xx_device_gpio = {
- .name = "pxa3xx-gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa_resource_gpio),
- .resource = pxa_resource_gpio,
-};
-
-struct platform_device pxa93x_device_gpio = {
- .name = "pxa93x-gpio",
- .id = -1,
- .num_resources = ARRAY_SIZE(pxa_resource_gpio),
- .resource = pxa_resource_gpio,
-};
-
/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
* See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_controller *info)
@@ -1118,3 +712,12 @@ void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata)
{
pxa_register_device(&pxa2xx_pxa_dma, dma_pdata);
}
+
+void __init pxa_register_wdt(unsigned int reset_status)
+{
+ struct resource res = DEFINE_RES_MEM(OST_PHYS, OST_LEN);
+
+ reset_status &= RESET_STATUS_WATCHDOG;
+ platform_device_register_resndata(NULL, "sa1100_wdt", -1, &res, 1,
+ &reset_status, sizeof(reset_status));
+}
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 498b07bc6a3e..82c83939017a 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -9,7 +9,6 @@ extern struct platform_device pxa3xx_device_mci2;
extern struct platform_device pxa3xx_device_mci3;
extern struct platform_device pxa25x_device_udc;
extern struct platform_device pxa27x_device_udc;
-extern struct platform_device pxa3xx_device_u2d;
extern struct platform_device pxa_device_fb;
extern struct platform_device pxa_device_ffuart;
extern struct platform_device pxa_device_btuart;
@@ -17,7 +16,6 @@ extern struct platform_device pxa_device_stuart;
extern struct platform_device pxa_device_hwuart;
extern struct platform_device pxa_device_i2c;
extern struct platform_device pxa_device_i2s;
-extern struct platform_device pxa_device_ficp;
extern struct platform_device sa1100_device_rtc;
extern struct platform_device pxa_device_rtc;
extern struct platform_device pxa_device_ac97;
diff --git a/arch/arm/mach-pxa/eseries-irq.h b/arch/arm/mach-pxa/eseries-irq.h
deleted file mode 100644
index 572d573ce66b..000000000000
--- a/arch/arm/mach-pxa/eseries-irq.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * eseries-irq.h
- *
- * Copyright (C) Ian Molton <spyro@f2s.com>
- */
-
-#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8)
-#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n))
-
-#define ANGELX_RDY0_IRQ IRQ_ANGELX(0)
-#define ANGELX_ST0_IRQ IRQ_ANGELX(1)
-#define ANGELX_CD0_IRQ IRQ_ANGELX(2)
-#define ANGELX_RDY1_IRQ IRQ_ANGELX(3)
-#define ANGELX_ST1_IRQ IRQ_ANGELX(4)
-#define ANGELX_CD1_IRQ IRQ_ANGELX(5)
-
-#define TMIO_IRQ_BASE (IRQ_BOARD_START+0)
-#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n))
-
-#define TMIO_SD_IRQ IRQ_TMIO(1)
-#define TMIO_USB_IRQ IRQ_TMIO(2)
-
-#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16)
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
deleted file mode 100644
index f37c44b6139d..000000000000
--- a/arch/arm/mach-pxa/eseries.c
+++ /dev/null
@@ -1,978 +0,0 @@
-/*
- * Hardware definitions for the Toshiba eseries PDAs
- *
- * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/clkdev.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk-provider.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/tc6387xb.h>
-#include <linux/mfd/tc6393xb.h>
-#include <linux/mfd/t7l66xb.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/memblock.h>
-
-#include <video/w100fb.h>
-
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include "pxa25x.h"
-#include <mach/eseries-gpio.h>
-#include "eseries-irq.h"
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include "udc.h"
-#include <linux/platform_data/irda-pxaficp.h>
-
-#include "devices.h"
-#include "generic.h"
-
-/* Only e800 has 128MB RAM */
-void __init eseries_fixup(struct tag *tags, char **cmdline)
-{
- if (machine_is_e800())
- memblock_add(0xa0000000, SZ_128M);
- else
- memblock_add(0xa0000000, SZ_64M);
-}
-
-static struct gpiod_lookup_table e7xx_gpio_vbus_gpiod_table __maybe_unused = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_E7XX_USB_DISC,
- "vbus", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_E7XX_USB_PULLUP,
- "pullup", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct platform_device e7xx_gpio_vbus __maybe_unused = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-struct pxaficp_platform_data e7xx_ficp_platform_data = {
- .gpio_pwdown = GPIO_E7XX_IR_OFF,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-int eseries_tmio_enable(struct platform_device *dev)
-{
- /* Reset - bring SUSPEND high before PCLR */
- gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
- gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0);
- msleep(1);
- gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1);
- msleep(1);
- gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 1);
- msleep(1);
- return 0;
-}
-
-int eseries_tmio_disable(struct platform_device *dev)
-{
- gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
- gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0);
- return 0;
-}
-
-int eseries_tmio_suspend(struct platform_device *dev)
-{
- gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
- return 0;
-}
-
-int eseries_tmio_resume(struct platform_device *dev)
-{
- gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1);
- msleep(1);
- return 0;
-}
-
-void eseries_get_tmio_gpios(void)
-{
- gpio_request(GPIO_ESERIES_TMIO_SUSPEND, NULL);
- gpio_request(GPIO_ESERIES_TMIO_PCLR, NULL);
- gpio_direction_output(GPIO_ESERIES_TMIO_SUSPEND, 0);
- gpio_direction_output(GPIO_ESERIES_TMIO_PCLR, 0);
-}
-
-/* TMIO controller uses the same resources on all e-series machines. */
-struct resource eseries_tmio_resources[] = {
- [0] = {
- .start = PXA_CS4_PHYS,
- .end = PXA_CS4_PHYS + 0x1fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ),
- .end = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* Some e-series hardware cannot control the 32K clock */
-static void __init __maybe_unused eseries_register_clks(void)
-{
- clk_register_fixed_rate(NULL, "CLK_CK32K", NULL, 0, 32768);
-}
-
-#ifdef CONFIG_MACH_E330
-/* -------------------- e330 tc6387xb parameters -------------------- */
-
-static struct tc6387xb_platform_data e330_tc6387xb_info = {
- .enable = &eseries_tmio_enable,
- .disable = &eseries_tmio_disable,
- .suspend = &eseries_tmio_suspend,
- .resume = &eseries_tmio_resume,
-};
-
-static struct platform_device e330_tc6387xb_device = {
- .name = "tc6387xb",
- .id = -1,
- .dev = {
- .platform_data = &e330_tc6387xb_info,
- },
- .num_resources = 2,
- .resource = eseries_tmio_resources,
-};
-
-/* --------------------------------------------------------------- */
-
-static struct platform_device *e330_devices[] __initdata = {
- &e330_tc6387xb_device,
- &e7xx_gpio_vbus,
-};
-
-static void __init e330_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- eseries_register_clks();
- eseries_get_tmio_gpios();
- gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
- platform_add_devices(ARRAY_AND_SIZE(e330_devices));
-}
-
-MACHINE_START(E330, "Toshiba e330")
- /* Maintainer: Ian Molton (spyro@f2s.com) */
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = ESERIES_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .fixup = eseries_fixup,
- .init_machine = e330_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E350
-/* -------------------- e350 t7l66xb parameters -------------------- */
-
-static struct t7l66xb_platform_data e350_t7l66xb_info = {
- .irq_base = IRQ_BOARD_START,
- .enable = &eseries_tmio_enable,
- .suspend = &eseries_tmio_suspend,
- .resume = &eseries_tmio_resume,
-};
-
-static struct platform_device e350_t7l66xb_device = {
- .name = "t7l66xb",
- .id = -1,
- .dev = {
- .platform_data = &e350_t7l66xb_info,
- },
- .num_resources = 2,
- .resource = eseries_tmio_resources,
-};
-
-/* ---------------------------------------------------------- */
-
-static struct platform_device *e350_devices[] __initdata = {
- &e350_t7l66xb_device,
- &e7xx_gpio_vbus,
-};
-
-static void __init e350_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- eseries_register_clks();
- eseries_get_tmio_gpios();
- gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
- platform_add_devices(ARRAY_AND_SIZE(e350_devices));
-}
-
-MACHINE_START(E350, "Toshiba e350")
- /* Maintainer: Ian Molton (spyro@f2s.com) */
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = ESERIES_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .fixup = eseries_fixup,
- .init_machine = e350_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E400
-/* ------------------------ E400 LCD definitions ------------------------ */
-
-static struct pxafb_mode_info e400_pxafb_mode_info = {
- .pixclock = 140703,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 4,
- .left_margin = 28,
- .right_margin = 8,
- .vsync_len = 3,
- .upper_margin = 5,
- .lower_margin = 6,
- .sync = 0,
-};
-
-static struct pxafb_mach_info e400_pxafb_mach_info = {
- .modes = &e400_pxafb_mode_info,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP,
- .lccr3 = 0,
- .pxafb_backlight_power = NULL,
-};
-
-/* ------------------------ E400 MFP config ----------------------------- */
-
-static unsigned long e400_pin_config[] __initdata = {
- /* Chip selects */
- GPIO15_nCS_1, /* CS1 - Flash */
- GPIO80_nCS_4, /* CS4 - TMIO */
-
- /* Clocks */
- GPIO12_32KHz,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
-
- /* TMIO controller */
- GPIO19_GPIO, /* t7l66xb #PCLR */
- GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
-
- /* wakeup */
- GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-/* ---------------------------------------------------------------------- */
-
-static struct mtd_partition partition_a = {
- .name = "Internal NAND flash",
- .offset = 0,
- .size = MTDPART_SIZ_FULL,
-};
-
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr e400_t7l66xb_nand_bbt = {
- .options = 0,
- .offs = 4,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-static struct tmio_nand_data e400_t7l66xb_nand_config = {
- .num_partitions = 1,
- .partition = &partition_a,
- .badblock_pattern = &e400_t7l66xb_nand_bbt,
-};
-
-static struct t7l66xb_platform_data e400_t7l66xb_info = {
- .irq_base = IRQ_BOARD_START,
- .enable = &eseries_tmio_enable,
- .suspend = &eseries_tmio_suspend,
- .resume = &eseries_tmio_resume,
-
- .nand_data = &e400_t7l66xb_nand_config,
-};
-
-static struct platform_device e400_t7l66xb_device = {
- .name = "t7l66xb",
- .id = -1,
- .dev = {
- .platform_data = &e400_t7l66xb_info,
- },
- .num_resources = 2,
- .resource = eseries_tmio_resources,
-};
-
-/* ---------------------------------------------------------- */
-
-static struct platform_device *e400_devices[] __initdata = {
- &e400_t7l66xb_device,
- &e7xx_gpio_vbus,
-};
-
-static void __init e400_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- /* Fixme - e400 may have a switched clock */
- eseries_register_clks();
- eseries_get_tmio_gpios();
- pxa_set_fb_info(NULL, &e400_pxafb_mach_info);
- gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
- platform_add_devices(ARRAY_AND_SIZE(e400_devices));
-}
-
-MACHINE_START(E400, "Toshiba e400")
- /* Maintainer: Ian Molton (spyro@f2s.com) */
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = ESERIES_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .fixup = eseries_fixup,
- .init_machine = e400_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E740
-/* ------------------------ e740 video support --------------------------- */
-
-static struct w100_gen_regs e740_lcd_regs = {
- .lcd_format = 0x00008023,
- .lcdd_cntl1 = 0x0f000000,
- .lcdd_cntl2 = 0x0003ffff,
- .genlcd_cntl1 = 0x00ffff03,
- .genlcd_cntl2 = 0x003c0f03,
- .genlcd_cntl3 = 0x000143aa,
-};
-
-static struct w100_mode e740_lcd_mode = {
- .xres = 240,
- .yres = 320,
- .left_margin = 20,
- .right_margin = 28,
- .upper_margin = 9,
- .lower_margin = 8,
- .crtc_ss = 0x80140013,
- .crtc_ls = 0x81150110,
- .crtc_gs = 0x80050005,
- .crtc_vpos_gs = 0x000a0009,
- .crtc_rev = 0x0040010a,
- .crtc_dclk = 0xa906000a,
- .crtc_gclk = 0x80050108,
- .crtc_goe = 0x80050108,
- .pll_freq = 57,
- .pixclk_divider = 4,
- .pixclk_divider_rotated = 4,
- .pixclk_src = CLK_SRC_XTAL,
- .sysclk_divider = 1,
- .sysclk_src = CLK_SRC_PLL,
- .crtc_ps1_active = 0x41060010,
-};
-
-static struct w100_gpio_regs e740_w100_gpio_info = {
- .init_data1 = 0x21002103,
- .gpio_dir1 = 0xffffdeff,
- .gpio_oe1 = 0x03c00643,
- .init_data2 = 0x003f003f,
- .gpio_dir2 = 0xffffffff,
- .gpio_oe2 = 0x000000ff,
-};
-
-static struct w100fb_mach_info e740_fb_info = {
- .modelist = &e740_lcd_mode,
- .num_modes = 1,
- .regs = &e740_lcd_regs,
- .gpio = &e740_w100_gpio_info,
- .xtal_freq = 14318000,
- .xtal_dbl = 1,
-};
-
-static struct resource e740_fb_resources[] = {
- [0] = {
- .start = 0x0c000000,
- .end = 0x0cffffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device e740_fb_device = {
- .name = "w100fb",
- .id = -1,
- .dev = {
- .platform_data = &e740_fb_info,
- },
- .num_resources = ARRAY_SIZE(e740_fb_resources),
- .resource = e740_fb_resources,
-};
-
-/* --------------------------- MFP Pin config -------------------------- */
-
-static unsigned long e740_pin_config[] __initdata = {
- /* Chip selects */
- GPIO15_nCS_1, /* CS1 - Flash */
- GPIO79_nCS_3, /* CS3 - IMAGEON */
- GPIO80_nCS_4, /* CS4 - TMIO */
-
- /* Clocks */
- GPIO12_32KHz,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
-
- /* TMIO controller */
- GPIO19_GPIO, /* t7l66xb #PCLR */
- GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
-
- /* UDC */
- GPIO13_GPIO,
- GPIO3_GPIO,
-
- /* IrDA */
- GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* Audio power control */
- GPIO16_GPIO, /* AC97 codec AVDD2 supply (analogue power) */
- GPIO40_GPIO, /* Mic amp power */
- GPIO41_GPIO, /* Headphone amp power */
-
- /* PC Card */
- GPIO8_GPIO, /* CD0 */
- GPIO44_GPIO, /* CD1 */
- GPIO11_GPIO, /* IRQ0 */
- GPIO6_GPIO, /* IRQ1 */
- GPIO27_GPIO, /* RST0 */
- GPIO24_GPIO, /* RST1 */
- GPIO20_GPIO, /* PWR0 */
- GPIO23_GPIO, /* PWR1 */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* wakeup */
- GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-/* -------------------- e740 t7l66xb parameters -------------------- */
-
-static struct t7l66xb_platform_data e740_t7l66xb_info = {
- .irq_base = IRQ_BOARD_START,
- .enable = &eseries_tmio_enable,
- .suspend = &eseries_tmio_suspend,
- .resume = &eseries_tmio_resume,
-};
-
-static struct platform_device e740_t7l66xb_device = {
- .name = "t7l66xb",
- .id = -1,
- .dev = {
- .platform_data = &e740_t7l66xb_info,
- },
- .num_resources = 2,
- .resource = eseries_tmio_resources,
-};
-
-static struct platform_device e740_audio_device = {
- .name = "e740-audio",
- .id = -1,
-};
-
-/* ----------------------------------------------------------------------- */
-
-static struct platform_device *e740_devices[] __initdata = {
- &e740_fb_device,
- &e740_t7l66xb_device,
- &e7xx_gpio_vbus,
- &e740_audio_device,
-};
-
-static void __init e740_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- eseries_register_clks();
- clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
- "UDCCLK", &pxa25x_device_udc.dev),
- eseries_get_tmio_gpios();
- gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
- platform_add_devices(ARRAY_AND_SIZE(e740_devices));
- pxa_set_ac97_info(NULL);
- pxa_set_ficp_info(&e7xx_ficp_platform_data);
-}
-
-MACHINE_START(E740, "Toshiba e740")
- /* Maintainer: Ian Molton (spyro@f2s.com) */
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = ESERIES_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .fixup = eseries_fixup,
- .init_machine = e740_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E750
-/* ---------------------- E750 LCD definitions -------------------- */
-
-static struct w100_gen_regs e750_lcd_regs = {
- .lcd_format = 0x00008003,
- .lcdd_cntl1 = 0x00000000,
- .lcdd_cntl2 = 0x0003ffff,
- .genlcd_cntl1 = 0x00fff003,
- .genlcd_cntl2 = 0x003c0f03,
- .genlcd_cntl3 = 0x000143aa,
-};
-
-static struct w100_mode e750_lcd_mode = {
- .xres = 240,
- .yres = 320,
- .left_margin = 21,
- .right_margin = 22,
- .upper_margin = 5,
- .lower_margin = 4,
- .crtc_ss = 0x80150014,
- .crtc_ls = 0x8014000d,
- .crtc_gs = 0xc1000005,
- .crtc_vpos_gs = 0x00020147,
- .crtc_rev = 0x0040010a,
- .crtc_dclk = 0xa1700030,
- .crtc_gclk = 0x80cc0015,
- .crtc_goe = 0x80cc0015,
- .crtc_ps1_active = 0x61060017,
- .pll_freq = 57,
- .pixclk_divider = 4,
- .pixclk_divider_rotated = 4,
- .pixclk_src = CLK_SRC_XTAL,
- .sysclk_divider = 1,
- .sysclk_src = CLK_SRC_PLL,
-};
-
-static struct w100_gpio_regs e750_w100_gpio_info = {
- .init_data1 = 0x01192f1b,
- .gpio_dir1 = 0xd5ffdeff,
- .gpio_oe1 = 0x000020bf,
- .init_data2 = 0x010f010f,
- .gpio_dir2 = 0xffffffff,
- .gpio_oe2 = 0x000001cf,
-};
-
-static struct w100fb_mach_info e750_fb_info = {
- .modelist = &e750_lcd_mode,
- .num_modes = 1,
- .regs = &e750_lcd_regs,
- .gpio = &e750_w100_gpio_info,
- .xtal_freq = 14318000,
- .xtal_dbl = 1,
-};
-
-static struct resource e750_fb_resources[] = {
- [0] = {
- .start = 0x0c000000,
- .end = 0x0cffffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device e750_fb_device = {
- .name = "w100fb",
- .id = -1,
- .dev = {
- .platform_data = &e750_fb_info,
- },
- .num_resources = ARRAY_SIZE(e750_fb_resources),
- .resource = e750_fb_resources,
-};
-
-/* -------------------- e750 MFP parameters -------------------- */
-
-static unsigned long e750_pin_config[] __initdata = {
- /* Chip selects */
- GPIO15_nCS_1, /* CS1 - Flash */
- GPIO79_nCS_3, /* CS3 - IMAGEON */
- GPIO80_nCS_4, /* CS4 - TMIO */
-
- /* Clocks */
- GPIO11_3_6MHz,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
-
- /* TMIO controller */
- GPIO19_GPIO, /* t7l66xb #PCLR */
- GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
-
- /* UDC */
- GPIO13_GPIO,
- GPIO3_GPIO,
-
- /* IrDA */
- GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* Audio power control */
- GPIO4_GPIO, /* Headphone amp power */
- GPIO7_GPIO, /* Speaker amp power */
- GPIO37_GPIO, /* Headphone detect */
-
- /* PC Card */
- GPIO8_GPIO, /* CD0 */
- GPIO44_GPIO, /* CD1 */
- /* GPIO11_GPIO, IRQ0 */
- GPIO6_GPIO, /* IRQ1 */
- GPIO27_GPIO, /* RST0 */
- GPIO24_GPIO, /* RST1 */
- GPIO20_GPIO, /* PWR0 */
- GPIO23_GPIO, /* PWR1 */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* wakeup */
- GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-/* ----------------- e750 tc6393xb parameters ------------------ */
-
-static struct tc6393xb_platform_data e750_tc6393xb_info = {
- .irq_base = IRQ_BOARD_START,
- .scr_pll2cr = 0x0cc1,
- .scr_gper = 0,
- .gpio_base = -1,
- .suspend = &eseries_tmio_suspend,
- .resume = &eseries_tmio_resume,
- .enable = &eseries_tmio_enable,
- .disable = &eseries_tmio_disable,
-};
-
-static struct platform_device e750_tc6393xb_device = {
- .name = "tc6393xb",
- .id = -1,
- .dev = {
- .platform_data = &e750_tc6393xb_info,
- },
- .num_resources = 2,
- .resource = eseries_tmio_resources,
-};
-
-static struct platform_device e750_audio_device = {
- .name = "e750-audio",
- .id = -1,
-};
-
-/* ------------------------------------------------------------- */
-
-static struct platform_device *e750_devices[] __initdata = {
- &e750_fb_device,
- &e750_tc6393xb_device,
- &e7xx_gpio_vbus,
- &e750_audio_device,
-};
-
-static void __init e750_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name,
- "GPIO11_CLK", NULL),
- eseries_get_tmio_gpios();
- gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
- platform_add_devices(ARRAY_AND_SIZE(e750_devices));
- pxa_set_ac97_info(NULL);
- pxa_set_ficp_info(&e7xx_ficp_platform_data);
-}
-
-MACHINE_START(E750, "Toshiba e750")
- /* Maintainer: Ian Molton (spyro@f2s.com) */
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = ESERIES_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .fixup = eseries_fixup,
- .init_machine = e750_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E800
-/* ------------------------ e800 LCD definitions ------------------------- */
-
-static unsigned long e800_pin_config[] __initdata = {
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* tc6393xb */
- GPIO11_3_6MHz,
-};
-
-static struct w100_gen_regs e800_lcd_regs = {
- .lcd_format = 0x00008003,
- .lcdd_cntl1 = 0x02a00000,
- .lcdd_cntl2 = 0x0003ffff,
- .genlcd_cntl1 = 0x000ff2a3,
- .genlcd_cntl2 = 0x000002a3,
- .genlcd_cntl3 = 0x000102aa,
-};
-
-static struct w100_mode e800_lcd_mode[2] = {
- [0] = {
- .xres = 480,
- .yres = 640,
- .left_margin = 52,
- .right_margin = 148,
- .upper_margin = 2,
- .lower_margin = 6,
- .crtc_ss = 0x80350034,
- .crtc_ls = 0x802b0026,
- .crtc_gs = 0x80160016,
- .crtc_vpos_gs = 0x00020003,
- .crtc_rev = 0x0040001d,
- .crtc_dclk = 0xe0000000,
- .crtc_gclk = 0x82a50049,
- .crtc_goe = 0x80ee001c,
- .crtc_ps1_active = 0x00000000,
- .pll_freq = 128,
- .pixclk_divider = 4,
- .pixclk_divider_rotated = 6,
- .pixclk_src = CLK_SRC_PLL,
- .sysclk_divider = 0,
- .sysclk_src = CLK_SRC_PLL,
- },
- [1] = {
- .xres = 240,
- .yres = 320,
- .left_margin = 15,
- .right_margin = 88,
- .upper_margin = 0,
- .lower_margin = 7,
- .crtc_ss = 0xd010000f,
- .crtc_ls = 0x80070003,
- .crtc_gs = 0x80000000,
- .crtc_vpos_gs = 0x01460147,
- .crtc_rev = 0x00400003,
- .crtc_dclk = 0xa1700030,
- .crtc_gclk = 0x814b0008,
- .crtc_goe = 0x80cc0015,
- .crtc_ps1_active = 0x00000000,
- .pll_freq = 100,
- .pixclk_divider = 6, /* Wince uses 14 which gives a */
- .pixclk_divider_rotated = 6, /* 7MHz Pclk. We use a 14MHz one */
- .pixclk_src = CLK_SRC_PLL,
- .sysclk_divider = 0,
- .sysclk_src = CLK_SRC_PLL,
- }
-};
-
-
-static struct w100_gpio_regs e800_w100_gpio_info = {
- .init_data1 = 0xc13fc019,
- .gpio_dir1 = 0x3e40df7f,
- .gpio_oe1 = 0x003c3000,
- .init_data2 = 0x00000000,
- .gpio_dir2 = 0x00000000,
- .gpio_oe2 = 0x00000000,
-};
-
-static struct w100_mem_info e800_w100_mem_info = {
- .ext_cntl = 0x09640011,
- .sdram_mode_reg = 0x00600021,
- .ext_timing_cntl = 0x10001545,
- .io_cntl = 0x7ddd7333,
- .size = 0x1fffff,
-};
-
-static void e800_tg_change(struct w100fb_par *par)
-{
- unsigned long tmp;
-
- tmp = w100fb_gpio_read(W100_GPIO_PORT_A);
- if (par->mode->xres == 480)
- tmp |= 0x100;
- else
- tmp &= ~0x100;
- w100fb_gpio_write(W100_GPIO_PORT_A, tmp);
-}
-
-static struct w100_tg_info e800_tg_info = {
- .change = e800_tg_change,
-};
-
-static struct w100fb_mach_info e800_fb_info = {
- .modelist = e800_lcd_mode,
- .num_modes = 2,
- .regs = &e800_lcd_regs,
- .gpio = &e800_w100_gpio_info,
- .mem = &e800_w100_mem_info,
- .tg = &e800_tg_info,
- .xtal_freq = 16000000,
-};
-
-static struct resource e800_fb_resources[] = {
- [0] = {
- .start = 0x0c000000,
- .end = 0x0cffffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device e800_fb_device = {
- .name = "w100fb",
- .id = -1,
- .dev = {
- .platform_data = &e800_fb_info,
- },
- .num_resources = ARRAY_SIZE(e800_fb_resources),
- .resource = e800_fb_resources,
-};
-
-/* --------------------------- UDC definitions --------------------------- */
-
-static struct gpiod_lookup_table e800_gpio_vbus_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_E800_USB_DISC,
- "vbus", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_E800_USB_PULLUP,
- "pullup", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct platform_device e800_gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-
-/* ----------------- e800 tc6393xb parameters ------------------ */
-
-static struct tc6393xb_platform_data e800_tc6393xb_info = {
- .irq_base = IRQ_BOARD_START,
- .scr_pll2cr = 0x0cc1,
- .scr_gper = 0,
- .gpio_base = -1,
- .suspend = &eseries_tmio_suspend,
- .resume = &eseries_tmio_resume,
- .enable = &eseries_tmio_enable,
- .disable = &eseries_tmio_disable,
-};
-
-static struct platform_device e800_tc6393xb_device = {
- .name = "tc6393xb",
- .id = -1,
- .dev = {
- .platform_data = &e800_tc6393xb_info,
- },
- .num_resources = 2,
- .resource = eseries_tmio_resources,
-};
-
-static struct platform_device e800_audio_device = {
- .name = "e800-audio",
- .id = -1,
-};
-
-/* ----------------------------------------------------------------------- */
-
-static struct platform_device *e800_devices[] __initdata = {
- &e800_fb_device,
- &e800_tc6393xb_device,
- &e800_gpio_vbus,
- &e800_audio_device,
-};
-
-static void __init e800_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(e800_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
- "GPIO11_CLK", NULL),
- eseries_get_tmio_gpios();
- gpiod_add_lookup_table(&e800_gpio_vbus_gpiod_table);
- platform_add_devices(ARRAY_AND_SIZE(e800_devices));
- pxa_set_ac97_info(NULL);
-}
-
-MACHINE_START(E800, "Toshiba e800")
- /* Maintainer: Ian Molton (spyro@f2s.com) */
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = ESERIES_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .fixup = eseries_fixup,
- .init_machine = e800_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
deleted file mode 100644
index eb85950e7c0e..000000000000
--- a/arch/arm/mach-pxa/ezx.c
+++ /dev/null
@@ -1,1255 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * ezx.c - Common code for the EZX platform.
- *
- * Copyright (C) 2005-2006 Harald Welte <laforge@openezx.org>,
- * 2007-2008 Daniel Ribeiro <drwyrm@gmail.com>,
- * 2007-2008 Stefan Schmidt <stefan@datenfreihafen.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio_keys.h>
-#include <linux/leds-lp3944.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa27x.h"
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/hardware.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/platform_data/media/camera-pxa.h>
-
-#include "devices.h"
-#include "generic.h"
-
-#define EZX_NR_IRQS (IRQ_BOARD_START + 24)
-
-#define GPIO12_A780_FLIP_LID 12
-#define GPIO15_A1200_FLIP_LID 15
-#define GPIO15_A910_FLIP_LID 15
-#define GPIO12_E680_LOCK_SWITCH 12
-#define GPIO15_E6_LOCK_SWITCH 15
-#define GPIO50_nCAM_EN 50
-#define GPIO19_GEN1_CAM_RST 19
-#define GPIO28_GEN2_CAM_RST 28
-
-static struct pwm_lookup ezx_pwm_lookup[] __maybe_unused = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78700,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data ezx_backlight_data = {
- .max_brightness = 1023,
- .dft_brightness = 1023,
-};
-
-static struct platform_device ezx_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &ezx_backlight_data,
- },
-};
-
-static struct pxafb_mode_info mode_ezx_old = {
- .pixclock = 150000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 10,
- .left_margin = 20,
- .right_margin = 10,
- .vsync_len = 2,
- .upper_margin = 3,
- .lower_margin = 2,
- .sync = 0,
-};
-
-static struct pxafb_mach_info ezx_fb_info_1 __maybe_unused = {
- .modes = &mode_ezx_old,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP,
-};
-
-static struct pxafb_mode_info mode_72r89803y01 = {
- .pixclock = 192308,
- .xres = 240,
- .yres = 320,
- .bpp = 32,
- .depth = 18,
- .hsync_len = 10,
- .left_margin = 20,
- .right_margin = 10,
- .vsync_len = 2,
- .upper_margin = 3,
- .lower_margin = 2,
- .sync = 0,
-};
-
-static struct pxafb_mach_info ezx_fb_info_2 __maybe_unused = {
- .modes = &mode_72r89803y01,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_18BPP,
-};
-
-static struct platform_device *ezx_devices[] __initdata __maybe_unused = {
- &ezx_backlight_device,
-};
-
-static unsigned long ezx_pin_config[] __initdata __maybe_unused = {
- /* PWM backlight */
- GPIO16_PWM0_OUT,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* PCAP SSP */
- GPIO29_SSP1_SCLK,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
- GPIO24_GPIO, /* pcap chip select */
- GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* pcap interrupt */
- GPIO4_GPIO | MFP_LPM_DRIVE_HIGH, /* WDI_AP */
- GPIO55_GPIO | MFP_LPM_DRIVE_HIGH, /* SYS_RESTART */
-
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO11_GPIO, /* mmc detect */
-
- /* usb to external transceiver */
- GPIO34_USB_P2_2,
- GPIO35_USB_P2_1,
- GPIO36_USB_P2_4,
- GPIO39_USB_P2_6,
- GPIO40_USB_P2_5,
- GPIO53_USB_P2_3,
-
- /* usb to Neptune GSM chip */
- GPIO30_USB_P3_2,
- GPIO31_USB_P3_6,
- GPIO90_USB_P3_5,
- GPIO91_USB_P3_1,
- GPIO56_USB_P3_4,
- GPIO113_USB_P3_3,
-};
-
-#if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_E680)
-static unsigned long gen1_pin_config[] __initdata = {
- /* flip / lockswitch */
- GPIO12_GPIO | WAKEUP_ON_EDGE_BOTH,
-
- /* bluetooth (bcm2035) */
- GPIO14_GPIO | WAKEUP_ON_EDGE_RISE, /* HOSTWAKE */
- GPIO48_GPIO, /* RESET */
- GPIO28_GPIO, /* WAKEUP */
-
- /* Neptune handshake */
- GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* BP_RDY */
- GPIO57_GPIO | MFP_LPM_DRIVE_HIGH, /* AP_RDY */
- GPIO13_GPIO | WAKEUP_ON_EDGE_BOTH, /* WDI */
- GPIO3_GPIO | WAKEUP_ON_EDGE_BOTH, /* WDI2 */
- GPIO82_GPIO | MFP_LPM_DRIVE_HIGH, /* RESET */
- GPIO99_GPIO | MFP_LPM_DRIVE_HIGH, /* TC_MM_EN */
-
- /* sound */
- GPIO52_SSP3_SCLK,
- GPIO83_SSP3_SFRM,
- GPIO81_SSP3_TXD,
- GPIO89_SSP3_RXD,
-
- /* ssp2 pins to in */
- GPIO22_GPIO, /* SSP2_SCLK */
- GPIO37_GPIO, /* SSP2_SFRM */
- GPIO38_GPIO, /* SSP2_TXD */
- GPIO88_GPIO, /* SSP2_RXD */
-
- /* camera */
- GPIO23_CIF_MCLK,
- GPIO54_CIF_PCLK,
- GPIO85_CIF_LV,
- GPIO84_CIF_FV,
- GPIO27_CIF_DD_0,
- GPIO114_CIF_DD_1,
- GPIO51_CIF_DD_2,
- GPIO115_CIF_DD_3,
- GPIO95_CIF_DD_4,
- GPIO94_CIF_DD_5,
- GPIO17_CIF_DD_6,
- GPIO108_CIF_DD_7,
- GPIO50_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_EN */
- GPIO19_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_RST */
-
- /* EMU */
- GPIO120_GPIO, /* EMU_MUX1 */
- GPIO119_GPIO, /* EMU_MUX2 */
- GPIO86_GPIO, /* SNP_INT_CTL */
- GPIO87_GPIO, /* SNP_INT_IN */
-};
-#endif
-
-#if defined(CONFIG_MACH_EZX_A1200) || defined(CONFIG_MACH_EZX_A910) || \
- defined(CONFIG_MACH_EZX_E2) || defined(CONFIG_MACH_EZX_E6)
-static unsigned long gen2_pin_config[] __initdata = {
- /* flip / lockswitch */
- GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH,
-
- /* EOC */
- GPIO10_GPIO | WAKEUP_ON_EDGE_RISE,
-
- /* bluetooth (bcm2045) */
- GPIO13_GPIO | WAKEUP_ON_EDGE_RISE, /* HOSTWAKE */
- GPIO37_GPIO, /* RESET */
- GPIO57_GPIO, /* WAKEUP */
-
- /* Neptune handshake */
- GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* BP_RDY */
- GPIO96_GPIO | MFP_LPM_DRIVE_HIGH, /* AP_RDY */
- GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* WDI */
- GPIO116_GPIO | MFP_LPM_DRIVE_HIGH, /* RESET */
- GPIO41_GPIO, /* BP_FLASH */
-
- /* sound */
- GPIO52_SSP3_SCLK,
- GPIO83_SSP3_SFRM,
- GPIO81_SSP3_TXD,
- GPIO82_SSP3_RXD,
-
- /* ssp2 pins to in */
- GPIO22_GPIO, /* SSP2_SCLK */
- GPIO14_GPIO, /* SSP2_SFRM */
- GPIO38_GPIO, /* SSP2_TXD */
- GPIO88_GPIO, /* SSP2_RXD */
-
- /* camera */
- GPIO23_CIF_MCLK,
- GPIO54_CIF_PCLK,
- GPIO85_CIF_LV,
- GPIO84_CIF_FV,
- GPIO27_CIF_DD_0,
- GPIO114_CIF_DD_1,
- GPIO51_CIF_DD_2,
- GPIO115_CIF_DD_3,
- GPIO95_CIF_DD_4,
- GPIO48_CIF_DD_5,
- GPIO93_CIF_DD_6,
- GPIO12_CIF_DD_7,
- GPIO50_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_EN */
- GPIO28_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_RST */
- GPIO17_GPIO, /* CAM_FLASH */
-};
-#endif
-
-#ifdef CONFIG_MACH_EZX_A780
-static unsigned long a780_pin_config[] __initdata = {
- /* keypad */
- GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
-
- /* attenuate sound */
- GPIO96_GPIO,
-};
-#endif
-
-#ifdef CONFIG_MACH_EZX_E680
-static unsigned long e680_pin_config[] __initdata = {
- /* keypad */
- GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO96_KP_DKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_DKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO98_KP_DKIN_5 | WAKEUP_ON_LEVEL_HIGH,
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
-
- /* MIDI */
- GPIO79_GPIO, /* VA_SEL_BUL */
- GPIO80_GPIO, /* FLT_SEL_BUL */
- GPIO78_GPIO, /* MIDI_RESET */
- GPIO33_GPIO, /* MIDI_CS */
- GPIO15_GPIO, /* MIDI_IRQ */
- GPIO49_GPIO, /* MIDI_NPWE */
- GPIO18_GPIO, /* MIDI_RDY */
-
- /* leds */
- GPIO46_GPIO,
- GPIO47_GPIO,
-};
-#endif
-
-#ifdef CONFIG_MACH_EZX_A1200
-static unsigned long a1200_pin_config[] __initdata = {
- /* keypad */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
-};
-#endif
-
-#ifdef CONFIG_MACH_EZX_A910
-static unsigned long a910_pin_config[] __initdata = {
- /* keypad */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
-
- /* WLAN */
- GPIO89_GPIO, /* RESET */
- GPIO33_GPIO, /* WAKEUP */
- GPIO94_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */
-
- /* MMC CS */
- GPIO20_GPIO,
-};
-#endif
-
-#ifdef CONFIG_MACH_EZX_E2
-static unsigned long e2_pin_config[] __initdata = {
- /* keypad */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
-};
-#endif
-
-#ifdef CONFIG_MACH_EZX_E6
-static unsigned long e6_pin_config[] __initdata = {
- /* keypad */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
-};
-#endif
-
-/* KEYPAD */
-#ifdef CONFIG_MACH_EZX_A780
-static const unsigned int a780_key_map[] = {
- KEY(0, 0, KEY_SEND),
- KEY(0, 1, KEY_BACK),
- KEY(0, 2, KEY_END),
- KEY(0, 3, KEY_PAGEUP),
- KEY(0, 4, KEY_UP),
-
- KEY(1, 0, KEY_NUMERIC_1),
- KEY(1, 1, KEY_NUMERIC_2),
- KEY(1, 2, KEY_NUMERIC_3),
- KEY(1, 3, KEY_SELECT),
- KEY(1, 4, KEY_KPENTER),
-
- KEY(2, 0, KEY_NUMERIC_4),
- KEY(2, 1, KEY_NUMERIC_5),
- KEY(2, 2, KEY_NUMERIC_6),
- KEY(2, 3, KEY_RECORD),
- KEY(2, 4, KEY_LEFT),
-
- KEY(3, 0, KEY_NUMERIC_7),
- KEY(3, 1, KEY_NUMERIC_8),
- KEY(3, 2, KEY_NUMERIC_9),
- KEY(3, 3, KEY_HOME),
- KEY(3, 4, KEY_RIGHT),
-
- KEY(4, 0, KEY_NUMERIC_STAR),
- KEY(4, 1, KEY_NUMERIC_0),
- KEY(4, 2, KEY_NUMERIC_POUND),
- KEY(4, 3, KEY_PAGEDOWN),
- KEY(4, 4, KEY_DOWN),
-};
-
-static struct matrix_keymap_data a780_matrix_keymap_data = {
- .keymap = a780_key_map,
- .keymap_size = ARRAY_SIZE(a780_key_map),
-};
-
-static struct pxa27x_keypad_platform_data a780_keypad_platform_data = {
- .matrix_key_rows = 5,
- .matrix_key_cols = 5,
- .matrix_keymap_data = &a780_matrix_keymap_data,
-
- .direct_key_map = { KEY_CAMERA },
- .direct_key_num = 1,
-
- .debounce_interval = 30,
-};
-#endif /* CONFIG_MACH_EZX_A780 */
-
-#ifdef CONFIG_MACH_EZX_E680
-static const unsigned int e680_key_map[] = {
- KEY(0, 0, KEY_UP),
- KEY(0, 1, KEY_RIGHT),
- KEY(0, 2, KEY_RESERVED),
- KEY(0, 3, KEY_SEND),
-
- KEY(1, 0, KEY_DOWN),
- KEY(1, 1, KEY_LEFT),
- KEY(1, 2, KEY_PAGEUP),
- KEY(1, 3, KEY_PAGEDOWN),
-
- KEY(2, 0, KEY_RESERVED),
- KEY(2, 1, KEY_RESERVED),
- KEY(2, 2, KEY_RESERVED),
- KEY(2, 3, KEY_KPENTER),
-};
-
-static struct matrix_keymap_data e680_matrix_keymap_data = {
- .keymap = e680_key_map,
- .keymap_size = ARRAY_SIZE(e680_key_map),
-};
-
-static struct pxa27x_keypad_platform_data e680_keypad_platform_data = {
- .matrix_key_rows = 3,
- .matrix_key_cols = 4,
- .matrix_keymap_data = &e680_matrix_keymap_data,
-
- .direct_key_map = {
- KEY_CAMERA,
- KEY_RESERVED,
- KEY_RESERVED,
- KEY_F1,
- KEY_CANCEL,
- KEY_F2,
- },
- .direct_key_num = 6,
-
- .debounce_interval = 30,
-};
-#endif /* CONFIG_MACH_EZX_E680 */
-
-#ifdef CONFIG_MACH_EZX_A1200
-static const unsigned int a1200_key_map[] = {
- KEY(0, 0, KEY_RESERVED),
- KEY(0, 1, KEY_RIGHT),
- KEY(0, 2, KEY_PAGEDOWN),
- KEY(0, 3, KEY_RESERVED),
- KEY(0, 4, KEY_RESERVED),
- KEY(0, 5, KEY_RESERVED),
-
- KEY(1, 0, KEY_RESERVED),
- KEY(1, 1, KEY_DOWN),
- KEY(1, 2, KEY_CAMERA),
- KEY(1, 3, KEY_RESERVED),
- KEY(1, 4, KEY_RESERVED),
- KEY(1, 5, KEY_RESERVED),
-
- KEY(2, 0, KEY_RESERVED),
- KEY(2, 1, KEY_KPENTER),
- KEY(2, 2, KEY_RECORD),
- KEY(2, 3, KEY_RESERVED),
- KEY(2, 4, KEY_RESERVED),
- KEY(2, 5, KEY_SELECT),
-
- KEY(3, 0, KEY_RESERVED),
- KEY(3, 1, KEY_UP),
- KEY(3, 2, KEY_SEND),
- KEY(3, 3, KEY_RESERVED),
- KEY(3, 4, KEY_RESERVED),
- KEY(3, 5, KEY_RESERVED),
-
- KEY(4, 0, KEY_RESERVED),
- KEY(4, 1, KEY_LEFT),
- KEY(4, 2, KEY_PAGEUP),
- KEY(4, 3, KEY_RESERVED),
- KEY(4, 4, KEY_RESERVED),
- KEY(4, 5, KEY_RESERVED),
-};
-
-static struct matrix_keymap_data a1200_matrix_keymap_data = {
- .keymap = a1200_key_map,
- .keymap_size = ARRAY_SIZE(a1200_key_map),
-};
-
-static struct pxa27x_keypad_platform_data a1200_keypad_platform_data = {
- .matrix_key_rows = 5,
- .matrix_key_cols = 6,
- .matrix_keymap_data = &a1200_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-#endif /* CONFIG_MACH_EZX_A1200 */
-
-#ifdef CONFIG_MACH_EZX_E6
-static const unsigned int e6_key_map[] = {
- KEY(0, 0, KEY_RESERVED),
- KEY(0, 1, KEY_RIGHT),
- KEY(0, 2, KEY_PAGEDOWN),
- KEY(0, 3, KEY_RESERVED),
- KEY(0, 4, KEY_RESERVED),
- KEY(0, 5, KEY_NEXTSONG),
-
- KEY(1, 0, KEY_RESERVED),
- KEY(1, 1, KEY_DOWN),
- KEY(1, 2, KEY_PROG1),
- KEY(1, 3, KEY_RESERVED),
- KEY(1, 4, KEY_RESERVED),
- KEY(1, 5, KEY_RESERVED),
-
- KEY(2, 0, KEY_RESERVED),
- KEY(2, 1, KEY_ENTER),
- KEY(2, 2, KEY_CAMERA),
- KEY(2, 3, KEY_RESERVED),
- KEY(2, 4, KEY_RESERVED),
- KEY(2, 5, KEY_WWW),
-
- KEY(3, 0, KEY_RESERVED),
- KEY(3, 1, KEY_UP),
- KEY(3, 2, KEY_SEND),
- KEY(3, 3, KEY_RESERVED),
- KEY(3, 4, KEY_RESERVED),
- KEY(3, 5, KEY_PLAYPAUSE),
-
- KEY(4, 0, KEY_RESERVED),
- KEY(4, 1, KEY_LEFT),
- KEY(4, 2, KEY_PAGEUP),
- KEY(4, 3, KEY_RESERVED),
- KEY(4, 4, KEY_RESERVED),
- KEY(4, 5, KEY_PREVIOUSSONG),
-};
-
-static struct matrix_keymap_data e6_keymap_data = {
- .keymap = e6_key_map,
- .keymap_size = ARRAY_SIZE(e6_key_map),
-};
-
-static struct pxa27x_keypad_platform_data e6_keypad_platform_data = {
- .matrix_key_rows = 5,
- .matrix_key_cols = 6,
- .matrix_keymap_data = &e6_keymap_data,
-
- .debounce_interval = 30,
-};
-#endif /* CONFIG_MACH_EZX_E6 */
-
-#ifdef CONFIG_MACH_EZX_A910
-static const unsigned int a910_key_map[] = {
- KEY(0, 0, KEY_NUMERIC_6),
- KEY(0, 1, KEY_RIGHT),
- KEY(0, 2, KEY_PAGEDOWN),
- KEY(0, 3, KEY_KPENTER),
- KEY(0, 4, KEY_NUMERIC_5),
- KEY(0, 5, KEY_CAMERA),
-
- KEY(1, 0, KEY_NUMERIC_8),
- KEY(1, 1, KEY_DOWN),
- KEY(1, 2, KEY_RESERVED),
- KEY(1, 3, KEY_F1), /* Left SoftKey */
- KEY(1, 4, KEY_NUMERIC_STAR),
- KEY(1, 5, KEY_RESERVED),
-
- KEY(2, 0, KEY_NUMERIC_7),
- KEY(2, 1, KEY_NUMERIC_9),
- KEY(2, 2, KEY_RECORD),
- KEY(2, 3, KEY_F2), /* Right SoftKey */
- KEY(2, 4, KEY_BACK),
- KEY(2, 5, KEY_SELECT),
-
- KEY(3, 0, KEY_NUMERIC_2),
- KEY(3, 1, KEY_UP),
- KEY(3, 2, KEY_SEND),
- KEY(3, 3, KEY_NUMERIC_0),
- KEY(3, 4, KEY_NUMERIC_1),
- KEY(3, 5, KEY_RECORD),
-
- KEY(4, 0, KEY_NUMERIC_4),
- KEY(4, 1, KEY_LEFT),
- KEY(4, 2, KEY_PAGEUP),
- KEY(4, 3, KEY_NUMERIC_POUND),
- KEY(4, 4, KEY_NUMERIC_3),
- KEY(4, 5, KEY_RESERVED),
-};
-
-static struct matrix_keymap_data a910_matrix_keymap_data = {
- .keymap = a910_key_map,
- .keymap_size = ARRAY_SIZE(a910_key_map),
-};
-
-static struct pxa27x_keypad_platform_data a910_keypad_platform_data = {
- .matrix_key_rows = 5,
- .matrix_key_cols = 6,
- .matrix_keymap_data = &a910_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-#endif /* CONFIG_MACH_EZX_A910 */
-
-#ifdef CONFIG_MACH_EZX_E2
-static const unsigned int e2_key_map[] = {
- KEY(0, 0, KEY_NUMERIC_6),
- KEY(0, 1, KEY_RIGHT),
- KEY(0, 2, KEY_NUMERIC_9),
- KEY(0, 3, KEY_NEXTSONG),
- KEY(0, 4, KEY_NUMERIC_5),
- KEY(0, 5, KEY_F1), /* Left SoftKey */
-
- KEY(1, 0, KEY_NUMERIC_8),
- KEY(1, 1, KEY_DOWN),
- KEY(1, 2, KEY_RESERVED),
- KEY(1, 3, KEY_PAGEUP),
- KEY(1, 4, KEY_NUMERIC_STAR),
- KEY(1, 5, KEY_F2), /* Right SoftKey */
-
- KEY(2, 0, KEY_NUMERIC_7),
- KEY(2, 1, KEY_KPENTER),
- KEY(2, 2, KEY_RECORD),
- KEY(2, 3, KEY_PAGEDOWN),
- KEY(2, 4, KEY_BACK),
- KEY(2, 5, KEY_NUMERIC_0),
-
- KEY(3, 0, KEY_NUMERIC_2),
- KEY(3, 1, KEY_UP),
- KEY(3, 2, KEY_SEND),
- KEY(3, 3, KEY_PLAYPAUSE),
- KEY(3, 4, KEY_NUMERIC_1),
- KEY(3, 5, KEY_SOUND), /* Music SoftKey */
-
- KEY(4, 0, KEY_NUMERIC_4),
- KEY(4, 1, KEY_LEFT),
- KEY(4, 2, KEY_NUMERIC_POUND),
- KEY(4, 3, KEY_PREVIOUSSONG),
- KEY(4, 4, KEY_NUMERIC_3),
- KEY(4, 5, KEY_RESERVED),
-};
-
-static struct matrix_keymap_data e2_matrix_keymap_data = {
- .keymap = e2_key_map,
- .keymap_size = ARRAY_SIZE(e2_key_map),
-};
-
-static struct pxa27x_keypad_platform_data e2_keypad_platform_data = {
- .matrix_key_rows = 5,
- .matrix_key_cols = 6,
- .matrix_keymap_data = &e2_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-#endif /* CONFIG_MACH_EZX_E2 */
-
-#if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_A910)
-/* camera */
-static struct regulator_consumer_supply camera_regulator_supplies[] = {
- REGULATOR_SUPPLY("vdd", "0-005d"),
-};
-
-static struct regulator_init_data camera_regulator_initdata = {
- .consumer_supplies = camera_regulator_supplies,
- .num_consumer_supplies = ARRAY_SIZE(camera_regulator_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config camera_regulator_config = {
- .supply_name = "camera_vdd",
- .microvolts = 2800000,
- .init_data = &camera_regulator_initdata,
-};
-
-static struct platform_device camera_supply_regulator_device = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &camera_regulator_config,
- },
-};
-
-static struct gpiod_lookup_table camera_supply_gpiod_table = {
- .dev_id = "reg-fixed-voltage.1",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO50_nCAM_EN,
- NULL, GPIO_ACTIVE_LOW),
- { },
- },
-};
-#endif
-
-#ifdef CONFIG_MACH_EZX_A780
-/* gpio_keys */
-static struct gpio_keys_button a780_buttons[] = {
- [0] = {
- .code = SW_LID,
- .gpio = GPIO12_A780_FLIP_LID,
- .active_low = 0,
- .desc = "A780 flip lid",
- .type = EV_SW,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data a780_gpio_keys_platform_data = {
- .buttons = a780_buttons,
- .nbuttons = ARRAY_SIZE(a780_buttons),
-};
-
-static struct platform_device a780_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &a780_gpio_keys_platform_data,
- },
-};
-
-/* camera */
-static int a780_camera_reset(struct device *dev)
-{
- gpio_set_value(GPIO19_GEN1_CAM_RST, 0);
- msleep(10);
- gpio_set_value(GPIO19_GEN1_CAM_RST, 1);
-
- return 0;
-}
-
-static int a780_camera_init(void)
-{
- int err;
-
- /*
- * GPIO50_nCAM_EN is active low
- * GPIO19_GEN1_CAM_RST is active on rising edge
- */
- err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST");
- if (err) {
- pr_err("%s: Failed to request CAM_RST\n", __func__);
- return err;
- }
-
- gpio_direction_output(GPIO19_GEN1_CAM_RST, 0);
- a780_camera_reset(NULL);
-
- return 0;
-}
-
-struct pxacamera_platform_data a780_pxacamera_platform_data = {
- .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
- PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN |
- PXA_CAMERA_PCP,
- .mclk_10khz = 5000,
- .sensor_i2c_adapter_id = 0,
- .sensor_i2c_address = 0x5d,
-};
-
-static struct i2c_board_info a780_i2c_board_info[] = {
- {
- I2C_BOARD_INFO("mt9m111", 0x5d),
- },
-};
-
-static struct platform_device *a780_devices[] __initdata = {
- &a780_gpio_keys,
- &camera_supply_regulator_device,
-};
-
-static void __init a780_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(a780_i2c_board_info));
-
- pxa_set_fb_info(NULL, &ezx_fb_info_1);
-
- pxa_set_keypad_info(&a780_keypad_platform_data);
-
- if (a780_camera_init() == 0)
- pxa_set_camera_info(&a780_pxacamera_platform_data);
-
- gpiod_add_lookup_table(&camera_supply_gpiod_table);
- pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
- platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
- platform_add_devices(ARRAY_AND_SIZE(a780_devices));
- regulator_has_full_constraints();
-}
-
-MACHINE_START(EZX_A780, "Motorola EZX A780")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = EZX_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = a780_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_EZX_E680
-/* gpio_keys */
-static struct gpio_keys_button e680_buttons[] = {
- [0] = {
- .code = KEY_SCREENLOCK,
- .gpio = GPIO12_E680_LOCK_SWITCH,
- .active_low = 0,
- .desc = "E680 lock switch",
- .type = EV_KEY,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data e680_gpio_keys_platform_data = {
- .buttons = e680_buttons,
- .nbuttons = ARRAY_SIZE(e680_buttons),
-};
-
-static struct platform_device e680_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &e680_gpio_keys_platform_data,
- },
-};
-
-static struct i2c_board_info __initdata e680_i2c_board_info[] = {
- { I2C_BOARD_INFO("tea5767", 0x81) },
-};
-
-static struct platform_device *e680_devices[] __initdata = {
- &e680_gpio_keys,
-};
-
-static void __init e680_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info));
-
- pxa_set_fb_info(NULL, &ezx_fb_info_1);
-
- pxa_set_keypad_info(&e680_keypad_platform_data);
-
- pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
- platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
- platform_add_devices(ARRAY_AND_SIZE(e680_devices));
-}
-
-MACHINE_START(EZX_E680, "Motorola EZX E680")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = EZX_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = e680_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_EZX_A1200
-/* gpio_keys */
-static struct gpio_keys_button a1200_buttons[] = {
- [0] = {
- .code = SW_LID,
- .gpio = GPIO15_A1200_FLIP_LID,
- .active_low = 0,
- .desc = "A1200 flip lid",
- .type = EV_SW,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data a1200_gpio_keys_platform_data = {
- .buttons = a1200_buttons,
- .nbuttons = ARRAY_SIZE(a1200_buttons),
-};
-
-static struct platform_device a1200_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &a1200_gpio_keys_platform_data,
- },
-};
-
-static struct i2c_board_info __initdata a1200_i2c_board_info[] = {
- { I2C_BOARD_INFO("tea5767", 0x81) },
-};
-
-static struct platform_device *a1200_devices[] __initdata = {
- &a1200_gpio_keys,
-};
-
-static void __init a1200_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info));
-
- pxa_set_fb_info(NULL, &ezx_fb_info_2);
-
- pxa_set_keypad_info(&a1200_keypad_platform_data);
-
- pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
- platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
- platform_add_devices(ARRAY_AND_SIZE(a1200_devices));
-}
-
-MACHINE_START(EZX_A1200, "Motorola EZX A1200")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = EZX_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = a1200_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_EZX_A910
-/* gpio_keys */
-static struct gpio_keys_button a910_buttons[] = {
- [0] = {
- .code = SW_LID,
- .gpio = GPIO15_A910_FLIP_LID,
- .active_low = 0,
- .desc = "A910 flip lid",
- .type = EV_SW,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data a910_gpio_keys_platform_data = {
- .buttons = a910_buttons,
- .nbuttons = ARRAY_SIZE(a910_buttons),
-};
-
-static struct platform_device a910_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &a910_gpio_keys_platform_data,
- },
-};
-
-/* camera */
-static int a910_camera_reset(struct device *dev)
-{
- gpio_set_value(GPIO28_GEN2_CAM_RST, 0);
- msleep(10);
- gpio_set_value(GPIO28_GEN2_CAM_RST, 1);
-
- return 0;
-}
-
-static int a910_camera_init(void)
-{
- int err;
-
- /*
- * GPIO50_nCAM_EN is active low
- * GPIO28_GEN2_CAM_RST is active on rising edge
- */
- err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST");
- if (err) {
- pr_err("%s: Failed to request CAM_RST\n", __func__);
- return err;
- }
-
- gpio_direction_output(GPIO28_GEN2_CAM_RST, 0);
- a910_camera_reset(NULL);
-
- return 0;
-}
-
-struct pxacamera_platform_data a910_pxacamera_platform_data = {
- .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
- PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN |
- PXA_CAMERA_PCP,
- .mclk_10khz = 5000,
- .sensor_i2c_adapter_id = 0,
- .sensor_i2c_address = 0x5d,
-};
-
-/* leds-lp3944 */
-static struct lp3944_platform_data a910_lp3944_leds = {
- .leds_size = LP3944_LEDS_MAX,
- .leds = {
- [0] = {
- .name = "a910:red:",
- .status = LP3944_LED_STATUS_OFF,
- .type = LP3944_LED_TYPE_LED,
- },
- [1] = {
- .name = "a910:green:",
- .status = LP3944_LED_STATUS_OFF,
- .type = LP3944_LED_TYPE_LED,
- },
- [2] {
- .name = "a910:blue:",
- .status = LP3944_LED_STATUS_OFF,
- .type = LP3944_LED_TYPE_LED,
- },
- /* Leds 3 and 4 are used as display power switches */
- [3] = {
- .name = "a910::cli_display",
- .status = LP3944_LED_STATUS_OFF,
- .type = LP3944_LED_TYPE_LED_INVERTED
- },
- [4] = {
- .name = "a910::main_display",
- .status = LP3944_LED_STATUS_ON,
- .type = LP3944_LED_TYPE_LED_INVERTED
- },
- [5] = { .type = LP3944_LED_TYPE_NONE },
- [6] = {
- .name = "a910::torch",
- .status = LP3944_LED_STATUS_OFF,
- .type = LP3944_LED_TYPE_LED,
- },
- [7] = {
- .name = "a910::flash",
- .status = LP3944_LED_STATUS_OFF,
- .type = LP3944_LED_TYPE_LED_INVERTED,
- },
- },
-};
-
-static struct i2c_board_info __initdata a910_i2c_board_info[] = {
- {
- I2C_BOARD_INFO("lp3944", 0x60),
- .platform_data = &a910_lp3944_leds,
- },
- {
- I2C_BOARD_INFO("mt9m111", 0x5d),
- },
-};
-
-static struct platform_device *a910_devices[] __initdata = {
- &a910_gpio_keys,
- &camera_supply_regulator_device,
-};
-
-static void __init a910_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info));
-
- pxa_set_fb_info(NULL, &ezx_fb_info_2);
-
- pxa_set_keypad_info(&a910_keypad_platform_data);
-
- if (a910_camera_init() == 0)
- pxa_set_camera_info(&a910_pxacamera_platform_data);
-
- gpiod_add_lookup_table(&camera_supply_gpiod_table);
- pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
- platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
- platform_add_devices(ARRAY_AND_SIZE(a910_devices));
- regulator_has_full_constraints();
-}
-
-MACHINE_START(EZX_A910, "Motorola EZX A910")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = EZX_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = a910_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_EZX_E6
-/* gpio_keys */
-static struct gpio_keys_button e6_buttons[] = {
- [0] = {
- .code = KEY_SCREENLOCK,
- .gpio = GPIO15_E6_LOCK_SWITCH,
- .active_low = 0,
- .desc = "E6 lock switch",
- .type = EV_KEY,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data e6_gpio_keys_platform_data = {
- .buttons = e6_buttons,
- .nbuttons = ARRAY_SIZE(e6_buttons),
-};
-
-static struct platform_device e6_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &e6_gpio_keys_platform_data,
- },
-};
-
-static struct i2c_board_info __initdata e6_i2c_board_info[] = {
- { I2C_BOARD_INFO("tea5767", 0x81) },
-};
-
-static struct platform_device *e6_devices[] __initdata = {
- &e6_gpio_keys,
-};
-
-static void __init e6_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info));
-
- pxa_set_fb_info(NULL, &ezx_fb_info_2);
-
- pxa_set_keypad_info(&e6_keypad_platform_data);
-
- pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
- platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
- platform_add_devices(ARRAY_AND_SIZE(e6_devices));
-}
-
-MACHINE_START(EZX_E6, "Motorola EZX E6")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = EZX_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = e6_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_EZX_E2
-static struct i2c_board_info __initdata e2_i2c_board_info[] = {
- { I2C_BOARD_INFO("tea5767", 0x81) },
-};
-
-static struct platform_device *e2_devices[] __initdata = {
-};
-
-static void __init e2_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config));
- pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info));
-
- pxa_set_fb_info(NULL, &ezx_fb_info_2);
-
- pxa_set_keypad_info(&e2_keypad_platform_data);
-
- pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
- platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
- platform_add_devices(ARRAY_AND_SIZE(e2_devices));
-}
-
-MACHINE_START(EZX_E2, "Motorola EZX E2")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = EZX_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = e2_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index ab7cdffd7ea8..02fdde7e3e34 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -17,15 +17,18 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/soc/pxa/cpu.h>
+#include <linux/soc/pxa/smemc.h>
+#include <linux/clk/pxa.h>
-#include <mach/hardware.h>
#include <asm/mach/map.h>
#include <asm/mach-types.h>
-#include <mach/irqs.h>
-#include <mach/reset.h>
-#include <mach/smemc.h>
-#include <mach/pxa3xx-regs.h>
+#include "addr-map.h"
+#include "irqs.h"
+#include "reset.h"
+#include "smemc.h"
+#include "pxa3xx-regs.h"
#include "generic.h"
#include <clocksource/pxa.h>
@@ -46,28 +49,47 @@ void clear_reset_status(unsigned int mask)
void __init pxa_timer_init(void)
{
if (cpu_is_pxa25x())
- pxa25x_clocks_init();
+ pxa25x_clocks_init(io_p2v(0x41300000));
if (cpu_is_pxa27x())
- pxa27x_clocks_init();
+ pxa27x_clocks_init(io_p2v(0x41300000));
if (cpu_is_pxa3xx())
- pxa3xx_clocks_init();
+ pxa3xx_clocks_init(io_p2v(0x41340000), io_p2v(0x41350000));
pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));
}
-/*
- * Get the clock frequency as reflected by CCCR and the turbo flag.
- * We assume these values have been applied via a fcs.
- * If info is not 0 we also display the current settings.
- */
-unsigned int get_clk_frequency_khz(int info)
+void pxa_smemc_set_pcmcia_timing(int sock, u32 mcmem, u32 mcatt, u32 mcio)
{
- if (cpu_is_pxa25x())
- return pxa25x_get_clk_frequency_khz(info);
- else if (cpu_is_pxa27x())
- return pxa27x_get_clk_frequency_khz(info);
- return 0;
+ __raw_writel(mcmem, MCMEM(sock));
+ __raw_writel(mcatt, MCATT(sock));
+ __raw_writel(mcio, MCIO(sock));
+}
+EXPORT_SYMBOL_GPL(pxa_smemc_set_pcmcia_timing);
+
+void pxa_smemc_set_pcmcia_socket(int nr)
+{
+ switch (nr) {
+ case 0:
+ __raw_writel(0, MECR);
+ break;
+ case 1:
+ /*
+ * We have at least one socket, so set MECR:CIT
+ * (Card Is There)
+ */
+ __raw_writel(MECR_CIT, MECR);
+ break;
+ case 2:
+ /* Set CIT and MECR:NOS (Number Of Sockets) */
+ __raw_writel(MECR_CIT | MECR_NOS, MECR);
+ break;
+ }
+}
+EXPORT_SYMBOL_GPL(pxa_smemc_set_pcmcia_socket);
+
+void __iomem *pxa_smemc_get_mdrefr(void)
+{
+ return MDREFR;
}
-EXPORT_SYMBOL(get_clk_frequency_khz);
/*
* Intel PXA2xx internal register mapping.
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 3b7873f8e1f8..7bb1499de4c5 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -10,7 +10,6 @@
struct irq_data;
-extern unsigned int get_clk_frequency_khz(int info);
extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *,
unsigned int));
extern void __init pxa_map_io(void);
@@ -23,19 +22,16 @@ extern void pxa_timer_init(void);
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
#define pxa25x_handle_irq icip_handle_irq
-extern int __init pxa25x_clocks_init(void);
extern void __init pxa25x_init_irq(void);
extern void __init pxa25x_map_io(void);
extern void __init pxa26x_init_irq(void);
#define pxa27x_handle_irq ichp_handle_irq
-extern int __init pxa27x_clocks_init(void);
extern unsigned pxa27x_get_clk_frequency_khz(int);
extern void __init pxa27x_init_irq(void);
extern void __init pxa27x_map_io(void);
#define pxa3xx_handle_irq ichp_handle_irq
-extern int __init pxa3xx_clocks_init(void);
extern void __init pxa3xx_init_irq(void);
extern void __init pxa3xx_map_io(void);
@@ -71,8 +67,3 @@ extern unsigned pxa25x_get_clk_frequency_khz(int);
#define pxa27x_get_clk_frequency_khz(x) (0)
#endif
-#ifdef CONFIG_PXA3xx
-extern unsigned pxa3xx_get_clk_frequency_khz(int);
-#else
-#define pxa3xx_get_clk_frequency_khz(x) (0)
-#endif
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 49dd618b10f7..72b08a9bf0fd 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -28,7 +28,6 @@
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <linux/sizes.h>
diff --git a/arch/arm/mach-pxa/gumstix.h b/arch/arm/mach-pxa/gumstix.h
index 470250cdee16..9005b3c0aabd 100644
--- a/arch/arm/mach-pxa/gumstix.h
+++ b/arch/arm/mach-pxa/gumstix.h
@@ -3,7 +3,7 @@
* arch/arm/mach-pxa/include/mach/gumstix.h
*/
-#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
/* BTRESET - Reset line to Bluetooth module, active low signal. */
#define GPIO_GUMSTIX_BTRESET 7
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
deleted file mode 100644
index ece1e71c90a9..000000000000
--- a/arch/arm/mach-pxa/h5000.c
+++ /dev/null
@@ -1,210 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Hardware definitions for HP iPAQ h5xxx Handheld Computers
- *
- * Copyright 2000-2003 Hewlett-Packard Company.
- * Copyright 2002 Jamey Hicks <jamey.hicks@hp.com>
- * Copyright 2004-2005 Phil Blundell <pb@handhelds.org>
- * Copyright 2007-2008 Anton Vorontsov <cbouatmailru@gmail.com>
- *
- * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
- * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
- * FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- * Author: Jamey Hicks.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/irq.h>
-
-#include "pxa25x.h"
-#include "h5000.h"
-#include "udc.h"
-#include <mach/smemc.h>
-
-#include "generic.h"
-
-/*
- * Flash
- */
-
-static struct mtd_partition h5000_flash0_partitions[] = {
- {
- .name = "bootldr",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE,
- },
- {
- .name = "root",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct mtd_partition h5000_flash1_partitions[] = {
- {
- .name = "second root",
- .size = SZ_16M - 0x00040000,
- .offset = 0,
- },
- {
- .name = "asset",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE,
- },
-};
-
-static struct physmap_flash_data h5000_flash0_data = {
- .width = 4,
- .parts = h5000_flash0_partitions,
- .nr_parts = ARRAY_SIZE(h5000_flash0_partitions),
-};
-
-static struct physmap_flash_data h5000_flash1_data = {
- .width = 4,
- .parts = h5000_flash1_partitions,
- .nr_parts = ARRAY_SIZE(h5000_flash1_partitions),
-};
-
-static struct resource h5000_flash0_resources = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-};
-
-static struct resource h5000_flash1_resources = {
- .start = PXA_CS0_PHYS + SZ_32M,
- .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-};
-
-static struct platform_device h5000_flash[] = {
- {
- .name = "physmap-flash",
- .id = 0,
- .resource = &h5000_flash0_resources,
- .num_resources = 1,
- .dev = {
- .platform_data = &h5000_flash0_data,
- },
- },
- {
- .name = "physmap-flash",
- .id = 1,
- .resource = &h5000_flash1_resources,
- .num_resources = 1,
- .dev = {
- .platform_data = &h5000_flash1_data,
- },
- },
-};
-
-/*
- * USB Device Controller
- */
-
-static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = {
- .gpio_pullup = H5000_GPIO_USB_PULLUP,
-};
-
-/*
- * GPIO setup
- */
-
-static unsigned long h5000_pin_config[] __initdata = {
- /* Crystal and Clock Signals */
- GPIO12_32KHz,
-
- /* SDRAM and Static Memory I/O Signals */
- GPIO15_nCS_1,
- GPIO78_nCS_2,
- GPIO79_nCS_3,
- GPIO80_nCS_4,
-
- /* FFUART */
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
- GPIO36_FFUART_DCD,
- GPIO37_FFUART_DSR,
- GPIO38_FFUART_RI,
- GPIO39_FFUART_TXD,
- GPIO40_FFUART_DTR,
- GPIO41_FFUART_RTS,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* SSP1 */
- GPIO23_SSP1_SCLK,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
-
- /* I2S */
- GPIO28_I2S_BITCLK_OUT,
- GPIO29_I2S_SDATA_IN,
- GPIO30_I2S_SDATA_OUT,
- GPIO31_I2S_SYNC,
- GPIO32_I2S_SYSCLK,
-};
-
-/*
- * Localbus setup:
- * CS0: Flash;
- * CS1: MediaQ chip, select 16-bit bus and vlio;
- * CS5: SAMCOP.
- */
-
-static void fix_msc(void)
-{
- __raw_writel(0x129c24f2, MSC0);
- __raw_writel(0x7ff424fa, MSC1);
- __raw_writel(0x7ff47ff4, MSC2);
-
- __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR);
-}
-
-/*
- * Platform devices
- */
-
-static struct platform_device *devices[] __initdata = {
- &h5000_flash[0],
- &h5000_flash[1],
-};
-
-static void __init h5000_init(void)
-{
- fix_msc();
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- pxa_set_udc_info(&h5000_udc_mach_info);
- platform_add_devices(ARRAY_AND_SIZE(devices));
-}
-
-MACHINE_START(H5400, "HP iPAQ H5000")
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = h5000_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/h5000.h b/arch/arm/mach-pxa/h5000.h
deleted file mode 100644
index 58687e94a0c7..000000000000
--- a/arch/arm/mach-pxa/h5000.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Hardware definitions for HP iPAQ h5xxx Handheld Computers
- *
- * Copyright(20)02 Hewlett-Packard Company.
- *
- * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
- * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
- * FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- * Author: Jamey Hicks
- */
-
-#ifndef __ASM_ARCH_H5000_H
-#define __ASM_ARCH_H5000_H
-
-#include "mfp-pxa25x.h"
-
-/*
- * CPU GPIOs
- */
-
-#define H5000_GPIO_POWER_BUTTON (0)
-#define H5000_GPIO_RESET_BUTTON_N (1)
-#define H5000_GPIO_OPT_INT (2)
-#define H5000_GPIO_BACKUP_POWER (3)
-#define H5000_GPIO_ACTION_BUTTON (4)
-#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */
-/* 6 not connected */
-#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */
-/* 8 not connected */
-#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */
-#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */
-#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */
-/*(12) not connected */
-#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */
-#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */
-/*(15) is CS1# */
-/*(16) not connected */
-/*(17) not connected */
-/*(18) is pcmcia ready */
-/*(19) is dreq1 */
-/*(20) is dreq0 */
-#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */
-/*(22) is not connected */
-#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */
-#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */
-#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */
-#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */
-/*(27) not connected */
-#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */
-#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */
-#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */
-#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */
-#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */
-/*(33) is CS5# */
-#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */
-#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */
-#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */
-#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */
-#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */
-#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */
-#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */
-#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */
-
-#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */
-#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */
-#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */
-#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */
-
-#define H5000_GPIO_IRDA_RXD (46)
-#define H5000_GPIO_IRDA_TXD (47)
-
-#define H5000_GPIO_POE_N (48) /* used for pcmcia */
-#define H5000_GPIO_PWE_N (49) /* used for pcmcia */
-#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */
-#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */
-#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */
-#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */
-#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */
-#define H5000_GPIO_PREG_N (55) /* used for pcmcia */
-#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */
-#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */
-
-#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */
-/*(59) not connected */
-#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */
-#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */
-#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */
-/*(63) is not connected */
-#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */
-#define H5000_GPIO_CHG_EN (65) /* to sc801 en */
-#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */
-#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */
-#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */
-/*(69) is not connected */
-#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */
-#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71)
-#define H5000_GPIO_BT_M_RESET (72)
-#define H5000_GPIO_STD_CHG_RATE (73)
-#define H5000_GPIO_SD_WP_N (74)
-#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */
-#define H5000_GPIO_HEADPHONE_DETECT (76)
-#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */
-/*(78) is CS2# */
-/*(79) is CS3# */
-/*(80) is CS4# */
-
-#endif /* __ASM_ARCH_H5000_H */
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
deleted file mode 100644
index 469ffeec6da5..000000000000
--- a/arch/arm/mach-pxa/himalaya.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/himalaya.c
- *
- * Hardware definitions for the HTC Himalaya
- *
- * Based on 2.6.21-hh20's himalaya.c and himalaya_lcd.c
- *
- * Copyright (c) 2008 Zbynek Michl <Zbynek.Michl@seznam.cz>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/fb.h>
-#include <linux/platform_device.h>
-
-#include <video/w100fb.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa25x.h"
-
-#include "generic.h"
-
-/* ---------------------- Himalaya LCD definitions -------------------- */
-
-static struct w100_gen_regs himalaya_lcd_regs = {
- .lcd_format = 0x00000003,
- .lcdd_cntl1 = 0x00000000,
- .lcdd_cntl2 = 0x0003ffff,
- .genlcd_cntl1 = 0x00fff003,
- .genlcd_cntl2 = 0x00000003,
- .genlcd_cntl3 = 0x000102aa,
-};
-
-static struct w100_mode himalaya4_lcd_mode = {
- .xres = 240,
- .yres = 320,
- .left_margin = 0,
- .right_margin = 31,
- .upper_margin = 15,
- .lower_margin = 0,
- .crtc_ss = 0x80150014,
- .crtc_ls = 0xa0fb00f7,
- .crtc_gs = 0xc0080007,
- .crtc_vpos_gs = 0x00080007,
- .crtc_rev = 0x0000000a,
- .crtc_dclk = 0x81700030,
- .crtc_gclk = 0x8015010f,
- .crtc_goe = 0x00000000,
- .pll_freq = 80,
- .pixclk_divider = 15,
- .pixclk_divider_rotated = 15,
- .pixclk_src = CLK_SRC_PLL,
- .sysclk_divider = 0,
- .sysclk_src = CLK_SRC_PLL,
-};
-
-static struct w100_mode himalaya6_lcd_mode = {
- .xres = 240,
- .yres = 320,
- .left_margin = 9,
- .right_margin = 8,
- .upper_margin = 5,
- .lower_margin = 4,
- .crtc_ss = 0x80150014,
- .crtc_ls = 0xa0fb00f7,
- .crtc_gs = 0xc0080007,
- .crtc_vpos_gs = 0x00080007,
- .crtc_rev = 0x0000000a,
- .crtc_dclk = 0xa1700030,
- .crtc_gclk = 0x8015010f,
- .crtc_goe = 0x00000000,
- .pll_freq = 95,
- .pixclk_divider = 0xb,
- .pixclk_divider_rotated = 4,
- .pixclk_src = CLK_SRC_PLL,
- .sysclk_divider = 1,
- .sysclk_src = CLK_SRC_PLL,
-};
-
-static struct w100_gpio_regs himalaya_w100_gpio_info = {
- .init_data1 = 0xffff0000, /* GPIO_DATA */
- .gpio_dir1 = 0x00000000, /* GPIO_CNTL1 */
- .gpio_oe1 = 0x003c0000, /* GPIO_CNTL2 */
- .init_data2 = 0x00000000, /* GPIO_DATA2 */
- .gpio_dir2 = 0x00000000, /* GPIO_CNTL3 */
- .gpio_oe2 = 0x00000000, /* GPIO_CNTL4 */
-};
-
-static struct w100fb_mach_info himalaya_fb_info = {
- .num_modes = 1,
- .regs = &himalaya_lcd_regs,
- .gpio = &himalaya_w100_gpio_info,
- .xtal_freq = 16000000,
-};
-
-static struct resource himalaya_fb_resources[] = {
- [0] = {
- .start = 0x08000000,
- .end = 0x08ffffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device himalaya_fb_device = {
- .name = "w100fb",
- .id = -1,
- .dev = {
- .platform_data = &himalaya_fb_info,
- },
- .num_resources = ARRAY_SIZE(himalaya_fb_resources),
- .resource = himalaya_fb_resources,
-};
-
-/* ----------------------------------------------------------------------- */
-
-static struct platform_device *devices[] __initdata = {
- &himalaya_fb_device,
-};
-
-static void __init himalaya_lcd_init(void)
-{
- int himalaya_boardid;
-
- himalaya_boardid = 0x4; /* hardcoded (detection needs ASIC3 functions) */
- printk(KERN_INFO "himalaya LCD Driver init. boardid=%d\n",
- himalaya_boardid);
-
- switch (himalaya_boardid) {
- case 0x4:
- himalaya_fb_info.modelist = &himalaya4_lcd_mode;
- break;
- case 0x6:
- himalaya_fb_info.modelist = &himalaya6_lcd_mode;
- break;
- default:
- printk(KERN_INFO "himalaya lcd_init: unknown boardid=%d. Using 0x4\n",
- himalaya_boardid);
- himalaya_fb_info.modelist = &himalaya4_lcd_mode;
- }
-}
-
-static void __init himalaya_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- himalaya_lcd_init();
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-
-MACHINE_START(HIMALAYA, "HTC Himalaya")
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_machine = himalaya_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
deleted file mode 100644
index e1870fbb19e7..000000000000
--- a/arch/arm/mach-pxa/hx4700.c
+++ /dev/null
@@ -1,928 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for HP iPAQ hx4700 PDAs.
- *
- * Copyright (c) 2008-2009 Philipp Zabel
- *
- * Based on code:
- * Copyright (c) 2004 Hewlett-Packard Company.
- * Copyright (c) 2005 SDG Systems, LLC
- * Copyright (c) 2006 Anton Vorontsov <cbou@mail.ru>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/input/navpoint.h>
-#include <linux/lcd.h>
-#include <linux/mfd/asic3.h>
-#include <linux/mtd/physmap.h>
-#include <linux/pda_power.h>
-#include <linux/platform_data/gpio-htc-egpio.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/gpio-regulator.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/max1586.h>
-#include <linux/spi/ads7846.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa27x.h"
-#include <mach/hx4700.h>
-#include <linux/platform_data/irda-pxaficp.h>
-
-#include <sound/ak4641.h>
-#include <video/platform_lcd.h>
-#include <video/w100fb.h>
-
-#include "devices.h"
-#include "generic.h"
-#include "udc.h"
-
-/* Physical address space information */
-
-#define ATI_W3220_PHYS PXA_CS2_PHYS /* ATI Imageon 3220 Graphics */
-#define ASIC3_PHYS PXA_CS3_PHYS
-#define ASIC3_SD_PHYS (PXA_CS3_PHYS + 0x02000000)
-
-static unsigned long hx4700_pin_config[] __initdata = {
-
- /* SDRAM and Static Memory I/O Signals */
- GPIO20_nSDCS_2,
- GPIO21_nSDCS_3,
- GPIO15_nCS_1,
- GPIO78_nCS_2, /* W3220 */
- GPIO79_nCS_3, /* ASIC3 */
- GPIO80_nCS_4,
- GPIO33_nCS_5, /* EGPIO, WLAN */
-
- /* PC CARD */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO54_nPCE_2,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
- GPIO85_nPCE_1,
- GPIO104_PSKTSEL,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* FFUART (RS-232) */
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
- GPIO36_FFUART_DCD,
- GPIO37_FFUART_DSR,
- GPIO38_FFUART_RI,
- GPIO39_FFUART_TXD,
- GPIO40_FFUART_DTR,
- GPIO41_FFUART_RTS,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD_LPM_LOW,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS_LPM_LOW,
-
- /* STUART (IRDA) */
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* PWM 1 (Backlight) */
- GPIO17_PWM1_OUT,
-
- /* I2S */
- GPIO28_I2S_BITCLK_OUT,
- GPIO29_I2S_SDATA_IN,
- GPIO30_I2S_SDATA_OUT,
- GPIO31_I2S_SYNC,
- GPIO113_I2S_SYSCLK,
-
- /* SSP 1 (NavPoint) */
- GPIO23_SSP1_SCLK_IN,
- GPIO24_SSP1_SFRM,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
-
- /* SSP 2 (TSC2046) */
- GPIO19_SSP2_SCLK,
- GPIO86_SSP2_RXD,
- GPIO87_SSP2_TXD,
- GPIO88_GPIO | MFP_LPM_DRIVE_HIGH, /* TSC2046_CS */
-
- /* BQ24022 Regulator */
- GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT, /* BQ24022_nCHARGE_EN */
- GPIO96_GPIO | MFP_LPM_KEEP_OUTPUT, /* BQ24022_ISET2 */
-
- /* HX4700 specific input GPIOs */
- GPIO12_GPIO | WAKEUP_ON_EDGE_RISE, /* ASIC3_IRQ */
- GPIO13_GPIO, /* W3220_IRQ */
- GPIO14_GPIO, /* nWLAN_IRQ */
-
- /* HX4700 specific output GPIOs */
- GPIO61_GPIO | MFP_LPM_DRIVE_HIGH, /* W3220_nRESET */
- GPIO71_GPIO | MFP_LPM_DRIVE_HIGH, /* ASIC3_nRESET */
- GPIO81_GPIO | MFP_LPM_DRIVE_HIGH, /* CPU_GP_nRESET */
- GPIO116_GPIO | MFP_LPM_DRIVE_HIGH, /* CPU_HW_nRESET */
- GPIO102_GPIO | MFP_LPM_DRIVE_LOW, /* SYNAPTICS_POWER_ON */
-
- GPIO10_GPIO, /* GSM_IRQ */
- GPIO13_GPIO, /* CPLD_IRQ */
- GPIO107_GPIO, /* DS1WM_IRQ */
- GPIO108_GPIO, /* GSM_READY */
- GPIO58_GPIO, /* TSC2046_nPENIRQ */
- GPIO66_GPIO, /* nSDIO_IRQ */
-};
-
-/*
- * IRDA
- */
-
-static struct pxaficp_platform_data ficp_info = {
- .gpio_pwdown = GPIO105_HX4700_nIR_ON,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-/*
- * GPIO Keys
- */
-
-#define INIT_KEY(_code, _gpio, _active_low, _desc) \
- { \
- .code = KEY_##_code, \
- .gpio = _gpio, \
- .active_low = _active_low, \
- .desc = _desc, \
- .type = EV_KEY, \
- .wakeup = 1, \
- }
-
-static struct gpio_keys_button gpio_keys_buttons[] = {
- INIT_KEY(POWER, GPIO0_HX4700_nKEY_POWER, 1, "Power button"),
- INIT_KEY(MAIL, GPIO94_HX4700_KEY_MAIL, 0, "Mail button"),
- INIT_KEY(ADDRESSBOOK, GPIO99_HX4700_KEY_CONTACTS,0, "Contacts button"),
- INIT_KEY(RECORD, GPIOD6_nKEY_RECORD, 1, "Record button"),
- INIT_KEY(CALENDAR, GPIOD1_nKEY_CALENDAR, 1, "Calendar button"),
- INIT_KEY(HOMEPAGE, GPIOD3_nKEY_HOME, 1, "Home button"),
-};
-
-static struct gpio_keys_platform_data gpio_keys_data = {
- .buttons = gpio_keys_buttons,
- .nbuttons = ARRAY_SIZE(gpio_keys_buttons),
-};
-
-static struct platform_device gpio_keys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &gpio_keys_data,
- },
- .id = -1,
-};
-
-/*
- * Synaptics NavPoint connected to SSP1
- */
-
-static struct navpoint_platform_data navpoint_platform_data = {
- .port = 1,
- .gpio = GPIO102_HX4700_SYNAPTICS_POWER_ON,
-};
-
-static struct platform_device navpoint = {
- .name = "navpoint",
- .id = -1,
- .dev = {
- .platform_data = &navpoint_platform_data,
- },
-};
-
-/*
- * ASIC3
- */
-
-static u16 asic3_gpio_config[] = {
- /* ASIC3 GPIO banks A and B along with some of C and D
- implement the buffering for the CF slot. */
- ASIC3_CONFIG_GPIO(0, 1, 1, 0),
- ASIC3_CONFIG_GPIO(1, 1, 1, 0),
- ASIC3_CONFIG_GPIO(2, 1, 1, 0),
- ASIC3_CONFIG_GPIO(3, 1, 1, 0),
- ASIC3_CONFIG_GPIO(4, 1, 1, 0),
- ASIC3_CONFIG_GPIO(5, 1, 1, 0),
- ASIC3_CONFIG_GPIO(6, 1, 1, 0),
- ASIC3_CONFIG_GPIO(7, 1, 1, 0),
- ASIC3_CONFIG_GPIO(8, 1, 1, 0),
- ASIC3_CONFIG_GPIO(9, 1, 1, 0),
- ASIC3_CONFIG_GPIO(10, 1, 1, 0),
- ASIC3_CONFIG_GPIO(11, 1, 1, 0),
- ASIC3_CONFIG_GPIO(12, 1, 1, 0),
- ASIC3_CONFIG_GPIO(13, 1, 1, 0),
- ASIC3_CONFIG_GPIO(14, 1, 1, 0),
- ASIC3_CONFIG_GPIO(15, 1, 1, 0),
-
- ASIC3_CONFIG_GPIO(16, 1, 1, 0),
- ASIC3_CONFIG_GPIO(17, 1, 1, 0),
- ASIC3_CONFIG_GPIO(18, 1, 1, 0),
- ASIC3_CONFIG_GPIO(19, 1, 1, 0),
- ASIC3_CONFIG_GPIO(20, 1, 1, 0),
- ASIC3_CONFIG_GPIO(21, 1, 1, 0),
- ASIC3_CONFIG_GPIO(22, 1, 1, 0),
- ASIC3_CONFIG_GPIO(23, 1, 1, 0),
- ASIC3_CONFIG_GPIO(24, 1, 1, 0),
- ASIC3_CONFIG_GPIO(25, 1, 1, 0),
- ASIC3_CONFIG_GPIO(26, 1, 1, 0),
- ASIC3_CONFIG_GPIO(27, 1, 1, 0),
- ASIC3_CONFIG_GPIO(28, 1, 1, 0),
- ASIC3_CONFIG_GPIO(29, 1, 1, 0),
- ASIC3_CONFIG_GPIO(30, 1, 1, 0),
- ASIC3_CONFIG_GPIO(31, 1, 1, 0),
-
- /* GPIOC - CF, LEDs, SD */
- ASIC3_GPIOC0_LED0, /* red */
- ASIC3_GPIOC1_LED1, /* green */
- ASIC3_GPIOC2_LED2, /* blue */
- ASIC3_GPIOC5_nCIOW,
- ASIC3_GPIOC6_nCIOR,
- ASIC3_GPIOC7_nPCE_1,
- ASIC3_GPIOC8_nPCE_2,
- ASIC3_GPIOC9_nPOE,
- ASIC3_GPIOC10_nPWE,
- ASIC3_GPIOC11_PSKTSEL,
- ASIC3_GPIOC12_nPREG,
- ASIC3_GPIOC13_nPWAIT,
- ASIC3_GPIOC14_nPIOIS16,
- ASIC3_GPIOC15_nPIOR,
-
- /* GPIOD: input GPIOs, CF */
- ASIC3_GPIOD4_CF_nCD,
- ASIC3_GPIOD11_nCIOIS16,
- ASIC3_GPIOD12_nCWAIT,
- ASIC3_GPIOD15_nPIOW,
-};
-
-static struct asic3_led asic3_leds[ASIC3_NUM_LEDS] = {
- [0] = {
- .name = "hx4700:amber",
- .default_trigger = "ds2760-battery.0-charging-blink-full-solid",
- },
- [1] = {
- .name = "hx4700:green",
- .default_trigger = "unused",
- },
- [2] = {
- .name = "hx4700:blue",
- .default_trigger = "hx4700-radio",
- },
-};
-
-static struct resource asic3_resources[] = {
- /* GPIO part */
- [0] = DEFINE_RES_MEM(ASIC3_PHYS, ASIC3_MAP_SIZE_16BIT),
- [1] = DEFINE_RES_IRQ(PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ)),
- /* SD part */
- [2] = DEFINE_RES_MEM(ASIC3_SD_PHYS, ASIC3_MAP_SIZE_16BIT),
- [3] = DEFINE_RES_IRQ(PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ)),
-};
-
-static struct asic3_platform_data asic3_platform_data = {
- .gpio_config = asic3_gpio_config,
- .gpio_config_num = ARRAY_SIZE(asic3_gpio_config),
- .irq_base = IRQ_BOARD_START,
- .gpio_base = HX4700_ASIC3_GPIO_BASE,
- .clock_rate = 4000000,
- .leds = asic3_leds,
-};
-
-static struct platform_device asic3 = {
- .name = "asic3",
- .id = -1,
- .resource = asic3_resources,
- .num_resources = ARRAY_SIZE(asic3_resources),
- .dev = {
- .platform_data = &asic3_platform_data,
- },
-};
-
-/*
- * EGPIO
- */
-
-static struct resource egpio_resources[] = {
- [0] = DEFINE_RES_MEM(PXA_CS5_PHYS, 0x4),
-};
-
-static struct htc_egpio_chip egpio_chips[] = {
- [0] = {
- .reg_start = 0,
- .gpio_base = HX4700_EGPIO_BASE,
- .num_gpios = 8,
- .direction = HTC_EGPIO_OUTPUT,
- },
-};
-
-static struct htc_egpio_platform_data egpio_info = {
- .reg_width = 16,
- .bus_width = 16,
- .chip = egpio_chips,
- .num_chips = ARRAY_SIZE(egpio_chips),
-};
-
-static struct platform_device egpio = {
- .name = "htc-egpio",
- .id = -1,
- .resource = egpio_resources,
- .num_resources = ARRAY_SIZE(egpio_resources),
- .dev = {
- .platform_data = &egpio_info,
- },
-};
-
-/*
- * LCD - Sony display connected to ATI Imageon w3220
- */
-
-static void sony_lcd_init(void)
-{
- gpio_set_value(GPIO84_HX4700_LCD_SQN, 1);
- gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
- gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
- gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 0);
- gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
- mdelay(10);
- gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
- gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
- mdelay(20);
-
- gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1);
- mdelay(5);
- gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 1);
-
- /* FIXME: init w3220 registers here */
-
- mdelay(5);
- gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 1);
- mdelay(10);
- gpio_set_value(GPIO62_HX4700_LCD_nRESET, 1);
- mdelay(10);
- gpio_set_value(GPIO59_HX4700_LCD_PC1, 1);
- mdelay(10);
- gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 1);
-}
-
-static void sony_lcd_off(void)
-{
- gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
- gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
- mdelay(10);
- gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 0);
- mdelay(10);
- gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
- mdelay(10);
- gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
-}
-
-#ifdef CONFIG_PM
-static void w3220_lcd_suspend(struct w100fb_par *wfb)
-{
- sony_lcd_off();
-}
-
-static void w3220_lcd_resume(struct w100fb_par *wfb)
-{
- sony_lcd_init();
-}
-#else
-#define w3220_lcd_resume NULL
-#define w3220_lcd_suspend NULL
-#endif
-
-static struct w100_tg_info w3220_tg_info = {
- .suspend = w3220_lcd_suspend,
- .resume = w3220_lcd_resume,
-};
-
-/* W3220_VGA QVGA */
-static struct w100_gen_regs w3220_regs = {
- .lcd_format = 0x00000003,
- .lcdd_cntl1 = 0x00000000,
- .lcdd_cntl2 = 0x0003ffff,
- .genlcd_cntl1 = 0x00abf003, /* 0x00fff003 */
- .genlcd_cntl2 = 0x00000003,
- .genlcd_cntl3 = 0x000102aa,
-};
-
-static struct w100_mode w3220_modes[] = {
-{
- .xres = 480,
- .yres = 640,
- .left_margin = 15,
- .right_margin = 16,
- .upper_margin = 8,
- .lower_margin = 7,
- .crtc_ss = 0x00000000,
- .crtc_ls = 0xa1ff01f9, /* 0x21ff01f9 */
- .crtc_gs = 0xc0000000, /* 0x40000000 */
- .crtc_vpos_gs = 0x0000028f,
- .crtc_ps1_active = 0x00000000, /* 0x41060010 */
- .crtc_rev = 0,
- .crtc_dclk = 0x80000000,
- .crtc_gclk = 0x040a0104,
- .crtc_goe = 0,
- .pll_freq = 95,
- .pixclk_divider = 4,
- .pixclk_divider_rotated = 4,
- .pixclk_src = CLK_SRC_PLL,
- .sysclk_divider = 0,
- .sysclk_src = CLK_SRC_PLL,
-},
-{
- .xres = 240,
- .yres = 320,
- .left_margin = 9,
- .right_margin = 8,
- .upper_margin = 5,
- .lower_margin = 4,
- .crtc_ss = 0x80150014,
- .crtc_ls = 0xa0fb00f7,
- .crtc_gs = 0xc0080007,
- .crtc_vpos_gs = 0x00080007,
- .crtc_rev = 0x0000000a,
- .crtc_dclk = 0x81700030,
- .crtc_gclk = 0x8015010f,
- .crtc_goe = 0x00000000,
- .pll_freq = 95,
- .pixclk_divider = 4,
- .pixclk_divider_rotated = 4,
- .pixclk_src = CLK_SRC_PLL,
- .sysclk_divider = 0,
- .sysclk_src = CLK_SRC_PLL,
-},
-};
-
-struct w100_mem_info w3220_mem_info = {
- .ext_cntl = 0x09640011,
- .sdram_mode_reg = 0x00600021,
- .ext_timing_cntl = 0x1a001545, /* 0x15001545 */
- .io_cntl = 0x7ddd7333,
- .size = 0x1fffff,
-};
-
-struct w100_bm_mem_info w3220_bm_mem_info = {
- .ext_mem_bw = 0x50413e01,
- .offset = 0,
- .ext_timing_ctl = 0x00043f7f,
- .ext_cntl = 0x00000010,
- .mode_reg = 0x00250000,
- .io_cntl = 0x0fff0000,
- .config = 0x08301480,
-};
-
-static struct w100_gpio_regs w3220_gpio_info = {
- .init_data1 = 0xdfe00100, /* GPIO_DATA */
- .gpio_dir1 = 0xffff0000, /* GPIO_CNTL1 */
- .gpio_oe1 = 0x00000000, /* GPIO_CNTL2 */
- .init_data2 = 0x00000000, /* GPIO_DATA2 */
- .gpio_dir2 = 0x00000000, /* GPIO_CNTL3 */
- .gpio_oe2 = 0x00000000, /* GPIO_CNTL4 */
-};
-
-static struct w100fb_mach_info w3220_info = {
- .tg = &w3220_tg_info,
- .mem = &w3220_mem_info,
- .bm_mem = &w3220_bm_mem_info,
- .gpio = &w3220_gpio_info,
- .regs = &w3220_regs,
- .modelist = w3220_modes,
- .num_modes = 2,
- .xtal_freq = 16000000,
-};
-
-static struct resource w3220_resources[] = {
- [0] = DEFINE_RES_MEM(ATI_W3220_PHYS, SZ_16M),
-};
-
-static struct platform_device w3220 = {
- .name = "w100fb",
- .id = -1,
- .dev = {
- .platform_data = &w3220_info,
- },
- .num_resources = ARRAY_SIZE(w3220_resources),
- .resource = w3220_resources,
-};
-
-static void hx4700_lcd_set_power(struct plat_lcd_data *pd, unsigned int power)
-{
- if (power)
- sony_lcd_init();
- else
- sony_lcd_off();
-}
-
-static struct plat_lcd_data hx4700_lcd_data = {
- .set_power = hx4700_lcd_set_power,
-};
-
-static struct platform_device hx4700_lcd = {
- .name = "platform-lcd",
- .id = -1,
- .dev = {
- .platform_data = &hx4700_lcd_data,
- .parent = &w3220.dev,
- },
-};
-
-/*
- * Backlight
- */
-
-static struct platform_pwm_backlight_data backlight_data = {
- .max_brightness = 200,
- .dft_brightness = 100,
-};
-
-static struct platform_device backlight = {
- .name = "pwm-backlight",
- .id = -1,
- .dev = {
- .parent = &pxa27x_device_pwm1.dev,
- .platform_data = &backlight_data,
- },
-};
-
-static struct pwm_lookup hx4700_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.1", 0, "pwm-backlight", NULL,
- 30923, PWM_POLARITY_NORMAL),
-};
-
-/*
- * USB "Transceiver"
- */
-
-static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- /* This GPIO is on ASIC3 */
- GPIO_LOOKUP("asic3",
- /* Convert to a local offset on the ASIC3 */
- GPIOD14_nUSBC_DETECT - HX4700_ASIC3_GPIO_BASE,
- "vbus", GPIO_ACTIVE_LOW),
- /* This one is on the primary SOC GPIO */
- GPIO_LOOKUP("gpio-pxa", GPIO76_HX4700_USBC_PUEN,
- "pullup", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-static struct pxa2xx_udc_mach_info hx4700_udc_info;
-
-/*
- * Touchscreen - TSC2046 connected to SSP2
- */
-
-static const struct ads7846_platform_data tsc2046_info = {
- .model = 7846,
- .vref_delay_usecs = 100,
- .pressure_max = 1024,
- .debounce_max = 10,
- .debounce_tol = 3,
- .debounce_rep = 1,
- .gpio_pendown = GPIO58_HX4700_TSC2046_nPENIRQ,
-};
-
-static struct pxa2xx_spi_chip tsc2046_chip = {
- .tx_threshold = 1,
- .rx_threshold = 2,
- .timeout = 64,
-};
-
-static struct spi_board_info tsc2046_board_info[] __initdata = {
- {
- .modalias = "ads7846",
- .bus_num = 2,
- .max_speed_hz = 2600000, /* 100 kHz sample rate */
- .irq = PXA_GPIO_TO_IRQ(GPIO58_HX4700_TSC2046_nPENIRQ),
- .platform_data = &tsc2046_info,
- .controller_data = &tsc2046_chip,
- },
-};
-
-static struct pxa2xx_spi_controller pxa_ssp2_master_info = {
- .num_chipselect = 1,
- .enable_dma = 1,
-};
-
-static struct gpiod_lookup_table pxa_ssp2_gpio_table = {
- .dev_id = "pxa2xx-spi.2",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", GPIO88_HX4700_TSC2046_CS, "cs", 0, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/*
- * External power
- */
-
-static int power_supply_init(struct device *dev)
-{
- return gpio_request(GPIOD9_nAC_IN, "AC charger detect");
-}
-
-static int hx4700_is_ac_online(void)
-{
- return !gpio_get_value(GPIOD9_nAC_IN);
-}
-
-static void power_supply_exit(struct device *dev)
-{
- gpio_free(GPIOD9_nAC_IN);
-}
-
-static char *hx4700_supplicants[] = {
- "ds2760-battery.0", "backup-battery"
-};
-
-static struct pda_power_pdata power_supply_info = {
- .init = power_supply_init,
- .is_ac_online = hx4700_is_ac_online,
- .exit = power_supply_exit,
- .supplied_to = hx4700_supplicants,
- .num_supplicants = ARRAY_SIZE(hx4700_supplicants),
-};
-
-static struct resource power_supply_resources[] = {
- [0] = DEFINE_RES_NAMED(PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN), 1, "ac",
- IORESOURCE_IRQ |
- IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE),
- [1] = DEFINE_RES_NAMED(PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT), 1, "usb",
- IORESOURCE_IRQ |
- IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE),
-};
-
-static struct platform_device power_supply = {
- .name = "pda-power",
- .id = -1,
- .dev = {
- .platform_data = &power_supply_info,
- },
- .resource = power_supply_resources,
- .num_resources = ARRAY_SIZE(power_supply_resources),
-};
-
-/*
- * Battery charger
- */
-
-static struct regulator_consumer_supply bq24022_consumers[] = {
- REGULATOR_SUPPLY("vbus_draw", NULL),
- REGULATOR_SUPPLY("ac_draw", NULL),
-};
-
-static struct regulator_init_data bq24022_init_data = {
- .constraints = {
- .max_uA = 500000,
- .valid_ops_mask = REGULATOR_CHANGE_CURRENT|REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(bq24022_consumers),
- .consumer_supplies = bq24022_consumers,
-};
-
-static enum gpiod_flags bq24022_gpiod_gflags[] = { GPIOD_OUT_LOW };
-
-static struct gpio_regulator_state bq24022_states[] = {
- { .value = 100000, .gpios = (0 << 0) },
- { .value = 500000, .gpios = (1 << 0) },
-};
-
-static struct gpio_regulator_config bq24022_info = {
- .supply_name = "bq24022",
-
- .enabled_at_boot = 0,
-
- .gflags = bq24022_gpiod_gflags,
- .ngpios = ARRAY_SIZE(bq24022_gpiod_gflags),
-
- .states = bq24022_states,
- .nr_states = ARRAY_SIZE(bq24022_states),
-
- .type = REGULATOR_CURRENT,
- .init_data = &bq24022_init_data,
-};
-
-static struct platform_device bq24022 = {
- .name = "gpio-regulator",
- .id = -1,
- .dev = {
- .platform_data = &bq24022_info,
- },
-};
-
-static struct gpiod_lookup_table bq24022_gpiod_table = {
- .dev_id = "gpio-regulator",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO96_HX4700_BQ24022_ISET2,
- NULL, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO72_HX4700_BQ24022_nCHARGE_EN,
- "enable", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/*
- * StrataFlash
- */
-
-static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
-{
- gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
-}
-
-static struct resource strataflash_resource[] = {
- [0] = DEFINE_RES_MEM(PXA_CS0_PHYS, SZ_64M),
- [1] = DEFINE_RES_MEM(PXA_CS0_PHYS + SZ_64M, SZ_64M),
-};
-
-static struct physmap_flash_data strataflash_data = {
- .width = 4,
- .set_vpp = hx4700_set_vpp,
-};
-
-static struct platform_device strataflash = {
- .name = "physmap-flash",
- .id = -1,
- .resource = strataflash_resource,
- .num_resources = ARRAY_SIZE(strataflash_resource),
- .dev = {
- .platform_data = &strataflash_data,
- },
-};
-
-/*
- * Maxim MAX1587A on PI2C
- */
-
-static struct regulator_consumer_supply max1587a_consumer =
- REGULATOR_SUPPLY("vcc_core", NULL);
-
-static struct regulator_init_data max1587a_v3_info = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 900000,
- .max_uV = 1705000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &max1587a_consumer,
-};
-
-static struct max1586_subdev_data max1587a_subdev = {
- .name = "vcc_core",
- .id = MAX1586_V3,
- .platform_data = &max1587a_v3_info,
-};
-
-static struct max1586_platform_data max1587a_info = {
- .num_subdevs = 1,
- .subdevs = &max1587a_subdev,
- .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
-};
-
-static struct i2c_board_info __initdata pi2c_board_info[] = {
- {
- I2C_BOARD_INFO("max1586", 0x14),
- .platform_data = &max1587a_info,
- },
-};
-
-/*
- * Asahi Kasei AK4641 on I2C
- */
-
-static struct ak4641_platform_data ak4641_info = {
- .gpio_power = GPIO27_HX4700_CODEC_ON,
- .gpio_npdn = GPIO109_HX4700_CODEC_nPDN,
-};
-
-static struct i2c_board_info i2c_board_info[] __initdata = {
- {
- I2C_BOARD_INFO("ak4641", 0x12),
- .platform_data = &ak4641_info,
- },
-};
-
-static struct platform_device audio = {
- .name = "hx4700-audio",
- .id = -1,
-};
-
-
-/*
- * Platform devices
- */
-
-static struct platform_device *devices[] __initdata = {
- &asic3,
- &gpio_keys,
- &navpoint,
- &backlight,
- &w3220,
- &hx4700_lcd,
- &egpio,
- &bq24022,
- &gpio_vbus,
- &power_supply,
- &strataflash,
- &audio,
-};
-
-static struct gpio global_gpios[] = {
- { GPIO12_HX4700_ASIC3_IRQ, GPIOF_IN, "ASIC3_IRQ" },
- { GPIO13_HX4700_W3220_IRQ, GPIOF_IN, "W3220_IRQ" },
- { GPIO14_HX4700_nWLAN_IRQ, GPIOF_IN, "WLAN_IRQ" },
- { GPIO59_HX4700_LCD_PC1, GPIOF_OUT_INIT_HIGH, "LCD_PC1" },
- { GPIO62_HX4700_LCD_nRESET, GPIOF_OUT_INIT_HIGH, "LCD_RESET" },
- { GPIO70_HX4700_LCD_SLIN1, GPIOF_OUT_INIT_HIGH, "LCD_SLIN1" },
- { GPIO84_HX4700_LCD_SQN, GPIOF_OUT_INIT_HIGH, "LCD_SQN" },
- { GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
- { GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
- { GPIO32_HX4700_RS232_ON, GPIOF_OUT_INIT_HIGH, "RS232_ON" },
- { GPIO61_HX4700_W3220_nRESET, GPIOF_OUT_INIT_HIGH, "W3220_nRESET" },
- { GPIO71_HX4700_ASIC3_nRESET, GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
- { GPIO81_HX4700_CPU_GP_nRESET, GPIOF_OUT_INIT_HIGH, "CPU_GP_nRESET" },
- { GPIO82_HX4700_EUART_RESET, GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
- { GPIO116_HX4700_CPU_HW_nRESET, GPIOF_OUT_INIT_HIGH, "CPU_HW_nRESET" },
-};
-
-static void __init hx4700_init(void)
-{
- int ret;
-
- PCFR = PCFR_GPR_EN | PCFR_OPDE;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
- gpio_set_wake(GPIO12_HX4700_ASIC3_IRQ, 1);
- ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
- if (ret)
- pr_err ("hx4700: Failed to request GPIOs.\n");
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- gpiod_add_lookup_table(&bq24022_gpiod_table);
- gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
- platform_add_devices(devices, ARRAY_SIZE(devices));
- pwm_add_table(hx4700_pwm_lookup, ARRAY_SIZE(hx4700_pwm_lookup));
-
- pxa_set_ficp_info(&ficp_info);
- pxa27x_set_i2c_power_info(NULL);
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(i2c_board_info));
- i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
- gpiod_add_lookup_table(&pxa_ssp2_gpio_table);
- pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
- spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
-
- gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 0);
- mdelay(10);
- gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 1);
- mdelay(10);
-
- pxa_set_udc_info(&hx4700_udc_info);
- regulator_has_full_constraints();
-}
-
-MACHINE_START(H4700, "HP iPAQ HX4700")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = HX4700_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_machine = hx4700_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
deleted file mode 100644
index 753fe166ab68..000000000000
--- a/arch/arm/mach-pxa/icontrol.c
+++ /dev/null
@@ -1,218 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/icontrol.c
- *
- * Support for the iControl and SafeTcam platforms from TMT Services
- * using the Embedian MXM-8x10 Computer on Module
- *
- * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd.
- *
- * 2010-01-21 Hennie van der Merve <hvdmerwe@tmtservies.co.za>
- */
-
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/property.h>
-#include <linux/gpio/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa320.h"
-#include "mxm8x10.h"
-
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/regulator/machine.h>
-
-#include "generic.h"
-
-#define ICONTROL_MCP251x_nCS1 (15)
-#define ICONTROL_MCP251x_nCS2 (16)
-#define ICONTROL_MCP251x_nCS3 (17)
-#define ICONTROL_MCP251x_nCS4 (24)
-
-#define ICONTROL_MCP251x_nIRQ1 (74)
-#define ICONTROL_MCP251x_nIRQ2 (75)
-#define ICONTROL_MCP251x_nIRQ3 (76)
-#define ICONTROL_MCP251x_nIRQ4 (77)
-
-static struct pxa2xx_spi_chip mcp251x_chip_info1 = {
- .tx_threshold = 8,
- .rx_threshold = 128,
- .dma_burst_size = 8,
- .timeout = 235,
-};
-
-static struct pxa2xx_spi_chip mcp251x_chip_info2 = {
- .tx_threshold = 8,
- .rx_threshold = 128,
- .dma_burst_size = 8,
- .timeout = 235,
-};
-
-static struct pxa2xx_spi_chip mcp251x_chip_info3 = {
- .tx_threshold = 8,
- .rx_threshold = 128,
- .dma_burst_size = 8,
- .timeout = 235,
-};
-
-static struct pxa2xx_spi_chip mcp251x_chip_info4 = {
- .tx_threshold = 8,
- .rx_threshold = 128,
- .dma_burst_size = 8,
- .timeout = 235,
-};
-
-static const struct property_entry mcp251x_properties[] = {
- PROPERTY_ENTRY_U32("clock-frequency", 16000000),
- {}
-};
-
-static const struct software_node mcp251x_node = {
- .properties = mcp251x_properties,
-};
-
-static struct spi_board_info mcp251x_board_info[] = {
- {
- .modalias = "mcp2515",
- .max_speed_hz = 6500000,
- .bus_num = 3,
- .chip_select = 0,
- .swnode = &mcp251x_node,
- .controller_data = &mcp251x_chip_info1,
- .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ1)
- },
- {
- .modalias = "mcp2515",
- .max_speed_hz = 6500000,
- .bus_num = 3,
- .chip_select = 1,
- .swnode = &mcp251x_node,
- .controller_data = &mcp251x_chip_info2,
- .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2)
- },
- {
- .modalias = "mcp2515",
- .max_speed_hz = 6500000,
- .bus_num = 4,
- .chip_select = 0,
- .swnode = &mcp251x_node,
- .controller_data = &mcp251x_chip_info3,
- .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3)
- },
- {
- .modalias = "mcp2515",
- .max_speed_hz = 6500000,
- .bus_num = 4,
- .chip_select = 1,
- .swnode = &mcp251x_node,
- .controller_data = &mcp251x_chip_info4,
- .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4)
- }
-};
-
-static struct pxa2xx_spi_controller pxa_ssp3_spi_master_info = {
- .num_chipselect = 2,
- .enable_dma = 1
-};
-
-static struct pxa2xx_spi_controller pxa_ssp4_spi_master_info = {
- .num_chipselect = 2,
- .enable_dma = 1
-};
-
-struct platform_device pxa_spi_ssp3 = {
- .name = "pxa2xx-spi",
- .id = 3,
- .dev = {
- .platform_data = &pxa_ssp3_spi_master_info,
- }
-};
-
-struct platform_device pxa_spi_ssp4 = {
- .name = "pxa2xx-spi",
- .id = 4,
- .dev = {
- .platform_data = &pxa_ssp4_spi_master_info,
- }
-};
-
-static struct gpiod_lookup_table pxa_ssp3_gpio_table = {
- .dev_id = "pxa2xx-spi.3",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS1, "cs", 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS2, "cs", 1, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpiod_lookup_table pxa_ssp4_gpio_table = {
- .dev_id = "pxa2xx-spi.4",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS3, "cs", 0, GPIO_ACTIVE_LOW),
- GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS4, "cs", 1, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct platform_device *icontrol_spi_devices[] __initdata = {
- &pxa_spi_ssp3,
- &pxa_spi_ssp4,
-};
-
-static mfp_cfg_t mfp_can_cfg[] __initdata = {
- /* CAN CS lines */
- GPIO15_GPIO,
- GPIO16_GPIO,
- GPIO17_GPIO,
- GPIO24_GPIO,
-
- /* SPI (SSP3) lines */
- GPIO89_SSP3_SCLK,
- GPIO91_SSP3_TXD,
- GPIO92_SSP3_RXD,
-
- /* SPI (SSP4) lines */
- GPIO93_SSP4_SCLK,
- GPIO95_SSP4_TXD,
- GPIO96_SSP4_RXD,
-
- /* CAN nIRQ lines */
- GPIO74_GPIO | MFP_LPM_EDGE_RISE,
- GPIO75_GPIO | MFP_LPM_EDGE_RISE,
- GPIO76_GPIO | MFP_LPM_EDGE_RISE,
- GPIO77_GPIO | MFP_LPM_EDGE_RISE
-};
-
-static void __init icontrol_can_init(void)
-{
- pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_can_cfg));
- gpiod_add_lookup_table(&pxa_ssp3_gpio_table);
- gpiod_add_lookup_table(&pxa_ssp4_gpio_table);
- platform_add_devices(ARRAY_AND_SIZE(icontrol_spi_devices));
- spi_register_board_info(ARRAY_AND_SIZE(mcp251x_board_info));
-}
-
-static void __init icontrol_init(void)
-{
- mxm_8x10_barebones_init();
- mxm_8x10_usb_host_init();
- mxm_8x10_mmc_init();
-
- icontrol_can_init();
-
- regulator_has_full_constraints();
-}
-
-MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = icontrol_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
deleted file mode 100644
index fb0850af8496..000000000000
--- a/arch/arm/mach-pxa/idp.c
+++ /dev/null
@@ -1,287 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/idp.c
- *
- * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
- *
- * 2001-09-13: Cliff Brake <cbrake@accelent.com>
- * Initial code
- *
- * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
- * <http://www.vibren.com> <http://bec-systems.com>
- * Updated for 2.6 kernel
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/fb.h>
-
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa25x.h"
-#include "idp.h"
-#include <linux/platform_data/video-pxafb.h>
-#include <mach/bitfield.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/smc91x.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/* TODO:
- * - add pxa2xx_audio_ops_t device structure
- * - Ethernet interrupt
- */
-
-static unsigned long idp_pin_config[] __initdata = {
- /* LCD */
- GPIOxx_LCD_DSTN_16BPP,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* STUART */
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO8_MMC_CS0,
-
- /* Ethernet */
- GPIO33_nCS_5, /* Ethernet CS */
- GPIO4_GPIO, /* Ethernet IRQ */
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (IDP_ETH_PHYS + 0x300),
- .end = (IDP_ETH_PHYS + 0xfffff),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(4),
- .end = PXA_GPIO_TO_IRQ(4),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct smc91x_platdata smc91x_platdata = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_USE_DMA | SMC91X_NOWAIT,
- .pxa_u16_align4 = true,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev.platform_data = &smc91x_platdata,
-};
-
-static void idp_backlight_power(int on)
-{
- if (on) {
- IDP_CPLD_LCD |= (1<<1);
- } else {
- IDP_CPLD_LCD &= ~(1<<1);
- }
-}
-
-static void idp_vlcd(int on)
-{
- if (on) {
- IDP_CPLD_LCD |= (1<<2);
- } else {
- IDP_CPLD_LCD &= ~(1<<2);
- }
-}
-
-static void idp_lcd_power(int on, struct fb_var_screeninfo *var)
-{
- if (on) {
- IDP_CPLD_LCD |= (1<<0);
- } else {
- IDP_CPLD_LCD &= ~(1<<0);
- }
-
- /* call idp_vlcd for now as core driver does not support
- * both power and vlcd hooks. Note, this is not technically
- * the correct sequence, but seems to work. Disclaimer:
- * this may eventually damage the display.
- */
-
- idp_vlcd(on);
-}
-
-static struct pxafb_mode_info sharp_lm8v31_mode = {
- .pixclock = 270000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 1,
- .left_margin = 3,
- .right_margin = 3,
- .vsync_len = 1,
- .upper_margin = 0,
- .lower_margin = 0,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info sharp_lm8v31 = {
- .modes = &sharp_lm8v31_mode,
- .num_modes = 1,
- .cmap_inverse = 0,
- .cmap_static = 0,
- .lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_AC_BIAS_FREQ(255),
- .pxafb_backlight_power = &idp_backlight_power,
- .pxafb_lcd_power = &idp_lcd_power
-};
-
-static struct pxamci_platform_data idp_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static void __init idp_init(void)
-{
- printk("idp_init()\n");
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- platform_device_register(&smc91x_device);
- //platform_device_register(&mst_audio_device);
- pxa_set_fb_info(NULL, &sharp_lm8v31);
- pxa_set_mci_info(&idp_mci_platform_data);
-}
-
-static struct map_desc idp_io_desc[] __initdata = {
- {
- .virtual = IDP_COREVOLT_VIRT,
- .pfn = __phys_to_pfn(IDP_COREVOLT_PHYS),
- .length = IDP_COREVOLT_SIZE,
- .type = MT_DEVICE
- }, {
- .virtual = IDP_CPLD_VIRT,
- .pfn = __phys_to_pfn(IDP_CPLD_PHYS),
- .length = IDP_CPLD_SIZE,
- .type = MT_DEVICE
- }
-};
-
-static void __init idp_map_io(void)
-{
- pxa25x_map_io();
- iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
-}
-
-/* LEDs */
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-struct idp_led {
- struct led_classdev cdev;
- u8 mask;
-};
-
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
- const char *name;
- const char *trigger;
-} idp_leds[] = {
- { "idp:green", "heartbeat", },
- { "idp:red", "cpu0", },
-};
-
-static void idp_led_set(struct led_classdev *cdev,
- enum led_brightness b)
-{
- struct idp_led *led = container_of(cdev,
- struct idp_led, cdev);
- u32 reg = IDP_CPLD_LED_CONTROL;
-
- if (b != LED_OFF)
- reg &= ~led->mask;
- else
- reg |= led->mask;
-
- IDP_CPLD_LED_CONTROL = reg;
-}
-
-static enum led_brightness idp_led_get(struct led_classdev *cdev)
-{
- struct idp_led *led = container_of(cdev,
- struct idp_led, cdev);
-
- return (IDP_CPLD_LED_CONTROL & led->mask) ? LED_OFF : LED_FULL;
-}
-
-static int __init idp_leds_init(void)
-{
- int i;
-
- if (!machine_is_pxa_idp())
- return -ENODEV;
-
- for (i = 0; i < ARRAY_SIZE(idp_leds); i++) {
- struct idp_led *led;
-
- led = kzalloc(sizeof(*led), GFP_KERNEL);
- if (!led)
- break;
-
- led->cdev.name = idp_leds[i].name;
- led->cdev.brightness_set = idp_led_set;
- led->cdev.brightness_get = idp_led_get;
- led->cdev.default_trigger = idp_leds[i].trigger;
-
- if (i == 0)
- led->mask = IDP_HB_LED;
- else
- led->mask = IDP_BUSY_LED;
-
- if (led_classdev_register(NULL, &led->cdev) < 0) {
- kfree(led);
- break;
- }
- }
-
- return 0;
-}
-
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(idp_leds_init);
-#endif
-
-MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
- /* Maintainer: Vibren Technologies */
- .map_io = idp_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = idp_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.h b/arch/arm/mach-pxa/idp.h
deleted file mode 100644
index a89e6723b1a1..000000000000
--- a/arch/arm/mach-pxa/idp.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/idp.h
- *
- * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
- *
- * 2001-09-13: Cliff Brake <cbrake@accelent.com>
- * Initial code
- *
- * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
- * <http://www.vibren.com> <http://bec-systems.com>
- * Changes for 2.6 kernel.
- */
-
-
-/*
- * Note: this file must be safe to include in assembly files
- *
- * Support for the Vibren PXA255 IDP requires rev04 or later
- * IDP hardware.
- */
-
-#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
-
-#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
-#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
-#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
-#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
-#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
-#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
-#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
-
-
-/*
- * virtual memory map
- */
-
-#define IDP_COREVOLT_VIRT (0xf0000000)
-#define IDP_COREVOLT_SIZE (1*1024*1024)
-
-#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
-#define IDP_CPLD_SIZE (1*1024*1024)
-
-#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
-#error Your custom IO space is getting a bit large !!
-#endif
-
-#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
-#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
-
-#ifndef __ASSEMBLY__
-# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
-#else
-# define __CPLD_REG(x) CPLD_P2V(x)
-#endif
-
-/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
-
-#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
-#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
-#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
-#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
-#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
-#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
-#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
-#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
-#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
-#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
-#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
-#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
-#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
-#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
-
-#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
-#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
-#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
-#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
-
-/* FPGA register virtual addresses */
-
-#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
-#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
-#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
-#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
-#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
-#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
-#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
-#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
-#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
-#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
-#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
-#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
-#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
-#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
-
-#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
-#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
-#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
-#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
-
-
-/*
- * Bit masks for various registers
- */
-
-// IDP_CPLD_PCCARD_PWR
-#define PCC0_PWR0 (1 << 0)
-#define PCC0_PWR1 (1 << 1)
-#define PCC0_PWR2 (1 << 2)
-#define PCC0_PWR3 (1 << 3)
-#define PCC1_PWR0 (1 << 4)
-#define PCC1_PWR1 (1 << 5)
-#define PCC1_PWR2 (1 << 6)
-#define PCC1_PWR3 (1 << 7)
-
-// IDP_CPLD_PCCARD_EN
-#define PCC0_RESET (1 << 6)
-#define PCC1_RESET (1 << 7)
-#define PCC0_ENABLE (1 << 0)
-#define PCC1_ENABLE (1 << 1)
-
-// IDP_CPLD_PCCARDx_STATUS
-#define _PCC_WRPROT (1 << 7) // 7-4 read as low true
-#define _PCC_RESET (1 << 6)
-#define _PCC_IRQ (1 << 5)
-#define _PCC_INPACK (1 << 4)
-#define PCC_BVD2 (1 << 3)
-#define PCC_BVD1 (1 << 2)
-#define PCC_VS2 (1 << 1)
-#define PCC_VS1 (1 << 0)
-
-/* A listing of interrupts used by external hardware devices */
-
-#define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5)
-#define IDE_IRQ PXA_GPIO_TO_IRQ(21)
-
-#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
-
-#define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4)
-#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-
-#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-
-#define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7)
-#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
-
-#define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8)
-#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
-
-#define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19)
-#define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22)
-
-
-/*
- * Macros for LED Driver
- */
-
-/* leds 0 = ON */
-#define IDP_HB_LED (1<<5)
-#define IDP_BUSY_LED (1<<6)
-
-#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
-
-/*
- * macros for MTD driver
- */
-
-#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
-#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
-
-/*
- * macros for matrix keyboard driver
- */
-
-#define KEYBD_MATRIX_NUMBER_INPUTS 7
-#define KEYBD_MATRIX_NUMBER_OUTPUTS 14
-
-#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
-#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
-
-#define KEYBD_MATRIX_SETTLING_TIME_US 100
-#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
-
-#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
-{\
- IDP_CPLD_KB_COL_LOW = outputs;\
- IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
-}
-
-#define KEYBD_MATRIX_GET_INPUTS(inputs) \
-{\
- inputs = (IDP_CPLD_KB_ROW & 0x7f);\
-}
-
-
diff --git a/arch/arm/mach-pxa/include/mach/audio.h b/arch/arm/mach-pxa/include/mach/audio.h
deleted file mode 100644
index 7beebf7297b5..000000000000
--- a/arch/arm/mach-pxa/include/mach/audio.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_AUDIO_H__
-#define __ASM_ARCH_AUDIO_H__
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/ac97_codec.h>
-
-/*
- * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
- * a -1 value means no gpio will be used for reset
- * @codec_pdata: AC97 codec platform_data
-
- * reset_gpio should only be specified for pxa27x CPUs where a silicon
- * bug prevents correct operation of the reset line. If not specified,
- * the default behaviour on these CPUs is to consider gpio 113 as the
- * AC97 reset line, which is the default on most boards.
- */
-typedef struct {
- int (*startup)(struct snd_pcm_substream *, void *);
- void (*shutdown)(struct snd_pcm_substream *, void *);
- void (*suspend)(void *);
- void (*resume)(void *);
- void *priv;
- int reset_gpio;
- void *codec_pdata[AC97_BUS_MAX_DEVICES];
-} pxa2xx_audio_ops_t;
-
-extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
deleted file mode 100644
index 04f3639c4082..000000000000
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/include/asm-arm/arch-pxa/balloon3.h
- *
- * Authors: Nick Bane and Wookey
- * Created: Oct, 2005
- * Copyright: Toby Churchill Ltd
- * Cribbed from mainstone.c, by Nicholas Pitre
- */
-
-#ifndef ASM_ARCH_BALLOON3_H
-#define ASM_ARCH_BALLOON3_H
-
-#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
-
-enum balloon3_features {
- BALLOON3_FEATURE_OHCI,
- BALLOON3_FEATURE_MMC,
- BALLOON3_FEATURE_CF,
- BALLOON3_FEATURE_AUDIO,
- BALLOON3_FEATURE_TOPPOLY,
-};
-
-#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS
-#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */
-#define BALLOON3_FPGA_LENGTH 0x01000000
-
-#define BALLOON3_FPGA_SETnCLR (0x1000)
-
-/* FPGA / CPLD registers for CF socket */
-#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
-#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
-/* FPGA / CPLD version register */
-#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c)
-/* FPGA / CPLD registers for NAND flash */
-#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000)
-#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
-#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
-#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
-#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
-
-/* fpga/cpld interrupt control register */
-#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C)
-#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c)
-
-#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000)
-#define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004)
-#define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c)
-
-/* CF Status Register bits (read-only) bits */
-#define BALLOON3_CF_nIRQ (1 << 0)
-#define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1)
-
-/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */
-#define BALLOON3_CF_RESET (1 << 0)
-#define BALLOON3_CF_ENABLE (1 << 1)
-#define BALLOON3_CF_ADD_ENABLE (1 << 2)
-
-/* CF Interrupt sources */
-#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
-#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
-
-/* NAND Control register */
-#define BALLOON3_NAND_CONTROL_FLWP (1 << 7)
-#define BALLOON3_NAND_CONTROL_FLSE (1 << 6)
-#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5)
-#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4)
-#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3)
-#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2)
-#define BALLOON3_NAND_CONTROL_FLALE (1 << 1)
-#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0)
-
-/* NAND Status register */
-#define BALLOON3_NAND_STAT_RNB (1 << 0)
-
-/* NAND Control2 register */
-#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0)
-
-/* GPIOs for irqs */
-#define BALLOON3_GPIO_AUX_NIRQ (94)
-#define BALLOON3_GPIO_CODEC_IRQ (95)
-
-/* Timer and Idle LED locations */
-#define BALLOON3_GPIO_LED_NAND (9)
-#define BALLOON3_GPIO_LED_IDLE (10)
-
-/* backlight control */
-#define BALLOON3_GPIO_RUN_BACKLIGHT (99)
-
-#define BALLOON3_GPIO_S0_CD (105)
-
-/* NAND */
-#define BALLOON3_GPIO_RUN_NAND (102)
-
-/* PCF8574A Leds */
-#define BALLOON3_PCF_GPIO_BASE 160
-#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0)
-#define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1)
-#define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2)
-#define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3)
-#define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4)
-#define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5)
-#define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6)
-#define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7)
-
-/* FPGA Interrupt Mask/Acknowledge Register */
-#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */
-#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */
-
-/* CPLD (and FPGA) interface definitions */
-#define CPLD_LCD0_DATA_SET 0x00
-#define CPLD_LCD0_DATA_CLR 0x10
-#define CPLD_LCD0_COMMAND_SET 0x01
-#define CPLD_LCD0_COMMAND_CLR 0x11
-#define CPLD_LCD1_DATA_SET 0x02
-#define CPLD_LCD1_DATA_CLR 0x12
-#define CPLD_LCD1_COMMAND_SET 0x03
-#define CPLD_LCD1_COMMAND_CLR 0x13
-
-#define CPLD_MISC_SET 0x07
-#define CPLD_MISC_CLR 0x17
-#define CPLD_MISC_LOON_NRESET_BIT 0
-#define CPLD_MISC_LOON_UNSUSP_BIT 1
-#define CPLD_MISC_RUN_5V_BIT 2
-#define CPLD_MISC_CHG_D0_BIT 3
-#define CPLD_MISC_CHG_D1_BIT 4
-#define CPLD_MISC_DAC_NCS_BIT 5
-
-#define CPLD_LCD_SET 0x08
-#define CPLD_LCD_CLR 0x18
-#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0
-#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1
-#define CPLD_LCD_LED_RED_BIT 4
-#define CPLD_LCD_LED_GREEN_BIT 5
-#define CPLD_LCD_NRESET_BIT 7
-
-#define CPLD_LCD_RO_SET 0x09
-#define CPLD_LCD_RO_CLR 0x19
-#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0
-#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1
-
-#define CPLD_SERIAL_SET 0x0a
-#define CPLD_SERIAL_CLR 0x1a
-#define CPLD_SERIAL_GSM_RI_BIT 0
-#define CPLD_SERIAL_GSM_CTS_BIT 1
-#define CPLD_SERIAL_GSM_DTR_BIT 2
-#define CPLD_SERIAL_LPR_CTS_BIT 3
-#define CPLD_SERIAL_TC232_CTS_BIT 4
-#define CPLD_SERIAL_TC232_DSR_BIT 5
-
-#define CPLD_SROUTING_SET 0x0b
-#define CPLD_SROUTING_CLR 0x1b
-#define CPLD_SROUTING_MSP430_LPR 0
-#define CPLD_SROUTING_MSP430_TC232 1
-#define CPLD_SROUTING_MSP430_GSM 2
-#define CPLD_SROUTING_LOON_LPR (0 << 4)
-#define CPLD_SROUTING_LOON_TC232 (1 << 4)
-#define CPLD_SROUTING_LOON_GSM (2 << 4)
-
-#define CPLD_AROUTING_SET 0x0c
-#define CPLD_AROUTING_CLR 0x1c
-#define CPLD_AROUTING_MIC2PHONE_BIT 0
-#define CPLD_AROUTING_PHONE2INT_BIT 1
-#define CPLD_AROUTING_PHONE2EXT_BIT 2
-#define CPLD_AROUTING_LOONL2INT_BIT 3
-#define CPLD_AROUTING_LOONL2EXT_BIT 4
-#define CPLD_AROUTING_LOONR2PHONE_BIT 5
-#define CPLD_AROUTING_LOONR2INT_BIT 6
-#define CPLD_AROUTING_LOONR2EXT_BIT 7
-
-/* Balloon3 Interrupts */
-#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x))
-
-#define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
-#define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
-
-#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16)
-
-extern int balloon3_has(enum balloon3_features feature);
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/bitfield.h b/arch/arm/mach-pxa/include/mach/bitfield.h
deleted file mode 100644
index fe2ca441bc0a..000000000000
--- a/arch/arm/mach-pxa/include/mach/bitfield.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * FILE bitfield.h
- *
- * Version 1.1
- * Author Copyright (c) Marc A. Viredaz, 1998
- * DEC Western Research Laboratory, Palo Alto, CA
- * Date April 1998 (April 1997)
- * System Advanced RISC Machine (ARM)
- * Language C or ARM Assembly
- * Purpose Definition of macros to operate on bit fields.
- */
-
-
-
-#ifndef __BITFIELD_H
-#define __BITFIELD_H
-
-#ifndef __ASSEMBLY__
-#define UData(Data) ((unsigned long) (Data))
-#else
-#define UData(Data) (Data)
-#endif
-
-
-/*
- * MACRO: Fld
- *
- * Purpose
- * The macro "Fld" encodes a bit field, given its size and its shift value
- * with respect to bit 0.
- *
- * Note
- * A more intuitive way to encode bit fields would have been to use their
- * mask. However, extracting size and shift value information from a bit
- * field's mask is cumbersome and might break the assembler (255-character
- * line-size limit).
- *
- * Input
- * Size Size of the bit field, in number of bits.
- * Shft Shift value of the bit field with respect to bit 0.
- *
- * Output
- * Fld Encoded bit field.
- */
-
-#define Fld(Size, Shft) (((Size) << 16) + (Shft))
-
-
-/*
- * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
- *
- * Purpose
- * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
- * the size, shift value, mask, aligned mask, and first bit of a
- * bit field.
- *
- * Input
- * Field Encoded bit field (using the macro "Fld").
- *
- * Output
- * FSize Size of the bit field, in number of bits.
- * FShft Shift value of the bit field with respect to bit 0.
- * FMsk Mask for the bit field.
- * FAlnMsk Mask for the bit field, aligned on bit 0.
- * F1stBit First bit of the bit field.
- */
-
-#define FSize(Field) ((Field) >> 16)
-#define FShft(Field) ((Field) & 0x0000FFFF)
-#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field) (UData (1) << FShft (Field))
-
-
-/*
- * MACRO: FInsrt
- *
- * Purpose
- * The macro "FInsrt" inserts a value into a bit field by shifting the
- * former appropriately.
- *
- * Input
- * Value Bit-field value.
- * Field Encoded bit field (using the macro "Fld").
- *
- * Output
- * FInsrt Bit-field value positioned appropriately.
- */
-
-#define FInsrt(Value, Field) \
- (UData (Value) << FShft (Field))
-
-
-/*
- * MACRO: FExtr
- *
- * Purpose
- * The macro "FExtr" extracts the value of a bit field by masking and
- * shifting it appropriately.
- *
- * Input
- * Data Data containing the bit-field to be extracted.
- * Field Encoded bit field (using the macro "Fld").
- *
- * Output
- * FExtr Bit-field value.
- */
-
-#define FExtr(Data, Field) \
- ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-
-#endif /* __BITFIELD_H */
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
deleted file mode 100644
index b565ca7b8cda..000000000000
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Hardware specific definitions for SL-C7xx series of PDAs
- *
- * Copyright (c) 2004-2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches
- */
-#ifndef __ASM_ARCH_CORGI_H
-#define __ASM_ARCH_CORGI_H 1
-
-#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
-
-/*
- * Corgi (Non Standard) GPIO Definitions
- */
-#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */
-#define CORGI_GPIO_AC_IN (1) /* Charger Detection */
-#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */
-#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */
-#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */
-#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */
-#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */
-#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */
-#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */
-#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */
-#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */
-#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */
-#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */
-#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */
-#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */
-#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */
-#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */
-#define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */
-#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */
-#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */
-#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */
-#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */
-#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */
-#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */
-#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */
-
-
-/*
- * Corgi Keyboard Definitions
- */
-#define CORGI_KEY_STROBE_NUM (12)
-#define CORGI_KEY_SENSE_NUM (8)
-#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc)
-#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000)
-#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26)
-#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003)
-#define CORGI_GPIO_LOW_SENSE_LSHIFT (6)
-#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a))
-#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a))
-#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0)
-#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000)
-#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f)
-#define CORGI_GPIO_KEY_SENSE(a) (58+(a))
-#define CORGI_GPIO_KEY_STROBE(a) (66+(a))
-
-
-/*
- * Corgi Interrupts
- */
-#define CORGI_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(0)
-#define CORGI_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1)
-#define CORGI_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(3)
-#define CORGI_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(4)
-#define CORGI_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5)
-#define CORGI_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9)
-#define CORGI_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(10)
-#define CORGI_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(11)
-#define CORGI_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14)
-#define CORGI_IRQ_GPIO_CHRG_FULL PXA_GPIO_TO_IRQ(16) /* Battery fully charged */
-#define CORGI_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17)
-#define CORGI_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */
-
-
-/*
- * Corgi SCOOP GPIOs and Config
- */
-#define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11
-#define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */
-#define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */
-#define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14
-#define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15
-#define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16
-#define CORGI_SCP_APM_ON SCOOP_GPCR_PA17
-#define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18
-#define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19
-
-#define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \
- CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \
- CORGI_SCP_MIC_BIAS )
-#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
-
-#define CORGI_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO)
-#define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0)
-#define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */
-#define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */
-#define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3)
-#define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4)
-#define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5)
-#define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6)
-#define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7)
-#define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8)
-
-#endif /* __ASM_ARCH_CORGI_H */
-
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
deleted file mode 100644
index 79f9842a7e1c..000000000000
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/dma.h
- *
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software, Inc.
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include <mach/hardware.h>
-
-/* DMA Controller Registers Definitions */
-#define DMAC_REGS_VIRT io_p2v(0x40000000)
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
deleted file mode 100644
index 5c645600d401..000000000000
--- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * eseries-gpio.h
- *
- * Copyright (C) Ian Molton <spyro@f2s.com>
- */
-
-/* e-series power button */
-#define GPIO_ESERIES_POWERBTN 0
-
-/* UDC GPIO definitions */
-#define GPIO_E7XX_USB_DISC 13
-#define GPIO_E7XX_USB_PULLUP 3
-
-#define GPIO_E800_USB_DISC 4
-#define GPIO_E800_USB_PULLUP 84
-
-/* e740 PCMCIA GPIO definitions */
-/* Note: PWR1 seems to be inverted */
-#define GPIO_E740_PCMCIA_CD0 8
-#define GPIO_E740_PCMCIA_CD1 44
-#define GPIO_E740_PCMCIA_RDY0 11
-#define GPIO_E740_PCMCIA_RDY1 6
-#define GPIO_E740_PCMCIA_RST0 27
-#define GPIO_E740_PCMCIA_RST1 24
-#define GPIO_E740_PCMCIA_PWR0 20
-#define GPIO_E740_PCMCIA_PWR1 23
-
-/* e750 PCMCIA GPIO definitions */
-#define GPIO_E750_PCMCIA_CD0 8
-#define GPIO_E750_PCMCIA_RDY0 12
-#define GPIO_E750_PCMCIA_RST0 27
-#define GPIO_E750_PCMCIA_PWR0 20
-
-/* e800 PCMCIA GPIO definitions */
-#define GPIO_E800_PCMCIA_RST0 69
-#define GPIO_E800_PCMCIA_RST1 72
-#define GPIO_E800_PCMCIA_PWR0 20
-#define GPIO_E800_PCMCIA_PWR1 73
-
-/* e7xx IrDA power control */
-#define GPIO_E7XX_IR_OFF 38
-
-/* e740 audio control GPIOs */
-#define GPIO_E740_WM9705_nAVDD2 16
-#define GPIO_E740_MIC_ON 40
-#define GPIO_E740_AMP_ON 41
-
-/* e750 audio control GPIOs */
-#define GPIO_E750_HP_AMP_OFF 4
-#define GPIO_E750_SPK_AMP_OFF 7
-#define GPIO_E750_HP_DETECT 37
-
-/* e800 audio control GPIOs */
-#define GPIO_E800_HP_DETECT 81
-#define GPIO_E800_HP_AMP_OFF 82
-#define GPIO_E800_SPK_AMP_ON 83
-
-/* ASIC related GPIOs */
-#define GPIO_ESERIES_TMIO_IRQ 5
-#define GPIO_ESERIES_TMIO_PCLR 19
-#define GPIO_ESERIES_TMIO_SUSPEND 45
-#define GPIO_E800_ANGELX_IRQ 8
diff --git a/arch/arm/mach-pxa/include/mach/generic.h b/arch/arm/mach-pxa/include/mach/generic.h
deleted file mode 100644
index 665542e0c9e2..000000000000
--- a/arch/arm/mach-pxa/include/mach/generic.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../generic.h"
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
deleted file mode 100644
index ee7eab16135f..000000000000
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/hardware.h
- *
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software Inc.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <mach/addr-map.h>
-
-/*
- * Workarounds for at least 2 errata so far require this.
- * The mapping is set in mach-pxa/generic.c.
- */
-#define UNCACHED_PHYS_0 0xfe000000
-#define UNCACHED_PHYS_0_SIZE 0x00100000
-
-/*
- * Intel PXA2xx internal register mapping:
- *
- * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
- * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
- * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
- * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
- * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
- * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
- * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
- *
- * Note that not all PXA2xx chips implement all those addresses, and the
- * kernel only maps the minimum needed range of this mapping.
- */
-#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
-#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
-
-#ifndef __ASSEMBLY__
-# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
-
-/* With indexed regs we don't want to feed the index through io_p2v()
- especially if it is a variable, otherwise horrible code will result. */
-# define __REG2(x,y) \
- (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
-
-# define __PREG(x) (io_v2p((u32)&(x)))
-
-#else
-
-# define __REG(x) io_p2v(x)
-# define __PREG(x) io_v2p(x)
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-#include <asm/cputype.h>
-
-/*
- * CPU Stepping CPU_ID JTAG_ID
- *
- * PXA210 B0 0x69052922 0x2926C013
- * PXA210 B1 0x69052923 0x3926C013
- * PXA210 B2 0x69052924 0x4926C013
- * PXA210 C0 0x69052D25 0x5926C013
- *
- * PXA250 A0 0x69052100 0x09264013
- * PXA250 A1 0x69052101 0x19264013
- * PXA250 B0 0x69052902 0x29264013
- * PXA250 B1 0x69052903 0x39264013
- * PXA250 B2 0x69052904 0x49264013
- * PXA250 C0 0x69052D05 0x59264013
- *
- * PXA255 A0 0x69052D06 0x69264013
- *
- * PXA26x A0 0x69052903 0x39264013
- * PXA26x B0 0x69052D05 0x59264013
- *
- * PXA27x A0 0x69054110 0x09265013
- * PXA27x A1 0x69054111 0x19265013
- * PXA27x B0 0x69054112 0x29265013
- * PXA27x B1 0x69054113 0x39265013
- * PXA27x C0 0x69054114 0x49265013
- * PXA27x C5 0x69054117 0x79265013
- *
- * PXA30x A0 0x69056880 0x0E648013
- * PXA30x A1 0x69056881 0x1E648013
- * PXA31x A0 0x69056890 0x0E649013
- * PXA31x A1 0x69056891 0x1E649013
- * PXA31x A2 0x69056892 0x2E649013
- * PXA32x B1 0x69056825 0x5E642013
- * PXA32x B2 0x69056826 0x6E642013
- *
- * PXA930 B0 0x69056835 0x5E643013
- * PXA930 B1 0x69056837 0x7E643013
- * PXA930 B2 0x69056838 0x8E643013
- *
- * PXA935 A0 0x56056931 0x1E653013
- * PXA935 B0 0x56056936 0x6E653013
- * PXA935 B1 0x56056938 0x8E653013
- */
-#ifdef CONFIG_PXA25x
-#define __cpu_is_pxa210(id) \
- ({ \
- unsigned int _id = (id) & 0xf3f0; \
- _id == 0x2120; \
- })
-
-#define __cpu_is_pxa250(id) \
- ({ \
- unsigned int _id = (id) & 0xf3ff; \
- _id <= 0x2105; \
- })
-
-#define __cpu_is_pxa255(id) \
- ({ \
- unsigned int _id = (id) & 0xffff; \
- _id == 0x2d06; \
- })
-
-#define __cpu_is_pxa25x(id) \
- ({ \
- unsigned int _id = (id) & 0xf300; \
- _id == 0x2100; \
- })
-#else
-#define __cpu_is_pxa210(id) (0)
-#define __cpu_is_pxa250(id) (0)
-#define __cpu_is_pxa255(id) (0)
-#define __cpu_is_pxa25x(id) (0)
-#endif
-
-#ifdef CONFIG_PXA27x
-#define __cpu_is_pxa27x(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x411; \
- })
-#else
-#define __cpu_is_pxa27x(id) (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA300
-#define __cpu_is_pxa300(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x688; \
- })
-#else
-#define __cpu_is_pxa300(id) (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA310
-#define __cpu_is_pxa310(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x689; \
- })
-#else
-#define __cpu_is_pxa310(id) (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA320
-#define __cpu_is_pxa320(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x603 || _id == 0x682; \
- })
-#else
-#define __cpu_is_pxa320(id) (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA930
-#define __cpu_is_pxa930(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x683; \
- })
-#else
-#define __cpu_is_pxa930(id) (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA935
-#define __cpu_is_pxa935(id) \
- ({ \
- unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x693; \
- })
-#else
-#define __cpu_is_pxa935(id) (0)
-#endif
-
-#define cpu_is_pxa210() \
- ({ \
- __cpu_is_pxa210(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa250() \
- ({ \
- __cpu_is_pxa250(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa255() \
- ({ \
- __cpu_is_pxa255(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa25x() \
- ({ \
- __cpu_is_pxa25x(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa27x() \
- ({ \
- __cpu_is_pxa27x(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa300() \
- ({ \
- __cpu_is_pxa300(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa310() \
- ({ \
- __cpu_is_pxa310(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa320() \
- ({ \
- __cpu_is_pxa320(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa930() \
- ({ \
- __cpu_is_pxa930(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa935() \
- ({ \
- __cpu_is_pxa935(read_cpuid_id()); \
- })
-
-
-
-/*
- * CPUID Core Generation Bit
- * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
- */
-#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
-#define __cpu_is_pxa2xx(id) \
- ({ \
- unsigned int _id = (id) >> 13 & 0x7; \
- _id <= 0x2; \
- })
-#else
-#define __cpu_is_pxa2xx(id) (0)
-#endif
-
-#ifdef CONFIG_PXA3xx
-#define __cpu_is_pxa3xx(id) \
- ({ \
- __cpu_is_pxa300(id) \
- || __cpu_is_pxa310(id) \
- || __cpu_is_pxa320(id) \
- || __cpu_is_pxa93x(id); \
- })
-#else
-#define __cpu_is_pxa3xx(id) (0)
-#endif
-
-#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
-#define __cpu_is_pxa93x(id) \
- ({ \
- __cpu_is_pxa930(id) \
- || __cpu_is_pxa935(id); \
- })
-#else
-#define __cpu_is_pxa93x(id) (0)
-#endif
-
-#define cpu_is_pxa2xx() \
- ({ \
- __cpu_is_pxa2xx(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa3xx() \
- ({ \
- __cpu_is_pxa3xx(read_cpuid_id()); \
- })
-
-#define cpu_is_pxa93x() \
- ({ \
- __cpu_is_pxa93x(read_cpuid_id()); \
- })
-
-
-/*
- * return current memory and LCD clock frequency in units of 10kHz
- */
-extern unsigned int get_memclk_frequency_10khz(void);
-
-#endif
-
-#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
deleted file mode 100644
index 0c30e6d9c660..000000000000
--- a/arch/arm/mach-pxa/include/mach/hx4700.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIO and IRQ definitions for HP iPAQ hx4700
- *
- * Copyright (c) 2008 Philipp Zabel
- */
-
-#ifndef _HX4700_H_
-#define _HX4700_H_
-
-#include <linux/gpio.h>
-#include <linux/mfd/asic3.h>
-#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
-
-#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO
-#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
-#define HX4700_NR_IRQS (IRQ_BOARD_START + 70)
-
-/*
- * PXA GPIOs
- */
-
-#define GPIO0_HX4700_nKEY_POWER 0
-#define GPIO12_HX4700_ASIC3_IRQ 12
-#define GPIO13_HX4700_W3220_IRQ 13
-#define GPIO14_HX4700_nWLAN_IRQ 14
-#define GPIO18_HX4700_RDY 18
-#define GPIO22_HX4700_LCD_RL 22
-#define GPIO27_HX4700_CODEC_ON 27
-#define GPIO32_HX4700_RS232_ON 32
-#define GPIO52_HX4700_CPU_nBATT_FAULT 52
-#define GPIO58_HX4700_TSC2046_nPENIRQ 58
-#define GPIO59_HX4700_LCD_PC1 59
-#define GPIO60_HX4700_CF_RNB 60
-#define GPIO61_HX4700_W3220_nRESET 61
-#define GPIO62_HX4700_LCD_nRESET 62
-#define GPIO63_HX4700_CPU_SS_nRESET 63
-#define GPIO65_HX4700_TSC2046_PEN_PU 65
-#define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66
-#define GPIO67_HX4700_EUART_PS 67
-#define GPIO70_HX4700_LCD_SLIN1 70
-#define GPIO71_HX4700_ASIC3_nRESET 71
-#define GPIO72_HX4700_BQ24022_nCHARGE_EN 72
-#define GPIO73_HX4700_LCD_UD_1 73
-#define GPIO75_HX4700_EARPHONE_nDET 75
-#define GPIO76_HX4700_USBC_PUEN 76
-#define GPIO81_HX4700_CPU_GP_nRESET 81
-#define GPIO82_HX4700_EUART_RESET 82
-#define GPIO83_HX4700_WLAN_nRESET 83
-#define GPIO84_HX4700_LCD_SQN 84
-#define GPIO85_HX4700_nPCE1 85
-#define GPIO88_HX4700_TSC2046_CS 88
-#define GPIO91_HX4700_FLASH_VPEN 91
-#define GPIO92_HX4700_HP_DRIVER 92
-#define GPIO93_HX4700_EUART_INT 93
-#define GPIO94_HX4700_KEY_MAIL 94
-#define GPIO95_HX4700_BATT_OFF 95
-#define GPIO96_HX4700_BQ24022_ISET2 96
-#define GPIO97_HX4700_nBL_DETECT 97
-#define GPIO99_HX4700_KEY_CONTACTS 99
-#define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */
-#define GPIO102_HX4700_SYNAPTICS_POWER_ON 102
-#define GPIO103_HX4700_SYNAPTICS_INT 103
-#define GPIO105_HX4700_nIR_ON 105
-#define GPIO106_HX4700_CPU_BT_nRESET 106
-#define GPIO107_HX4700_SPK_nSD 107
-#define GPIO109_HX4700_CODEC_nPDN 109
-#define GPIO110_HX4700_LCD_LVDD_3V3_ON 110
-#define GPIO111_HX4700_LCD_AVDD_3V3_ON 111
-#define GPIO112_HX4700_LCD_N2V7_7V3_ON 112
-#define GPIO114_HX4700_CF_RESET 114
-#define GPIO116_HX4700_CPU_HW_nRESET 116
-
-/*
- * ASIC3 GPIOs
- */
-
-#define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32)
-#define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48)
-
-#define GPIOC0_LED_RED (GPIOC_BASE + 0)
-#define GPIOC1_LED_GREEN (GPIOC_BASE + 1)
-#define GPIOC2_LED_BLUE (GPIOC_BASE + 2)
-#define GPIOC3_nSD_CS (GPIOC_BASE + 3)
-#define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */
-#define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */
-#define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */
-#define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */
-#define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */
-#define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */
-#define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */
-#define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */
-#define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */
-#define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */
-#define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */
-#define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */
-
-#define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */
-#define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1)
-#define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2)
-#define GPIOD3_nKEY_HOME (GPIOD_BASE + 3)
-#define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */
-#define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */
-#define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6)
-#define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7)
-#define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */
-#define GPIOD9_nAC_IN (GPIOD_BASE + 9)
-#define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */
-#define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */
-#define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */
-#define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */
-#define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14)
-#define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */
-
-/*
- * EGPIOs
- */
-
-#define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */
-#define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */
-#define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */
-#define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */
-#define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */
-#define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */
-#define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */
-#define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */
-#define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */
-
-#endif /* _HX4700_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
deleted file mode 100644
index a3af4a2f9446..000000000000
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/lubbock.h
- *
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software Inc.
- */
-
-#include <mach/irqs.h>
-
-#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS
-
-#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS
-#define LUBBOCK_FPGA_VIRT (0xf0000000)
-#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
-#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
-
-#ifndef __ASSEMBLY__
-# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x)))
-#else
-# define __LUB_REG(x) LUB_P2V(x)
-#endif
-
-/* FPGA register virtual addresses */
-#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
-#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
-#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
-#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
-#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
-#define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
-#define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
-#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
-#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
-
-/* Board specific IRQs */
-#define LUBBOCK_NR_IRQS IRQ_BOARD_START
-
-#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x))
-#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
-#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
-#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
-#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3)
-#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
-#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
-#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
-#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
-
-#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32)
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
deleted file mode 100644
index 7d3af561af6f..000000000000
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIO and IRQ definitions for HTC Magician PDA phones
- *
- * Copyright (c) 2007 Philipp Zabel
- */
-
-#ifndef _MAGICIAN_H_
-#define _MAGICIAN_H_
-
-#include <linux/gpio.h>
-#include <mach/irqs.h>
-
-/*
- * PXA GPIOs
- */
-
-#define GPIO0_MAGICIAN_KEY_POWER 0
-#define GPIO9_MAGICIAN_UNKNOWN 9
-#define GPIO10_MAGICIAN_GSM_IRQ 10
-#define GPIO11_MAGICIAN_GSM_OUT1 11
-#define GPIO13_MAGICIAN_CPLD_IRQ 13
-#define GPIO14_MAGICIAN_TSC2046_CS 14
-#define GPIO18_MAGICIAN_UNKNOWN 18
-#define GPIO22_MAGICIAN_VIBRA_EN 22
-#define GPIO26_MAGICIAN_GSM_POWER 26
-#define GPIO27_MAGICIAN_USBC_PUEN 27
-#define GPIO30_MAGICIAN_BQ24022_nCHARGE_EN 30
-#define GPIO37_MAGICIAN_KEY_HANGUP 37
-#define GPIO38_MAGICIAN_KEY_CONTACTS 38
-#define GPIO40_MAGICIAN_GSM_OUT2 40
-#define GPIO48_MAGICIAN_UNKNOWN 48
-#define GPIO56_MAGICIAN_UNKNOWN 56
-#define GPIO57_MAGICIAN_CAM_RESET 57
-#define GPIO75_MAGICIAN_SAMSUNG_POWER 75
-#define GPIO83_MAGICIAN_nIR_EN 83
-#define GPIO86_MAGICIAN_GSM_RESET 86
-#define GPIO87_MAGICIAN_GSM_SELECT 87
-#define GPIO90_MAGICIAN_KEY_CALENDAR 90
-#define GPIO91_MAGICIAN_KEY_CAMERA 91
-#define GPIO93_MAGICIAN_KEY_UP 93
-#define GPIO94_MAGICIAN_KEY_DOWN 94
-#define GPIO95_MAGICIAN_KEY_LEFT 95
-#define GPIO96_MAGICIAN_KEY_RIGHT 96
-#define GPIO97_MAGICIAN_KEY_ENTER 97
-#define GPIO98_MAGICIAN_KEY_RECORD 98
-#define GPIO99_MAGICIAN_HEADPHONE_IN 99
-#define GPIO100_MAGICIAN_KEY_VOL_UP 100
-#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
-#define GPIO102_MAGICIAN_KEY_PHONE 102
-#define GPIO103_MAGICIAN_LED_KP 103
-#define GPIO104_MAGICIAN_LCD_VOFF_EN 104
-#define GPIO105_MAGICIAN_LCD_VON_EN 105
-#define GPIO106_MAGICIAN_LCD_DCDC_NRESET 106
-#define GPIO107_MAGICIAN_DS1WM_IRQ 107
-#define GPIO108_MAGICIAN_GSM_READY 108
-#define GPIO114_MAGICIAN_UNKNOWN 114
-#define GPIO115_MAGICIAN_nPEN_IRQ 115
-#define GPIO116_MAGICIAN_nCAM_EN 116
-#define GPIO119_MAGICIAN_UNKNOWN 119
-#define GPIO120_MAGICIAN_UNKNOWN 120
-
-/*
- * CPLD IRQs
- */
-
-#define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0)
-#define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1)
-#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2)
-#define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3)
-
-#define MAGICIAN_NR_IRQS (IRQ_BOARD_START + 8)
-
-/*
- * CPLD EGPIOs
- */
-
-#define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO
-#define MAGICIAN_EGPIO(reg,bit) \
- (MAGICIAN_EGPIO_BASE + 8*reg + bit)
-
-/* output */
-
-#define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2)
-#define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5)
-#define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6)
-#define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7)
-#define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0)
-#define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1)
-#define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2)
-#define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3)
-#define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4)
-#define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5)
-#define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6)
-#define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7)
-#define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0)
-#define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1)
-#define EGPIO_MAGICIAN_IR_RX_SHUTDOWN MAGICIAN_EGPIO(2, 2)
-#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3)
-#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4)
-#define EGPIO_MAGICIAN_BQ24022_ISET2 MAGICIAN_EGPIO(2, 5)
-#define EGPIO_MAGICIAN_NICD_CHARGE MAGICIAN_EGPIO(2, 6)
-#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7)
-
-/* input */
-
-/* USB or AC charger type */
-#define EGPIO_MAGICIAN_CABLE_TYPE MAGICIAN_EGPIO(4, 0)
-/*
- * Vbus is detected
- * FIXME behaves like (6,3), may differ for host/device
- */
-#define EGPIO_MAGICIAN_CABLE_VBUS MAGICIAN_EGPIO(4, 1)
-
-#define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0)
-#define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1)
-#define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2)
-#define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3)
-#define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4)
-
-#define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1)
-/* FIXME behaves like (4,1), may differ for host/device */
-#define EGPIO_MAGICIAN_CABLE_INSERTED MAGICIAN_EGPIO(6, 3)
-
-#endif /* _MAGICIAN_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
deleted file mode 100644
index 1698f2ffd7c7..000000000000
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/mainstone.h
- *
- * Author: Nicolas Pitre
- * Created: Nov 14, 2002
- * Copyright: MontaVista Software Inc.
- */
-
-#ifndef ASM_ARCH_MAINSTONE_H
-#define ASM_ARCH_MAINSTONE_H
-
-#include <mach/irqs.h>
-
-#define MST_ETH_PHYS PXA_CS4_PHYS
-
-#define MST_FPGA_PHYS PXA_CS2_PHYS
-#define MST_FPGA_VIRT (0xf0000000)
-#define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
-#define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
-
-#ifndef __ASSEMBLY__
-# define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x)))
-#else
-# define __MST_REG(x) MST_P2V(x)
-#endif
-
-/* board level registers in the FPGA */
-
-#define MST_LEDDAT1 __MST_REG(0x08000010)
-#define MST_LEDDAT2 __MST_REG(0x08000014)
-#define MST_LEDCTRL __MST_REG(0x08000040)
-#define MST_GPSWR __MST_REG(0x08000060)
-#define MST_MSCWR1 __MST_REG(0x08000080)
-#define MST_MSCWR2 __MST_REG(0x08000084)
-#define MST_MSCWR3 __MST_REG(0x08000088)
-#define MST_MSCRD __MST_REG(0x08000090)
-#define MST_INTMSKENA __MST_REG(0x080000c0)
-#define MST_INTSETCLR __MST_REG(0x080000d0)
-#define MST_PCMCIA0 __MST_REG(0x080000e0)
-#define MST_PCMCIA1 __MST_REG(0x080000e4)
-
-#define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */
-#define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */
-#define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */
-#define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */
-#define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */
-#define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */
-#define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */
-#define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */
-#define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */
-
-#define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */
-#define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */
-#define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */
-#define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */
-#define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */
-
-#define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */
-#define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */
-#define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */
-#define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */
-#define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */
-
-#define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */
-#define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */
-#define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */
-#define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */
-#define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */
-#define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */
-#define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */
-
-#define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */
-#define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */
-#define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */
-
-#define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */
-#define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */
-#define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */
-#define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */
-#define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */
-#define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */
-#define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */
-#define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */
-#define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */
-#define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */
-
-#define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */
-#define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */
-#define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */
-#define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */
-#define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */
-#define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */
-#define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */
-#define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */
-#define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */
-#define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
-#define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
-#define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */
-#define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */
-#define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */
-
-#define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */
-#define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */
-#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */
-#define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */
-#define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */
-#define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */
-#define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */
-#define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */
-
-#define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */
-#define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/
-#define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */
-#define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */
-#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */
-#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
-
-#define MST_PCMCIA_INPUTS \
- (MST_PCMCIA_nIRQ | MST_PCMCIA_nSPKR_BVD2 | MST_PCMCIA_nSTSCHG_BVD1 | \
- MST_PCMCIA_nVS2 | MST_PCMCIA_nVS1 | MST_PCMCIA_nCD)
-
-/* board specific IRQs */
-#define MAINSTONE_NR_IRQS IRQ_BOARD_START
-
-#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x))
-#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
-#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
-#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
-#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3)
-#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4)
-#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5)
-#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6)
-#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7)
-#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9)
-#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
-#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11)
-#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13)
-#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
-#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
deleted file mode 100644
index 4b31bef9e50a..000000000000
--- a/arch/arm/mach-pxa/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * MTD primitives for XIP support. Architecture specific functions
- *
- * Do not include this file directly. It's included from linux/mtd/xip.h
- *
- * Author: Nicolas Pitre
- * Created: Nov 2, 2004
- * Copyright: (C) 2004 MontaVista Software, Inc.
- */
-
-#ifndef __ARCH_PXA_MTD_XIP_H__
-#define __ARCH_PXA_MTD_XIP_H__
-
-#include <mach/regs-ost.h>
-
-/* restored July 2017, this did not build since 2011! */
-
-#define ICIP io_p2v(0x40d00000)
-#define ICMR io_p2v(0x40d00004)
-#define xip_irqpending() (readl(ICIP) & readl(ICMR))
-
-/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime() readl(OSCR)
-#define xip_elapsed_since(x) (signed)((readl(OSCR) - (x)) / 4)
-
-/*
- * xip_cpu_idle() is used when waiting for a delay equal or larger than
- * the system timer tick period. This should put the CPU into idle mode
- * to save power and to be woken up only when some interrupts are pending.
- * As above, this should not rely upon standard kernel code.
- */
-
-#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
-
-#endif /* __ARCH_PXA_MTD_XIP_H__ */
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h
deleted file mode 100644
index 99a6d8b3a1e3..000000000000
--- a/arch/arm/mach-pxa/include/mach/palmld.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIOs and interrupts for Palm LifeDrive Handheld Computer
- *
- * Authors: Alex Osborne <ato@meshy.org>
- * Marek Vasut <marek.vasut@gmail.com>
- */
-
-#ifndef _INCLUDE_PALMLD_H_
-#define _INCLUDE_PALMLD_H_
-
-#include "irqs.h" /* PXA_GPIO_TO_IRQ */
-
-/** HERE ARE GPIOs **/
-
-/* GPIOs */
-#define GPIO_NR_PALMLD_GPIO_RESET 1
-#define GPIO_NR_PALMLD_POWER_DETECT 4
-#define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10
-#define GPIO_NR_PALMLD_POWER_SWITCH 12
-#define GPIO_NR_PALMLD_EARPHONE_DETECT 13
-#define GPIO_NR_PALMLD_LOCK_SWITCH 15
-
-/* SD/MMC */
-#define GPIO_NR_PALMLD_SD_DETECT_N 14
-#define GPIO_NR_PALMLD_SD_POWER 114
-#define GPIO_NR_PALMLD_SD_READONLY 116
-
-/* TOUCHSCREEN */
-#define GPIO_NR_PALMLD_WM9712_IRQ 27
-
-/* IRDA */
-#define GPIO_NR_PALMLD_IR_DISABLE 108
-
-/* LCD/BACKLIGHT */
-#define GPIO_NR_PALMLD_BL_POWER 19
-#define GPIO_NR_PALMLD_LCD_POWER 96
-
-/* LCD BORDER */
-#define GPIO_NR_PALMLD_BORDER_SWITCH 21
-#define GPIO_NR_PALMLD_BORDER_SELECT 22
-
-/* BLUETOOTH */
-#define GPIO_NR_PALMLD_BT_POWER 17
-#define GPIO_NR_PALMLD_BT_RESET 83
-
-/* PCMCIA (WiFi) */
-#define GPIO_NR_PALMLD_PCMCIA_READY 38
-#define GPIO_NR_PALMLD_PCMCIA_POWER 36
-#define GPIO_NR_PALMLD_PCMCIA_RESET 81
-
-/* LEDs */
-#define GPIO_NR_PALMLD_LED_GREEN 52
-#define GPIO_NR_PALMLD_LED_AMBER 94
-
-/* IDE */
-#define GPIO_NR_PALMLD_IDE_RESET 98
-#define GPIO_NR_PALMLD_IDE_PWEN 115
-
-/* USB */
-#define GPIO_NR_PALMLD_USB_DETECT_N 3
-#define GPIO_NR_PALMLD_USB_READY 86
-#define GPIO_NR_PALMLD_USB_RESET 88
-#define GPIO_NR_PALMLD_USB_INT 106
-#define GPIO_NR_PALMLD_USB_POWER 118
-/* 20, 53 and 86 are usb related too */
-
-/* INTERRUPTS */
-#define IRQ_GPIO_PALMLD_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET)
-#define IRQ_GPIO_PALMLD_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N)
-#define IRQ_GPIO_PALMLD_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ)
-#define IRQ_GPIO_PALMLD_IDE_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ)
-
-
-/** HERE ARE INIT VALUES **/
-
-/* IO mappings */
-#define PALMLD_USB_PHYS PXA_CS2_PHYS
-#define PALMLD_USB_VIRT 0xf0000000
-#define PALMLD_USB_SIZE 0x00100000
-
-#define PALMLD_IDE_PHYS 0x20000000
-#define PALMLD_IDE_VIRT 0xf1000000
-#define PALMLD_IDE_SIZE 0x00100000
-
-#define PALMLD_PHYS_IO_START 0x40000000
-#define PALMLD_STR_BASE 0xa0200000
-
-/* BATTERY */
-#define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
-#define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
-#define PALMLD_BAT_MAX_CURRENT 0 /* unknown */
-#define PALMLD_BAT_MIN_CURRENT 0 /* unknown */
-#define PALMLD_BAT_MAX_CHARGE 1 /* unknown */
-#define PALMLD_BAT_MIN_CHARGE 1 /* unknown */
-#define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */
-
-#define PALMLD_BAT_MEASURE_DELAY (HZ * 1)
-
-/* BACKLIGHT */
-#define PALMLD_MAX_INTENSITY 0xFE
-#define PALMLD_DEFAULT_INTENSITY 0x7E
-#define PALMLD_LIMIT_MASK 0x7F
-#define PALMLD_PRESCALER 0x3F
-#define PALMLD_PERIOD_NS 3500
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h
deleted file mode 100644
index 9257a02c46e5..000000000000
--- a/arch/arm/mach-pxa/include/mach/palmtc.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/include/asm-arm/arch-pxa/palmtc-gpio.h
- *
- * GPIOs and interrupts for Palm Tungsten|C Handheld Computer
- *
- * Authors: Alex Osborne <bobofdoom@gmail.com>
- * Marek Vasut <marek.vasut@gmail.com>
- * Holger Bocklet <bitz.email@gmx.net>
- */
-
-#ifndef _INCLUDE_PALMTC_H_
-#define _INCLUDE_PALMTC_H_
-
-#include "irqs.h" /* PXA_GPIO_TO_IRQ */
-
-/** HERE ARE GPIOs **/
-
-/* GPIOs */
-#define GPIO_NR_PALMTC_EARPHONE_DETECT 2
-#define GPIO_NR_PALMTC_CRADLE_DETECT 5
-#define GPIO_NR_PALMTC_HOTSYNC_BUTTON 7
-
-/* SD/MMC */
-#define GPIO_NR_PALMTC_SD_DETECT_N 12
-#define GPIO_NR_PALMTC_SD_POWER 32
-#define GPIO_NR_PALMTC_SD_READONLY 54
-
-/* WLAN */
-#define GPIO_NR_PALMTC_PCMCIA_READY 13
-#define GPIO_NR_PALMTC_PCMCIA_PWRREADY 14
-#define GPIO_NR_PALMTC_PCMCIA_POWER1 15
-#define GPIO_NR_PALMTC_PCMCIA_POWER2 33
-#define GPIO_NR_PALMTC_PCMCIA_POWER3 55
-#define GPIO_NR_PALMTC_PCMCIA_RESET 78
-
-/* UDC */
-#define GPIO_NR_PALMTC_USB_DETECT_N 4
-#define GPIO_NR_PALMTC_USB_POWER 36
-
-/* LCD/BACKLIGHT */
-#define GPIO_NR_PALMTC_BL_POWER 16
-#define GPIO_NR_PALMTC_LCD_POWER 44
-#define GPIO_NR_PALMTC_LCD_BLANK 38
-
-/* UART */
-#define GPIO_NR_PALMTC_RS232_POWER 37
-
-/* IRDA */
-#define GPIO_NR_PALMTC_IR_DISABLE 45
-
-/* IRQs */
-#define IRQ_GPIO_PALMTC_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N)
-#define IRQ_GPIO_PALMTC_WLAN_READY PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY)
-
-/* UCB1400 GPIOs */
-#define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00)
-#define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01)
-#define GPIO_NR_PALMTC_SPEAKER_ENABLE (0x80 | 0x03)
-#define GPIO_NR_PALMTC_VIBRA_POWER (0x80 | 0x05)
-#define GPIO_NR_PALMTC_LED_POWER (0x80 | 0x07)
-
-/** HERE ARE INIT VALUES **/
-#define PALMTC_UCB1400_GPIO_OFFSET 0x80
-
-/* BATTERY */
-#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
-#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
-#define PALMTC_BAT_MAX_CURRENT 0 /* unknown */
-#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */
-#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */
-#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */
-#define PALMTC_MAX_LIFE_MINS 240 /* on-life in minutes */
-
-#define PALMTC_BAT_MEASURE_DELAY (HZ * 1)
-
-/* BACKLIGHT */
-#define PALMTC_MAX_INTENSITY 0xFE
-#define PALMTC_DEFAULT_INTENSITY 0x7E
-#define PALMTC_LIMIT_MASK 0x7F
-#define PALMTC_PRESCALER 0x3F
-#define PALMTC_PERIOD_NS 3500
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
deleted file mode 100644
index ec88abf0fc6c..000000000000
--- a/arch/arm/mach-pxa/include/mach/palmtx.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIOs and interrupts for Palm T|X Handheld Computer
- *
- * Based on palmld-gpio.h by Alex Osborne
- *
- * Authors: Marek Vasut <marek.vasut@gmail.com>
- * Cristiano P. <cristianop@users.sourceforge.net>
- * Jan Herman <2hp@seznam.cz>
- */
-
-#ifndef _INCLUDE_PALMTX_H_
-#define _INCLUDE_PALMTX_H_
-
-#include "irqs.h" /* PXA_GPIO_TO_IRQ */
-
-/** HERE ARE GPIOs **/
-
-/* GPIOs */
-#define GPIO_NR_PALMTX_GPIO_RESET 1
-
-#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */
-#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10
-#define GPIO_NR_PALMTX_EARPHONE_DETECT 107
-
-/* SD/MMC */
-#define GPIO_NR_PALMTX_SD_DETECT_N 14
-#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */
-#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */
-
-/* TOUCHSCREEN */
-#define GPIO_NR_PALMTX_WM9712_IRQ 27
-
-/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
-#define GPIO_NR_PALMTX_IR_DISABLE 40
-
-/* USB */
-#define GPIO_NR_PALMTX_USB_DETECT_N 13
-#define GPIO_NR_PALMTX_USB_PULLUP 93
-
-/* LCD/BACKLIGHT */
-#define GPIO_NR_PALMTX_BL_POWER 84
-#define GPIO_NR_PALMTX_LCD_POWER 96
-
-/* LCD BORDER */
-#define GPIO_NR_PALMTX_BORDER_SWITCH 98
-#define GPIO_NR_PALMTX_BORDER_SELECT 22
-
-/* BLUETOOTH */
-#define GPIO_NR_PALMTX_BT_POWER 17
-#define GPIO_NR_PALMTX_BT_RESET 83
-
-/* PCMCIA (WiFi) */
-#define GPIO_NR_PALMTX_PCMCIA_POWER1 94
-#define GPIO_NR_PALMTX_PCMCIA_POWER2 108
-#define GPIO_NR_PALMTX_PCMCIA_RESET 79
-#define GPIO_NR_PALMTX_PCMCIA_READY 116
-
-/* NAND Flash ... this GPIO may be incorrect! */
-#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79
-
-/* INTERRUPTS */
-#define IRQ_GPIO_PALMTX_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N)
-#define IRQ_GPIO_PALMTX_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ)
-#define IRQ_GPIO_PALMTX_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT)
-#define IRQ_GPIO_PALMTX_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET)
-
-/** HERE ARE INIT VALUES **/
-
-/* Various addresses */
-#define PALMTX_PCMCIA_PHYS 0x28000000
-#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)
-#define PALMTX_PCMCIA_SIZE 0x100000
-
-#define PALMTX_PHYS_RAM_START 0xa0000000
-#define PALMTX_PHYS_IO_START 0x40000000
-
-#define PALMTX_STR_BASE 0xa0200000
-
-#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
-#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */
-
-#define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24))
-#define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25))
-#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)
-#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
-
-/* TOUCHSCREEN */
-#define AC97_LINK_FRAME 21
-
-
-/* BATTERY */
-#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
-#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMTX_BAT_MAX_CURRENT 0 /* unknown */
-#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */
-#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */
-#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */
-#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */
-
-#define PALMTX_BAT_MEASURE_DELAY (HZ * 1)
-
-/* BACKLIGHT */
-#define PALMTX_MAX_INTENSITY 0xFE
-#define PALMTX_DEFAULT_INTENSITY 0x7E
-#define PALMTX_LIMIT_MASK 0x7F
-#define PALMTX_PRESCALER 0x3F
-#define PALMTX_PERIOD_NS 3500
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
deleted file mode 100644
index b56b19351a03..000000000000
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/poodle.h
- *
- * May be copied or modified under the terms of the GNU General Public
- * License. See linux/COPYING for more information.
- *
- * Based on:
- * arch/arm/mach-sa1100/include/mach/collie.h
- *
- * ChangeLog:
- * 04-06-2001 Lineo Japan, Inc.
- * 04-16-2001 SHARP Corporation
- * Update to 2.6 John Lenz
- */
-#ifndef __ASM_ARCH_POODLE_H
-#define __ASM_ARCH_POODLE_H 1
-
-#include "irqs.h" /* PXA_GPIO_TO_IRQ */
-
-/*
- * GPIOs
- */
-/* PXA GPIOs */
-#define POODLE_GPIO_ON_KEY (0)
-#define POODLE_GPIO_AC_IN (1)
-#define POODLE_GPIO_CO 16
-#define POODLE_GPIO_TP_INT (5)
-#define POODLE_GPIO_TP_CS (24)
-#define POODLE_GPIO_WAKEUP (11) /* change battery */
-#define POODLE_GPIO_GA_INT (10)
-#define POODLE_GPIO_IR_ON (22)
-#define POODLE_GPIO_HP_IN (4)
-#define POODLE_GPIO_CF_IRQ (17)
-#define POODLE_GPIO_CF_CD (14)
-#define POODLE_GPIO_CF_STSCHG (14)
-#define POODLE_GPIO_SD_PWR (33)
-#define POODLE_GPIO_SD_PWR1 (3)
-#define POODLE_GPIO_nSD_CLK (6)
-#define POODLE_GPIO_nSD_WP (7)
-#define POODLE_GPIO_nSD_INT (8)
-#define POODLE_GPIO_nSD_DETECT (9)
-#define POODLE_GPIO_MAIN_BAT_LOW (13)
-#define POODLE_GPIO_BAT_COVER (13)
-#define POODLE_GPIO_USB_PULLUP (20)
-#define POODLE_GPIO_ADC_TEMP_ON (21)
-#define POODLE_GPIO_BYPASS_ON (36)
-#define POODLE_GPIO_CHRG_ON (38)
-#define POODLE_GPIO_CHRG_FULL (16)
-#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */
-
-/* PXA GPIOs */
-#define POODLE_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(0)
-#define POODLE_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1)
-#define POODLE_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(4)
-#define POODLE_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(16)
-#define POODLE_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5)
-#define POODLE_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(11)
-#define POODLE_IRQ_GPIO_GA_INT PXA_GPIO_TO_IRQ(10)
-#define POODLE_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17)
-#define POODLE_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14)
-#define POODLE_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(8)
-#define POODLE_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9)
-#define POODLE_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(13)
-
-/* SCOOP GPIOs */
-#define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11
-#define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13
-#define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18
-#define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20
-#define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21
-#define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22
-
-#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
-#define POODLE_SCOOP_IO_OUT ( 0 )
-
-#define POODLE_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO)
-#define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0)
-#define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2)
-#define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7)
-#define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9)
-#define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10)
-#define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11)
-
-#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8)
-#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10)
-#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11)
-#define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12)
-#define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13)
-
-#define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */
-
-extern struct platform_device poodle_locomo_device;
-
-#endif /* __ASM_ARCH_POODLE_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h
deleted file mode 100644
index 1db96fd4df32..000000000000
--- a/arch/arm/mach-pxa/include/mach/regs-ac97.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_REGS_AC97_H
-#define __ASM_ARCH_REGS_AC97_H
-
-#include <mach/hardware.h>
-
-/*
- * AC97 Controller registers
- */
-
-#define POCR __REG(0x40500000) /* PCM Out Control Register */
-#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
-
-#define PICR __REG(0x40500004) /* PCM In Control Register */
-#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
-
-#define MCCR __REG(0x40500008) /* Mic In Control Register */
-#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
-
-#define GCR __REG(0x4050000C) /* Global Control Register */
-#ifdef CONFIG_PXA3xx
-#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
-#endif
-#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
-#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
-#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
-#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
-#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
-#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
-#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
-#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
-#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
-#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
-#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
-
-#define POSR __REG(0x40500010) /* PCM Out Status Register */
-#define POSR_FIFOE (1 << 4) /* FIFO error */
-#define POSR_FSR (1 << 2) /* FIFO Service Request */
-
-#define PISR __REG(0x40500014) /* PCM In Status Register */
-#define PISR_FIFOE (1 << 4) /* FIFO error */
-#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
-#define PISR_FSR (1 << 2) /* FIFO Service Request */
-
-#define MCSR __REG(0x40500018) /* Mic In Status Register */
-#define MCSR_FIFOE (1 << 4) /* FIFO error */
-#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
-#define MCSR_FSR (1 << 2) /* FIFO Service Request */
-
-#define GSR __REG(0x4050001C) /* Global Status Register */
-#define GSR_CDONE (1 << 19) /* Command Done */
-#define GSR_SDONE (1 << 18) /* Status Done */
-#define GSR_RDCS (1 << 15) /* Read Completion Status */
-#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
-#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
-#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
-#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
-#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
-#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
-#define GSR_PCR (1 << 8) /* Primary Codec Ready */
-#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
-#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
-#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
-#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
-#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
-#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
-#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
-
-#define CAR __REG(0x40500020) /* CODEC Access Register */
-#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
-
-#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
-#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
-
-#define MOCR __REG(0x40500100) /* Modem Out Control Register */
-#define MOCR_FEIE (1 << 3) /* FIFO Error */
-#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
-
-#define MICR __REG(0x40500108) /* Modem In Control Register */
-#define MICR_FEIE (1 << 3) /* FIFO Error */
-#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
-
-#define MOSR __REG(0x40500110) /* Modem Out Status Register */
-#define MOSR_FIFOE (1 << 4) /* FIFO error */
-#define MOSR_FSR (1 << 2) /* FIFO Service Request */
-
-#define MISR __REG(0x40500118) /* Modem In Status Register */
-#define MISR_FIFOE (1 << 4) /* FIFO error */
-#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
-#define MISR_FSR (1 << 2) /* FIFO Service Request */
-
-#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
-
-#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
-#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
-#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
-#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
-
-#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
deleted file mode 100644
index e2b6e3d1f625..000000000000
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_REGS_LCD_H
-#define __ASM_ARCH_REGS_LCD_H
-
-#include <mach/bitfield.h>
-
-/*
- * LCD Controller Registers and Bits Definitions
- */
-#define LCCR0 (0x000) /* LCD Controller Control Register 0 */
-#define LCCR1 (0x004) /* LCD Controller Control Register 1 */
-#define LCCR2 (0x008) /* LCD Controller Control Register 2 */
-#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
-#define LCCR4 (0x010) /* LCD Controller Control Register 4 */
-#define LCCR5 (0x014) /* LCD Controller Control Register 5 */
-#define LCSR (0x038) /* LCD Controller Status Register 0 */
-#define LCSR1 (0x034) /* LCD Controller Status Register 1 */
-#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */
-#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
-#define TMEDCR (0x044) /* TMED Control Register */
-
-#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
-#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
-#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
-#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
-#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
-#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
-#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
-
-#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */
-#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */
-#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */
-#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */
-
-#define CMDCR (0x100) /* Command Control Register */
-#define PRSR (0x104) /* Panel Read Status Register */
-
-#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))
-
-#define LCCR3_PDFOR_0 (0 << 30)
-#define LCCR3_PDFOR_1 (1 << 30)
-#define LCCR3_PDFOR_2 (2 << 30)
-#define LCCR3_PDFOR_3 (3 << 30)
-
-#define LCCR4_PAL_FOR_0 (0 << 15)
-#define LCCR4_PAL_FOR_1 (1 << 15)
-#define LCCR4_PAL_FOR_2 (2 << 15)
-#define LCCR4_PAL_FOR_3 (3 << 15)
-#define LCCR4_PAL_FOR_MASK (3 << 15)
-
-#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
-#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
-#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */
-#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */
-#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */
-#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */
-#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
-
-#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
-#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
-#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
-#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
-#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */
-#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
-#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
-
-#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
-#define LCCR0_SFM (1 << 4) /* Start of frame mask */
-#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
-#define LCCR0_EFM (1 << 6) /* End of Frame mask */
-#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
-#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
-#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
-#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */
-#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
-#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
-#define LCCR0_DIS (1 << 10) /* LCD Disable */
-#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
-#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
-#define LCCR0_PDD_S 12
-#define LCCR0_BM (1 << 20) /* Branch mask */
-#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
-#define LCCR0_LCDT (1 << 22) /* LCD panel type */
-#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
-#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
-#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
-#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
-
-#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
-#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
-
-#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
-#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
-
-#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
-#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
-
-#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
-#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
-
-#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
-#define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
-
-#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
-#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
-
-#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
-#define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW))
-
-#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
-#define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW))
-
-#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
-#define LCCR3_API_S 16
-#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
-#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
-#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
-#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
-#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
-
-#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */
-#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
-#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
-
-#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
-#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
-#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD)))
-
-#define LCCR3_ACB Fld (8, 8) /* AC Bias */
-#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB)))
-
-#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */
-#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */
-
-#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */
-#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */
-
-#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */
-#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */
-#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */
-#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */
-
-#define LCSR_LDD (1 << 0) /* LCD Disable Done */
-#define LCSR_SOF (1 << 1) /* Start of frame */
-#define LCSR_BER (1 << 2) /* Bus error */
-#define LCSR_ABC (1 << 3) /* AC Bias count */
-#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
-#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
-#define LCSR_OU (1 << 6) /* output FIFO underrun */
-#define LCSR_QD (1 << 7) /* quick disable */
-#define LCSR_EOF (1 << 8) /* end of frame */
-#define LCSR_BS (1 << 9) /* branch status */
-#define LCSR_SINT (1 << 10) /* subsequent interrupt */
-#define LCSR_RD_ST (1 << 11) /* read status */
-#define LCSR_CMD_INT (1 << 12) /* command interrupt */
-
-#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */
-#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */
-#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */
-#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */
-
-#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
-
-/* overlay control registers */
-#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */
-#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */
-#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */
-#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */
-#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */
-#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */
-#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */
-
-/* smartpanel related */
-#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */
-#define PRSR_A0 (1 << 8) /* Read Data Source */
-#define PRSR_ST_OK (1 << 9) /* Status OK */
-#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */
-
-#define SMART_CMD_A0 (0x1 << 8)
-#define SMART_CMD_READ_STATUS_REG (0x0 << 9)
-#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WRITE_COMMAND (0x1 << 9)
-#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9)
-#define SMART_CMD_NOOP (0x4 << 9)
-#define SMART_CMD_INTERRUPT (0x5 << 9)
-
-#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
-#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff))
-
-/* SMART_DELAY() is introduced for software controlled delay primitive which
- * can be inserted between command sequences, unused command 0x6 is used here
- * and delay ranges from 0ms ~ 255ms
- */
-#define SMART_CMD_DELAY (0x6 << 9)
-#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff))
-#endif /* __ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h
deleted file mode 100644
index 9a168f83afeb..000000000000
--- a/arch/arm/mach-pxa/include/mach/regs-uart.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_REGS_UART_H
-#define __ASM_ARCH_REGS_UART_H
-
-/*
- * UARTs
- */
-
-/* Full Function UART (FFUART) */
-#define FFUART FFRBR
-#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
-#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
-#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
-#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
-#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
-#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
-#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
-#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
-#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
-#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
-#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
-#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Bluetooth UART (BTUART) */
-#define BTUART BTRBR
-#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
-#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
-#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
-#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
-#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
-#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
-#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
-#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
-#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
-#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
-#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
-#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Standard UART (STUART) */
-#define STUART STRBR
-#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
-#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
-#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
-#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
-#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
-#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
-#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
-#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
-#define STMSR __REG(0x40700018) /* Reserved */
-#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
-#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
-#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Hardware UART (HWUART) */
-#define HWUART HWRBR
-#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
-#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
-#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
-#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
-#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
-#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
-#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
-#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
-#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
-#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
-#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
-#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
-#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
-#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
-#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-#define IER_DMAE (1 << 7) /* DMA Requests Enable */
-#define IER_UUE (1 << 6) /* UART Unit Enable */
-#define IER_NRZE (1 << 5) /* NRZ coding Enable */
-#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
-#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
-#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
-#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
-#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
-#define IIR_TOD (1 << 3) /* Time Out Detected */
-#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
-#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
-#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
-
-#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
-#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
-#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
-#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
-#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1 (0)
-#define FCR_ITL_8 (FCR_ITL1)
-#define FCR_ITL_16 (FCR_ITL2)
-#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
-#define LCR_SB (1 << 6) /* Set Break */
-#define LCR_STKYP (1 << 5) /* Sticky Parity */
-#define LCR_EPS (1 << 4) /* Even Parity Select */
-#define LCR_PEN (1 << 3) /* Parity Enable */
-#define LCR_STB (1 << 2) /* Stop Bit */
-#define LCR_WLS1 (1 << 1) /* Word Length Select */
-#define LCR_WLS0 (1 << 0) /* Word Length Select */
-
-#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
-#define LSR_TEMT (1 << 6) /* Transmitter Empty */
-#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
-#define LSR_BI (1 << 4) /* Break Interrupt */
-#define LSR_FE (1 << 3) /* Framing Error */
-#define LSR_PE (1 << 2) /* Parity Error */
-#define LSR_OE (1 << 1) /* Overrun Error */
-#define LSR_DR (1 << 0) /* Data Ready */
-
-#define MCR_LOOP (1 << 4)
-#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
-#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
-#define MCR_RTS (1 << 1) /* Request to Send */
-#define MCR_DTR (1 << 0) /* Data Terminal Ready */
-
-#define MSR_DCD (1 << 7) /* Data Carrier Detect */
-#define MSR_RI (1 << 6) /* Ring Indicator */
-#define MSR_DSR (1 << 5) /* Data Set Ready */
-#define MSR_CTS (1 << 4) /* Clear To Send */
-#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
-#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
-#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
-#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
-
-/*
- * IrSR (Infrared Selection Register)
- */
-#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
-#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
-#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
-#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
-#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
-
-#endif /* __ASM_ARCH_REGS_UART_H */
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
deleted file mode 100644
index 8bfaca3a8b64..000000000000
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Hardware specific definitions for Sharp SL-C6000x series of PDAs
- *
- * Copyright (c) 2005 Dirk Opfer
- *
- * Based on Sharp's 2.4 kernel patches
- */
-#ifndef _ASM_ARCH_TOSA_H_
-#define _ASM_ARCH_TOSA_H_ 1
-
-#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
-
-/* TOSA Chip selects */
-#define TOSA_LCDC_PHYS PXA_CS4_PHYS
-/* Internel Scoop */
-#define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000)
-/* Jacket Scoop */
-#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000)
-
-#define TOSA_NR_IRQS (IRQ_BOARD_START + TC6393XB_NR_IRQS)
-/*
- * SCOOP2 internal GPIOs
- */
-#define TOSA_SCOOP_GPIO_BASE PXA_NR_BUILTIN_GPIO
-#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
-#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1)
-#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
-#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
-#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
-#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
-#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6)
-#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7)
-#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19
-
-/* GPIO Direction 1 : output mode / 0:input mode */
-#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \
- TOSA_SCOOP_AUD_PWR_ON)
-
-/*
- * SCOOP2 jacket GPIOs
- */
-#define TOSA_SCOOP_JC_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12)
-#define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0)
-#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
-#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
-#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3)
-#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4)
-#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5)
-#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
-#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
-#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
-
-/* GPIO Direction 1 : output mode / 0:input mode */
-#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL)
-
-/*
- * TC6393XB GPIOs
- */
-#define TOSA_TC6393XB_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 2 * 12)
-
-#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0)
-#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1)
-#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3)
-#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4)
-#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6)
-#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7)
-#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9)
-#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10)
-#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11)
-#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12)
-#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14)
-#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15)
-
-/*
- * PXA GPIOs
- */
-#define TOSA_GPIO_POWERON (0)
-#define TOSA_GPIO_RESET (1)
-#define TOSA_GPIO_AC_IN (2)
-#define TOSA_GPIO_RECORD_BTN (3)
-#define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */
-#define TOSA_GPIO_USB_IN (5)
-#define TOSA_GPIO_JACKET_DETECT (7)
-#define TOSA_GPIO_nSD_DETECT (9)
-#define TOSA_GPIO_nSD_INT (10)
-#define TOSA_GPIO_TC6393XB_CLK (11)
-#define TOSA_GPIO_BAT1_CRG (12)
-#define TOSA_GPIO_CF_CD (13)
-#define TOSA_GPIO_BAT0_CRG (14)
-#define TOSA_GPIO_TC6393XB_INT (15)
-#define TOSA_GPIO_BAT0_LOW (17)
-#define TOSA_GPIO_TC6393XB_RDY (18)
-#define TOSA_GPIO_ON_RESET (19)
-#define TOSA_GPIO_EAR_IN (20)
-#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
-#define TOSA_GPIO_ON_KEY (22)
-#define TOSA_GPIO_VGA_LINE (27)
-#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */
-#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
-#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */
-#define TOSA_GPIO_IRDA_TX (47)
-#define TOSA_GPIO_TG_SPI_SCLK (81)
-#define TOSA_GPIO_TG_SPI_CS (82)
-#define TOSA_GPIO_TG_SPI_MOSI (83)
-#define TOSA_GPIO_BAT1_LOW (84)
-
-#define TOSA_GPIO_HP_IN GPIO_EAR_IN
-
-#define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW
-
-#define TOSA_KEY_STROBE_NUM (11)
-#define TOSA_KEY_SENSE_NUM (7)
-
-#define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000)
-#define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f)
-#define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0)
-#define TOSA_GPIO_ALL_SENSE_RSHIFT (5)
-#define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a))
-#define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a))
-#define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000)
-#define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff)
-#define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00)
-#define TOSA_GPIO_KEY_SENSE(a) (69+(a))
-#define TOSA_GPIO_KEY_STROBE(a) (58+(a))
-
-/*
- * Interrupts
- */
-#define TOSA_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP)
-#define TOSA_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN)
-#define TOSA_IRQ_GPIO_RECORD_BTN PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN)
-#define TOSA_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC)
-#define TOSA_IRQ_GPIO_USB_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN)
-#define TOSA_IRQ_GPIO_JACKET_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT)
-#define TOSA_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT)
-#define TOSA_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT)
-#define TOSA_IRQ_GPIO_BAT1_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG)
-#define TOSA_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD)
-#define TOSA_IRQ_GPIO_BAT0_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG)
-#define TOSA_IRQ_GPIO_TC6393XB_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT)
-#define TOSA_IRQ_GPIO_BAT0_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW)
-#define TOSA_IRQ_GPIO_EAR_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN)
-#define TOSA_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ)
-#define TOSA_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY)
-#define TOSA_IRQ_GPIO_VGA_LINE PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE)
-#define TOSA_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT)
-#define TOSA_IRQ_GPIO_JC_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ)
-#define TOSA_IRQ_GPIO_BAT_LOCKED PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED)
-#define TOSA_IRQ_GPIO_BAT1_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW)
-#define TOSA_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(69+(a))
-
-#define TOSA_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW)
-
-#define TOSA_KEY_SYNC KEY_102ND /* ??? */
-
-#ifndef CONFIG_TOSA_USE_EXT_KEYCODES
-#define TOSA_KEY_RECORD KEY_YEN
-#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA
-#define TOSA_KEY_CANCEL KEY_ESC
-#define TOSA_KEY_CENTER KEY_HIRAGANA
-#define TOSA_KEY_OK KEY_HENKAN
-#define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA
-#define TOSA_KEY_HOMEPAGE KEY_HANGEUL
-#define TOSA_KEY_LIGHT KEY_MUHENKAN
-#define TOSA_KEY_MENU KEY_HANJA
-#define TOSA_KEY_FN KEY_RIGHTALT
-#define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU
-#else
-#define TOSA_KEY_RECORD KEY_RECORD
-#define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK
-#define TOSA_KEY_CANCEL KEY_CANCEL
-#define TOSA_KEY_CENTER KEY_SELECT /* ??? */
-#define TOSA_KEY_OK KEY_OK
-#define TOSA_KEY_CALENDAR KEY_CALENDAR
-#define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE
-#define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE
-#define TOSA_KEY_MENU KEY_MENU
-#define TOSA_KEY_FN KEY_FN
-#define TOSA_KEY_MAIL KEY_MAIL
-#endif
-
-#endif /* _ASM_ARCH_TOSA_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
deleted file mode 100644
index 3cddb1428c5e..000000000000
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/************************************************************************
- * Include file for TRIZEPS4 SoM and ConXS eval-board
- * Copyright (c) Jürgen Schindele
- * 2006
- ************************************************************************/
-
-/*
- * Includes/Defines
- */
-#ifndef _TRIPEPS4_H_
-#define _TRIPEPS4_H_
-
-#include "irqs.h" /* PXA_GPIO_TO_IRQ */
-
-/* physical memory regions */
-#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
-#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */
-#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
-#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
-#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
-
- /* Logic on ConXS-board CSFR register*/
-#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS)
- /* Logic on ConXS-board BOCR register*/
-#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000)
- /* Logic on ConXS-board IRCR register*/
-#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000)
- /* Logic on ConXS-board UPSR register*/
-#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000)
- /* Logic on ConXS-board DICR register*/
-#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000)
-
-/* virtual memory regions */
-#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
-
-#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */
-#define TRIZEPS4_CFSR_VIRT 0xF0100000
-#define TRIZEPS4_BOCR_VIRT 0xF0200000
-#define TRIZEPS4_DICR_VIRT 0xF0300000
-#define TRIZEPS4_IRCR_VIRT 0xF0400000
-#define TRIZEPS4_UPSR_VIRT 0xF0500000
-
-/* size of flash */
-#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
-
-/* Ethernet Controller Davicom DM9000 */
-#define GPIO_DM9000 101
-#define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000)
-
-/* UCB1400 audio / TS-controller */
-#define GPIO_UCB1400 1
-#define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400)
-
-/* PCMCIA socket Compact Flash */
-#define GPIO_PCD 11 /* PCMCIA Card Detect */
-#define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD)
-#define GPIO_PRDY 13 /* READY / nINT */
-#define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY)
-
-/* MMC socket */
-#define GPIO_MMC_DET 12
-#define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET)
-
-/* DOC NAND chip */
-#define GPIO_DOC_LOCK 94
-#define GPIO_DOC_IRQ 93
-#define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ)
-
-/* SPI interface */
-#define GPIO_SPI 53
-#define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI)
-
-/* LEDS using tx2 / rx2 */
-#define GPIO_SYS_BUSY_LED 46
-#define GPIO_HEARTBEAT_LED 47
-
-/* Off-module PIC on ConXS board */
-#define GPIO_PIC 0
-#define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC)
-
-#ifdef CONFIG_MACH_TRIZEPS_CONXS
-/* for CONXS base board define these registers */
-#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
-#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
-
-#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
-#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
-
-#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
-#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
-
-#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
-#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
-
-#ifndef __ASSEMBLY__
-static inline unsigned short CFSR_readw(void)
-{
- /* [Compact Flash Status Register] is read only */
- return *((unsigned short *)CFSR_P2V(0x0C000000));
-}
-static inline void BCR_writew(unsigned short value)
-{
- /* [Board Control Regsiter] is write only */
- *((unsigned short *)BCR_P2V(0x0E000000)) = value;
-}
-static inline void DCR_writew(unsigned short value)
-{
- /* [Display Control Register] is write only */
- *((unsigned short *)DCR_P2V(0x0E000000)) = value;
-}
-static inline void IRCR_writew(unsigned short value)
-{
- /* [InfraRed data Control Register] is write only */
- *((unsigned short *)IRCR_P2V(0x0E000000)) = value;
-}
-#else
-#define ConXS_CFSR CFSR_P2V(0x0C000000)
-#define ConXS_BCR BCR_P2V(0x0E000000)
-#define ConXS_DCR DCR_P2V(0x0F800000)
-#define ConXS_IRCR IRCR_P2V(0x0F800000)
-#endif
-#else
-/* for whatever baseboard define function registers */
-static inline unsigned short CFSR_readw(void)
-{
- return 0;
-}
-static inline void BCR_writew(unsigned short value)
-{
- ;
-}
-static inline void DCR_writew(unsigned short value)
-{
- ;
-}
-static inline void IRCR_writew(unsigned short value)
-{
- ;
-}
-#endif /* CONFIG_MACH_TRIZEPS_CONXS */
-
-#define ConXS_CFSR_BVD_MASK 0x0003
-#define ConXS_CFSR_BVD1 (1 << 0)
-#define ConXS_CFSR_BVD2 (1 << 1)
-#define ConXS_CFSR_VS_MASK 0x000C
-#define ConXS_CFSR_VS1 (1 << 2)
-#define ConXS_CFSR_VS2 (1 << 3)
-#define ConXS_CFSR_VS_5V (0x3 << 2)
-#define ConXS_CFSR_VS_3V3 0x0
-
-#define ConXS_BCR_S0_POW_EN0 (1 << 0)
-#define ConXS_BCR_S0_POW_EN1 (1 << 1)
-#define ConXS_BCR_L_DISP (1 << 4)
-#define ConXS_BCR_CF_BUF_EN (1 << 5)
-#define ConXS_BCR_CF_RESET (1 << 7)
-#define ConXS_BCR_S0_VCC_3V3 0x1
-#define ConXS_BCR_S0_VCC_5V0 0x2
-#define ConXS_BCR_S0_VPP_12V 0x4
-#define ConXS_BCR_S0_VPP_3V3 0x8
-
-#define ConXS_IRCR_MODE (1 << 0)
-#define ConXS_IRCR_SD (1 << 1)
-
-#endif /* _TRIPEPS4_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
deleted file mode 100644
index 1ed629e38ce6..000000000000
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/uncompress.h
- *
- * Author: Nicolas Pitre
- * Copyright: (C) 2001 MontaVista Software Inc.
- */
-
-#include <linux/serial_reg.h>
-#include <asm/mach-types.h>
-
-#define FFUART_BASE (0x40100000)
-#define BTUART_BASE (0x40200000)
-#define STUART_BASE (0x40700000)
-
-unsigned long uart_base;
-unsigned int uart_shift;
-unsigned int uart_is_pxa;
-
-static inline unsigned char uart_read(int offset)
-{
- return *(volatile unsigned char *)(uart_base + (offset << uart_shift));
-}
-
-static inline void uart_write(unsigned char val, int offset)
-{
- *(volatile unsigned char *)(uart_base + (offset << uart_shift)) = val;
-}
-
-static inline int uart_is_enabled(void)
-{
- /* assume enabled by default for non-PXA uarts */
- return uart_is_pxa ? uart_read(UART_IER) & UART_IER_UUE : 1;
-}
-
-static inline void putc(char c)
-{
- if (!uart_is_enabled())
- return;
-
- while (!(uart_read(UART_LSR) & UART_LSR_THRE))
- barrier();
-
- uart_write(c, UART_TX);
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-static inline void arch_decomp_setup(void)
-{
- /* initialize to default */
- uart_base = FFUART_BASE;
- uart_shift = 2;
- uart_is_pxa = 1;
-
- if (machine_is_littleton() || machine_is_csb726() ||
- machine_is_cm_x300() || machine_is_balloon3())
- uart_base = STUART_BASE;
-
- if (machine_is_arcom_zeus()) {
- uart_base = 0x10000000; /* nCS4 */
- uart_shift = 1;
- uart_is_pxa = 0;
- }
-}
diff --git a/arch/arm/mach-pxa/include/mach/vpac270.h b/arch/arm/mach-pxa/include/mach/vpac270.h
deleted file mode 100644
index 0cd094d8c553..000000000000
--- a/arch/arm/mach-pxa/include/mach/vpac270.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIOs and interrupts for Voipac PXA270
- *
- * Copyright (C) 2010
- * Marek Vasut <marek.vasut@gmail.com>
- */
-
-#ifndef _INCLUDE_VPAC270_H_
-#define _INCLUDE_VPAC270_H_
-
-#define GPIO1_VPAC270_USER_BTN 1
-
-#define GPIO15_VPAC270_LED_ORANGE 15
-
-#define GPIO81_VPAC270_BKL_ON 81
-#define GPIO83_VPAC270_NL_ON 83
-
-#define GPIO52_VPAC270_SD_READONLY 52
-#define GPIO53_VPAC270_SD_DETECT_N 53
-
-#define GPIO84_VPAC270_PCMCIA_CD 84
-#define GPIO35_VPAC270_PCMCIA_RDY 35
-#define GPIO107_VPAC270_PCMCIA_PPEN 107
-#define GPIO11_VPAC270_PCMCIA_RESET 11
-#define GPIO17_VPAC270_CF_CD 17
-#define GPIO12_VPAC270_CF_RDY 12
-#define GPIO16_VPAC270_CF_RESET 16
-
-#define GPIO41_VPAC270_UDC_DETECT 41
-
-#define GPIO114_VPAC270_ETH_IRQ 114
-
-#define GPIO36_VPAC270_IDE_IRQ 36
-
-#define GPIO113_VPAC270_TS_IRQ 113
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h
deleted file mode 100644
index a78b2e28b1db..000000000000
--- a/arch/arm/mach-pxa/include/mach/z2.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/z2.h
- *
- * Author: Ken McGuire
- * Created: Feb 6, 2009
- */
-
-#ifndef ASM_ARCH_ZIPIT2_H
-#define ASM_ARCH_ZIPIT2_H
-
-/* LEDs */
-#define GPIO10_ZIPITZ2_LED_WIFI 10
-#define GPIO85_ZIPITZ2_LED_CHARGED 85
-#define GPIO83_ZIPITZ2_LED_CHARGING 83
-
-/* SD/MMC */
-#define GPIO96_ZIPITZ2_SD_DETECT 96
-
-/* GPIO Buttons */
-#define GPIO1_ZIPITZ2_POWER_BUTTON 1
-#define GPIO98_ZIPITZ2_LID_BUTTON 98
-
-/* Libertas GSPI8686 WiFi */
-#define GPIO14_ZIPITZ2_WIFI_POWER 14
-#define GPIO24_ZIPITZ2_WIFI_CS 24
-#define GPIO36_ZIPITZ2_WIFI_IRQ 36
-
-/* LCD */
-#define GPIO19_ZIPITZ2_LCD_RESET 19
-#define GPIO88_ZIPITZ2_LCD_CS 88
-
-/* MISC GPIOs */
-#define GPIO0_ZIPITZ2_AC_DETECT 0
-#define GPIO37_ZIPITZ2_HEADSET_DETECT 37
-
-#endif
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 74efc3ab595f..a9ef71008147 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -17,13 +17,14 @@
#include <linux/irq.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/soc/pxa/cpu.h>
#include <asm/exception.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "generic.h"
+#include "pxa-regs.h"
#define ICIP (0x000)
#define ICMR (0x004)
@@ -256,8 +257,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
}
pxa_irq_base = io_p2v(res.start);
- if (of_find_property(node, "marvell,intc-priority", NULL))
- cpu_has_ipr = 1;
+ cpu_has_ipr = of_property_read_bool(node, "marvell,intc-priority");
ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
if (ret < 0) {
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/irqs.h
index 22bf536a462d..22bf536a462d 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/irqs.h
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
deleted file mode 100644
index 73f5953b3bb6..000000000000
--- a/arch/arm/mach-pxa/littleton.c
+++ /dev/null
@@ -1,463 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/littleton.c
- *
- * Support for the Marvell Littleton Development Platform.
- *
- * Author: Jason Chagas (largely modified code)
- * Created: Nov 20, 2006
- * Copyright: (C) Copyright 2006 Marvell International Ltd.
- *
- * 2007-11-22 modified to align with latest kernel
- * eric miao <eric.miao@marvell.com>
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/gpio/machine.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/smc91x.h>
-#include <linux/i2c.h>
-#include <linux/leds.h>
-#include <linux/mfd/da903x.h>
-#include <linux/platform_data/max732x.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include "pxa300.h"
-#include "devices.h"
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include "littleton.h"
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-
-#include "generic.h"
-
-/* Littleton MFP configurations */
-static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
- /* LCD */
- GPIO54_LCD_LDD_0,
- GPIO55_LCD_LDD_1,
- GPIO56_LCD_LDD_2,
- GPIO57_LCD_LDD_3,
- GPIO58_LCD_LDD_4,
- GPIO59_LCD_LDD_5,
- GPIO60_LCD_LDD_6,
- GPIO61_LCD_LDD_7,
- GPIO62_LCD_LDD_8,
- GPIO63_LCD_LDD_9,
- GPIO64_LCD_LDD_10,
- GPIO65_LCD_LDD_11,
- GPIO66_LCD_LDD_12,
- GPIO67_LCD_LDD_13,
- GPIO68_LCD_LDD_14,
- GPIO69_LCD_LDD_15,
- GPIO70_LCD_LDD_16,
- GPIO71_LCD_LDD_17,
- GPIO72_LCD_FCLK,
- GPIO73_LCD_LCLK,
- GPIO74_LCD_PCLK,
- GPIO75_LCD_BIAS,
-
- /* SSP2 */
- GPIO25_SSP2_SCLK,
- GPIO27_SSP2_TXD,
- GPIO17_GPIO, /* SFRM as chip-select */
-
- /* Debug Ethernet */
- GPIO90_GPIO,
-
- /* Keypad */
- GPIO107_KP_DKIN_0,
- GPIO108_KP_DKIN_1,
- GPIO115_KP_MKIN_0,
- GPIO116_KP_MKIN_1,
- GPIO117_KP_MKIN_2,
- GPIO118_KP_MKIN_3,
- GPIO119_KP_MKIN_4,
- GPIO120_KP_MKIN_5,
- GPIO121_KP_MKOUT_0,
- GPIO122_KP_MKOUT_1,
- GPIO123_KP_MKOUT_2,
- GPIO124_KP_MKOUT_3,
- GPIO125_KP_MKOUT_4,
-
- /* MMC1 */
- GPIO3_MMC1_DAT0,
- GPIO4_MMC1_DAT1,
- GPIO5_MMC1_DAT2,
- GPIO6_MMC1_DAT3,
- GPIO7_MMC1_CLK,
- GPIO8_MMC1_CMD,
- GPIO15_GPIO, /* card detect */
-
- /* UART3 */
- GPIO107_UART3_CTS,
- GPIO108_UART3_RTS,
- GPIO109_UART3_TXD,
- GPIO110_UART3_RXD,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (LITTLETON_ETH_PHYS + 0x300),
- .end = (LITTLETON_ETH_PHYS + 0xfffff),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
- .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- }
-};
-
-static struct smc91x_platdata littleton_smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT |
- SMC91X_NOWAIT | SMC91X_USE_DMA,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &littleton_smc91x_info,
- },
-};
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
- [0] = {
- /* VGA */
- .pixclock = 38250,
- .xres = 480,
- .yres = 640,
- .bpp = 16,
- .hsync_len = 8,
- .left_margin = 8,
- .right_margin = 24,
- .vsync_len = 2,
- .upper_margin = 2,
- .lower_margin = 4,
- .sync = 0,
- },
- [1] = {
- /* QVGA */
- .pixclock = 153000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 8,
- .left_margin = 8,
- .right_margin = 88,
- .vsync_len = 2,
- .upper_margin = 2,
- .lower_margin = 2,
- .sync = 0,
- },
-};
-
-static struct pxafb_mach_info littleton_lcd_info = {
- .modes = tpo_tdo24mtea1_modes,
- .num_modes = 2,
- .lcd_conn = LCD_COLOR_TFT_16BPP,
-};
-
-static void __init littleton_init_lcd(void)
-{
- pxa_set_fb_info(NULL, &littleton_lcd_info);
-}
-#else
-static inline void littleton_init_lcd(void) {};
-#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
-
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_controller littleton_spi_info = {
- .num_chipselect = 1,
-};
-
-static struct pxa2xx_spi_chip littleton_tdo24m_chip = {
- .rx_threshold = 1,
- .tx_threshold = 1,
-};
-
-static struct spi_board_info littleton_spi_devices[] __initdata = {
- {
- .modalias = "tdo24m",
- .max_speed_hz = 1000000,
- .bus_num = 2,
- .chip_select = 0,
- .controller_data= &littleton_tdo24m_chip,
- },
-};
-
-static struct gpiod_lookup_table littleton_spi_gpio_table = {
- .dev_id = "pxa2xx-spi.2",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", LITTLETON_GPIO_LCD_CS, "cs", 0, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init littleton_init_spi(void)
-{
- gpiod_add_lookup_table(&littleton_spi_gpio_table);
- pxa2xx_set_spi_info(2, &littleton_spi_info);
- spi_register_board_info(ARRAY_AND_SIZE(littleton_spi_devices));
-}
-#else
-static inline void littleton_init_spi(void) {}
-#endif
-
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int littleton_matrix_key_map[] = {
- /* KEY(row, col, key_code) */
- KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
- KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7),
- KEY(1, 2, KEY_8), KEY(2, 2, KEY_9),
-
- KEY(0, 3, KEY_KPASTERISK), /* * */
- KEY(2, 3, KEY_KPDOT), /* # */
-
- KEY(5, 4, KEY_ENTER),
-
- KEY(5, 0, KEY_UP),
- KEY(5, 1, KEY_DOWN),
- KEY(5, 2, KEY_LEFT),
- KEY(5, 3, KEY_RIGHT),
- KEY(3, 2, KEY_HOME),
- KEY(4, 1, KEY_END),
- KEY(3, 3, KEY_BACK),
-
- KEY(4, 0, KEY_SEND),
- KEY(4, 2, KEY_VOLUMEUP),
- KEY(4, 3, KEY_VOLUMEDOWN),
-
- KEY(3, 0, KEY_F22), /* soft1 */
- KEY(3, 1, KEY_F23), /* soft2 */
-};
-
-static struct matrix_keymap_data littleton_matrix_keymap_data = {
- .keymap = littleton_matrix_key_map,
- .keymap_size = ARRAY_SIZE(littleton_matrix_key_map),
-};
-
-static struct pxa27x_keypad_platform_data littleton_keypad_info = {
- .matrix_key_rows = 6,
- .matrix_key_cols = 5,
- .matrix_keymap_data = &littleton_matrix_keymap_data,
-
- .enable_rotary0 = 1,
- .rotary0_up_key = KEY_UP,
- .rotary0_down_key = KEY_DOWN,
-
- .debounce_interval = 30,
-};
-static void __init littleton_init_keypad(void)
-{
- pxa_set_keypad_info(&littleton_keypad_info);
-}
-#else
-static inline void littleton_init_keypad(void) {}
-#endif
-
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data littleton_mci_platform_data = {
- .detect_delay_ms = 200,
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table littleton_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on MFP (gpio-pxa) GPIO 15 */
- GPIO_LOOKUP("gpio-pxa", MFP_PIN_GPIO15,
- "cd", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init littleton_init_mmc(void)
-{
- gpiod_add_lookup_table(&littleton_mci_gpio_table);
- pxa_set_mci_info(&littleton_mci_platform_data);
-}
-#else
-static inline void littleton_init_mmc(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
-static struct mtd_partition littleton_nand_partitions[] = {
- [0] = {
- .name = "Bootloader",
- .offset = 0,
- .size = 0x060000,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- [1] = {
- .name = "Kernel",
- .offset = 0x060000,
- .size = 0x200000,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- [2] = {
- .name = "Filesystem",
- .offset = 0x0260000,
- .size = 0x3000000, /* 48M - rootfs */
- },
- [3] = {
- .name = "MassStorage",
- .offset = 0x3260000,
- .size = 0x3d40000,
- },
- [4] = {
- .name = "BBT",
- .offset = 0x6FA0000,
- .size = 0x80000,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* NOTE: we reserve some blocks at the end of the NAND flash for
- * bad block management, and the max number of relocation blocks
- * differs on different platforms. Please take care with it when
- * defining the partition table.
- */
-};
-
-static struct pxa3xx_nand_platform_data littleton_nand_info = {
- .parts = littleton_nand_partitions,
- .nr_parts = ARRAY_SIZE(littleton_nand_partitions),
-};
-
-static void __init littleton_init_nand(void)
-{
- pxa3xx_set_nand_info(&littleton_nand_info);
-}
-#else
-static inline void littleton_init_nand(void) {}
-#endif /* IS_ENABLED(CONFIG_MTD_NAND_MARVELL) */
-
-#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
-static struct led_info littleton_da9034_leds[] = {
- [0] = {
- .name = "littleton:keypad1",
- .flags = DA9034_LED_RAMP,
- },
- [1] = {
- .name = "littleton:keypad2",
- .flags = DA9034_LED_RAMP,
- },
- [2] = {
- .name = "littleton:vibra",
- .flags = 0,
- },
-};
-
-static struct da9034_touch_pdata littleton_da9034_touch = {
- .x_inverted = 1,
- .interval_ms = 20,
-};
-
-static struct da903x_subdev_info littleton_da9034_subdevs[] = {
- {
- .name = "da903x-led",
- .id = DA9034_ID_LED_1,
- .platform_data = &littleton_da9034_leds[0],
- }, {
- .name = "da903x-led",
- .id = DA9034_ID_LED_2,
- .platform_data = &littleton_da9034_leds[1],
- }, {
- .name = "da903x-led",
- .id = DA9034_ID_VIBRA,
- .platform_data = &littleton_da9034_leds[2],
- }, {
- .name = "da903x-backlight",
- .id = DA9034_ID_WLED,
- }, {
- .name = "da9034-touch",
- .id = DA9034_ID_TOUCH,
- .platform_data = &littleton_da9034_touch,
- },
-};
-
-static struct da903x_platform_data littleton_da9034_info = {
- .num_subdevs = ARRAY_SIZE(littleton_da9034_subdevs),
- .subdevs = littleton_da9034_subdevs,
-};
-
-static struct max732x_platform_data littleton_max7320_info = {
- .gpio_base = EXT0_GPIO_BASE,
-};
-
-static struct i2c_board_info littleton_i2c_info[] = {
- [0] = {
- .type = "da9034",
- .addr = 0x34,
- .platform_data = &littleton_da9034_info,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO18)),
- },
- [1] = {
- .type = "max7320",
- .addr = 0x50,
- .platform_data = &littleton_max7320_info,
- },
-};
-
-static void __init littleton_init_i2c(void)
-{
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(littleton_i2c_info));
-}
-#else
-static inline void littleton_init_i2c(void) {}
-#endif /* CONFIG_I2C_PXA || CONFIG_I2C_PXA_MODULE */
-
-static void __init littleton_init(void)
-{
- /* initialize MFP configurations */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- /*
- * Note: we depend bootloader set the correct
- * value to MSC register for SMC91x.
- */
- platform_device_register(&smc91x_device);
-
- littleton_init_spi();
- littleton_init_i2c();
- littleton_init_mmc();
- littleton_init_lcd();
- littleton_init_keypad();
- littleton_init_nand();
-}
-
-MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = LITTLETON_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = littleton_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/littleton.h b/arch/arm/mach-pxa/littleton.h
deleted file mode 100644
index a0a8d2bf9d71..000000000000
--- a/arch/arm/mach-pxa/littleton.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_LITTLETON_H
-#define __ASM_ARCH_LITTLETON_H
-
-#define LITTLETON_ETH_PHYS 0x30000000
-
-#define LITTLETON_GPIO_LCD_CS (17)
-
-#define EXT0_GPIO_BASE (PXA_NR_BUILTIN_GPIO)
-#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x))
-
-#define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8)
-
-#endif /* __ASM_ARCH_LITTLETON_H */
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
deleted file mode 100644
index 6fc40bc06910..000000000000
--- a/arch/arm/mach-pxa/lpd270.c
+++ /dev/null
@@ -1,518 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/lpd270.c
- *
- * Support for the LogicPD PXA270 Card Engine.
- * Derived from the mainstone code, which carries these notices:
- *
- * Author: Nicolas Pitre
- * Created: Nov 05, 2002
- * Copyright: MontaVista Software Inc.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/bitops.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/smc91x.h>
-
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <linux/sizes.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/flash.h>
-
-#include "pxa27x.h"
-#include "lpd270.h"
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/smemc.h>
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned long lpd270_pin_config[] __initdata = {
- /* Chip Selects */
- GPIO15_nCS_1, /* Mainboard Flash */
- GPIO78_nCS_2, /* CPLD + Ethernet */
-
- /* LCD - 16bpp Active TFT */
- GPIO58_LCD_LDD_0,
- GPIO59_LCD_LDD_1,
- GPIO60_LCD_LDD_2,
- GPIO61_LCD_LDD_3,
- GPIO62_LCD_LDD_4,
- GPIO63_LCD_LDD_5,
- GPIO64_LCD_LDD_6,
- GPIO65_LCD_LDD_7,
- GPIO66_LCD_LDD_8,
- GPIO67_LCD_LDD_9,
- GPIO68_LCD_LDD_10,
- GPIO69_LCD_LDD_11,
- GPIO70_LCD_LDD_12,
- GPIO71_LCD_LDD_13,
- GPIO72_LCD_LDD_14,
- GPIO73_LCD_LDD_15,
- GPIO74_LCD_FCLK,
- GPIO75_LCD_LCLK,
- GPIO76_LCD_PCLK,
- GPIO77_LCD_BIAS,
- GPIO16_PWM0_OUT, /* Backlight */
-
- /* USB Host */
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO45_AC97_SYSCLK,
-
- GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
-};
-
-static unsigned int lpd270_irq_enabled;
-
-static void lpd270_mask_irq(struct irq_data *d)
-{
- int lpd270_irq = d->irq - LPD270_IRQ(0);
-
- __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
-
- lpd270_irq_enabled &= ~(1 << lpd270_irq);
- __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
-}
-
-static void lpd270_unmask_irq(struct irq_data *d)
-{
- int lpd270_irq = d->irq - LPD270_IRQ(0);
-
- lpd270_irq_enabled |= 1 << lpd270_irq;
- __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
-}
-
-static struct irq_chip lpd270_irq_chip = {
- .name = "CPLD",
- .irq_ack = lpd270_mask_irq,
- .irq_mask = lpd270_mask_irq,
- .irq_unmask = lpd270_unmask_irq,
-};
-
-static void lpd270_irq_handler(struct irq_desc *desc)
-{
- unsigned int irq;
- unsigned long pending;
-
- pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
- do {
- /* clear useless edge notification */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
- if (likely(pending)) {
- irq = LPD270_IRQ(0) + __ffs(pending);
- generic_handle_irq(irq);
-
- pending = __raw_readw(LPD270_INT_STATUS) &
- lpd270_irq_enabled;
- }
- } while (pending);
-}
-
-static void __init lpd270_init_irq(void)
-{
- int irq;
-
- pxa27x_init_irq();
-
- __raw_writew(0, LPD270_INT_MASK);
- __raw_writew(0, LPD270_INT_STATUS);
-
- /* setup extra LogicPD PXA270 irqs */
- for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
- irq_set_chip_and_handler(irq, &lpd270_irq_chip,
- handle_level_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
- irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
- irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
-}
-
-
-#ifdef CONFIG_PM
-static void lpd270_irq_resume(void)
-{
- __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
-}
-
-static struct syscore_ops lpd270_irq_syscore_ops = {
- .resume = lpd270_irq_resume,
-};
-
-static int __init lpd270_irq_device_init(void)
-{
- if (machine_is_logicpd_pxa270()) {
- register_syscore_ops(&lpd270_irq_syscore_ops);
- return 0;
- }
- return -ENODEV;
-}
-
-device_initcall(lpd270_irq_device_init);
-#endif
-
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = LPD270_ETH_PHYS,
- .end = (LPD270_ETH_PHYS + 0xfffff),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = LPD270_ETHERNET_IRQ,
- .end = LPD270_ETHERNET_IRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-struct smc91x_platdata smc91x_platdata = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev.platform_data = &smc91x_platdata,
-};
-
-static struct resource lpd270_flash_resources[] = {
- [0] = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_CS1_PHYS,
- .end = PXA_CS1_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct mtd_partition lpd270_flash0_partitions[] = {
- {
- .name = "Bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- }, {
- .name = "Kernel",
- .size = 0x00400000,
- .offset = 0x00040000,
- }, {
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00440000
- },
-};
-
-static struct flash_platform_data lpd270_flash_data[2] = {
- {
- .name = "processor-flash",
- .map_name = "cfi_probe",
- .parts = lpd270_flash0_partitions,
- .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
- }, {
- .name = "mainboard-flash",
- .map_name = "cfi_probe",
- .parts = NULL,
- .nr_parts = 0,
- }
-};
-
-static struct platform_device lpd270_flash_device[2] = {
- {
- .name = "pxa2xx-flash",
- .id = 0,
- .dev = {
- .platform_data = &lpd270_flash_data[0],
- },
- .resource = &lpd270_flash_resources[0],
- .num_resources = 1,
- }, {
- .name = "pxa2xx-flash",
- .id = 1,
- .dev = {
- .platform_data = &lpd270_flash_data[1],
- },
- .resource = &lpd270_flash_resources[1],
- .num_resources = 1,
- },
-};
-
-static struct pwm_lookup lpd270_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data lpd270_backlight_data = {
- .max_brightness = 1,
- .dft_brightness = 1,
-};
-
-static struct platform_device lpd270_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &lpd270_backlight_data,
- },
-};
-
-/* 5.7" TFT QVGA (LoLo display number 1) */
-static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
- .pixclock = 150000,
- .xres = 320,
- .yres = 240,
- .bpp = 16,
- .hsync_len = 0x14,
- .left_margin = 0x28,
- .right_margin = 0x0a,
- .vsync_len = 0x02,
- .upper_margin = 0x08,
- .lower_margin = 0x14,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info sharp_lq057q3dc02 = {
- .modes = &sharp_lq057q3dc02_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_ALTERNATE_MAPPING,
-};
-
-/* 12.1" TFT SVGA (LoLo display number 2) */
-static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
- .pixclock = 50000,
- .xres = 800,
- .yres = 600,
- .bpp = 16,
- .hsync_len = 0x05,
- .left_margin = 0x52,
- .right_margin = 0x05,
- .vsync_len = 0x04,
- .upper_margin = 0x14,
- .lower_margin = 0x0a,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info sharp_lq121s1dg31 = {
- .modes = &sharp_lq121s1dg31_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_ALTERNATE_MAPPING,
-};
-
-/* 3.6" TFT QVGA (LoLo display number 3) */
-static struct pxafb_mode_info sharp_lq036q1da01_mode = {
- .pixclock = 150000,
- .xres = 320,
- .yres = 240,
- .bpp = 16,
- .hsync_len = 0x0e,
- .left_margin = 0x04,
- .right_margin = 0x0a,
- .vsync_len = 0x03,
- .upper_margin = 0x03,
- .lower_margin = 0x03,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info sharp_lq036q1da01 = {
- .modes = &sharp_lq036q1da01_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_ALTERNATE_MAPPING,
-};
-
-/* 6.4" TFT VGA (LoLo display number 5) */
-static struct pxafb_mode_info sharp_lq64d343_mode = {
- .pixclock = 25000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 0x31,
- .left_margin = 0x89,
- .right_margin = 0x19,
- .vsync_len = 0x12,
- .upper_margin = 0x22,
- .lower_margin = 0x00,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info sharp_lq64d343 = {
- .modes = &sharp_lq64d343_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_ALTERNATE_MAPPING,
-};
-
-/* 10.4" TFT VGA (LoLo display number 7) */
-static struct pxafb_mode_info sharp_lq10d368_mode = {
- .pixclock = 25000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 0x31,
- .left_margin = 0x89,
- .right_margin = 0x19,
- .vsync_len = 0x12,
- .upper_margin = 0x22,
- .lower_margin = 0x00,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info sharp_lq10d368 = {
- .modes = &sharp_lq10d368_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_ALTERNATE_MAPPING,
-};
-
-/* 3.5" TFT QVGA (LoLo display number 8) */
-static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
- .pixclock = 150000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 0x0e,
- .left_margin = 0x0a,
- .right_margin = 0x0a,
- .vsync_len = 0x03,
- .upper_margin = 0x05,
- .lower_margin = 0x14,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info sharp_lq035q7db02_20 = {
- .modes = &sharp_lq035q7db02_20_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_ALTERNATE_MAPPING,
-};
-
-static struct pxafb_mach_info *lpd270_lcd_to_use;
-
-static int __init lpd270_set_lcd(char *str)
-{
- if (!strncasecmp(str, "lq057q3dc02", 11)) {
- lpd270_lcd_to_use = &sharp_lq057q3dc02;
- } else if (!strncasecmp(str, "lq121s1dg31", 11)) {
- lpd270_lcd_to_use = &sharp_lq121s1dg31;
- } else if (!strncasecmp(str, "lq036q1da01", 11)) {
- lpd270_lcd_to_use = &sharp_lq036q1da01;
- } else if (!strncasecmp(str, "lq64d343", 8)) {
- lpd270_lcd_to_use = &sharp_lq64d343;
- } else if (!strncasecmp(str, "lq10d368", 8)) {
- lpd270_lcd_to_use = &sharp_lq10d368;
- } else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
- lpd270_lcd_to_use = &sharp_lq035q7db02_20;
- } else {
- printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
- }
-
- return 1;
-}
-
-__setup("lcd=", lpd270_set_lcd);
-
-static struct platform_device *platform_devices[] __initdata = {
- &smc91x_device,
- &lpd270_backlight_device,
- &lpd270_flash_device[0],
- &lpd270_flash_device[1],
-};
-
-static struct pxaohci_platform_data lpd270_ohci_platform_data = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-static void __init lpd270_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
- lpd270_flash_data[1].width = 4;
-
- /*
- * System bus arbiter setting:
- * - Core_Park
- * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
- */
- ARB_CNTRL = ARB_CORE_PARK | 0x234;
-
- pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
- pxa_set_ac97_info(NULL);
-
- if (lpd270_lcd_to_use != NULL)
- pxa_set_fb_info(NULL, lpd270_lcd_to_use);
-
- pxa_set_ohci_info(&lpd270_ohci_platform_data);
-}
-
-
-static struct map_desc lpd270_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)LPD270_CPLD_VIRT,
- .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
- .length = LPD270_CPLD_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-static void __init lpd270_map_io(void)
-{
- pxa27x_map_io();
- iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
-
- /* for use I SRAM as framebuffer. */
- PSLR |= 0x00000F04;
- PCFR = 0x00000066;
-}
-
-MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
- /* Maintainer: Peter Barada */
- .atag_offset = 0x100,
- .map_io = lpd270_map_io,
- .nr_irqs = LPD270_NR_IRQS,
- .init_irq = lpd270_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = lpd270_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/lpd270.h b/arch/arm/mach-pxa/lpd270.h
deleted file mode 100644
index 4b096fb9d61f..000000000000
--- a/arch/arm/mach-pxa/lpd270.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/lpd270.h
- *
- * Author: Lennert Buytenhek
- * Created: Feb 10, 2006
- */
-
-#ifndef __ASM_ARCH_LPD270_H
-#define __ASM_ARCH_LPD270_H
-
-#define LPD270_CPLD_PHYS PXA_CS2_PHYS
-#define LPD270_CPLD_VIRT IOMEM(0xf0000000)
-#define LPD270_CPLD_SIZE 0x00100000
-
-#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000)
-
-/* CPLD registers */
-#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x))
-#define LPD270_CONTROL LPD270_CPLD_REG(0x00)
-#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04)
-#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08)
-#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14)
-#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20)
-#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24)
-#define LPD270_EGPIO LPD270_CPLD_REG(0x30)
-#define LPD270_INT_MASK LPD270_CPLD_REG(0x40)
-#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50)
-
-#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
-#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
-#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */
-
-#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
-#define LPD270_USBC_IRQ LPD270_IRQ(2)
-#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
-#define LPD270_AC97_IRQ LPD270_IRQ(4)
-#define LPD270_NR_IRQS (IRQ_BOARD_START + 5)
-
-#endif
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
deleted file mode 100644
index e2411971422d..000000000000
--- a/arch/arm/mach-pxa/lubbock.c
+++ /dev/null
@@ -1,640 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/lubbock.c
- *
- * Support for the Intel DBPXA250 Development Platform.
- *
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software Inc.
- */
-#include <linux/clkdev.h>
-#include <linux/gpio.h>
-#include <linux/gpio/gpio-reg.h>
-#include <linux/gpio/machine.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/major.h>
-#include <linux/fb.h>
-#include <linux/interrupt.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/smc91x.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/spi/pxa2xx_spi.h>
-
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <linux/sizes.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/flash.h>
-
-#include <asm/hardware/sa1111.h>
-
-#include "pxa25x.h"
-#include <mach/audio.h>
-#include <mach/lubbock.h>
-#include "udc.h"
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include "pm.h"
-#include <mach/smemc.h>
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned long lubbock_pin_config[] __initdata = {
- GPIO15_nCS_1, /* CS1 - Flash */
- GPIO78_nCS_2, /* CS2 - Baseboard FGPA */
- GPIO79_nCS_3, /* CS3 - SMC ethernet */
- GPIO80_nCS_4, /* CS4 - SA1111 */
-
- /* SSP data pins */
- GPIO23_SSP1_SCLK,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* LCD - 16bpp DSTN */
- GPIOxx_LCD_DSTN_16BPP,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* PC Card */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO8_MMC_CS0,
-
- /* SA1111 chip */
- GPIO11_3_6MHz,
-
- /* wakeup */
- GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-#define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
-
-void lubbock_set_hexled(uint32_t value)
-{
- LUB_HEXLED = value;
-}
-
-static struct gpio_chip *lubbock_misc_wr_gc;
-
-static void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
-{
- unsigned long m = mask, v = set;
- lubbock_misc_wr_gc->set_multiple(lubbock_misc_wr_gc, &m, &v);
-}
-
-static int lubbock_udc_is_connected(void)
-{
- return (LUB_MISC_RD & (1 << 9)) == 0;
-}
-
-static struct pxa2xx_udc_mach_info udc_info __initdata = {
- .udc_is_connected = lubbock_udc_is_connected,
- // no D+ pullup; lubbock can't connect/disconnect in software
-};
-
-/* GPIOs for SA1111 PCMCIA */
-static struct gpiod_lookup_table sa1111_pcmcia_gpio_table = {
- .dev_id = "1800",
- .table = {
- { "sa1111", 0, "a0vpp", GPIO_ACTIVE_HIGH },
- { "sa1111", 1, "a1vpp", GPIO_ACTIVE_HIGH },
- { "sa1111", 2, "a0vcc", GPIO_ACTIVE_HIGH },
- { "sa1111", 3, "a1vcc", GPIO_ACTIVE_HIGH },
- { "lubbock", 14, "b0vcc", GPIO_ACTIVE_HIGH },
- { "lubbock", 15, "b1vcc", GPIO_ACTIVE_HIGH },
- { },
- },
-};
-
-static void lubbock_init_pcmcia(void)
-{
- struct clk *clk;
-
- gpiod_add_lookup_table(&sa1111_pcmcia_gpio_table);
-
- /* Add an alias for the SA1111 PCMCIA clock */
- clk = clk_get_sys("pxa2xx-pcmcia", NULL);
- if (!IS_ERR(clk)) {
- clkdev_create(clk, NULL, "1800");
- clk_put(clk);
- }
-}
-
-static struct resource sa1111_resources[] = {
- [0] = {
- .start = 0x10000000,
- .end = 0x10001fff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = LUBBOCK_SA1111_IRQ,
- .end = LUBBOCK_SA1111_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct sa1111_platform_data sa1111_info = {
- .irq_base = LUBBOCK_SA1111_IRQ_BASE,
- .disable_devs = SA1111_DEVID_SAC,
-};
-
-static struct platform_device sa1111_device = {
- .name = "sa1111",
- .id = -1,
- .num_resources = ARRAY_SIZE(sa1111_resources),
- .resource = sa1111_resources,
- .dev = {
- .platform_data = &sa1111_info,
- },
-};
-
-/* ADS7846 is connected through SSP ... and if your board has J5 populated,
- * you can select it to replace the ucb1400 by switching the touchscreen cable
- * (to J5) and poking board registers (as done below). Else it's only useful
- * for the temperature sensors.
- */
-static struct pxa2xx_spi_controller pxa_ssp_master_info = {
- .num_chipselect = 1,
-};
-
-static int lubbock_ads7846_pendown_state(void)
-{
- /* TS_BUSY is bit 8 in LUB_MISC_RD, but pendown is irq-only */
- return 0;
-}
-
-static struct ads7846_platform_data ads_info = {
- .model = 7846,
- .vref_delay_usecs = 100, /* internal, no cap */
- .get_pendown_state = lubbock_ads7846_pendown_state,
- // .x_plate_ohms = 500, /* GUESS! */
- // .y_plate_ohms = 500, /* GUESS! */
-};
-
-static struct gpiod_lookup_table ads7846_cs_gpios = {
- .dev_id = "ads7846",
- .table = {
- GPIO_LOOKUP("lubbock", 11, "cs", GPIO_ACTIVE_LOW),
- {}
- },
-};
-
-static struct pxa2xx_spi_chip ads_hw = {
- .tx_threshold = 1,
- .rx_threshold = 2,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = { {
- .modalias = "ads7846",
- .platform_data = &ads_info,
- .controller_data = &ads_hw,
- .irq = LUBBOCK_BB_IRQ,
- .max_speed_hz = 120000 /* max sample rate at 3V */
- * 26 /* command + data + overhead */,
- .bus_num = 1,
- .chip_select = 0,
-},
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .name = "smc91x-regs",
- .start = 0x0c000c00,
- .end = 0x0c0fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = LUBBOCK_ETH_IRQ,
- .end = LUBBOCK_ETH_IRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
- [2] = {
- .name = "smc91x-attrib",
- .start = 0x0e000000,
- .end = 0x0e0fffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct smc91x_platdata lubbock_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_2,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &lubbock_smc91x_info,
- },
-};
-
-static struct resource flash_resources[] = {
- [0] = {
- .start = 0x00000000,
- .end = SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x04000000,
- .end = 0x04000000 + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct mtd_partition lubbock_partitions[] = {
- {
- .name = "Bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- },{
- .name = "Kernel",
- .size = 0x00100000,
- .offset = 0x00040000,
- },{
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00140000
- }
-};
-
-static struct flash_platform_data lubbock_flash_data[2] = {
- {
- .map_name = "cfi_probe",
- .parts = lubbock_partitions,
- .nr_parts = ARRAY_SIZE(lubbock_partitions),
- }, {
- .map_name = "cfi_probe",
- .parts = NULL,
- .nr_parts = 0,
- }
-};
-
-static struct platform_device lubbock_flash_device[2] = {
- {
- .name = "pxa2xx-flash",
- .id = 0,
- .dev = {
- .platform_data = &lubbock_flash_data[0],
- },
- .resource = &flash_resources[0],
- .num_resources = 1,
- },
- {
- .name = "pxa2xx-flash",
- .id = 1,
- .dev = {
- .platform_data = &lubbock_flash_data[1],
- },
- .resource = &flash_resources[1],
- .num_resources = 1,
- },
-};
-
-static struct resource lubbock_cplds_resources[] = {
- [0] = {
- .start = LUBBOCK_FPGA_PHYS + 0xc0,
- .end = LUBBOCK_FPGA_PHYS + 0xe0 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(0),
- .end = PXA_GPIO_TO_IRQ(0),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
- [2] = {
- .start = LUBBOCK_IRQ(0),
- .end = LUBBOCK_IRQ(6),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device lubbock_cplds_device = {
- .name = "pxa_cplds_irqs",
- .id = -1,
- .resource = &lubbock_cplds_resources[0],
- .num_resources = 3,
-};
-
-
-static struct platform_device *devices[] __initdata = {
- &sa1111_device,
- &smc91x_device,
- &lubbock_flash_device[0],
- &lubbock_flash_device[1],
- &lubbock_cplds_device,
-};
-
-static struct pxafb_mode_info sharp_lm8v31_mode = {
- .pixclock = 270000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 1,
- .left_margin = 3,
- .right_margin = 3,
- .vsync_len = 1,
- .upper_margin = 0,
- .lower_margin = 0,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info sharp_lm8v31 = {
- .modes = &sharp_lm8v31_mode,
- .num_modes = 1,
- .cmap_inverse = 0,
- .cmap_static = 0,
- .lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_AC_BIAS_FREQ(255),
-};
-
-#define MMC_POLL_RATE msecs_to_jiffies(1000)
-
-static irq_handler_t mmc_detect_int;
-static void *mmc_detect_int_data;
-static struct timer_list mmc_timer;
-
-static void lubbock_mmc_poll(struct timer_list *unused)
-{
- unsigned long flags;
-
- /* clear any previous irq state, then ... */
- local_irq_save(flags);
- LUB_IRQ_SET_CLR &= ~(1 << 0);
- local_irq_restore(flags);
-
- /* poll until mmc/sd card is removed */
- if (LUB_IRQ_SET_CLR & (1 << 0))
- mod_timer(&mmc_timer, jiffies + MMC_POLL_RATE);
- else {
- (void) mmc_detect_int(LUBBOCK_SD_IRQ, mmc_detect_int_data);
- enable_irq(LUBBOCK_SD_IRQ);
- }
-}
-
-static irqreturn_t lubbock_detect_int(int irq, void *data)
-{
- /* IRQ is level triggered; disable, and poll for removal */
- disable_irq(irq);
- mod_timer(&mmc_timer, jiffies + MMC_POLL_RATE);
-
- return mmc_detect_int(irq, data);
-}
-
-static int lubbock_mci_init(struct device *dev,
- irq_handler_t detect_int,
- void *data)
-{
- /* detect card insert/eject */
- mmc_detect_int = detect_int;
- mmc_detect_int_data = data;
- timer_setup(&mmc_timer, lubbock_mmc_poll, 0);
- return request_irq(LUBBOCK_SD_IRQ, lubbock_detect_int,
- 0, "lubbock-sd-detect", data);
-}
-
-static int lubbock_mci_get_ro(struct device *dev)
-{
- return (LUB_MISC_RD & (1 << 2)) != 0;
-}
-
-static void lubbock_mci_exit(struct device *dev, void *data)
-{
- free_irq(LUBBOCK_SD_IRQ, data);
- del_timer_sync(&mmc_timer);
-}
-
-static struct pxamci_platform_data lubbock_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .detect_delay_ms = 10,
- .init = lubbock_mci_init,
- .get_ro = lubbock_mci_get_ro,
- .exit = lubbock_mci_exit,
-};
-
-static void lubbock_irda_transceiver_mode(struct device *dev, int mode)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- if (mode & IR_SIRMODE) {
- lubbock_set_misc_wr(BIT(4), 0);
- } else if (mode & IR_FIRMODE) {
- lubbock_set_misc_wr(BIT(4), BIT(4));
- }
- pxa2xx_transceiver_mode(dev, mode);
- local_irq_restore(flags);
-}
-
-static struct pxaficp_platform_data lubbock_ficp_platform_data = {
- .gpio_pwdown = -1,
- .transceiver_cap = IR_SIRMODE | IR_FIRMODE,
- .transceiver_mode = lubbock_irda_transceiver_mode,
-};
-
-static void __init lubbock_init(void)
-{
- int flashboot = (LUB_CONF_SWITCHES & 1);
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));
-
- lubbock_misc_wr_gc = gpio_reg_init(NULL, (void *)&LUB_MISC_WR,
- -1, 16, "lubbock", 0, LUB_MISC_WR,
- NULL, NULL, NULL);
- if (IS_ERR(lubbock_misc_wr_gc)) {
- pr_err("Lubbock: unable to register lubbock GPIOs: %ld\n",
- PTR_ERR(lubbock_misc_wr_gc));
- lubbock_misc_wr_gc = NULL;
- }
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- lubbock_init_pcmcia();
-
- clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL);
- pxa_set_udc_info(&udc_info);
- pxa_set_fb_info(NULL, &sharp_lm8v31);
- pxa_set_mci_info(&lubbock_mci_platform_data);
- pxa_set_ficp_info(&lubbock_ficp_platform_data);
- pxa_set_ac97_info(NULL);
-
- lubbock_flash_data[0].width = lubbock_flash_data[1].width =
- (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
- /* Compensate for the nROMBT switch which swaps the flash banks */
- printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n",
- flashboot?"Flash":"ROM", flashboot);
-
- lubbock_flash_data[flashboot^1].name = "application-flash";
- lubbock_flash_data[flashboot].name = "boot-rom";
- (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-
- gpiod_add_lookup_table(&ads7846_cs_gpios);
-
- pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
- spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-}
-
-static struct map_desc lubbock_io_desc[] __initdata = {
- { /* CPLD */
- .virtual = LUBBOCK_FPGA_VIRT,
- .pfn = __phys_to_pfn(LUBBOCK_FPGA_PHYS),
- .length = 0x00100000,
- .type = MT_DEVICE
- }
-};
-
-static void __init lubbock_map_io(void)
-{
- pxa25x_map_io();
- iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
-
- PCFR |= PCFR_OPDE;
-}
-
-/*
- * Driver for the 8 discrete LEDs available for general use:
- * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
- * so be sure to not monkey with them here.
- */
-
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-struct lubbock_led {
- struct led_classdev cdev;
- u8 mask;
-};
-
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
- const char *name;
- const char *trigger;
-} lubbock_leds[] = {
- { "lubbock:D28", "default-on", },
- { "lubbock:D27", "cpu0", },
- { "lubbock:D26", "heartbeat" },
- { "lubbock:D25", },
- { "lubbock:D24", },
- { "lubbock:D23", },
- { "lubbock:D22", },
- { "lubbock:D21", },
-};
-
-static void lubbock_led_set(struct led_classdev *cdev,
- enum led_brightness b)
-{
- struct lubbock_led *led = container_of(cdev,
- struct lubbock_led, cdev);
- u32 reg = LUB_DISC_BLNK_LED;
-
- if (b != LED_OFF)
- reg |= led->mask;
- else
- reg &= ~led->mask;
-
- LUB_DISC_BLNK_LED = reg;
-}
-
-static enum led_brightness lubbock_led_get(struct led_classdev *cdev)
-{
- struct lubbock_led *led = container_of(cdev,
- struct lubbock_led, cdev);
- u32 reg = LUB_DISC_BLNK_LED;
-
- return (reg & led->mask) ? LED_FULL : LED_OFF;
-}
-
-static int __init lubbock_leds_init(void)
-{
- int i;
-
- if (!machine_is_lubbock())
- return -ENODEV;
-
- /* All ON */
- LUB_DISC_BLNK_LED |= 0xff;
- for (i = 0; i < ARRAY_SIZE(lubbock_leds); i++) {
- struct lubbock_led *led;
-
- led = kzalloc(sizeof(*led), GFP_KERNEL);
- if (!led)
- break;
-
- led->cdev.name = lubbock_leds[i].name;
- led->cdev.brightness_set = lubbock_led_set;
- led->cdev.brightness_get = lubbock_led_get;
- led->cdev.default_trigger = lubbock_leds[i].trigger;
- led->mask = BIT(i);
-
- if (led_classdev_register(NULL, &led->cdev) < 0) {
- kfree(led);
- break;
- }
- }
-
- return 0;
-}
-
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(lubbock_leds_init);
-#endif
-
-MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
- /* Maintainer: MontaVista Software Inc. */
- .map_io = lubbock_map_io,
- .nr_irqs = LUBBOCK_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = lubbock_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
deleted file mode 100644
index 200fd35168e0..000000000000
--- a/arch/arm/mach-pxa/magician.c
+++ /dev/null
@@ -1,1062 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for HTC Magician PDA phones:
- * i-mate JAM, O2 Xda mini, Orange SPV M500, Qtek s100, Qtek s110
- * and T-Mobile MDA Compact.
- *
- * Copyright (c) 2006-2007 Philipp Zabel
- *
- * Based on hx4700.c, spitz.c and others.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/mfd/htc-pasic3.h>
-#include <linux/mtd/physmap.h>
-#include <linux/pda_power.h>
-#include <linux/platform_data/gpio-htc-egpio.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/regulator/driver.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/gpio-regulator.h>
-#include <linux/regulator/machine.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/system_info.h>
-
-#include "pxa27x.h"
-#include <mach/magician.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-
-#include <linux/regulator/max1586.h>
-
-#include <linux/platform_data/pxa2xx_udc.h>
-
-#include "udc.h"
-#include "pxa27x-udc.h"
-#include "devices.h"
-#include "generic.h"
-
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/spi/ads7846.h>
-
-static unsigned long magician_pin_config[] __initdata = {
-
- /* SDRAM and Static Memory I/O Signals */
- GPIO20_nSDCS_2,
- GPIO21_nSDCS_3,
- GPIO15_nCS_1,
- GPIO78_nCS_2, /* PASIC3 */
- GPIO79_nCS_3, /* EGPIO CPLD */
- GPIO80_nCS_4,
- GPIO33_nCS_5,
-
- /* I2C UDA1380 + OV9640 */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* PWM 0 - LCD backlight */
- GPIO16_PWM0_OUT,
-
- /* I2S UDA1380 capture */
- GPIO28_I2S_BITCLK_OUT,
- GPIO29_I2S_SDATA_IN,
- GPIO31_I2S_SYNC,
- GPIO113_I2S_SYSCLK,
-
- /* SSP 1 UDA1380 playback */
- GPIO23_SSP1_SCLK,
- GPIO24_SSP1_SFRM,
- GPIO25_SSP1_TXD,
-
- /* SSP 2 TSC2046 touchscreen */
- GPIO19_SSP2_SCLK,
- MFP_CFG_OUT(GPIO14, AF0, DRIVE_HIGH), /* frame as GPIO */
- GPIO89_SSP2_TXD,
- GPIO88_SSP2_RXD,
-
- /* MMC/SD/SDHC slot */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* QCI camera interface */
- GPIO12_CIF_DD_7,
- GPIO17_CIF_DD_6,
- GPIO50_CIF_DD_3,
- GPIO51_CIF_DD_2,
- GPIO52_CIF_DD_4,
- GPIO53_CIF_MCLK,
- GPIO54_CIF_PCLK,
- GPIO55_CIF_DD_1,
- GPIO81_CIF_DD_0,
- GPIO82_CIF_DD_5,
- GPIO84_CIF_FV,
- GPIO85_CIF_LV,
-
- /* Magician specific input GPIOs */
- GPIO9_GPIO, /* unknown */
- GPIO10_GPIO, /* GSM_IRQ */
- GPIO13_GPIO, /* CPLD_IRQ */
- GPIO107_GPIO, /* DS1WM_IRQ */
- GPIO108_GPIO, /* GSM_READY */
- GPIO115_GPIO, /* nPEN_IRQ */
-};
-
-/*
- * IrDA
- */
-
-static struct pxaficp_platform_data magician_ficp_info = {
- .gpio_pwdown = GPIO83_MAGICIAN_nIR_EN,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
- .gpio_pwdown_inverted = 0,
-};
-
-/*
- * GPIO Keys
- */
-
-#define INIT_KEY(_code, _gpio, _desc) \
- { \
- .code = KEY_##_code, \
- .gpio = _gpio, \
- .desc = _desc, \
- .type = EV_KEY, \
- .wakeup = 1, \
- }
-
-static struct gpio_keys_button magician_button_table[] = {
- INIT_KEY(POWER, GPIO0_MAGICIAN_KEY_POWER, "Power button"),
- INIT_KEY(ESC, GPIO37_MAGICIAN_KEY_HANGUP, "Hangup button"),
- INIT_KEY(F10, GPIO38_MAGICIAN_KEY_CONTACTS, "Contacts button"),
- INIT_KEY(CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, "Calendar button"),
- INIT_KEY(CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, "Camera button"),
- INIT_KEY(UP, GPIO93_MAGICIAN_KEY_UP, "Up button"),
- INIT_KEY(DOWN, GPIO94_MAGICIAN_KEY_DOWN, "Down button"),
- INIT_KEY(LEFT, GPIO95_MAGICIAN_KEY_LEFT, "Left button"),
- INIT_KEY(RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, "Right button"),
- INIT_KEY(KPENTER, GPIO97_MAGICIAN_KEY_ENTER, "Action button"),
- INIT_KEY(RECORD, GPIO98_MAGICIAN_KEY_RECORD, "Record button"),
- INIT_KEY(VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, "Volume up"),
- INIT_KEY(VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, "Volume down"),
- INIT_KEY(PHONE, GPIO102_MAGICIAN_KEY_PHONE, "Phone button"),
- INIT_KEY(PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, "Headset button"),
-};
-
-static struct gpio_keys_platform_data gpio_keys_data = {
- .buttons = magician_button_table,
- .nbuttons = ARRAY_SIZE(magician_button_table),
-};
-
-static struct platform_device gpio_keys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &gpio_keys_data,
- },
- .id = -1,
-};
-
-/*
- * EGPIO (Xilinx CPLD)
- *
- * 32-bit aligned 8-bit registers
- * 16 possible registers (reg windows size), only 7 used:
- * 3x output, 1x irq, 3x input
- */
-
-static struct resource egpio_resources[] = {
- [0] = {
- .start = PXA_CS3_PHYS,
- .end = PXA_CS3_PHYS + 0x20 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ),
- .end = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct htc_egpio_chip egpio_chips[] = {
- [0] = {
- .reg_start = 0,
- .gpio_base = MAGICIAN_EGPIO(0, 0),
- .num_gpios = 24,
- .direction = HTC_EGPIO_OUTPUT,
- /*
- * Depends on modules configuration
- */
- .initial_values = 0x40, /* EGPIO_MAGICIAN_GSM_RESET */
- },
- [1] = {
- .reg_start = 4,
- .gpio_base = MAGICIAN_EGPIO(4, 0),
- .num_gpios = 24,
- .direction = HTC_EGPIO_INPUT,
- },
-};
-
-static struct htc_egpio_platform_data egpio_info = {
- .reg_width = 8,
- .bus_width = 32,
- .irq_base = IRQ_BOARD_START,
- .num_irqs = 4,
- .ack_register = 3,
- .chip = egpio_chips,
- .num_chips = ARRAY_SIZE(egpio_chips),
-};
-
-static struct platform_device egpio = {
- .name = "htc-egpio",
- .id = -1,
- .resource = egpio_resources,
- .num_resources = ARRAY_SIZE(egpio_resources),
- .dev = {
- .platform_data = &egpio_info,
- },
-};
-
-/*
- * PXAFB LCD - Toppoly TD028STEB1 or Samsung LTP280QV
- */
-
-static struct pxafb_mode_info toppoly_modes[] = {
- {
- .pixclock = 96153,
- .bpp = 16,
- .xres = 240,
- .yres = 320,
- .hsync_len = 11,
- .vsync_len = 3,
- .left_margin = 19,
- .upper_margin = 2,
- .right_margin = 10,
- .lower_margin = 2,
- .sync = 0,
- },
-};
-
-static struct pxafb_mode_info samsung_modes[] = {
- {
- .pixclock = 226469,
- .bpp = 16,
- .xres = 240,
- .yres = 320,
- .hsync_len = 8,
- .vsync_len = 4,
- .left_margin = 9,
- .upper_margin = 4,
- .right_margin = 9,
- .lower_margin = 4,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- },
-};
-
-static void toppoly_lcd_power(int on, struct fb_var_screeninfo *si)
-{
- pr_debug("Toppoly LCD power: %s\n", on ? "on" : "off");
-
- if (on) {
- gpio_set_value(EGPIO_MAGICIAN_TOPPOLY_POWER, 1);
- gpio_set_value(GPIO106_MAGICIAN_LCD_DCDC_NRESET, 1);
- udelay(2000);
- gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
- udelay(2000);
- /* FIXME: enable LCDC here */
- udelay(2000);
- gpio_set_value(GPIO104_MAGICIAN_LCD_VOFF_EN, 1);
- udelay(2000);
- gpio_set_value(GPIO105_MAGICIAN_LCD_VON_EN, 1);
- } else {
- msleep(15);
- gpio_set_value(GPIO105_MAGICIAN_LCD_VON_EN, 0);
- udelay(500);
- gpio_set_value(GPIO104_MAGICIAN_LCD_VOFF_EN, 0);
- udelay(1000);
- gpio_set_value(GPIO106_MAGICIAN_LCD_DCDC_NRESET, 0);
- gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
- }
-}
-
-static void samsung_lcd_power(int on, struct fb_var_screeninfo *si)
-{
- pr_debug("Samsung LCD power: %s\n", on ? "on" : "off");
-
- if (on) {
- if (system_rev < 3)
- gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 1);
- else
- gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
- mdelay(6);
- gpio_set_value(GPIO106_MAGICIAN_LCD_DCDC_NRESET, 1);
- mdelay(6); /* Avdd -> Voff >5ms */
- gpio_set_value(GPIO104_MAGICIAN_LCD_VOFF_EN, 1);
- mdelay(16); /* Voff -> Von >(5+10)ms */
- gpio_set_value(GPIO105_MAGICIAN_LCD_VON_EN, 1);
- } else {
- gpio_set_value(GPIO105_MAGICIAN_LCD_VON_EN, 0);
- mdelay(16);
- gpio_set_value(GPIO104_MAGICIAN_LCD_VOFF_EN, 0);
- mdelay(6);
- gpio_set_value(GPIO106_MAGICIAN_LCD_DCDC_NRESET, 0);
- mdelay(6);
- if (system_rev < 3)
- gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 0);
- else
- gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
- }
-}
-
-static struct pxafb_mach_info toppoly_info = {
- .modes = toppoly_modes,
- .num_modes = 1,
- .fixed_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP,
- .pxafb_lcd_power = toppoly_lcd_power,
-};
-
-static struct pxafb_mach_info samsung_info = {
- .modes = samsung_modes,
- .num_modes = 1,
- .fixed_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
- LCD_ALTERNATE_MAPPING,
- .pxafb_lcd_power = samsung_lcd_power,
-};
-
-/*
- * Backlight
- */
-
-static struct pwm_lookup magician_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight", NULL, 30923,
- PWM_POLARITY_NORMAL),
-};
-
- /*
- * fixed regulator for pwm_backlight
- */
-
-static struct regulator_consumer_supply pwm_backlight_supply[] = {
- REGULATOR_SUPPLY("power", "pwm_backlight"),
-};
-
-
-static struct gpio magician_bl_gpios[] = {
- { EGPIO_MAGICIAN_BL_POWER, GPIOF_DIR_OUT, "Backlight power" },
- { EGPIO_MAGICIAN_BL_POWER2, GPIOF_DIR_OUT, "Backlight power 2" },
-};
-
-static int magician_backlight_init(struct device *dev)
-{
- return gpio_request_array(ARRAY_AND_SIZE(magician_bl_gpios));
-}
-
-static int magician_backlight_notify(struct device *dev, int brightness)
-{
- pr_debug("Brightness = %i\n", brightness);
- gpio_set_value(EGPIO_MAGICIAN_BL_POWER, brightness);
- if (brightness >= 200) {
- gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
- return brightness - 72;
- } else {
- gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
- return brightness;
- }
-}
-
-static void magician_backlight_exit(struct device *dev)
-{
- gpio_free_array(ARRAY_AND_SIZE(magician_bl_gpios));
-}
-
-/*
- * LCD PWM backlight (main)
- *
- * MP1521 frequency should be:
- * 100-400 Hz = 2 .5*10^6 - 10 *10^6 ns
- */
-
-static struct platform_pwm_backlight_data backlight_data = {
- .max_brightness = 272,
- .dft_brightness = 100,
- .init = magician_backlight_init,
- .notify = magician_backlight_notify,
- .exit = magician_backlight_exit,
-};
-
-static struct platform_device backlight = {
- .name = "pwm-backlight",
- .id = -1,
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &backlight_data,
- },
-};
-
-/*
- * GPIO LEDs, Phone keys backlight, vibra
- */
-
-static struct gpio_led gpio_leds[] = {
- {
- .name = "magician::vibra",
- .default_trigger = "none",
- .gpio = GPIO22_MAGICIAN_VIBRA_EN,
- },
- {
- .name = "magician::phone_bl",
- .default_trigger = "backlight",
- .gpio = GPIO103_MAGICIAN_LED_KP,
- },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &gpio_led_info,
- },
-};
-
-/*
- * PASIC3 with DS1WM
- */
-
-static struct resource pasic3_resources[] = {
- [0] = {
- .start = PXA_CS2_PHYS,
- .end = PXA_CS2_PHYS + 0x1b,
- .flags = IORESOURCE_MEM,
- },
- /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */
- [1] = {
- .start = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ),
- .end = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct pasic3_platform_data pasic3_platform_data = {
- .clock_rate = 4000000,
-};
-
-static struct platform_device pasic3 = {
- .name = "pasic3",
- .id = -1,
- .num_resources = ARRAY_SIZE(pasic3_resources),
- .resource = pasic3_resources,
- .dev = {
- .platform_data = &pasic3_platform_data,
- },
-};
-
-/*
- * PXA UDC
- */
-
-static void magician_udc_command(int cmd)
-{
- if (cmd == PXA2XX_UDC_CMD_CONNECT)
- UP2OCR |= UP2OCR_DPPUE | UP2OCR_DPPUBE;
- else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
- UP2OCR &= ~(UP2OCR_DPPUE | UP2OCR_DPPUBE);
-}
-
-static struct pxa2xx_udc_mach_info magician_udc_info __initdata = {
- .udc_command = magician_udc_command,
- .gpio_pullup = GPIO27_MAGICIAN_USBC_PUEN,
-};
-
-/*
- * USB device VBus detection
- */
-
-static struct resource gpio_vbus_resource = {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_MAGICIAN_VBUS,
- .end = IRQ_MAGICIAN_VBUS,
-};
-
-static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- /*
- * EGPIO on register 4 index 1, the second EGPIO chip
- * starts at register 4 so this will be at index 1 on that
- * chip.
- */
- GPIO_LOOKUP("htc-egpio-1", 1,
- "vbus", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO27_MAGICIAN_USBC_PUEN,
- "pullup", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
- .num_resources = 1,
- .resource = &gpio_vbus_resource,
-};
-
-/*
- * External power
- */
-
-static int magician_supply_init(struct device *dev)
-{
- int ret = -1;
-
- ret = gpio_request(EGPIO_MAGICIAN_CABLE_TYPE, "Cable is AC charger");
- if (ret) {
- pr_err("Cannot request AC/USB charger GPIO (%i)\n", ret);
- goto err_ac;
- }
-
- ret = gpio_request(EGPIO_MAGICIAN_CABLE_INSERTED, "Cable inserted");
- if (ret) {
- pr_err("Cannot request cable detection GPIO (%i)\n", ret);
- goto err_usb;
- }
-
- return 0;
-
-err_usb:
- gpio_free(EGPIO_MAGICIAN_CABLE_TYPE);
-err_ac:
- return ret;
-}
-
-static void magician_set_charge(int flags)
-{
- if (flags & PDA_POWER_CHARGE_AC) {
- pr_debug("Charging from AC\n");
- gpio_set_value(EGPIO_MAGICIAN_NICD_CHARGE, 1);
- } else if (flags & PDA_POWER_CHARGE_USB) {
- pr_debug("Charging from USB\n");
- gpio_set_value(EGPIO_MAGICIAN_NICD_CHARGE, 1);
- } else {
- pr_debug("Charging disabled\n");
- gpio_set_value(EGPIO_MAGICIAN_NICD_CHARGE, 0);
- }
-}
-
-static int magician_is_ac_online(void)
-{
- return gpio_get_value(EGPIO_MAGICIAN_CABLE_INSERTED) &&
- gpio_get_value(EGPIO_MAGICIAN_CABLE_TYPE); /* AC=1 */
-}
-
-static int magician_is_usb_online(void)
-{
- return gpio_get_value(EGPIO_MAGICIAN_CABLE_INSERTED) &&
- (!gpio_get_value(EGPIO_MAGICIAN_CABLE_TYPE)); /* USB=0 */
-}
-
-static void magician_supply_exit(struct device *dev)
-{
- gpio_free(EGPIO_MAGICIAN_CABLE_INSERTED);
- gpio_free(EGPIO_MAGICIAN_CABLE_TYPE);
-}
-
-static char *magician_supplicants[] = {
- "ds2760-battery.0", "backup-battery"
-};
-
-static struct pda_power_pdata power_supply_info = {
- .init = magician_supply_init,
- .exit = magician_supply_exit,
- .is_ac_online = magician_is_ac_online,
- .is_usb_online = magician_is_usb_online,
- .set_charge = magician_set_charge,
- .supplied_to = magician_supplicants,
- .num_supplicants = ARRAY_SIZE(magician_supplicants),
-};
-
-static struct resource power_supply_resources[] = {
- [0] = {
- .name = "ac",
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_LOWEDGE,
- .start = IRQ_MAGICIAN_VBUS,
- .end = IRQ_MAGICIAN_VBUS,
- },
- [1] = {
- .name = "usb",
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_LOWEDGE,
- .start = IRQ_MAGICIAN_VBUS,
- .end = IRQ_MAGICIAN_VBUS,
- },
-};
-
-static struct platform_device power_supply = {
- .name = "pda-power",
- .id = -1,
- .dev = {
- .platform_data = &power_supply_info,
- },
- .resource = power_supply_resources,
- .num_resources = ARRAY_SIZE(power_supply_resources),
-};
-
-/*
- * Battery charger
- */
-
-static struct regulator_consumer_supply bq24022_consumers[] = {
- REGULATOR_SUPPLY("vbus_draw", NULL),
- REGULATOR_SUPPLY("ac_draw", NULL),
-};
-
-static struct regulator_init_data bq24022_init_data = {
- .constraints = {
- .max_uA = 500000,
- .valid_ops_mask = REGULATOR_CHANGE_CURRENT |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(bq24022_consumers),
- .consumer_supplies = bq24022_consumers,
-};
-
-
-static enum gpiod_flags bq24022_gpiod_gflags[] = { GPIOD_OUT_LOW };
-
-static struct gpio_regulator_state bq24022_states[] = {
- { .value = 100000, .gpios = (0 << 0) },
- { .value = 500000, .gpios = (1 << 0) },
-};
-
-static struct gpio_regulator_config bq24022_info = {
- .supply_name = "bq24022",
-
- .enabled_at_boot = 1,
-
- .gflags = bq24022_gpiod_gflags,
- .ngpios = ARRAY_SIZE(bq24022_gpiod_gflags),
-
- .states = bq24022_states,
- .nr_states = ARRAY_SIZE(bq24022_states),
-
- .type = REGULATOR_CURRENT,
- .init_data = &bq24022_init_data,
-};
-
-static struct platform_device bq24022 = {
- .name = "gpio-regulator",
- .id = -1,
- .dev = {
- .platform_data = &bq24022_info,
- },
-};
-
-static struct gpiod_lookup_table bq24022_gpiod_table = {
- .dev_id = "gpio-regulator",
- .table = {
- GPIO_LOOKUP("gpio-pxa", EGPIO_MAGICIAN_BQ24022_ISET2,
- NULL, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
- "enable", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/*
- * fixed regulator for ads7846
- */
-
-static struct regulator_consumer_supply ads7846_supply =
- REGULATOR_SUPPLY("vcc", "spi2.0");
-
-static struct regulator_init_data vads7846_regulator = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &ads7846_supply,
-};
-
-static struct fixed_voltage_config vads7846 = {
- .supply_name = "vads7846",
- .microvolts = 3300000, /* probably */
- .startup_delay = 0,
- .init_data = &vads7846_regulator,
-};
-
-static struct platform_device vads7846_device = {
- .name = "reg-fixed-voltage",
- .id = -1,
- .dev = {
- .platform_data = &vads7846,
- },
-};
-
-/*
- * Vcore regulator MAX1587A
- */
-
-static struct regulator_consumer_supply magician_max1587a_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data magician_max1587a_v3_info = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 700000,
- .max_uV = 1475000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .consumer_supplies = magician_max1587a_consumers,
- .num_consumer_supplies = ARRAY_SIZE(magician_max1587a_consumers),
-};
-
-static struct max1586_subdev_data magician_max1587a_subdevs[] = {
- {
- .name = "vcc_core",
- .id = MAX1586_V3,
- .platform_data = &magician_max1587a_v3_info,
- }
-};
-
-static struct max1586_platform_data magician_max1587a_info = {
- .subdevs = magician_max1587a_subdevs,
- .num_subdevs = ARRAY_SIZE(magician_max1587a_subdevs),
- /*
- * NOTICE measured directly on the PCB (board_id == 0x3a), but
- * if R24 is present, it will boost the voltage
- * (write 1.475V, get 1.645V and smoke)
- */
- .v3_gain = MAX1586_GAIN_NO_R24,
-};
-
-static struct i2c_board_info magician_pwr_i2c_board_info[] __initdata = {
- {
- I2C_BOARD_INFO("max1586", 0x14),
- .platform_data = &magician_max1587a_info,
- },
-};
-
-/*
- * MMC/SD
- */
-
-static int magician_mci_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- return request_irq(IRQ_MAGICIAN_SD, detect_irq, 0,
- "mmc card detect", data);
-}
-
-static void magician_mci_exit(struct device *dev, void *data)
-{
- free_irq(IRQ_MAGICIAN_SD, data);
-}
-
-static struct pxamci_platform_data magician_mci_info = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .init = magician_mci_init,
- .exit = magician_mci_exit,
- .gpio_card_ro_invert = 1,
-};
-
-/*
- * Write protect on EGPIO register 5 index 4, this is on the second HTC
- * EGPIO chip which starts at register 4, so we need offset 8+4=12 on that
- * particular chip.
- */
-#define EGPIO_MAGICIAN_nSD_READONLY_OFFSET 12
-/*
- * Power on EGPIO register 2 index 0, so this is on the first HTC EGPIO chip
- * starting at register 0 so we need offset 2*8+0 = 16 on that chip.
- */
-#define EGPIO_MAGICIAN_nSD_POWER_OFFSET 16
-
-static struct gpiod_lookup_table magician_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("htc-egpio-1", EGPIO_MAGICIAN_nSD_READONLY_OFFSET,
- "wp", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("htc-egpio-0", EGPIO_MAGICIAN_nSD_POWER_OFFSET,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/*
- * USB OHCI
- */
-
-static struct pxaohci_platform_data magician_ohci_info = {
- .port_mode = PMM_PERPORT_MODE,
- /* port1: CSR Bluetooth, port2: OTG with UDC */
- .flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
- .power_budget = 0,
- .power_on_delay = 100,
-};
-
-/*
- * StrataFlash
- */
-
-static int magician_flash_init(struct platform_device *pdev)
-{
- int ret = gpio_request(EGPIO_MAGICIAN_FLASH_VPP, "flash Vpp enable");
-
- if (ret) {
- pr_err("Cannot request flash enable GPIO (%i)\n", ret);
- return ret;
- }
-
- ret = gpio_direction_output(EGPIO_MAGICIAN_FLASH_VPP, 1);
- if (ret) {
- pr_err("Cannot set direction for flash enable (%i)\n", ret);
- gpio_free(EGPIO_MAGICIAN_FLASH_VPP);
- }
-
- return ret;
-}
-
-static void magician_set_vpp(struct platform_device *pdev, int vpp)
-{
- gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
-}
-
-static void magician_flash_exit(struct platform_device *pdev)
-{
- gpio_free(EGPIO_MAGICIAN_FLASH_VPP);
-}
-
-static struct resource strataflash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct mtd_partition magician_flash_parts[] = {
- {
- .name = "Bootloader",
- .offset = 0x0,
- .size = 0x40000,
- .mask_flags = MTD_WRITEABLE, /* EXPERIMENTAL */
- },
- {
- .name = "Linux Kernel",
- .offset = 0x40000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-/*
- * physmap-flash driver
- */
-
-static struct physmap_flash_data strataflash_data = {
- .width = 4,
- .init = magician_flash_init,
- .set_vpp = magician_set_vpp,
- .exit = magician_flash_exit,
- .parts = magician_flash_parts,
- .nr_parts = ARRAY_SIZE(magician_flash_parts),
-};
-
-static struct platform_device strataflash = {
- .name = "physmap-flash",
- .id = -1,
- .resource = &strataflash_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = &strataflash_data,
- },
-};
-
-/*
- * PXA I2C main controller
- */
-
-static struct i2c_pxa_platform_data i2c_info = {
- /* OV9640 I2C device doesn't support fast mode */
- .fast_mode = 0,
-};
-
-/*
- * PXA I2C power controller
- */
-
-static struct i2c_pxa_platform_data magician_i2c_power_info = {
- .fast_mode = 1,
-};
-
-/*
- * Touchscreen
- */
-
-static struct ads7846_platform_data ads7846_pdata = {
- .model = 7846,
- .x_plate_ohms = 317,
- .y_plate_ohms = 500,
- .pressure_max = 1023, /* with x plate ohms it will overflow 255 */
- .debounce_max = 3, /* first readout is always bad */
- .debounce_tol = 30,
- .debounce_rep = 0,
- .gpio_pendown = GPIO115_MAGICIAN_nPEN_IRQ,
- .keep_vref_on = 1,
- .wakeup = true,
- .vref_delay_usecs = 100,
- .penirq_recheck_delay_usecs = 100,
-};
-
-struct pxa2xx_spi_chip tsc2046_chip_info = {
- .tx_threshold = 1,
- .rx_threshold = 2,
- .timeout = 64,
-};
-
-static struct pxa2xx_spi_controller magician_spi_info = {
- .num_chipselect = 1,
- .enable_dma = 1,
-};
-
-static struct gpiod_lookup_table magician_spi_gpio_table = {
- .dev_id = "pxa2xx-spi.2",
- .table = {
- /* NOTICE must be GPIO, incompatibility with hw PXA SPI framing */
- GPIO_LOOKUP_IDX("gpio-pxa", GPIO14_MAGICIAN_TSC2046_CS, "cs", 0, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct spi_board_info ads7846_spi_board_info[] __initdata = {
- {
- .modalias = "ads7846",
- .bus_num = 2,
- .max_speed_hz = 2500000,
- .platform_data = &ads7846_pdata,
- .controller_data = &tsc2046_chip_info,
- .irq = PXA_GPIO_TO_IRQ(GPIO115_MAGICIAN_nPEN_IRQ),
- },
-};
-
-/*
- * Platform devices
- */
-
-static struct platform_device *devices[] __initdata = {
- &gpio_keys,
- &egpio,
- &backlight,
- &pasic3,
- &bq24022,
- &gpio_vbus,
- &power_supply,
- &strataflash,
- &leds_gpio,
- &vads7846_device,
-};
-
-static struct gpio magician_global_gpios[] = {
- { GPIO13_MAGICIAN_CPLD_IRQ, GPIOF_IN, "CPLD_IRQ" },
- { GPIO107_MAGICIAN_DS1WM_IRQ, GPIOF_IN, "DS1WM_IRQ" },
-
- /* NOTICE valid LCD init sequence */
- { GPIO106_MAGICIAN_LCD_DCDC_NRESET, GPIOF_OUT_INIT_LOW, "LCD DCDC nreset" },
- { GPIO104_MAGICIAN_LCD_VOFF_EN, GPIOF_OUT_INIT_LOW, "LCD VOFF enable" },
- { GPIO105_MAGICIAN_LCD_VON_EN, GPIOF_OUT_INIT_LOW, "LCD VON enable" },
-};
-
-static void __init magician_init(void)
-{
- void __iomem *cpld;
- int lcd_select;
- int err;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
- err = gpio_request_array(ARRAY_AND_SIZE(magician_global_gpios));
- if (err)
- pr_err("magician: Failed to request global GPIOs: %d\n", err);
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
-
- pwm_add_table(magician_pwm_lookup, ARRAY_SIZE(magician_pwm_lookup));
-
- pxa_set_ficp_info(&magician_ficp_info);
- pxa27x_set_i2c_power_info(&magician_i2c_power_info);
- pxa_set_i2c_info(&i2c_info);
-
- i2c_register_board_info(1,
- ARRAY_AND_SIZE(magician_pwr_i2c_board_info));
-
- gpiod_add_lookup_table(&magician_mci_gpio_table);
- pxa_set_mci_info(&magician_mci_info);
- pxa_set_ohci_info(&magician_ohci_info);
- pxa_set_udc_info(&magician_udc_info);
-
- /* Check LCD type we have */
- cpld = ioremap(PXA_CS3_PHYS, 0x1000);
- if (cpld) {
- u8 board_id = __raw_readb(cpld + 0x14);
-
- iounmap(cpld);
- system_rev = board_id & 0x7;
- lcd_select = board_id & 0x8;
- pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly");
- if (lcd_select && (system_rev < 3))
- /* NOTICE valid LCD init sequence */
- gpio_request_one(GPIO75_MAGICIAN_SAMSUNG_POWER,
- GPIOF_OUT_INIT_LOW, "Samsung LCD Power");
- pxa_set_fb_info(NULL,
- lcd_select ? &samsung_info : &toppoly_info);
- } else
- pr_err("LCD detection: CPLD mapping failed\n");
-
- gpiod_add_lookup_table(&magician_spi_gpio_table);
- pxa2xx_set_spi_info(2, &magician_spi_info);
- spi_register_board_info(ARRAY_AND_SIZE(ads7846_spi_board_info));
-
- regulator_register_always_on(0, "power", pwm_backlight_supply,
- ARRAY_SIZE(pwm_backlight_supply), 5000000);
-
- gpiod_add_lookup_table(&bq24022_gpiod_table);
- gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
- platform_add_devices(ARRAY_AND_SIZE(devices));
-}
-
-MACHINE_START(MAGICIAN, "HTC Magician")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = MAGICIAN_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_machine = magician_init,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
deleted file mode 100644
index d237bd030238..000000000000
--- a/arch/arm/mach-pxa/mainstone.c
+++ /dev/null
@@ -1,729 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/mainstone.c
- *
- * Support for the Intel HCDDBBVA0 Development Platform.
- * (go figure how they came up with such name...)
- *
- * Author: Nicolas Pitre
- * Created: Nov 05, 2002
- * Copyright: MontaVista Software Inc.
- */
-#include <linux/gpio.h>
-#include <linux/gpio/gpio-reg.h>
-#include <linux/gpio/machine.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/bitops.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/smc91x.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <linux/sizes.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/flash.h>
-
-#include "pxa27x.h"
-#include <mach/mainstone.h>
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <mach/smemc.h>
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned long mainstone_pin_config[] = {
- /* Chip Select */
- GPIO15_nCS_1,
-
- /* LCD - 16bpp Active TFT */
- GPIOxx_LCD_TFT_16BPP,
- GPIO16_PWM0_OUT, /* Backlight */
-
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO112_MMC_CMD,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
-
- /* USB Host Port 1 */
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
-
- /* PC Card */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO79_PSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO45_AC97_SYSCLK,
-
- /* Keypad */
- GPIO93_KP_DKIN_0,
- GPIO94_KP_DKIN_1,
- GPIO95_KP_DKIN_2,
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
- GPIO96_KP_MKOUT_6,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* GPIO */
- GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (MST_ETH_PHYS + 0x300),
- .end = (MST_ETH_PHYS + 0xfffff),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = MAINSTONE_IRQ(3),
- .end = MAINSTONE_IRQ(3),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct smc91x_platdata mainstone_smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT | SMC91X_USE_DMA,
- .pxa_u16_align4 = true,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &mainstone_smc91x_info,
- },
-};
-
-static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
-{
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
- return 0;
-}
-
-static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
-{
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
-}
-
-static long mst_audio_suspend_mask;
-
-static void mst_audio_suspend(void *priv)
-{
- mst_audio_suspend_mask = MST_MSCWR2;
- MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
-}
-
-static void mst_audio_resume(void *priv)
-{
- MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
-}
-
-static pxa2xx_audio_ops_t mst_audio_ops = {
- .startup = mst_audio_startup,
- .shutdown = mst_audio_shutdown,
- .suspend = mst_audio_suspend,
- .resume = mst_audio_resume,
-};
-
-static struct resource flash_resources[] = {
- [0] = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_CS1_PHYS,
- .end = PXA_CS1_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct mtd_partition mainstoneflash0_partitions[] = {
- {
- .name = "Bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- },{
- .name = "Kernel",
- .size = 0x00400000,
- .offset = 0x00040000,
- },{
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00440000
- }
-};
-
-static struct flash_platform_data mst_flash_data[2] = {
- {
- .map_name = "cfi_probe",
- .parts = mainstoneflash0_partitions,
- .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
- }, {
- .map_name = "cfi_probe",
- .parts = NULL,
- .nr_parts = 0,
- }
-};
-
-static struct platform_device mst_flash_device[2] = {
- {
- .name = "pxa2xx-flash",
- .id = 0,
- .dev = {
- .platform_data = &mst_flash_data[0],
- },
- .resource = &flash_resources[0],
- .num_resources = 1,
- },
- {
- .name = "pxa2xx-flash",
- .id = 1,
- .dev = {
- .platform_data = &mst_flash_data[1],
- },
- .resource = &flash_resources[1],
- .num_resources = 1,
- },
-};
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pwm_lookup mainstone_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data mainstone_backlight_data = {
- .max_brightness = 1023,
- .dft_brightness = 1023,
-};
-
-static struct platform_device mainstone_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &mainstone_backlight_data,
- },
-};
-
-static void __init mainstone_backlight_register(void)
-{
- int ret;
-
- pwm_add_table(mainstone_pwm_lookup, ARRAY_SIZE(mainstone_pwm_lookup));
-
- ret = platform_device_register(&mainstone_backlight_device);
- if (ret) {
- printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
- pwm_remove_table(mainstone_pwm_lookup,
- ARRAY_SIZE(mainstone_pwm_lookup));
- }
-}
-#else
-#define mainstone_backlight_register() do { } while (0)
-#endif
-
-static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
- .pixclock = 50000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 1,
- .left_margin = 0x9f,
- .right_margin = 1,
- .vsync_len = 44,
- .upper_margin = 0,
- .lower_margin = 0,
- .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
- .pixclock = 110000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 4,
- .left_margin = 8,
- .right_margin = 20,
- .vsync_len = 3,
- .upper_margin = 1,
- .lower_margin = 10,
- .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info mainstone_pxafb_info = {
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
-{
- int err;
-
- /* make sure SD/Memory Stick multiplexer's signals
- * are routed to MMC controller
- */
- MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
-
- err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, 0,
- "MMC card detect", data);
- if (err)
- printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
-
- return err;
-}
-
-static int mainstone_mci_setpower(struct device *dev, unsigned int vdd)
-{
- struct pxamci_platform_data* p_d = dev->platform_data;
-
- if (( 1 << vdd) & p_d->ocr_mask) {
- printk(KERN_DEBUG "%s: on\n", __func__);
- MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
- MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
- } else {
- printk(KERN_DEBUG "%s: off\n", __func__);
- MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
- }
- return 0;
-}
-
-static void mainstone_mci_exit(struct device *dev, void *data)
-{
- free_irq(MAINSTONE_MMC_IRQ, data);
-}
-
-static struct pxamci_platform_data mainstone_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .init = mainstone_mci_init,
- .setpower = mainstone_mci_setpower,
- .exit = mainstone_mci_exit,
-};
-
-static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- if (mode & IR_SIRMODE) {
- MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
- } else if (mode & IR_FIRMODE) {
- MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
- }
- pxa2xx_transceiver_mode(dev, mode);
- if (mode & IR_OFF) {
- MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
- } else {
- MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
- }
- local_irq_restore(flags);
-}
-
-static struct pxaficp_platform_data mainstone_ficp_platform_data = {
- .gpio_pwdown = -1,
- .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
- .transceiver_mode = mainstone_irda_transceiver_mode,
-};
-
-static struct gpio_keys_button gpio_keys_button[] = {
- [0] = {
- .desc = "wakeup",
- .code = KEY_SUSPEND,
- .type = EV_KEY,
- .gpio = 1,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data mainstone_gpio_keys = {
- .buttons = gpio_keys_button,
- .nbuttons = 1,
-};
-
-static struct platform_device mst_gpio_keys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &mainstone_gpio_keys,
- },
-};
-
-static struct resource mst_cplds_resources[] = {
- [0] = {
- .start = MST_FPGA_PHYS + 0xc0,
- .end = MST_FPGA_PHYS + 0xe0 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(0),
- .end = PXA_GPIO_TO_IRQ(0),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
- [2] = {
- .start = MAINSTONE_IRQ(0),
- .end = MAINSTONE_IRQ(15),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mst_cplds_device = {
- .name = "pxa_cplds_irqs",
- .id = -1,
- .resource = &mst_cplds_resources[0],
- .num_resources = 3,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &smc91x_device,
- &mst_flash_device[0],
- &mst_flash_device[1],
- &mst_gpio_keys_device,
- &mst_cplds_device,
-};
-
-static struct pxaohci_platform_data mainstone_ohci_platform_data = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int mainstone_matrix_keys[] = {
- KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
- KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
- KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
- KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L),
- KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O),
- KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R),
- KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U),
- KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X),
- KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z),
-
- KEY(0, 4, KEY_DOT), /* . */
- KEY(1, 4, KEY_CLOSE), /* @ */
- KEY(4, 4, KEY_SLASH),
- KEY(5, 4, KEY_BACKSLASH),
- KEY(0, 5, KEY_HOME),
- KEY(1, 5, KEY_LEFTSHIFT),
- KEY(2, 5, KEY_SPACE),
- KEY(3, 5, KEY_SPACE),
- KEY(4, 5, KEY_ENTER),
- KEY(5, 5, KEY_BACKSPACE),
-
- KEY(0, 6, KEY_UP),
- KEY(1, 6, KEY_DOWN),
- KEY(2, 6, KEY_LEFT),
- KEY(3, 6, KEY_RIGHT),
- KEY(4, 6, KEY_SELECT),
-};
-
-static struct matrix_keymap_data mainstone_matrix_keymap_data = {
- .keymap = mainstone_matrix_keys,
- .keymap_size = ARRAY_SIZE(mainstone_matrix_keys),
-};
-
-struct pxa27x_keypad_platform_data mainstone_keypad_info = {
- .matrix_key_rows = 6,
- .matrix_key_cols = 7,
- .matrix_keymap_data = &mainstone_matrix_keymap_data,
-
- .enable_rotary0 = 1,
- .rotary0_up_key = KEY_UP,
- .rotary0_down_key = KEY_DOWN,
-
- .debounce_interval = 30,
-};
-
-static void __init mainstone_init_keypad(void)
-{
- pxa_set_keypad_info(&mainstone_keypad_info);
-}
-#else
-static inline void mainstone_init_keypad(void) {}
-#endif
-
-static int mst_pcmcia0_irqs[11] = {
- [0 ... 4] = -1,
- [5] = MAINSTONE_S0_CD_IRQ,
- [6 ... 7] = -1,
- [8] = MAINSTONE_S0_STSCHG_IRQ,
- [9] = -1,
- [10] = MAINSTONE_S0_IRQ,
-};
-
-static int mst_pcmcia1_irqs[11] = {
- [0 ... 4] = -1,
- [5] = MAINSTONE_S1_CD_IRQ,
- [6 ... 7] = -1,
- [8] = MAINSTONE_S1_STSCHG_IRQ,
- [9] = -1,
- [10] = MAINSTONE_S1_IRQ,
-};
-
-static struct gpiod_lookup_table mainstone_pcmcia_gpio_table = {
- .dev_id = "pxa2xx-pcmcia",
- .table = {
- GPIO_LOOKUP("mst-pcmcia0", 0, "a0vpp", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia0", 1, "a1vpp", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia0", 2, "a0vcc", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia0", 3, "a1vcc", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia0", 4, "areset", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia0", 5, "adetect", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("mst-pcmcia0", 6, "avs1", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("mst-pcmcia0", 7, "avs2", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("mst-pcmcia0", 8, "abvd1", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia0", 9, "abvd2", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia0", 10, "aready", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 0, "b0vpp", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 1, "b1vpp", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 2, "b0vcc", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 3, "b1vcc", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 4, "breset", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 5, "bdetect", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("mst-pcmcia1", 6, "bvs1", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("mst-pcmcia1", 7, "bvs2", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("mst-pcmcia1", 8, "bbvd1", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 9, "bbvd2", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("mst-pcmcia1", 10, "bready", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static void __init mainstone_init(void)
-{
- int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
-
- /* Register board control register(s) as GPIOs */
- gpio_reg_init(NULL, (void __iomem *)&MST_PCMCIA0, -1, 11,
- "mst-pcmcia0", MST_PCMCIA_INPUTS, 0, NULL,
- NULL, mst_pcmcia0_irqs);
- gpio_reg_init(NULL, (void __iomem *)&MST_PCMCIA1, -1, 11,
- "mst-pcmcia1", MST_PCMCIA_INPUTS, 0, NULL,
- NULL, mst_pcmcia1_irqs);
- gpiod_add_lookup_table(&mainstone_pcmcia_gpio_table);
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
- mst_flash_data[1].width = 4;
-
- /* Compensate for SW7 which swaps the flash banks */
- mst_flash_data[SW7].name = "processor-flash";
- mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
-
- printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
- mst_flash_data[0].name);
-
- /* system bus arbiter setting
- * - Core_Park
- * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
- */
- ARB_CNTRL = ARB_CORE_PARK | 0x234;
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
- /* reading Mainstone's "Virtual Configuration Register"
- might be handy to select LCD type here */
- if (0)
- mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
- else
- mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
-
- pxa_set_fb_info(NULL, &mainstone_pxafb_info);
- mainstone_backlight_register();
-
- pxa_set_mci_info(&mainstone_mci_platform_data);
- pxa_set_ficp_info(&mainstone_ficp_platform_data);
- pxa_set_ohci_info(&mainstone_ohci_platform_data);
- pxa_set_i2c_info(NULL);
- pxa_set_ac97_info(&mst_audio_ops);
-
- mainstone_init_keypad();
-}
-
-
-static struct map_desc mainstone_io_desc[] __initdata = {
- { /* CPLD */
- .virtual = MST_FPGA_VIRT,
- .pfn = __phys_to_pfn(MST_FPGA_PHYS),
- .length = 0x00100000,
- .type = MT_DEVICE
- }
-};
-
-static void __init mainstone_map_io(void)
-{
- pxa27x_map_io();
- iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
-
- /* for use I SRAM as framebuffer. */
- PSLR |= 0xF04;
- PCFR = 0x66;
-}
-
-/*
- * Driver for the 8 discrete LEDs available for general use:
- * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
- * so be sure to not monkey with them here.
- */
-
-#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
-struct mainstone_led {
- struct led_classdev cdev;
- u8 mask;
-};
-
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
- const char *name;
- const char *trigger;
-} mainstone_leds[] = {
- { "mainstone:D28", "default-on", },
- { "mainstone:D27", "cpu0", },
- { "mainstone:D26", "heartbeat" },
- { "mainstone:D25", },
- { "mainstone:D24", },
- { "mainstone:D23", },
- { "mainstone:D22", },
- { "mainstone:D21", },
-};
-
-static void mainstone_led_set(struct led_classdev *cdev,
- enum led_brightness b)
-{
- struct mainstone_led *led = container_of(cdev,
- struct mainstone_led, cdev);
- u32 reg = MST_LEDCTRL;
-
- if (b != LED_OFF)
- reg |= led->mask;
- else
- reg &= ~led->mask;
-
- MST_LEDCTRL = reg;
-}
-
-static enum led_brightness mainstone_led_get(struct led_classdev *cdev)
-{
- struct mainstone_led *led = container_of(cdev,
- struct mainstone_led, cdev);
- u32 reg = MST_LEDCTRL;
-
- return (reg & led->mask) ? LED_FULL : LED_OFF;
-}
-
-static int __init mainstone_leds_init(void)
-{
- int i;
-
- if (!machine_is_mainstone())
- return -ENODEV;
-
- /* All ON */
- MST_LEDCTRL |= 0xff;
- for (i = 0; i < ARRAY_SIZE(mainstone_leds); i++) {
- struct mainstone_led *led;
-
- led = kzalloc(sizeof(*led), GFP_KERNEL);
- if (!led)
- break;
-
- led->cdev.name = mainstone_leds[i].name;
- led->cdev.brightness_set = mainstone_led_set;
- led->cdev.brightness_get = mainstone_led_get;
- led->cdev.default_trigger = mainstone_leds[i].trigger;
- led->mask = BIT(i);
-
- if (led_classdev_register(NULL, &led->cdev) < 0) {
- kfree(led);
- break;
- }
- }
-
- return 0;
-}
-
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(mainstone_leds_init);
-#endif
-
-MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
- /* Maintainer: MontaVista Software Inc. */
- .atag_offset = 0x100, /* BLOB boot parameter setting */
- .map_io = mainstone_map_io,
- .nr_irqs = MAINSTONE_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = mainstone_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/mfp-pxa25x.h b/arch/arm/mach-pxa/mfp-pxa25x.h
index d0ebb2154503..3dc5c833e28f 100644
--- a/arch/arm/mach-pxa/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/mfp-pxa25x.h
@@ -158,39 +158,6 @@
#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
-#ifdef CONFIG_CPU_PXA26x
-/* GPIO */
-#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
-#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1)
-#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1)
-#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1)
-#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1)
-
-/* SDRAM */
-#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH)
-#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH)
-#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH)
-
-/* USB */
-#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1)
-#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2)
-#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2)
-#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW)
-#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
-#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH)
-
-/* ASSP */
-#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3)
-#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW)
-#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3)
-#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
-#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1)
-#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
-
-/* AC97 */
-#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH)
-#endif /* CONFIG_CPU_PXA26x */
-
/* commonly used pin configurations */
#define GPIOxx_LCD_16BPP \
GPIO58_LCD_LDD_0, \
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 6a5451b186c2..b556452dfcf9 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -16,8 +16,9 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
+#include <linux/soc/pxa/cpu.h>
-#include <mach/pxa2xx-regs.h>
+#include "pxa2xx-regs.h"
#include "mfp-pxa2xx.h"
#include "generic.h"
@@ -225,11 +226,7 @@ static void __init pxa25x_mfp_init(void)
int i;
/* running before pxa_gpio_probe() */
-#ifdef CONFIG_CPU_PXA26x
- pxa_last_gpio = 89;
-#else
pxa_last_gpio = 84;
-#endif
for (i = 0; i <= pxa_last_gpio; i++)
gpio_desc[i].valid = 1;
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.h b/arch/arm/mach-pxa/mfp-pxa2xx.h
index 980145e7ee99..683a3ea5f154 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.h
@@ -2,7 +2,7 @@
#ifndef __ASM_ARCH_MFP_PXA2XX_H
#define __ASM_ARCH_MFP_PXA2XX_H
-#include <plat/mfp.h>
+#include <linux/soc/pxa/mfp.h>
/*
* the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c
index 56114df9700d..d16ab7451efe 100644
--- a/arch/arm/mach-pxa/mfp-pxa3xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c
@@ -16,9 +16,8 @@
#include <linux/io.h>
#include <linux/syscore_ops.h>
-#include <mach/hardware.h>
#include "mfp-pxa3xx.h"
-#include <mach/pxa3xx-regs.h>
+#include "pxa3xx-regs.h"
#ifdef CONFIG_PM
/*
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.h b/arch/arm/mach-pxa/mfp-pxa3xx.h
index cdd830926d1c..81fec4fa5a0f 100644
--- a/arch/arm/mach-pxa/mfp-pxa3xx.h
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.h
@@ -2,7 +2,7 @@
#ifndef __ASM_ARCH_MFP_PXA3XX_H
#define __ASM_ARCH_MFP_PXA3XX_H
-#include <plat/mfp.h>
+#include <linux/soc/pxa/mfp.h>
#define MFPR_BASE (0x40e10000)
diff --git a/arch/arm/mach-pxa/mfp-pxa930.h b/arch/arm/mach-pxa/mfp-pxa930.h
deleted file mode 100644
index 0d195d3a8c61..000000000000
--- a/arch/arm/mach-pxa/mfp-pxa930.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/mfp-pxa930.h
- *
- * PXA930 specific MFP configuration definitions
- *
- * Copyright (C) 2007-2008 Marvell International Ltd.
- */
-
-#ifndef __ASM_ARCH_MFP_PXA9xx_H
-#define __ASM_ARCH_MFP_PXA9xx_H
-
-#include "mfp-pxa3xx.h"
-
-/* GPIO */
-#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
-#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
-#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
-#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
-
-#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0)
-#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0)
-#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0)
-#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0)
-
-#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0)
-#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0)
-#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0)
-#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0)
-#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0)
-#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0)
-#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0)
-#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0)
-#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0)
-#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0)
-#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0)
-#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0)
-#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0)
-#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0)
-#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0)
-#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0)
-#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0)
-#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0)
-#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0)
-#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0)
-#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0)
-#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0)
-#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0)
-#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0)
-#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0)
-
-#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0)
-#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0)
-#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0)
-#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0)
-#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0)
-#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0)
-#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0)
-#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0)
-#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0)
-#define RDY_GPIO_62 MFP_CFG(RDY, AF0)
-#define PMIC_INT_GPIO83 MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH)
-
-/* Chip Select */
-#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
-#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
-
-/* AC97 */
-#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3)
-#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3)
-#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3)
-#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3)
-#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3)
-#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3)
-
-/* I2C */
-#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
-#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
-
-#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
-#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
-
-#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
-#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
-
-#define GPIO73_CI2C_SCL MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH)
-#define GPIO74_CI2C_SDA MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH)
-
-#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
-#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
-
-#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
-#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
-
-#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
-#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
-
-#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
-#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
-
-/* QCI */
-#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
-#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
-#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
-#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
-#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
-#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
-#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
-#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
-#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
-#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
-#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
-#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
-#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
-#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
-
-/* KEYPAD */
-#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT)
-#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT)
-#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT)
-#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT)
-#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT)
-#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
-#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
-#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT)
-
-#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT)
-#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT)
-#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT)
-#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT)
-
-#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT)
-#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT)
-#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT)
-#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT)
-#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT)
-#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT)
-
-#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT)
-#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT)
-#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT)
-#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT)
-#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT)
-#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT)
-#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT)
-#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1)
-#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4)
-
-#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
-#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
-#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
-#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
-#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
-#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
-#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
-#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
-#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
-
-/* LCD */
-#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1)
-#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1)
-#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1)
-#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1)
-#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1)
-#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2)
-#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1)
-#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1)
-#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1)
-#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1)
-#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1)
-#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1)
-#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1)
-#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1)
-#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1)
-#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1)
-#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1)
-#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1)
-#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1)
-#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1)
-#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1)
-#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1)
-#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1)
-#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1)
-#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1)
-#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3)
-#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3)
-#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1)
-
-/* Mini-LCD */
-#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3)
-#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3)
-#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3)
-#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3)
-#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3)
-#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3)
-#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3)
-#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3)
-#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3)
-#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3)
-#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3)
-#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3)
-#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3)
-#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3)
-#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3)
-#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3)
-#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3)
-#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3)
-#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3)
-#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3)
-#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5)
-
-/* MMC1 */
-#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4)
-#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4)
-#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4)
-#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4)
-#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4)
-#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4)
-#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3)
-#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3)
-#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3)
-#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3)
-#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3)
-#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3)
-
-#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2)
-#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2)
-#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2)
-#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3)
-#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2)
-
-/* MMC2 */
-#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7)
-#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7)
-#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7)
-#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7)
-#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7)
-#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7)
-
-#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1)
-#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1)
-#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1)
-#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1)
-#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1)
-#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1)
-
-#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3)
-#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3)
-#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3)
-#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3)
-#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3)
-#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3)
-
-/* BSSP1 */
-#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3)
-#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3)
-#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3)
-#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3)
-#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5)
-#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5)
-
-/* BSSP2 */
-#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1)
-#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1)
-#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1)
-#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1)
-#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1)
-#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4)
-
-/* BSSP3 */
-#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1)
-#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1)
-#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1)
-#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1)
-#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1)
-
-/* BSSP4 */
-#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4)
-#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4)
-#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4)
-#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4)
-
-#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4)
-#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4)
-#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4)
-#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4)
-
-/* GSSP1 */
-#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2)
-#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2)
-#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2)
-#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2)
-#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2)
-
-#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4)
-#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4)
-#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4)
-#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4)
-
-/* GSSP2 */
-#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4)
-#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4)
-#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4)
-#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4)
-
-#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4)
-#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4)
-#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4)
-#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4)
-
-#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2)
-#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2)
-#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2)
-#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2)
-#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2)
-#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5)
-
-#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2)
-#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2)
-#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2)
-#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2)
-
-/* UART1 - FFUART */
-#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1)
-#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1)
-#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1)
-#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1)
-#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1)
-#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1)
-#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1)
-#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1)
-
-#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2)
-#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2)
-#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2)
-#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2)
-#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2)
-#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2)
-#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2)
-#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2)
-
-#define GPIO53_UART1_TXD MFP_CFG(GPIO53, AF2)
-#define GPIO54_UART1_RXD MFP_CFG(GPIO54, AF2)
-
-/* UART2 - BTUART */
-#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1)
-#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1)
-#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1)
-#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1)
-
-/* UART3 - STUART */
-#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3)
-#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3)
-#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3)
-#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3)
-
-#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5)
-#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5)
-#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5)
-#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5)
-
-/* DFI */
-#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2)
-#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2)
-#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2)
-#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2)
-#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2)
-#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2)
-#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2)
-#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2)
-#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2)
-#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2)
-#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2)
-#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2)
-#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2)
-#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2)
-#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2)
-#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2)
-#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2)
-#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2)
-#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2)
-#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2)
-#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2)
-#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2)
-
-/* DFI - NAND */
-#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
-#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
-#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
-#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
-#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
-#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
-#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
-#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
-#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
-#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
-#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
-#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
-#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
-#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
-#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
-#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
-#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
-#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
-#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
-#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
-#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
-#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
-#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
-#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
-#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
-
-/* PWM */
-#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
-#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
-#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
-#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
-#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
-#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
-#define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW)
-
-/* CIR */
-#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1)
-#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3)
-
-/* USB P2 */
-#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3)
-#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5)
-#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2)
-#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7)
-#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6)
-#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3)
-
-#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2)
-#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
-#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2)
-#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2)
-#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2)
-#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2)
-#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2)
-#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2)
-
-#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3)
-#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3)
-#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3)
-#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3)
-#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3)
-#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3)
-#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3)
-#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3)
-
-/* ULPI */
-#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4)
-#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7)
-#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5)
-#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5)
-#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5)
-#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5)
-#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5)
-#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5)
-#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4)
-#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4)
-#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4)
-#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4)
-
-#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3)
-#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7)
-#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5)
-#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4)
-#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3)
-#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3)
-
-#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5)
-#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7)
-#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5)
-#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4)
-
-#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3)
-#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7)
-#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3)
-#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5)
-#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4)
-#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3)
-
-/* 1 wire */
-#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5)
-
-#endif /* __ASM_ARCH_MFP_PXA9xx_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/mfp.h
index dbb961fb570e..7e0879bd4102 100644
--- a/arch/arm/mach-pxa/include/mach/mfp.h
+++ b/arch/arm/mach-pxa/mfp.h
@@ -13,6 +13,6 @@
#ifndef __ASM_ARCH_MFP_H
#define __ASM_ARCH_MFP_H
-#include <plat/mfp.h>
+#include <linux/soc/pxa/mfp.h>
#endif /* __ASM_ARCH_MFP_H */
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
deleted file mode 100644
index a79f296e81e0..000000000000
--- a/arch/arm/mach-pxa/mioa701.c
+++ /dev/null
@@ -1,784 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Handles the Mitac Mio A701 Board
- *
- * Copyright (C) 2008 Robert Jarzmik
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/gpio_keys.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/rtc.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/pda_power.h>
-#include <linux/power_supply.h>
-#include <linux/wm97xx.h>
-#include <linux/mtd/physmap.h>
-#include <linux/reboot.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/max1586.h>
-#include <linux/slab.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa27x.h"
-#include "regs-rtc.h"
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include "udc.h"
-#include "pxa27x-udc.h"
-#include <linux/platform_data/media/camera-pxa.h>
-#include <mach/audio.h>
-#include <mach/smemc.h>
-
-#include "mioa701.h"
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned long mioa701_pin_config[] = {
- /* Mio global */
- MIO_CFG_OUT(GPIO9_CHARGE_EN, AF0, DRIVE_LOW),
- MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW),
- MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH),
- MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH),
- MIO_CFG_IN(GPIO80_MAYBE_CHARGE_VDROP, AF0),
-
- /* Backlight PWM 0 */
- GPIO16_PWM0_OUT,
-
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- MIO_CFG_IN(GPIO78_SDIO_RO, AF0),
- MIO_CFG_IN(GPIO15_SDIO_INSERT, AF0),
- MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW),
-
- /* USB */
- MIO_CFG_IN(GPIO13_nUSB_DETECT, AF0),
- MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW),
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* QCI */
- GPIO12_CIF_DD_7,
- GPIO17_CIF_DD_6,
- GPIO50_CIF_DD_3,
- GPIO51_CIF_DD_2,
- GPIO52_CIF_DD_4,
- GPIO53_CIF_MCLK,
- GPIO54_CIF_PCLK,
- GPIO55_CIF_DD_1,
- GPIO81_CIF_DD_0,
- GPIO82_CIF_DD_5,
- GPIO84_CIF_FV,
- GPIO85_CIF_LV,
- MIO_CFG_OUT(GPIO56_MT9M111_nOE, AF0, DRIVE_LOW),
-
- /* Bluetooth */
- MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0),
- GPIO44_BTUART_CTS,
- GPIO42_BTUART_RXD,
- GPIO45_BTUART_RTS,
- GPIO43_BTUART_TXD,
- MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW),
- MIO_CFG_OUT(GPIO77_BT_UNKNOWN1, AF0, DRIVE_HIGH),
- MIO_CFG_OUT(GPIO86_BT_MAYBE_nRESET, AF0, DRIVE_HIGH),
-
- /* GPS */
- MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW),
- MIO_CFG_OUT(GPIO26_GPS_ON, AF0, DRIVE_LOW),
- MIO_CFG_OUT(GPIO27_GPS_RESET, AF0, DRIVE_LOW),
- MIO_CFG_OUT(GPIO106_GPS_UNKNOWN2, AF0, DRIVE_LOW),
- MIO_CFG_OUT(GPIO107_GPS_UNKNOWN3, AF0, DRIVE_LOW),
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* GSM */
- MIO_CFG_OUT(GPIO24_GSM_MOD_RESET_CMD, AF0, DRIVE_LOW),
- MIO_CFG_OUT(GPIO88_GSM_nMOD_ON_CMD, AF0, DRIVE_HIGH),
- MIO_CFG_OUT(GPIO90_GSM_nMOD_OFF_CMD, AF0, DRIVE_HIGH),
- MIO_CFG_OUT(GPIO114_GSM_nMOD_DTE_UART_STATE, AF0, DRIVE_HIGH),
- MIO_CFG_IN(GPIO25_GSM_MOD_ON_STATE, AF0),
- MIO_CFG_IN(GPIO113_GSM_EVENT, AF0) | WAKEUP_ON_EDGE_BOTH,
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
- GPIO36_FFUART_DCD,
- GPIO37_FFUART_DSR,
- GPIO39_FFUART_TXD,
- GPIO40_FFUART_DTR,
- GPIO41_FFUART_RTS,
-
- /* Sound */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO89_AC97_SYSCLK,
- MIO_CFG_IN(GPIO12_HPJACK_INSERT, AF0),
-
- /* Leds */
- MIO_CFG_OUT(GPIO10_LED_nCharging, AF0, DRIVE_HIGH),
- MIO_CFG_OUT(GPIO97_LED_nBlue, AF0, DRIVE_HIGH),
- MIO_CFG_OUT(GPIO98_LED_nOrange, AF0, DRIVE_HIGH),
- MIO_CFG_OUT(GPIO82_LED_nVibra, AF0, DRIVE_HIGH),
- MIO_CFG_OUT(GPIO115_LED_nKeyboard, AF0, DRIVE_HIGH),
-
- /* Keyboard */
- MIO_CFG_IN(GPIO0_KEY_POWER, AF0) | WAKEUP_ON_EDGE_BOTH,
- MIO_CFG_IN(GPIO93_KEY_VOLUME_UP, AF0),
- MIO_CFG_IN(GPIO94_KEY_VOLUME_DOWN, AF0),
- GPIO100_KP_MKIN_0,
- GPIO101_KP_MKIN_1,
- GPIO102_KP_MKIN_2,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* Unknown */
- MFP_CFG_IN(GPIO20, AF0),
- MFP_CFG_IN(GPIO21, AF0),
- MFP_CFG_IN(GPIO33, AF0),
- MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH),
- MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH),
- MFP_CFG_IN(GPIO96, AF0),
- MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH),
-};
-
-static struct pwm_lookup mioa701_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight", NULL, 4000 * 1024,
- PWM_POLARITY_NORMAL),
-};
-
-/* LCD Screen and Backlight */
-static struct platform_pwm_backlight_data mioa701_backlight_data = {
- .max_brightness = 100,
- .dft_brightness = 50,
-};
-
-/*
- * LTM0305A776C LCD panel timings
- *
- * see:
- * - the LTM0305A776C datasheet,
- * - and the PXA27x Programmers' manual
- */
-static struct pxafb_mode_info mioa701_ltm0305a776c = {
- .pixclock = 220000, /* CLK=4.545 MHz */
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 4,
- .vsync_len = 2,
- .left_margin = 6,
- .right_margin = 4,
- .upper_margin = 5,
- .lower_margin = 3,
-};
-
-static void mioa701_lcd_power(int on, struct fb_var_screeninfo *si)
-{
- gpio_set_value(GPIO87_LCD_POWER, on);
-}
-
-static struct pxafb_mach_info mioa701_pxafb_info = {
- .modes = &mioa701_ltm0305a776c,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
- .pxafb_lcd_power = mioa701_lcd_power,
-};
-
-/*
- * Keyboard configuration
- */
-static const unsigned int mioa701_matrix_keys[] = {
- KEY(0, 0, KEY_UP),
- KEY(0, 1, KEY_RIGHT),
- KEY(0, 2, KEY_MEDIA),
- KEY(1, 0, KEY_DOWN),
- KEY(1, 1, KEY_ENTER),
- KEY(1, 2, KEY_CONNECT), /* GPS key */
- KEY(2, 0, KEY_LEFT),
- KEY(2, 1, KEY_PHONE), /* Phone Green key */
- KEY(2, 2, KEY_CAMERA) /* Camera key */
-};
-
-static struct matrix_keymap_data mioa701_matrix_keymap_data = {
- .keymap = mioa701_matrix_keys,
- .keymap_size = ARRAY_SIZE(mioa701_matrix_keys),
-};
-
-static struct pxa27x_keypad_platform_data mioa701_keypad_info = {
- .matrix_key_rows = 3,
- .matrix_key_cols = 3,
- .matrix_keymap_data = &mioa701_matrix_keymap_data,
-};
-
-/*
- * GPIO Key Configuration
- */
-#define MIO_KEY(key, _gpio, _desc, _wakeup) \
- { .code = (key), .gpio = (_gpio), .active_low = 0, \
- .desc = (_desc), .type = EV_KEY, .wakeup = (_wakeup) }
-static struct gpio_keys_button mioa701_button_table[] = {
- MIO_KEY(KEY_EXIT, GPIO0_KEY_POWER, "Power button", 1),
- MIO_KEY(KEY_VOLUMEUP, GPIO93_KEY_VOLUME_UP, "Volume up", 0),
- MIO_KEY(KEY_VOLUMEDOWN, GPIO94_KEY_VOLUME_DOWN, "Volume down", 0),
- MIO_KEY(KEY_HP, GPIO12_HPJACK_INSERT, "HP jack detect", 0)
-};
-
-static struct gpio_keys_platform_data mioa701_gpio_keys_data = {
- .buttons = mioa701_button_table,
- .nbuttons = ARRAY_SIZE(mioa701_button_table),
-};
-
-/*
- * Leds and vibrator
- */
-#define ONE_LED(_gpio, _name) \
-{ .gpio = (_gpio), .name = (_name), .active_low = true }
-static struct gpio_led gpio_leds[] = {
- ONE_LED(GPIO10_LED_nCharging, "mioa701:charging"),
- ONE_LED(GPIO97_LED_nBlue, "mioa701:blue"),
- ONE_LED(GPIO98_LED_nOrange, "mioa701:orange"),
- ONE_LED(GPIO82_LED_nVibra, "mioa701:vibra"),
- ONE_LED(GPIO115_LED_nKeyboard, "mioa701:keyboard")
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-/*
- * GSM Sagem XS200 chip
- *
- * GSM handling was purged from kernel. For history, this is the way to go :
- * - init : GPIO24_GSM_MOD_RESET_CMD = 0, GPIO114_GSM_nMOD_DTE_UART_STATE = 1
- * GPIO88_GSM_nMOD_ON_CMD = 1, GPIO90_GSM_nMOD_OFF_CMD = 1
- * - reset : GPIO24_GSM_MOD_RESET_CMD = 1, msleep(100),
- * GPIO24_GSM_MOD_RESET_CMD = 0
- * - turn on : GPIO88_GSM_nMOD_ON_CMD = 0, msleep(1000),
- * GPIO88_GSM_nMOD_ON_CMD = 1
- * - turn off : GPIO90_GSM_nMOD_OFF_CMD = 0, msleep(1000),
- * GPIO90_GSM_nMOD_OFF_CMD = 1
- */
-static int is_gsm_on(void)
-{
- int is_on;
-
- is_on = !!gpio_get_value(GPIO25_GSM_MOD_ON_STATE);
- return is_on;
-}
-
-irqreturn_t gsm_on_irq(int irq, void *p)
-{
- printk(KERN_DEBUG "Mioa701: GSM status changed to %s\n",
- is_gsm_on() ? "on" : "off");
- return IRQ_HANDLED;
-}
-
-static struct gpio gsm_gpios[] = {
- { GPIO25_GSM_MOD_ON_STATE, GPIOF_IN, "GSM state" },
- { GPIO113_GSM_EVENT, GPIOF_IN, "GSM event" },
-};
-
-static int __init gsm_init(void)
-{
- int rc;
-
- rc = gpio_request_array(ARRAY_AND_SIZE(gsm_gpios));
- if (rc)
- goto err_gpio;
- rc = request_irq(gpio_to_irq(GPIO25_GSM_MOD_ON_STATE), gsm_on_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "GSM XS200 Power Irq", NULL);
- if (rc)
- goto err_irq;
-
- gpio_set_wake(GPIO113_GSM_EVENT, 1);
- return 0;
-
-err_irq:
- printk(KERN_ERR "Mioa701: Can't request GSM_ON irq\n");
- gpio_free_array(ARRAY_AND_SIZE(gsm_gpios));
-err_gpio:
- printk(KERN_ERR "Mioa701: gsm not available\n");
- return rc;
-}
-
-static void gsm_exit(void)
-{
- free_irq(gpio_to_irq(GPIO25_GSM_MOD_ON_STATE), NULL);
- gpio_free_array(ARRAY_AND_SIZE(gsm_gpios));
-}
-
-/*
- * Bluetooth BRF6150 chip
- *
- * BT handling was purged from kernel. For history, this is the way to go :
- * - turn on : GPIO83_BT_ON = 1
- * - turn off : GPIO83_BT_ON = 0
- */
-
-/*
- * GPS Sirf Star III chip
- *
- * GPS handling was purged from kernel. For history, this is the way to go :
- * - init : GPIO23_GPS_UNKNOWN1 = 1, GPIO26_GPS_ON = 0, GPIO27_GPS_RESET = 0
- * GPIO106_GPS_UNKNOWN2 = 0, GPIO107_GPS_UNKNOWN3 = 0
- * - turn on : GPIO27_GPS_RESET = 1, GPIO26_GPS_ON = 1
- * - turn off : GPIO26_GPS_ON = 0, GPIO27_GPS_RESET = 0
- */
-
-/*
- * USB UDC
- */
-static int is_usb_connected(void)
-{
- return !gpio_get_value(GPIO13_nUSB_DETECT);
-}
-
-static struct pxa2xx_udc_mach_info mioa701_udc_info = {
- .udc_is_connected = is_usb_connected,
- .gpio_pullup = GPIO22_USB_ENABLE,
-};
-
-static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO13_nUSB_DETECT,
- "vbus", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/*
- * SDIO/MMC Card controller
- */
-/**
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
- */
-static struct pxamci_platform_data mioa701_mci_info = {
- .detect_delay_ms = 250,
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table mioa701_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on GPIO 15 */
- GPIO_LOOKUP("gpio-pxa", GPIO15_SDIO_INSERT,
- "cd", GPIO_ACTIVE_LOW),
- /* Write protect on GPIO 78 */
- GPIO_LOOKUP("gpio-pxa", GPIO78_SDIO_RO,
- "wp", GPIO_ACTIVE_LOW),
- /* Power on GPIO 91 */
- GPIO_LOOKUP("gpio-pxa", GPIO91_SDIO_EN,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/* FlashRAM */
-static struct resource docg3_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device docg3 = {
- .name = "docg3",
- .id = -1,
- .resource = &docg3_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = NULL,
- },
-};
-
-/*
- * Suspend/Resume bootstrap management
- *
- * MIO A701 reboot sequence is highly ROM dependent. From the one dissassembled,
- * this sequence is as follows :
- * - disables interrupts
- * - initialize SDRAM (self refresh RAM into active RAM)
- * - initialize GPIOs (depends on value at 0xa020b020)
- * - initialize coprossessors
- * - if edge detect on PWR_SCL(GPIO3), then proceed to cold start
- * - or if value at 0xa020b000 not equal to 0x0f0f0f0f, proceed to cold start
- * - else do a resume, ie. jump to addr 0xa0100000
- */
-#define RESUME_ENABLE_ADDR 0xa020b000
-#define RESUME_ENABLE_VAL 0x0f0f0f0f
-#define RESUME_BT_ADDR 0xa020b020
-#define RESUME_UNKNOWN_ADDR 0xa020b024
-#define RESUME_VECTOR_ADDR 0xa0100000
-#define BOOTSTRAP_WORDS mioa701_bootstrap_lg/4
-
-static u32 *save_buffer;
-
-static void install_bootstrap(void)
-{
- int i;
- u32 *rom_bootstrap = phys_to_virt(RESUME_VECTOR_ADDR);
- u32 *src = &mioa701_bootstrap;
-
- for (i = 0; i < BOOTSTRAP_WORDS; i++)
- rom_bootstrap[i] = src[i];
-}
-
-
-static int mioa701_sys_suspend(void)
-{
- int i = 0, is_bt_on;
- u32 *mem_resume_vector = phys_to_virt(RESUME_VECTOR_ADDR);
- u32 *mem_resume_enabler = phys_to_virt(RESUME_ENABLE_ADDR);
- u32 *mem_resume_bt = phys_to_virt(RESUME_BT_ADDR);
- u32 *mem_resume_unknown = phys_to_virt(RESUME_UNKNOWN_ADDR);
-
- /* Devices prepare suspend */
- is_bt_on = !!gpio_get_value(GPIO83_BT_ON);
- pxa2xx_mfp_set_lpm(GPIO83_BT_ON,
- is_bt_on ? MFP_LPM_DRIVE_HIGH : MFP_LPM_DRIVE_LOW);
-
- for (i = 0; i < BOOTSTRAP_WORDS; i++)
- save_buffer[i] = mem_resume_vector[i];
- save_buffer[i++] = *mem_resume_enabler;
- save_buffer[i++] = *mem_resume_bt;
- save_buffer[i++] = *mem_resume_unknown;
-
- *mem_resume_enabler = RESUME_ENABLE_VAL;
- *mem_resume_bt = is_bt_on;
-
- install_bootstrap();
- return 0;
-}
-
-static void mioa701_sys_resume(void)
-{
- int i = 0;
- u32 *mem_resume_vector = phys_to_virt(RESUME_VECTOR_ADDR);
- u32 *mem_resume_enabler = phys_to_virt(RESUME_ENABLE_ADDR);
- u32 *mem_resume_bt = phys_to_virt(RESUME_BT_ADDR);
- u32 *mem_resume_unknown = phys_to_virt(RESUME_UNKNOWN_ADDR);
-
- for (i = 0; i < BOOTSTRAP_WORDS; i++)
- mem_resume_vector[i] = save_buffer[i];
- *mem_resume_enabler = save_buffer[i++];
- *mem_resume_bt = save_buffer[i++];
- *mem_resume_unknown = save_buffer[i++];
-}
-
-static struct syscore_ops mioa701_syscore_ops = {
- .suspend = mioa701_sys_suspend,
- .resume = mioa701_sys_resume,
-};
-
-static int __init bootstrap_init(void)
-{
- int save_size = mioa701_bootstrap_lg + (sizeof(u32) * 3);
-
- register_syscore_ops(&mioa701_syscore_ops);
-
- save_buffer = kmalloc(save_size, GFP_KERNEL);
- if (!save_buffer)
- return -ENOMEM;
- printk(KERN_INFO "MioA701: allocated %d bytes for bootstrap\n",
- save_size);
- return 0;
-}
-
-static void bootstrap_exit(void)
-{
- kfree(save_buffer);
- unregister_syscore_ops(&mioa701_syscore_ops);
-
- printk(KERN_CRIT "Unregistering mioa701 suspend will hang next"
- "resume !!!\n");
-}
-
-/*
- * Power Supply
- */
-static char *supplicants[] = {
- "mioa701_battery"
-};
-
-static int is_ac_connected(void)
-{
- return gpio_get_value(GPIO96_AC_DETECT);
-}
-
-static void mioa701_set_charge(int flags)
-{
- gpio_set_value(GPIO9_CHARGE_EN, (flags == PDA_POWER_CHARGE_USB));
-}
-
-static struct pda_power_pdata power_pdata = {
- .is_ac_online = is_ac_connected,
- .is_usb_online = is_usb_connected,
- .set_charge = mioa701_set_charge,
- .supplied_to = supplicants,
- .num_supplicants = ARRAY_SIZE(supplicants),
-};
-
-static struct resource power_resources[] = {
- [0] = {
- .name = "ac",
- .start = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT),
- .end = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_LOWEDGE,
- },
- [1] = {
- .name = "usb",
- .start = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT),
- .end = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device power_dev = {
- .name = "pda-power",
- .id = -1,
- .resource = power_resources,
- .num_resources = ARRAY_SIZE(power_resources),
- .dev = {
- .platform_data = &power_pdata,
- },
-};
-
-static struct wm97xx_batt_pdata mioa701_battery_data = {
- .batt_aux = WM97XX_AUX_ID1,
- .temp_aux = -1,
- .min_voltage = 0xc00,
- .max_voltage = 0xfc0,
- .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION,
- .batt_div = 1,
- .batt_mult = 1,
- .batt_name = "mioa701_battery",
-};
-
-static struct wm97xx_pdata mioa701_wm97xx_pdata = {
- .batt_pdata = &mioa701_battery_data,
-};
-
-/*
- * Voltage regulation
- */
-static struct regulator_consumer_supply max1586_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data max1586_v3_info = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 1000000,
- .max_uV = 1705000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(max1586_consumers),
- .consumer_supplies = max1586_consumers,
-};
-
-static struct max1586_subdev_data max1586_subdevs[] = {
- { .name = "vcc_core", .id = MAX1586_V3,
- .platform_data = &max1586_v3_info },
-};
-
-static struct max1586_platform_data max1586_info = {
- .subdevs = max1586_subdevs,
- .num_subdevs = ARRAY_SIZE(max1586_subdevs),
- .v3_gain = MAX1586_GAIN_NO_R24, /* 700..1475 mV */
-};
-
-/*
- * Camera interface
- */
-struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
- .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
- PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
- .mclk_10khz = 5000,
- .sensor_i2c_adapter_id = 0,
- .sensor_i2c_address = 0x5d,
-};
-
-static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
- {
- I2C_BOARD_INFO("max1586", 0x14),
- .platform_data = &max1586_info,
- },
-};
-
-/* Board I2C devices. */
-static struct i2c_board_info mioa701_i2c_devices[] = {
- {
- I2C_BOARD_INFO("mt9m111", 0x5d),
- },
-};
-
-struct i2c_pxa_platform_data i2c_pdata = {
- .fast_mode = 1,
-};
-
-static pxa2xx_audio_ops_t mioa701_ac97_info = {
- .reset_gpio = 95,
- .codec_pdata = { &mioa701_wm97xx_pdata, },
-};
-
-/*
- * Mio global
- */
-
-/* Devices */
-#define MIO_PARENT_DEV(var, strname, tparent, pdata) \
-static struct platform_device var = { \
- .name = strname, \
- .id = -1, \
- .dev = { \
- .platform_data = pdata, \
- .parent = tparent, \
- }, \
-};
-#define MIO_SIMPLE_DEV(var, strname, pdata) \
- MIO_PARENT_DEV(var, strname, NULL, pdata)
-
-MIO_SIMPLE_DEV(mioa701_gpio_keys, "gpio-keys", &mioa701_gpio_keys_data)
-MIO_PARENT_DEV(mioa701_backlight, "pwm-backlight", &pxa27x_device_pwm0.dev,
- &mioa701_backlight_data);
-MIO_SIMPLE_DEV(mioa701_led, "leds-gpio", &gpio_led_info)
-MIO_SIMPLE_DEV(pxa2xx_pcm, "pxa2xx-pcm", NULL)
-MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL)
-MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL)
-MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", NULL);
-
-static struct platform_device *devices[] __initdata = {
- &mioa701_gpio_keys,
- &mioa701_backlight,
- &mioa701_led,
- &pxa2xx_pcm,
- &mioa701_sound,
- &power_dev,
- &docg3,
- &gpio_vbus,
- &mioa701_board,
-};
-
-static void mioa701_machine_exit(void);
-
-static void mioa701_poweroff(void)
-{
- mioa701_machine_exit();
- pxa_restart(REBOOT_SOFT, NULL);
-}
-
-static void mioa701_restart(enum reboot_mode c, const char *cmd)
-{
- mioa701_machine_exit();
- pxa_restart(REBOOT_SOFT, cmd);
-}
-
-static struct gpio global_gpios[] = {
- { GPIO9_CHARGE_EN, GPIOF_OUT_INIT_HIGH, "Charger enable" },
- { GPIO18_POWEROFF, GPIOF_OUT_INIT_LOW, "Power Off" },
- { GPIO87_LCD_POWER, GPIOF_OUT_INIT_LOW, "LCD Power" },
- { GPIO56_MT9M111_nOE, GPIOF_OUT_INIT_LOW, "Camera nOE" },
-};
-
-static struct regulator_consumer_supply fixed_5v0_consumers[] = {
- REGULATOR_SUPPLY("power", "pwm-backlight"),
-};
-
-static void __init mioa701_machine_init(void)
-{
- int rc;
-
- PSLR = 0xff100000; /* SYSDEL=125ms, PWRDEL=125ms, PSLR_SL_ROD=1 */
- PCFR = PCFR_DC_EN | PCFR_GPR_EN | PCFR_OPDE;
- RTTR = 32768 - 1; /* Reset crazy WinCE value */
- UP2OCR = UP2OCR_HXOE;
-
- /*
- * Set up the flash memory : DiskOnChip G3 on first static memory bank
- */
- __raw_writel(0x7ff02dd8, MSC0);
- __raw_writel(0x0001c391, MCMEM0);
- __raw_writel(0x0001c391, MCATT0);
- __raw_writel(0x0001c391, MCIO0);
-
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- rc = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
- if (rc)
- pr_err("MioA701: Failed to request GPIOs: %d", rc);
- bootstrap_init();
- pxa_set_fb_info(NULL, &mioa701_pxafb_info);
- gpiod_add_lookup_table(&mioa701_mci_gpio_table);
- pxa_set_mci_info(&mioa701_mci_info);
- pxa_set_keypad_info(&mioa701_keypad_info);
- pxa_set_udc_info(&mioa701_udc_info);
- pxa_set_ac97_info(&mioa701_ac97_info);
- pm_power_off = mioa701_poweroff;
- pwm_add_table(mioa701_pwm_lookup, ARRAY_SIZE(mioa701_pwm_lookup));
- gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
- platform_add_devices(devices, ARRAY_SIZE(devices));
- gsm_init();
-
- i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices));
- i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices));
- pxa_set_i2c_info(&i2c_pdata);
- pxa27x_set_i2c_power_info(NULL);
- pxa_set_camera_info(&mioa701_pxacamera_platform_data);
-
- regulator_register_always_on(0, "fixed-5.0V", fixed_5v0_consumers,
- ARRAY_SIZE(fixed_5v0_consumers),
- 5000000);
- regulator_has_full_constraints();
-}
-
-static void mioa701_machine_exit(void)
-{
- bootstrap_exit();
- gsm_exit();
-}
-
-MACHINE_START(MIOA701, "MIO A701")
- .atag_offset = 0x100,
- .map_io = &pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = &pxa27x_init_irq,
- .handle_irq = &pxa27x_handle_irq,
- .init_machine = mioa701_machine_init,
- .init_time = pxa_timer_init,
- .restart = mioa701_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/mioa701.h b/arch/arm/mach-pxa/mioa701.h
deleted file mode 100644
index d94295c67460..000000000000
--- a/arch/arm/mach-pxa/mioa701.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _MIOA701_H_
-#define _MIOA701_H_
-
-#define MIO_CFG_IN(pin, af) \
- ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
- (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN))
-
-#define MIO_CFG_OUT(pin, af, state) \
- ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
- (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
-
-/* Global GPIOs */
-#define GPIO9_CHARGE_EN 9
-#define GPIO18_POWEROFF 18
-#define GPIO87_LCD_POWER 87
-#define GPIO96_AC_DETECT 96
-#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */
-
-/* USB */
-#define GPIO13_nUSB_DETECT 13
-#define GPIO22_USB_ENABLE 22
-
-/* SDIO bits */
-#define GPIO78_SDIO_RO 78
-#define GPIO15_SDIO_INSERT 15
-#define GPIO91_SDIO_EN 91
-
-/* Bluetooth */
-#define GPIO14_BT_nACTIVITY 14
-#define GPIO83_BT_ON 83
-#define GPIO77_BT_UNKNOWN1 77
-#define GPIO86_BT_MAYBE_nRESET 86
-
-/* GPS */
-#define GPIO23_GPS_UNKNOWN1 23
-#define GPIO26_GPS_ON 26
-#define GPIO27_GPS_RESET 27
-#define GPIO106_GPS_UNKNOWN2 106
-#define GPIO107_GPS_UNKNOWN3 107
-
-/* GSM */
-#define GPIO24_GSM_MOD_RESET_CMD 24
-#define GPIO88_GSM_nMOD_ON_CMD 88
-#define GPIO90_GSM_nMOD_OFF_CMD 90
-#define GPIO114_GSM_nMOD_DTE_UART_STATE 114
-#define GPIO25_GSM_MOD_ON_STATE 25
-#define GPIO113_GSM_EVENT 113
-
-/* SOUND */
-#define GPIO12_HPJACK_INSERT 12
-
-/* LEDS */
-#define GPIO10_LED_nCharging 10
-#define GPIO97_LED_nBlue 97
-#define GPIO98_LED_nOrange 98
-#define GPIO82_LED_nVibra 82
-#define GPIO115_LED_nKeyboard 115
-
-/* Keyboard */
-#define GPIO0_KEY_POWER 0
-#define GPIO93_KEY_VOLUME_UP 93
-#define GPIO94_KEY_VOLUME_DOWN 94
-
-/* Camera */
-#define GPIO56_MT9M111_nOE 56
-
-extern struct input_dev *mioa701_evdev;
-extern void mioa701_gpio_lpm_set(unsigned long mfp_pin);
-
-/* Assembler externals mioa701_bootresume.S */
-extern u32 mioa701_bootstrap;
-extern u32 mioa701_jumpaddr;
-extern u32 mioa701_bootstrap_lg;
-
-#endif /* _MIOA701_H */
diff --git a/arch/arm/mach-pxa/mioa701_bootresume.S b/arch/arm/mach-pxa/mioa701_bootresume.S
deleted file mode 100644
index 4ad2fa27fc41..000000000000
--- a/arch/arm/mach-pxa/mioa701_bootresume.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Bootloader to resume MIO A701
- *
- * 2007-1-12 Robert Jarzmik
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-/*
- * Note: Yes, part of the following code is located into the .data section.
- * This is to allow jumpaddr to be accessed with a relative load
- * while we can't rely on any MMU translation. We could have put
- * sleep_save_sp in the .text section as well, but some setups might
- * insist on it to be truly read-only.
- */
- .data
- .align 2
-ENTRY(mioa701_bootstrap)
-0:
- b 1f
-ENTRY(mioa701_jumpaddr)
- .word 0x40f00008 @ PSPR in no-MMU mode
-1:
- mov r0, #0xa0000000 @ Don't suppose memory access works
- orr r0, r0, #0x00200000 @ even if it's supposed to
- orr r0, r0, #0x0000b000
- mov r1, #0
- str r1, [r0] @ Early disable resume for next boot
- ldr r0, mioa701_jumpaddr @ (Murphy's Law)
- ldr r0, [r0]
- ret r0
-2:
-
-ENTRY(mioa701_bootstrap_lg)
- .data
- .align 2
- .word 2b-0b
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
deleted file mode 100644
index 8ef8ac4ab4ac..000000000000
--- a/arch/arm/mach-pxa/mp900.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/mp900.c
- *
- * Support for the NEC MobilePro900/C platform
- *
- * Based on mach-pxa/gumstix.c
- *
- * 2007, 2008 Kristoffer Ericson <kristoffer.ericson@gmail.com>
- * 2007, 2008 Michael Petchkovsky <mkpetch@internode.on.net>
- */
-
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/usb/isp116x.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa25x.h"
-#include "generic.h"
-
-static void isp116x_pfm_delay(struct device *dev, int delay)
-{
-
- /* 400MHz PXA2 = 2.5ns / instruction */
-
- int cyc = delay / 10;
-
- /* 4 Instructions = 4 x 2.5ns = 10ns */
- __asm__ volatile ("0:\n"
- "subs %0, %1, #1\n"
- "bge 0b\n"
- :"=r" (cyc)
- :"0"(cyc)
- );
-}
-
-static struct isp116x_platform_data isp116x_pfm_data = {
- .remote_wakeup_enable = 1,
- .delay = isp116x_pfm_delay,
-};
-
-static struct resource isp116x_pfm_resources[] = {
- [0] = {
- .start = 0x0d000000,
- .end = 0x0d000000 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x0d000000 + 4,
- .end = 0x0d000000 + 5,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = 61,
- .end = 61,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mp900c_dummy_device = {
- .name = "mp900c_dummy",
- .id = -1,
-};
-
-static struct platform_device mp900c_usb = {
- .name = "isp116x-hcd",
- .num_resources = ARRAY_SIZE(isp116x_pfm_resources),
- .resource = isp116x_pfm_resources,
- .dev.platform_data = &isp116x_pfm_data,
-};
-
-static struct platform_device *devices[] __initdata = {
- &mp900c_dummy_device,
- &mp900c_usb,
-};
-
-static void __init mp900c_init(void)
-{
- printk(KERN_INFO "MobilePro 900/C machine init\n");
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-/* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
-MACHINE_START(NEC_MP900, "MobilePro900/C")
- .atag_offset = 0x220100,
- .init_time = pxa_timer_init,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_machine = mp900c_init,
- .restart = pxa_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
deleted file mode 100644
index fde386f6cffe..000000000000
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ /dev/null
@@ -1,481 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/mxm8x10.c
- *
- * Support for the Embedian MXM-8x10 Computer on Module
- *
- * Copyright (C) 2006 Marvell International Ltd.
- * Copyright (C) 2009 Embedian Inc.
- * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd.
- *
- * 2007-09-04: eric miao <eric.y.miao@gmail.com>
- * rewrite to align with latest kernel
- *
- * 2010-01-09: Edwin Peer <epeer@tmtservices.co.za>
- * Hennie van der Merwe <hvdmerwe@tmtservices.co.za>
- * rework for upstream merge
- */
-
-#include <linux/serial_8250.h>
-#include <linux/dm9000.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include "pxa320.h"
-
-#include "mxm8x10.h"
-
-#include "devices.h"
-#include "generic.h"
-
-/* GPIO pin definition
-
-External device stuff - Leave unconfigured for now...
----------------------
-GPIO0 - DREQ (External DMA Request)
-GPIO3 - nGCS2 (External Chip Select) Where is nGCS0; nGCS1; nGCS4; nGCS5 ?
-GPIO4 - nGCS3
-GPIO15 - EXT_GPIO1
-GPIO16 - EXT_GPIO2
-GPIO17 - EXT_GPIO3
-GPIO24 - EXT_GPIO4
-GPIO25 - EXT_GPIO5
-GPIO26 - EXT_GPIO6
-GPIO27 - EXT_GPIO7
-GPIO28 - EXT_GPIO8
-GPIO29 - EXT_GPIO9
-GPIO30 - EXT_GPIO10
-GPIO31 - EXT_GPIO11
-GPIO57 - EXT_GPIO12
-GPIO74 - EXT_IRQ1
-GPIO75 - EXT_IRQ2
-GPIO76 - EXT_IRQ3
-GPIO77 - EXT_IRQ4
-GPIO78 - EXT_IRQ5
-GPIO79 - EXT_IRQ6
-GPIO80 - EXT_IRQ7
-GPIO81 - EXT_IRQ8
-GPIO87 - VCCIO_PWREN (External Device PWREN)
-
-Dallas 1-Wire - Leave unconfigured for now...
--------------
-GPIO0_2 - DS - 1Wire
-
-Ethernet
---------
-GPIO1 - DM9000 PWR
-GPIO9 - DM9K_nIRQ
-GPIO36 - DM9K_RESET
-
-Keypad - Leave unconfigured by for now...
-------
-GPIO1_2 - KP_DKIN0
-GPIO5_2 - KP_MKOUT7
-GPIO82 - KP_DKIN1
-GPIO85 - KP_DKIN2
-GPIO86 - KP_DKIN3
-GPIO113 - KP_MKIN0
-GPIO114 - KP_MKIN1
-GPIO115 - KP_MKIN2
-GPIO116 - KP_MKIN3
-GPIO117 - KP_MKIN4
-GPIO118 - KP_MKIN5
-GPIO119 - KP_MKIN6
-GPIO120 - KP_MKIN7
-GPIO121 - KP_MKOUT0
-GPIO122 - KP_MKOUT1
-GPIO122 - KP_MKOUT2
-GPIO123 - KP_MKOUT3
-GPIO124 - KP_MKOUT4
-GPIO125 - KP_MKOUT5
-GPIO127 - KP_MKOUT6
-
-Data Bus - Leave unconfigured for now...
---------
-GPIO2 - nWait (Data Bus)
-
-USB Device
-----------
-GPIO4_2 - USBD_PULLUP
-GPIO10 - UTM_CLK (USB Device UTM Clk)
-GPIO49 - USB 2.0 Device UTM_DATA0
-GPIO50 - USB 2.0 Device UTM_DATA1
-GPIO51 - USB 2.0 Device UTM_DATA2
-GPIO52 - USB 2.0 Device UTM_DATA3
-GPIO53 - USB 2.0 Device UTM_DATA4
-GPIO54 - USB 2.0 Device UTM_DATA5
-GPIO55 - USB 2.0 Device UTM_DATA6
-GPIO56 - USB 2.0 Device UTM_DATA7
-GPIO58 - UTM_RXVALID (USB 2.0 Device)
-GPIO59 - UTM_RXACTIVE (USB 2.0 Device)
-GPIO60 - UTM_RXERROR
-GPIO61 - UTM_OPMODE0
-GPIO62 - UTM_OPMODE1
-GPIO71 - USBD_INT (USB Device?)
-GPIO73 - UTM_TXREADY (USB 2.0 Device)
-GPIO83 - UTM_TXVALID (USB 2.0 Device)
-GPIO98 - UTM_RESET (USB 2.0 device)
-GPIO99 - UTM_XCVR_SELECT
-GPIO100 - UTM_TERM_SELECT
-GPIO101 - UTM_SUSPENDM_X
-GPIO102 - UTM_LINESTATE0
-GPIO103 - UTM_LINESTATE1
-
-Card-Bus Interface - Leave unconfigured for now...
-------------------
-GPIO5 - nPIOR (I/O space output enable)
-GPIO6 - nPIOW (I/O space write enable)
-GPIO7 - nIOS16 (Input from I/O space telling size of data bus)
-GPIO8 - nPWAIT (Input for inserting wait states)
-
-LCD
----
-GPIO6_2 - LDD0
-GPIO7_2 - LDD1
-GPIO8_2 - LDD2
-GPIO9_2 - LDD3
-GPIO11_2 - LDD5
-GPIO12_2 - LDD6
-GPIO13_2 - LDD7
-GPIO14_2 - VSYNC
-GPIO15_2 - HSYNC
-GPIO16_2 - VCLK
-GPIO17_2 - HCLK
-GPIO18_2 - VDEN
-GPIO63 - LDD8 (CPU LCD)
-GPIO64 - LDD9 (CPU LCD)
-GPIO65 - LDD10 (CPU LCD)
-GPIO66 - LDD11 (CPU LCD)
-GPIO67 - LDD12 (CPU LCD)
-GPIO68 - LDD13 (CPU LCD)
-GPIO69 - LDD14 (CPU LCD)
-GPIO70 - LDD15 (CPU LCD)
-GPIO88 - VCCLCD_PWREN (LCD Panel PWREN)
-GPIO97 - BACKLIGHT_EN
-GPIO104 - LCD_PWREN
-
-PWM - Leave unconfigured for now...
----
-GPIO11 - PWM0
-GPIO12 - PWM1
-GPIO13 - PWM2
-GPIO14 - PWM3
-
-SD-CARD
--------
-GPIO18 - SDDATA0
-GPIO19 - SDDATA1
-GPIO20 - SDDATA2
-GPIO21 - SDDATA3
-GPIO22 - SDCLK
-GPIO23 - SDCMD
-GPIO72 - SD_WP
-GPIO84 - SD_nIRQ_CD (SD-Card)
-
-I2C
----
-GPIO32 - I2CSCL
-GPIO33 - I2CSDA
-
-AC97
-----
-GPIO35 - AC97_SDATA_IN
-GPIO37 - AC97_SDATA_OUT
-GPIO38 - AC97_SYNC
-GPIO39 - AC97_BITCLK
-GPIO40 - AC97_nRESET
-
-UART1
------
-GPIO41 - UART_RXD1
-GPIO42 - UART_TXD1
-GPIO43 - UART_CTS1
-GPIO44 - UART_DCD1
-GPIO45 - UART_DSR1
-GPIO46 - UART_nRI1
-GPIO47 - UART_DTR1
-GPIO48 - UART_RTS1
-
-UART2
------
-GPIO109 - RTS2
-GPIO110 - RXD2
-GPIO111 - TXD2
-GPIO112 - nCTS2
-
-UART3
------
-GPIO105 - nCTS3
-GPIO106 - nRTS3
-GPIO107 - TXD3
-GPIO108 - RXD3
-
-SSP3 - Leave unconfigured for now...
-----
-GPIO89 - SSP3_CLK
-GPIO90 - SSP3_SFRM
-GPIO91 - SSP3_TXD
-GPIO92 - SSP3_RXD
-
-SSP4
-GPIO93 - SSP4_CLK
-GPIO94 - SSP4_SFRM
-GPIO95 - SSP4_TXD
-GPIO96 - SSP4_RXD
-*/
-
-static mfp_cfg_t mfp_cfg[] __initdata = {
- /* USB */
- GPIO10_UTM_CLK,
- GPIO49_U2D_PHYDATA_0,
- GPIO50_U2D_PHYDATA_1,
- GPIO51_U2D_PHYDATA_2,
- GPIO52_U2D_PHYDATA_3,
- GPIO53_U2D_PHYDATA_4,
- GPIO54_U2D_PHYDATA_5,
- GPIO55_U2D_PHYDATA_6,
- GPIO56_U2D_PHYDATA_7,
- GPIO58_UTM_RXVALID,
- GPIO59_UTM_RXACTIVE,
- GPIO60_U2D_RXERROR,
- GPIO61_U2D_OPMODE0,
- GPIO62_U2D_OPMODE1,
- GPIO71_GPIO, /* USBD_INT */
- GPIO73_UTM_TXREADY,
- GPIO83_U2D_TXVALID,
- GPIO98_U2D_RESET,
- GPIO99_U2D_XCVR_SEL,
- GPIO100_U2D_TERM_SEL,
- GPIO101_U2D_SUSPEND,
- GPIO102_UTM_LINESTATE_0,
- GPIO103_UTM_LINESTATE_1,
- GPIO4_2_GPIO | MFP_PULL_HIGH, /* UTM_PULLUP */
-
- /* DM9000 */
- GPIO1_GPIO,
- GPIO9_GPIO,
- GPIO36_GPIO,
-
- /* AC97 */
- GPIO35_AC97_SDATA_IN_0,
- GPIO37_AC97_SDATA_OUT,
- GPIO38_AC97_SYNC,
- GPIO39_AC97_BITCLK,
- GPIO40_AC97_nACRESET,
-
- /* UARTS */
- GPIO41_UART1_RXD,
- GPIO42_UART1_TXD,
- GPIO43_UART1_CTS,
- GPIO44_UART1_DCD,
- GPIO45_UART1_DSR,
- GPIO46_UART1_RI,
- GPIO47_UART1_DTR,
- GPIO48_UART1_RTS,
-
- GPIO109_UART2_RTS,
- GPIO110_UART2_RXD,
- GPIO111_UART2_TXD,
- GPIO112_UART2_CTS,
-
- GPIO105_UART3_CTS,
- GPIO106_UART3_RTS,
- GPIO107_UART3_TXD,
- GPIO108_UART3_RXD,
-
- GPIO78_GPIO,
- GPIO79_GPIO,
- GPIO80_GPIO,
- GPIO81_GPIO,
-
- /* I2C */
- GPIO32_I2C_SCL,
- GPIO33_I2C_SDA,
-
- /* MMC */
- GPIO18_MMC1_DAT0,
- GPIO19_MMC1_DAT1,
- GPIO20_MMC1_DAT2,
- GPIO21_MMC1_DAT3,
- GPIO22_MMC1_CLK,
- GPIO23_MMC1_CMD,
- GPIO72_GPIO | MFP_PULL_HIGH, /* Card Detect */
- GPIO84_GPIO | MFP_PULL_LOW, /* Write Protect */
-
- /* IRQ */
- GPIO74_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ1 */
- GPIO75_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ2 */
- GPIO76_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ3 */
- GPIO77_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ4 */
- GPIO78_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ5 */
- GPIO79_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ6 */
- GPIO80_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ7 */
- GPIO81_GPIO | MFP_LPM_EDGE_RISE /* EXT_IRQ8 */
-};
-
-/* MMC/MCI Support */
-#if defined(CONFIG_MMC)
-static struct pxamci_platform_data mxm_8x10_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 10,
-};
-
-static struct gpiod_lookup_table mxm_8x10_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on GPIO 72 */
- GPIO_LOOKUP("gpio-pxa", MXM_8X10_SD_nCD,
- "cd", GPIO_ACTIVE_LOW),
- /* Write protect on GPIO 84 */
- GPIO_LOOKUP("gpio-pxa", MXM_8X10_SD_WP,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-void __init mxm_8x10_mmc_init(void)
-{
- gpiod_add_lookup_table(&mxm_8x10_mci_gpio_table);
- pxa_set_mci_info(&mxm_8x10_mci_platform_data);
-}
-#endif
-
-/* USB Open Host Controller Interface */
-static struct pxaohci_platform_data mxm_8x10_ohci_platform_data = {
- .port_mode = PMM_NPS_MODE,
- .flags = ENABLE_PORT_ALL
-};
-
-void __init mxm_8x10_usb_host_init(void)
-{
- pxa_set_ohci_info(&mxm_8x10_ohci_platform_data);
-}
-
-/* AC97 Sound Support */
-static struct platform_device mxm_8x10_ac97_device = {
- .name = "pxa2xx-ac97"
-};
-
-void __init mxm_8x10_ac97_init(void)
-{
- platform_device_register(&mxm_8x10_ac97_device);
-}
-
-/* NAND flash Support */
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
-#define NAND_BLOCK_SIZE SZ_128K
-#define NB(x) (NAND_BLOCK_SIZE * (x))
-static struct mtd_partition mxm_8x10_nand_partitions[] = {
- [0] = {
- .name = "boot",
- .size = NB(0x002),
- .offset = NB(0x000),
- .mask_flags = MTD_WRITEABLE
- },
- [1] = {
- .name = "kernel",
- .size = NB(0x010),
- .offset = NB(0x002),
- .mask_flags = MTD_WRITEABLE
- },
- [2] = {
- .name = "root",
- .size = NB(0x36c),
- .offset = NB(0x012)
- },
- [3] = {
- .name = "bbt",
- .size = NB(0x082),
- .offset = NB(0x37e),
- .mask_flags = MTD_WRITEABLE
- }
-};
-
-static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = {
- .keep_config = 1,
- .parts = mxm_8x10_nand_partitions,
- .nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions)
-};
-
-static void __init mxm_8x10_nand_init(void)
-{
- pxa3xx_set_nand_info(&mxm_8x10_nand_info);
-}
-#else
-static inline void mxm_8x10_nand_init(void) {}
-#endif /* IS_ENABLED(CONFIG_MTD_NAND_MARVELL) */
-
-/* Ethernet support: Davicom DM9000 */
-static struct resource dm9k_resources[] = {
- [0] = {
- .start = MXM_8X10_ETH_PHYS + 0x300,
- .end = MXM_8X10_ETH_PHYS + 0x300,
- .flags = IORESOURCE_MEM
- },
- [1] = {
- .start = MXM_8X10_ETH_PHYS + 0x308,
- .end = MXM_8X10_ETH_PHYS + 0x308,
- .flags = IORESOURCE_MEM
- },
- [2] = {
- .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)),
- .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-static struct dm9000_plat_data dm9k_plat_data = {
- .flags = DM9000_PLATF_16BITONLY
-};
-
-static struct platform_device dm9k_device = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9k_resources),
- .resource = dm9k_resources,
- .dev = {
- .platform_data = &dm9k_plat_data
- }
-};
-
-static void __init mxm_8x10_ethernet_init(void)
-{
- platform_device_register(&dm9k_device);
-}
-
-/* PXA UARTs */
-static void __init mxm_8x10_uarts_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-}
-
-/* I2C and Real Time Clock */
-static struct i2c_board_info __initdata mxm_8x10_i2c_devices[] = {
- {
- I2C_BOARD_INFO("ds1337", 0x68)
- }
-};
-
-static void __init mxm_8x10_i2c_init(void)
-{
- i2c_register_board_info(0, mxm_8x10_i2c_devices,
- ARRAY_SIZE(mxm_8x10_i2c_devices));
- pxa_set_i2c_info(NULL);
-}
-
-void __init mxm_8x10_barebones_init(void)
-{
- pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg));
-
- mxm_8x10_uarts_init();
- mxm_8x10_nand_init();
- mxm_8x10_i2c_init();
- mxm_8x10_ethernet_init();
-}
diff --git a/arch/arm/mach-pxa/mxm8x10.h b/arch/arm/mach-pxa/mxm8x10.h
deleted file mode 100644
index dcd32321c995..000000000000
--- a/arch/arm/mach-pxa/mxm8x10.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_MXM_8X10_H
-#define __MACH_MXM_8X10_H
-
-#define MXM_8X10_ETH_PHYS 0x13000000
-
-#if defined(CONFIG_MMC)
-
-#define MXM_8X10_SD_nCD (72)
-#define MXM_8X10_SD_WP (84)
-
-extern void mxm_8x10_mmc_init(void);
-#else
-static inline void mxm_8x10_mmc_init(void) {}
-#endif
-
-extern void mxm_8x10_usb_host_init(void);
-extern void mxm_8x10_ac97_init(void);
-
-extern void mxm_8x10_barebones_init(void);
-
-#endif /* __MACH_MXM_8X10_H */
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
deleted file mode 100644
index 6230381a7ca0..000000000000
--- a/arch/arm/mach-pxa/palm27x.c
+++ /dev/null
@@ -1,473 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Common code for Palm LD, T5, TX, Z72
- *
- * Copyright (C) 2010-2011 Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/pda_power.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/wm97xx.h>
-#include <linux/power_supply.h>
-#include <linux/regulator/max1586.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa27x.h"
-#include <mach/audio.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include "udc.h"
-#include <linux/platform_data/asoc-palm27x.h>
-#include "palm27x.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data palm27x_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 200,
-};
-
-void __init palm27x_mmc_init(struct gpiod_lookup_table *gtable)
-{
- if (gtable)
- gpiod_add_lookup_table(gtable);
- pxa_set_mci_info(&palm27x_mci_platform_data);
-}
-#endif
-
-/******************************************************************************
- * Power management - standby
- ******************************************************************************/
-#if defined(CONFIG_SUSPEND)
-void __init palm27x_pm_init(unsigned long str_base)
-{
- static const unsigned long resume[] = {
- 0xe3a00101, /* mov r0, #0x40000000 */
- 0xe380060f, /* orr r0, r0, #0x00f00000 */
- 0xe590f008, /* ldr pc, [r0, #0x08] */
- };
-
- /*
- * Copy the bootloader.
- * NOTE: PalmZ72 uses a different wakeup method!
- */
- memcpy(phys_to_virt(str_base), resume, sizeof(resume));
-}
-#endif
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-struct pxafb_mode_info palm_320x480_lcd_mode = {
- .pixclock = 57692,
- .xres = 320,
- .yres = 480,
- .bpp = 16,
-
- .left_margin = 32,
- .right_margin = 1,
- .upper_margin = 7,
- .lower_margin = 1,
-
- .hsync_len = 4,
- .vsync_len = 1,
-};
-
-struct pxafb_mode_info palm_320x320_lcd_mode = {
- .pixclock = 115384,
- .xres = 320,
- .yres = 320,
- .bpp = 16,
-
- .left_margin = 27,
- .right_margin = 7,
- .upper_margin = 7,
- .lower_margin = 8,
-
- .hsync_len = 6,
- .vsync_len = 1,
-};
-
-struct pxafb_mode_info palm_320x320_new_lcd_mode = {
- .pixclock = 86538,
- .xres = 320,
- .yres = 320,
- .bpp = 16,
-
- .left_margin = 20,
- .right_margin = 8,
- .upper_margin = 8,
- .lower_margin = 5,
-
- .hsync_len = 4,
- .vsync_len = 1,
-};
-
-static struct pxafb_mach_info palm27x_lcd_screen = {
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static int palm27x_lcd_power;
-static void palm27x_lcd_ctl(int on, struct fb_var_screeninfo *info)
-{
- gpio_set_value(palm27x_lcd_power, on);
-}
-
-void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode)
-{
- palm27x_lcd_screen.modes = mode;
-
- if (gpio_is_valid(power)) {
- if (!gpio_request(power, "LCD power")) {
- pr_err("Palm27x: failed to claim lcd power gpio!\n");
- return;
- }
- if (!gpio_direction_output(power, 1)) {
- pr_err("Palm27x: lcd power configuration failed!\n");
- return;
- }
- palm27x_lcd_power = power;
- palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl;
- }
-
- pxa_set_fb_info(NULL, &palm27x_lcd_screen);
-}
-#endif
-
-/******************************************************************************
- * USB Gadget
- ******************************************************************************/
-#if defined(CONFIG_USB_PXA27X) || \
- defined(CONFIG_USB_PXA27X_MODULE)
-
-/* The actual GPIO offsets get filled in in the palm27x_udc_init() call */
-static struct gpiod_lookup_table palm27x_udc_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", 0,
- "vbus", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", 0,
- "pullup", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device palm27x_gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-void __init palm27x_udc_init(int vbus, int pullup, int vbus_inverted)
-{
- palm27x_udc_gpiod_table.table[0].chip_hwnum = vbus;
- palm27x_udc_gpiod_table.table[1].chip_hwnum = pullup;
- if (vbus_inverted)
- palm27x_udc_gpiod_table.table[0].flags = GPIO_ACTIVE_LOW;
-
- gpiod_add_lookup_table(&palm27x_udc_gpiod_table);
- platform_device_register(&palm27x_gpio_vbus);
-}
-#endif
-
-/******************************************************************************
- * IrDA
- ******************************************************************************/
-#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE)
-static struct pxaficp_platform_data palm27x_ficp_platform_data = {
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-void __init palm27x_irda_init(int pwdn)
-{
- palm27x_ficp_platform_data.gpio_pwdown = pwdn;
- pxa_set_ficp_info(&palm27x_ficp_platform_data);
-}
-#endif
-
-/******************************************************************************
- * WM97xx audio, battery
- ******************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \
- defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE)
-static struct wm97xx_batt_pdata palm27x_batt_pdata = {
- .batt_aux = WM97XX_AUX_ID3,
- .temp_aux = WM97XX_AUX_ID2,
- .batt_mult = 1000,
- .batt_div = 414,
- .temp_mult = 1,
- .temp_div = 1,
- .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO,
- .batt_name = "main-batt",
-};
-
-static struct wm97xx_pdata palm27x_wm97xx_pdata = {
- .batt_pdata = &palm27x_batt_pdata,
-};
-
-static pxa2xx_audio_ops_t palm27x_ac97_pdata = {
- .codec_pdata = { &palm27x_wm97xx_pdata, },
-};
-
-static struct palm27x_asoc_info palm27x_asoc_pdata = {
- .jack_gpio = -1,
-};
-
-static struct platform_device palm27x_asoc = {
- .name = "palm27x-asoc",
- .id = -1,
- .dev = {
- .platform_data = &palm27x_asoc_pdata,
- },
-};
-
-void __init palm27x_ac97_init(int minv, int maxv, int jack, int reset)
-{
- palm27x_ac97_pdata.reset_gpio = reset;
- palm27x_asoc_pdata.jack_gpio = jack;
-
- if (minv < 0 || maxv < 0) {
- palm27x_ac97_pdata.codec_pdata[0] = NULL;
- pxa_set_ac97_info(&palm27x_ac97_pdata);
- } else {
- palm27x_batt_pdata.min_voltage = minv,
- palm27x_batt_pdata.max_voltage = maxv,
-
- pxa_set_ac97_info(&palm27x_ac97_pdata);
- platform_device_register(&palm27x_asoc);
- }
-}
-#endif
-
-/******************************************************************************
- * Backlight
- ******************************************************************************/
-#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
-static struct pwm_lookup palm27x_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 3500 * 1024,
- PWM_POLARITY_NORMAL),
-};
-
-static int palm_bl_power;
-static int palm_lcd_power;
-
-static int palm27x_backlight_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(palm_bl_power, "BL POWER");
- if (ret)
- goto err;
- ret = gpio_direction_output(palm_bl_power, 0);
- if (ret)
- goto err2;
-
- if (gpio_is_valid(palm_lcd_power)) {
- ret = gpio_request(palm_lcd_power, "LCD POWER");
- if (ret)
- goto err2;
- ret = gpio_direction_output(palm_lcd_power, 0);
- if (ret)
- goto err3;
- }
-
- return 0;
-err3:
- gpio_free(palm_lcd_power);
-err2:
- gpio_free(palm_bl_power);
-err:
- return ret;
-}
-
-static int palm27x_backlight_notify(struct device *dev, int brightness)
-{
- gpio_set_value(palm_bl_power, brightness);
- if (gpio_is_valid(palm_lcd_power))
- gpio_set_value(palm_lcd_power, brightness);
- return brightness;
-}
-
-static void palm27x_backlight_exit(struct device *dev)
-{
- gpio_free(palm_bl_power);
- if (gpio_is_valid(palm_lcd_power))
- gpio_free(palm_lcd_power);
-}
-
-static struct platform_pwm_backlight_data palm27x_backlight_data = {
- .max_brightness = 0xfe,
- .dft_brightness = 0x7e,
- .init = palm27x_backlight_init,
- .notify = palm27x_backlight_notify,
- .exit = palm27x_backlight_exit,
-};
-
-static struct platform_device palm27x_backlight = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &palm27x_backlight_data,
- },
-};
-
-void __init palm27x_pwm_init(int bl, int lcd)
-{
- palm_bl_power = bl;
- palm_lcd_power = lcd;
- pwm_add_table(palm27x_pwm_lookup, ARRAY_SIZE(palm27x_pwm_lookup));
- platform_device_register(&palm27x_backlight);
-}
-#endif
-
-/******************************************************************************
- * Power supply
- ******************************************************************************/
-#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE)
-static int palm_ac_state;
-static int palm_usb_state;
-
-static int palm27x_power_supply_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(palm_ac_state, "AC state");
- if (ret)
- goto err1;
- ret = gpio_direction_input(palm_ac_state);
- if (ret)
- goto err2;
-
- if (gpio_is_valid(palm_usb_state)) {
- ret = gpio_request(palm_usb_state, "USB state");
- if (ret)
- goto err2;
- ret = gpio_direction_input(palm_usb_state);
- if (ret)
- goto err3;
- }
-
- return 0;
-err3:
- gpio_free(palm_usb_state);
-err2:
- gpio_free(palm_ac_state);
-err1:
- return ret;
-}
-
-static void palm27x_power_supply_exit(struct device *dev)
-{
- gpio_free(palm_usb_state);
- gpio_free(palm_ac_state);
-}
-
-static int palm27x_is_ac_online(void)
-{
- return gpio_get_value(palm_ac_state);
-}
-
-static int palm27x_is_usb_online(void)
-{
- return !gpio_get_value(palm_usb_state);
-}
-static char *palm27x_supplicants[] = {
- "main-battery",
-};
-
-static struct pda_power_pdata palm27x_ps_info = {
- .init = palm27x_power_supply_init,
- .exit = palm27x_power_supply_exit,
- .is_ac_online = palm27x_is_ac_online,
- .is_usb_online = palm27x_is_usb_online,
- .supplied_to = palm27x_supplicants,
- .num_supplicants = ARRAY_SIZE(palm27x_supplicants),
-};
-
-static struct platform_device palm27x_power_supply = {
- .name = "pda-power",
- .id = -1,
- .dev = {
- .platform_data = &palm27x_ps_info,
- },
-};
-
-void __init palm27x_power_init(int ac, int usb)
-{
- palm_ac_state = ac;
- palm_usb_state = usb;
- platform_device_register(&palm27x_power_supply);
-}
-#endif
-
-/******************************************************************************
- * Core power regulator
- ******************************************************************************/
-#if defined(CONFIG_REGULATOR_MAX1586) || \
- defined(CONFIG_REGULATOR_MAX1586_MODULE)
-static struct regulator_consumer_supply palm27x_max1587a_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data palm27x_max1587a_v3_info = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 900000,
- .max_uV = 1705000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .consumer_supplies = palm27x_max1587a_consumers,
- .num_consumer_supplies = ARRAY_SIZE(palm27x_max1587a_consumers),
-};
-
-static struct max1586_subdev_data palm27x_max1587a_subdevs[] = {
- {
- .name = "vcc_core",
- .id = MAX1586_V3,
- .platform_data = &palm27x_max1587a_v3_info,
- }
-};
-
-static struct max1586_platform_data palm27x_max1587a_info = {
- .subdevs = palm27x_max1587a_subdevs,
- .num_subdevs = ARRAY_SIZE(palm27x_max1587a_subdevs),
- .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
-};
-
-static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = {
- {
- I2C_BOARD_INFO("max1586", 0x14),
- .platform_data = &palm27x_max1587a_info,
- },
-};
-
-static struct i2c_pxa_platform_data palm27x_i2c_power_info = {
- .use_pio = 1,
-};
-
-void __init palm27x_pmic_init(void)
-{
- i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info));
- pxa27x_set_i2c_power_info(&palm27x_i2c_power_info);
-}
-#endif
diff --git a/arch/arm/mach-pxa/palm27x.h b/arch/arm/mach-pxa/palm27x.h
deleted file mode 100644
index bd3075bbb3aa..000000000000
--- a/arch/arm/mach-pxa/palm27x.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Common functions for Palm LD, T5, TX, Z72
- *
- * Copyright (C) 2010
- * Marek Vasut <marek.vasut@gmail.com>
- */
-#ifndef __INCLUDE_MACH_PALM27X__
-#define __INCLUDE_MACH_PALM27X__
-
-#include <linux/gpio/machine.h>
-
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-extern void __init palm27x_mmc_init(struct gpiod_lookup_table *gtable);
-#else
-static inline void palm27x_mmc_init(struct gpiod_lookup_table *gtable)
-{}
-#endif
-
-#if defined(CONFIG_SUSPEND)
-extern void __init palm27x_pm_init(unsigned long str_base);
-#else
-static inline void palm27x_pm_init(unsigned long str_base) {}
-#endif
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-extern struct pxafb_mode_info palm_320x480_lcd_mode;
-extern struct pxafb_mode_info palm_320x320_lcd_mode;
-extern struct pxafb_mode_info palm_320x320_new_lcd_mode;
-extern void __init palm27x_lcd_init(int power,
- struct pxafb_mode_info *mode);
-#else
-#define palm27x_lcd_init(power, mode) do {} while (0)
-#endif
-
-#if defined(CONFIG_USB_PXA27X) || \
- defined(CONFIG_USB_PXA27X_MODULE)
-extern void __init palm27x_udc_init(int vbus, int pullup,
- int vbus_inverted);
-#else
-static inline void palm27x_udc_init(int vbus, int pullup, int vbus_inverted) {}
-#endif
-
-#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE)
-extern void __init palm27x_irda_init(int pwdn);
-#else
-static inline void palm27x_irda_init(int pwdn) {}
-#endif
-
-#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \
- defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE)
-extern void __init palm27x_ac97_init(int minv, int maxv, int jack,
- int reset);
-#else
-static inline void palm27x_ac97_init(int minv, int maxv, int jack, int reset) {}
-#endif
-
-#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
-extern void __init palm27x_pwm_init(int bl, int lcd);
-#else
-static inline void palm27x_pwm_init(int bl, int lcd) {}
-#endif
-
-#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE)
-extern void __init palm27x_power_init(int ac, int usb);
-#else
-static inline void palm27x_power_init(int ac, int usb) {}
-#endif
-
-#if defined(CONFIG_REGULATOR_MAX1586) || \
- defined(CONFIG_REGULATOR_MAX1586_MODULE)
-extern void __init palm27x_pmic_init(void);
-#else
-static inline void palm27x_pmic_init(void) {}
-#endif
-
-#endif /* __INCLUDE_MACH_PALM27X__ */
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
deleted file mode 100644
index 5f73716a77f0..000000000000
--- a/arch/arm/mach-pxa/palmld.c
+++ /dev/null
@@ -1,377 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware definitions for Palm LifeDrive
- *
- * Author: Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on work of:
- * Alex Osborne <ato@meshy.org>
- *
- * (find more info at www.hackndev.com)
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/pda_power.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio.h>
-#include <linux/wm97xx.h>
-#include <linux/power_supply.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa27x.h"
-#include <mach/audio.h>
-#include <mach/palmld.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/platform_data/asoc-palm27x.h>
-#include "palm27x.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long palmld_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO14_GPIO, /* SD detect */
- GPIO114_GPIO, /* SD power */
- GPIO116_GPIO, /* SD r/o switch */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO89_AC97_SYSCLK,
- GPIO95_AC97_nRESET,
-
- /* IrDA */
- GPIO108_GPIO, /* ir disable */
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-
- /* MATRIX KEYPAD */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* PWM */
- GPIO16_PWM0_OUT,
-
- /* GPIO KEYS */
- GPIO10_GPIO, /* hotsync button */
- GPIO12_GPIO, /* power switch */
- GPIO15_GPIO, /* lock switch */
-
- /* LEDs */
- GPIO52_GPIO, /* green led */
- GPIO94_GPIO, /* orange led */
-
- /* PCMCIA */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO79_PSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
- GPIO36_GPIO, /* wifi power */
- GPIO38_GPIO, /* wifi ready */
- GPIO81_GPIO, /* wifi reset */
-
- /* FFUART */
- GPIO34_FFUART_RXD,
- GPIO39_FFUART_TXD,
-
- /* HDD */
- GPIO98_GPIO, /* HDD reset */
- GPIO115_GPIO, /* HDD power */
-
- /* MISC */
- GPIO13_GPIO, /* earphone detect */
-};
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition palmld_partitions[] = {
- {
- .name = "Flash",
- .offset = 0x00000000,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data palmld_flash_data[] = {
- {
- .width = 2, /* bankwidth in bytes */
- .parts = palmld_partitions,
- .nr_parts = ARRAY_SIZE(palmld_partitions)
- }
-};
-
-static struct resource palmld_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_4M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device palmld_flash = {
- .name = "physmap-flash",
- .id = 0,
- .resource = &palmld_flash_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = palmld_flash_data,
- },
-};
-
-static void __init palmld_nor_init(void)
-{
- platform_device_register(&palmld_flash);
-}
-#else
-static inline void palmld_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keyboard
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int palmld_matrix_keys[] = {
- KEY(0, 1, KEY_F2),
- KEY(0, 2, KEY_UP),
-
- KEY(1, 0, KEY_F3),
- KEY(1, 1, KEY_F4),
- KEY(1, 2, KEY_RIGHT),
-
- KEY(2, 0, KEY_F1),
- KEY(2, 1, KEY_F5),
- KEY(2, 2, KEY_DOWN),
-
- KEY(3, 0, KEY_F6),
- KEY(3, 1, KEY_ENTER),
- KEY(3, 2, KEY_LEFT),
-};
-
-static struct matrix_keymap_data palmld_matrix_keymap_data = {
- .keymap = palmld_matrix_keys,
- .keymap_size = ARRAY_SIZE(palmld_matrix_keys),
-};
-
-static struct pxa27x_keypad_platform_data palmld_keypad_platform_data = {
- .matrix_key_rows = 4,
- .matrix_key_cols = 3,
- .matrix_keymap_data = &palmld_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-
-static void __init palmld_kpc_init(void)
-{
- pxa_set_keypad_info(&palmld_keypad_platform_data);
-}
-#else
-static inline void palmld_kpc_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button palmld_pxa_buttons[] = {
- {KEY_F8, GPIO_NR_PALMLD_HOTSYNC_BUTTON_N, 1, "HotSync Button" },
- {KEY_F9, GPIO_NR_PALMLD_LOCK_SWITCH, 0, "Lock Switch" },
- {KEY_POWER, GPIO_NR_PALMLD_POWER_SWITCH, 0, "Power Switch" },
-};
-
-static struct gpio_keys_platform_data palmld_pxa_keys_data = {
- .buttons = palmld_pxa_buttons,
- .nbuttons = ARRAY_SIZE(palmld_pxa_buttons),
-};
-
-static struct platform_device palmld_pxa_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &palmld_pxa_keys_data,
- },
-};
-
-static void __init palmld_keys_init(void)
-{
- platform_device_register(&palmld_pxa_keys);
-}
-#else
-static inline void palmld_keys_init(void) {}
-#endif
-
-/******************************************************************************
- * LEDs
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-struct gpio_led gpio_leds[] = {
-{
- .name = "palmld:green:led",
- .default_trigger = "none",
- .gpio = GPIO_NR_PALMLD_LED_GREEN,
-}, {
- .name = "palmld:amber:led",
- .default_trigger = "none",
- .gpio = GPIO_NR_PALMLD_LED_AMBER,
-},
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device palmld_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &gpio_led_info,
- }
-};
-
-static void __init palmld_leds_init(void)
-{
- platform_device_register(&palmld_leds);
-}
-#else
-static inline void palmld_leds_init(void) {}
-#endif
-
-/******************************************************************************
- * HDD
- ******************************************************************************/
-#if defined(CONFIG_PATA_PALMLD) || defined(CONFIG_PATA_PALMLD_MODULE)
-static struct platform_device palmld_ide_device = {
- .name = "pata_palmld",
- .id = -1,
-};
-
-static struct gpiod_lookup_table palmld_ide_gpio_table = {
- .dev_id = "pata_palmld",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMLD_IDE_PWEN,
- "power", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMLD_IDE_RESET,
- "reset", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init palmld_ide_init(void)
-{
- gpiod_add_lookup_table(&palmld_ide_gpio_table);
- platform_device_register(&palmld_ide_device);
-}
-#else
-static inline void palmld_ide_init(void) {}
-#endif
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static struct map_desc palmld_io_desc[] __initdata = {
-{
- .virtual = PALMLD_IDE_VIRT,
- .pfn = __phys_to_pfn(PALMLD_IDE_PHYS),
- .length = PALMLD_IDE_SIZE,
- .type = MT_DEVICE
-},
-{
- .virtual = PALMLD_USB_VIRT,
- .pfn = __phys_to_pfn(PALMLD_USB_PHYS),
- .length = PALMLD_USB_SIZE,
- .type = MT_DEVICE
-},
-};
-
-static void __init palmld_map_io(void)
-{
- pxa27x_map_io();
- iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc));
-}
-
-static struct gpiod_lookup_table palmld_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMLD_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMLD_SD_READONLY,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMLD_SD_POWER,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static void __init palmld_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- palm27x_mmc_init(&palmld_mci_gpio_table);
- palm27x_pm_init(PALMLD_STR_BASE);
- palm27x_lcd_init(-1, &palm_320x480_lcd_mode);
- palm27x_irda_init(GPIO_NR_PALMLD_IR_DISABLE);
- palm27x_ac97_init(PALMLD_BAT_MIN_VOLTAGE, PALMLD_BAT_MAX_VOLTAGE,
- GPIO_NR_PALMLD_EARPHONE_DETECT, 95);
- palm27x_pwm_init(GPIO_NR_PALMLD_BL_POWER, GPIO_NR_PALMLD_LCD_POWER);
- palm27x_power_init(GPIO_NR_PALMLD_POWER_DETECT,
- GPIO_NR_PALMLD_USB_DETECT_N);
- palm27x_pmic_init();
- palmld_kpc_init();
- palmld_keys_init();
- palmld_nor_init();
- palmld_leds_init();
- palmld_ide_init();
-}
-
-MACHINE_START(PALMLD, "Palm LifeDrive")
- .atag_offset = 0x100,
- .map_io = palmld_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = palmld_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
deleted file mode 100644
index 7c7cbb4e677e..000000000000
--- a/arch/arm/mach-pxa/palmt5.c
+++ /dev/null
@@ -1,225 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware definitions for Palm Tungsten|T5
- *
- * Author: Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on work of:
- * Ales Snuparek <snuparek@atlas.cz>
- * Justin Kendrick <twilightsentry@gmail.com>
- * RichardT5 <richard_t5@users.sourceforge.net>
- *
- * (find more info at www.hackndev.com)
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/memblock.h>
-#include <linux/pda_power.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio.h>
-#include <linux/wm97xx.h>
-#include <linux/power_supply.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa27x.h"
-#include <mach/audio.h>
-#include "palmt5.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include "udc.h"
-#include <linux/platform_data/asoc-palm27x.h>
-#include "palm27x.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long palmt5_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO14_GPIO, /* SD detect */
- GPIO114_GPIO, /* SD power */
- GPIO115_GPIO, /* SD r/o switch */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO89_AC97_SYSCLK,
- GPIO95_AC97_nRESET,
-
- /* IrDA */
- GPIO40_GPIO, /* ir disable */
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-
- /* USB */
- GPIO15_GPIO, /* usb detect */
- GPIO93_GPIO, /* usb power */
-
- /* MATRIX KEYPAD */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* PWM */
- GPIO16_PWM0_OUT,
-
- /* FFUART */
- GPIO34_FFUART_RXD,
- GPIO39_FFUART_TXD,
-
- /* MISC */
- GPIO10_GPIO, /* hotsync button */
- GPIO90_GPIO, /* power detect */
- GPIO107_GPIO, /* earphone detect */
-};
-
-/******************************************************************************
- * GPIO keyboard
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int palmt5_matrix_keys[] = {
- KEY(0, 0, KEY_POWER),
- KEY(0, 1, KEY_F1),
- KEY(0, 2, KEY_ENTER),
-
- KEY(1, 0, KEY_F2),
- KEY(1, 1, KEY_F3),
- KEY(1, 2, KEY_F4),
-
- KEY(2, 0, KEY_UP),
- KEY(2, 2, KEY_DOWN),
-
- KEY(3, 0, KEY_RIGHT),
- KEY(3, 2, KEY_LEFT),
-};
-
-static struct matrix_keymap_data palmt5_matrix_keymap_data = {
- .keymap = palmt5_matrix_keys,
- .keymap_size = ARRAY_SIZE(palmt5_matrix_keys),
-};
-
-static struct pxa27x_keypad_platform_data palmt5_keypad_platform_data = {
- .matrix_key_rows = 4,
- .matrix_key_cols = 3,
- .matrix_keymap_data = &palmt5_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-
-static void __init palmt5_kpc_init(void)
-{
- pxa_set_keypad_info(&palmt5_keypad_platform_data);
-}
-#else
-static inline void palmt5_kpc_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button palmt5_pxa_buttons[] = {
- {KEY_F8, GPIO_NR_PALMT5_HOTSYNC_BUTTON_N, 1, "HotSync Button" },
-};
-
-static struct gpio_keys_platform_data palmt5_pxa_keys_data = {
- .buttons = palmt5_pxa_buttons,
- .nbuttons = ARRAY_SIZE(palmt5_pxa_buttons),
-};
-
-static struct platform_device palmt5_pxa_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &palmt5_pxa_keys_data,
- },
-};
-
-static void __init palmt5_keys_init(void)
-{
- platform_device_register(&palmt5_pxa_keys);
-}
-#else
-static inline void palmt5_keys_init(void) {}
-#endif
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void __init palmt5_reserve(void)
-{
- memblock_reserve(0xa0200000, 0x1000);
-}
-
-static struct gpiod_lookup_table palmt5_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMT5_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMT5_SD_READONLY,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMT5_SD_POWER,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static void __init palmt5_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- palm27x_mmc_init(&palmt5_mci_gpio_table);
- palm27x_pm_init(PALMT5_STR_BASE);
- palm27x_lcd_init(-1, &palm_320x480_lcd_mode);
- palm27x_udc_init(GPIO_NR_PALMT5_USB_DETECT_N,
- GPIO_NR_PALMT5_USB_PULLUP, 1);
- palm27x_irda_init(GPIO_NR_PALMT5_IR_DISABLE);
- palm27x_ac97_init(PALMT5_BAT_MIN_VOLTAGE, PALMT5_BAT_MAX_VOLTAGE,
- GPIO_NR_PALMT5_EARPHONE_DETECT, 95);
- palm27x_pwm_init(GPIO_NR_PALMT5_BL_POWER, GPIO_NR_PALMT5_LCD_POWER);
- palm27x_power_init(GPIO_NR_PALMT5_POWER_DETECT, -1);
- palm27x_pmic_init();
- palmt5_kpc_init();
- palmt5_keys_init();
-}
-
-MACHINE_START(PALMT5, "Palm Tungsten|T5")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .reserve = palmt5_reserve,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = palmt5_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/palmt5.h b/arch/arm/mach-pxa/palmt5.h
deleted file mode 100644
index 1fb1da7c8da3..000000000000
--- a/arch/arm/mach-pxa/palmt5.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer
- *
- * Authors: Ales Snuparek <snuparek@atlas.cz>
- * Marek Vasut <marek.vasut@gmail.com>
- * Justin Kendrick <twilightsentry@gmail.com>
- * RichardT5 <richard_t5@users.sourceforge.net>
- */
-
-#ifndef _INCLUDE_PALMT5_H_
-#define _INCLUDE_PALMT5_H_
-
-#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
-
-/** HERE ARE GPIOs **/
-
-/* GPIOs */
-#define GPIO_NR_PALMT5_GPIO_RESET 1
-
-#define GPIO_NR_PALMT5_POWER_DETECT 90
-#define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N 10
-#define GPIO_NR_PALMT5_EARPHONE_DETECT 107
-
-/* SD/MMC */
-#define GPIO_NR_PALMT5_SD_DETECT_N 14
-#define GPIO_NR_PALMT5_SD_POWER 114
-#define GPIO_NR_PALMT5_SD_READONLY 115
-
-/* TOUCHSCREEN */
-#define GPIO_NR_PALMT5_WM9712_IRQ 27
-
-/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
-#define GPIO_NR_PALMT5_IR_DISABLE 40
-
-/* USB */
-#define GPIO_NR_PALMT5_USB_DETECT_N 15
-#define GPIO_NR_PALMT5_USB_PULLUP 93
-
-/* LCD/BACKLIGHT */
-#define GPIO_NR_PALMT5_BL_POWER 84
-#define GPIO_NR_PALMT5_LCD_POWER 96
-
-/* BLUETOOTH */
-#define GPIO_NR_PALMT5_BT_POWER 17
-#define GPIO_NR_PALMT5_BT_RESET 83
-
-/* INTERRUPTS */
-#define IRQ_GPIO_PALMT5_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N)
-#define IRQ_GPIO_PALMT5_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ)
-#define IRQ_GPIO_PALMT5_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT)
-#define IRQ_GPIO_PALMT5_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET)
-
-/** HERE ARE INIT VALUES **/
-
-/* Various addresses */
-#define PALMT5_PHYS_RAM_START 0xa0000000
-#define PALMT5_PHYS_IO_START 0x40000000
-#define PALMT5_STR_BASE 0xa0200000
-
-/* TOUCHSCREEN */
-#define AC97_LINK_FRAME 21
-
-/* BATTERY */
-#define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
-#define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMT5_BAT_MAX_CURRENT 0 /* unknown */
-#define PALMT5_BAT_MIN_CURRENT 0 /* unknown */
-#define PALMT5_BAT_MAX_CHARGE 1 /* unknown */
-#define PALMT5_BAT_MIN_CHARGE 1 /* unknown */
-#define PALMT5_MAX_LIFE_MINS 360 /* on-life in minutes */
-
-#define PALMT5_BAT_MEASURE_DELAY (HZ * 1)
-
-/* BACKLIGHT */
-#define PALMT5_MAX_INTENSITY 0xFE
-#define PALMT5_DEFAULT_INTENSITY 0x7E
-#define PALMT5_LIMIT_MASK 0x7F
-#define PALMT5_PRESCALER 0x3F
-#define PALMT5_PERIOD_NS 3500
-
-#endif
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
deleted file mode 100644
index 455cb8ccaf26..000000000000
--- a/arch/arm/mach-pxa/palmtc.c
+++ /dev/null
@@ -1,539 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/palmtc.c
- *
- * Support for the Palm Tungsten|C
- *
- * Author: Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on work of:
- * Petr Blaha <p3t3@centrum.cz>
- * Chetan S. Kumar <shivakumar.chetan@gmail.com>
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/input.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio/machine.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/ucb1400.h>
-#include <linux/power_supply.h>
-#include <linux/gpio_keys.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa25x.h"
-#include <mach/audio.h>
-#include <mach/palmtc.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include "udc.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long palmtc_pin_config[] __initdata = {
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO8_MMC_CS0,
- GPIO12_GPIO, /* detect */
- GPIO32_GPIO, /* power */
- GPIO54_GPIO, /* r/o switch */
-
- /* PCMCIA */
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO49_nPWE,
- GPIO48_nPOE,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO57_nIOIS16,
- GPIO56_nPWAIT,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* IrDA */
- GPIO45_GPIO, /* ir disable */
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-
- /* PWM */
- GPIO17_PWM1_OUT,
-
- /* USB */
- GPIO4_GPIO, /* detect */
- GPIO36_GPIO, /* pullup */
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* MATRIX KEYPAD */
- GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* in 0 */
- GPIO9_GPIO | WAKEUP_ON_EDGE_BOTH, /* in 1 */
- GPIO10_GPIO | WAKEUP_ON_EDGE_BOTH, /* in 2 */
- GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* in 3 */
- GPIO18_GPIO | MFP_LPM_DRIVE_LOW, /* out 0 */
- GPIO19_GPIO | MFP_LPM_DRIVE_LOW, /* out 1 */
- GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* out 2 */
- GPIO21_GPIO | MFP_LPM_DRIVE_LOW, /* out 3 */
- GPIO22_GPIO | MFP_LPM_DRIVE_LOW, /* out 4 */
- GPIO23_GPIO | MFP_LPM_DRIVE_LOW, /* out 5 */
- GPIO24_GPIO | MFP_LPM_DRIVE_LOW, /* out 6 */
- GPIO25_GPIO | MFP_LPM_DRIVE_LOW, /* out 7 */
- GPIO26_GPIO | MFP_LPM_DRIVE_LOW, /* out 8 */
- GPIO27_GPIO | MFP_LPM_DRIVE_LOW, /* out 9 */
- GPIO79_GPIO | MFP_LPM_DRIVE_LOW, /* out 10 */
- GPIO80_GPIO | MFP_LPM_DRIVE_LOW, /* out 11 */
-
- /* PXA GPIO KEYS */
- GPIO7_GPIO | WAKEUP_ON_EDGE_BOTH, /* hotsync button on cradle */
-
- /* MISC */
- GPIO1_RST, /* reset */
- GPIO2_GPIO, /* earphone detect */
- GPIO16_GPIO, /* backlight switch */
-};
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data palmtc_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 200,
-};
-
-static struct gpiod_lookup_table palmtc_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_SD_READONLY,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_SD_POWER,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static void __init palmtc_mmc_init(void)
-{
- gpiod_add_lookup_table(&palmtc_mci_gpio_table);
- pxa_set_mci_info(&palmtc_mci_platform_data);
-}
-#else
-static inline void palmtc_mmc_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button palmtc_pxa_buttons[] = {
- {KEY_F8, GPIO_NR_PALMTC_HOTSYNC_BUTTON, 1, "HotSync Button", EV_KEY, 1},
-};
-
-static struct gpio_keys_platform_data palmtc_pxa_keys_data = {
- .buttons = palmtc_pxa_buttons,
- .nbuttons = ARRAY_SIZE(palmtc_pxa_buttons),
-};
-
-static struct platform_device palmtc_pxa_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &palmtc_pxa_keys_data,
- },
-};
-
-static void __init palmtc_keys_init(void)
-{
- platform_device_register(&palmtc_pxa_keys);
-}
-#else
-static inline void palmtc_keys_init(void) {}
-#endif
-
-/******************************************************************************
- * Backlight
- ******************************************************************************/
-#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
-
-static struct gpiod_lookup_table palmtc_pwm_bl_gpio_table = {
- .dev_id = "pwm-backlight.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_BL_POWER,
- "enable", GPIO_ACTIVE_HIGH),
- },
-};
-
-static struct pwm_lookup palmtc_pwm_lookup[] = {
- PWM_LOOKUP("pxa25x-pwm.1", 0, "pwm-backlight.0", NULL, PALMTC_PERIOD_NS,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data palmtc_backlight_data = {
- .max_brightness = PALMTC_MAX_INTENSITY,
- .dft_brightness = PALMTC_MAX_INTENSITY,
-};
-
-static struct platform_device palmtc_backlight = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa25x_device_pwm1.dev,
- .platform_data = &palmtc_backlight_data,
- },
-};
-
-static void __init palmtc_pwm_init(void)
-{
- gpiod_add_lookup_table(&palmtc_pwm_bl_gpio_table);
- pwm_add_table(palmtc_pwm_lookup, ARRAY_SIZE(palmtc_pwm_lookup));
- platform_device_register(&palmtc_backlight);
-}
-#else
-static inline void palmtc_pwm_init(void) {}
-#endif
-
-/******************************************************************************
- * IrDA
- ******************************************************************************/
-#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE)
-static struct pxaficp_platform_data palmtc_ficp_platform_data = {
- .gpio_pwdown = GPIO_NR_PALMTC_IR_DISABLE,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-static void __init palmtc_irda_init(void)
-{
- pxa_set_ficp_info(&palmtc_ficp_platform_data);
-}
-#else
-static inline void palmtc_irda_init(void) {}
-#endif
-
-/******************************************************************************
- * Keyboard
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
-static const uint32_t palmtc_matrix_keys[] = {
- KEY(0, 0, KEY_F1),
- KEY(0, 1, KEY_X),
- KEY(0, 2, KEY_POWER),
- KEY(0, 3, KEY_TAB),
- KEY(0, 4, KEY_A),
- KEY(0, 5, KEY_Q),
- KEY(0, 6, KEY_LEFTSHIFT),
- KEY(0, 7, KEY_Z),
- KEY(0, 8, KEY_S),
- KEY(0, 9, KEY_W),
- KEY(0, 10, KEY_E),
- KEY(0, 11, KEY_UP),
-
- KEY(1, 0, KEY_F2),
- KEY(1, 1, KEY_DOWN),
- KEY(1, 3, KEY_D),
- KEY(1, 4, KEY_C),
- KEY(1, 5, KEY_F),
- KEY(1, 6, KEY_R),
- KEY(1, 7, KEY_SPACE),
- KEY(1, 8, KEY_V),
- KEY(1, 9, KEY_G),
- KEY(1, 10, KEY_T),
- KEY(1, 11, KEY_LEFT),
-
- KEY(2, 0, KEY_F3),
- KEY(2, 1, KEY_LEFTCTRL),
- KEY(2, 3, KEY_H),
- KEY(2, 4, KEY_Y),
- KEY(2, 5, KEY_N),
- KEY(2, 6, KEY_J),
- KEY(2, 7, KEY_U),
- KEY(2, 8, KEY_M),
- KEY(2, 9, KEY_K),
- KEY(2, 10, KEY_I),
- KEY(2, 11, KEY_RIGHT),
-
- KEY(3, 0, KEY_F4),
- KEY(3, 1, KEY_ENTER),
- KEY(3, 3, KEY_DOT),
- KEY(3, 4, KEY_L),
- KEY(3, 5, KEY_O),
- KEY(3, 6, KEY_LEFTALT),
- KEY(3, 7, KEY_ENTER),
- KEY(3, 8, KEY_BACKSPACE),
- KEY(3, 9, KEY_P),
- KEY(3, 10, KEY_B),
- KEY(3, 11, KEY_FN),
-};
-
-const struct matrix_keymap_data palmtc_keymap_data = {
- .keymap = palmtc_matrix_keys,
- .keymap_size = ARRAY_SIZE(palmtc_matrix_keys),
-};
-
-static const unsigned int palmtc_keypad_row_gpios[] = {
- 0, 9, 10, 11
-};
-
-static const unsigned int palmtc_keypad_col_gpios[] = {
- 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 79, 80
-};
-
-static struct matrix_keypad_platform_data palmtc_keypad_platform_data = {
- .keymap_data = &palmtc_keymap_data,
- .row_gpios = palmtc_keypad_row_gpios,
- .num_row_gpios = ARRAY_SIZE(palmtc_keypad_row_gpios),
- .col_gpios = palmtc_keypad_col_gpios,
- .num_col_gpios = ARRAY_SIZE(palmtc_keypad_col_gpios),
- .active_low = 1,
-
- .debounce_ms = 20,
- .col_scan_delay_us = 5,
-};
-
-static struct platform_device palmtc_keyboard = {
- .name = "matrix-keypad",
- .id = -1,
- .dev = {
- .platform_data = &palmtc_keypad_platform_data,
- },
-};
-static void __init palmtc_mkp_init(void)
-{
- platform_device_register(&palmtc_keyboard);
-}
-#else
-static inline void palmtc_mkp_init(void) {}
-#endif
-
-/******************************************************************************
- * UDC
- ******************************************************************************/
-#if defined(CONFIG_USB_PXA25X)||defined(CONFIG_USB_PXA25X_MODULE)
-static struct gpiod_lookup_table palmtc_udc_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_USB_DETECT_N,
- "vbus", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_USB_POWER,
- "pullup", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device palmtc_gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-static void __init palmtc_udc_init(void)
-{
- gpiod_add_lookup_table(&palmtc_udc_gpiod_table);
- platform_device_register(&palmtc_gpio_vbus);
-};
-#else
-static inline void palmtc_udc_init(void) {}
-#endif
-
-/******************************************************************************
- * Touchscreen / Battery / GPIO-extender
- ******************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \
- defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
-static struct platform_device palmtc_ucb1400_device = {
- .name = "ucb1400_core",
- .id = -1,
-};
-
-static void __init palmtc_ts_init(void)
-{
- pxa_set_ac97_info(NULL);
- platform_device_register(&palmtc_ucb1400_device);
-}
-#else
-static inline void palmtc_ts_init(void) {}
-#endif
-
-/******************************************************************************
- * LEDs
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-struct gpio_led palmtc_gpio_leds[] = {
-{
- .name = "palmtc:green:user",
- .default_trigger = "none",
- .gpio = GPIO_NR_PALMTC_LED_POWER,
- .active_low = 1,
-}, {
- .name = "palmtc:vibra:vibra",
- .default_trigger = "none",
- .gpio = GPIO_NR_PALMTC_VIBRA_POWER,
- .active_low = 1,
-}
-
-};
-
-static struct gpio_led_platform_data palmtc_gpio_led_info = {
- .leds = palmtc_gpio_leds,
- .num_leds = ARRAY_SIZE(palmtc_gpio_leds),
-};
-
-static struct platform_device palmtc_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &palmtc_gpio_led_info,
- }
-};
-
-static void __init palmtc_leds_init(void)
-{
- platform_device_register(&palmtc_leds);
-}
-#else
-static inline void palmtc_leds_init(void) {}
-#endif
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct resource palmtc_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_16M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct mtd_partition palmtc_flash_parts[] = {
- {
- .name = "U-Boot Bootloader",
- .offset = 0x0,
- .size = 0x40000,
- },
- {
- .name = "Linux Kernel",
- .offset = 0x40000,
- .size = 0x2c0000,
- },
- {
- .name = "Filesystem",
- .offset = 0x300000,
- .size = 0xcc0000,
- },
- {
- .name = "U-Boot Environment",
- .offset = 0xfc0000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data palmtc_flash_data = {
- .width = 4,
- .parts = palmtc_flash_parts,
- .nr_parts = ARRAY_SIZE(palmtc_flash_parts),
-};
-
-static struct platform_device palmtc_flash = {
- .name = "physmap-flash",
- .id = -1,
- .resource = &palmtc_flash_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = &palmtc_flash_data,
- },
-};
-
-static void __init palmtc_nor_init(void)
-{
- platform_device_register(&palmtc_flash);
-}
-#else
-static inline void palmtc_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info palmtc_lcd_modes[] = {
- {
- .pixclock = 115384,
- .xres = 320,
- .yres = 320,
- .bpp = 16,
-
- .left_margin = 27,
- .right_margin = 7,
- .upper_margin = 7,
- .lower_margin = 8,
-
- .hsync_len = 6,
- .vsync_len = 1,
- },
-};
-
-static struct pxafb_mach_info palmtc_lcd_screen = {
- .modes = palmtc_lcd_modes,
- .num_modes = ARRAY_SIZE(palmtc_lcd_modes),
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static void __init palmtc_lcd_init(void)
-{
- pxa_set_fb_info(NULL, &palmtc_lcd_screen);
-}
-#else
-static inline void palmtc_lcd_init(void) {}
-#endif
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void __init palmtc_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- pxa_set_hwuart_info(NULL);
-
- palmtc_mmc_init();
- palmtc_keys_init();
- palmtc_pwm_init();
- palmtc_irda_init();
- palmtc_mkp_init();
- palmtc_udc_init();
- palmtc_ts_init();
- palmtc_nor_init();
- palmtc_lcd_init();
- palmtc_leds_init();
-};
-
-MACHINE_START(PALMTC, "Palm Tungsten|C")
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = palmtc_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
deleted file mode 100644
index a2b10db4aacc..000000000000
--- a/arch/arm/mach-pxa/palmte2.c
+++ /dev/null
@@ -1,383 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware definitions for Palm Tungsten|E2
- *
- * Author:
- * Carlos Eduardo Medaglia Dyonisio <cadu@nerdfeliz.com>
- *
- * Rewrite for mainline:
- * Marek Vasut <marek.vasut@gmail.com>
- *
- * (find more info at www.hackndev.com)
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio/machine.h>
-#include <linux/input.h>
-#include <linux/pda_power.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio.h>
-#include <linux/wm97xx.h>
-#include <linux/power_supply.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa25x.h"
-#include <mach/audio.h>
-#include "palmte2.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include "udc.h"
-#include <linux/platform_data/asoc-palm27x.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long palmte2_pin_config[] __initdata = {
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO8_MMC_CS0,
- GPIO10_GPIO, /* SD detect */
- GPIO55_GPIO, /* SD power */
- GPIO51_GPIO, /* SD r/o switch */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* PWM */
- GPIO16_PWM0_OUT,
-
- /* USB */
- GPIO15_GPIO, /* usb detect */
- GPIO53_GPIO, /* usb power */
-
- /* IrDA */
- GPIO48_GPIO, /* ir disable */
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* GPIO KEYS */
- GPIO5_GPIO, /* notes */
- GPIO7_GPIO, /* tasks */
- GPIO11_GPIO, /* calendar */
- GPIO13_GPIO, /* contacts */
- GPIO14_GPIO, /* center */
- GPIO19_GPIO, /* left */
- GPIO20_GPIO, /* right */
- GPIO21_GPIO, /* down */
- GPIO22_GPIO, /* up */
-
- /* MISC */
- GPIO1_RST, /* reset */
- GPIO4_GPIO, /* Hotsync button */
- GPIO9_GPIO, /* power detect */
- GPIO15_GPIO, /* earphone detect */
- GPIO37_GPIO, /* LCD power */
- GPIO56_GPIO, /* Backlight power */
-};
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-static struct pxamci_platform_data palmte2_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table palmte2_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTE2_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTE2_SD_READONLY,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTE2_SD_POWER,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-static struct gpio_keys_button palmte2_pxa_buttons[] = {
- {KEY_F1, GPIO_NR_PALMTE2_KEY_CONTACTS, 1, "Contacts" },
- {KEY_F2, GPIO_NR_PALMTE2_KEY_CALENDAR, 1, "Calendar" },
- {KEY_F3, GPIO_NR_PALMTE2_KEY_TASKS, 1, "Tasks" },
- {KEY_F4, GPIO_NR_PALMTE2_KEY_NOTES, 1, "Notes" },
- {KEY_ENTER, GPIO_NR_PALMTE2_KEY_CENTER, 1, "Center" },
- {KEY_LEFT, GPIO_NR_PALMTE2_KEY_LEFT, 1, "Left" },
- {KEY_RIGHT, GPIO_NR_PALMTE2_KEY_RIGHT, 1, "Right" },
- {KEY_DOWN, GPIO_NR_PALMTE2_KEY_DOWN, 1, "Down" },
- {KEY_UP, GPIO_NR_PALMTE2_KEY_UP, 1, "Up" },
-};
-
-static struct gpio_keys_platform_data palmte2_pxa_keys_data = {
- .buttons = palmte2_pxa_buttons,
- .nbuttons = ARRAY_SIZE(palmte2_pxa_buttons),
-};
-
-static struct platform_device palmte2_pxa_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &palmte2_pxa_keys_data,
- },
-};
-#endif
-
-/******************************************************************************
- * Backlight
- ******************************************************************************/
-static struct pwm_lookup palmte2_pwm_lookup[] = {
- PWM_LOOKUP("pxa25x-pwm.0", 0, "pwm-backlight.0", NULL,
- PALMTE2_PERIOD_NS, PWM_POLARITY_NORMAL),
-};
-
-static struct gpio palmte_bl_gpios[] = {
- { GPIO_NR_PALMTE2_BL_POWER, GPIOF_INIT_LOW, "Backlight power" },
- { GPIO_NR_PALMTE2_LCD_POWER, GPIOF_INIT_LOW, "LCD power" },
-};
-
-static int palmte2_backlight_init(struct device *dev)
-{
- return gpio_request_array(ARRAY_AND_SIZE(palmte_bl_gpios));
-}
-
-static int palmte2_backlight_notify(struct device *dev, int brightness)
-{
- gpio_set_value(GPIO_NR_PALMTE2_BL_POWER, brightness);
- gpio_set_value(GPIO_NR_PALMTE2_LCD_POWER, brightness);
- return brightness;
-}
-
-static void palmte2_backlight_exit(struct device *dev)
-{
- gpio_free_array(ARRAY_AND_SIZE(palmte_bl_gpios));
-}
-
-static struct platform_pwm_backlight_data palmte2_backlight_data = {
- .max_brightness = PALMTE2_MAX_INTENSITY,
- .dft_brightness = PALMTE2_MAX_INTENSITY,
- .init = palmte2_backlight_init,
- .notify = palmte2_backlight_notify,
- .exit = palmte2_backlight_exit,
-};
-
-static struct platform_device palmte2_backlight = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa25x_device_pwm0.dev,
- .platform_data = &palmte2_backlight_data,
- },
-};
-
-/******************************************************************************
- * IrDA
- ******************************************************************************/
-static struct pxaficp_platform_data palmte2_ficp_platform_data = {
- .gpio_pwdown = GPIO_NR_PALMTE2_IR_DISABLE,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-/******************************************************************************
- * UDC
- ******************************************************************************/
-static struct gpiod_lookup_table palmte2_udc_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTE2_USB_DETECT_N,
- "vbus", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTE2_USB_PULLUP,
- "pullup", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device palmte2_gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-/******************************************************************************
- * Power supply
- ******************************************************************************/
-static int power_supply_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(GPIO_NR_PALMTE2_POWER_DETECT, "CABLE_STATE_AC");
- if (ret)
- goto err1;
- ret = gpio_direction_input(GPIO_NR_PALMTE2_POWER_DETECT);
- if (ret)
- goto err2;
-
- return 0;
-
-err2:
- gpio_free(GPIO_NR_PALMTE2_POWER_DETECT);
-err1:
- return ret;
-}
-
-static int palmte2_is_ac_online(void)
-{
- return gpio_get_value(GPIO_NR_PALMTE2_POWER_DETECT);
-}
-
-static void power_supply_exit(struct device *dev)
-{
- gpio_free(GPIO_NR_PALMTE2_POWER_DETECT);
-}
-
-static char *palmte2_supplicants[] = {
- "main-battery",
-};
-
-static struct pda_power_pdata power_supply_info = {
- .init = power_supply_init,
- .is_ac_online = palmte2_is_ac_online,
- .exit = power_supply_exit,
- .supplied_to = palmte2_supplicants,
- .num_supplicants = ARRAY_SIZE(palmte2_supplicants),
-};
-
-static struct platform_device power_supply = {
- .name = "pda-power",
- .id = -1,
- .dev = {
- .platform_data = &power_supply_info,
- },
-};
-
-/******************************************************************************
- * WM97xx audio, battery
- ******************************************************************************/
-static struct wm97xx_batt_pdata palmte2_batt_pdata = {
- .batt_aux = WM97XX_AUX_ID3,
- .temp_aux = WM97XX_AUX_ID2,
- .max_voltage = PALMTE2_BAT_MAX_VOLTAGE,
- .min_voltage = PALMTE2_BAT_MIN_VOLTAGE,
- .batt_mult = 1000,
- .batt_div = 414,
- .temp_mult = 1,
- .temp_div = 1,
- .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO,
- .batt_name = "main-batt",
-};
-
-static struct wm97xx_pdata palmte2_wm97xx_pdata = {
- .batt_pdata = &palmte2_batt_pdata,
-};
-
-static pxa2xx_audio_ops_t palmte2_ac97_pdata = {
- .codec_pdata = { &palmte2_wm97xx_pdata, },
-};
-
-static struct palm27x_asoc_info palmte2_asoc_pdata = {
- .jack_gpio = GPIO_NR_PALMTE2_EARPHONE_DETECT,
-};
-
-static struct platform_device palmte2_asoc = {
- .name = "palm27x-asoc",
- .id = -1,
- .dev = {
- .platform_data = &palmte2_asoc_pdata,
- },
-};
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-static struct pxafb_mode_info palmte2_lcd_modes[] = {
-{
- .pixclock = 77757,
- .xres = 320,
- .yres = 320,
- .bpp = 16,
-
- .left_margin = 28,
- .right_margin = 7,
- .upper_margin = 7,
- .lower_margin = 5,
-
- .hsync_len = 4,
- .vsync_len = 1,
-},
-};
-
-static struct pxafb_mach_info palmte2_lcd_screen = {
- .modes = palmte2_lcd_modes,
- .num_modes = ARRAY_SIZE(palmte2_lcd_modes),
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static struct platform_device *devices[] __initdata = {
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
- &palmte2_pxa_keys,
-#endif
- &palmte2_backlight,
- &power_supply,
- &palmte2_asoc,
- &palmte2_gpio_vbus,
-};
-
-/* setup udc GPIOs initial state */
-static void __init palmte2_udc_init(void)
-{
- if (!gpio_request(GPIO_NR_PALMTE2_USB_PULLUP, "UDC Vbus")) {
- gpio_direction_output(GPIO_NR_PALMTE2_USB_PULLUP, 1);
- gpio_free(GPIO_NR_PALMTE2_USB_PULLUP);
- }
-}
-
-static void __init palmte2_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(palmte2_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- pxa_set_fb_info(NULL, &palmte2_lcd_screen);
- gpiod_add_lookup_table(&palmte2_mci_gpio_table);
- pxa_set_mci_info(&palmte2_mci_platform_data);
- palmte2_udc_init();
- pxa_set_ac97_info(&palmte2_ac97_pdata);
- pxa_set_ficp_info(&palmte2_ficp_platform_data);
-
- pwm_add_table(palmte2_pwm_lookup, ARRAY_SIZE(palmte2_pwm_lookup));
- gpiod_add_lookup_table(&palmte2_udc_gpiod_table);
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-MACHINE_START(PALMTE2, "Palm Tungsten|E2")
- .atag_offset = 0x100,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = palmte2_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/palmte2.h b/arch/arm/mach-pxa/palmte2.h
deleted file mode 100644
index 2589400c1a2f..000000000000
--- a/arch/arm/mach-pxa/palmte2.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIOs and interrupts for Palm Tungsten|E2 Handheld Computer
- *
- * Author:
- * Carlos Eduardo Medaglia Dyonisio <cadu@nerdfeliz.com>
- */
-
-#ifndef _INCLUDE_PALMTE2_H_
-#define _INCLUDE_PALMTE2_H_
-
-/** HERE ARE GPIOs **/
-
-/* GPIOs */
-#define GPIO_NR_PALMTE2_POWER_DETECT 9
-#define GPIO_NR_PALMTE2_HOTSYNC_BUTTON_N 4
-#define GPIO_NR_PALMTE2_EARPHONE_DETECT 15
-
-/* SD/MMC */
-#define GPIO_NR_PALMTE2_SD_DETECT_N 10
-#define GPIO_NR_PALMTE2_SD_POWER 55
-#define GPIO_NR_PALMTE2_SD_READONLY 51
-
-/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
-#define GPIO_NR_PALMTE2_IR_DISABLE 48
-
-/* USB */
-#define GPIO_NR_PALMTE2_USB_DETECT_N 35
-#define GPIO_NR_PALMTE2_USB_PULLUP 53
-
-/* LCD/BACKLIGHT */
-#define GPIO_NR_PALMTE2_BL_POWER 56
-#define GPIO_NR_PALMTE2_LCD_POWER 37
-
-/* KEYS */
-#define GPIO_NR_PALMTE2_KEY_NOTES 5
-#define GPIO_NR_PALMTE2_KEY_TASKS 7
-#define GPIO_NR_PALMTE2_KEY_CALENDAR 11
-#define GPIO_NR_PALMTE2_KEY_CONTACTS 13
-#define GPIO_NR_PALMTE2_KEY_CENTER 14
-#define GPIO_NR_PALMTE2_KEY_LEFT 19
-#define GPIO_NR_PALMTE2_KEY_RIGHT 20
-#define GPIO_NR_PALMTE2_KEY_DOWN 21
-#define GPIO_NR_PALMTE2_KEY_UP 22
-
-/** HERE ARE INIT VALUES **/
-
-/* BACKLIGHT */
-#define PALMTE2_MAX_INTENSITY 0xFE
-#define PALMTE2_DEFAULT_INTENSITY 0x7E
-#define PALMTE2_LIMIT_MASK 0x7F
-#define PALMTE2_PRESCALER 0x3F
-#define PALMTE2_PERIOD_NS 3500
-
-/* BATTERY */
-#define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
-#define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMTE2_BAT_MAX_CURRENT 0 /* unknown */
-#define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */
-#define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */
-#define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */
-#define PALMTE2_MAX_LIFE_MINS 360 /* on-life in minutes */
-
-#endif
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
deleted file mode 100644
index 2bf0f7f3ea24..000000000000
--- a/arch/arm/mach-pxa/palmtreo.c
+++ /dev/null
@@ -1,548 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware definitions for Palm Treo smartphones
- *
- * currently supported:
- * Palm Treo 680 (GSM)
- * Palm Centro 685 (GSM)
- *
- * Author: Tomas Cech <sleep_walker@suse.cz>
- *
- * (find more info at www.hackndev.com)
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/memblock.h>
-#include <linux/pda_power.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio.h>
-#include <linux/power_supply.h>
-#include <linux/w1-gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa27x.h"
-#include "pxa27x-udc.h"
-#include <mach/audio.h>
-#include "palmtreo.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include "udc.h"
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/pxa2xx-regs.h>
-#include <linux/platform_data/asoc-palm27x.h>
-#include <linux/platform_data/media/camera-pxa.h>
-#include "palm27x.h"
-
-#include <sound/pxa2xx-lib.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long treo_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO113_GPIO, /* SD detect */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO89_AC97_SYSCLK,
- GPIO95_AC97_nRESET,
-
- /* IrDA */
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-
- /* PWM */
- GPIO16_PWM0_OUT,
-
- /* USB */
- GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */
-
- /* MATRIX KEYPAD */
- GPIO101_KP_MKIN_1,
- GPIO102_KP_MKIN_2,
- GPIO97_KP_MKIN_3,
- GPIO98_KP_MKIN_4,
- GPIO91_KP_MKIN_6,
- GPIO13_KP_MKIN_7,
- GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
- GPIO96_KP_MKOUT_6,
- GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */
-
- /* Quick Capture Interface */
- GPIO84_CIF_FV,
- GPIO85_CIF_LV,
- GPIO53_CIF_MCLK,
- GPIO54_CIF_PCLK,
- GPIO81_CIF_DD_0,
- GPIO55_CIF_DD_1,
- GPIO51_CIF_DD_2,
- GPIO50_CIF_DD_3,
- GPIO52_CIF_DD_4,
- GPIO48_CIF_DD_5,
- GPIO17_CIF_DD_6,
- GPIO12_CIF_DD_7,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* GSM */
- GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH, /* GSM host wake up */
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
- GPIO39_FFUART_TXD,
- GPIO41_FFUART_RTS,
-
- /* MISC. */
- GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* external power detect */
- GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* silent switch */
- GPIO116_GPIO, /* headphone detect */
- GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */
-};
-
-#ifdef CONFIG_MACH_TREO680
-static unsigned long treo680_pin_config[] __initdata = {
- GPIO33_GPIO, /* SD read only */
-
- /* MATRIX KEYPAD - different wake up source */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO99_KP_MKIN_5,
-
- /* LCD... L_BIAS alt fn not configured on Treo680; is GPIO instead */
- GPIOxx_LCD_16BPP,
- GPIO74_LCD_FCLK,
- GPIO75_LCD_LCLK,
- GPIO76_LCD_PCLK,
-};
-#endif /* CONFIG_MACH_TREO680 */
-
-#ifdef CONFIG_MACH_CENTRO
-static unsigned long centro685_pin_config[] __initdata = {
- /* Bluetooth attached to BT UART*/
- MFP_CFG_OUT(GPIO80, AF0, DRIVE_LOW), /* power: LOW = off */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* MATRIX KEYPAD - different wake up source */
- GPIO100_KP_MKIN_0,
- GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-};
-#endif /* CONFIG_MACH_CENTRO */
-
-/******************************************************************************
- * GPIO keyboard
- ******************************************************************************/
-#if IS_ENABLED(CONFIG_KEYBOARD_PXA27x)
-static const unsigned int treo680_matrix_keys[] = {
- KEY(0, 0, KEY_F8), /* Red/Off/Power */
- KEY(0, 1, KEY_LEFT),
- KEY(0, 2, KEY_LEFTCTRL), /* Alternate */
- KEY(0, 3, KEY_L),
- KEY(0, 4, KEY_A),
- KEY(0, 5, KEY_Q),
- KEY(0, 6, KEY_P),
-
- KEY(1, 0, KEY_RIGHTCTRL), /* Menu */
- KEY(1, 1, KEY_RIGHT),
- KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */
- KEY(1, 3, KEY_Z),
- KEY(1, 4, KEY_S),
- KEY(1, 5, KEY_W),
-
- KEY(2, 0, KEY_F1), /* Phone */
- KEY(2, 1, KEY_UP),
- KEY(2, 2, KEY_0),
- KEY(2, 3, KEY_X),
- KEY(2, 4, KEY_D),
- KEY(2, 5, KEY_E),
-
- KEY(3, 0, KEY_F10), /* Calendar */
- KEY(3, 1, KEY_DOWN),
- KEY(3, 2, KEY_SPACE),
- KEY(3, 3, KEY_C),
- KEY(3, 4, KEY_F),
- KEY(3, 5, KEY_R),
-
- KEY(4, 0, KEY_F12), /* Mail */
- KEY(4, 1, KEY_KPENTER),
- KEY(4, 2, KEY_RIGHTALT), /* Alt */
- KEY(4, 3, KEY_V),
- KEY(4, 4, KEY_G),
- KEY(4, 5, KEY_T),
-
- KEY(5, 0, KEY_F9), /* Home */
- KEY(5, 1, KEY_PAGEUP), /* Side up */
- KEY(5, 2, KEY_DOT),
- KEY(5, 3, KEY_B),
- KEY(5, 4, KEY_H),
- KEY(5, 5, KEY_Y),
-
- KEY(6, 0, KEY_TAB), /* Side Activate */
- KEY(6, 1, KEY_PAGEDOWN), /* Side down */
- KEY(6, 2, KEY_ENTER),
- KEY(6, 3, KEY_N),
- KEY(6, 4, KEY_J),
- KEY(6, 5, KEY_U),
-
- KEY(7, 0, KEY_F6), /* Green/Call */
- KEY(7, 1, KEY_O),
- KEY(7, 2, KEY_BACKSPACE),
- KEY(7, 3, KEY_M),
- KEY(7, 4, KEY_K),
- KEY(7, 5, KEY_I),
-};
-
-static const unsigned int centro_matrix_keys[] = {
- KEY(0, 0, KEY_F9), /* Home */
- KEY(0, 1, KEY_LEFT),
- KEY(0, 2, KEY_LEFTCTRL), /* Alternate */
- KEY(0, 3, KEY_L),
- KEY(0, 4, KEY_A),
- KEY(0, 5, KEY_Q),
- KEY(0, 6, KEY_P),
-
- KEY(1, 0, KEY_RIGHTCTRL), /* Menu */
- KEY(1, 1, KEY_RIGHT),
- KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */
- KEY(1, 3, KEY_Z),
- KEY(1, 4, KEY_S),
- KEY(1, 5, KEY_W),
-
- KEY(2, 0, KEY_F1), /* Phone */
- KEY(2, 1, KEY_UP),
- KEY(2, 2, KEY_0),
- KEY(2, 3, KEY_X),
- KEY(2, 4, KEY_D),
- KEY(2, 5, KEY_E),
-
- KEY(3, 0, KEY_F10), /* Calendar */
- KEY(3, 1, KEY_DOWN),
- KEY(3, 2, KEY_SPACE),
- KEY(3, 3, KEY_C),
- KEY(3, 4, KEY_F),
- KEY(3, 5, KEY_R),
-
- KEY(4, 0, KEY_F12), /* Mail */
- KEY(4, 1, KEY_KPENTER),
- KEY(4, 2, KEY_RIGHTALT), /* Alt */
- KEY(4, 3, KEY_V),
- KEY(4, 4, KEY_G),
- KEY(4, 5, KEY_T),
-
- KEY(5, 0, KEY_F8), /* Red/Off/Power */
- KEY(5, 1, KEY_PAGEUP), /* Side up */
- KEY(5, 2, KEY_DOT),
- KEY(5, 3, KEY_B),
- KEY(5, 4, KEY_H),
- KEY(5, 5, KEY_Y),
-
- KEY(6, 0, KEY_TAB), /* Side Activate */
- KEY(6, 1, KEY_PAGEDOWN), /* Side down */
- KEY(6, 2, KEY_ENTER),
- KEY(6, 3, KEY_N),
- KEY(6, 4, KEY_J),
- KEY(6, 5, KEY_U),
-
- KEY(7, 0, KEY_F6), /* Green/Call */
- KEY(7, 1, KEY_O),
- KEY(7, 2, KEY_BACKSPACE),
- KEY(7, 3, KEY_M),
- KEY(7, 4, KEY_K),
- KEY(7, 5, KEY_I),
-};
-
-static struct matrix_keymap_data treo680_matrix_keymap_data = {
- .keymap = treo680_matrix_keys,
- .keymap_size = ARRAY_SIZE(treo680_matrix_keys),
-};
-
-static struct matrix_keymap_data centro_matrix_keymap_data = {
- .keymap = centro_matrix_keys,
- .keymap_size = ARRAY_SIZE(centro_matrix_keys),
-};
-
-static struct pxa27x_keypad_platform_data treo680_keypad_pdata = {
- .matrix_key_rows = 8,
- .matrix_key_cols = 7,
- .matrix_keymap_data = &treo680_matrix_keymap_data,
- .direct_key_map = { KEY_CONNECT },
- .direct_key_num = 1,
-
- .debounce_interval = 30,
-};
-
-static void __init palmtreo_kpc_init(void)
-{
- static struct pxa27x_keypad_platform_data *data = &treo680_keypad_pdata;
-
- if (machine_is_centro())
- data->matrix_keymap_data = &centro_matrix_keymap_data;
-
- pxa_set_keypad_info(&treo680_keypad_pdata);
-}
-#else
-static inline void palmtreo_kpc_init(void) {}
-#endif
-
-/******************************************************************************
- * USB host
- ******************************************************************************/
-#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
-static struct pxaohci_platform_data treo680_ohci_info = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 | ENABLE_PORT3,
- .power_budget = 0,
-};
-
-static void __init palmtreo_uhc_init(void)
-{
- if (machine_is_treo680())
- pxa_set_ohci_info(&treo680_ohci_info);
-}
-#else
-static inline void palmtreo_uhc_init(void) {}
-#endif
-
-/******************************************************************************
- * Vibra and LEDs
- ******************************************************************************/
-static struct gpio_led treo680_gpio_leds[] = {
- {
- .name = "treo680:vibra:vibra",
- .default_trigger = "none",
- .gpio = GPIO_NR_TREO680_VIBRATE_EN,
- },
- {
- .name = "treo680:green:led",
- .default_trigger = "mmc0",
- .gpio = GPIO_NR_TREO_GREEN_LED,
- },
- {
- .name = "treo680:white:keybbl",
- .default_trigger = "none",
- .gpio = GPIO_NR_TREO680_KEYB_BL,
- },
-};
-
-static struct gpio_led_platform_data treo680_gpio_led_info = {
- .leds = treo680_gpio_leds,
- .num_leds = ARRAY_SIZE(treo680_gpio_leds),
-};
-
-static struct gpio_led centro_gpio_leds[] = {
- {
- .name = "centro:vibra:vibra",
- .default_trigger = "none",
- .gpio = GPIO_NR_CENTRO_VIBRATE_EN,
- },
- {
- .name = "centro:green:led",
- .default_trigger = "mmc0",
- .gpio = GPIO_NR_TREO_GREEN_LED,
- },
- {
- .name = "centro:white:keybbl",
- .default_trigger = "none",
- .active_low = 1,
- .gpio = GPIO_NR_CENTRO_KEYB_BL,
- },
-};
-
-static struct gpio_led_platform_data centro_gpio_led_info = {
- .leds = centro_gpio_leds,
- .num_leds = ARRAY_SIZE(centro_gpio_leds),
-};
-
-static struct platform_device palmtreo_leds = {
- .name = "leds-gpio",
- .id = -1,
-};
-
-static void __init palmtreo_leds_init(void)
-{
- if (machine_is_centro())
- palmtreo_leds.dev.platform_data = &centro_gpio_led_info;
- else if (machine_is_treo680())
- palmtreo_leds.dev.platform_data = &treo680_gpio_led_info;
-
- platform_device_register(&palmtreo_leds);
-}
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void __init treo_reserve(void)
-{
- memblock_reserve(0xa0000000, 0x1000);
- memblock_reserve(0xa2000000, 0x1000);
-}
-
-static void __init palmphone_common_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(treo_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- palm27x_pm_init(TREO_STR_BASE);
- palm27x_lcd_init(GPIO_NR_TREO_BL_POWER, &palm_320x320_new_lcd_mode);
- palm27x_udc_init(GPIO_NR_TREO_USB_DETECT, GPIO_NR_TREO_USB_PULLUP, 1);
- palm27x_irda_init(GPIO_NR_TREO_IR_EN);
- palm27x_ac97_init(-1, -1, -1, 95);
- palm27x_pwm_init(GPIO_NR_TREO_BL_POWER, -1);
- palm27x_power_init(GPIO_NR_TREO_POWER_DETECT, -1);
- palm27x_pmic_init();
- palmtreo_kpc_init();
- palmtreo_uhc_init();
- palmtreo_leds_init();
-}
-
-#ifdef CONFIG_MACH_TREO680
-void __init treo680_gpio_init(void)
-{
- unsigned int gpio;
-
- /* drive all three lcd gpios high initially */
- const unsigned long lcd_flags = GPIOF_INIT_HIGH | GPIOF_DIR_OUT;
-
- /*
- * LCD GPIO initialization...
- */
-
- /*
- * This is likely the power to the lcd. Toggling it low/high appears to
- * turn the lcd off/on. Can be toggled after lcd is initialized without
- * any apparent adverse effects to the lcd operation. Note that this
- * gpio line is used by the lcd controller as the L_BIAS signal, but
- * treo680 configures it as gpio.
- */
- gpio = GPIO_NR_TREO680_LCD_POWER;
- if (gpio_request_one(gpio, lcd_flags, "LCD power") < 0)
- goto fail;
-
- /*
- * These two are called "enables", for lack of a better understanding.
- * If either of these are toggled after the lcd is initialized, the
- * image becomes degraded. N.B. The IPL shipped with the treo
- * configures GPIO_NR_TREO680_LCD_EN_N as output and drives it high. If
- * the IPL is ever reprogrammed, this initialization may be need to be
- * revisited.
- */
- gpio = GPIO_NR_TREO680_LCD_EN;
- if (gpio_request_one(gpio, lcd_flags, "LCD enable") < 0)
- goto fail;
- gpio = GPIO_NR_TREO680_LCD_EN_N;
- if (gpio_request_one(gpio, lcd_flags, "LCD enable_n") < 0)
- goto fail;
-
- /* driving this low turns LCD on */
- gpio_set_value(GPIO_NR_TREO680_LCD_EN_N, 0);
-
- return;
- fail:
- pr_err("gpio %d initialization failed\n", gpio);
- gpio_free(GPIO_NR_TREO680_LCD_POWER);
- gpio_free(GPIO_NR_TREO680_LCD_EN);
- gpio_free(GPIO_NR_TREO680_LCD_EN_N);
-}
-
-static struct gpiod_lookup_table treo680_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_TREO_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_TREO680_SD_READONLY,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_TREO680_SD_POWER,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static void __init treo680_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
- palmphone_common_init();
- treo680_gpio_init();
- palm27x_mmc_init(&treo680_mci_gpio_table);
-}
-#endif
-
-#ifdef CONFIG_MACH_CENTRO
-
-static struct gpiod_lookup_table centro685_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_TREO_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_CENTRO_SD_POWER,
- "power", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init centro_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config));
- palmphone_common_init();
- palm27x_mmc_init(&centro685_mci_gpio_table);
-}
-#endif
-
-#ifdef CONFIG_MACH_TREO680
-MACHINE_START(TREO680, "Palm Treo 680")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .reserve = treo_reserve,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = treo680_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_CENTRO
-MACHINE_START(CENTRO, "Palm Centro 685")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .reserve = treo_reserve,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = centro_init,
- .restart = pxa_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-pxa/palmtreo.h b/arch/arm/mach-pxa/palmtreo.h
deleted file mode 100644
index 5715cd505424..000000000000
--- a/arch/arm/mach-pxa/palmtreo.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIOs and interrupts for Palm Treo smartphones
- *
- * currently supported:
- * Palm Treo 680 (GSM)
- * Palm Centro 685 (GSM)
- *
- * Author: Tomas Cech <sleep_walker@suse.cz>
- *
- * find more info at www.hackndev.com
- */
-
-#ifndef _INCLUDE_TREO_H_
-#define _INCLUDE_TREO_H_
-
-/* GPIOs */
-#define GPIO_NR_TREO_POWER_DETECT 0
-#define GPIO_NR_TREO_AMP_EN 27
-#define GPIO_NR_TREO_GREEN_LED 20
-#define GPIO_NR_TREO_RED_LED 79
-#define GPIO_NR_TREO_SD_DETECT_N 113
-#define GPIO_NR_TREO_EP_DETECT_N 116
-#define GPIO_NR_TREO_USB_DETECT 1
-#define GPIO_NR_TREO_USB_PULLUP 114
-#define GPIO_NR_TREO_GSM_POWER 40
-#define GPIO_NR_TREO_GSM_RESET 87
-#define GPIO_NR_TREO_GSM_WAKE 57
-#define GPIO_NR_TREO_GSM_HOST_WAKE 14
-#define GPIO_NR_TREO_GSM_TRIGGER 10
-#define GPIO_NR_TREO_IR_EN 115
-#define GPIO_NR_TREO_IR_TXD 47
-#define GPIO_NR_TREO_BL_POWER 38
-#define GPIO_NR_TREO_LCD_POWER 25
-
-/* Treo680 specific GPIOs */
-#define GPIO_NR_TREO680_SD_READONLY 33
-#define GPIO_NR_TREO680_SD_POWER 42
-#define GPIO_NR_TREO680_VIBRATE_EN 44
-#define GPIO_NR_TREO680_KEYB_BL 24
-#define GPIO_NR_TREO680_BT_EN 43
-#define GPIO_NR_TREO680_LCD_POWER 77
-#define GPIO_NR_TREO680_LCD_EN 86
-#define GPIO_NR_TREO680_LCD_EN_N 25
-
-/* Centro685 specific GPIOs */
-#define GPIO_NR_CENTRO_SD_POWER 21
-#define GPIO_NR_CENTRO_VIBRATE_EN 22
-#define GPIO_NR_CENTRO_KEYB_BL 33
-#define GPIO_NR_CENTRO_BT_EN 80
-
-/* Various addresses */
-#define TREO_PHYS_RAM_START 0xa0000000
-#define TREO_PHYS_IO_START 0x40000000
-#define TREO_STR_BASE 0xa2000000
-
-/* BACKLIGHT */
-#define TREO_MAX_INTENSITY 254
-#define TREO_DEFAULT_INTENSITY 160
-#define TREO_LIMIT_MASK 0x7F
-#define TREO_PRESCALER 63
-#define TREO_PERIOD_NS 3500
-
-#endif
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
deleted file mode 100644
index 07332c92c9f7..000000000000
--- a/arch/arm/mach-pxa/palmtx.c
+++ /dev/null
@@ -1,381 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware definitions for PalmTX
- *
- * Author: Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on work of:
- * Alex Osborne <ato@meshy.org>
- * Cristiano P. <cristianop@users.sourceforge.net>
- * Jan Herman <2hp@seznam.cz>
- * Michal Hrusecky
- *
- * (find more info at www.hackndev.com)
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/pda_power.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio.h>
-#include <linux/wm97xx.h>
-#include <linux/power_supply.h>
-#include <linux/mtd/platnand.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa27x.h"
-#include <mach/audio.h>
-#include <mach/palmtx.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include "udc.h"
-#include <linux/platform_data/asoc-palm27x.h>
-#include "palm27x.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long palmtx_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO14_GPIO, /* SD detect */
- GPIO114_GPIO, /* SD power */
- GPIO115_GPIO, /* SD r/o switch */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO89_AC97_SYSCLK,
- GPIO95_AC97_nRESET,
-
- /* IrDA */
- GPIO40_GPIO, /* ir disable */
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-
- /* PWM */
- GPIO16_PWM0_OUT,
-
- /* USB */
- GPIO13_GPIO, /* usb detect */
- GPIO93_GPIO, /* usb power */
-
- /* PCMCIA */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO79_PSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
- GPIO94_GPIO, /* wifi power 1 */
- GPIO108_GPIO, /* wifi power 2 */
- GPIO116_GPIO, /* wifi ready */
-
- /* MATRIX KEYPAD */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* FFUART */
- GPIO34_FFUART_RXD,
- GPIO39_FFUART_TXD,
-
- /* NAND */
- GPIO15_nCS_1,
- GPIO18_RDY,
-
- /* MISC. */
- GPIO10_GPIO, /* hotsync button */
- GPIO12_GPIO, /* power detect */
- GPIO107_GPIO, /* earphone detect */
-};
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition palmtx_partitions[] = {
- {
- .name = "Flash",
- .offset = 0x00000000,
- .size = MTDPART_SIZ_FULL,
- .mask_flags = 0
- }
-};
-
-static struct physmap_flash_data palmtx_flash_data[] = {
- {
- .width = 2, /* bankwidth in bytes */
- .parts = palmtx_partitions,
- .nr_parts = ARRAY_SIZE(palmtx_partitions)
- }
-};
-
-static struct resource palmtx_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_8M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device palmtx_flash = {
- .name = "physmap-flash",
- .id = 0,
- .resource = &palmtx_flash_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = palmtx_flash_data,
- },
-};
-
-static void __init palmtx_nor_init(void)
-{
- platform_device_register(&palmtx_flash);
-}
-#else
-static inline void palmtx_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keyboard
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int palmtx_matrix_keys[] = {
- KEY(0, 0, KEY_POWER),
- KEY(0, 1, KEY_F1),
- KEY(0, 2, KEY_ENTER),
-
- KEY(1, 0, KEY_F2),
- KEY(1, 1, KEY_F3),
- KEY(1, 2, KEY_F4),
-
- KEY(2, 0, KEY_UP),
- KEY(2, 2, KEY_DOWN),
-
- KEY(3, 0, KEY_RIGHT),
- KEY(3, 2, KEY_LEFT),
-};
-
-static struct matrix_keymap_data palmtx_matrix_keymap_data = {
- .keymap = palmtx_matrix_keys,
- .keymap_size = ARRAY_SIZE(palmtx_matrix_keys),
-};
-
-static struct pxa27x_keypad_platform_data palmtx_keypad_platform_data = {
- .matrix_key_rows = 4,
- .matrix_key_cols = 3,
- .matrix_keymap_data = &palmtx_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-
-static void __init palmtx_kpc_init(void)
-{
- pxa_set_keypad_info(&palmtx_keypad_platform_data);
-}
-#else
-static inline void palmtx_kpc_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button palmtx_pxa_buttons[] = {
- {KEY_F8, GPIO_NR_PALMTX_HOTSYNC_BUTTON_N, 1, "HotSync Button" },
-};
-
-static struct gpio_keys_platform_data palmtx_pxa_keys_data = {
- .buttons = palmtx_pxa_buttons,
- .nbuttons = ARRAY_SIZE(palmtx_pxa_buttons),
-};
-
-static struct platform_device palmtx_pxa_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &palmtx_pxa_keys_data,
- },
-};
-
-static void __init palmtx_keys_init(void)
-{
- platform_device_register(&palmtx_pxa_keys);
-}
-#else
-static inline void palmtx_keys_init(void) {}
-#endif
-
-/******************************************************************************
- * NAND Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_NAND_PLATFORM) || \
- defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-static void palmtx_nand_cmd_ctl(struct nand_chip *this, int cmd,
- unsigned int ctrl)
-{
- char __iomem *nandaddr = this->legacy.IO_ADDR_W;
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, PALMTX_NAND_CLE_VIRT);
- else if (ctrl & NAND_ALE)
- writeb(cmd, PALMTX_NAND_ALE_VIRT);
- else
- writeb(cmd, nandaddr);
-}
-
-static struct mtd_partition palmtx_partition_info[] = {
- [0] = {
- .name = "palmtx-0",
- .offset = 0,
- .size = MTDPART_SIZ_FULL
- },
-};
-
-struct platform_nand_data palmtx_nand_platdata = {
- .chip = {
- .nr_chips = 1,
- .chip_offset = 0,
- .nr_partitions = ARRAY_SIZE(palmtx_partition_info),
- .partitions = palmtx_partition_info,
- .chip_delay = 20,
- },
- .ctrl = {
- .cmd_ctrl = palmtx_nand_cmd_ctl,
- },
-};
-
-static struct resource palmtx_nand_resource[] = {
- [0] = {
- .start = PXA_CS1_PHYS,
- .end = PXA_CS1_PHYS + SZ_1M - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device palmtx_nand = {
- .name = "gen_nand",
- .num_resources = ARRAY_SIZE(palmtx_nand_resource),
- .resource = palmtx_nand_resource,
- .id = -1,
- .dev = {
- .platform_data = &palmtx_nand_platdata,
- }
-};
-
-static void __init palmtx_nand_init(void)
-{
- platform_device_register(&palmtx_nand);
-}
-#else
-static inline void palmtx_nand_init(void) {}
-#endif
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static struct map_desc palmtx_io_desc[] __initdata = {
-{
- .virtual = (unsigned long)PALMTX_PCMCIA_VIRT,
- .pfn = __phys_to_pfn(PALMTX_PCMCIA_PHYS),
- .length = PALMTX_PCMCIA_SIZE,
- .type = MT_DEVICE,
-}, {
- .virtual = (unsigned long)PALMTX_NAND_ALE_VIRT,
- .pfn = __phys_to_pfn(PALMTX_NAND_ALE_PHYS),
- .length = SZ_1M,
- .type = MT_DEVICE,
-}, {
- .virtual = (unsigned long)PALMTX_NAND_CLE_VIRT,
- .pfn = __phys_to_pfn(PALMTX_NAND_CLE_PHYS),
- .length = SZ_1M,
- .type = MT_DEVICE,
-}
-};
-
-static void __init palmtx_map_io(void)
-{
- pxa27x_map_io();
- iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc));
-}
-
-static struct gpiod_lookup_table palmtx_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTX_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTX_SD_READONLY,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTX_SD_POWER,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static void __init palmtx_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- palm27x_mmc_init(&palmtx_mci_gpio_table);
- palm27x_pm_init(PALMTX_STR_BASE);
- palm27x_lcd_init(-1, &palm_320x480_lcd_mode);
- palm27x_udc_init(GPIO_NR_PALMTX_USB_DETECT_N,
- GPIO_NR_PALMTX_USB_PULLUP, 1);
- palm27x_irda_init(GPIO_NR_PALMTX_IR_DISABLE);
- palm27x_ac97_init(PALMTX_BAT_MIN_VOLTAGE, PALMTX_BAT_MAX_VOLTAGE,
- GPIO_NR_PALMTX_EARPHONE_DETECT, 95);
- palm27x_pwm_init(GPIO_NR_PALMTX_BL_POWER, GPIO_NR_PALMTX_LCD_POWER);
- palm27x_power_init(GPIO_NR_PALMTX_POWER_DETECT, -1);
- palm27x_pmic_init();
- palmtx_kpc_init();
- palmtx_keys_init();
- palmtx_nor_init();
- palmtx_nand_init();
-}
-
-MACHINE_START(PALMTX, "Palm T|X")
- .atag_offset = 0x100,
- .map_io = palmtx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = palmtx_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
deleted file mode 100644
index b4a5fe02a0af..000000000000
--- a/arch/arm/mach-pxa/palmz72.c
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware definitions for Palm Zire72
- *
- * Authors:
- * Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>
- * Sergey Lapin <slapin@ossfans.org>
- * Alex Osborne <bobofdoom@gmail.com>
- * Jan Herman <2hp@seznam.cz>
- *
- * Rewrite for mainline:
- * Marek Vasut <marek.vasut@gmail.com>
- *
- * (find more info at www.hackndev.com)
- */
-
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/pda_power.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio.h>
-#include <linux/wm97xx.h>
-#include <linux/power_supply.h>
-#include <linux/platform_data/i2c-gpio.h>
-#include <linux/gpio/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/suspend.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa27x.h"
-#include <mach/audio.h>
-#include "palmz72.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include "udc.h"
-#include <linux/platform_data/asoc-palm27x.h>
-#include "palm27x.h"
-
-#include "pm.h"
-#include <linux/platform_data/media/camera-pxa.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long palmz72_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO14_GPIO, /* SD detect */
- GPIO115_GPIO, /* SD RO */
- GPIO98_GPIO, /* SD power */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO89_AC97_SYSCLK,
- GPIO113_AC97_nRESET,
-
- /* IrDA */
- GPIO49_GPIO, /* ir disable */
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-
- /* PWM */
- GPIO16_PWM0_OUT,
-
- /* USB */
- GPIO15_GPIO, /* usb detect */
- GPIO95_GPIO, /* usb pullup */
-
- /* Matrix keypad */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- GPIO20_GPIO, /* bl power */
- GPIO21_GPIO, /* LCD border switch */
- GPIO22_GPIO, /* LCD border color */
- GPIO96_GPIO, /* lcd power */
-
- /* PXA Camera */
- GPIO81_CIF_DD_0,
- GPIO48_CIF_DD_5,
- GPIO50_CIF_DD_3,
- GPIO51_CIF_DD_2,
- GPIO52_CIF_DD_4,
- GPIO53_CIF_MCLK,
- GPIO54_CIF_PCLK,
- GPIO55_CIF_DD_1,
- GPIO84_CIF_FV,
- GPIO85_CIF_LV,
- GPIO93_CIF_DD_6,
- GPIO108_CIF_DD_7,
-
- GPIO56_GPIO, /* OV9640 Powerdown */
- GPIO57_GPIO, /* OV9640 Reset */
- GPIO91_GPIO, /* OV9640 Power */
-
- /* I2C */
- GPIO117_GPIO, /* I2C_SCL */
- GPIO118_GPIO, /* I2C_SDA */
-
- /* Misc. */
- GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */
- GPIO88_GPIO, /* green led */
- GPIO27_GPIO, /* WM9712 IRQ */
-};
-
-/******************************************************************************
- * GPIO keyboard
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int palmz72_matrix_keys[] = {
- KEY(0, 0, KEY_POWER),
- KEY(0, 1, KEY_F1),
- KEY(0, 2, KEY_ENTER),
-
- KEY(1, 0, KEY_F2),
- KEY(1, 1, KEY_F3),
- KEY(1, 2, KEY_F4),
-
- KEY(2, 0, KEY_UP),
- KEY(2, 2, KEY_DOWN),
-
- KEY(3, 0, KEY_RIGHT),
- KEY(3, 2, KEY_LEFT),
-};
-
-static struct matrix_keymap_data almz72_matrix_keymap_data = {
- .keymap = palmz72_matrix_keys,
- .keymap_size = ARRAY_SIZE(palmz72_matrix_keys),
-};
-
-static struct pxa27x_keypad_platform_data palmz72_keypad_platform_data = {
- .matrix_key_rows = 4,
- .matrix_key_cols = 3,
- .matrix_keymap_data = &almz72_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-
-static void __init palmz72_kpc_init(void)
-{
- pxa_set_keypad_info(&palmz72_keypad_platform_data);
-}
-#else
-static inline void palmz72_kpc_init(void) {}
-#endif
-
-/******************************************************************************
- * LEDs
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-static struct gpio_led gpio_leds[] = {
- {
- .name = "palmz72:green:led",
- .default_trigger = "none",
- .gpio = GPIO_NR_PALMZ72_LED_GREEN,
- },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device palmz72_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &gpio_led_info,
- }
-};
-
-static void __init palmz72_leds_init(void)
-{
- platform_device_register(&palmz72_leds);
-}
-#else
-static inline void palmz72_leds_init(void) {}
-#endif
-
-#ifdef CONFIG_PM
-
-/* We have some black magic here
- * PalmOS ROM on recover expects special struct physical address
- * to be transferred via PSPR. Using this struct PalmOS restores
- * its state after sleep. As for Linux, we need to setup it the
- * same way. More than that, PalmOS ROM changes some values in memory.
- * For now only one location is found, which needs special treatment.
- * Thanks to Alex Osborne, Andrzej Zaborowski, and lots of other people
- * for reading backtraces for me :)
- */
-
-#define PALMZ72_SAVE_DWORD ((unsigned long *)0xc0000050)
-
-static struct palmz72_resume_info palmz72_resume_info = {
- .magic0 = 0xb4e6,
- .magic1 = 1,
-
- /* reset state, MMU off etc */
- .arm_control = 0,
- .aux_control = 0,
- .ttb = 0,
- .domain_access = 0,
- .process_id = 0,
-};
-
-static unsigned long store_ptr;
-
-/* syscore_ops for Palm Zire 72 PM */
-
-static int palmz72_pm_suspend(void)
-{
- /* setup the resume_info struct for the original bootloader */
- palmz72_resume_info.resume_addr = (u32) cpu_resume;
-
- /* Storing memory touched by ROM */
- store_ptr = *PALMZ72_SAVE_DWORD;
-
- /* Setting PSPR to a proper value */
- PSPR = __pa_symbol(&palmz72_resume_info);
-
- return 0;
-}
-
-static void palmz72_pm_resume(void)
-{
- *PALMZ72_SAVE_DWORD = store_ptr;
-}
-
-static struct syscore_ops palmz72_pm_syscore_ops = {
- .suspend = palmz72_pm_suspend,
- .resume = palmz72_pm_resume,
-};
-
-static int __init palmz72_pm_init(void)
-{
- if (machine_is_palmz72()) {
- register_syscore_ops(&palmz72_pm_syscore_ops);
- return 0;
- }
- return -ENODEV;
-}
-
-device_initcall(palmz72_pm_init);
-#endif
-
-static struct gpiod_lookup_table palmz72_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMZ72_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMZ72_SD_RO,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMZ72_SD_POWER_N,
- "power", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void __init palmz72_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config));
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- palm27x_mmc_init(&palmz72_mci_gpio_table);
- palm27x_lcd_init(-1, &palm_320x320_lcd_mode);
- palm27x_udc_init(GPIO_NR_PALMZ72_USB_DETECT_N,
- GPIO_NR_PALMZ72_USB_PULLUP, 0);
- palm27x_irda_init(GPIO_NR_PALMZ72_IR_DISABLE);
- palm27x_ac97_init(PALMZ72_BAT_MIN_VOLTAGE, PALMZ72_BAT_MAX_VOLTAGE,
- -1, 113);
- palm27x_pwm_init(-1, -1);
- palm27x_power_init(-1, -1);
- palm27x_pmic_init();
- palmz72_kpc_init();
- palmz72_leds_init();
-}
-
-MACHINE_START(PALMZ72, "Palm Zire72")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = palmz72_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/palmz72.h b/arch/arm/mach-pxa/palmz72.h
deleted file mode 100644
index 40f3f9987983..000000000000
--- a/arch/arm/mach-pxa/palmz72.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIOs and interrupts for Palm Zire72 Handheld Computer
- *
- * Authors: Alex Osborne <bobofdoom@gmail.com>
- * Jan Herman <2hp@seznam.cz>
- * Sergey Lapin <slapin@ossfans.org>
- */
-
-#ifndef _INCLUDE_PALMZ72_H_
-#define _INCLUDE_PALMZ72_H_
-
-/* Power and control */
-#define GPIO_NR_PALMZ72_GPIO_RESET 1
-#define GPIO_NR_PALMZ72_POWER_DETECT 0
-
-/* SD/MMC */
-#define GPIO_NR_PALMZ72_SD_DETECT_N 14
-#define GPIO_NR_PALMZ72_SD_POWER_N 98
-#define GPIO_NR_PALMZ72_SD_RO 115
-
-/* Touchscreen */
-#define GPIO_NR_PALMZ72_WM9712_IRQ 27
-
-/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
-#define GPIO_NR_PALMZ72_IR_DISABLE 49
-
-/* USB */
-#define GPIO_NR_PALMZ72_USB_DETECT_N 15
-#define GPIO_NR_PALMZ72_USB_PULLUP 95
-
-/* LCD/Backlight */
-#define GPIO_NR_PALMZ72_BL_POWER 20
-#define GPIO_NR_PALMZ72_LCD_POWER 96
-
-/* LED */
-#define GPIO_NR_PALMZ72_LED_GREEN 88
-
-/* Bluetooth */
-#define GPIO_NR_PALMZ72_BT_POWER 17
-#define GPIO_NR_PALMZ72_BT_RESET 83
-
-/* Camera */
-#define GPIO_NR_PALMZ72_CAM_PWDN 56
-#define GPIO_NR_PALMZ72_CAM_RESET 57
-#define GPIO_NR_PALMZ72_CAM_POWER 91
-
-/** Initial values **/
-
-/* Battery */
-#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
-#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
-#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */
-#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */
-#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */
-#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */
-#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */
-
-/* Backlight */
-#define PALMZ72_MAX_INTENSITY 0xFE
-#define PALMZ72_DEFAULT_INTENSITY 0x7E
-#define PALMZ72_LIMIT_MASK 0x7F
-#define PALMZ72_PRESCALER 0x3F
-#define PALMZ72_PERIOD_NS 3500
-
-#ifdef CONFIG_PM
-struct palmz72_resume_info {
- u32 magic0; /* 0x0 */
- u32 magic1; /* 0x4 */
- u32 resume_addr; /* 0x8 */
- u32 pad[11]; /* 0xc..0x37 */
- u32 arm_control; /* 0x38 */
- u32 aux_control; /* 0x3c */
- u32 ttb; /* 0x40 */
- u32 domain_access; /* 0x44 */
- u32 process_id; /* 0x48 */
-};
-#endif
-#endif
-
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
deleted file mode 100644
index 7ff6f0d655c8..000000000000
--- a/arch/arm/mach-pxa/pcm027.c
+++ /dev/null
@@ -1,266 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/pcm027.c
- * Support for the Phytec phyCORE-PXA270 CPU card (aka PCM-027).
- *
- * Refer
- * http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-XScale-PXA270.html
- * for additional hardware info
- *
- * Author: Juergen Kilb
- * Created: April 05, 2005
- * Copyright: Phytec Messtechnik GmbH
- * e-Mail: armlinux@phytec.de
- *
- * based on Intel Mainstone Board
- *
- * Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
- */
-
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/max7301.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/leds.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "pxa27x.h"
-#include "pcm027.h"
-#include "generic.h"
-
-/*
- * ABSTRACT:
- *
- * The PXA270 processor comes with a bunch of hardware on its silicon.
- * Not all of this hardware can be used at the same time and not all
- * is routed to module's connectors. Also it depends on the baseboard, what
- * kind of hardware can be used in which way.
- * -> So this file supports the main devices on the CPU card only!
- * Refer pcm990-baseboard.c how to extend this features to get a full
- * blown system with many common interfaces.
- *
- * The PCM-027 supports the following interfaces through its connectors and
- * will be used in pcm990-baseboard.c:
- *
- * - LCD support
- * - MMC support
- * - IDE/CF card
- * - FFUART
- * - BTUART
- * - IRUART
- * - AC97
- * - SSP
- * - SSP3
- *
- * Claimed GPIOs:
- * GPIO0 -> IRQ input from RTC
- * GPIO2 -> SYS_ENA*)
- * GPIO3 -> PWR_SCL
- * GPIO4 -> PWR_SDA
- * GPIO5 -> PowerCap0*)
- * GPIO6 -> PowerCap1*)
- * GPIO7 -> PowerCap2*)
- * GPIO8 -> PowerCap3*)
- * GPIO15 -> /CS1
- * GPIO20 -> /CS2
- * GPIO21 -> /CS3
- * GPIO33 -> /CS5 network controller select
- * GPIO52 -> IRQ from network controller
- * GPIO78 -> /CS2
- * GPIO80 -> /CS4
- * GPIO90 -> LED0
- * GPIO91 -> LED1
- * GPIO114 -> IRQ from CAN controller
- * GPIO117 -> SCL
- * GPIO118 -> SDA
- *
- * *) CPU internal use only
- */
-
-static unsigned long pcm027_pin_config[] __initdata = {
- /* Chip Selects */
- GPIO20_nSDCS_2,
- GPIO21_nSDCS_3,
- GPIO15_nCS_1,
- GPIO78_nCS_2,
- GPIO80_nCS_4,
- GPIO33_nCS_5, /* Ethernet */
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* GPIO */
- GPIO52_GPIO, /* IRQ from network controller */
-#ifdef CONFIG_LEDS_GPIO
- GPIO90_GPIO, /* PCM027_LED_CPU */
- GPIO91_GPIO, /* PCM027_LED_HEART_BEAT */
-#endif
- GPIO114_GPIO, /* IRQ from CAN controller */
-};
-
-/*
- * SMC91x network controller specific stuff
- */
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = PCM027_ETH_PHYS + 0x300,
- .end = PCM027_ETH_PHYS + PCM027_ETH_SIZE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PCM027_ETH_IRQ,
- .end = PCM027_ETH_IRQ,
- /* note: smc91x's driver doesn't use the trigger bits yet */
- .flags = IORESOURCE_IRQ | PCM027_ETH_IRQ_EDGE,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-/*
- * SPI host and devices
- */
-static struct pxa2xx_spi_controller pxa_ssp_master_info = {
- .num_chipselect = 1,
-};
-
-static struct max7301_platform_data max7301_info = {
- .base = -1,
-};
-
-/* bus_num must match id in pxa2xx_set_spi_info() call */
-static struct spi_board_info spi_board_info[] __initdata = {
- {
- .modalias = "max7301",
- .platform_data = &max7301_info,
- .max_speed_hz = 13000000,
- .bus_num = 1,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-/*
- * NOR flash
- */
-static struct physmap_flash_data pcm027_flash_data = {
- .width = 4,
-};
-
-static struct resource pcm027_flash_resource = {
- .start = PCM027_FLASH_PHYS,
- .end = PCM027_FLASH_PHYS + PCM027_FLASH_SIZE - 1 ,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm027_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &pcm027_flash_data,
- },
- .resource = &pcm027_flash_resource,
- .num_resources = 1,
-};
-
-#ifdef CONFIG_LEDS_GPIO
-
-static struct gpio_led pcm027_led[] = {
- {
- .name = "led0:red", /* FIXME */
- .gpio = PCM027_LED_CPU
- },
- {
- .name = "led1:green", /* FIXME */
- .gpio = PCM027_LED_HEARD_BEAT
- },
-};
-
-static struct gpio_led_platform_data pcm027_led_data = {
- .num_leds = ARRAY_SIZE(pcm027_led),
- .leds = pcm027_led
-};
-
-static struct platform_device pcm027_led_dev = {
- .name = "leds-gpio",
- .id = 0,
- .dev = {
- .platform_data = &pcm027_led_data,
- },
-};
-
-#endif /* CONFIG_LEDS_GPIO */
-
-/*
- * declare the available device resources on this board
- */
-static struct platform_device *devices[] __initdata = {
- &smc91x_device,
- &pcm027_flash,
-#ifdef CONFIG_LEDS_GPIO
- &pcm027_led_dev
-#endif
-};
-
-/*
- * pcm027_init - breath some life into the board
- */
-static void __init pcm027_init(void)
-{
- /* system bus arbiter setting
- * - Core_Park
- * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
- */
- ARB_CNTRL = ARB_CORE_PARK | 0x234;
-
- pxa2xx_mfp_config(pcm027_pin_config, ARRAY_SIZE(pcm027_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- /* at last call the baseboard to initialize itself */
-#ifdef CONFIG_MACH_PCM990_BASEBOARD
- pcm990_baseboard_init();
-#endif
-
- pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
- spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-}
-
-static void __init pcm027_map_io(void)
-{
- pxa27x_map_io();
-
- /* initialize sleep mode regs (wake-up sources, etc) */
- PGSR0 = 0x01308000;
- PGSR1 = 0x00CF0002;
- PGSR2 = 0x0E294000;
- PGSR3 = 0x0000C000;
- PWER = 0x40000000 | PWER_GPIO0 | PWER_GPIO1;
- PRER = 0x00000000;
- PFER = 0x00000003;
-}
-
-MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
- /* Maintainer: Pengutronix */
- .atag_offset = 0x100,
- .map_io = pcm027_map_io,
- .nr_irqs = PCM027_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = pcm027_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm027.h b/arch/arm/mach-pxa/pcm027.h
deleted file mode 100644
index 0c4ab636ce4e..000000000000
--- a/arch/arm/mach-pxa/pcm027.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-pxa/include/mach/pcm027.h
- *
- * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
- * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
- */
-
-/*
- * Definitions of CPU card resources only
- */
-
-#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
-
-/* phyCORE-PXA270 (PCM027) Interrupts */
-#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
-#define PCM027_BTDET_IRQ PCM027_IRQ(0)
-#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
-#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
-#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
-
-#define PCM027_NR_IRQS (IRQ_BOARD_START + 32)
-
-/* I2C RTC */
-#define PCM027_RTC_IRQ_GPIO 0
-#define PCM027_RTC_IRQ PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO)
-#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
-#define ADR_PCM027_RTC 0x51 /* I2C address */
-
-/* I2C EEPROM */
-#define ADR_PCM027_EEPROM 0x54 /* I2C address */
-
-/* Ethernet chip (SMSC91C111) */
-#define PCM027_ETH_IRQ_GPIO 52
-#define PCM027_ETH_IRQ PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO)
-#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-#define PCM027_ETH_PHYS PXA_CS5_PHYS
-#define PCM027_ETH_SIZE (1*1024*1024)
-
-/* CAN controller SJA1000 (unsupported yet) */
-#define PCM027_CAN_IRQ_GPIO 114
-#define PCM027_CAN_IRQ PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO)
-#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
-#define PCM027_CAN_PHYS 0x22000000
-#define PCM027_CAN_SIZE 0x100
-
-/* SPI GPIO expander (unsupported yet) */
-#define PCM027_EGPIO_IRQ_GPIO 27
-#define PCM027_EGPIO_IRQ PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO)
-#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
-#define PCM027_EGPIO_CS 24
-/*
- * TODO: Switch this pin from dedicated usage to GPIO if
- * more than the MAX7301 device is connected to this SPI bus
- */
-#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD
-
-/* Flash memory */
-#define PCM027_FLASH_PHYS 0x00000000
-#define PCM027_FLASH_SIZE 0x02000000
-
-/* onboard LEDs connected to GPIO */
-#define PCM027_LED_CPU 90
-#define PCM027_LED_HEARD_BEAT 91
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
- * TODO: Add your own basebaord init function and call it from
- * inside pcm027_init(). This example here is for the developmen board.
- * Refer pcm990-baseboard.c
- */
-extern void pcm990_baseboard_init(void);
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
deleted file mode 100644
index 8dfcc366d0fe..000000000000
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ /dev/null
@@ -1,408 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-pxa/pcm990-baseboard.c
- * Support for the Phytec phyCORE-PXA270 Development Platform (PCM-990).
- *
- * Refer
- * http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-XScale-PXA270.html
- * for additional hardware info
- *
- * Author: Juergen Kilb
- * Created: April 05, 2005
- * Copyright: Phytec Messtechnik GmbH
- * e-Mail: armlinux@phytec.de
- *
- * based on Intel Mainstone Board
- *
- * Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
- */
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-
-#include <asm/mach/map.h>
-#include "pxa27x.h"
-#include <mach/audio.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include "pcm990_baseboard.h"
-#include <linux/platform_data/video-pxafb.h>
-
-#include "devices.h"
-#include "generic.h"
-
-static unsigned long pcm990_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO112_MMC_CMD,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- /* USB */
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
- /* PWM0 */
- GPIO16_PWM0_OUT,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-};
-
-static void __iomem *pcm990_cpld_base;
-
-static u8 pcm990_cpld_readb(unsigned int reg)
-{
- return readb(pcm990_cpld_base + reg);
-}
-
-static void pcm990_cpld_writeb(u8 value, unsigned int reg)
-{
- writeb(value, pcm990_cpld_base + reg);
-}
-
-/*
- * pcm990_lcd_power - control power supply to the LCD
- * @on: 0 = switch off, 1 = switch on
- *
- * Called by the pxafb driver
- */
-#ifndef CONFIG_PCM990_DISPLAY_NONE
-static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
-{
- if (on) {
- /* enable LCD-Latches
- * power on LCD
- */
- pcm990_cpld_writeb(PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON,
- PCM990_CTRL_REG3);
- } else {
- /* disable LCD-Latches
- * power off LCD
- */
- pcm990_cpld_writeb(0, PCM990_CTRL_REG3);
- }
-}
-#endif
-
-#if defined(CONFIG_PCM990_DISPLAY_SHARP)
-static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
- .pixclock = 28000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 20,
- .left_margin = 103,
- .right_margin = 47,
- .vsync_len = 6,
- .upper_margin = 28,
- .lower_margin = 5,
- .sync = 0,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info pcm990_fbinfo __initdata = {
- .modes = &fb_info_sharp_lq084v1dg21,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
- .pxafb_lcd_power = pcm990_lcd_power,
-};
-#elif defined(CONFIG_PCM990_DISPLAY_NEC)
-struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
- .pixclock = 39720,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 32,
- .left_margin = 16,
- .right_margin = 48,
- .vsync_len = 2,
- .upper_margin = 12,
- .lower_margin = 17,
- .sync = 0,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info pcm990_fbinfo __initdata = {
- .modes = &fb_info_nec_nl6448bc20_18d,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
- .pxafb_lcd_power = pcm990_lcd_power,
-};
-#endif
-
-static struct pwm_lookup pcm990_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data pcm990_backlight_data = {
- .max_brightness = 1023,
- .dft_brightness = 1023,
-};
-
-static struct platform_device pcm990_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm0.dev,
- .platform_data = &pcm990_backlight_data,
- },
-};
-
-/*
- * The PCM-990 development baseboard uses PCM-027's hardware in the
- * following way:
- *
- * - LCD support is in use
- * - GPIO16 is output for back light on/off with PWM
- * - GPIO58 ... GPIO73 are outputs for display data
- * - GPIO74 is output output for LCDFCLK
- * - GPIO75 is output for LCDLCLK
- * - GPIO76 is output for LCDPCLK
- * - GPIO77 is output for LCDBIAS
- * - MMC support is in use
- * - GPIO32 is output for MMCCLK
- * - GPIO92 is MMDAT0
- * - GPIO109 is MMDAT1
- * - GPIO110 is MMCS0
- * - GPIO111 is MMCS1
- * - GPIO112 is MMCMD
- * - IDE/CF card is in use
- * - GPIO48 is output /POE
- * - GPIO49 is output /PWE
- * - GPIO50 is output /PIOR
- * - GPIO51 is output /PIOW
- * - GPIO54 is output /PCE2
- * - GPIO55 is output /PREG
- * - GPIO56 is input /PWAIT
- * - GPIO57 is output /PIOS16
- * - GPIO79 is output PSKTSEL
- * - GPIO85 is output /PCE1
- * - FFUART is in use
- * - GPIO34 is input FFRXD
- * - GPIO35 is input FFCTS
- * - GPIO36 is input FFDCD
- * - GPIO37 is input FFDSR
- * - GPIO38 is input FFRI
- * - GPIO39 is output FFTXD
- * - GPIO40 is output FFDTR
- * - GPIO41 is output FFRTS
- * - BTUART is in use
- * - GPIO42 is input BTRXD
- * - GPIO43 is output BTTXD
- * - GPIO44 is input BTCTS
- * - GPIO45 is output BTRTS
- * - IRUART is in use
- * - GPIO46 is input STDRXD
- * - GPIO47 is output STDTXD
- * - AC97 is in use*)
- * - GPIO28 is input AC97CLK
- * - GPIO29 is input AC97DatIn
- * - GPIO30 is output AC97DatO
- * - GPIO31 is output AC97SYNC
- * - GPIO113 is output AC97_RESET
- * - SSP is in use
- * - GPIO23 is output SSPSCLK
- * - GPIO24 is output chip select to Max7301
- * - GPIO25 is output SSPTXD
- * - GPIO26 is input SSPRXD
- * - GPIO27 is input for Max7301 IRQ
- * - GPIO53 is input SSPSYSCLK
- * - SSP3 is in use
- * - GPIO81 is output SSPTXD3
- * - GPIO82 is input SSPRXD3
- * - GPIO83 is output SSPSFRM
- * - GPIO84 is output SSPCLK3
- *
- * Otherwise claimed GPIOs:
- * GPIO1 -> IRQ from user switch
- * GPIO9 -> IRQ from power management
- * GPIO10 -> IRQ from WML9712 AC97 controller
- * GPIO11 -> IRQ from IDE controller
- * GPIO12 -> IRQ from CF controller
- * GPIO13 -> IRQ from CF controller
- * GPIO14 -> GPIO free
- * GPIO15 -> /CS1 selects baseboard's Control CPLD (U7, 16 bit wide data path)
- * GPIO19 -> GPIO free
- * GPIO20 -> /SDCS2
- * GPIO21 -> /CS3 PC card socket select
- * GPIO33 -> /CS5 network controller select
- * GPIO78 -> /CS2 (16 bit wide data path)
- * GPIO80 -> /CS4 (16 bit wide data path)
- * GPIO86 -> GPIO free
- * GPIO87 -> GPIO free
- * GPIO90 -> LED0 on CPU module
- * GPIO91 -> LED1 on CPI module
- * GPIO117 -> SCL
- * GPIO118 -> SDA
- */
-
-static unsigned long pcm990_irq_enabled;
-
-static void pcm990_mask_ack_irq(struct irq_data *d)
-{
- int pcm990_irq = (d->irq - PCM027_IRQ(0));
-
- pcm990_irq_enabled &= ~(1 << pcm990_irq);
-
- pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
-}
-
-static void pcm990_unmask_irq(struct irq_data *d)
-{
- int pcm990_irq = (d->irq - PCM027_IRQ(0));
- u8 val;
-
- /* the irq can be acknowledged only if deasserted, so it's done here */
-
- pcm990_irq_enabled |= (1 << pcm990_irq);
-
- val = pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
- val |= 1 << pcm990_irq;
- pcm990_cpld_writeb(val, PCM990_CTRL_INTSETCLR);
-
- pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
-}
-
-static struct irq_chip pcm990_irq_chip = {
- .irq_mask_ack = pcm990_mask_ack_irq,
- .irq_unmask = pcm990_unmask_irq,
-};
-
-static void pcm990_irq_handler(struct irq_desc *desc)
-{
- unsigned int irq;
- unsigned long pending;
-
- pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
- pending &= pcm990_irq_enabled;
-
- do {
- /* clear our parent IRQ */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
- if (likely(pending)) {
- irq = PCM027_IRQ(0) + __ffs(pending);
- generic_handle_irq(irq);
- }
- pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
- pending &= pcm990_irq_enabled;
- } while (pending);
-}
-
-static void __init pcm990_init_irq(void)
-{
- int irq;
-
- /* setup extra PCM990 irqs */
- for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
- irq_set_chip_and_handler(irq, &pcm990_irq_chip,
- handle_level_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-
- /* disable all Interrupts */
- pcm990_cpld_writeb(0x0, PCM990_CTRL_INTMSKENA);
- pcm990_cpld_writeb(0xff, PCM990_CTRL_INTSETCLR);
-
- irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
- irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
-}
-
-static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
- void *data)
-{
- int err;
-
- err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, 0,
- "MMC card detect", data);
- if (err)
- printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
- "card detect IRQ\n");
-
- return err;
-}
-
-static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
-{
- struct pxamci_platform_data *p_d = dev->platform_data;
- u8 val;
-
- val = pcm990_cpld_readb(PCM990_CTRL_REG5);
-
- if ((1 << vdd) & p_d->ocr_mask)
- val |= PCM990_CTRL_MMC2PWR;
- else
- val &= ~PCM990_CTRL_MMC2PWR;
-
- pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
- return 0;
-}
-
-static void pcm990_mci_exit(struct device *dev, void *data)
-{
- free_irq(PCM027_MMCDET_IRQ, data);
-}
-
-#define MSECS_PER_JIFFY (1000/HZ)
-
-static struct pxamci_platform_data pcm990_mci_platform_data = {
- .detect_delay_ms = 250,
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .init = pcm990_mci_init,
- .setpower = pcm990_mci_setpower,
- .exit = pcm990_mci_exit,
-};
-
-static struct pxaohci_platform_data pcm990_ohci_platform_data = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
- .power_on_delay = 10,
-};
-
-/*
- * system init for baseboard usage. Will be called by pcm027 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init pcm990_baseboard_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_pin_config));
-
- pcm990_cpld_base = ioremap(PCM990_CTRL_PHYS, PCM990_CTRL_SIZE);
- if (!pcm990_cpld_base) {
- pr_err("pcm990: failed to ioremap cpld\n");
- return;
- }
-
- /* register CPLD's IRQ controller */
- pcm990_init_irq();
-
-#ifndef CONFIG_PCM990_DISPLAY_NONE
- pxa_set_fb_info(NULL, &pcm990_fbinfo);
-#endif
- pwm_add_table(pcm990_pwm_lookup, ARRAY_SIZE(pcm990_pwm_lookup));
- platform_device_register(&pcm990_backlight_device);
-
- /* MMC */
- pxa_set_mci_info(&pcm990_mci_platform_data);
-
- /* USB host */
- pxa_set_ohci_info(&pcm990_ohci_platform_data);
-
- pxa_set_i2c_info(NULL);
- pxa_set_ac97_info(NULL);
-
- printk(KERN_INFO "PCM-990 Evaluation baseboard initialized\n");
-}
diff --git a/arch/arm/mach-pxa/pcm990_baseboard.h b/arch/arm/mach-pxa/pcm990_baseboard.h
deleted file mode 100644
index 5be11d1b7019..000000000000
--- a/arch/arm/mach-pxa/pcm990_baseboard.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
- *
- * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
- * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
- */
-
-#include "pcm027.h"
-#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
-
-/*
- * definitions relevant only when the PCM-990
- * development base board is in use
- */
-
-/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
-#define PCM990_CTRL_INT_IRQ_GPIO 9
-#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO)
-#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
-#define PCM990_CTRL_SIZE (1*1024*1024)
-
-#define PCM990_CTRL_PWR_IRQ_GPIO 14
-#define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO)
-#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-
-/* visible CPLD (U7) registers */
-#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
-#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
-#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
-#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
-
-#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
-#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
-#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
-#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
-
-#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
-#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
-#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
-#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
-
-#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
-#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
-#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
-#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
-#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
-
-#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
-#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
-
-#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
-#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
-#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
-#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
-#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
-
-#define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */
-#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
-#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
-#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
-#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
-
-#define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */
-#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
-#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
-#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
-#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
-
-#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
-#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
-#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
-#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
-#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
-
-#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
-#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
-#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
-#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
-
-#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
-#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
-#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
-
-#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
-#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
-#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
-#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
-#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
-
-/*
- * IDE
- */
-#define PCM990_IDE_IRQ_GPIO 13
-#define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO)
-#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
-#define PCM990_IDE_PLD_BASE 0xee000000
-#define PCM990_IDE_PLD_SIZE (1*1024*1024)
-
-/* visible CPLD (U6) registers */
-#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
-#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
-#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
-
-#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
-#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
-#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
-#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
-
-#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
-#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
-#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
-#define PCM990_IDE_RDY 0x0008 /* RDY */
-
-#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
-#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
-#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
-#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
-
-#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
-#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
-#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
-#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
-
-#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
-#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
-
-/*
- * Compact Flash
- */
-#define PCM990_CF_IRQ_GPIO 11
-#define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO)
-#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-
-#define PCM990_CF_CD_GPIO 12
-#define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO)
-#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
-
-#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
-
-/* visible CPLD (U6) registers */
-#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
-#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
-#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
-#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
-#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
-
-#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
-#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
-#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
-
-#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
-#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
-#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
-#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
-
-#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
-#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
-#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
-#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
-#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
-
-#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
-#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
-#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
-#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
-#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
-
-#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
-#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
-#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
-#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
-#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
-
-#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
-#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
-#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
-
-/*
- * Wolfson AC97 Touch
- */
-#define PCM990_AC97_IRQ_GPIO 10
-#define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO)
-#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING
-
-/*
- * MMC phyCORE
- */
-#define PCM990_MMC0_IRQ_GPIO 9
-#define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO)
-#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
-
-/*
- * USB phyCore
- */
-#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
-#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index f2237f471750..c63e854921ea 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -51,8 +51,6 @@ int pxa_pm_enter(suspend_state_t state)
/* if invalid, display message and wait for a hardware reset */
if (checksum != sleep_save_checksum) {
- lubbock_set_hexled(0xbadbadc5);
-
while (1)
pxa_cpu_pm_fns->enter(state);
}
diff --git a/arch/arm/mach-pxa/pm.h b/arch/arm/mach-pxa/pm.h
index 00ea3529e30e..a16fa140883c 100644
--- a/arch/arm/mach-pxa/pm.h
+++ b/arch/arm/mach-pxa/pm.h
@@ -27,13 +27,3 @@ extern void pxa_pm_finish(void);
extern const char pm_enter_standby_start[], pm_enter_standby_end[];
extern int pxa3xx_finish_suspend(unsigned long);
-
-/* NOTE: this is for PM debugging on Lubbock, it's really a big
- * ugly, but let's keep the crap minimum here, instead of direct
- * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c
- */
-#ifdef CONFIG_ARCH_LUBBOCK
-extern void lubbock_set_hexled(uint32_t value);
-#else
-#define lubbock_set_hexled(x)
-#endif
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
deleted file mode 100644
index 58cfa434afde..000000000000
--- a/arch/arm/mach-pxa/poodle.c
+++ /dev/null
@@ -1,475 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/poodle.c
- *
- * Support for the SHARP Poodle Board.
- *
- * Based on:
- * linux/arch/arm/mach-pxa/lubbock.c Author: Nicolas Pitre
- *
- * Change Log
- * 12-Dec-2002 Sharp Corporation for Poodle
- * John Lenz <lenz@cs.wisc.edu> updates to 2.6
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/fb.h>
-#include <linux/pm.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/regulator/machine.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/mtd/sharpsl.h>
-#include <linux/memblock.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/setup.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include "pxa25x.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include "udc.h"
-#include <linux/platform_data/irda-pxaficp.h>
-#include <mach/poodle.h>
-#include <linux/platform_data/video-pxafb.h>
-
-#include <asm/hardware/scoop.h>
-#include <asm/hardware/locomo.h>
-#include <asm/mach/sharpsl_param.h>
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned long poodle_pin_config[] __initdata = {
- /* I/O */
- GPIO79_nCS_3,
- GPIO80_nCS_4,
- GPIO18_RDY,
-
- /* Clock */
- GPIO12_32KHz,
-
- /* SSP1 */
- GPIO23_SSP1_SCLK,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
- GPIO24_GPIO, /* POODLE_GPIO_TP_CS - SFRM as chip select */
-
- /* I2S */
- GPIO28_I2S_BITCLK_OUT,
- GPIO29_I2S_SDATA_IN,
- GPIO30_I2S_SDATA_OUT,
- GPIO31_I2S_SYNC,
- GPIO32_I2S_SYSCLK,
-
- /* Infra-Red */
- GPIO47_FICP_TXD,
- GPIO46_FICP_RXD,
-
- /* FFUART */
- GPIO40_FFUART_DTR,
- GPIO41_FFUART_RTS,
- GPIO39_FFUART_TXD,
- GPIO37_FFUART_DSR,
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* PC Card */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO8_MMC_CS0,
-
- /* GPIO */
- GPIO9_GPIO, /* POODLE_GPIO_nSD_DETECT */
- GPIO7_GPIO, /* POODLE_GPIO_nSD_WP */
- GPIO3_GPIO, /* POODLE_GPIO_SD_PWR */
- GPIO33_GPIO, /* POODLE_GPIO_SD_PWR1 */
-
- GPIO20_GPIO, /* POODLE_GPIO_USB_PULLUP */
- GPIO22_GPIO, /* POODLE_GPIO_IR_ON */
-};
-
-static struct resource poodle_scoop_resources[] = {
- [0] = {
- .start = 0x10800000,
- .end = 0x10800fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct scoop_config poodle_scoop_setup = {
- .io_dir = POODLE_SCOOP_IO_DIR,
- .io_out = POODLE_SCOOP_IO_OUT,
- .gpio_base = POODLE_SCOOP_GPIO_BASE,
-};
-
-struct platform_device poodle_scoop_device = {
- .name = "sharp-scoop",
- .id = -1,
- .dev = {
- .platform_data = &poodle_scoop_setup,
- },
- .num_resources = ARRAY_SIZE(poodle_scoop_resources),
- .resource = poodle_scoop_resources,
-};
-
-static struct scoop_pcmcia_dev poodle_pcmcia_scoop[] = {
-{
- .dev = &poodle_scoop_device.dev,
- .irq = POODLE_IRQ_GPIO_CF_IRQ,
- .cd_irq = POODLE_IRQ_GPIO_CF_CD,
- .cd_irq_str = "PCMCIA0 CD",
-},
-};
-
-static struct scoop_pcmcia_config poodle_pcmcia_config = {
- .devs = &poodle_pcmcia_scoop[0],
- .num_devs = 1,
-};
-
-EXPORT_SYMBOL(poodle_scoop_device);
-
-
-static struct platform_device poodle_audio_device = {
- .name = "poodle-audio",
- .id = -1,
-};
-
-/* LoCoMo device */
-static struct resource locomo_resources[] = {
- [0] = {
- .start = 0x10000000,
- .end = 0x10001fff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(10),
- .end = PXA_GPIO_TO_IRQ(10),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct locomo_platform_data locomo_info = {
- .irq_base = IRQ_BOARD_START,
-};
-
-struct platform_device poodle_locomo_device = {
- .name = "locomo",
- .id = 0,
- .num_resources = ARRAY_SIZE(locomo_resources),
- .resource = locomo_resources,
- .dev = {
- .platform_data = &locomo_info,
- },
-};
-
-EXPORT_SYMBOL(poodle_locomo_device);
-
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_controller poodle_spi_info = {
- .num_chipselect = 1,
-};
-
-static struct gpiod_lookup_table poodle_spi_gpio_table = {
- .dev_id = "pxa2xx-spi.1",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", POODLE_GPIO_TP_CS, "cs", 0, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct ads7846_platform_data poodle_ads7846_info = {
- .model = 7846,
- .vref_delay_usecs = 100,
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .gpio_pendown = POODLE_GPIO_TP_INT,
-};
-
-static struct spi_board_info poodle_spi_devices[] = {
- {
- .modalias = "ads7846",
- .max_speed_hz = 10000,
- .bus_num = 1,
- .platform_data = &poodle_ads7846_info,
- .irq = PXA_GPIO_TO_IRQ(POODLE_GPIO_TP_INT),
- },
-};
-
-static void __init poodle_init_spi(void)
-{
- gpiod_add_lookup_table(&poodle_spi_gpio_table);
- pxa2xx_set_spi_info(1, &poodle_spi_info);
- spi_register_board_info(ARRAY_AND_SIZE(poodle_spi_devices));
-}
-#else
-static inline void poodle_init_spi(void) {}
-#endif
-
-/*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
- */
-static int poodle_mci_init(struct device *dev, irq_handler_t poodle_detect_int, void *data)
-{
- int err;
-
- err = gpio_request(POODLE_GPIO_SD_PWR, "SD_PWR");
- if (err)
- goto err_free_2;
-
- err = gpio_request(POODLE_GPIO_SD_PWR1, "SD_PWR1");
- if (err)
- goto err_free_3;
-
- gpio_direction_output(POODLE_GPIO_SD_PWR, 0);
- gpio_direction_output(POODLE_GPIO_SD_PWR1, 0);
-
- return 0;
-
-err_free_3:
- gpio_free(POODLE_GPIO_SD_PWR);
-err_free_2:
- return err;
-}
-
-static int poodle_mci_setpower(struct device *dev, unsigned int vdd)
-{
- struct pxamci_platform_data* p_d = dev->platform_data;
-
- if ((1 << vdd) & p_d->ocr_mask) {
- gpio_set_value(POODLE_GPIO_SD_PWR, 1);
- mdelay(2);
- gpio_set_value(POODLE_GPIO_SD_PWR1, 1);
- } else {
- gpio_set_value(POODLE_GPIO_SD_PWR1, 0);
- gpio_set_value(POODLE_GPIO_SD_PWR, 0);
- }
-
- return 0;
-}
-
-static void poodle_mci_exit(struct device *dev, void *data)
-{
- gpio_free(POODLE_GPIO_SD_PWR1);
- gpio_free(POODLE_GPIO_SD_PWR);
-}
-
-static struct pxamci_platform_data poodle_mci_platform_data = {
- .detect_delay_ms = 250,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .init = poodle_mci_init,
- .setpower = poodle_mci_setpower,
- .exit = poodle_mci_exit,
-};
-
-static struct gpiod_lookup_table poodle_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", POODLE_GPIO_nSD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", POODLE_GPIO_nSD_WP,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/*
- * Irda
- */
-static struct pxaficp_platform_data poodle_ficp_platform_data = {
- .gpio_pwdown = POODLE_GPIO_IR_ON,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-
-/*
- * USB Device Controller
- */
-static struct pxa2xx_udc_mach_info udc_info __initdata = {
- /* no connect GPIO; poodle can't tell connection status */
- .gpio_pullup = POODLE_GPIO_USB_PULLUP,
-};
-
-
-/* PXAFB device */
-static struct pxafb_mode_info poodle_fb_mode = {
- .pixclock = 144700,
- .xres = 320,
- .yres = 240,
- .bpp = 16,
- .hsync_len = 7,
- .left_margin = 11,
- .right_margin = 30,
- .vsync_len = 2,
- .upper_margin = 2,
- .lower_margin = 0,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info poodle_fb_info = {
- .modes = &poodle_fb_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP,
-};
-
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr sharpsl_bbt = {
- .options = 0,
- .offs = 4,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-static const char * const probes[] = {
- "cmdlinepart",
- "ofpart",
- "sharpslpart",
- NULL,
-};
-
-static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
- .badblock_pattern = &sharpsl_bbt,
- .part_parsers = probes,
-};
-
-static struct resource sharpsl_nand_resources[] = {
- {
- .start = 0x0C000000,
- .end = 0x0C000FFF,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device sharpsl_nand_device = {
- .name = "sharpsl-nand",
- .id = -1,
- .resource = sharpsl_nand_resources,
- .num_resources = ARRAY_SIZE(sharpsl_nand_resources),
- .dev.platform_data = &sharpsl_nand_platform_data,
-};
-
-static struct mtd_partition sharpsl_rom_parts[] = {
- {
- .name ="Boot PROM Filesystem",
- .offset = 0x00120000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data sharpsl_rom_data = {
- .width = 2,
- .nr_parts = ARRAY_SIZE(sharpsl_rom_parts),
- .parts = sharpsl_rom_parts,
-};
-
-static struct resource sharpsl_rom_resources[] = {
- {
- .start = 0x00000000,
- .end = 0x007fffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device sharpsl_rom_device = {
- .name = "physmap-flash",
- .id = -1,
- .resource = sharpsl_rom_resources,
- .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
- .dev.platform_data = &sharpsl_rom_data,
-};
-
-static struct platform_device *devices[] __initdata = {
- &poodle_locomo_device,
- &poodle_scoop_device,
- &poodle_audio_device,
- &sharpsl_nand_device,
- &sharpsl_rom_device,
-};
-
-static struct i2c_board_info __initdata poodle_i2c_devices[] = {
- { I2C_BOARD_INFO("wm8731", 0x1b) },
-};
-
-static void poodle_poweroff(void)
-{
- pxa_restart(REBOOT_HARD, NULL);
-}
-
-static void __init poodle_init(void)
-{
- int ret = 0;
-
- pm_power_off = poodle_poweroff;
-
- PCFR |= PCFR_OPDE;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(poodle_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- platform_scoop_config = &poodle_pcmcia_config;
-
- ret = platform_add_devices(devices, ARRAY_SIZE(devices));
- if (ret)
- pr_warn("poodle: Unable to register LoCoMo device\n");
-
- pxa_set_fb_info(&poodle_locomo_device.dev, &poodle_fb_info);
- pxa_set_udc_info(&udc_info);
- gpiod_add_lookup_table(&poodle_mci_gpio_table);
- pxa_set_mci_info(&poodle_mci_platform_data);
- pxa_set_ficp_info(&poodle_ficp_platform_data);
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(poodle_i2c_devices));
- poodle_init_spi();
- regulator_has_full_constraints();
-}
-
-static void __init fixup_poodle(struct tag *tags, char **cmdline)
-{
- sharpsl_save_param();
- memblock_add(0xa0000000, SZ_32M);
-}
-
-MACHINE_START(POODLE, "SHARP Poodle")
- .fixup = fixup_poodle,
- .map_io = pxa25x_map_io,
- .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = poodle_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
index d32d5c8e966f..5e5d543fdf46 100644
--- a/arch/arm/mach-pxa/pxa-dt.c
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -11,7 +11,7 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "generic.h"
diff --git a/arch/arm/mach-pxa/pxa-regs.h b/arch/arm/mach-pxa/pxa-regs.h
new file mode 100644
index 000000000000..ba5120c06b8a
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa-regs.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Author: Nicolas Pitre
+ * Created: Jun 15, 2001
+ * Copyright: MontaVista Software Inc.
+ */
+#ifndef __ASM_MACH_PXA_REGS_H
+#define __ASM_MACH_PXA_REGS_H
+
+/*
+ * Workarounds for at least 2 errata so far require this.
+ * The mapping is set in mach-pxa/generic.c.
+ */
+#define UNCACHED_PHYS_0 0xfe000000
+#define UNCACHED_PHYS_0_SIZE 0x00100000
+
+/*
+ * Intel PXA2xx internal register mapping:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
+ * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
+ * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
+ * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
+ *
+ * Note that not all PXA2xx chips implement all those addresses, and the
+ * kernel only maps the minimum needed range of this mapping.
+ */
+#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
+#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
+
+#ifndef __ASSEMBLY__
+# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
+
+/* With indexed regs we don't want to feed the index through io_p2v()
+ especially if it is a variable, otherwise horrible code will result. */
+# define __REG2(x,y) \
+ (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
+
+# define __PREG(x) (io_v2p((u32)&(x)))
+
+#else
+
+# define __REG(x) io_p2v(x)
+# define __PREG(x) io_v2p(x)
+
+#endif
+
+
+#endif
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 678641ab46e5..1b83be181bab 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -26,16 +26,16 @@
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/platform_data/mmp_dma.h>
+#include <linux/soc/pxa/cpu.h>
#include <asm/mach/map.h>
#include <asm/suspend.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "pxa25x.h"
-#include <mach/reset.h>
+#include "reset.h"
#include "pm.h"
-#include <mach/dma.h>
-#include <mach/smemc.h>
+#include "addr-map.h"
+#include "smemc.h"
#include "generic.h"
#include "devices.h"
@@ -145,13 +145,6 @@ void __init pxa25x_init_irq(void)
pxa_init_irq(32, pxa25x_set_wake);
}
-#ifdef CONFIG_CPU_PXA26x
-void __init pxa26x_init_irq(void)
-{
- pxa_init_irq(32, pxa25x_set_wake);
-}
-#endif
-
static int __init __init
pxa25x_dt_init_irq(struct device_node *node, struct device_node *parent)
{
@@ -240,7 +233,7 @@ static int __init pxa25x_init(void)
if (cpu_is_pxa25x()) {
- reset_status = RCSR;
+ pxa_register_wdt(RCSR);
pxa25x_init_pm();
diff --git a/arch/arm/mach-pxa/pxa25x.h b/arch/arm/mach-pxa/pxa25x.h
index b58d0fbdb4db..eaaa87666324 100644
--- a/arch/arm/mach-pxa/pxa25x.h
+++ b/arch/arm/mach-pxa/pxa25x.h
@@ -2,9 +2,9 @@
#ifndef __MACH_PXA25x_H
#define __MACH_PXA25x_H
-#include <mach/hardware.h>
-#include <mach/pxa2xx-regs.h>
+#include "addr-map.h"
+#include "pxa2xx-regs.h"
#include "mfp-pxa25x.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#endif /* __MACH_PXA25x_H */
diff --git a/arch/arm/mach-pxa/pxa27x-udc.h b/arch/arm/mach-pxa/pxa27x-udc.h
index faf73804697f..2d3df3b1cb68 100644
--- a/arch/arm/mach-pxa/pxa27x-udc.h
+++ b/arch/arm/mach-pxa/pxa27x-udc.h
@@ -2,6 +2,8 @@
#ifndef _ASM_ARCH_PXA27X_UDC_H
#define _ASM_ARCH_PXA27X_UDC_H
+#include "pxa-regs.h"
+
#ifdef _ASM_ARCH_PXA25X_UDC_H
#error You cannot include both PXA25x and PXA27x UDC support
#endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index f0ba7ed24cb6..4135ba2877c4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -23,18 +23,18 @@
#include <linux/irq.h>
#include <linux/platform_data/i2c-pxa.h>
#include <linux/platform_data/mmp_dma.h>
+#include <linux/soc/pxa/cpu.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/suspend.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "pxa27x.h"
-#include <mach/reset.h>
+#include "reset.h"
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include "pm.h"
-#include <mach/dma.h>
-#include <mach/smemc.h>
+#include "addr-map.h"
+#include "smemc.h"
#include "generic.h"
#include "devices.h"
@@ -85,18 +85,6 @@ EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
*/
static unsigned int pwrmode = PWRMODE_SLEEP;
-int pxa27x_set_pwrmode(unsigned int mode)
-{
- switch (mode) {
- case PWRMODE_SLEEP:
- case PWRMODE_DEEPSLEEP:
- pwrmode = mode;
- return 0;
- }
-
- return -EINVAL;
-}
-
/*
* List of global PXA peripheral registers to preserve.
* More ones like CP and general purpose register values are preserved
@@ -109,7 +97,7 @@ enum {
SLEEP_SAVE_COUNT
};
-void pxa27x_cpu_pm_save(unsigned long *sleep_save)
+static void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
SAVE(PCFR);
@@ -117,7 +105,7 @@ void pxa27x_cpu_pm_save(unsigned long *sleep_save)
SAVE(PSTR);
}
-void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
+static void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
RESTORE(PCFR);
@@ -127,14 +115,18 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
RESTORE(PSTR);
}
-void pxa27x_cpu_pm_enter(suspend_state_t state)
+static void pxa27x_cpu_pm_enter(suspend_state_t state)
{
extern void pxa_cpu_standby(void);
#ifndef CONFIG_IWMMXT
u64 acc0;
+#ifndef CONFIG_AS_IS_LLVM
asm volatile(".arch_extension xscale\n\t"
"mra %Q0, %R0, acc0" : "=r" (acc0));
+#else
+ asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
+#endif
#endif
/* ensure voltage-change sequencer not initiated, which hangs */
@@ -153,8 +145,12 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
case PM_SUSPEND_MEM:
cpu_suspend(pwrmode, pxa27x_finish_suspend);
#ifndef CONFIG_IWMMXT
+#ifndef CONFIG_AS_IS_LLVM
asm volatile(".arch_extension xscale\n\t"
"mar acc0, %Q0, %R0" : "=r" (acc0));
+#else
+ asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
+#endif
#endif
break;
}
@@ -337,7 +333,7 @@ static int __init pxa27x_init(void)
if (cpu_is_pxa27x()) {
- reset_status = RCSR;
+ pxa_register_wdt(RCSR);
pxa27x_init_pm();
diff --git a/arch/arm/mach-pxa/pxa27x.h b/arch/arm/mach-pxa/pxa27x.h
index abdc02fb4f03..c9d9948ae7d1 100644
--- a/arch/arm/mach-pxa/pxa27x.h
+++ b/arch/arm/mach-pxa/pxa27x.h
@@ -3,10 +3,10 @@
#define __MACH_PXA27x_H
#include <linux/suspend.h>
-#include <mach/hardware.h>
-#include <mach/pxa2xx-regs.h>
+#include "addr-map.h"
+#include "pxa2xx-regs.h"
#include "mfp-pxa27x.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
@@ -20,7 +20,4 @@
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
-extern int pxa27x_set_pwrmode(unsigned int mode);
-extern void pxa27x_cpu_pm_enter(suspend_state_t state);
-
#endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/pxa2xx-regs.h
index fa121e135915..0b7eaf6b5813 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/pxa2xx-regs.h
@@ -11,7 +11,7 @@
#ifndef __PXA2XX_REGS_H
#define __PXA2XX_REGS_H
-#include <mach/hardware.h>
+#include "pxa-regs.h"
/*
* Power Manager
@@ -136,51 +136,6 @@
#define CKEN io_p2v(0x41300004) /* Clock Enable Register */
#define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
-#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
-#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CCCR_CPDIS_BIT (31)
-#define CCCR_PPDIS_BIT (30)
-#define CCCR_LCD_26_BIT (27)
-#define CCCR_A_BIT (25)
-
-#define CCSR_N2_MASK CCCR_N_MASK
-#define CCSR_M_MASK CCCR_M_MASK
-#define CCSR_L_MASK CCCR_L_MASK
-#define CCSR_N2_SHIFT 7
-
-#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
-#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
-#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
-#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
-#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
-#define CKEN_IM (20) /* Internal Memory Clock Enable */
-#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
-#define CKEN_USIM (18) /* USIM Unit Clock Enable */
-#define CKEN_MSL (17) /* MSL Unit Clock Enable */
-#define CKEN_LCD (16) /* LCD Unit Clock Enable */
-#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
-#define CKEN_I2C (14) /* I2C Unit Clock Enable */
-#define CKEN_FICP (13) /* FICP Unit Clock Enable */
-#define CKEN_MMC (12) /* MMC Unit Clock Enable */
-#define CKEN_USB (11) /* USB Unit Clock Enable */
-#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
-#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
-#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
-#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
-#define CKEN_I2S (8) /* I2S Unit Clock Enable */
-#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
-#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
-#define CKEN_STUART (5) /* STUART Unit Clock Enable */
-#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
-#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
-#define CKEN_SSP (3) /* SSP Unit Clock Enable */
-#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
-#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
-#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
-#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
-
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index 2d26cd2afbf3..35c23a5d73a3 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -12,11 +12,12 @@
#include <linux/device.h>
#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/pxa2xx-regs.h>
+#include "pxa2xx-regs.h"
#include "mfp-pxa25x.h"
-#include <mach/reset.h>
-#include <linux/platform_data/irda-pxaficp.h>
+#include "generic.h"
+#include "reset.h"
+#include "smemc.h"
+#include <linux/soc/pxa/smemc.h>
void pxa2xx_clear_reset_status(unsigned int mask)
{
@@ -24,30 +25,26 @@ void pxa2xx_clear_reset_status(unsigned int mask)
RCSR = mask;
}
-static unsigned long pxa2xx_mfp_fir[] = {
- GPIO46_FICP_RXD,
- GPIO47_FICP_TXD,
-};
+#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
+#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
-static unsigned long pxa2xx_mfp_sir[] = {
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-};
+int pxa2xx_smemc_get_sdram_rows(void)
+{
+ static int sdram_rows;
+ unsigned int drac2 = 0, drac0 = 0;
+ u32 mdcnfg;
-static unsigned long pxa2xx_mfp_off[] = {
- GPIO46_GPIO | MFP_LPM_DRIVE_LOW,
- GPIO47_GPIO | MFP_LPM_DRIVE_LOW,
-};
+ if (sdram_rows)
+ return sdram_rows;
-void pxa2xx_transceiver_mode(struct device *dev, int mode)
-{
- if (mode & IR_OFF) {
- pxa2xx_mfp_config(pxa2xx_mfp_off, ARRAY_SIZE(pxa2xx_mfp_off));
- } else if (mode & IR_SIRMODE) {
- pxa2xx_mfp_config(pxa2xx_mfp_sir, ARRAY_SIZE(pxa2xx_mfp_sir));
- } else if (mode & IR_FIRMODE) {
- pxa2xx_mfp_config(pxa2xx_mfp_fir, ARRAY_SIZE(pxa2xx_mfp_fir));
- } else
- BUG();
+ mdcnfg = readl_relaxed(MDCNFG);
+
+ if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
+ drac2 = MDCNFG_DRAC2(mdcnfg);
+
+ if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
+ drac0 = MDCNFG_DRAC0(mdcnfg);
+
+ sdram_rows = 1 << (11 + max(drac0, drac2));
+ return sdram_rows;
}
-EXPORT_SYMBOL_GPL(pxa2xx_transceiver_mode);
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 7f2f5a6a2263..f77ec118d5b9 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
+#include <linux/soc/pxa/cpu.h>
#include "pxa300.h"
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 78abcc741df7..e372e6c118de 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
+#include <linux/soc/pxa/cpu.h>
#include "pxa320.h"
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/pxa3xx-regs.h
index 070f6c74196e..4b11cf81a9e6 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/pxa3xx-regs.h
@@ -10,7 +10,7 @@
#ifndef __ASM_ARCH_PXA3XX_REGS_H
#define __ASM_ARCH_PXA3XX_REGS_H
-#include <mach/hardware.h>
+#include "pxa-regs.h"
/*
* Oscillator Configuration Register (OSCC)
@@ -131,73 +131,4 @@
#define CKENC __REG(0x41340024) /* C Clock Enable Register */
#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
-#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */
-#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */
-#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */
-#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
-#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
-
-#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */
-#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */
-#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */
-#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
-#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
-#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
-#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */
-
-#define ACCR_SMCFS(x) (((x) & 0x7) << 23)
-#define ACCR_SFLFS(x) (((x) & 0x3) << 18)
-#define ACCR_XSPCLK(x) (((x) & 0x3) << 16)
-#define ACCR_HSS(x) (((x) & 0x3) << 14)
-#define ACCR_DMCFS(x) (((x) & 0x3) << 12)
-#define ACCR_XN(x) (((x) & 0x7) << 8)
-#define ACCR_XL(x) ((x) & 0x1f)
-
-/*
- * Clock Enable Bit
- */
-#define CKEN_LCD 1 /* < LCD Clock Enable */
-#define CKEN_USBH 2 /* < USB host clock enable */
-#define CKEN_CAMERA 3 /* < Camera interface clock enable */
-#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
-#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
-#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
-#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
-#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
-#define CKEN_BOOT 11 /* < Boot rom clock enable */
-#define CKEN_MMC1 12 /* < MMC1 Clock enable */
-#define CKEN_MMC2 13 /* < MMC2 clock enable */
-#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
-#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
-#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
-#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
-#define CKEN_TPM 19 /* < TPM clock enable */
-#define CKEN_UDC 20 /* < UDC clock enable */
-#define CKEN_BTUART 21 /* < BTUART clock enable */
-#define CKEN_FFUART 22 /* < FFUART clock enable */
-#define CKEN_STUART 23 /* < STUART clock enable */
-#define CKEN_AC97 24 /* < AC97 clock enable */
-#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
-#define CKEN_SSP1 26 /* < SSP1 clock enable */
-#define CKEN_SSP2 27 /* < SSP2 clock enable */
-#define CKEN_SSP3 28 /* < SSP3 clock enable */
-#define CKEN_SSP4 29 /* < SSP4 clock enable */
-#define CKEN_MSL0 30 /* < MSL0 clock enable */
-#define CKEN_PWM0 32 /* < PWM[0] clock enable */
-#define CKEN_PWM1 33 /* < PWM[1] clock enable */
-#define CKEN_I2C 36 /* < I2C clock enable */
-#define CKEN_INTC 38 /* < Interrupt controller clock enable */
-#define CKEN_GPIO 39 /* < GPIO clock enable */
-#define CKEN_1WIRE 40 /* < 1-wire clock enable */
-#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
-#define CKEN_MINI_IM 48 /* < Mini-IM */
-#define CKEN_MINI_LCD 49 /* < Mini LCD */
-
-#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
-#define CKEN_MVED 43 /* < MVED clock enable */
-
-/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
-#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */
-#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */
-
#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
deleted file mode 100644
index 4bd7da1f8657..000000000000
--- a/arch/arm/mach-pxa/pxa3xx-ulpi.c
+++ /dev/null
@@ -1,385 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
- *
- * code specific to pxa3xx aka Monahans
- *
- * Copyright (C) 2010 CompuLab Ltd.
- *
- * 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
- * initial version: pxa310 USB Host mode support
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/usb.h>
-#include <linux/usb/otg.h>
-
-#include <mach/hardware.h>
-#include "regs-u2d.h"
-#include <linux/platform_data/usb-pxa3xx-ulpi.h>
-
-struct pxa3xx_u2d_ulpi {
- struct clk *clk;
- void __iomem *mmio_base;
-
- struct usb_phy *otg;
- unsigned int ulpi_mode;
-};
-
-static struct pxa3xx_u2d_ulpi *u2d;
-
-static inline u32 u2d_readl(u32 reg)
-{
- return __raw_readl(u2d->mmio_base + reg);
-}
-
-static inline void u2d_writel(u32 reg, u32 val)
-{
- __raw_writel(val, u2d->mmio_base + reg);
-}
-
-#if defined(CONFIG_PXA310_ULPI)
-enum u2d_ulpi_phy_mode {
- SYNCH = 0,
- CARKIT = (1 << 0),
- SER_3PIN = (1 << 1),
- SER_6PIN = (1 << 2),
- LOWPOWER = (1 << 3),
-};
-
-static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
-{
- return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
-}
-
-static int pxa310_ulpi_poll(void)
-{
- int timeout = 50000;
-
- while (timeout--) {
- if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
- return 0;
-
- cpu_relax();
- }
-
- pr_warn("%s: ULPI access timed out!\n", __func__);
-
- return -ETIMEDOUT;
-}
-
-static int pxa310_ulpi_read(struct usb_phy *otg, u32 reg)
-{
- int err;
-
- if (pxa310_ulpi_get_phymode() != SYNCH) {
- pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
- return -EBUSY;
- }
-
- u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
- msleep(5);
-
- err = pxa310_ulpi_poll();
- if (err)
- return err;
-
- return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
-}
-
-static int pxa310_ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
-{
- if (pxa310_ulpi_get_phymode() != SYNCH) {
- pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
- return -EBUSY;
- }
-
- u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
- msleep(5);
-
- return pxa310_ulpi_poll();
-}
-
-struct usb_phy_io_ops pxa310_ulpi_access_ops = {
- .read = pxa310_ulpi_read,
- .write = pxa310_ulpi_write,
-};
-
-static void pxa310_otg_transceiver_rtsm(void)
-{
- u32 u2dotgcr;
-
- /* put PHY to sync mode */
- u2dotgcr = u2d_readl(U2DOTGCR);
- u2dotgcr |= U2DOTGCR_RTSM | U2DOTGCR_UTMID;
- u2d_writel(U2DOTGCR, u2dotgcr);
- msleep(10);
-
- /* setup OTG sync mode */
- u2dotgcr = u2d_readl(U2DOTGCR);
- u2dotgcr |= U2DOTGCR_ULAF;
- u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
- u2d_writel(U2DOTGCR, u2dotgcr);
-}
-
-static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
-{
- int err;
-
- pxa310_otg_transceiver_rtsm();
-
- err = usb_phy_init(u2d->otg);
- if (err) {
- pr_err("OTG transceiver init failed");
- return err;
- }
-
- err = otg_set_vbus(u2d->otg->otg, 1);
- if (err) {
- pr_err("OTG transceiver VBUS set failed");
- return err;
- }
-
- err = otg_set_host(u2d->otg->otg, host);
- if (err)
- pr_err("OTG transceiver Host mode set failed");
-
- return err;
-}
-
-static int pxa310_start_otg_hc(struct usb_bus *host)
-{
- u32 u2dotgcr;
- int err;
-
- /* disable USB device controller */
- u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
- u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
- u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
-
- err = pxa310_start_otg_host_transcvr(host);
- if (err)
- return err;
-
- /* set xceiver mode */
- if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
- u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
- else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
- u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
-
- /* start OTG host controller */
- u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
- u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
-
- return 0;
-}
-
-static void pxa310_stop_otg_hc(void)
-{
- pxa310_otg_transceiver_rtsm();
-
- otg_set_host(u2d->otg->otg, NULL);
- otg_set_vbus(u2d->otg->otg, 0);
- usb_phy_shutdown(u2d->otg);
-}
-
-static void pxa310_u2d_setup_otg_hc(void)
-{
- u32 u2dotgcr;
-
- u2dotgcr = u2d_readl(U2DOTGCR);
- u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
- u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
- u2d_writel(U2DOTGCR, u2dotgcr);
- msleep(5);
- u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
- msleep(5);
- u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
-}
-
-static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
-{
- unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
-
- if (pdata) {
- if (pdata->ulpi_mode & ULPI_SER_6PIN)
- ulpi_mode |= ULPI_IC_6PIN_SERIAL;
- else if (pdata->ulpi_mode & ULPI_SER_3PIN)
- ulpi_mode |= ULPI_IC_3PIN_SERIAL;
- }
-
- u2d->ulpi_mode = ulpi_mode;
-
- u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
- if (!u2d->otg)
- return -ENOMEM;
-
- u2d->otg->io_priv = u2d->mmio_base;
-
- return 0;
-}
-
-static void pxa310_otg_exit(void)
-{
- kfree(u2d->otg);
-}
-#else
-static inline void pxa310_u2d_setup_otg_hc(void) {}
-static inline int pxa310_start_otg_hc(struct usb_bus *host)
-{
- return 0;
-}
-static inline void pxa310_stop_otg_hc(void) {}
-static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
-{
- return 0;
-}
-static inline void pxa310_otg_exit(void) {}
-#endif /* CONFIG_PXA310_ULPI */
-
-int pxa3xx_u2d_start_hc(struct usb_bus *host)
-{
- int err = 0;
-
- /* In case the PXA3xx ULPI isn't used, do nothing. */
- if (!u2d)
- return 0;
-
- clk_prepare_enable(u2d->clk);
-
- if (cpu_is_pxa310()) {
- pxa310_u2d_setup_otg_hc();
- err = pxa310_start_otg_hc(host);
- }
-
- return err;
-}
-EXPORT_SYMBOL_GPL(pxa3xx_u2d_start_hc);
-
-void pxa3xx_u2d_stop_hc(struct usb_bus *host)
-{
- /* In case the PXA3xx ULPI isn't used, do nothing. */
- if (!u2d)
- return;
-
- if (cpu_is_pxa310())
- pxa310_stop_otg_hc();
-
- clk_disable_unprepare(u2d->clk);
-}
-EXPORT_SYMBOL_GPL(pxa3xx_u2d_stop_hc);
-
-static int pxa3xx_u2d_probe(struct platform_device *pdev)
-{
- struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
- struct resource *r;
- int err;
-
- u2d = kzalloc(sizeof(*u2d), GFP_KERNEL);
- if (!u2d)
- return -ENOMEM;
-
- u2d->clk = clk_get(&pdev->dev, NULL);
- if (IS_ERR(u2d->clk)) {
- dev_err(&pdev->dev, "failed to get u2d clock\n");
- err = PTR_ERR(u2d->clk);
- goto err_free_mem;
- }
-
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!r) {
- dev_err(&pdev->dev, "no IO memory resource defined\n");
- err = -ENODEV;
- goto err_put_clk;
- }
-
- r = request_mem_region(r->start, resource_size(r), pdev->name);
- if (!r) {
- dev_err(&pdev->dev, "failed to request memory resource\n");
- err = -EBUSY;
- goto err_put_clk;
- }
-
- u2d->mmio_base = ioremap(r->start, resource_size(r));
- if (!u2d->mmio_base) {
- dev_err(&pdev->dev, "ioremap() failed\n");
- err = -ENODEV;
- goto err_free_res;
- }
-
- if (pdata->init) {
- err = pdata->init(&pdev->dev);
- if (err)
- goto err_free_io;
- }
-
- /* Only PXA310 U2D has OTG functionality */
- if (cpu_is_pxa310()) {
- err = pxa310_otg_init(pdata);
- if (err)
- goto err_free_plat;
- }
-
- platform_set_drvdata(pdev, u2d);
-
- return 0;
-
-err_free_plat:
- if (pdata->exit)
- pdata->exit(&pdev->dev);
-err_free_io:
- iounmap(u2d->mmio_base);
-err_free_res:
- release_mem_region(r->start, resource_size(r));
-err_put_clk:
- clk_put(u2d->clk);
-err_free_mem:
- kfree(u2d);
- return err;
-}
-
-static int pxa3xx_u2d_remove(struct platform_device *pdev)
-{
- struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
- struct resource *r;
-
- if (cpu_is_pxa310()) {
- pxa310_stop_otg_hc();
- pxa310_otg_exit();
- }
-
- if (pdata->exit)
- pdata->exit(&pdev->dev);
-
- platform_set_drvdata(pdev, NULL);
- iounmap(u2d->mmio_base);
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- release_mem_region(r->start, resource_size(r));
-
- clk_put(u2d->clk);
-
- kfree(u2d);
-
- return 0;
-}
-
-static struct platform_driver pxa3xx_u2d_ulpi_driver = {
- .driver = {
- .name = "pxa3xx-u2d",
- },
- .probe = pxa3xx_u2d_probe,
- .remove = pxa3xx_u2d_remove,
-};
-module_platform_driver(pxa3xx_u2d_ulpi_driver);
-
-MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
-MODULE_AUTHOR("Igor Grinberg");
-MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 560160682df6..1d1e5713464d 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -24,17 +24,18 @@
#include <linux/syscore_ops.h>
#include <linux/platform_data/i2c-pxa.h>
#include <linux/platform_data/mmp_dma.h>
+#include <linux/soc/pxa/cpu.h>
+#include <linux/clk/pxa.h>
#include <asm/mach/map.h>
#include <asm/suspend.h>
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/reset.h>
+#include "pxa3xx-regs.h"
+#include "reset.h"
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include "pm.h"
-#include <mach/dma.h>
-#include <mach/smemc.h>
-#include <mach/irqs.h>
+#include "addr-map.h"
+#include "smemc.h"
+#include "irqs.h"
#include "generic.h"
#include "devices.h"
@@ -51,6 +52,10 @@ extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
#define NDCR_ND_ARB_EN (1 << 12)
#define NDCR_ND_ARB_CNTL (1 << 19)
+#define CKEN_BOOT 11 /* < Boot rom clock enable */
+#define CKEN_TPM 19 /* < TPM clock enable */
+#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
+
#ifdef CONFIG_PM
#define ISRAM_START 0x5c000000
@@ -103,8 +108,12 @@ static void pxa3xx_cpu_pm_suspend(void)
#ifndef CONFIG_IWMMXT
u64 acc0;
+#ifdef CONFIG_CC_IS_GCC
asm volatile(".arch_extension xscale\n\t"
"mra %Q0, %R0, acc0" : "=r" (acc0));
+#else
+ asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
+#endif
#endif
/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
@@ -132,8 +141,12 @@ static void pxa3xx_cpu_pm_suspend(void)
AD3ER = 0;
#ifndef CONFIG_IWMMXT
+#ifndef CONFIG_AS_IS_LLVM
asm volatile(".arch_extension xscale\n\t"
"mar acc0, %Q0, %R0" : "=r" (acc0));
+#else
+ asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
+#endif
#endif
}
@@ -350,13 +363,6 @@ static void __init __pxa3xx_init_irq(void)
pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
}
-void __init pxa3xx_init_irq(void)
-{
- __pxa3xx_init_irq();
- pxa_init_irq(56, pxa3xx_set_wake);
-}
-
-#ifdef CONFIG_OF
static int __init __init
pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
{
@@ -367,7 +373,6 @@ pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
return 0;
}
IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
-#endif /* CONFIG_OF */
static struct map_desc pxa3xx_io_desc[] __initdata = {
{ /* Mem Ctl */
@@ -390,80 +395,13 @@ void __init pxa3xx_map_io(void)
pxa3xx_get_clk_frequency_khz(1);
}
-/*
- * device registration specific to PXA3xx.
- */
-
-void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
-{
- pxa_register_device(&pxa3xx_device_i2c_power, info);
-}
-
-static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
- .irq_base = PXA_GPIO_TO_IRQ(0),
-};
-
-static struct platform_device *devices[] __initdata = {
- &pxa27x_device_udc,
- &pxa_device_pmu,
- &pxa_device_i2s,
- &pxa_device_asoc_ssp1,
- &pxa_device_asoc_ssp2,
- &pxa_device_asoc_ssp3,
- &pxa_device_asoc_ssp4,
- &pxa_device_asoc_platform,
- &pxa_device_rtc,
- &pxa3xx_device_ssp1,
- &pxa3xx_device_ssp2,
- &pxa3xx_device_ssp3,
- &pxa3xx_device_ssp4,
- &pxa27x_device_pwm0,
- &pxa27x_device_pwm1,
-};
-
-static const struct dma_slave_map pxa3xx_slave_map[] = {
- /* PXA25x, PXA27x and PXA3xx common entries */
- { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
- { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
- { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
- PDMA_FILTER_PARAM(LOWEST, 10) },
- { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
- { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
- { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
- { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
- { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
- { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
- { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
- { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
- { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
- { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
- { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
- { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
-
- /* PXA3xx specific map */
- { "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
- { "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
- { "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) },
- { "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) },
- { "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) },
- { "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) },
- { "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) },
-};
-
-static struct mmp_dma_platdata pxa3xx_dma_pdata = {
- .dma_channels = 32,
- .nb_requestors = 100,
- .slave_map = pxa3xx_slave_map,
- .slave_map_cnt = ARRAY_SIZE(pxa3xx_slave_map),
-};
-
static int __init pxa3xx_init(void)
{
int ret = 0;
if (cpu_is_pxa3xx()) {
- reset_status = ARSR;
+ pxa_register_wdt(ARSR);
/*
* clear RDH bit every time after reset
@@ -488,20 +426,6 @@ static int __init pxa3xx_init(void)
register_syscore_ops(&pxa_irq_syscore_ops);
register_syscore_ops(&pxa3xx_mfp_syscore_ops);
-
- if (of_have_populated_dt())
- return 0;
-
- pxa2xx_set_dmac_info(&pxa3xx_dma_pdata);
- ret = platform_add_devices(devices, ARRAY_SIZE(devices));
- if (ret)
- return ret;
- if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
- platform_device_add_data(&pxa3xx_device_gpio,
- &pxa3xx_gpio_pdata,
- sizeof(pxa3xx_gpio_pdata));
- ret = platform_device_register(&pxa3xx_device_gpio);
- }
}
return ret;
diff --git a/arch/arm/mach-pxa/pxa3xx.h b/arch/arm/mach-pxa/pxa3xx.h
index 6d4502aa9d06..81825f7ad258 100644
--- a/arch/arm/mach-pxa/pxa3xx.h
+++ b/arch/arm/mach-pxa/pxa3xx.h
@@ -2,8 +2,8 @@
#ifndef __MACH_PXA3XX_H
#define __MACH_PXA3XX_H
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/irqs.h>
+#include "addr-map.h"
+#include "pxa3xx-regs.h"
+#include "irqs.h"
#endif /* __MACH_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
deleted file mode 100644
index bf91de4267e5..000000000000
--- a/arch/arm/mach-pxa/pxa930.c
+++ /dev/null
@@ -1,216 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/pxa930.c
- *
- * Code specific to PXA930
- *
- * Copyright (C) 2007-2008 Marvell Internation Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/dma-mapping.h>
-#include <linux/irq.h>
-#include <linux/gpio-pxa.h>
-#include <linux/platform_device.h>
-
-#include "pxa930.h"
-
-#include "devices.h"
-
-static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
-
- MFP_ADDR(GPIO0, 0x02e0),
- MFP_ADDR(GPIO1, 0x02dc),
- MFP_ADDR(GPIO2, 0x02e8),
- MFP_ADDR(GPIO3, 0x02d8),
- MFP_ADDR(GPIO4, 0x02e4),
- MFP_ADDR(GPIO5, 0x02ec),
- MFP_ADDR(GPIO6, 0x02f8),
- MFP_ADDR(GPIO7, 0x02fc),
- MFP_ADDR(GPIO8, 0x0300),
- MFP_ADDR(GPIO9, 0x02d4),
- MFP_ADDR(GPIO10, 0x02f4),
- MFP_ADDR(GPIO11, 0x02f0),
- MFP_ADDR(GPIO12, 0x0304),
- MFP_ADDR(GPIO13, 0x0310),
- MFP_ADDR(GPIO14, 0x0308),
- MFP_ADDR(GPIO15, 0x030c),
- MFP_ADDR(GPIO16, 0x04e8),
- MFP_ADDR(GPIO17, 0x04f4),
- MFP_ADDR(GPIO18, 0x04f8),
- MFP_ADDR(GPIO19, 0x04fc),
- MFP_ADDR(GPIO20, 0x0518),
- MFP_ADDR(GPIO21, 0x051c),
- MFP_ADDR(GPIO22, 0x04ec),
- MFP_ADDR(GPIO23, 0x0500),
- MFP_ADDR(GPIO24, 0x04f0),
- MFP_ADDR(GPIO25, 0x0504),
- MFP_ADDR(GPIO26, 0x0510),
- MFP_ADDR(GPIO27, 0x0514),
- MFP_ADDR(GPIO28, 0x0520),
- MFP_ADDR(GPIO29, 0x0600),
- MFP_ADDR(GPIO30, 0x0618),
- MFP_ADDR(GPIO31, 0x0610),
- MFP_ADDR(GPIO32, 0x060c),
- MFP_ADDR(GPIO33, 0x061c),
- MFP_ADDR(GPIO34, 0x0620),
- MFP_ADDR(GPIO35, 0x0628),
- MFP_ADDR(GPIO36, 0x062c),
- MFP_ADDR(GPIO37, 0x0630),
- MFP_ADDR(GPIO38, 0x0634),
- MFP_ADDR(GPIO39, 0x0638),
- MFP_ADDR(GPIO40, 0x063c),
- MFP_ADDR(GPIO41, 0x0614),
- MFP_ADDR(GPIO42, 0x0624),
- MFP_ADDR(GPIO43, 0x0608),
- MFP_ADDR(GPIO44, 0x0604),
- MFP_ADDR(GPIO45, 0x050c),
- MFP_ADDR(GPIO46, 0x0508),
- MFP_ADDR(GPIO47, 0x02bc),
- MFP_ADDR(GPIO48, 0x02b4),
- MFP_ADDR(GPIO49, 0x02b8),
- MFP_ADDR(GPIO50, 0x02c8),
- MFP_ADDR(GPIO51, 0x02c0),
- MFP_ADDR(GPIO52, 0x02c4),
- MFP_ADDR(GPIO53, 0x02d0),
- MFP_ADDR(GPIO54, 0x02cc),
- MFP_ADDR(GPIO55, 0x029c),
- MFP_ADDR(GPIO56, 0x02a0),
- MFP_ADDR(GPIO57, 0x0294),
- MFP_ADDR(GPIO58, 0x0298),
- MFP_ADDR(GPIO59, 0x02a4),
- MFP_ADDR(GPIO60, 0x02a8),
- MFP_ADDR(GPIO61, 0x02b0),
- MFP_ADDR(GPIO62, 0x02ac),
- MFP_ADDR(GPIO63, 0x0640),
- MFP_ADDR(GPIO64, 0x065c),
- MFP_ADDR(GPIO65, 0x0648),
- MFP_ADDR(GPIO66, 0x0644),
- MFP_ADDR(GPIO67, 0x0674),
- MFP_ADDR(GPIO68, 0x0658),
- MFP_ADDR(GPIO69, 0x0654),
- MFP_ADDR(GPIO70, 0x0660),
- MFP_ADDR(GPIO71, 0x0668),
- MFP_ADDR(GPIO72, 0x0664),
- MFP_ADDR(GPIO73, 0x0650),
- MFP_ADDR(GPIO74, 0x066c),
- MFP_ADDR(GPIO75, 0x064c),
- MFP_ADDR(GPIO76, 0x0670),
- MFP_ADDR(GPIO77, 0x0678),
- MFP_ADDR(GPIO78, 0x067c),
- MFP_ADDR(GPIO79, 0x0694),
- MFP_ADDR(GPIO80, 0x069c),
- MFP_ADDR(GPIO81, 0x06a0),
- MFP_ADDR(GPIO82, 0x06a4),
- MFP_ADDR(GPIO83, 0x0698),
- MFP_ADDR(GPIO84, 0x06bc),
- MFP_ADDR(GPIO85, 0x06b4),
- MFP_ADDR(GPIO86, 0x06b0),
- MFP_ADDR(GPIO87, 0x06c0),
- MFP_ADDR(GPIO88, 0x06c4),
- MFP_ADDR(GPIO89, 0x06ac),
- MFP_ADDR(GPIO90, 0x0680),
- MFP_ADDR(GPIO91, 0x0684),
- MFP_ADDR(GPIO92, 0x0688),
- MFP_ADDR(GPIO93, 0x0690),
- MFP_ADDR(GPIO94, 0x068c),
- MFP_ADDR(GPIO95, 0x06a8),
- MFP_ADDR(GPIO96, 0x06b8),
- MFP_ADDR(GPIO97, 0x0410),
- MFP_ADDR(GPIO98, 0x0418),
- MFP_ADDR(GPIO99, 0x041c),
- MFP_ADDR(GPIO100, 0x0414),
- MFP_ADDR(GPIO101, 0x0408),
- MFP_ADDR(GPIO102, 0x0324),
- MFP_ADDR(GPIO103, 0x040c),
- MFP_ADDR(GPIO104, 0x0400),
- MFP_ADDR(GPIO105, 0x0328),
- MFP_ADDR(GPIO106, 0x0404),
-
- MFP_ADDR(nXCVREN, 0x0204),
- MFP_ADDR(DF_CLE_nOE, 0x020c),
- MFP_ADDR(DF_nADV1_ALE, 0x0218),
- MFP_ADDR(DF_SCLK_E, 0x0214),
- MFP_ADDR(DF_SCLK_S, 0x0210),
- MFP_ADDR(nBE0, 0x021c),
- MFP_ADDR(nBE1, 0x0220),
- MFP_ADDR(DF_nADV2_ALE, 0x0224),
- MFP_ADDR(DF_INT_RnB, 0x0228),
- MFP_ADDR(DF_nCS0, 0x022c),
- MFP_ADDR(DF_nCS1, 0x0230),
- MFP_ADDR(nLUA, 0x0254),
- MFP_ADDR(nLLA, 0x0258),
- MFP_ADDR(DF_nWE, 0x0234),
- MFP_ADDR(DF_nRE_nOE, 0x0238),
- MFP_ADDR(DF_ADDR0, 0x024c),
- MFP_ADDR(DF_ADDR1, 0x0250),
- MFP_ADDR(DF_ADDR2, 0x025c),
- MFP_ADDR(DF_ADDR3, 0x0260),
- MFP_ADDR(DF_IO0, 0x023c),
- MFP_ADDR(DF_IO1, 0x0240),
- MFP_ADDR(DF_IO2, 0x0244),
- MFP_ADDR(DF_IO3, 0x0248),
- MFP_ADDR(DF_IO4, 0x0264),
- MFP_ADDR(DF_IO5, 0x0268),
- MFP_ADDR(DF_IO6, 0x026c),
- MFP_ADDR(DF_IO7, 0x0270),
- MFP_ADDR(DF_IO8, 0x0274),
- MFP_ADDR(DF_IO9, 0x0278),
- MFP_ADDR(DF_IO10, 0x027c),
- MFP_ADDR(DF_IO11, 0x0280),
- MFP_ADDR(DF_IO12, 0x0284),
- MFP_ADDR(DF_IO13, 0x0288),
- MFP_ADDR(DF_IO14, 0x028c),
- MFP_ADDR(DF_IO15, 0x0290),
-
- MFP_ADDR(GSIM_UIO, 0x0314),
- MFP_ADDR(GSIM_UCLK, 0x0318),
- MFP_ADDR(GSIM_UDET, 0x031c),
- MFP_ADDR(GSIM_nURST, 0x0320),
-
- MFP_ADDR(PMIC_INT, 0x06c8),
-
- MFP_ADDR(RDY, 0x0200),
-
- MFP_ADDR_END,
-};
-
-static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
- MFP_ADDR(GPIO159, 0x0524),
- MFP_ADDR(GPIO163, 0x0534),
- MFP_ADDR(GPIO167, 0x0544),
- MFP_ADDR(GPIO168, 0x0548),
- MFP_ADDR(GPIO169, 0x054c),
- MFP_ADDR(GPIO170, 0x0550),
- MFP_ADDR(GPIO171, 0x0554),
- MFP_ADDR(GPIO172, 0x0558),
- MFP_ADDR(GPIO173, 0x055c),
-
- MFP_ADDR_END,
-};
-
-static struct pxa_gpio_platform_data pxa93x_gpio_pdata = {
- .irq_base = PXA_GPIO_TO_IRQ(0),
-};
-
-static int __init pxa930_init(void)
-{
- int ret = 0;
-
- if (cpu_is_pxa93x()) {
- mfp_init_base(io_p2v(MFPR_BASE));
- mfp_init_addr(pxa930_mfp_addr_map);
- platform_device_add_data(&pxa93x_device_gpio,
- &pxa93x_gpio_pdata,
- sizeof(pxa93x_gpio_pdata));
- ret = platform_device_register(&pxa93x_device_gpio);
- }
-
- if (cpu_is_pxa935())
- mfp_init_addr(pxa935_mfp_addr_map);
-
- return 0;
-}
-
-core_initcall(pxa930_init);
diff --git a/arch/arm/mach-pxa/pxa930.h b/arch/arm/mach-pxa/pxa930.h
deleted file mode 100644
index bbf25c044641..000000000000
--- a/arch/arm/mach-pxa/pxa930.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_PXA930_H
-#define __MACH_PXA930_H
-
-#include "pxa3xx.h"
-#include "mfp-pxa930.h"
-
-#endif /* __MACH_PXA930_H */
diff --git a/arch/arm/mach-pxa/pxa_cplds_irqs.c b/arch/arm/mach-pxa/pxa_cplds_irqs.c
deleted file mode 100644
index eda5a47d7fbb..000000000000
--- a/arch/arm/mach-pxa/pxa_cplds_irqs.c
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Intel Reference Systems cplds
- *
- * Copyright (C) 2014 Robert Jarzmik
- *
- * Cplds motherboard driver, supporting lubbock and mainstone SoC board.
- */
-
-#include <linux/bitops.h>
-#include <linux/gpio.h>
-#include <linux/gpio/consumer.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/mfd/core.h>
-#include <linux/module.h>
-#include <linux/of_platform.h>
-
-#define FPGA_IRQ_MASK_EN 0x0
-#define FPGA_IRQ_SET_CLR 0x10
-
-#define CPLDS_NB_IRQ 32
-
-struct cplds {
- void __iomem *base;
- int irq;
- unsigned int irq_mask;
- struct gpio_desc *gpio0;
- struct irq_domain *irqdomain;
-};
-
-static irqreturn_t cplds_irq_handler(int in_irq, void *d)
-{
- struct cplds *fpga = d;
- unsigned long pending;
- unsigned int bit;
-
- do {
- pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
- for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
- generic_handle_domain_irq(fpga->irqdomain, bit);
- } while (pending);
-
- return IRQ_HANDLED;
-}
-
-static void cplds_irq_mask(struct irq_data *d)
-{
- struct cplds *fpga = irq_data_get_irq_chip_data(d);
- unsigned int cplds_irq = irqd_to_hwirq(d);
- unsigned int bit = BIT(cplds_irq);
-
- fpga->irq_mask &= ~bit;
- writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
-}
-
-static void cplds_irq_unmask(struct irq_data *d)
-{
- struct cplds *fpga = irq_data_get_irq_chip_data(d);
- unsigned int cplds_irq = irqd_to_hwirq(d);
- unsigned int set, bit = BIT(cplds_irq);
-
- set = readl(fpga->base + FPGA_IRQ_SET_CLR);
- writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
-
- fpga->irq_mask |= bit;
- writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
-}
-
-static struct irq_chip cplds_irq_chip = {
- .name = "pxa_cplds",
- .irq_ack = cplds_irq_mask,
- .irq_mask = cplds_irq_mask,
- .irq_unmask = cplds_irq_unmask,
- .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
-};
-
-static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hwirq)
-{
- struct cplds *fpga = d->host_data;
-
- irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, fpga);
-
- return 0;
-}
-
-static const struct irq_domain_ops cplds_irq_domain_ops = {
- .xlate = irq_domain_xlate_twocell,
- .map = cplds_irq_domain_map,
-};
-
-static int cplds_resume(struct platform_device *pdev)
-{
- struct cplds *fpga = platform_get_drvdata(pdev);
-
- writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
-
- return 0;
-}
-
-static int cplds_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct cplds *fpga;
- int ret;
- int base_irq;
- unsigned long irqflags = 0;
-
- fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
- if (!fpga)
- return -ENOMEM;
-
- fpga->irq = platform_get_irq(pdev, 0);
- if (fpga->irq <= 0)
- return fpga->irq;
-
- base_irq = platform_get_irq(pdev, 1);
- if (base_irq < 0) {
- base_irq = 0;
- } else {
- ret = devm_irq_alloc_descs(&pdev->dev, base_irq, base_irq, CPLDS_NB_IRQ, 0);
- if (ret < 0)
- return ret;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- fpga->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(fpga->base))
- return PTR_ERR(fpga->base);
-
- platform_set_drvdata(pdev, fpga);
-
- writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
- writel(0, fpga->base + FPGA_IRQ_SET_CLR);
-
- irqflags = irq_get_trigger_type(fpga->irq);
- ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
- irqflags, dev_name(&pdev->dev), fpga);
- if (ret == -ENOSYS)
- return -EPROBE_DEFER;
-
- if (ret) {
- dev_err(&pdev->dev, "couldn't request main irq%d: %d\n",
- fpga->irq, ret);
- return ret;
- }
-
- irq_set_irq_wake(fpga->irq, 1);
- if (base_irq)
- fpga->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
- CPLDS_NB_IRQ,
- base_irq, 0,
- &cplds_irq_domain_ops,
- fpga);
- else
- fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
- CPLDS_NB_IRQ,
- &cplds_irq_domain_ops,
- fpga);
- if (!fpga->irqdomain)
- return -ENODEV;
-
- return 0;
-}
-
-static int cplds_remove(struct platform_device *pdev)
-{
- struct cplds *fpga = platform_get_drvdata(pdev);
-
- irq_set_chip_and_handler(fpga->irq, NULL, NULL);
-
- return 0;
-}
-
-static const struct of_device_id cplds_id_table[] = {
- { .compatible = "intel,lubbock-cplds-irqs", },
- { .compatible = "intel,mainstone-cplds-irqs", },
- { }
-};
-MODULE_DEVICE_TABLE(of, cplds_id_table);
-
-static struct platform_driver cplds_driver = {
- .driver = {
- .name = "pxa_cplds_irqs",
- .of_match_table = of_match_ptr(cplds_id_table),
- },
- .probe = cplds_probe,
- .remove = cplds_remove,
- .resume = cplds_resume,
-};
-
-module_platform_driver(cplds_driver);
-
-MODULE_DESCRIPTION("PXA Cplds interrupts driver");
-MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/regs-ost.h
index deb564ed8ee7..c8001cfc8d6b 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ost.h
+++ b/arch/arm/mach-pxa/regs-ost.h
@@ -2,11 +2,13 @@
#ifndef __ASM_MACH_REGS_OST_H
#define __ASM_MACH_REGS_OST_H
-#include <mach/hardware.h>
+#include "pxa-regs.h"
/*
* OS Timer & Match Registers
*/
+#define OST_PHYS 0x40A00000
+#define OST_LEN 0x00000020
#define OSMR0 io_p2v(0x40A00000) /* */
#define OSMR1 io_p2v(0x40A00004) /* */
diff --git a/arch/arm/mach-pxa/regs-rtc.h b/arch/arm/mach-pxa/regs-rtc.h
index b1f9ff14e335..96255a0f595e 100644
--- a/arch/arm/mach-pxa/regs-rtc.h
+++ b/arch/arm/mach-pxa/regs-rtc.h
@@ -2,7 +2,7 @@
#ifndef __ASM_MACH_REGS_RTC_H
#define __ASM_MACH_REGS_RTC_H
-#include <mach/hardware.h>
+#include "pxa-regs.h"
/*
* Real Time Clock
diff --git a/arch/arm/mach-pxa/regs-u2d.h b/arch/arm/mach-pxa/regs-u2d.h
deleted file mode 100644
index fe4c80ad87ec..000000000000
--- a/arch/arm/mach-pxa/regs-u2d.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_PXA3xx_U2D_H
-#define __ASM_ARCH_PXA3xx_U2D_H
-
-#include <mach/bitfield.h>
-
-/*
- * USB2 device controller registers and bits definitions
- */
-#define U2DCR (0x0000) /* U2D Control Register */
-#define U2DCR_NDC (1 << 31) /* NAK During Config */
-#define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */
-#define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */
-#define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */
-#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */
-#define U2DCR_ABP (1 << 21) /* Application Bus Power */
-#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */
-#define U2DCR_CC (1 << 19) /* Configuration Change */
-#define U2DCR_HS (1 << 18) /* High Speed USB Detection */
-#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */
-#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */
-#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */
-#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */
-#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */
-#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */
-#define U2DCR_UDR (1 << 2) /* U2D Resume */
-#define U2DCR_UDA (1 << 1) /* U2D Active */
-#define U2DCR_UDE (1 << 0) /* U2D Enable */
-
-#define U2DICR (0x0004) /* U2D Interrupt Control Register */
-#define U2DISR (0x000C) /* U2D Interrupt Status Register */
-#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */
-#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */
-#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */
-#define U2DINT_RU (1 << 28) /* Interrupt - Resume */
-#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */
-#define U2DINT_RS (1 << 26) /* Interrupt - Reset */
-#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */
-#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */
-#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */
-#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */
-
-#define U2DFNR (0x0014) /* U2D Frame Number Register */
-
-#define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3))
-#define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */
-#define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */
-
-#define U2DOTGCR (0x0020) /* U2D OTG Control Register */
-#define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */
-#define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */
-#define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */
-#define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */
-
-#ifdef CONFIG_CPU_PXA930
-#define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */
-#define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */
-#define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */
-#endif
-
-#define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */
-#define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */
-#define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */
-#define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */
-#define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */
-#define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */
-
-#define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */
-#define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */
-
-#define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */
-#define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */
-#define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */
-#define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */
-#define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */
-#define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */
-#define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */
-#define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */
-#define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */
-#define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */
-#define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */
-#define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */
-#define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */
-#define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */
-#define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */
-#define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */
-
-#define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */
-#define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */
-#define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */
-#define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */
-#define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */
-#define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */
-#define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */
-#define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */
-#define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */
-#define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */
-#define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */
-#define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */
-
-#define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */
-#define U2DOTGUCR_RUN (1 << 25) /* RUN */
-#define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */
-#define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */
-#define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */
-#define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */
-
-#define U2DP3CR (0x0034) /* U2D Port 3 Control Register */
-#define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */
-#define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */
-#define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */
-#define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */
-
-#define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */
-#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */
-#define U2DCSR0_SA (1 << 7) /* SETUP Active */
-#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
-#define U2DCSR0_FST (1 << 5) /* Force Stall */
-#define U2DCSR0_SST (1 << 4) /* Send Stall */
-#define U2DCSR0_DME (1 << 3) /* DMA Enable */
-#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
-#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */
-#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */
-
-#define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */
-#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */
-#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */
-#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */
-#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
-#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */
-#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */
-#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */
-#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */
-#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */
-#define U2DCSR_DME (1 << 3) /* DMA Enable */
-#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */
-#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */
-#define U2DCSR_FS (1 << 0) /* FIFO needs Service */
-
-#define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */
-#define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */
-
-#define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */
-
-#define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */
-#define U2DEPCR_EE (1 << 0) /* Endpoint Enable */
-#define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */
-
-#define U2DSCA (0x0500) /* U2D Setup Command Address */
-#define U2DSCA_VALUE (0x0120)
-
-#define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */
-#define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */
-
-/* U2DMA registers */
-#define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */
-#define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */
-#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */
-#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
-#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
-#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
-#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
-#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */
-#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */
-#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */
-#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */
-#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */
-#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */
-#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */
-#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */
-#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */
-#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */
-#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */
-#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */
-
-#define U2DMACR (0x1080) /* U2DMA Control Register */
-#define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */
-
-#define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */
-#define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */
-
-#define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */
-#define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */
-
-#define U2DMADADR_STOP (1U << 0)
-
-#define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */
-#define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */
-#define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */
-#define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */
-
-#define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */
-#define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */
-
-#define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */
-#define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
-#define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */
-#define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */
-#define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */
-
-#endif /* __ASM_ARCH_PXA3xx_U2D_H */
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index af78405aa4e9..f0be90573ad3 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -7,12 +7,9 @@
#include <asm/proc-fns.h>
#include <asm/system_misc.h>
-#include <mach/regs-ost.h>
-#include <mach/reset.h>
-#include <mach/smemc.h>
-
-unsigned int reset_status;
-EXPORT_SYMBOL(reset_status);
+#include "regs-ost.h"
+#include "reset.h"
+#include "smemc.h"
static void do_hw_reset(void);
diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/reset.h
index e1c4d100fd45..963dd190bc13 100644
--- a/arch/arm/mach-pxa/include/mach/reset.h
+++ b/arch/arm/mach-pxa/reset.h
@@ -8,8 +8,8 @@
#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
#define RESET_STATUS_ALL (0xf)
-extern unsigned int reset_status;
extern void clear_reset_status(unsigned int mask);
+extern void pxa_register_wdt(unsigned int reset_status);
/**
* init_gpio_reset() - register GPIO as reset generator
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
deleted file mode 100644
index 3275b679792b..000000000000
--- a/arch/arm/mach-pxa/saar.c
+++ /dev/null
@@ -1,604 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/saar.c
- *
- * Support for the Marvell PXA930 Handheld Platform (aka SAAR)
- *
- * Copyright (C) 2007-2008 Marvell International Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/smc91x.h>
-#include <linux/mfd/da903x.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/onenand.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-
-#include "pxa930.h"
-#include <linux/platform_data/video-pxafb.h>
-
-#include "devices.h"
-#include "generic.h"
-
-#define GPIO_LCD_RESET (16)
-
-/* SAAR MFP configurations */
-static mfp_cfg_t saar_mfp_cfg[] __initdata = {
- /* LCD */
- GPIO23_LCD_DD0,
- GPIO24_LCD_DD1,
- GPIO25_LCD_DD2,
- GPIO26_LCD_DD3,
- GPIO27_LCD_DD4,
- GPIO28_LCD_DD5,
- GPIO29_LCD_DD6,
- GPIO44_LCD_DD7,
- GPIO21_LCD_CS,
- GPIO22_LCD_VSYNC,
- GPIO17_LCD_FCLK_RD,
- GPIO18_LCD_LCLK_A0,
- GPIO19_LCD_PCLK_WR,
- GPIO16_GPIO, /* LCD reset */
-
- /* Ethernet */
- DF_nCS1_nCS3,
- GPIO97_GPIO,
-
- /* DFI */
- DF_INT_RnB_ND_INT_RnB,
- DF_nRE_nOE_ND_nRE,
- DF_nWE_ND_nWE,
- DF_CLE_nOE_ND_CLE,
- DF_nADV1_ALE_ND_ALE,
- DF_nADV2_ALE_nCS3,
- DF_nCS0_ND_nCS0,
- DF_IO0_ND_IO0,
- DF_IO1_ND_IO1,
- DF_IO2_ND_IO2,
- DF_IO3_ND_IO3,
- DF_IO4_ND_IO4,
- DF_IO5_ND_IO5,
- DF_IO6_ND_IO6,
- DF_IO7_ND_IO7,
- DF_IO8_ND_IO8,
- DF_IO9_ND_IO9,
- DF_IO10_ND_IO10,
- DF_IO11_ND_IO11,
- DF_IO12_ND_IO12,
- DF_IO13_ND_IO13,
- DF_IO14_ND_IO14,
- DF_IO15_ND_IO15,
-};
-
-#define SAAR_ETH_PHYS (0x14000000)
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (SAAR_ETH_PHYS + 0x300),
- .end = (SAAR_ETH_PHYS + 0xfffff),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
- .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct smc91x_platdata saar_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &saar_smc91x_info,
- },
-};
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static uint16_t lcd_power_on[] = {
- /* single frame */
- SMART_CMD_NOOP,
- SMART_CMD(0x00),
- SMART_DELAY(0),
-
- SMART_CMD_NOOP,
- SMART_CMD(0x00),
- SMART_DELAY(0),
-
- SMART_CMD_NOOP,
- SMART_CMD(0x00),
- SMART_DELAY(0),
-
- SMART_CMD_NOOP,
- SMART_CMD(0x00),
- SMART_DELAY(10),
-
- /* calibration control */
- SMART_CMD(0x00),
- SMART_CMD(0xA4),
- SMART_DAT(0x80),
- SMART_DAT(0x01),
- SMART_DELAY(150),
-
- /*Power-On Init sequence*/
- SMART_CMD(0x00), /* output ctrl */
- SMART_CMD(0x01),
- SMART_DAT(0x01),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* wave ctrl */
- SMART_CMD(0x02),
- SMART_DAT(0x07),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x03), /* entry mode */
- SMART_DAT(0xD0),
- SMART_DAT(0x30),
- SMART_CMD(0x00),
- SMART_CMD(0x08), /* display ctrl 2 */
- SMART_DAT(0x08),
- SMART_DAT(0x08),
- SMART_CMD(0x00),
- SMART_CMD(0x09), /* display ctrl 3 */
- SMART_DAT(0x04),
- SMART_DAT(0x2F),
- SMART_CMD(0x00),
- SMART_CMD(0x0A), /* display ctrl 4 */
- SMART_DAT(0x00),
- SMART_DAT(0x08),
- SMART_CMD(0x00),
- SMART_CMD(0x0D), /* Frame Marker position */
- SMART_DAT(0x00),
- SMART_DAT(0x08),
- SMART_CMD(0x00),
- SMART_CMD(0x60), /* Driver output control */
- SMART_DAT(0x27),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x61), /* Base image display control */
- SMART_DAT(0x00),
- SMART_DAT(0x01),
- SMART_CMD(0x00),
- SMART_CMD(0x30), /* Y settings 30h-3Dh */
- SMART_DAT(0x07),
- SMART_DAT(0x07),
- SMART_CMD(0x00),
- SMART_CMD(0x31),
- SMART_DAT(0x00),
- SMART_DAT(0x07),
- SMART_CMD(0x00),
- SMART_CMD(0x32), /* Timing(3), ASW HOLD=0.5CLK */
- SMART_DAT(0x04),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x33), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
- SMART_DAT(0x03),
- SMART_DAT(0x03),
- SMART_CMD(0x00),
- SMART_CMD(0x34),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x35),
- SMART_DAT(0x02),
- SMART_DAT(0x05),
- SMART_CMD(0x00),
- SMART_CMD(0x36),
- SMART_DAT(0x1F),
- SMART_DAT(0x1F),
- SMART_CMD(0x00),
- SMART_CMD(0x37),
- SMART_DAT(0x07),
- SMART_DAT(0x07),
- SMART_CMD(0x00),
- SMART_CMD(0x38),
- SMART_DAT(0x00),
- SMART_DAT(0x07),
- SMART_CMD(0x00),
- SMART_CMD(0x39),
- SMART_DAT(0x04),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x3A),
- SMART_DAT(0x03),
- SMART_DAT(0x03),
- SMART_CMD(0x00),
- SMART_CMD(0x3B),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x3C),
- SMART_DAT(0x02),
- SMART_DAT(0x05),
- SMART_CMD(0x00),
- SMART_CMD(0x3D),
- SMART_DAT(0x1F),
- SMART_DAT(0x1F),
- SMART_CMD(0x00), /* Display control 1 */
- SMART_CMD(0x07),
- SMART_DAT(0x00),
- SMART_DAT(0x01),
- SMART_CMD(0x00), /* Power control 5 */
- SMART_CMD(0x17),
- SMART_DAT(0x00),
- SMART_DAT(0x01),
- SMART_CMD(0x00), /* Power control 1 */
- SMART_CMD(0x10),
- SMART_DAT(0x10),
- SMART_DAT(0xB0),
- SMART_CMD(0x00), /* Power control 2 */
- SMART_CMD(0x11),
- SMART_DAT(0x01),
- SMART_DAT(0x30),
- SMART_CMD(0x00), /* Power control 3 */
- SMART_CMD(0x12),
- SMART_DAT(0x01),
- SMART_DAT(0x9E),
- SMART_CMD(0x00), /* Power control 4 */
- SMART_CMD(0x13),
- SMART_DAT(0x17),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* Power control 3 */
- SMART_CMD(0x12),
- SMART_DAT(0x01),
- SMART_DAT(0xBE),
- SMART_DELAY(100),
-
- /* display mode : 240*320 */
- SMART_CMD(0x00), /* RAM address set(H) 0*/
- SMART_CMD(0x20),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* RAM address set(V) 4*/
- SMART_CMD(0x21),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* Start of Window RAM address set(H) 8*/
- SMART_CMD(0x50),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* End of Window RAM address set(H) 12*/
- SMART_CMD(0x51),
- SMART_DAT(0x00),
- SMART_DAT(0xEF),
- SMART_CMD(0x00), /* Start of Window RAM address set(V) 16*/
- SMART_CMD(0x52),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* End of Window RAM address set(V) 20*/
- SMART_CMD(0x53),
- SMART_DAT(0x01),
- SMART_DAT(0x3F),
- SMART_CMD(0x00), /* Panel interface control 1 */
- SMART_CMD(0x90),
- SMART_DAT(0x00),
- SMART_DAT(0x1A),
- SMART_CMD(0x00), /* Panel interface control 2 */
- SMART_CMD(0x92),
- SMART_DAT(0x04),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* Panel interface control 3 */
- SMART_CMD(0x93),
- SMART_DAT(0x00),
- SMART_DAT(0x05),
- SMART_DELAY(20),
-};
-
-static uint16_t lcd_panel_on[] = {
- SMART_CMD(0x00),
- SMART_CMD(0x07),
- SMART_DAT(0x00),
- SMART_DAT(0x21),
- SMART_DELAY(1),
-
- SMART_CMD(0x00),
- SMART_CMD(0x07),
- SMART_DAT(0x00),
- SMART_DAT(0x61),
- SMART_DELAY(100),
-
- SMART_CMD(0x00),
- SMART_CMD(0x07),
- SMART_DAT(0x01),
- SMART_DAT(0x73),
- SMART_DELAY(1),
-};
-
-static uint16_t lcd_panel_off[] = {
- SMART_CMD(0x00),
- SMART_CMD(0x07),
- SMART_DAT(0x00),
- SMART_DAT(0x72),
- SMART_DELAY(40),
-
- SMART_CMD(0x00),
- SMART_CMD(0x07),
- SMART_DAT(0x00),
- SMART_DAT(0x01),
- SMART_DELAY(1),
-
- SMART_CMD(0x00),
- SMART_CMD(0x07),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_DELAY(1),
-};
-
-static uint16_t lcd_power_off[] = {
- SMART_CMD(0x00),
- SMART_CMD(0x10),
- SMART_DAT(0x00),
- SMART_DAT(0x80),
-
- SMART_CMD(0x00),
- SMART_CMD(0x11),
- SMART_DAT(0x01),
- SMART_DAT(0x60),
-
- SMART_CMD(0x00),
- SMART_CMD(0x12),
- SMART_DAT(0x01),
- SMART_DAT(0xAE),
- SMART_DELAY(40),
-
- SMART_CMD(0x00),
- SMART_CMD(0x10),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
-};
-
-static uint16_t update_framedata[] = {
- /* set display ram: 240*320 */
- SMART_CMD(0x00), /* RAM address set(H) 0*/
- SMART_CMD(0x20),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* RAM address set(V) 4*/
- SMART_CMD(0x21),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */
- SMART_CMD(0x50),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */
- SMART_CMD(0x51),
- SMART_DAT(0x00),
- SMART_DAT(0xEF),
- SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */
- SMART_CMD(0x52),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */
- SMART_CMD(0x53),
- SMART_DAT(0x01),
- SMART_DAT(0x3F),
-
- /* wait for vsync cmd before transferring frame data */
- SMART_CMD_WAIT_FOR_VSYNC,
-
- /* write ram */
- SMART_CMD(0x00),
- SMART_CMD(0x22),
-
- /* write frame data */
- SMART_CMD_WRITE_FRAME,
-};
-
-static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var)
-{
- static int pin_requested = 0;
- struct fb_info *info = container_of(var, struct fb_info, var);
- int err;
-
- if (!pin_requested) {
- err = gpio_request(GPIO_LCD_RESET, "lcd reset");
- if (err) {
- pr_err("failed to request gpio for LCD reset\n");
- return;
- }
-
- gpio_direction_output(GPIO_LCD_RESET, 0);
- pin_requested = 1;
- }
-
- if (on) {
- gpio_set_value(GPIO_LCD_RESET, 0); msleep(100);
- gpio_set_value(GPIO_LCD_RESET, 1); msleep(10);
-
- pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on));
- pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on));
- } else {
- pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off));
- pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off));
- }
-
- err = pxafb_smart_flush(info);
- if (err)
- pr_err("%s: timed out\n", __func__);
-}
-
-static void ltm022a97a_update(struct fb_info *info)
-{
- pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
- pxafb_smart_flush(info);
-}
-
-static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = {
- [0] = {
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .a0csrd_set_hld = 30,
- .a0cswr_set_hld = 30,
- .wr_pulse_width = 30,
- .rd_pulse_width = 30,
- .op_hold_time = 30,
- .cmd_inh_time = 60,
-
- /* L_LCLK_A0 and L_LCLK_RD active low */
- .sync = FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT,
- },
-};
-
-static struct pxafb_mach_info saar_lcd_info = {
- .modes = toshiba_ltm022a97a_modes,
- .num_modes = 1,
- .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
- .pxafb_lcd_power = ltm022a97a_lcd_power,
- .smart_update = ltm022a97a_update,
-};
-
-static void __init saar_init_lcd(void)
-{
- pxa_set_fb_info(NULL, &saar_lcd_info);
-}
-#else
-static inline void saar_init_lcd(void) {}
-#endif
-
-#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
-static struct da9034_backlight_pdata saar_da9034_backlight = {
- .output_current = 4, /* 4mA */
-};
-
-static struct da903x_subdev_info saar_da9034_subdevs[] = {
- [0] = {
- .name = "da903x-backlight",
- .id = DA9034_ID_WLED,
- .platform_data = &saar_da9034_backlight,
- },
-};
-
-static struct da903x_platform_data saar_da9034_info = {
- .num_subdevs = ARRAY_SIZE(saar_da9034_subdevs),
- .subdevs = saar_da9034_subdevs,
-};
-
-static struct i2c_board_info saar_i2c_info[] = {
- [0] = {
- .type = "da9034",
- .addr = 0x34,
- .platform_data = &saar_da9034_info,
- .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
- },
-};
-
-static void __init saar_init_i2c(void)
-{
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info));
-}
-#else
-static inline void saar_init_i2c(void) {}
-#endif
-
-#if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
-static struct mtd_partition saar_onenand_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = SZ_1M,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_128K,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "reserved",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_8M,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = (SZ_2M + SZ_1M),
- .mask_flags = 0,
- }, {
- .name = "filesystem",
- .offset = MTDPART_OFS_APPEND,
- .size = SZ_32M + SZ_16M,
- .mask_flags = 0,
- }
-};
-
-static struct onenand_platform_data saar_onenand_info = {
- .parts = saar_onenand_partitions,
- .nr_parts = ARRAY_SIZE(saar_onenand_partitions),
-};
-
-#define SMC_CS0_PHYS_BASE (0x10000000)
-
-static struct resource saar_resource_onenand[] = {
- [0] = {
- .start = SMC_CS0_PHYS_BASE,
- .end = SMC_CS0_PHYS_BASE + SZ_1M,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device saar_device_onenand = {
- .name = "onenand-flash",
- .id = -1,
- .dev = {
- .platform_data = &saar_onenand_info,
- },
- .resource = saar_resource_onenand,
- .num_resources = ARRAY_SIZE(saar_resource_onenand),
-};
-
-static void __init saar_init_onenand(void)
-{
- platform_device_register(&saar_device_onenand);
-}
-#else
-static void __init saar_init_onenand(void) {}
-#endif
-
-static void __init saar_init(void)
-{
- /* initialize MFP configurations */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- platform_device_register(&smc91x_device);
- saar_init_onenand();
-
- saar_init_i2c();
- saar_init_lcd();
-}
-
-MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
- /* Maintainer: Eric Miao <eric.miao@marvell.com> */
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = saar_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 83cfbb882a2d..d29bdcd5270e 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -24,7 +24,7 @@
#include <asm/mach-types.h>
#include "pm.h"
-#include <mach/pxa2xx-regs.h>
+#include "pxa2xx-regs.h"
#include "regs-rtc.h"
#include "sharpsl_pm.h"
@@ -170,10 +170,6 @@ extern int max1111_read_channel(int);
*/
int sharpsl_pm_pxa_read_max1111(int channel)
{
- /* Ugly, better move this function into another module */
- if (machine_is_tosa())
- return 0;
-
/* max1111 accepts channels from 0-3, however,
* it is encoded from 0-7 here in the code.
*/
@@ -894,7 +890,7 @@ static int sharpsl_pm_probe(struct platform_device *pdev)
return 0;
}
-static int sharpsl_pm_remove(struct platform_device *pdev)
+static void sharpsl_pm_remove(struct platform_device *pdev)
{
suspend_set_ops(NULL);
@@ -921,13 +917,11 @@ static int sharpsl_pm_remove(struct platform_device *pdev)
del_timer_sync(&sharpsl_pm.chrg_full_timer);
del_timer_sync(&sharpsl_pm.ac_timer);
-
- return 0;
}
static struct platform_driver sharpsl_pm_driver = {
.probe = sharpsl_pm_probe,
- .remove = sharpsl_pm_remove,
+ .remove_new = sharpsl_pm_remove,
.suspend = sharpsl_pm_suspend,
.resume = sharpsl_pm_resume,
.driver = {
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 6c5b3ffd2cd3..d58cf52e3848 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -13,13 +13,14 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/smemc.h>
-#include <mach/pxa2xx-regs.h>
+#include "smemc.h"
+#include "pxa2xx-regs.h"
#define MDREFR_KDIV 0x200a4000 // all banks
#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
-
+#define CCCR_N_MASK 0x00000380
+#define CCCR_M_MASK 0x00000060
+#define CCCR_L_MASK 0x0000001f
.text
#ifdef CONFIG_PXA3xx
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index 32e82cc92ea5..2d2a321d82f8 100644
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -8,9 +8,10 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
+#include <linux/soc/pxa/cpu.h>
-#include <mach/hardware.h>
-#include <mach/smemc.h>
+#include "smemc.h"
+#include <linux/soc/pxa/smemc.h>
#ifdef CONFIG_PM
static unsigned long msc[2];
@@ -70,3 +71,11 @@ static int __init smemc_init(void)
}
subsys_initcall(smemc_init);
#endif
+
+static const unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
+unsigned int pxa3xx_smemc_get_memclkdiv(void)
+{
+ unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
+
+ return df_clkdiv[(memclkcfg >> 16) & 0x3];
+}
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/smemc.h
index 9b2453a7ab23..9b2453a7ab23 100644
--- a/arch/arm/mach-pxa/include/mach/smemc.h
+++ b/arch/arm/mach-pxa/smemc.h
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index a648e7094e84..4325bdc2b9ff 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -25,6 +25,7 @@
#include <linux/spi/pxa2xx_spi.h>
#include <linux/mtd/sharpsl.h>
#include <linux/mtd/physmap.h>
+#include <linux/input-event-codes.h>
#include <linux/input/matrix_keypad.h>
#include <linux/regulator/machine.h>
#include <linux/io.h>
@@ -39,14 +40,13 @@
#include "pxa27x.h"
#include "pxa27x-udc.h"
-#include <mach/reset.h>
-#include <linux/platform_data/irda-pxaficp.h>
+#include "reset.h"
#include <linux/platform_data/mmc-pxamci.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <linux/platform_data/video-pxafb.h>
-#include <mach/spitz.h>
+#include "spitz.h"
#include "sharpsl_pm.h"
-#include <mach/smemc.h>
+#include "smemc.h"
#include "generic.h"
#include "devices.h"
@@ -578,7 +578,7 @@ static struct pxa2xx_spi_controller spitz_spi_info = {
};
static struct gpiod_lookup_table spitz_spi_gpio_table = {
- .dev_id = "pxa2xx-spi.2",
+ .dev_id = "spi2",
.table = {
GPIO_LOOKUP_IDX("gpio-pxa", SPITZ_GPIO_ADS7846_CS, "cs", 0, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("gpio-pxa", SPITZ_GPIO_LCDCON_CS, "cs", 1, GPIO_ACTIVE_LOW),
@@ -688,27 +688,6 @@ static inline void spitz_uhc_init(void) {}
#endif
/******************************************************************************
- * IrDA
- ******************************************************************************/
-#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
-static struct pxaficp_platform_data spitz_ficp_platform_data = {
- .transceiver_cap = IR_SIRMODE | IR_OFF,
-};
-
-static void __init spitz_irda_init(void)
-{
- if (machine_is_akita())
- spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
- else
- spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
-
- pxa_set_ficp_info(&spitz_ficp_platform_data);
-}
-#else
-static inline void spitz_irda_init(void) {}
-#endif
-
-/******************************************************************************
* Framebuffer
******************************************************************************/
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
@@ -962,11 +941,42 @@ static void __init spitz_i2c_init(void)
static inline void spitz_i2c_init(void) {}
#endif
+static struct gpiod_lookup_table spitz_audio_gpio_table = {
+ .dev_id = "spitz-audio",
+ .table = {
+ GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_L - SPITZ_SCP_GPIO_BASE,
+ "mute-l", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_R - SPITZ_SCP_GPIO_BASE,
+ "mute-r", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("sharp-scoop.1", SPITZ_GPIO_MIC_BIAS - SPITZ_SCP2_GPIO_BASE,
+ "mic", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table akita_audio_gpio_table = {
+ .dev_id = "spitz-audio",
+ .table = {
+ GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_L - SPITZ_SCP_GPIO_BASE,
+ "mute-l", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_R - SPITZ_SCP_GPIO_BASE,
+ "mute-r", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("i2c-max7310", AKITA_GPIO_MIC_BIAS - AKITA_IOEXP_GPIO_BASE,
+ "mic", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
/******************************************************************************
* Audio devices
******************************************************************************/
static inline void spitz_audio_init(void)
{
+ if (machine_is_akita())
+ gpiod_add_lookup_table(&akita_audio_gpio_table);
+ else
+ gpiod_add_lookup_table(&spitz_audio_gpio_table);
+
platform_device_register_simple("spitz-audio", -1, NULL, 0);
}
@@ -1011,7 +1021,6 @@ static void __init spitz_init(void)
spitz_leds_init();
spitz_mmc_init();
spitz_pcmcia_init();
- spitz_irda_init();
spitz_uhc_init();
spitz_lcd_init();
spitz_nor_init();
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/spitz.h
index 04828d8918aa..04828d8918aa 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/spitz.h
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 25a1f8c5a738..6689b67f9ce5 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -18,9 +18,8 @@
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/spitz.h>
+#include "spitz.h"
#include "pxa27x.h"
#include "sharpsl_pm.h"
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index eab1645bb4ad..ad32b9c0ebce 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -1,19 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* PXA27x standby mode
*
* Author: David Burrage
*
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2005 (c) MontaVista Software, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/pxa2xx-regs.h>
+#include "pxa2xx-regs.h"
.text
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
deleted file mode 100644
index a15eb3b9484d..000000000000
--- a/arch/arm/mach-pxa/tavorevb.c
+++ /dev/null
@@ -1,506 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/tavorevb.c
- *
- * Support for the Marvell PXA930 Evaluation Board
- *
- * Copyright (C) 2007-2008 Marvell International Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/gpio.h>
-#include <linux/smc91x.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa930.h"
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-
-#include "devices.h"
-#include "generic.h"
-
-/* Tavor EVB MFP configurations */
-static mfp_cfg_t tavorevb_mfp_cfg[] __initdata = {
- /* Ethernet */
- DF_nCS1_nCS3,
- GPIO47_GPIO,
-
- /* LCD */
- GPIO23_LCD_DD0,
- GPIO24_LCD_DD1,
- GPIO25_LCD_DD2,
- GPIO26_LCD_DD3,
- GPIO27_LCD_DD4,
- GPIO28_LCD_DD5,
- GPIO29_LCD_DD6,
- GPIO44_LCD_DD7,
- GPIO21_LCD_CS,
- GPIO22_LCD_CS2,
-
- GPIO17_LCD_FCLK_RD,
- GPIO18_LCD_LCLK_A0,
- GPIO19_LCD_PCLK_WR,
-
- /* LCD Backlight */
- GPIO43_PWM3, /* primary backlight */
- GPIO32_PWM0, /* secondary backlight */
-
- /* Keypad */
- GPIO0_KP_MKIN_0,
- GPIO2_KP_MKIN_1,
- GPIO4_KP_MKIN_2,
- GPIO6_KP_MKIN_3,
- GPIO8_KP_MKIN_4,
- GPIO10_KP_MKIN_5,
- GPIO12_KP_MKIN_6,
- GPIO1_KP_MKOUT_0,
- GPIO3_KP_MKOUT_1,
- GPIO5_KP_MKOUT_2,
- GPIO7_KP_MKOUT_3,
- GPIO9_KP_MKOUT_4,
- GPIO11_KP_MKOUT_5,
- GPIO13_KP_MKOUT_6,
-
- GPIO14_KP_DKIN_2,
- GPIO15_KP_DKIN_3,
-};
-
-#define TAVOREVB_ETH_PHYS (0x14000000)
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (TAVOREVB_ETH_PHYS + 0x300),
- .end = (TAVOREVB_ETH_PHYS + 0xfffff),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)),
- .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct smc91x_platdata tavorevb_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &tavorevb_smc91x_info,
- },
-};
-
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int tavorevb_matrix_key_map[] = {
- /* KEY(row, col, key_code) */
- KEY(0, 4, KEY_A), KEY(0, 5, KEY_B), KEY(0, 6, KEY_C),
- KEY(1, 4, KEY_E), KEY(1, 5, KEY_F), KEY(1, 6, KEY_G),
- KEY(2, 4, KEY_I), KEY(2, 5, KEY_J), KEY(2, 6, KEY_K),
- KEY(3, 4, KEY_M), KEY(3, 5, KEY_N), KEY(3, 6, KEY_O),
- KEY(4, 5, KEY_R), KEY(4, 6, KEY_S),
- KEY(5, 4, KEY_U), KEY(5, 4, KEY_V), KEY(5, 6, KEY_W),
-
- KEY(6, 4, KEY_Y), KEY(6, 5, KEY_Z),
-
- KEY(0, 3, KEY_0), KEY(2, 0, KEY_1), KEY(2, 1, KEY_2), KEY(2, 2, KEY_3),
- KEY(2, 3, KEY_4), KEY(1, 0, KEY_5), KEY(1, 1, KEY_6), KEY(1, 2, KEY_7),
- KEY(1, 3, KEY_8), KEY(0, 2, KEY_9),
-
- KEY(6, 6, KEY_SPACE),
- KEY(0, 0, KEY_KPASTERISK), /* * */
- KEY(0, 1, KEY_KPDOT), /* # */
-
- KEY(4, 1, KEY_UP),
- KEY(4, 3, KEY_DOWN),
- KEY(4, 0, KEY_LEFT),
- KEY(4, 2, KEY_RIGHT),
- KEY(6, 0, KEY_HOME),
- KEY(3, 2, KEY_END),
- KEY(6, 1, KEY_DELETE),
- KEY(5, 2, KEY_BACK),
- KEY(6, 3, KEY_CAPSLOCK), /* KEY_LEFTSHIFT), */
-
- KEY(4, 4, KEY_ENTER), /* scroll push */
- KEY(6, 2, KEY_ENTER), /* keypad action */
-
- KEY(3, 1, KEY_SEND),
- KEY(5, 3, KEY_RECORD),
- KEY(5, 0, KEY_VOLUMEUP),
- KEY(5, 1, KEY_VOLUMEDOWN),
-
- KEY(3, 0, KEY_F22), /* soft1 */
- KEY(3, 3, KEY_F23), /* soft2 */
-};
-
-static struct matrix_keymap_data tavorevb_matrix_keymap_data = {
- .keymap = tavorevb_matrix_key_map,
- .keymap_size = ARRAY_SIZE(tavorevb_matrix_key_map),
-};
-
-static struct pxa27x_keypad_platform_data tavorevb_keypad_info = {
- .matrix_key_rows = 7,
- .matrix_key_cols = 7,
- .matrix_keymap_data = &tavorevb_matrix_keymap_data,
- .debounce_interval = 30,
-};
-
-static void __init tavorevb_init_keypad(void)
-{
- pxa_set_keypad_info(&tavorevb_keypad_info);
-}
-#else
-static inline void tavorevb_init_keypad(void) {}
-#endif /* CONFIG_KEYBOARD_PXA27x || CONFIG_KEYBOARD_PXA27x_MODULE */
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pwm_lookup tavorevb_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.0", 1, "pwm-backlight.0", NULL, 100000,
- PWM_POLARITY_NORMAL),
- PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.1", NULL, 100000,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data tavorevb_backlight_data[] = {
- [0] = {
- /* primary backlight */
- .max_brightness = 100,
- .dft_brightness = 100,
- },
- [1] = {
- /* secondary backlight */
- .max_brightness = 100,
- .dft_brightness = 100,
- },
-};
-
-static struct platform_device tavorevb_backlight_devices[] = {
- [0] = {
- .name = "pwm-backlight",
- .id = 0,
- .dev = {
- .platform_data = &tavorevb_backlight_data[0],
- },
- },
- [1] = {
- .name = "pwm-backlight",
- .id = 1,
- .dev = {
- .platform_data = &tavorevb_backlight_data[1],
- },
- },
-};
-
-static uint16_t panel_init[] = {
- /* DSTB OUT */
- SMART_CMD(0x00),
- SMART_CMD_NOOP,
- SMART_DELAY(1),
-
- SMART_CMD(0x00),
- SMART_CMD_NOOP,
- SMART_DELAY(1),
-
- SMART_CMD(0x00),
- SMART_CMD_NOOP,
- SMART_DELAY(1),
-
- /* STB OUT */
- SMART_CMD(0x00),
- SMART_CMD(0x1D),
- SMART_DAT(0x00),
- SMART_DAT(0x05),
- SMART_DELAY(1),
-
- /* P-ON Init sequence */
- SMART_CMD(0x00), /* OSC ON */
- SMART_CMD(0x00),
- SMART_DAT(0x00),
- SMART_DAT(0x01),
- SMART_CMD(0x00),
- SMART_CMD(0x01), /* SOURCE DRIVER SHIFT DIRECTION and display RAM setting */
- SMART_DAT(0x01),
- SMART_DAT(0x27),
- SMART_CMD(0x00),
- SMART_CMD(0x02), /* LINE INV */
- SMART_DAT(0x02),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x03), /* IF mode(1) */
- SMART_DAT(0x01), /* 8bit smart mode(8-8),high speed write mode */
- SMART_DAT(0x30),
- SMART_CMD(0x07),
- SMART_CMD(0x00), /* RAM Write Mode */
- SMART_DAT(0x00),
- SMART_DAT(0x03),
- SMART_CMD(0x00),
-
- /* DISPLAY Setting, 262K, fixed(NO scroll), no split screen */
- SMART_CMD(0x07),
- SMART_DAT(0x40), /* 16/18/19 BPP */
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x08), /* BP, FP Seting, BP=2H, FP=3H */
- SMART_DAT(0x03),
- SMART_DAT(0x02),
- SMART_CMD(0x00),
- SMART_CMD(0x0C), /* IF mode(2), using internal clock & MPU */
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x0D), /* Frame setting, 1Min. Frequence, 16CLK */
- SMART_DAT(0x00),
- SMART_DAT(0x10),
- SMART_CMD(0x00),
- SMART_CMD(0x12), /* Timing(1),ASW W=4CLK, ASW ST=1CLK */
- SMART_DAT(0x03),
- SMART_DAT(0x02),
- SMART_CMD(0x00),
- SMART_CMD(0x13), /* Timing(2),OEV ST=0.5CLK, OEV ED=1CLK */
- SMART_DAT(0x01),
- SMART_DAT(0x02),
- SMART_CMD(0x00),
- SMART_CMD(0x14), /* Timing(3), ASW HOLD=0.5CLK */
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x15), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
- SMART_DAT(0x20),
- SMART_DAT(0x00),
- SMART_CMD(0x00),
- SMART_CMD(0x1C),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x03),
- SMART_CMD(0x00),
- SMART_DAT(0x04),
- SMART_DAT(0x03),
- SMART_CMD(0x03),
- SMART_CMD(0x01),
- SMART_DAT(0x03),
- SMART_DAT(0x04),
- SMART_CMD(0x03),
- SMART_CMD(0x02),
- SMART_DAT(0x04),
- SMART_DAT(0x03),
- SMART_CMD(0x03),
- SMART_CMD(0x03),
- SMART_DAT(0x03),
- SMART_DAT(0x03),
- SMART_CMD(0x03),
- SMART_CMD(0x04),
- SMART_DAT(0x01),
- SMART_DAT(0x01),
- SMART_CMD(0x03),
- SMART_CMD(0x05),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x04),
- SMART_CMD(0x02),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x04),
- SMART_CMD(0x03),
- SMART_DAT(0x01),
- SMART_DAT(0x3F),
- SMART_DELAY(0),
-
- /* DISP RAM setting: 240*320 */
- SMART_CMD(0x04), /* HADDR, START 0 */
- SMART_CMD(0x06),
- SMART_DAT(0x00),
- SMART_DAT(0x00), /* x1,3 */
- SMART_CMD(0x04), /* HADDR, END 4 */
- SMART_CMD(0x07),
- SMART_DAT(0x00),
- SMART_DAT(0xEF), /* x2, 7 */
- SMART_CMD(0x04), /* VADDR, START 8 */
- SMART_CMD(0x08),
- SMART_DAT(0x00), /* y1, 10 */
- SMART_DAT(0x00), /* y1, 11 */
- SMART_CMD(0x04), /* VADDR, END 12 */
- SMART_CMD(0x09),
- SMART_DAT(0x01), /* y2, 14 */
- SMART_DAT(0x3F), /* y2, 15 */
- SMART_CMD(0x02), /* RAM ADDR SETTING 16 */
- SMART_CMD(0x00),
- SMART_DAT(0x00),
- SMART_DAT(0x00), /* x1, 19 */
- SMART_CMD(0x02), /* RAM ADDR SETTING 20 */
- SMART_CMD(0x01),
- SMART_DAT(0x00), /* y1, 22 */
- SMART_DAT(0x00), /* y1, 23 */
-};
-
-static uint16_t panel_on[] = {
- /* Power-IC ON */
- SMART_CMD(0x01),
- SMART_CMD(0x02),
- SMART_DAT(0x07),
- SMART_DAT(0x7D),
- SMART_CMD(0x01),
- SMART_CMD(0x03),
- SMART_DAT(0x00),
- SMART_DAT(0x05),
- SMART_CMD(0x01),
- SMART_CMD(0x04),
- SMART_DAT(0x00),
- SMART_DAT(0x00),
- SMART_CMD(0x01),
- SMART_CMD(0x05),
- SMART_DAT(0x00),
- SMART_DAT(0x15),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0xC0),
- SMART_DAT(0x10),
- SMART_DELAY(30),
-
- /* DISP ON */
- SMART_CMD(0x01),
- SMART_CMD(0x01),
- SMART_DAT(0x00),
- SMART_DAT(0x01),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0xFF),
- SMART_DAT(0xFE),
- SMART_DELAY(150),
-};
-
-static uint16_t panel_off[] = {
- SMART_CMD(0x00),
- SMART_CMD(0x1E),
- SMART_DAT(0x00),
- SMART_DAT(0x0A),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0xFF),
- SMART_DAT(0xEE),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0xF8),
- SMART_DAT(0x12),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0xE8),
- SMART_DAT(0x11),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0xC0),
- SMART_DAT(0x11),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0x40),
- SMART_DAT(0x11),
- SMART_CMD(0x01),
- SMART_CMD(0x00),
- SMART_DAT(0x00),
- SMART_DAT(0x10),
-};
-
-static uint16_t update_framedata[] = {
- /* write ram */
- SMART_CMD(0x02),
- SMART_CMD(0x02),
-
- /* write frame data */
- SMART_CMD_WRITE_FRAME,
-};
-
-static void ltm020d550_lcd_power(int on, struct fb_var_screeninfo *var)
-{
- struct fb_info *info = container_of(var, struct fb_info, var);
-
- if (on) {
- pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_init));
- pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_on));
- } else {
- pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_off));
- }
-
- if (pxafb_smart_flush(info))
- pr_err("%s: timed out\n", __func__);
-}
-
-static void ltm020d550_update(struct fb_info *info)
-{
- pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
- pxafb_smart_flush(info);
-}
-
-static struct pxafb_mode_info toshiba_ltm020d550_modes[] = {
- [0] = {
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .a0csrd_set_hld = 30,
- .a0cswr_set_hld = 30,
- .wr_pulse_width = 30,
- .rd_pulse_width = 170,
- .op_hold_time = 30,
- .cmd_inh_time = 60,
-
- /* L_LCLK_A0 and L_LCLK_RD active low */
- .sync = FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT,
- },
-};
-
-static struct pxafb_mach_info tavorevb_lcd_info = {
- .modes = toshiba_ltm020d550_modes,
- .num_modes = 1,
- .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
- .pxafb_lcd_power = ltm020d550_lcd_power,
- .smart_update = ltm020d550_update,
-};
-
-static void __init tavorevb_init_lcd(void)
-{
- pwm_add_table(tavorevb_pwm_lookup, ARRAY_SIZE(tavorevb_pwm_lookup));
- platform_device_register(&tavorevb_backlight_devices[0]);
- platform_device_register(&tavorevb_backlight_devices[1]);
- pxa_set_fb_info(NULL, &tavorevb_lcd_info);
-}
-#else
-static inline void tavorevb_init_lcd(void) {}
-#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
-
-static void __init tavorevb_init(void)
-{
- /* initialize MFP configurations */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- platform_device_register(&smc91x_device);
-
- tavorevb_init_lcd();
- tavorevb_init_keypad();
-}
-
-MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
- /* Maintainer: Eric Miao <eric.miao@marvell.com> */
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = tavorevb_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c
deleted file mode 100644
index c9541632b8b1..000000000000
--- a/arch/arm/mach-pxa/tosa-bt.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Bluetooth built-in chip control
- *
- * Copyright (c) 2008 Dmitry Baryshkov
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/rfkill.h>
-
-#include "tosa_bt.h"
-
-static void tosa_bt_on(struct tosa_bt_data *data)
-{
- gpio_set_value(data->gpio_reset, 0);
- gpio_set_value(data->gpio_pwr, 1);
- gpio_set_value(data->gpio_reset, 1);
- mdelay(20);
- gpio_set_value(data->gpio_reset, 0);
-}
-
-static void tosa_bt_off(struct tosa_bt_data *data)
-{
- gpio_set_value(data->gpio_reset, 1);
- mdelay(10);
- gpio_set_value(data->gpio_pwr, 0);
- gpio_set_value(data->gpio_reset, 0);
-}
-
-static int tosa_bt_set_block(void *data, bool blocked)
-{
- pr_info("BT_RADIO going: %s\n", blocked ? "off" : "on");
-
- if (!blocked) {
- pr_info("TOSA_BT: going ON\n");
- tosa_bt_on(data);
- } else {
- pr_info("TOSA_BT: going OFF\n");
- tosa_bt_off(data);
- }
-
- return 0;
-}
-
-static const struct rfkill_ops tosa_bt_rfkill_ops = {
- .set_block = tosa_bt_set_block,
-};
-
-static int tosa_bt_probe(struct platform_device *dev)
-{
- int rc;
- struct rfkill *rfk;
-
- struct tosa_bt_data *data = dev->dev.platform_data;
-
- rc = gpio_request(data->gpio_reset, "Bluetooth reset");
- if (rc)
- goto err_reset;
- rc = gpio_direction_output(data->gpio_reset, 0);
- if (rc)
- goto err_reset_dir;
- rc = gpio_request(data->gpio_pwr, "Bluetooth power");
- if (rc)
- goto err_pwr;
- rc = gpio_direction_output(data->gpio_pwr, 0);
- if (rc)
- goto err_pwr_dir;
-
- rfk = rfkill_alloc("tosa-bt", &dev->dev, RFKILL_TYPE_BLUETOOTH,
- &tosa_bt_rfkill_ops, data);
- if (!rfk) {
- rc = -ENOMEM;
- goto err_rfk_alloc;
- }
-
- rc = rfkill_register(rfk);
- if (rc)
- goto err_rfkill;
-
- platform_set_drvdata(dev, rfk);
-
- return 0;
-
-err_rfkill:
- rfkill_destroy(rfk);
-err_rfk_alloc:
- tosa_bt_off(data);
-err_pwr_dir:
- gpio_free(data->gpio_pwr);
-err_pwr:
-err_reset_dir:
- gpio_free(data->gpio_reset);
-err_reset:
- return rc;
-}
-
-static int tosa_bt_remove(struct platform_device *dev)
-{
- struct tosa_bt_data *data = dev->dev.platform_data;
- struct rfkill *rfk = platform_get_drvdata(dev);
-
- platform_set_drvdata(dev, NULL);
-
- if (rfk) {
- rfkill_unregister(rfk);
- rfkill_destroy(rfk);
- }
- rfk = NULL;
-
- tosa_bt_off(data);
-
- gpio_free(data->gpio_pwr);
- gpio_free(data->gpio_reset);
-
- return 0;
-}
-
-static struct platform_driver tosa_bt_driver = {
- .probe = tosa_bt_probe,
- .remove = tosa_bt_remove,
-
- .driver = {
- .name = "tosa-bt",
- },
-};
-module_platform_driver(tosa_bt_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Dmitry Baryshkov");
-MODULE_DESCRIPTION("Bluetooth built-in chip control");
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
deleted file mode 100644
index 431709725d02..000000000000
--- a/arch/arm/mach-pxa/tosa.c
+++ /dev/null
@@ -1,980 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for Sharp SL-C6000x PDAs
- * Model: (Tosa)
- *
- * Copyright (c) 2005 Dirk Opfer
- *
- * Based on code written by Sharp/Lineo for 2.4 kernels
- */
-
-#include <linux/clkdev.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/major.h>
-#include <linux/fs.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/mmc/host.h>
-#include <linux/mfd/tc6393xb.h>
-#include <linux/mfd/tmio.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/pm.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/power/gpio-charger.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/reboot.h>
-#include <linux/memblock.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include "pxa25x.h"
-#include <mach/reset.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include "udc.h"
-#include "tosa_bt.h"
-#include <mach/audio.h>
-#include <mach/smemc.h>
-
-#include <asm/mach/arch.h>
-#include <mach/tosa.h>
-
-#include <asm/hardware/scoop.h>
-#include <asm/mach/sharpsl_param.h>
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned long tosa_pin_config[] = {
- GPIO78_nCS_2, /* Scoop */
- GPIO80_nCS_4, /* tg6393xb */
- GPIO33_nCS_5, /* Scoop */
-
- // GPIO76 CARD_VCC_ON1
-
- GPIO19_GPIO, /* Reset out */
- GPIO1_RST | WAKEUP_ON_EDGE_FALL,
-
- GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* WAKE_UP */
- GPIO2_GPIO | WAKEUP_ON_EDGE_BOTH, /* AC_IN */
- GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* RECORD */
- GPIO4_GPIO | WAKEUP_ON_EDGE_FALL, /* SYNC */
- GPIO20_GPIO, /* EAR_IN */
- GPIO22_GPIO, /* On */
-
- GPIO5_GPIO, /* USB_IN */
- GPIO32_GPIO, /* Pen IRQ */
-
- GPIO7_GPIO, /* Jacket Detect */
- GPIO14_GPIO, /* BAT0_CRG */
- GPIO12_GPIO, /* BAT1_CRG */
- GPIO17_GPIO, /* BAT0_LOW */
- GPIO84_GPIO, /* BAT1_LOW */
- GPIO38_GPIO, /* BAT_LOCK */
-
- GPIO11_3_6MHz,
- GPIO15_GPIO, /* TC6393XB IRQ */
- GPIO18_RDY,
- GPIO27_GPIO, /* LCD Sync */
-
- /* MMC */
- GPIO6_MMC_CLK,
- GPIO8_MMC_CS0,
- GPIO9_GPIO, /* Detect */
- GPIO10_GPIO, /* nSD_INT */
-
- /* CF */
- GPIO13_GPIO, /* CD_IRQ */
- GPIO21_GPIO, /* Main Slot IRQ */
- GPIO36_GPIO, /* Jacket Slot IRQ */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* AC97 */
- GPIO31_AC97_SYNC,
- GPIO30_AC97_SDATA_OUT,
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- // GPIO79 nAUD_IRQ
-
- /* FFUART */
- GPIO34_FFUART_RXD,
- GPIO35_FFUART_CTS,
- GPIO37_FFUART_DSR,
- GPIO39_FFUART_TXD,
- GPIO40_FFUART_DTR,
- GPIO41_FFUART_RTS,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* Keybd */
- GPIO58_GPIO | MFP_LPM_DRIVE_LOW, /* Column 0 */
- GPIO59_GPIO | MFP_LPM_DRIVE_LOW, /* Column 1 */
- GPIO60_GPIO | MFP_LPM_DRIVE_LOW, /* Column 2 */
- GPIO61_GPIO | MFP_LPM_DRIVE_LOW, /* Column 3 */
- GPIO62_GPIO | MFP_LPM_DRIVE_LOW, /* Column 4 */
- GPIO63_GPIO | MFP_LPM_DRIVE_LOW, /* Column 5 */
- GPIO64_GPIO | MFP_LPM_DRIVE_LOW, /* Column 6 */
- GPIO65_GPIO | MFP_LPM_DRIVE_LOW, /* Column 7 */
- GPIO66_GPIO | MFP_LPM_DRIVE_LOW, /* Column 8 */
- GPIO67_GPIO | MFP_LPM_DRIVE_LOW, /* Column 9 */
- GPIO68_GPIO | MFP_LPM_DRIVE_LOW, /* Column 10 */
- GPIO69_GPIO | MFP_LPM_DRIVE_LOW, /* Row 0 */
- GPIO70_GPIO | MFP_LPM_DRIVE_LOW, /* Row 1 */
- GPIO71_GPIO | MFP_LPM_DRIVE_LOW, /* Row 2 */
- GPIO72_GPIO | MFP_LPM_DRIVE_LOW, /* Row 3 */
- GPIO73_GPIO | MFP_LPM_DRIVE_LOW, /* Row 4 */
- GPIO74_GPIO | MFP_LPM_DRIVE_LOW, /* Row 5 */
- GPIO75_GPIO | MFP_LPM_DRIVE_LOW, /* Row 6 */
-
- /* SPI */
- GPIO81_SSP2_CLK_OUT,
- GPIO82_SSP2_FRM_OUT,
- GPIO83_SSP2_TXD,
-
- /* IrDA is managed in other way */
- GPIO46_GPIO,
- GPIO47_GPIO,
-};
-
-/*
- * SCOOP Device
- */
-static struct resource tosa_scoop_resources[] = {
- [0] = {
- .start = TOSA_CF_PHYS,
- .end = TOSA_CF_PHYS + 0xfff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct scoop_config tosa_scoop_setup = {
- .io_dir = TOSA_SCOOP_IO_DIR,
- .gpio_base = TOSA_SCOOP_GPIO_BASE,
-};
-
-static struct platform_device tosascoop_device = {
- .name = "sharp-scoop",
- .id = 0,
- .dev = {
- .platform_data = &tosa_scoop_setup,
- },
- .num_resources = ARRAY_SIZE(tosa_scoop_resources),
- .resource = tosa_scoop_resources,
-};
-
-
-/*
- * SCOOP Device Jacket
- */
-static struct resource tosa_scoop_jc_resources[] = {
- [0] = {
- .start = TOSA_SCOOP_PHYS + 0x40,
- .end = TOSA_SCOOP_PHYS + 0xfff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct scoop_config tosa_scoop_jc_setup = {
- .io_dir = TOSA_SCOOP_JC_IO_DIR,
- .gpio_base = TOSA_SCOOP_JC_GPIO_BASE,
-};
-
-static struct platform_device tosascoop_jc_device = {
- .name = "sharp-scoop",
- .id = 1,
- .dev = {
- .platform_data = &tosa_scoop_jc_setup,
- .parent = &tosascoop_device.dev,
- },
- .num_resources = ARRAY_SIZE(tosa_scoop_jc_resources),
- .resource = tosa_scoop_jc_resources,
-};
-
-/*
- * PCMCIA
- */
-static struct scoop_pcmcia_dev tosa_pcmcia_scoop[] = {
-{
- .dev = &tosascoop_device.dev,
- .irq = TOSA_IRQ_GPIO_CF_IRQ,
- .cd_irq = TOSA_IRQ_GPIO_CF_CD,
- .cd_irq_str = "PCMCIA0 CD",
-},{
- .dev = &tosascoop_jc_device.dev,
- .irq = TOSA_IRQ_GPIO_JC_CF_IRQ,
- .cd_irq = -1,
-},
-};
-
-static struct scoop_pcmcia_config tosa_pcmcia_config = {
- .devs = &tosa_pcmcia_scoop[0],
- .num_devs = 2,
-};
-
-/*
- * USB Device Controller
- */
-static struct gpiod_lookup_table tosa_udc_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_USB_IN,
- "vbus", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_USB_PULLUP,
- "pullup", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device tosa_gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-/*
- * MMC/SD Device
- */
-static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void *data)
-{
- int err;
-
- err = gpio_request(TOSA_GPIO_nSD_INT, "SD Int");
- if (err) {
- printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n");
- goto err_gpio_int;
- }
- err = gpio_direction_input(TOSA_GPIO_nSD_INT);
- if (err)
- goto err_gpio_int_dir;
-
- return 0;
-
-err_gpio_int_dir:
- gpio_free(TOSA_GPIO_nSD_INT);
-err_gpio_int:
- return err;
-}
-
-static void tosa_mci_exit(struct device *dev, void *data)
-{
- gpio_free(TOSA_GPIO_nSD_INT);
-}
-
-static struct pxamci_platform_data tosa_mci_platform_data = {
- .detect_delay_ms = 250,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .init = tosa_mci_init,
- .exit = tosa_mci_exit,
-};
-
-static struct gpiod_lookup_table tosa_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_nSD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_SD_WP,
- "wp", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_PWR_ON,
- "power", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/*
- * Irda
- */
-static void tosa_irda_transceiver_mode(struct device *dev, int mode)
-{
- if (mode & IR_OFF) {
- gpio_set_value(TOSA_GPIO_IR_POWERDWN, 0);
- pxa2xx_transceiver_mode(dev, mode);
- gpio_direction_output(TOSA_GPIO_IRDA_TX, 0);
- } else {
- pxa2xx_transceiver_mode(dev, mode);
- gpio_set_value(TOSA_GPIO_IR_POWERDWN, 1);
- }
-}
-
-static int tosa_irda_startup(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(TOSA_GPIO_IRDA_TX, "IrDA TX");
- if (ret)
- goto err_tx;
- ret = gpio_direction_output(TOSA_GPIO_IRDA_TX, 0);
- if (ret)
- goto err_tx_dir;
-
- ret = gpio_request(TOSA_GPIO_IR_POWERDWN, "IrDA powerdown");
- if (ret)
- goto err_pwr;
-
- ret = gpio_direction_output(TOSA_GPIO_IR_POWERDWN, 0);
- if (ret)
- goto err_pwr_dir;
-
- tosa_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF);
-
- return 0;
-
-err_pwr_dir:
- gpio_free(TOSA_GPIO_IR_POWERDWN);
-err_pwr:
-err_tx_dir:
- gpio_free(TOSA_GPIO_IRDA_TX);
-err_tx:
- return ret;
-}
-
-static void tosa_irda_shutdown(struct device *dev)
-{
- tosa_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF);
- gpio_free(TOSA_GPIO_IR_POWERDWN);
- gpio_free(TOSA_GPIO_IRDA_TX);
-}
-
-static struct pxaficp_platform_data tosa_ficp_platform_data = {
- .gpio_pwdown = -1,
- .transceiver_cap = IR_SIRMODE | IR_OFF,
- .transceiver_mode = tosa_irda_transceiver_mode,
- .startup = tosa_irda_startup,
- .shutdown = tosa_irda_shutdown,
-};
-
-/*
- * Tosa AC IN
- */
-static struct gpiod_lookup_table tosa_power_gpiod_table = {
- .dev_id = "gpio-charger",
- .table = {
- GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_AC_IN,
- NULL, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static char *tosa_ac_supplied_to[] = {
- "main-battery",
- "backup-battery",
- "jacket-battery",
-};
-
-static struct gpio_charger_platform_data tosa_power_data = {
- .name = "charger",
- .type = POWER_SUPPLY_TYPE_MAINS,
- .supplied_to = tosa_ac_supplied_to,
- .num_supplicants = ARRAY_SIZE(tosa_ac_supplied_to),
-};
-
-static struct resource tosa_power_resource[] = {
- {
- .name = "ac",
- .start = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN),
- .end = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN),
- .flags = IORESOURCE_IRQ |
- IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device tosa_power_device = {
- .name = "gpio-charger",
- .id = -1,
- .dev.platform_data = &tosa_power_data,
- .resource = tosa_power_resource,
- .num_resources = ARRAY_SIZE(tosa_power_resource),
-};
-
-/*
- * Tosa Keyboard
- */
-static const uint32_t tosakbd_keymap[] = {
- KEY(0, 1, KEY_W),
- KEY(0, 5, KEY_K),
- KEY(0, 6, KEY_BACKSPACE),
- KEY(0, 7, KEY_P),
- KEY(1, 0, KEY_Q),
- KEY(1, 1, KEY_E),
- KEY(1, 2, KEY_T),
- KEY(1, 3, KEY_Y),
- KEY(1, 5, KEY_O),
- KEY(1, 6, KEY_I),
- KEY(1, 7, KEY_COMMA),
- KEY(2, 0, KEY_A),
- KEY(2, 1, KEY_D),
- KEY(2, 2, KEY_G),
- KEY(2, 3, KEY_U),
- KEY(2, 5, KEY_L),
- KEY(2, 6, KEY_ENTER),
- KEY(2, 7, KEY_DOT),
- KEY(3, 0, KEY_Z),
- KEY(3, 1, KEY_C),
- KEY(3, 2, KEY_V),
- KEY(3, 3, KEY_J),
- KEY(3, 4, TOSA_KEY_ADDRESSBOOK),
- KEY(3, 5, TOSA_KEY_CANCEL),
- KEY(3, 6, TOSA_KEY_CENTER),
- KEY(3, 7, TOSA_KEY_OK),
- KEY(3, 8, KEY_LEFTSHIFT),
- KEY(4, 0, KEY_S),
- KEY(4, 1, KEY_R),
- KEY(4, 2, KEY_B),
- KEY(4, 3, KEY_N),
- KEY(4, 4, TOSA_KEY_CALENDAR),
- KEY(4, 5, TOSA_KEY_HOMEPAGE),
- KEY(4, 6, KEY_LEFTCTRL),
- KEY(4, 7, TOSA_KEY_LIGHT),
- KEY(4, 9, KEY_RIGHTSHIFT),
- KEY(5, 0, KEY_TAB),
- KEY(5, 1, KEY_SLASH),
- KEY(5, 2, KEY_H),
- KEY(5, 3, KEY_M),
- KEY(5, 4, TOSA_KEY_MENU),
- KEY(5, 6, KEY_UP),
- KEY(5, 10, TOSA_KEY_FN),
- KEY(6, 0, KEY_X),
- KEY(6, 1, KEY_F),
- KEY(6, 2, KEY_SPACE),
- KEY(6, 3, KEY_APOSTROPHE),
- KEY(6, 4, TOSA_KEY_MAIL),
- KEY(6, 5, KEY_LEFT),
- KEY(6, 6, KEY_DOWN),
- KEY(6, 7, KEY_RIGHT),
-};
-
-static struct matrix_keymap_data tosakbd_keymap_data = {
- .keymap = tosakbd_keymap,
- .keymap_size = ARRAY_SIZE(tosakbd_keymap),
-};
-
-static const int tosakbd_col_gpios[] =
- { 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68 };
-static const int tosakbd_row_gpios[] =
- { 69, 70, 71, 72, 73, 74, 75 };
-
-static struct matrix_keypad_platform_data tosakbd_pdata = {
- .keymap_data = &tosakbd_keymap_data,
- .row_gpios = tosakbd_row_gpios,
- .col_gpios = tosakbd_col_gpios,
- .num_row_gpios = ARRAY_SIZE(tosakbd_row_gpios),
- .num_col_gpios = ARRAY_SIZE(tosakbd_col_gpios),
- .col_scan_delay_us = 10,
- .debounce_ms = 10,
- .wakeup = 1,
-};
-
-static struct platform_device tosakbd_device = {
- .name = "matrix-keypad",
- .id = -1,
- .dev = {
- .platform_data = &tosakbd_pdata,
- },
-};
-
-static struct gpio_keys_button tosa_gpio_keys[] = {
- /*
- * Two following keys are directly tied to "ON" button of tosa. Why?
- * The first one can be used as a wakeup source, the second can't;
- * also the first one is OR of ac_powered and on_button.
- */
- {
- .type = EV_PWR,
- .code = KEY_RESERVED,
- .gpio = TOSA_GPIO_POWERON,
- .desc = "Poweron",
- .wakeup = 1,
- .active_low = 1,
- },
- {
- .type = EV_PWR,
- .code = KEY_SUSPEND,
- .gpio = TOSA_GPIO_ON_KEY,
- .desc = "On key",
- /*
- * can't be used as wakeup
- * .wakeup = 1,
- */
- .active_low = 1,
- },
- {
- .type = EV_KEY,
- .code = TOSA_KEY_RECORD,
- .gpio = TOSA_GPIO_RECORD_BTN,
- .desc = "Record Button",
- .wakeup = 1,
- .active_low = 1,
- },
- {
- .type = EV_KEY,
- .code = TOSA_KEY_SYNC,
- .gpio = TOSA_GPIO_SYNC,
- .desc = "Sync Button",
- .wakeup = 1,
- .active_low = 1,
- },
- {
- .type = EV_SW,
- .code = SW_HEADPHONE_INSERT,
- .gpio = TOSA_GPIO_EAR_IN,
- .desc = "HeadPhone insert",
- .active_low = 1,
- .debounce_interval = 300,
- },
-};
-
-static struct gpio_keys_platform_data tosa_gpio_keys_platform_data = {
- .buttons = tosa_gpio_keys,
- .nbuttons = ARRAY_SIZE(tosa_gpio_keys),
-};
-
-static struct platform_device tosa_gpio_keys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &tosa_gpio_keys_platform_data,
- },
-};
-
-/*
- * Tosa LEDs
- */
-static struct gpio_led tosa_gpio_leds[] = {
- {
- .name = "tosa:amber:charge",
- .default_trigger = "main-battery-charging",
- .gpio = TOSA_GPIO_CHRG_ERR_LED,
- },
- {
- .name = "tosa:green:mail",
- .default_trigger = "nand-disk",
- .gpio = TOSA_GPIO_NOTE_LED,
- },
- {
- .name = "tosa:dual:wlan",
- .default_trigger = "none",
- .gpio = TOSA_GPIO_WLAN_LED,
- },
- {
- .name = "tosa:blue:bluetooth",
- .default_trigger = "tosa-bt",
- .gpio = TOSA_GPIO_BT_LED,
- },
-};
-
-static struct gpio_led_platform_data tosa_gpio_leds_platform_data = {
- .leds = tosa_gpio_leds,
- .num_leds = ARRAY_SIZE(tosa_gpio_leds),
-};
-
-static struct platform_device tosaled_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &tosa_gpio_leds_platform_data,
- },
-};
-
-/*
- * Toshiba Mobile IO Controller
- */
-static struct resource tc6393xb_resources[] = {
- [0] = {
- .start = TOSA_LCDC_PHYS,
- .end = TOSA_LCDC_PHYS + 0x3ffffff,
- .flags = IORESOURCE_MEM,
- },
-
- [1] = {
- .start = TOSA_IRQ_GPIO_TC6393XB_INT,
- .end = TOSA_IRQ_GPIO_TC6393XB_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-
-static int tosa_tc6393xb_enable(struct platform_device *dev)
-{
- int rc;
-
- rc = gpio_request(TOSA_GPIO_TC6393XB_REST_IN, "tc6393xb #pclr");
- if (rc)
- goto err_req_pclr;
- rc = gpio_request(TOSA_GPIO_TC6393XB_SUSPEND, "tc6393xb #suspend");
- if (rc)
- goto err_req_suspend;
- rc = gpio_request(TOSA_GPIO_TC6393XB_L3V_ON, "tc6393xb l3v");
- if (rc)
- goto err_req_l3v;
- rc = gpio_direction_output(TOSA_GPIO_TC6393XB_L3V_ON, 0);
- if (rc)
- goto err_dir_l3v;
- rc = gpio_direction_output(TOSA_GPIO_TC6393XB_SUSPEND, 0);
- if (rc)
- goto err_dir_suspend;
- rc = gpio_direction_output(TOSA_GPIO_TC6393XB_REST_IN, 0);
- if (rc)
- goto err_dir_pclr;
-
- mdelay(1);
-
- gpio_set_value(TOSA_GPIO_TC6393XB_SUSPEND, 1);
-
- mdelay(10);
-
- gpio_set_value(TOSA_GPIO_TC6393XB_REST_IN, 1);
- gpio_set_value(TOSA_GPIO_TC6393XB_L3V_ON, 1);
-
- return 0;
-err_dir_pclr:
-err_dir_suspend:
-err_dir_l3v:
- gpio_free(TOSA_GPIO_TC6393XB_L3V_ON);
-err_req_l3v:
- gpio_free(TOSA_GPIO_TC6393XB_SUSPEND);
-err_req_suspend:
- gpio_free(TOSA_GPIO_TC6393XB_REST_IN);
-err_req_pclr:
- return rc;
-}
-
-static int tosa_tc6393xb_disable(struct platform_device *dev)
-{
- gpio_free(TOSA_GPIO_TC6393XB_L3V_ON);
- gpio_free(TOSA_GPIO_TC6393XB_SUSPEND);
- gpio_free(TOSA_GPIO_TC6393XB_REST_IN);
-
- return 0;
-}
-
-static int tosa_tc6393xb_resume(struct platform_device *dev)
-{
- gpio_set_value(TOSA_GPIO_TC6393XB_SUSPEND, 1);
- mdelay(10);
- gpio_set_value(TOSA_GPIO_TC6393XB_L3V_ON, 1);
- mdelay(10);
-
- return 0;
-}
-
-static int tosa_tc6393xb_suspend(struct platform_device *dev)
-{
- gpio_set_value(TOSA_GPIO_TC6393XB_L3V_ON, 0);
- gpio_set_value(TOSA_GPIO_TC6393XB_SUSPEND, 0);
- return 0;
-}
-
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr tosa_tc6393xb_nand_bbt = {
- .options = 0,
- .offs = 4,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-static const char * const probes[] = {
- "cmdlinepart",
- "ofpart",
- "sharpslpart",
- NULL,
-};
-
-static struct tmio_nand_data tosa_tc6393xb_nand_config = {
- .badblock_pattern = &tosa_tc6393xb_nand_bbt,
- .part_parsers = probes,
-};
-
-static int tosa_tc6393xb_setup(struct platform_device *dev)
-{
- int rc;
-
- rc = gpio_request(TOSA_GPIO_CARD_VCC_ON, "CARD_VCC_ON");
- if (rc)
- goto err_req;
-
- rc = gpio_direction_output(TOSA_GPIO_CARD_VCC_ON, 1);
- if (rc)
- goto err_dir;
-
- return rc;
-
-err_dir:
- gpio_free(TOSA_GPIO_CARD_VCC_ON);
-err_req:
- return rc;
-}
-
-static void tosa_tc6393xb_teardown(struct platform_device *dev)
-{
- gpio_free(TOSA_GPIO_CARD_VCC_ON);
-}
-
-#ifdef CONFIG_MFD_TC6393XB
-static struct fb_videomode tosa_tc6393xb_lcd_mode[] = {
- {
- .xres = 480,
- .yres = 640,
- .pixclock = 0x002cdf00,/* PLL divisor */
- .left_margin = 0x004c,
- .right_margin = 0x005b,
- .upper_margin = 0x0001,
- .lower_margin = 0x000d,
- .hsync_len = 0x0002,
- .vsync_len = 0x0001,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- },{
- .xres = 240,
- .yres = 320,
- .pixclock = 0x00e7f203,/* PLL divisor */
- .left_margin = 0x0024,
- .right_margin = 0x002f,
- .upper_margin = 0x0001,
- .lower_margin = 0x000d,
- .hsync_len = 0x0002,
- .vsync_len = 0x0001,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- }
-};
-
-static struct tmio_fb_data tosa_tc6393xb_fb_config = {
- .lcd_set_power = tc6393xb_lcd_set_power,
- .lcd_mode = tc6393xb_lcd_mode,
- .num_modes = ARRAY_SIZE(tosa_tc6393xb_lcd_mode),
- .modes = &tosa_tc6393xb_lcd_mode[0],
- .height = 82,
- .width = 60,
-};
-#endif
-
-static struct tc6393xb_platform_data tosa_tc6393xb_data = {
- .scr_pll2cr = 0x0cc1,
- .scr_gper = 0x3300,
-
- .irq_base = IRQ_BOARD_START,
- .gpio_base = TOSA_TC6393XB_GPIO_BASE,
- .setup = tosa_tc6393xb_setup,
- .teardown = tosa_tc6393xb_teardown,
-
- .enable = tosa_tc6393xb_enable,
- .disable = tosa_tc6393xb_disable,
- .suspend = tosa_tc6393xb_suspend,
- .resume = tosa_tc6393xb_resume,
-
- .nand_data = &tosa_tc6393xb_nand_config,
-#ifdef CONFIG_MFD_TC6393XB
- .fb_data = &tosa_tc6393xb_fb_config,
-#endif
-
- .resume_restore = 1,
-};
-
-
-static struct platform_device tc6393xb_device = {
- .name = "tc6393xb",
- .id = -1,
- .dev = {
- .platform_data = &tosa_tc6393xb_data,
- },
- .num_resources = ARRAY_SIZE(tc6393xb_resources),
- .resource = tc6393xb_resources,
-};
-
-static struct tosa_bt_data tosa_bt_data = {
- .gpio_pwr = TOSA_GPIO_BT_PWR_EN,
- .gpio_reset = TOSA_GPIO_BT_RESET,
-};
-
-static struct platform_device tosa_bt_device = {
- .name = "tosa-bt",
- .id = -1,
- .dev.platform_data = &tosa_bt_data,
-};
-
-static struct pxa2xx_spi_controller pxa_ssp_master_info = {
- .num_chipselect = 1,
-};
-
-static struct gpiod_lookup_table tosa_lcd_gpio_table = {
- .dev_id = "spi2.0",
- .table = {
- GPIO_LOOKUP("tc6393xb",
- TOSA_GPIO_TG_ON - TOSA_TC6393XB_GPIO_BASE,
- "tg #pwr", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct gpiod_lookup_table tosa_lcd_bl_gpio_table = {
- .dev_id = "i2c-tosa-bl",
- .table = {
- GPIO_LOOKUP("tc6393xb",
- TOSA_GPIO_BL_C20MA - TOSA_TC6393XB_GPIO_BASE,
- "backlight", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
- {
- .modalias = "tosa-lcd",
- // .platform_data
- .max_speed_hz = 28750,
- .bus_num = 2,
- .chip_select = 0,
- .mode = SPI_MODE_0,
- },
-};
-
-static struct mtd_partition sharpsl_rom_parts[] = {
- {
- .name ="Boot PROM Filesystem",
- .offset = 0x00160000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data sharpsl_rom_data = {
- .width = 2,
- .nr_parts = ARRAY_SIZE(sharpsl_rom_parts),
- .parts = sharpsl_rom_parts,
-};
-
-static struct resource sharpsl_rom_resources[] = {
- {
- .start = 0x00000000,
- .end = 0x007fffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device sharpsl_rom_device = {
- .name = "physmap-flash",
- .id = -1,
- .resource = sharpsl_rom_resources,
- .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
- .dev.platform_data = &sharpsl_rom_data,
-};
-
-static struct platform_device wm9712_device = {
- .name = "wm9712-codec",
- .id = -1,
-};
-
-static struct platform_device tosa_audio_device = {
- .name = "tosa-audio",
- .id = -1,
-};
-
-static struct platform_device *devices[] __initdata = {
- &tosascoop_device,
- &tosascoop_jc_device,
- &tc6393xb_device,
- &tosa_power_device,
- &tosakbd_device,
- &tosa_gpio_keys_device,
- &tosaled_device,
- &tosa_bt_device,
- &sharpsl_rom_device,
- &wm9712_device,
- &tosa_gpio_vbus,
- &tosa_audio_device,
-};
-
-static void tosa_poweroff(void)
-{
- pxa_restart(REBOOT_GPIO, NULL);
-}
-
-static void tosa_restart(enum reboot_mode mode, const char *cmd)
-{
- uint32_t msc0 = __raw_readl(MSC0);
-
- /* Bootloader magic for a reboot */
- if((msc0 & 0xffff0000) == 0x7ff00000)
- __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
-
- tosa_poweroff();
-}
-
-static void __init tosa_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- gpio_set_wake(MFP_PIN_GPIO1, 1);
- /* We can't pass to gpio-keys since it will drop the Reset altfunc */
-
- init_gpio_reset(TOSA_GPIO_ON_RESET, 0, 0);
-
- pm_power_off = tosa_poweroff;
-
- PCFR |= PCFR_OPDE;
-
- /* enable batt_fault */
- PMCR = 0x01;
-
- gpiod_add_lookup_table(&tosa_mci_gpio_table);
- pxa_set_mci_info(&tosa_mci_platform_data);
- pxa_set_ficp_info(&tosa_ficp_platform_data);
- pxa_set_i2c_info(NULL);
- pxa_set_ac97_info(NULL);
- platform_scoop_config = &tosa_pcmcia_config;
-
- pxa2xx_set_spi_info(2, &pxa_ssp_master_info);
- gpiod_add_lookup_table(&tosa_lcd_gpio_table);
- gpiod_add_lookup_table(&tosa_lcd_bl_gpio_table);
- spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-
- clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL);
-
- gpiod_add_lookup_table(&tosa_udc_gpiod_table);
- gpiod_add_lookup_table(&tosa_power_gpiod_table);
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init fixup_tosa(struct tag *tags, char **cmdline)
-{
- sharpsl_save_param();
- memblock_add(0xa0000000, SZ_64M);
-}
-
-MACHINE_START(TOSA, "SHARP Tosa")
- .fixup = fixup_tosa,
- .map_io = pxa25x_map_io,
- .nr_irqs = TOSA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_machine = tosa_init,
- .init_time = pxa_timer_init,
- .restart = tosa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa_bt.h b/arch/arm/mach-pxa/tosa_bt.h
deleted file mode 100644
index 56acd5dabec4..000000000000
--- a/arch/arm/mach-pxa/tosa_bt.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Tosa bluetooth built-in chip control.
- *
- * Later it may be shared with some other platforms.
- *
- * Copyright (c) 2008 Dmitry Baryshkov
- */
-#ifndef TOSA_BT_H
-#define TOSA_BT_H
-
-struct tosa_bt_data {
- int gpio_pwr;
- int gpio_reset;
-};
-
-#endif
-
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
deleted file mode 100644
index f76f8be09554..000000000000
--- a/arch/arm/mach-pxa/trizeps4.c
+++ /dev/null
@@ -1,575 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/trizeps4.c
- *
- * Support for the Keith und Koep Trizeps4 Module Platform.
- *
- * Author: Jürgen Schindele
- * Created: 20 02, 2006
- * Copyright: Jürgen Schindele
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/bitops.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/dm9000.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/regulator/machine.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <linux/sizes.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/flash.h>
-
-#include "pxa27x.h"
-#include <mach/trizeps4.h>
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/irda-pxaficp.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <mach/smemc.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/* comment out the following line if you want to use the
- * Standard UART from PXA for serial / irda transmission
- * and acivate it if you have status leds connected */
-#define STATUS_LEDS_ON_STUART_PINS 1
-
-/*****************************************************************************
- * MultiFunctionPins of CPU
- *****************************************************************************/
-static unsigned long trizeps4_pin_config[] __initdata = {
- /* Chip Selects */
- GPIO15_nCS_1, /* DiskOnChip CS */
- GPIO93_GPIO, /* TRIZEPS4_DOC_IRQ */
- GPIO94_GPIO, /* DOC lock */
-
- GPIO78_nCS_2, /* DM9000 CS */
- GPIO101_GPIO, /* TRIZEPS4_ETH_IRQ */
-
- GPIO79_nCS_3, /* Logic CS */
- GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, /* Logic irq */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* LCD - 16bpp Active TFT */
- GPIOxx_LCD_TFT_16BPP,
-
- /* UART */
- GPIO9_FFUART_CTS,
- GPIO10_FFUART_DCD,
- GPIO16_FFUART_TXD,
- GPIO33_FFUART_DSR,
- GPIO38_FFUART_RI,
- GPIO82_FFUART_DTR,
- GPIO83_FFUART_RTS,
- GPIO96_FFUART_RXD,
-
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-#ifdef STATUS_LEDS_ON_STUART_PINS
- GPIO46_GPIO,
- GPIO47_GPIO,
-#else
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-#endif
- /* PCMCIA */
- GPIO11_GPIO, /* TRIZEPS4_CD_IRQ */
- GPIO13_GPIO, /* TRIZEPS4_READY_NINT */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO54_nPCE_2,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
- GPIO102_nPCE_1,
- GPIO104_PSKTSEL,
-
- /* MultiMediaCard */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO12_GPIO, /* TRIZEPS4_MMC_IRQ */
-
- /* USB OHCI */
- GPIO88_USBH1_PWR, /* USBHPWR1 */
- GPIO89_USBH1_PEN, /* USBHPEN1 */
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-};
-
-static unsigned long trizeps4wl_pin_config[] __initdata = {
- /* SSP 2 */
- GPIO14_SSP2_SFRM,
- GPIO19_SSP2_SCLK,
- GPIO53_GPIO, /* TRIZEPS4_SPI_IRQ */
- GPIO86_SSP2_RXD,
- GPIO87_SSP2_TXD,
-};
-
-/****************************************************************************
- * ONBOARD FLASH
- ****************************************************************************/
-static struct mtd_partition trizeps4_partitions[] = {
- {
- .name = "Bootloader",
- .offset = 0x00000000,
- .size = 0x00040000,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- }, {
- .name = "Backup",
- .offset = 0x00040000,
- .size = 0x00040000,
- }, {
- .name = "Image",
- .offset = 0x00080000,
- .size = 0x01080000,
- }, {
- .name = "IPSM",
- .offset = 0x01100000,
- .size = 0x00e00000,
- }, {
- .name = "Registry",
- .offset = 0x01f00000,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct physmap_flash_data trizeps4_flash_data[] = {
- {
- .width = 4, /* bankwidth in bytes */
- .parts = trizeps4_partitions,
- .nr_parts = ARRAY_SIZE(trizeps4_partitions)
- }
-};
-
-static struct resource flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = trizeps4_flash_data,
- },
- .resource = &flash_resource,
- .num_resources = 1,
-};
-
-/****************************************************************************
- * DAVICOM DM9000 Ethernet
- ****************************************************************************/
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = TRIZEPS4_ETH_PHYS+0x300,
- .end = TRIZEPS4_ETH_PHYS+0x400-1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = TRIZEPS4_ETH_PHYS+0x8300,
- .end = TRIZEPS4_ETH_PHYS+0x8400-1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = TRIZEPS4_ETH_IRQ,
- .end = TRIZEPS4_ETH_IRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct dm9000_plat_data tri_dm9000_platdata = {
- .flags = DM9000_PLATF_32BITONLY,
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
- .dev = {
- .platform_data = &tri_dm9000_platdata,
- }
-};
-
-/****************************************************************************
- * LED's on GPIO pins of PXA
- ****************************************************************************/
-static struct gpio_led trizeps4_led[] = {
-#ifdef STATUS_LEDS_ON_STUART_PINS
- {
- .name = "led0:orange:heartbeat", /* */
- .default_trigger = "heartbeat",
- .gpio = GPIO_HEARTBEAT_LED,
- .active_low = 1,
- },
- {
- .name = "led1:yellow:cpubusy", /* */
- .default_trigger = "cpu-busy",
- .gpio = GPIO_SYS_BUSY_LED,
- .active_low = 1,
- },
-#endif
-};
-
-static struct gpio_led_platform_data trizeps4_led_data = {
- .leds = trizeps4_led,
- .num_leds = ARRAY_SIZE(trizeps4_led),
-};
-
-static struct platform_device leds_devices = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &trizeps4_led_data,
- },
-};
-
-static struct platform_device *trizeps4_devices[] __initdata = {
- &flash_device,
- &dm9000_device,
- &leds_devices,
-};
-
-static struct platform_device *trizeps4wl_devices[] __initdata = {
- &flash_device,
- &leds_devices,
-};
-
-static short trizeps_conxs_bcr;
-
-/* PCCARD power switching supports only 3,3V */
-void board_pcmcia_power(int power)
-{
- if (power) {
- /* switch power on, put in reset and enable buffers */
- trizeps_conxs_bcr |= power;
- trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
- trizeps_conxs_bcr &= ~ConXS_BCR_CF_BUF_EN;
- BCR_writew(trizeps_conxs_bcr);
- /* wait a little */
- udelay(2000);
- /* take reset away */
- trizeps_conxs_bcr &= ~ConXS_BCR_CF_RESET;
- BCR_writew(trizeps_conxs_bcr);
- udelay(2000);
- } else {
- /* put in reset */
- trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
- BCR_writew(trizeps_conxs_bcr);
- udelay(1000);
- /* switch power off */
- trizeps_conxs_bcr &= ~0xf;
- BCR_writew(trizeps_conxs_bcr);
- }
- pr_debug("%s: o%s 0x%x\n", __func__, power ? "n" : "ff",
- trizeps_conxs_bcr);
-}
-EXPORT_SYMBOL(board_pcmcia_power);
-
-/* backlight power switching for LCD panel */
-static void board_backlight_power(int on)
-{
- if (on)
- trizeps_conxs_bcr |= ConXS_BCR_L_DISP;
- else
- trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP;
-
- pr_debug("%s: o%s 0x%x\n", __func__, on ? "n" : "ff",
- trizeps_conxs_bcr);
- BCR_writew(trizeps_conxs_bcr);
-}
-
-/* a I2C based RTC is known on CONXS board */
-static struct i2c_board_info trizeps4_i2c_devices[] __initdata = {
- { I2C_BOARD_INFO("rtc-pcf8593", 0x51) }
-};
-
-/****************************************************************************
- * MMC card slot external to module
- ****************************************************************************/
-static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int,
- void *data)
-{
- int err;
-
- err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int,
- IRQF_TRIGGER_RISING, "MMC card detect", data);
- if (err) {
- printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request"
- "MMC card detect IRQ\n");
- return -1;
- }
- return 0;
-}
-
-static void trizeps4_mci_exit(struct device *dev, void *data)
-{
- free_irq(TRIZEPS4_MMC_IRQ, data);
-}
-
-static struct pxamci_platform_data trizeps4_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .detect_delay_ms= 10,
- .init = trizeps4_mci_init,
- .exit = trizeps4_mci_exit,
- .get_ro = NULL, /* write-protection not supported */
- .setpower = NULL, /* power-switching not supported */
-};
-
-/****************************************************************************
- * IRDA mode switching on stuart
- ****************************************************************************/
-#ifndef STATUS_LEDS_ON_STUART_PINS
-static short trizeps_conxs_ircr;
-
-static int trizeps4_irda_startup(struct device *dev)
-{
- trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
- IRCR_writew(trizeps_conxs_ircr);
- return 0;
-}
-
-static void trizeps4_irda_shutdown(struct device *dev)
-{
- trizeps_conxs_ircr |= ConXS_IRCR_SD;
- IRCR_writew(trizeps_conxs_ircr);
-}
-
-static void trizeps4_irda_transceiver_mode(struct device *dev, int mode)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- /* Switch mode */
- if (mode & IR_SIRMODE)
- trizeps_conxs_ircr &= ~ConXS_IRCR_MODE; /* Slow mode */
- else if (mode & IR_FIRMODE)
- trizeps_conxs_ircr |= ConXS_IRCR_MODE; /* Fast mode */
-
- /* Switch power */
- if (mode & IR_OFF)
- trizeps_conxs_ircr |= ConXS_IRCR_SD;
- else
- trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
-
- IRCR_writew(trizeps_conxs_ircr);
- local_irq_restore(flags);
-
- pxa2xx_transceiver_mode(dev, mode);
-}
-
-static struct pxaficp_platform_data trizeps4_ficp_platform_data = {
- .gpio_pwdown = -1,
- .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
- .transceiver_mode = trizeps4_irda_transceiver_mode,
- .startup = trizeps4_irda_startup,
- .shutdown = trizeps4_irda_shutdown,
-};
-#endif
-
-/****************************************************************************
- * OHCI USB port
- ****************************************************************************/
-static struct pxaohci_platform_data trizeps4_ohci_platform_data = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-static struct map_desc trizeps4_io_desc[] __initdata = {
- { /* ConXS CFSR */
- .virtual = TRIZEPS4_CFSR_VIRT,
- .pfn = __phys_to_pfn(TRIZEPS4_CFSR_PHYS),
- .length = 0x00001000,
- .type = MT_DEVICE
- },
- { /* ConXS BCR */
- .virtual = TRIZEPS4_BOCR_VIRT,
- .pfn = __phys_to_pfn(TRIZEPS4_BOCR_PHYS),
- .length = 0x00001000,
- .type = MT_DEVICE
- },
- { /* ConXS IRCR */
- .virtual = TRIZEPS4_IRCR_VIRT,
- .pfn = __phys_to_pfn(TRIZEPS4_IRCR_PHYS),
- .length = 0x00001000,
- .type = MT_DEVICE
- },
- { /* ConXS DCR */
- .virtual = TRIZEPS4_DICR_VIRT,
- .pfn = __phys_to_pfn(TRIZEPS4_DICR_PHYS),
- .length = 0x00001000,
- .type = MT_DEVICE
- },
- { /* ConXS UPSR */
- .virtual = TRIZEPS4_UPSR_VIRT,
- .pfn = __phys_to_pfn(TRIZEPS4_UPSR_PHYS),
- .length = 0x00001000,
- .type = MT_DEVICE
- }
-};
-
-static struct pxafb_mode_info sharp_lcd_mode = {
- .pixclock = 78000,
- .xres = 640,
- .yres = 480,
- .bpp = 8,
- .hsync_len = 4,
- .left_margin = 4,
- .right_margin = 4,
- .vsync_len = 2,
- .upper_margin = 0,
- .lower_margin = 0,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info sharp_lcd = {
- .modes = &sharp_lcd_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL,
- .cmap_inverse = 0,
- .cmap_static = 0,
- .pxafb_backlight_power = board_backlight_power,
-};
-
-static struct pxafb_mode_info toshiba_lcd_mode = {
- .pixclock = 39720,
- .xres = 640,
- .yres = 480,
- .bpp = 8,
- .hsync_len = 63,
- .left_margin = 12,
- .right_margin = 12,
- .vsync_len = 4,
- .upper_margin = 32,
- .lower_margin = 10,
- .sync = 0,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info toshiba_lcd = {
- .modes = &toshiba_lcd_mode,
- .num_modes = 1,
- .lcd_conn = (LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL),
- .cmap_inverse = 0,
- .cmap_static = 0,
- .pxafb_backlight_power = board_backlight_power,
-};
-
-static void __init trizeps4_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(trizeps4_pin_config));
- if (machine_is_trizeps4wl()) {
- pxa2xx_mfp_config(ARRAY_AND_SIZE(trizeps4wl_pin_config));
- platform_add_devices(trizeps4wl_devices,
- ARRAY_SIZE(trizeps4wl_devices));
- } else {
- platform_add_devices(trizeps4_devices,
- ARRAY_SIZE(trizeps4_devices));
- }
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- if (0) /* dont know how to determine LCD */
- pxa_set_fb_info(NULL, &sharp_lcd);
- else
- pxa_set_fb_info(NULL, &toshiba_lcd);
-
- pxa_set_mci_info(&trizeps4_mci_platform_data);
-#ifndef STATUS_LEDS_ON_STUART_PINS
- pxa_set_ficp_info(&trizeps4_ficp_platform_data);
-#endif
- pxa_set_ohci_info(&trizeps4_ohci_platform_data);
- pxa_set_ac97_info(NULL);
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, trizeps4_i2c_devices,
- ARRAY_SIZE(trizeps4_i2c_devices));
-
- /* this is the reset value */
- trizeps_conxs_bcr = 0x00A0;
-
- BCR_writew(trizeps_conxs_bcr);
- board_backlight_power(1);
-
- regulator_has_full_constraints();
-}
-
-static void __init trizeps4_map_io(void)
-{
- pxa27x_map_io();
- iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
-
- if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) {
- /* if flash is 16 bit wide its a Trizeps4 WL */
- __machine_arch_type = MACH_TYPE_TRIZEPS4WL;
- trizeps4_flash_data[0].width = 2;
- } else {
- /* if flash is 32 bit wide its a Trizeps4 */
- __machine_arch_type = MACH_TYPE_TRIZEPS4;
- trizeps4_flash_data[0].width = 4;
- }
-}
-
-MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
- /* MAINTAINER("Jürgen Schindele") */
- .atag_offset = 0x100,
- .init_machine = trizeps4_init,
- .map_io = trizeps4_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-
-MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
- /* MAINTAINER("Jürgen Schindele") */
- .atag_offset = 0x100,
- .init_machine = trizeps4_init,
- .map_io = trizeps4_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
deleted file mode 100644
index 3aa34e9a15d3..000000000000
--- a/arch/arm/mach-pxa/viper.c
+++ /dev/null
@@ -1,1022 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/viper.c
- *
- * Support for the Arcom VIPER SBC.
- *
- * Author: Ian Campbell
- * Created: Feb 03, 2003
- * Copyright: Arcom Control Systems
- *
- * Maintained by Marc Zyngier <maz@misterjones.org>
- * <marc.zyngier@altran.com>
- *
- * Based on lubbock.c:
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software Inc.
- */
-
-#include <linux/types.h>
-#include <linux/memory.h>
-#include <linux/cpu.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/major.h>
-#include <linux/module.h>
-#include <linux/pm.h>
-#include <linux/sched.h>
-#include <linux/gpio.h>
-#include <linux/jiffies.h>
-#include <linux/platform_data/i2c-gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/serial_8250.h>
-#include <linux/smc91x.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/usb/isp116x.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/syscore_ops.h>
-
-#include "pxa25x.h"
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <mach/regs-uart.h>
-#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
-#include "viper.h"
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <linux/sizes.h>
-#include <asm/system_info.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include "generic.h"
-#include "devices.h"
-
-static unsigned int icr;
-
-static void viper_icr_set_bit(unsigned int bit)
-{
- icr |= bit;
- VIPER_ICR = icr;
-}
-
-static void viper_icr_clear_bit(unsigned int bit)
-{
- icr &= ~bit;
- VIPER_ICR = icr;
-}
-
-/* This function is used from the pcmcia module to reset the CF */
-static void viper_cf_reset(int state)
-{
- if (state)
- viper_icr_set_bit(VIPER_ICR_CF_RST);
- else
- viper_icr_clear_bit(VIPER_ICR_CF_RST);
-}
-
-static struct arcom_pcmcia_pdata viper_pcmcia_info = {
- .cd_gpio = VIPER_CF_CD_GPIO,
- .rdy_gpio = VIPER_CF_RDY_GPIO,
- .pwr_gpio = VIPER_CF_POWER_GPIO,
- .reset = viper_cf_reset,
-};
-
-static struct platform_device viper_pcmcia_device = {
- .name = "viper-pcmcia",
- .id = -1,
- .dev = {
- .platform_data = &viper_pcmcia_info,
- },
-};
-
-/*
- * The CPLD version register was not present on VIPER boards prior to
- * v2i1. On v1 boards where the version register is not present we
- * will just read back the previous value from the databus.
- *
- * Therefore we do two reads. The first time we write 0 to the
- * (read-only) register before reading and the second time we write
- * 0xff first. If the two reads do not match or they read back as 0xff
- * or 0x00 then we have version 1 hardware.
- */
-static u8 viper_hw_version(void)
-{
- u8 v1, v2;
- unsigned long flags;
-
- local_irq_save(flags);
-
- VIPER_VERSION = 0;
- v1 = VIPER_VERSION;
- VIPER_VERSION = 0xff;
- v2 = VIPER_VERSION;
-
- v1 = (v1 != v2 || v1 == 0xff) ? 0 : v1;
-
- local_irq_restore(flags);
- return v1;
-}
-
-/* CPU system core operations. */
-static int viper_cpu_suspend(void)
-{
- viper_icr_set_bit(VIPER_ICR_R_DIS);
- return 0;
-}
-
-static void viper_cpu_resume(void)
-{
- viper_icr_clear_bit(VIPER_ICR_R_DIS);
-}
-
-static struct syscore_ops viper_cpu_syscore_ops = {
- .suspend = viper_cpu_suspend,
- .resume = viper_cpu_resume,
-};
-
-static unsigned int current_voltage_divisor;
-
-/*
- * If force is not true then step from existing to new divisor. If
- * force is true then jump straight to the new divisor. Stepping is
- * used because if the jump in voltage is too large, the VCC can dip
- * too low and the regulator cuts out.
- *
- * force can be used to initialize the divisor to a know state by
- * setting the value for the current clock speed, since we are already
- * running at that speed we know the voltage should be pretty close so
- * the jump won't be too large
- */
-static void viper_set_core_cpu_voltage(unsigned long khz, int force)
-{
- int i = 0;
- unsigned int divisor = 0;
- const char *v;
-
- if (khz < 200000) {
- v = "1.0"; divisor = 0xfff;
- } else if (khz < 300000) {
- v = "1.1"; divisor = 0xde5;
- } else {
- v = "1.3"; divisor = 0x325;
- }
-
- pr_debug("viper: setting CPU core voltage to %sV at %d.%03dMHz\n",
- v, (int)khz / 1000, (int)khz % 1000);
-
-#define STEP 0x100
- do {
- int step;
-
- if (force)
- step = divisor;
- else if (current_voltage_divisor < divisor - STEP)
- step = current_voltage_divisor + STEP;
- else if (current_voltage_divisor > divisor + STEP)
- step = current_voltage_divisor - STEP;
- else
- step = divisor;
- force = 0;
-
- gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
- gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
-
- for (i = 1 << 11 ; i > 0 ; i >>= 1) {
- udelay(1);
-
- gpio_set_value(VIPER_PSU_DATA_GPIO, step & i);
- udelay(1);
-
- gpio_set_value(VIPER_PSU_CLK_GPIO, 1);
- udelay(1);
-
- gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
- }
- udelay(1);
-
- gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 1);
- udelay(1);
-
- gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
-
- current_voltage_divisor = step;
- } while (current_voltage_divisor != divisor);
-}
-
-/* Interrupt handling */
-static unsigned long viper_irq_enabled_mask;
-static const int viper_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, 9, 14, 15 };
-static const int viper_isa_irq_map[] = {
- 0, /* ISA irq #0, invalid */
- 0, /* ISA irq #1, invalid */
- 0, /* ISA irq #2, invalid */
- 1 << 0, /* ISA irq #3 */
- 1 << 1, /* ISA irq #4 */
- 1 << 2, /* ISA irq #5 */
- 1 << 3, /* ISA irq #6 */
- 1 << 4, /* ISA irq #7 */
- 0, /* ISA irq #8, invalid */
- 1 << 8, /* ISA irq #9 */
- 1 << 5, /* ISA irq #10 */
- 1 << 6, /* ISA irq #11 */
- 1 << 7, /* ISA irq #12 */
- 0, /* ISA irq #13, invalid */
- 1 << 9, /* ISA irq #14 */
- 1 << 10, /* ISA irq #15 */
-};
-
-static inline int viper_irq_to_bitmask(unsigned int irq)
-{
- return viper_isa_irq_map[irq - PXA_ISA_IRQ(0)];
-}
-
-static inline int viper_bit_to_irq(int bit)
-{
- return viper_isa_irqs[bit] + PXA_ISA_IRQ(0);
-}
-
-static void viper_ack_irq(struct irq_data *d)
-{
- int viper_irq = viper_irq_to_bitmask(d->irq);
-
- if (viper_irq & 0xff)
- VIPER_LO_IRQ_STATUS = viper_irq;
- else
- VIPER_HI_IRQ_STATUS = (viper_irq >> 8);
-}
-
-static void viper_mask_irq(struct irq_data *d)
-{
- viper_irq_enabled_mask &= ~(viper_irq_to_bitmask(d->irq));
-}
-
-static void viper_unmask_irq(struct irq_data *d)
-{
- viper_irq_enabled_mask |= viper_irq_to_bitmask(d->irq);
-}
-
-static inline unsigned long viper_irq_pending(void)
-{
- return (VIPER_HI_IRQ_STATUS << 8 | VIPER_LO_IRQ_STATUS) &
- viper_irq_enabled_mask;
-}
-
-static void viper_irq_handler(struct irq_desc *desc)
-{
- unsigned int irq;
- unsigned long pending;
-
- pending = viper_irq_pending();
- do {
- /* we're in a chained irq handler,
- * so ack the interrupt by hand */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-
- if (likely(pending)) {
- irq = viper_bit_to_irq(__ffs(pending));
- generic_handle_irq(irq);
- }
- pending = viper_irq_pending();
- } while (pending);
-}
-
-static struct irq_chip viper_irq_chip = {
- .name = "ISA",
- .irq_ack = viper_ack_irq,
- .irq_mask = viper_mask_irq,
- .irq_unmask = viper_unmask_irq
-};
-
-static void __init viper_init_irq(void)
-{
- int level;
- int isa_irq;
-
- pxa25x_init_irq();
-
- /* setup ISA IRQs */
- for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
- isa_irq = viper_bit_to_irq(level);
- irq_set_chip_and_handler(isa_irq, &viper_irq_chip,
- handle_edge_irq);
- irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-
- irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
- viper_irq_handler);
- irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
-}
-
-/* Flat Panel */
-static struct pxafb_mode_info fb_mode_info[] = {
- {
- .pixclock = 157500,
-
- .xres = 320,
- .yres = 240,
-
- .bpp = 16,
-
- .hsync_len = 63,
- .left_margin = 7,
- .right_margin = 13,
-
- .vsync_len = 20,
- .upper_margin = 0,
- .lower_margin = 0,
-
- .sync = 0,
- },
-};
-
-static struct pxafb_mach_info fb_info = {
- .modes = fb_mode_info,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static struct pwm_lookup viper_pwm_lookup[] = {
- PWM_LOOKUP("pxa25x-pwm.0", 0, "pwm-backlight.0", NULL, 1000000,
- PWM_POLARITY_NORMAL),
-};
-
-static int viper_backlight_init(struct device *dev)
-{
- int ret;
-
- /* GPIO9 and 10 control FB backlight. Initialise to off */
- ret = gpio_request(VIPER_BCKLIGHT_EN_GPIO, "Backlight");
- if (ret)
- goto err_request_bckl;
-
- ret = gpio_request(VIPER_LCD_EN_GPIO, "LCD");
- if (ret)
- goto err_request_lcd;
-
- ret = gpio_direction_output(VIPER_BCKLIGHT_EN_GPIO, 0);
- if (ret)
- goto err_dir;
-
- ret = gpio_direction_output(VIPER_LCD_EN_GPIO, 0);
- if (ret)
- goto err_dir;
-
- return 0;
-
-err_dir:
- gpio_free(VIPER_LCD_EN_GPIO);
-err_request_lcd:
- gpio_free(VIPER_BCKLIGHT_EN_GPIO);
-err_request_bckl:
- dev_err(dev, "Failed to setup LCD GPIOs\n");
-
- return ret;
-}
-
-static int viper_backlight_notify(struct device *dev, int brightness)
-{
- gpio_set_value(VIPER_LCD_EN_GPIO, !!brightness);
- gpio_set_value(VIPER_BCKLIGHT_EN_GPIO, !!brightness);
-
- return brightness;
-}
-
-static void viper_backlight_exit(struct device *dev)
-{
- gpio_free(VIPER_LCD_EN_GPIO);
- gpio_free(VIPER_BCKLIGHT_EN_GPIO);
-}
-
-static struct platform_pwm_backlight_data viper_backlight_data = {
- .max_brightness = 100,
- .dft_brightness = 100,
- .init = viper_backlight_init,
- .notify = viper_backlight_notify,
- .exit = viper_backlight_exit,
-};
-
-static struct platform_device viper_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa25x_device_pwm0.dev,
- .platform_data = &viper_backlight_data,
- },
-};
-
-/* Ethernet */
-static struct resource smc91x_resources[] = {
- [0] = {
- .name = "smc91x-regs",
- .start = VIPER_ETH_PHYS + 0x300,
- .end = VIPER_ETH_PHYS + 0x30f,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
- .end = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
- [2] = {
- .name = "smc91x-data32",
- .start = VIPER_ETH_DATA_PHYS,
- .end = VIPER_ETH_DATA_PHYS + 3,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct smc91x_platdata viper_smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &viper_smc91x_info,
- },
-};
-
-/* i2c */
-static struct gpiod_lookup_table viper_i2c_gpiod_table = {
- .dev_id = "i2c-gpio.1",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SDA_GPIO,
- NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("gpio-pxa", VIPER_RTC_I2C_SCL_GPIO,
- NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_bus_data = {
- .udelay = 10,
- .timeout = HZ,
-};
-
-static struct platform_device i2c_bus_device = {
- .name = "i2c-gpio",
- .id = 1, /* pxa2xx-i2c is bus 0, so start at 1 */
- .dev = {
- .platform_data = &i2c_bus_data,
- }
-};
-
-static struct i2c_board_info __initdata viper_i2c_devices[] = {
- {
- I2C_BOARD_INFO("ds1338", 0x68),
- },
-};
-
-/*
- * Serial configuration:
- * You can either have the standard PXA ports driven by the PXA driver,
- * or all the ports (PXA + 16850) driven by the 8250 driver.
- * Choose your poison.
- */
-
-static struct resource viper_serial_resources[] = {
-#ifndef CONFIG_SERIAL_PXA
- {
- .start = 0x40100000,
- .end = 0x4010001f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x40200000,
- .end = 0x4020001f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x40700000,
- .end = 0x4070001f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = VIPER_UARTA_PHYS,
- .end = VIPER_UARTA_PHYS + 0xf,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = VIPER_UARTB_PHYS,
- .end = VIPER_UARTB_PHYS + 0xf,
- .flags = IORESOURCE_MEM,
- },
-#else
- {
- 0,
- },
-#endif
-};
-
-static struct plat_serial8250_port serial_platform_data[] = {
-#ifndef CONFIG_SERIAL_PXA
- /* Internal UARTs */
- {
- .membase = (void *)&FFUART,
- .mapbase = __PREG(FFUART),
- .irq = IRQ_FFUART,
- .uartclk = 921600 * 16,
- .regshift = 2,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- {
- .membase = (void *)&BTUART,
- .mapbase = __PREG(BTUART),
- .irq = IRQ_BTUART,
- .uartclk = 921600 * 16,
- .regshift = 2,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- {
- .membase = (void *)&STUART,
- .mapbase = __PREG(STUART),
- .irq = IRQ_STUART,
- .uartclk = 921600 * 16,
- .regshift = 2,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- /* External UARTs */
- {
- .mapbase = VIPER_UARTA_PHYS,
- .irq = PXA_GPIO_TO_IRQ(VIPER_UARTA_GPIO),
- .irqflags = IRQF_TRIGGER_RISING,
- .uartclk = 1843200,
- .regshift = 1,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
- UPF_SKIP_TEST,
- },
- {
- .mapbase = VIPER_UARTB_PHYS,
- .irq = PXA_GPIO_TO_IRQ(VIPER_UARTB_GPIO),
- .irqflags = IRQF_TRIGGER_RISING,
- .uartclk = 1843200,
- .regshift = 1,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
- UPF_SKIP_TEST,
- },
-#endif
- { },
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = serial_platform_data,
- },
- .num_resources = ARRAY_SIZE(viper_serial_resources),
- .resource = viper_serial_resources,
-};
-
-/* USB */
-static void isp116x_delay(struct device *dev, int delay)
-{
- ndelay(delay);
-}
-
-static struct resource isp116x_resources[] = {
- [0] = { /* DATA */
- .start = VIPER_USB_PHYS + 0,
- .end = VIPER_USB_PHYS + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* ADDR */
- .start = VIPER_USB_PHYS + 2,
- .end = VIPER_USB_PHYS + 3,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
- .end = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-/* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */
-static struct isp116x_platform_data isp116x_platform_data = {
- /* Enable internal resistors on downstream ports */
- .sel15Kres = 1,
- /* On-chip overcurrent protection */
- .oc_enable = 1,
- /* INT output polarity */
- .int_act_high = 1,
- /* INT edge or level triggered */
- .int_edge_triggered = 0,
-
- /* WAKEUP pin connected - NOT SUPPORTED */
- /* .remote_wakeup_connected = 0, */
- /* Wakeup by devices on usb bus enabled */
- .remote_wakeup_enable = 0,
- .delay = isp116x_delay,
-};
-
-static struct platform_device isp116x_device = {
- .name = "isp116x-hcd",
- .id = -1,
- .num_resources = ARRAY_SIZE(isp116x_resources),
- .resource = isp116x_resources,
- .dev = {
- .platform_data = &isp116x_platform_data,
- },
-
-};
-
-/* MTD */
-static struct resource mtd_resources[] = {
- [0] = { /* RedBoot config + filesystem flash */
- .start = VIPER_FLASH_PHYS,
- .end = VIPER_FLASH_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* Boot flash */
- .start = VIPER_BOOT_PHYS,
- .end = VIPER_BOOT_PHYS + SZ_1M - 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = { /*
- * SRAM size is actually 256KB, 8bits, with a sparse mapping
- * (each byte is on a 16bit boundary).
- */
- .start = _VIPER_SRAM_BASE,
- .end = _VIPER_SRAM_BASE + SZ_512K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct mtd_partition viper_boot_flash_partition = {
- .name = "RedBoot",
- .size = SZ_1M,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE, /* force R/O */
-};
-
-static struct physmap_flash_data viper_flash_data[] = {
- [0] = {
- .width = 2,
- .parts = NULL,
- .nr_parts = 0,
- },
- [1] = {
- .width = 2,
- .parts = &viper_boot_flash_partition,
- .nr_parts = 1,
- },
-};
-
-static struct platform_device viper_mtd_devices[] = {
- [0] = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &viper_flash_data[0],
- },
- .resource = &mtd_resources[0],
- .num_resources = 1,
- },
- [1] = {
- .name = "physmap-flash",
- .id = 1,
- .dev = {
- .platform_data = &viper_flash_data[1],
- },
- .resource = &mtd_resources[1],
- .num_resources = 1,
- },
-};
-
-static struct platform_device *viper_devs[] __initdata = {
- &smc91x_device,
- &i2c_bus_device,
- &serial_device,
- &isp116x_device,
- &viper_mtd_devices[0],
- &viper_mtd_devices[1],
- &viper_backlight_device,
- &viper_pcmcia_device,
-};
-
-static mfp_cfg_t viper_pin_config[] __initdata = {
- /* Chip selects */
- GPIO15_nCS_1,
- GPIO78_nCS_2,
- GPIO79_nCS_3,
- GPIO80_nCS_4,
- GPIO33_nCS_5,
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* FP Backlight */
- GPIO9_GPIO, /* VIPER_BCKLIGHT_EN_GPIO */
- GPIO10_GPIO, /* VIPER_LCD_EN_GPIO */
- GPIO16_PWM0_OUT,
-
- /* Ethernet PHY Ready */
- GPIO18_RDY,
-
- /* Serial shutdown */
- GPIO12_GPIO | MFP_LPM_DRIVE_HIGH, /* VIPER_UART_SHDN_GPIO */
-
- /* Compact-Flash / PC104 */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
- GPIO8_GPIO, /* VIPER_CF_RDY_GPIO */
- GPIO32_GPIO, /* VIPER_CF_CD_GPIO */
- GPIO82_GPIO, /* VIPER_CF_POWER_GPIO */
-
- /* Integrated UPS control */
- GPIO20_GPIO, /* VIPER_UPS_GPIO */
-
- /* Vcc regulator control */
- GPIO6_GPIO, /* VIPER_PSU_DATA_GPIO */
- GPIO11_GPIO, /* VIPER_PSU_CLK_GPIO */
- GPIO19_GPIO, /* VIPER_PSU_nCS_LD_GPIO */
-
- /* i2c busses */
- GPIO26_GPIO, /* VIPER_TPM_I2C_SDA_GPIO */
- GPIO27_GPIO, /* VIPER_TPM_I2C_SCL_GPIO */
- GPIO83_GPIO, /* VIPER_RTC_I2C_SDA_GPIO */
- GPIO84_GPIO, /* VIPER_RTC_I2C_SCL_GPIO */
-
- /* PC/104 Interrupt */
- GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* VIPER_CPLD_GPIO */
-};
-
-static unsigned long viper_tpm;
-
-static int __init viper_tpm_setup(char *str)
-{
- return kstrtoul(str, 10, &viper_tpm) >= 0;
-}
-
-__setup("tpm=", viper_tpm_setup);
-
-struct gpiod_lookup_table viper_tpm_i2c_gpiod_table = {
- .dev_id = "i2c-gpio.2",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SDA_GPIO,
- NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("gpio-pxa", VIPER_TPM_I2C_SCL_GPIO,
- NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static void __init viper_tpm_init(void)
-{
- struct platform_device *tpm_device;
- struct i2c_gpio_platform_data i2c_tpm_data = {
- .udelay = 10,
- .timeout = HZ,
- };
- char *errstr;
-
- /* Allocate TPM i2c bus if requested */
- if (!viper_tpm)
- return;
-
- gpiod_add_lookup_table(&viper_tpm_i2c_gpiod_table);
- tpm_device = platform_device_alloc("i2c-gpio", 2);
- if (tpm_device) {
- if (!platform_device_add_data(tpm_device,
- &i2c_tpm_data,
- sizeof(i2c_tpm_data))) {
- if (platform_device_add(tpm_device)) {
- errstr = "register TPM i2c bus";
- goto error_free_tpm;
- }
- } else {
- errstr = "allocate TPM i2c bus data";
- goto error_free_tpm;
- }
- } else {
- errstr = "allocate TPM i2c device";
- goto error_tpm;
- }
-
- return;
-
-error_free_tpm:
- kfree(tpm_device);
-error_tpm:
- pr_err("viper: Couldn't %s, giving up\n", errstr);
-}
-
-static void __init viper_init_vcore_gpios(void)
-{
- if (gpio_request(VIPER_PSU_DATA_GPIO, "PSU data"))
- goto err_request_data;
-
- if (gpio_request(VIPER_PSU_CLK_GPIO, "PSU clock"))
- goto err_request_clk;
-
- if (gpio_request(VIPER_PSU_nCS_LD_GPIO, "PSU cs"))
- goto err_request_cs;
-
- if (gpio_direction_output(VIPER_PSU_DATA_GPIO, 0) ||
- gpio_direction_output(VIPER_PSU_CLK_GPIO, 0) ||
- gpio_direction_output(VIPER_PSU_nCS_LD_GPIO, 0))
- goto err_dir;
-
- /* c/should assume redboot set the correct level ??? */
- viper_set_core_cpu_voltage(get_clk_frequency_khz(0), 1);
-
- return;
-
-err_dir:
- gpio_free(VIPER_PSU_nCS_LD_GPIO);
-err_request_cs:
- gpio_free(VIPER_PSU_CLK_GPIO);
-err_request_clk:
- gpio_free(VIPER_PSU_DATA_GPIO);
-err_request_data:
- pr_err("viper: Failed to setup vcore control GPIOs\n");
-}
-
-static void __init viper_init_serial_gpio(void)
-{
- if (gpio_request(VIPER_UART_SHDN_GPIO, "UARTs shutdown"))
- goto err_request;
-
- if (gpio_direction_output(VIPER_UART_SHDN_GPIO, 0))
- goto err_dir;
-
- return;
-
-err_dir:
- gpio_free(VIPER_UART_SHDN_GPIO);
-err_request:
- pr_err("viper: Failed to setup UART shutdown GPIO\n");
-}
-
-#ifdef CONFIG_CPU_FREQ
-static int viper_cpufreq_notifier(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- struct cpufreq_freqs *freq = data;
-
- /* TODO: Adjust timings??? */
-
- switch (val) {
- case CPUFREQ_PRECHANGE:
- if (freq->old < freq->new) {
- /* we are getting faster so raise the voltage
- * before we change freq */
- viper_set_core_cpu_voltage(freq->new, 0);
- }
- break;
- case CPUFREQ_POSTCHANGE:
- if (freq->old > freq->new) {
- /* we are slowing down so drop the power
- * after we change freq */
- viper_set_core_cpu_voltage(freq->new, 0);
- }
- break;
- default:
- /* ignore */
- break;
- }
-
- return 0;
-}
-
-static struct notifier_block viper_cpufreq_notifier_block = {
- .notifier_call = viper_cpufreq_notifier
-};
-
-static void __init viper_init_cpufreq(void)
-{
- if (cpufreq_register_notifier(&viper_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER))
- pr_err("viper: Failed to setup cpufreq notifier\n");
-}
-#else
-static inline void viper_init_cpufreq(void) {}
-#endif
-
-static void viper_power_off(void)
-{
- pr_notice("Shutting off UPS\n");
- gpio_set_value(VIPER_UPS_GPIO, 1);
- /* Spin to death... */
- while (1);
-}
-
-static void __init viper_init(void)
-{
- u8 version;
-
- pm_power_off = viper_power_off;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- /* Wake-up serial console */
- viper_init_serial_gpio();
-
- pxa_set_fb_info(NULL, &fb_info);
-
- /* v1 hardware cannot use the datacs line */
- version = viper_hw_version();
- if (version == 0)
- smc91x_device.num_resources--;
-
- pxa_set_i2c_info(NULL);
- gpiod_add_lookup_table(&viper_i2c_gpiod_table);
- pwm_add_table(viper_pwm_lookup, ARRAY_SIZE(viper_pwm_lookup));
- platform_add_devices(viper_devs, ARRAY_SIZE(viper_devs));
-
- viper_init_vcore_gpios();
- viper_init_cpufreq();
-
- register_syscore_ops(&viper_cpu_syscore_ops);
-
- if (version) {
- pr_info("viper: hardware v%di%d detected. "
- "CPLD revision %d.\n",
- VIPER_BOARD_VERSION(version),
- VIPER_BOARD_ISSUE(version),
- VIPER_CPLD_REVISION(version));
- system_rev = (VIPER_BOARD_VERSION(version) << 8) |
- (VIPER_BOARD_ISSUE(version) << 4) |
- VIPER_CPLD_REVISION(version);
- } else {
- pr_info("viper: No version register.\n");
- }
-
- i2c_register_board_info(1, ARRAY_AND_SIZE(viper_i2c_devices));
-
- viper_tpm_init();
- pxa_set_ac97_info(NULL);
-}
-
-static struct map_desc viper_io_desc[] __initdata = {
- {
- .virtual = VIPER_CPLD_BASE,
- .pfn = __phys_to_pfn(VIPER_CPLD_PHYS),
- .length = 0x00300000,
- .type = MT_DEVICE,
- },
- {
- .virtual = VIPER_PC104IO_BASE,
- .pfn = __phys_to_pfn(0x30000000),
- .length = 0x00800000,
- .type = MT_DEVICE,
- },
-};
-
-static void __init viper_map_io(void)
-{
- pxa25x_map_io();
-
- iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc));
-
- PCFR |= PCFR_OPDE;
-}
-
-MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
- /* Maintainer: Marc Zyngier <maz@misterjones.org> */
- .atag_offset = 0x100,
- .map_io = viper_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = viper_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = viper_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/viper.h b/arch/arm/mach-pxa/viper.h
deleted file mode 100644
index 5a8b132229dc..000000000000
--- a/arch/arm/mach-pxa/viper.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/viper.h
- *
- * Author: Ian Campbell
- * Created: Feb 03, 2003
- * Copyright: Arcom Control Systems.
- *
- * Maintained by Marc Zyngier <maz@misterjones.org>
- * <marc.zyngier@altran.com>
- *
- * Created based on lubbock.h:
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software Inc.
- */
-
-#ifndef ARCH_VIPER_H
-#define ARCH_VIPER_H
-
-#define VIPER_BOOT_PHYS PXA_CS0_PHYS
-#define VIPER_FLASH_PHYS PXA_CS1_PHYS
-#define VIPER_ETH_PHYS PXA_CS2_PHYS
-#define VIPER_USB_PHYS PXA_CS3_PHYS
-#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS
-#define VIPER_CPLD_PHYS PXA_CS5_PHYS
-
-#define VIPER_CPLD_BASE (0xf0000000)
-#define VIPER_PC104IO_BASE (0xf1000000)
-#define VIPER_USB_BASE (0xf1800000)
-
-#define VIPER_ETH_GPIO (0)
-#define VIPER_CPLD_GPIO (1)
-#define VIPER_USB_GPIO (2)
-#define VIPER_UARTA_GPIO (4)
-#define VIPER_UARTB_GPIO (3)
-#define VIPER_CF_CD_GPIO (32)
-#define VIPER_CF_RDY_GPIO (8)
-#define VIPER_BCKLIGHT_EN_GPIO (9)
-#define VIPER_LCD_EN_GPIO (10)
-#define VIPER_PSU_DATA_GPIO (6)
-#define VIPER_PSU_CLK_GPIO (11)
-#define VIPER_UART_SHDN_GPIO (12)
-#define VIPER_BRIGHTNESS_GPIO (16)
-#define VIPER_PSU_nCS_LD_GPIO (19)
-#define VIPER_UPS_GPIO (20)
-#define VIPER_CF_POWER_GPIO (82)
-#define VIPER_TPM_I2C_SDA_GPIO (26)
-#define VIPER_TPM_I2C_SCL_GPIO (27)
-#define VIPER_RTC_I2C_SDA_GPIO (83)
-#define VIPER_RTC_I2C_SCL_GPIO (84)
-
-#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
-#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
-
-#ifndef __ASSEMBLY__
-# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x)))
-#endif
-
-/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
-
-/* ... Physical addresses */
-#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000)
-#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002)
-#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004)
-#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006)
-#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010)
-#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000)
-#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000)
-
-/* ... Virtual addresses */
-#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
-#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
-#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
-#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
-
-/* Decode VIPER_VERSION register */
-#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7)
-#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3)
-#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7)
-
-/* Interrupt and Configuration Register (VIPER_ICR) */
-/* This is a write only register. Only CF_RST is used under Linux */
-
-#define VIPER_ICR_RETRIG (1 << 0)
-#define VIPER_ICR_AUTO_CLR (1 << 1)
-#define VIPER_ICR_R_DIS (1 << 2)
-#define VIPER_ICR_CF_RST (1 << 3)
-
-#endif
-
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
deleted file mode 100644
index 14505e83479e..000000000000
--- a/arch/arm/mach-pxa/vpac270.c
+++ /dev/null
@@ -1,736 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware definitions for Voipac PXA270
- *
- * Copyright (C) 2010
- * Marek Vasut <marek.vasut@gmail.com>
- */
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/onenand.h>
-#include <linux/dm9000.h>
-#include <linux/ucb1400.h>
-#include <linux/ata_platform.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/max1586.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa27x.h"
-#include <mach/audio.h>
-#include <mach/vpac270.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include "pxa27x-udc.h"
-#include "udc.h"
-#include <linux/platform_data/ata-pxa.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long vpac270_pin_config[] __initdata = {
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
- GPIO53_GPIO, /* SD detect */
- GPIO52_GPIO, /* SD r/o switch */
-
- /* GPIO KEYS */
- GPIO1_GPIO, /* USER BTN */
-
- /* LEDs */
- GPIO15_GPIO, /* orange led */
-
- /* FFUART */
- GPIO34_FFUART_RXD,
- GPIO39_FFUART_TXD,
- GPIO27_FFUART_RTS,
- GPIO100_FFUART_CTS,
- GPIO33_FFUART_DSR,
- GPIO40_FFUART_DTR,
- GPIO10_FFUART_DCD,
- GPIO38_FFUART_RI,
-
- /* LCD */
- GPIO58_LCD_LDD_0,
- GPIO59_LCD_LDD_1,
- GPIO60_LCD_LDD_2,
- GPIO61_LCD_LDD_3,
- GPIO62_LCD_LDD_4,
- GPIO63_LCD_LDD_5,
- GPIO64_LCD_LDD_6,
- GPIO65_LCD_LDD_7,
- GPIO66_LCD_LDD_8,
- GPIO67_LCD_LDD_9,
- GPIO68_LCD_LDD_10,
- GPIO69_LCD_LDD_11,
- GPIO70_LCD_LDD_12,
- GPIO71_LCD_LDD_13,
- GPIO72_LCD_LDD_14,
- GPIO73_LCD_LDD_15,
- GPIO86_LCD_LDD_16,
- GPIO87_LCD_LDD_17,
- GPIO74_LCD_FCLK,
- GPIO75_LCD_LCLK,
- GPIO76_LCD_PCLK,
- GPIO77_LCD_BIAS,
-
- /* PCMCIA */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO55_nPREG,
- GPIO57_nIOIS16,
- GPIO56_nPWAIT,
- GPIO104_PSKTSEL,
- GPIO84_GPIO, /* PCMCIA CD */
- GPIO35_GPIO, /* PCMCIA RDY */
- GPIO107_GPIO, /* PCMCIA PPEN */
- GPIO11_GPIO, /* PCMCIA RESET */
- GPIO17_GPIO, /* CF CD */
- GPIO12_GPIO, /* CF RDY */
- GPIO16_GPIO, /* CF RESET */
-
- /* UHC */
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
- GPIO119_USBH2_PWR,
- GPIO120_USBH2_PEN,
-
- /* UDC */
- GPIO41_GPIO,
-
- /* Ethernet */
- GPIO114_GPIO, /* IRQ */
-
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO95_AC97_nRESET,
- GPIO98_AC97_SYSCLK,
- GPIO113_GPIO, /* TS IRQ */
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* IDE */
- GPIO36_GPIO, /* IDE IRQ */
- GPIO80_DREQ_1,
-};
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition vpac270_nor_partitions[] = {
- {
- .name = "Flash",
- .offset = 0x00000000,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct physmap_flash_data vpac270_flash_data[] = {
- {
- .width = 2, /* bankwidth in bytes */
- .parts = vpac270_nor_partitions,
- .nr_parts = ARRAY_SIZE(vpac270_nor_partitions)
- }
-};
-
-static struct resource vpac270_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device vpac270_flash = {
- .name = "physmap-flash",
- .id = 0,
- .resource = &vpac270_flash_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = vpac270_flash_data,
- },
-};
-static void __init vpac270_nor_init(void)
-{
- platform_device_register(&vpac270_flash);
-}
-#else
-static inline void vpac270_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * OneNAND Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
-static struct mtd_partition vpac270_onenand_partitions[] = {
- {
- .name = "Flash",
- .offset = 0x00000000,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct onenand_platform_data vpac270_onenand_info = {
- .parts = vpac270_onenand_partitions,
- .nr_parts = ARRAY_SIZE(vpac270_onenand_partitions),
-};
-
-static struct resource vpac270_onenand_resources[] = {
- [0] = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_1M,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device vpac270_onenand = {
- .name = "onenand-flash",
- .id = -1,
- .resource = vpac270_onenand_resources,
- .num_resources = ARRAY_SIZE(vpac270_onenand_resources),
- .dev = {
- .platform_data = &vpac270_onenand_info,
- },
-};
-
-static void __init vpac270_onenand_init(void)
-{
- platform_device_register(&vpac270_onenand);
-}
-#else
-static void __init vpac270_onenand_init(void) {}
-#endif
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data vpac270_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 200,
-};
-
-static struct gpiod_lookup_table vpac270_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO53_VPAC270_SD_DETECT_N,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", GPIO52_VPAC270_SD_READONLY,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init vpac270_mmc_init(void)
-{
- gpiod_add_lookup_table(&vpac270_mci_gpio_table);
- pxa_set_mci_info(&vpac270_mci_platform_data);
-}
-#else
-static inline void vpac270_mmc_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button vpac270_pxa_buttons[] = {
- {KEY_POWER, GPIO1_VPAC270_USER_BTN, 0, "USER BTN"},
-};
-
-static struct gpio_keys_platform_data vpac270_pxa_keys_data = {
- .buttons = vpac270_pxa_buttons,
- .nbuttons = ARRAY_SIZE(vpac270_pxa_buttons),
-};
-
-static struct platform_device vpac270_pxa_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &vpac270_pxa_keys_data,
- },
-};
-
-static void __init vpac270_keys_init(void)
-{
- platform_device_register(&vpac270_pxa_keys);
-}
-#else
-static inline void vpac270_keys_init(void) {}
-#endif
-
-/******************************************************************************
- * LED
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-struct gpio_led vpac270_gpio_leds[] = {
-{
- .name = "vpac270:orange:user",
- .default_trigger = "none",
- .gpio = GPIO15_VPAC270_LED_ORANGE,
- .active_low = 1,
-}
-};
-
-static struct gpio_led_platform_data vpac270_gpio_led_info = {
- .leds = vpac270_gpio_leds,
- .num_leds = ARRAY_SIZE(vpac270_gpio_leds),
-};
-
-static struct platform_device vpac270_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &vpac270_gpio_led_info,
- }
-};
-
-static void __init vpac270_leds_init(void)
-{
- platform_device_register(&vpac270_leds);
-}
-#else
-static inline void vpac270_leds_init(void) {}
-#endif
-
-/******************************************************************************
- * USB Host
- ******************************************************************************/
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static int vpac270_ohci_init(struct device *dev)
-{
- UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
- return 0;
-}
-
-static struct pxaohci_platform_data vpac270_ohci_info = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 | ENABLE_PORT2 |
- POWER_CONTROL_LOW | POWER_SENSE_LOW,
- .init = vpac270_ohci_init,
-};
-
-static void __init vpac270_uhc_init(void)
-{
- pxa_set_ohci_info(&vpac270_ohci_info);
-}
-#else
-static inline void vpac270_uhc_init(void) {}
-#endif
-
-/******************************************************************************
- * USB Gadget
- ******************************************************************************/
-#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
-static struct gpiod_lookup_table vpac270_gpio_vbus_gpiod_table = {
- .dev_id = "gpio-vbus",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO41_VPAC270_UDC_DETECT,
- "vbus", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device vpac270_gpio_vbus = {
- .name = "gpio-vbus",
- .id = -1,
-};
-
-static void vpac270_udc_command(int cmd)
-{
- if (cmd == PXA2XX_UDC_CMD_CONNECT)
- UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
- else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
- UP2OCR = UP2OCR_HXOE;
-}
-
-static struct pxa2xx_udc_mach_info vpac270_udc_info __initdata = {
- .udc_command = vpac270_udc_command,
- .gpio_pullup = -1,
-};
-
-static void __init vpac270_udc_init(void)
-{
- pxa_set_udc_info(&vpac270_udc_info);
- gpiod_add_lookup_table(&vpac270_gpio_vbus_gpiod_table);
- platform_device_register(&vpac270_gpio_vbus);
-}
-#else
-static inline void vpac270_udc_init(void) {}
-#endif
-
-/******************************************************************************
- * Ethernet
- ******************************************************************************/
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
-static struct resource vpac270_dm9000_resources[] = {
- [0] = {
- .start = PXA_CS2_PHYS + 0x300,
- .end = PXA_CS2_PHYS + 0x303,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_CS2_PHYS + 0x304,
- .end = PXA_CS2_PHYS + 0x343,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ),
- .end = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct dm9000_plat_data vpac270_dm9000_platdata = {
- .flags = DM9000_PLATF_32BITONLY,
-};
-
-static struct platform_device vpac270_dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(vpac270_dm9000_resources),
- .resource = vpac270_dm9000_resources,
- .dev = {
- .platform_data = &vpac270_dm9000_platdata,
- }
-};
-
-static void __init vpac270_eth_init(void)
-{
- platform_device_register(&vpac270_dm9000_device);
-}
-#else
-static inline void vpac270_eth_init(void) {}
-#endif
-
-/******************************************************************************
- * Audio and Touchscreen
- ******************************************************************************/
-#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \
- defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
-static pxa2xx_audio_ops_t vpac270_ac97_pdata = {
- .reset_gpio = 95,
-};
-
-static struct ucb1400_pdata vpac270_ucb1400_pdata = {
- .irq = PXA_GPIO_TO_IRQ(GPIO113_VPAC270_TS_IRQ),
-};
-
-static struct platform_device vpac270_ucb1400_device = {
- .name = "ucb1400_core",
- .id = -1,
- .dev = {
- .platform_data = &vpac270_ucb1400_pdata,
- },
-};
-
-static void __init vpac270_ts_init(void)
-{
- pxa_set_ac97_info(&vpac270_ac97_pdata);
- platform_device_register(&vpac270_ucb1400_device);
-}
-#else
-static inline void vpac270_ts_init(void) {}
-#endif
-
-/******************************************************************************
- * RTC
- ******************************************************************************/
-#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
-static struct i2c_board_info __initdata vpac270_i2c_devs[] = {
- {
- I2C_BOARD_INFO("ds1339", 0x68),
- },
-};
-
-static void __init vpac270_rtc_init(void)
-{
- i2c_register_board_info(0, ARRAY_AND_SIZE(vpac270_i2c_devs));
-}
-#else
-static inline void vpac270_rtc_init(void) {}
-#endif
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info vpac270_lcd_modes[] = {
-{
- .pixclock = 57692,
- .xres = 640,
- .yres = 480,
- .bpp = 32,
- .depth = 18,
-
- .left_margin = 144,
- .right_margin = 32,
- .upper_margin = 13,
- .lower_margin = 30,
-
- .hsync_len = 32,
- .vsync_len = 2,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-}, { /* CRT 640x480 */
- .pixclock = 35000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .depth = 16,
-
- .left_margin = 96,
- .right_margin = 48,
- .upper_margin = 33,
- .lower_margin = 10,
-
- .hsync_len = 48,
- .vsync_len = 1,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-}, { /* CRT 800x600 H=30kHz V=48HZ */
- .pixclock = 25000,
- .xres = 800,
- .yres = 600,
- .bpp = 16,
- .depth = 16,
-
- .left_margin = 50,
- .right_margin = 1,
- .upper_margin = 21,
- .lower_margin = 12,
-
- .hsync_len = 8,
- .vsync_len = 1,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-}, { /* CRT 1024x768 H=40kHz V=50Hz */
- .pixclock = 15000,
- .xres = 1024,
- .yres = 768,
- .bpp = 16,
- .depth = 16,
-
- .left_margin = 220,
- .right_margin = 8,
- .upper_margin = 33,
- .lower_margin = 2,
-
- .hsync_len = 48,
- .vsync_len = 1,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-}
-};
-
-static struct pxafb_mach_info vpac270_lcd_screen = {
- .modes = vpac270_lcd_modes,
- .num_modes = ARRAY_SIZE(vpac270_lcd_modes),
- .lcd_conn = LCD_COLOR_TFT_18BPP,
-};
-
-static void vpac270_lcd_power(int on, struct fb_var_screeninfo *info)
-{
- gpio_set_value(GPIO81_VPAC270_BKL_ON, on);
-}
-
-static void __init vpac270_lcd_init(void)
-{
- int ret;
-
- ret = gpio_request(GPIO81_VPAC270_BKL_ON, "BKL-ON");
- if (ret) {
- pr_err("Requesting BKL-ON GPIO failed!\n");
- goto err;
- }
-
- ret = gpio_direction_output(GPIO81_VPAC270_BKL_ON, 1);
- if (ret) {
- pr_err("Setting BKL-ON GPIO direction failed!\n");
- goto err2;
- }
-
- vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power;
- pxa_set_fb_info(NULL, &vpac270_lcd_screen);
- return;
-
-err2:
- gpio_free(GPIO81_VPAC270_BKL_ON);
-err:
- return;
-}
-#else
-static inline void vpac270_lcd_init(void) {}
-#endif
-
-/******************************************************************************
- * PATA IDE
- ******************************************************************************/
-#if defined(CONFIG_PATA_PXA) || defined(CONFIG_PATA_PXA_MODULE)
-static struct pata_pxa_pdata vpac270_pata_pdata = {
- .reg_shift = 1,
- .dma_dreq = 1,
- .irq_flags = IRQF_TRIGGER_RISING,
-};
-
-static struct resource vpac270_ide_resources[] = {
- [0] = { /* I/O Base address */
- .start = PXA_CS3_PHYS + 0x120,
- .end = PXA_CS3_PHYS + 0x13f,
- .flags = IORESOURCE_MEM
- },
- [1] = { /* CTL Base address */
- .start = PXA_CS3_PHYS + 0x15c,
- .end = PXA_CS3_PHYS + 0x15f,
- .flags = IORESOURCE_MEM
- },
- [2] = { /* DMA Base address */
- .start = PXA_CS3_PHYS + 0x20,
- .end = PXA_CS3_PHYS + 0x2f,
- .flags = IORESOURCE_DMA
- },
- [3] = { /* IDE IRQ pin */
- .start = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ),
- .end = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ),
- .flags = IORESOURCE_IRQ
- }
-};
-
-static struct platform_device vpac270_ide_device = {
- .name = "pata_pxa",
- .num_resources = ARRAY_SIZE(vpac270_ide_resources),
- .resource = vpac270_ide_resources,
- .dev = {
- .platform_data = &vpac270_pata_pdata,
- .coherent_dma_mask = 0xffffffff,
- }
-};
-
-static void __init vpac270_ide_init(void)
-{
- platform_device_register(&vpac270_ide_device);
-}
-#else
-static inline void vpac270_ide_init(void) {}
-#endif
-
-/******************************************************************************
- * Core power regulator
- ******************************************************************************/
-#if defined(CONFIG_REGULATOR_MAX1586) || \
- defined(CONFIG_REGULATOR_MAX1586_MODULE)
-static struct regulator_consumer_supply vpac270_max1587a_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data vpac270_max1587a_v3_info = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 900000,
- .max_uV = 1705000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .consumer_supplies = vpac270_max1587a_consumers,
- .num_consumer_supplies = ARRAY_SIZE(vpac270_max1587a_consumers),
-};
-
-static struct max1586_subdev_data vpac270_max1587a_subdevs[] = {
- {
- .name = "vcc_core",
- .id = MAX1586_V3,
- .platform_data = &vpac270_max1587a_v3_info,
- }
-};
-
-static struct max1586_platform_data vpac270_max1587a_info = {
- .subdevs = vpac270_max1587a_subdevs,
- .num_subdevs = ARRAY_SIZE(vpac270_max1587a_subdevs),
- .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
-};
-
-static struct i2c_board_info __initdata vpac270_pi2c_board_info[] = {
- {
- I2C_BOARD_INFO("max1586", 0x14),
- .platform_data = &vpac270_max1587a_info,
- },
-};
-
-static void __init vpac270_pmic_init(void)
-{
- i2c_register_board_info(1, ARRAY_AND_SIZE(vpac270_pi2c_board_info));
-}
-#else
-static inline void vpac270_pmic_init(void) {}
-#endif
-
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void __init vpac270_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(vpac270_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- pxa_set_i2c_info(NULL);
- pxa27x_set_i2c_power_info(NULL);
-
- vpac270_pmic_init();
- vpac270_lcd_init();
- vpac270_mmc_init();
- vpac270_nor_init();
- vpac270_onenand_init();
- vpac270_leds_init();
- vpac270_keys_init();
- vpac270_uhc_init();
- vpac270_udc_init();
- vpac270_eth_init();
- vpac270_ts_init();
- vpac270_rtc_init();
- vpac270_ide_init();
-
- regulator_has_full_constraints();
-}
-
-MACHINE_START(VPAC270, "Voipac PXA270")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = vpac270_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
deleted file mode 100644
index f485146b899f..000000000000
--- a/arch/arm/mach-pxa/xcep.c
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* linux/arch/arm/mach-pxa/xcep.c
- *
- * Support for the Iskratel Electronics XCEP platform as used in
- * the Libera instruments from Instrumentation Technologies.
- *
- * Author: Ales Bardorfer <ales@i-tech.si>
- * Contributions by: Abbott, MG (Michael) <michael.abbott@diamond.ac.uk>
- * Contributions by: Matej Kenda <matej.kenda@i-tech.si>
- * Created: June 2006
- * Copyright: (C) 2006-2009 Instrumentation Technologies
- */
-
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/smc91x.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include "pxa25x.h"
-#include <mach/smemc.h>
-
-#include "generic.h"
-#include "devices.h"
-
-#define XCEP_ETH_PHYS (PXA_CS3_PHYS + 0x00000300)
-#define XCEP_ETH_PHYS_END (PXA_CS3_PHYS + 0x000fffff)
-#define XCEP_ETH_ATTR (PXA_CS3_PHYS + 0x02000000)
-#define XCEP_ETH_ATTR_END (PXA_CS3_PHYS + 0x020fffff)
-#define XCEP_ETH_IRQ IRQ_GPIO0
-
-/* XCEP CPLD base */
-#define XCEP_CPLD_BASE 0xf0000000
-
-
-/* Flash partitions. */
-
-static struct mtd_partition xcep_partitions[] = {
- {
- .name = "Bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE
- }, {
- .name = "Bootloader ENV",
- .size = 0x00040000,
- .offset = 0x00040000,
- .mask_flags = MTD_WRITEABLE
- }, {
- .name = "Kernel",
- .size = 0x00100000,
- .offset = 0x00080000,
- }, {
- .name = "Rescue fs",
- .size = 0x00280000,
- .offset = 0x00180000,
- }, {
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00400000
- }
-};
-
-static struct physmap_flash_data xcep_flash_data[] = {
- {
- .width = 4, /* bankwidth in bytes */
- .parts = xcep_partitions,
- .nr_parts = ARRAY_SIZE(xcep_partitions)
- }
-};
-
-static struct resource flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = xcep_flash_data,
- },
- .resource = &flash_resource,
- .num_resources = 1,
-};
-
-
-
-/* SMC LAN91C111 network controller. */
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .name = "smc91x-regs",
- .start = XCEP_ETH_PHYS,
- .end = XCEP_ETH_PHYS_END,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = XCEP_ETH_IRQ,
- .end = XCEP_ETH_IRQ,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .name = "smc91x-attrib",
- .start = XCEP_ETH_ATTR,
- .end = XCEP_ETH_ATTR_END,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct smc91x_platdata xcep_smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT | SMC91X_USE_DMA,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &xcep_smc91x_info,
- },
-};
-
-
-static struct platform_device *devices[] __initdata = {
- &flash_device,
- &smc91x_device,
-};
-
-
-/* We have to state that there are HWMON devices on the I2C bus on XCEP.
- * Drivers for HWMON verify capabilities of the adapter when loading and
- * refuse to attach if the adapter doesn't support HWMON class of devices. */
-static struct i2c_pxa_platform_data xcep_i2c_platform_data = {
- .class = I2C_CLASS_HWMON
-};
-
-
-static mfp_cfg_t xcep_pin_config[] __initdata = {
- GPIO79_nCS_3, /* SMC 91C111 chip select. */
- GPIO80_nCS_4, /* CPLD chip select. */
- /* SSP communication to MSP430 */
- GPIO23_SSP1_SCLK,
- GPIO24_SSP1_SFRM,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
- GPIO27_SSP1_EXTCLK
-};
-
-static void __init xcep_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(xcep_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
- pxa_set_hwuart_info(NULL);
-
- /* See Intel XScale Developer's Guide for details */
- /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */
- __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1);
- /* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */
- __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2);
-
- platform_add_devices(ARRAY_AND_SIZE(devices));
- pxa_set_i2c_info(&xcep_i2c_platform_data);
-}
-
-MACHINE_START(XCEP, "Iskratel XCEP")
- .atag_offset = 0x100,
- .init_machine = xcep_init,
- .map_io = pxa25x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa25x_init_irq,
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .restart = pxa_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
deleted file mode 100644
index 7eaeda269927..000000000000
--- a/arch/arm/mach-pxa/z2.c
+++ /dev/null
@@ -1,770 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/z2.c
- *
- * Support for the Zipit Z2 Handheld device.
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * Based on research and code by: Ken McGuire
- * Based on mainstone.c as modified for the Zipit Z2.
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/z2_battery.h>
-#include <linux/dma-mapping.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/spi/libertas_spi.h>
-#include <linux/power_supply.h>
-#include <linux/mtd/physmap.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio_keys.h>
-#include <linux/delay.h>
-#include <linux/regulator/machine.h>
-#include <linux/platform_data/i2c-pxa.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa27x.h"
-#include "mfp-pxa27x.h"
-#include <mach/z2.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include "pm.h"
-
-#include "generic.h"
-#include "devices.h"
-
-/******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static unsigned long z2_pin_config[] = {
-
- /* LCD - 16bpp Active TFT */
- GPIO58_LCD_LDD_0,
- GPIO59_LCD_LDD_1,
- GPIO60_LCD_LDD_2,
- GPIO61_LCD_LDD_3,
- GPIO62_LCD_LDD_4,
- GPIO63_LCD_LDD_5,
- GPIO64_LCD_LDD_6,
- GPIO65_LCD_LDD_7,
- GPIO66_LCD_LDD_8,
- GPIO67_LCD_LDD_9,
- GPIO68_LCD_LDD_10,
- GPIO69_LCD_LDD_11,
- GPIO70_LCD_LDD_12,
- GPIO71_LCD_LDD_13,
- GPIO72_LCD_LDD_14,
- GPIO73_LCD_LDD_15,
- GPIO74_LCD_FCLK,
- GPIO75_LCD_LCLK,
- GPIO76_LCD_PCLK,
- GPIO77_LCD_BIAS,
- GPIO19_GPIO, /* LCD reset */
- GPIO88_GPIO, /* LCD chipselect */
-
- /* PWM */
- GPIO115_PWM1_OUT, /* Keypad Backlight */
- GPIO11_PWM2_OUT, /* LCD Backlight */
-
- /* MMC */
- GPIO32_MMC_CLK,
- GPIO112_MMC_CMD,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO96_GPIO, /* SD detect */
-
- /* STUART */
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* Keypad */
- GPIO100_KP_MKIN_0,
- GPIO101_KP_MKIN_1,
- GPIO102_KP_MKIN_2,
- GPIO34_KP_MKIN_3,
- GPIO38_KP_MKIN_4,
- GPIO16_KP_MKIN_5,
- GPIO17_KP_MKIN_6,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
- GPIO35_KP_MKOUT_6,
- GPIO41_KP_MKOUT_7,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* SSP1 */
- GPIO23_SSP1_SCLK, /* SSP1_SCK */
- GPIO25_SSP1_TXD, /* SSP1_TXD */
- GPIO26_SSP1_RXD, /* SSP1_RXD */
-
- /* SSP2 */
- GPIO22_SSP2_SCLK, /* SSP2_SCK */
- GPIO13_SSP2_TXD, /* SSP2_TXD */
- GPIO40_SSP2_RXD, /* SSP2_RXD */
-
- /* LEDs */
- GPIO10_GPIO, /* WiFi LED */
- GPIO83_GPIO, /* Charging LED */
- GPIO85_GPIO, /* Charged LED */
-
- /* I2S */
- GPIO28_I2S_BITCLK_OUT,
- GPIO29_I2S_SDATA_IN,
- GPIO30_I2S_SDATA_OUT,
- GPIO31_I2S_SYNC,
- GPIO113_I2S_SYSCLK,
-
- /* MISC */
- GPIO0_GPIO, /* AC power detect */
- GPIO1_GPIO, /* Power button */
- GPIO37_GPIO, /* Headphone detect */
- GPIO98_GPIO, /* Lid switch */
- GPIO14_GPIO, /* WiFi Power */
- GPIO24_GPIO, /* WiFi CS */
- GPIO36_GPIO, /* WiFi IRQ */
- GPIO88_GPIO, /* LCD CS */
-};
-
-/******************************************************************************
- * NOR Flash
- ******************************************************************************/
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct resource z2_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_8M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct mtd_partition z2_flash_parts[] = {
- {
- .name = "U-Boot Bootloader",
- .offset = 0x0,
- .size = 0x40000,
- }, {
- .name = "U-Boot Environment",
- .offset = 0x40000,
- .size = 0x20000,
- }, {
- .name = "Flash",
- .offset = 0x60000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data z2_flash_data = {
- .width = 2,
- .parts = z2_flash_parts,
- .nr_parts = ARRAY_SIZE(z2_flash_parts),
-};
-
-static struct platform_device z2_flash = {
- .name = "physmap-flash",
- .id = -1,
- .resource = &z2_flash_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = &z2_flash_data,
- },
-};
-
-static void __init z2_nor_init(void)
-{
- platform_device_register(&z2_flash);
-}
-#else
-static inline void z2_nor_init(void) {}
-#endif
-
-/******************************************************************************
- * Backlight
- ******************************************************************************/
-#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
-static struct pwm_lookup z2_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.1", 0, "pwm-backlight.0", NULL, 1260320,
- PWM_POLARITY_NORMAL),
- PWM_LOOKUP("pxa27x-pwm.0", 1, "pwm-backlight.1", NULL, 1260320,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data z2_backlight_data[] = {
- [0] = {
- /* Keypad Backlight */
- .max_brightness = 1023,
- .dft_brightness = 0,
- },
- [1] = {
- /* LCD Backlight */
- .max_brightness = 1023,
- .dft_brightness = 512,
- },
-};
-
-static struct platform_device z2_backlight_devices[2] = {
- {
- .name = "pwm-backlight",
- .id = 0,
- .dev = {
- .platform_data = &z2_backlight_data[1],
- },
- },
- {
- .name = "pwm-backlight",
- .id = 1,
- .dev = {
- .platform_data = &z2_backlight_data[0],
- },
- },
-};
-static void __init z2_pwm_init(void)
-{
- pwm_add_table(z2_pwm_lookup, ARRAY_SIZE(z2_pwm_lookup));
- platform_device_register(&z2_backlight_devices[0]);
- platform_device_register(&z2_backlight_devices[1]);
-}
-#else
-static inline void z2_pwm_init(void) {}
-#endif
-
-/******************************************************************************
- * Framebuffer
- ******************************************************************************/
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info z2_lcd_modes[] = {
-{
- .pixclock = 192000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
-
- .left_margin = 4,
- .right_margin = 8,
- .upper_margin = 4,
- .lower_margin = 8,
-
- .hsync_len = 4,
- .vsync_len = 4,
-},
-};
-
-static struct pxafb_mach_info z2_lcd_screen = {
- .modes = z2_lcd_modes,
- .num_modes = ARRAY_SIZE(z2_lcd_modes),
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_BIAS_ACTIVE_LOW |
- LCD_ALTERNATE_MAPPING,
-};
-
-static void __init z2_lcd_init(void)
-{
- pxa_set_fb_info(NULL, &z2_lcd_screen);
-}
-#else
-static inline void z2_lcd_init(void) {}
-#endif
-
-/******************************************************************************
- * SD/MMC card controller
- ******************************************************************************/
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data z2_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 200,
-};
-
-static struct gpiod_lookup_table z2_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO96_ZIPITZ2_SD_DETECT,
- "cd", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init z2_mmc_init(void)
-{
- gpiod_add_lookup_table(&z2_mci_gpio_table);
- pxa_set_mci_info(&z2_mci_platform_data);
-}
-#else
-static inline void z2_mmc_init(void) {}
-#endif
-
-/******************************************************************************
- * LEDs
- ******************************************************************************/
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-struct gpio_led z2_gpio_leds[] = {
-{
- .name = "z2:green:wifi",
- .default_trigger = "none",
- .gpio = GPIO10_ZIPITZ2_LED_WIFI,
- .active_low = 1,
-}, {
- .name = "z2:green:charged",
- .default_trigger = "mmc0",
- .gpio = GPIO85_ZIPITZ2_LED_CHARGED,
- .active_low = 1,
-}, {
- .name = "z2:amber:charging",
- .default_trigger = "Z2-charging-or-full",
- .gpio = GPIO83_ZIPITZ2_LED_CHARGING,
- .active_low = 1,
-},
-};
-
-static struct gpio_led_platform_data z2_gpio_led_info = {
- .leds = z2_gpio_leds,
- .num_leds = ARRAY_SIZE(z2_gpio_leds),
-};
-
-static struct platform_device z2_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &z2_gpio_led_info,
- }
-};
-
-static void __init z2_leds_init(void)
-{
- platform_device_register(&z2_leds);
-}
-#else
-static inline void z2_leds_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keyboard
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int z2_matrix_keys[] = {
- KEY(0, 0, KEY_OPTION),
- KEY(1, 0, KEY_UP),
- KEY(2, 0, KEY_DOWN),
- KEY(3, 0, KEY_LEFT),
- KEY(4, 0, KEY_RIGHT),
- KEY(5, 0, KEY_END),
- KEY(6, 0, KEY_KPPLUS),
-
- KEY(0, 1, KEY_HOME),
- KEY(1, 1, KEY_Q),
- KEY(2, 1, KEY_I),
- KEY(3, 1, KEY_G),
- KEY(4, 1, KEY_X),
- KEY(5, 1, KEY_ENTER),
- KEY(6, 1, KEY_KPMINUS),
-
- KEY(0, 2, KEY_PAGEUP),
- KEY(1, 2, KEY_W),
- KEY(2, 2, KEY_O),
- KEY(3, 2, KEY_H),
- KEY(4, 2, KEY_C),
- KEY(5, 2, KEY_LEFTALT),
-
- KEY(0, 3, KEY_PAGEDOWN),
- KEY(1, 3, KEY_E),
- KEY(2, 3, KEY_P),
- KEY(3, 3, KEY_J),
- KEY(4, 3, KEY_V),
- KEY(5, 3, KEY_LEFTSHIFT),
-
- KEY(0, 4, KEY_ESC),
- KEY(1, 4, KEY_R),
- KEY(2, 4, KEY_A),
- KEY(3, 4, KEY_K),
- KEY(4, 4, KEY_B),
- KEY(5, 4, KEY_LEFTCTRL),
-
- KEY(0, 5, KEY_TAB),
- KEY(1, 5, KEY_T),
- KEY(2, 5, KEY_S),
- KEY(3, 5, KEY_L),
- KEY(4, 5, KEY_N),
- KEY(5, 5, KEY_SPACE),
-
- KEY(0, 6, KEY_STOPCD),
- KEY(1, 6, KEY_Y),
- KEY(2, 6, KEY_D),
- KEY(3, 6, KEY_BACKSPACE),
- KEY(4, 6, KEY_M),
- KEY(5, 6, KEY_COMMA),
-
- KEY(0, 7, KEY_PLAYCD),
- KEY(1, 7, KEY_U),
- KEY(2, 7, KEY_F),
- KEY(3, 7, KEY_Z),
- KEY(4, 7, KEY_SEMICOLON),
- KEY(5, 7, KEY_DOT),
-};
-
-static struct matrix_keymap_data z2_matrix_keymap_data = {
- .keymap = z2_matrix_keys,
- .keymap_size = ARRAY_SIZE(z2_matrix_keys),
-};
-
-static struct pxa27x_keypad_platform_data z2_keypad_platform_data = {
- .matrix_key_rows = 7,
- .matrix_key_cols = 8,
- .matrix_keymap_data = &z2_matrix_keymap_data,
-
- .debounce_interval = 30,
-};
-
-static void __init z2_mkp_init(void)
-{
- pxa_set_keypad_info(&z2_keypad_platform_data);
-}
-#else
-static inline void z2_mkp_init(void) {}
-#endif
-
-/******************************************************************************
- * GPIO keys
- ******************************************************************************/
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button z2_pxa_buttons[] = {
- {
- .code = KEY_POWER,
- .gpio = GPIO1_ZIPITZ2_POWER_BUTTON,
- .active_low = 0,
- .desc = "Power Button",
- .wakeup = 1,
- .type = EV_KEY,
- },
- {
- .code = SW_LID,
- .gpio = GPIO98_ZIPITZ2_LID_BUTTON,
- .active_low = 1,
- .desc = "Lid Switch",
- .wakeup = 0,
- .type = EV_SW,
- },
-};
-
-static struct gpio_keys_platform_data z2_pxa_keys_data = {
- .buttons = z2_pxa_buttons,
- .nbuttons = ARRAY_SIZE(z2_pxa_buttons),
-};
-
-static struct platform_device z2_pxa_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &z2_pxa_keys_data,
- },
-};
-
-static void __init z2_keys_init(void)
-{
- platform_device_register(&z2_pxa_keys);
-}
-#else
-static inline void z2_keys_init(void) {}
-#endif
-
-/******************************************************************************
- * Battery
- ******************************************************************************/
-#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
-static struct z2_battery_info batt_chip_info = {
- .batt_I2C_bus = 0,
- .batt_I2C_addr = 0x55,
- .batt_I2C_reg = 2,
- .min_voltage = 3475000,
- .max_voltage = 4190000,
- .batt_div = 59,
- .batt_mult = 1000000,
- .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION,
- .batt_name = "Z2",
-};
-
-static struct gpiod_lookup_table z2_battery_gpio_table = {
- .dev_id = "aer915",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO0_ZIPITZ2_AC_DETECT,
- NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct i2c_board_info __initdata z2_i2c_board_info[] = {
- {
- I2C_BOARD_INFO("aer915", 0x55),
- .dev_name = "aer915",
- .platform_data = &batt_chip_info,
- }, {
- I2C_BOARD_INFO("wm8750", 0x1b),
- },
-
-};
-
-static void __init z2_i2c_init(void)
-{
- pxa_set_i2c_info(NULL);
- gpiod_add_lookup_table(&z2_battery_gpio_table);
- i2c_register_board_info(0, ARRAY_AND_SIZE(z2_i2c_board_info));
-}
-#else
-static inline void z2_i2c_init(void) {}
-#endif
-
-/******************************************************************************
- * SSP Devices - WiFi and LCD control
- ******************************************************************************/
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-/* WiFi */
-static int z2_lbs_spi_setup(struct spi_device *spi)
-{
- int ret = 0;
-
- ret = gpio_request(GPIO14_ZIPITZ2_WIFI_POWER, "WiFi Power");
- if (ret)
- goto err;
-
- ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_POWER, 1);
- if (ret)
- goto err2;
-
- /* Wait until card is powered on */
- mdelay(180);
-
- spi->bits_per_word = 16;
- spi->mode = SPI_MODE_2,
-
- spi_setup(spi);
-
- return 0;
-
-err2:
- gpio_free(GPIO14_ZIPITZ2_WIFI_POWER);
-err:
- return ret;
-};
-
-static int z2_lbs_spi_teardown(struct spi_device *spi)
-{
- gpio_set_value(GPIO14_ZIPITZ2_WIFI_POWER, 0);
- gpio_free(GPIO14_ZIPITZ2_WIFI_POWER);
-
- return 0;
-};
-
-static struct pxa2xx_spi_chip z2_lbs_chip_info = {
- .rx_threshold = 8,
- .tx_threshold = 8,
- .timeout = 1000,
-};
-
-static struct libertas_spi_platform_data z2_lbs_pdata = {
- .use_dummy_writes = 1,
- .setup = z2_lbs_spi_setup,
- .teardown = z2_lbs_spi_teardown,
-};
-
-/* LCD */
-static struct pxa2xx_spi_chip lms283_chip_info = {
- .rx_threshold = 1,
- .tx_threshold = 1,
- .timeout = 64,
-};
-
-static struct gpiod_lookup_table lms283_gpio_table = {
- .dev_id = "spi2.0", /* SPI bus 2 chip select 0 */
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO19_ZIPITZ2_LCD_RESET,
- "reset", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-{
- .modalias = "libertas_spi",
- .platform_data = &z2_lbs_pdata,
- .controller_data = &z2_lbs_chip_info,
- .irq = PXA_GPIO_TO_IRQ(GPIO36_ZIPITZ2_WIFI_IRQ),
- .max_speed_hz = 13000000,
- .bus_num = 1,
- .chip_select = 0,
-},
-{
- .modalias = "lms283gf05",
- .controller_data = &lms283_chip_info,
- .max_speed_hz = 400000,
- .bus_num = 2,
- .chip_select = 0,
-},
-};
-
-static struct pxa2xx_spi_controller pxa_ssp1_master_info = {
- .num_chipselect = 1,
- .enable_dma = 1,
-};
-
-static struct pxa2xx_spi_controller pxa_ssp2_master_info = {
- .num_chipselect = 1,
-};
-
-static struct gpiod_lookup_table pxa_ssp1_gpio_table = {
- .dev_id = "pxa2xx-spi.1",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", GPIO24_ZIPITZ2_WIFI_CS, "cs", 0, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct gpiod_lookup_table pxa_ssp2_gpio_table = {
- .dev_id = "pxa2xx-spi.2",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", GPIO88_ZIPITZ2_LCD_CS, "cs", 0, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init z2_spi_init(void)
-{
- gpiod_add_lookup_table(&pxa_ssp1_gpio_table);
- gpiod_add_lookup_table(&pxa_ssp2_gpio_table);
- pxa2xx_set_spi_info(1, &pxa_ssp1_master_info);
- pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
- gpiod_add_lookup_table(&lms283_gpio_table);
- spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-}
-#else
-static inline void z2_spi_init(void) {}
-#endif
-
-/******************************************************************************
- * Core power regulator
- ******************************************************************************/
-#if defined(CONFIG_REGULATOR_TPS65023) || \
- defined(CONFIG_REGULATOR_TPS65023_MODULE)
-static struct regulator_consumer_supply z2_tps65021_consumers[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data z2_tps65021_info[] = {
- {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 800000,
- .max_uV = 1600000,
- .always_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .consumer_supplies = z2_tps65021_consumers,
- .num_consumer_supplies = ARRAY_SIZE(z2_tps65021_consumers),
- }, {
- .constraints = {
- .name = "DCDC2",
- .min_uV = 3300000,
- .max_uV = 3300000,
- .always_on = 1,
- },
- }, {
- .constraints = {
- .name = "DCDC3",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .always_on = 1,
- },
- }, {
- .constraints = {
- .name = "LDO1",
- .min_uV = 1000000,
- .max_uV = 3150000,
- .always_on = 1,
- },
- }, {
- .constraints = {
- .name = "LDO2",
- .min_uV = 1050000,
- .max_uV = 3300000,
- .always_on = 1,
- },
- }
-};
-
-static struct i2c_board_info __initdata z2_pi2c_board_info[] = {
- {
- I2C_BOARD_INFO("tps65021", 0x48),
- .platform_data = &z2_tps65021_info,
- },
-};
-
-static void __init z2_pmic_init(void)
-{
- pxa27x_set_i2c_power_info(NULL);
- i2c_register_board_info(1, ARRAY_AND_SIZE(z2_pi2c_board_info));
-}
-#else
-static inline void z2_pmic_init(void) {}
-#endif
-
-#ifdef CONFIG_PM
-static void z2_power_off(void)
-{
- /* We're using deep sleep as poweroff, so clear PSPR to ensure that
- * bootloader will jump to its entry point in resume handler
- */
- PSPR = 0x0;
- local_irq_disable();
- pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
- pxa27x_cpu_pm_enter(PM_SUSPEND_MEM);
-}
-#else
-#define z2_power_off NULL
-#endif
-
-/******************************************************************************
- * Machine init
- ******************************************************************************/
-static void __init z2_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(z2_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- z2_lcd_init();
- z2_mmc_init();
- z2_mkp_init();
- z2_i2c_init();
- z2_spi_init();
- z2_nor_init();
- z2_pwm_init();
- z2_leds_init();
- z2_keys_init();
- z2_pmic_init();
-
- pm_power_off = z2_power_off;
-}
-
-MACHINE_START(ZIPIT2, "Zipit Z2")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = z2_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
deleted file mode 100644
index 97700429633e..000000000000
--- a/arch/arm/mach-pxa/zeus.c
+++ /dev/null
@@ -1,962 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for the Arcom ZEUS.
- *
- * Copyright (C) 2006 Arcom Control Systems Ltd.
- *
- * Loosely based on Arcom's 2.6.16.28.
- * Maintained by Marc Zyngier <maz@misterjones.org>
- */
-
-#include <linux/cpufreq.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/irq.h>
-#include <linux/pm.h>
-#include <linux/property.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/serial_8250.h>
-#include <linux/dm9000.h>
-#include <linux/mmc/host.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/apm-emulation.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/suspend.h>
-#include <asm/system_info.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "pxa27x.h"
-#include "devices.h"
-#include <mach/regs-uart.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include "pxa27x-udc.h"
-#include "udc.h"
-#include <linux/platform_data/video-pxafb.h>
-#include "pm.h"
-#include <mach/audio.h>
-#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
-#include "zeus.h"
-#include <mach/smemc.h>
-
-#include "generic.h"
-
-/*
- * Interrupt handling
- */
-
-static unsigned long zeus_irq_enabled_mask;
-static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
-static const int zeus_isa_irq_map[] = {
- 0, /* ISA irq #0, invalid */
- 0, /* ISA irq #1, invalid */
- 0, /* ISA irq #2, invalid */
- 1 << 0, /* ISA irq #3 */
- 1 << 1, /* ISA irq #4 */
- 1 << 2, /* ISA irq #5 */
- 1 << 3, /* ISA irq #6 */
- 1 << 4, /* ISA irq #7 */
- 0, /* ISA irq #8, invalid */
- 0, /* ISA irq #9, invalid */
- 1 << 5, /* ISA irq #10 */
- 1 << 6, /* ISA irq #11 */
- 1 << 7, /* ISA irq #12 */
-};
-
-static inline int zeus_irq_to_bitmask(unsigned int irq)
-{
- return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
-}
-
-static inline int zeus_bit_to_irq(int bit)
-{
- return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
-}
-
-static void zeus_ack_irq(struct irq_data *d)
-{
- __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
-}
-
-static void zeus_mask_irq(struct irq_data *d)
-{
- zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
-}
-
-static void zeus_unmask_irq(struct irq_data *d)
-{
- zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
-}
-
-static inline unsigned long zeus_irq_pending(void)
-{
- return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
-}
-
-static void zeus_irq_handler(struct irq_desc *desc)
-{
- unsigned int irq;
- unsigned long pending;
-
- pending = zeus_irq_pending();
- do {
- /* we're in a chained irq handler,
- * so ack the interrupt by hand */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-
- if (likely(pending)) {
- irq = zeus_bit_to_irq(__ffs(pending));
- generic_handle_irq(irq);
- }
- pending = zeus_irq_pending();
- } while (pending);
-}
-
-static struct irq_chip zeus_irq_chip = {
- .name = "ISA",
- .irq_ack = zeus_ack_irq,
- .irq_mask = zeus_mask_irq,
- .irq_unmask = zeus_unmask_irq,
-};
-
-static void __init zeus_init_irq(void)
-{
- int level;
- int isa_irq;
-
- pxa27x_init_irq();
-
- /* Peripheral IRQs. It would be nice to move those inside driver
- configuration, but it is not supported at the moment. */
- irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
- irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
- irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
- irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
- IRQ_TYPE_EDGE_FALLING);
- irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
-
- /* Setup ISA IRQs */
- for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
- isa_irq = zeus_bit_to_irq(level);
- irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
- handle_edge_irq);
- irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-
- irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
- irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
-}
-
-
-/*
- * Platform devices
- */
-
-/* Flash */
-static struct resource zeus_mtd_resources[] = {
- [0] = { /* NOR Flash (up to 64MB) */
- .start = ZEUS_FLASH_PHYS,
- .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* SRAM */
- .start = ZEUS_SRAM_PHYS,
- .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct physmap_flash_data zeus_flash_data[] = {
- [0] = {
- .width = 2,
- .parts = NULL,
- .nr_parts = 0,
- },
-};
-
-static struct platform_device zeus_mtd_devices[] = {
- [0] = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &zeus_flash_data[0],
- },
- .resource = &zeus_mtd_resources[0],
- .num_resources = 1,
- },
-};
-
-/* Serial */
-static struct resource zeus_serial_resources[] = {
- {
- .start = 0x10000000,
- .end = 0x1000000f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x10800000,
- .end = 0x1080000f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x11000000,
- .end = 0x1100000f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x40100000,
- .end = 0x4010001f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x40200000,
- .end = 0x4020001f,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x40700000,
- .end = 0x4070001f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct plat_serial8250_port serial_platform_data[] = {
- /* External UARTs */
- /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
- { /* COM1 */
- .mapbase = 0x10000000,
- .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
- .irqflags = IRQF_TRIGGER_RISING,
- .uartclk = 14745600,
- .regshift = 1,
- .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- { /* COM2 */
- .mapbase = 0x10800000,
- .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
- .irqflags = IRQF_TRIGGER_RISING,
- .uartclk = 14745600,
- .regshift = 1,
- .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- { /* COM3 */
- .mapbase = 0x11000000,
- .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
- .irqflags = IRQF_TRIGGER_RISING,
- .uartclk = 14745600,
- .regshift = 1,
- .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- { /* COM4 */
- .mapbase = 0x11800000,
- .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
- .irqflags = IRQF_TRIGGER_RISING,
- .uartclk = 14745600,
- .regshift = 1,
- .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- /* Internal UARTs */
- { /* FFUART */
- .membase = (void *)&FFUART,
- .mapbase = __PREG(FFUART),
- .irq = IRQ_FFUART,
- .uartclk = 921600 * 16,
- .regshift = 2,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- { /* BTUART */
- .membase = (void *)&BTUART,
- .mapbase = __PREG(BTUART),
- .irq = IRQ_BTUART,
- .uartclk = 921600 * 16,
- .regshift = 2,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- { /* STUART */
- .membase = (void *)&STUART,
- .mapbase = __PREG(STUART),
- .irq = IRQ_STUART,
- .uartclk = 921600 * 16,
- .regshift = 2,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
- .iotype = UPIO_MEM,
- },
- { },
-};
-
-static struct platform_device zeus_serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = serial_platform_data,
- },
- .num_resources = ARRAY_SIZE(zeus_serial_resources),
- .resource = zeus_serial_resources,
-};
-
-/* Ethernet */
-static struct resource zeus_dm9k0_resource[] = {
- [0] = {
- .start = ZEUS_ETH0_PHYS,
- .end = ZEUS_ETH0_PHYS + 1,
- .flags = IORESOURCE_MEM
- },
- [1] = {
- .start = ZEUS_ETH0_PHYS + 2,
- .end = ZEUS_ETH0_PHYS + 3,
- .flags = IORESOURCE_MEM
- },
- [2] = {
- .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
- .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct resource zeus_dm9k1_resource[] = {
- [0] = {
- .start = ZEUS_ETH1_PHYS,
- .end = ZEUS_ETH1_PHYS + 1,
- .flags = IORESOURCE_MEM
- },
- [1] = {
- .start = ZEUS_ETH1_PHYS + 2,
- .end = ZEUS_ETH1_PHYS + 3,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
- .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct dm9000_plat_data zeus_dm9k_platdata = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device zeus_dm9k0_device = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
- .resource = zeus_dm9k0_resource,
- .dev = {
- .platform_data = &zeus_dm9k_platdata,
- }
-};
-
-static struct platform_device zeus_dm9k1_device = {
- .name = "dm9000",
- .id = 1,
- .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
- .resource = zeus_dm9k1_resource,
- .dev = {
- .platform_data = &zeus_dm9k_platdata,
- }
-};
-
-/* External SRAM */
-static struct resource zeus_sram_resource = {
- .start = ZEUS_SRAM_PHYS,
- .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device zeus_sram_device = {
- .name = "pxa2xx-8bit-sram",
- .id = 0,
- .num_resources = 1,
- .resource = &zeus_sram_resource,
-};
-
-/* SPI interface on SSP3 */
-static struct pxa2xx_spi_controller pxa2xx_spi_ssp3_master_info = {
- .num_chipselect = 1,
- .enable_dma = 1,
-};
-
-/* CAN bus on SPI */
-static struct regulator_consumer_supply can_regulator_consumer =
- REGULATOR_SUPPLY("vdd", "spi3.0");
-
-static struct regulator_init_data can_regulator_init_data = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .consumer_supplies = &can_regulator_consumer,
- .num_consumer_supplies = 1,
-};
-
-static struct fixed_voltage_config can_regulator_pdata = {
- .supply_name = "CAN_SHDN",
- .microvolts = 3300000,
- .init_data = &can_regulator_init_data,
-};
-
-static struct platform_device can_regulator_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &can_regulator_pdata,
- },
-};
-
-static struct gpiod_lookup_table can_regulator_gpiod_table = {
- .dev_id = "reg-fixed-voltage.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", ZEUS_CAN_SHDN_GPIO,
- NULL, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static const struct property_entry mcp251x_properties[] = {
- PROPERTY_ENTRY_U32("clock-frequency", 16000000),
- {}
-};
-
-static const struct software_node mcp251x_node = {
- .properties = mcp251x_properties,
-};
-
-static struct spi_board_info zeus_spi_board_info[] = {
- [0] = {
- .modalias = "mcp2515",
- .swnode = &mcp251x_node,
- .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
- .max_speed_hz = 1*1000*1000,
- .bus_num = 3,
- .mode = SPI_MODE_0,
- .chip_select = 0,
- },
-};
-
-/* Leds */
-static struct gpio_led zeus_leds[] = {
- [0] = {
- .name = "zeus:yellow:1",
- .default_trigger = "heartbeat",
- .gpio = ZEUS_EXT0_GPIO(3),
- .active_low = 1,
- },
- [1] = {
- .name = "zeus:yellow:2",
- .default_trigger = "default-on",
- .gpio = ZEUS_EXT0_GPIO(4),
- .active_low = 1,
- },
- [2] = {
- .name = "zeus:yellow:3",
- .default_trigger = "default-on",
- .gpio = ZEUS_EXT0_GPIO(5),
- .active_low = 1,
- },
-};
-
-static struct gpio_led_platform_data zeus_leds_info = {
- .leds = zeus_leds,
- .num_leds = ARRAY_SIZE(zeus_leds),
-};
-
-static struct platform_device zeus_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &zeus_leds_info,
- },
-};
-
-static void zeus_cf_reset(int state)
-{
- u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
-
- if (state)
- cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
- else
- cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
-
- __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
-}
-
-static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
- .cd_gpio = ZEUS_CF_CD_GPIO,
- .rdy_gpio = ZEUS_CF_RDY_GPIO,
- .pwr_gpio = ZEUS_CF_PWEN_GPIO,
- .reset = zeus_cf_reset,
-};
-
-static struct platform_device zeus_pcmcia_device = {
- .name = "zeus-pcmcia",
- .id = -1,
- .dev = {
- .platform_data = &zeus_pcmcia_info,
- },
-};
-
-static struct resource zeus_max6369_resource = {
- .start = ZEUS_CPLD_EXTWDOG_PHYS,
- .end = ZEUS_CPLD_EXTWDOG_PHYS,
- .flags = IORESOURCE_MEM,
-};
-
-struct platform_device zeus_max6369_device = {
- .name = "max6369_wdt",
- .id = -1,
- .resource = &zeus_max6369_resource,
- .num_resources = 1,
-};
-
-/* AC'97 */
-static pxa2xx_audio_ops_t zeus_ac97_info = {
- .reset_gpio = 95,
-};
-
-
-/*
- * USB host
- */
-
-static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
- REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
-};
-
-static struct regulator_init_data zeus_ohci_regulator_data = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(zeus_ohci_regulator_supplies),
- .consumer_supplies = zeus_ohci_regulator_supplies,
-};
-
-static struct fixed_voltage_config zeus_ohci_regulator_config = {
- .supply_name = "vbus2",
- .microvolts = 5000000, /* 5.0V */
- .startup_delay = 0,
- .init_data = &zeus_ohci_regulator_data,
-};
-
-static struct platform_device zeus_ohci_regulator_device = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &zeus_ohci_regulator_config,
- },
-};
-
-static struct gpiod_lookup_table zeus_ohci_regulator_gpiod_table = {
- .dev_id = "reg-fixed-voltage.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", ZEUS_USB2_PWREN_GPIO,
- NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct pxaohci_platform_data zeus_ohci_platform_data = {
- .port_mode = PMM_NPS_MODE,
- /* Clear Power Control Polarity Low and set Power Sense
- * Polarity Low. Supply power to USB ports. */
- .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
-};
-
-static void __init zeus_register_ohci(void)
-{
- /* Port 2 is shared between host and client interface. */
- UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
-
- pxa_set_ohci_info(&zeus_ohci_platform_data);
-}
-
-/*
- * Flat Panel
- */
-
-static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
-{
- gpio_set_value(ZEUS_LCD_EN_GPIO, on);
-}
-
-static void zeus_backlight_power(int on)
-{
- gpio_set_value(ZEUS_BKLEN_GPIO, on);
-}
-
-static int zeus_setup_fb_gpios(void)
-{
- int err;
-
- if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
- goto out_err;
-
- if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
- goto out_err_lcd;
-
- if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
- goto out_err_lcd;
-
- if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
- goto out_err_bkl;
-
- return 0;
-
-out_err_bkl:
- gpio_free(ZEUS_BKLEN_GPIO);
-out_err_lcd:
- gpio_free(ZEUS_LCD_EN_GPIO);
-out_err:
- return err;
-}
-
-static struct pxafb_mode_info zeus_fb_mode_info[] = {
- {
- .pixclock = 39722,
-
- .xres = 640,
- .yres = 480,
-
- .bpp = 16,
-
- .hsync_len = 63,
- .left_margin = 16,
- .right_margin = 81,
-
- .vsync_len = 2,
- .upper_margin = 12,
- .lower_margin = 31,
-
- .sync = 0,
- },
-};
-
-static struct pxafb_mach_info zeus_fb_info = {
- .modes = zeus_fb_mode_info,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
- .pxafb_lcd_power = zeus_lcd_power,
- .pxafb_backlight_power = zeus_backlight_power,
-};
-
-/*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
- */
-
-static struct pxamci_platform_data zeus_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .detect_delay_ms = 250,
- .gpio_card_ro_invert = 1,
-};
-
-static struct gpiod_lookup_table zeus_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_CD_GPIO,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_WP_GPIO,
- "wp", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/*
- * USB Device Controller
- */
-static void zeus_udc_command(int cmd)
-{
- switch (cmd) {
- case PXA2XX_UDC_CMD_DISCONNECT:
- pr_info("zeus: disconnecting USB client\n");
- UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
- break;
-
- case PXA2XX_UDC_CMD_CONNECT:
- pr_info("zeus: connecting USB client\n");
- UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
- break;
- }
-}
-
-static struct pxa2xx_udc_mach_info zeus_udc_info = {
- .udc_command = zeus_udc_command,
-};
-
-static struct platform_device *zeus_devices[] __initdata = {
- &zeus_serial_device,
- &zeus_mtd_devices[0],
- &zeus_dm9k0_device,
- &zeus_dm9k1_device,
- &zeus_sram_device,
- &zeus_leds_device,
- &zeus_pcmcia_device,
- &zeus_max6369_device,
- &can_regulator_device,
- &zeus_ohci_regulator_device,
-};
-
-#ifdef CONFIG_PM
-static void zeus_power_off(void)
-{
- local_irq_disable();
- cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
-}
-#else
-#define zeus_power_off NULL
-#endif
-
-#ifdef CONFIG_APM_EMULATION
-static void zeus_get_power_status(struct apm_power_info *info)
-{
- /* Power supply is always present */
- info->ac_line_status = APM_AC_ONLINE;
- info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
- info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
-}
-
-static inline void zeus_setup_apm(void)
-{
- apm_get_power_status = zeus_get_power_status;
-}
-#else
-static inline void zeus_setup_apm(void)
-{
-}
-#endif
-
-static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
- unsigned ngpio, void *context)
-{
- int i;
- u8 pcb_info = 0;
-
- for (i = 0; i < 8; i++) {
- int pcb_bit = gpio + i + 8;
-
- if (gpio_request(pcb_bit, "pcb info")) {
- dev_err(&client->dev, "Can't request pcb info %d\n", i);
- continue;
- }
-
- if (gpio_direction_input(pcb_bit)) {
- dev_err(&client->dev, "Can't read pcb info %d\n", i);
- gpio_free(pcb_bit);
- continue;
- }
-
- pcb_info |= !!gpio_get_value(pcb_bit) << i;
-
- gpio_free(pcb_bit);
- }
-
- dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
- pcb_info >> 4, pcb_info & 0xf);
-
- return 0;
-}
-
-static struct pca953x_platform_data zeus_pca953x_pdata[] = {
- [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
- [1] = {
- .gpio_base = ZEUS_EXT1_GPIO_BASE,
- .setup = zeus_get_pcb_info,
- },
- [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
-};
-
-static struct i2c_board_info __initdata zeus_i2c_devices[] = {
- {
- I2C_BOARD_INFO("pca9535", 0x21),
- .platform_data = &zeus_pca953x_pdata[0],
- },
- {
- I2C_BOARD_INFO("pca9535", 0x22),
- .platform_data = &zeus_pca953x_pdata[1],
- },
- {
- I2C_BOARD_INFO("pca9535", 0x20),
- .platform_data = &zeus_pca953x_pdata[2],
- .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
- },
- { I2C_BOARD_INFO("lm75a", 0x48) },
- { I2C_BOARD_INFO("24c01", 0x50) },
- { I2C_BOARD_INFO("isl1208", 0x6f) },
-};
-
-static mfp_cfg_t zeus_pin_config[] __initdata = {
- /* AC97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- GPIO15_nCS_1,
- GPIO78_nCS_2,
- GPIO80_nCS_4,
- GPIO33_nCS_5,
-
- GPIO22_GPIO,
- GPIO32_MMC_CLK,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
- GPIO112_MMC_CMD,
-
- GPIO88_USBH1_PWR,
- GPIO89_USBH1_PEN,
- GPIO119_USBH2_PWR,
- GPIO120_USBH2_PEN,
-
- GPIO86_LCD_LDD_16,
- GPIO87_LCD_LDD_17,
-
- GPIO102_GPIO,
- GPIO104_CIF_DD_2,
- GPIO105_CIF_DD_1,
-
- GPIO81_SSP3_TXD,
- GPIO82_SSP3_RXD,
- GPIO83_SSP3_SFRM,
- GPIO84_SSP3_SCLK,
-
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO79_PSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
- GPIO36_GPIO, /* CF CD */
- GPIO97_GPIO, /* CF PWREN */
- GPIO99_GPIO, /* CF RDY */
-};
-
-/*
- * DM9k MSCx settings: SRAM, 16 bits
- * 17 cycles delay first access
- * 5 cycles delay next access
- * 13 cycles recovery time
- * faster device
- */
-#define DM9K_MSC_VALUE 0xe4c9
-
-static void __init zeus_init(void)
-{
- u16 dm9000_msc = DM9K_MSC_VALUE;
- u32 msc0, msc1;
-
- system_rev = __raw_readw(ZEUS_CPLD_VERSION);
- pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
-
- /* Fix timings for dm9000s (CS1/CS2)*/
- msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
- msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
- __raw_writel(msc0, MSC0);
- __raw_writel(msc1, MSC1);
-
- pm_power_off = zeus_power_off;
- zeus_setup_apm();
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
-
- gpiod_add_lookup_table(&can_regulator_gpiod_table);
- gpiod_add_lookup_table(&zeus_ohci_regulator_gpiod_table);
- platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
-
- zeus_register_ohci();
-
- if (zeus_setup_fb_gpios())
- pr_err("Failed to setup fb gpios\n");
- else
- pxa_set_fb_info(NULL, &zeus_fb_info);
-
- gpiod_add_lookup_table(&zeus_mci_gpio_table);
- pxa_set_mci_info(&zeus_mci_platform_data);
- pxa_set_udc_info(&zeus_udc_info);
- pxa_set_ac97_info(&zeus_ac97_info);
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
- pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
- spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
-
- regulator_has_full_constraints();
-}
-
-static struct map_desc zeus_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)ZEUS_CPLD_VERSION,
- .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
- .length = 0x1000,
- .type = MT_DEVICE,
- },
- {
- .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
- .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
- .length = 0x1000,
- .type = MT_DEVICE,
- },
- {
- .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
- .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
- .length = 0x1000,
- .type = MT_DEVICE,
- },
- {
- .virtual = (unsigned long)ZEUS_PC104IO,
- .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
- .length = 0x00800000,
- .type = MT_DEVICE,
- },
-};
-
-static void __init zeus_map_io(void)
-{
- pxa27x_map_io();
-
- iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
-
- /* Clear PSPR to ensure a full restart on wake-up. */
- PMCR = PSPR = 0;
-
- /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
- writel(readl(OSCC) | OSCC_OON, OSCC);
-
- /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
- * float chip selects and PCMCIA */
- PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
-}
-
-MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
- /* Maintainer: Marc Zyngier <maz@misterjones.org> */
- .atag_offset = 0x100,
- .map_io = zeus_map_io,
- .nr_irqs = ZEUS_NR_IRQS,
- .init_irq = zeus_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = zeus_init,
- .restart = pxa_restart,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/zeus.h b/arch/arm/mach-pxa/zeus.h
deleted file mode 100644
index 8fa6b2923f63..000000000000
--- a/arch/arm/mach-pxa/zeus.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/zeus.h
- *
- * Author: David Vrabel
- * Created: Sept 28, 2005
- * Copyright: Arcom Control Systems Ltd.
- *
- * Maintained by: Marc Zyngier <maz@misterjones.org>
- */
-
-#ifndef _MACH_ZEUS_H
-#define _MACH_ZEUS_H
-
-#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48)
-
-/* Physical addresses */
-#define ZEUS_FLASH_PHYS PXA_CS0_PHYS
-#define ZEUS_ETH0_PHYS PXA_CS1_PHYS
-#define ZEUS_ETH1_PHYS PXA_CS2_PHYS
-#define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000)
-#define ZEUS_SRAM_PHYS PXA_CS5_PHYS
-#define ZEUS_PC104IO_PHYS (0x30000000)
-
-#define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000)
-#define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000)
-#define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000)
-#define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000)
-
-/* GPIOs */
-#define ZEUS_AC97_GPIO 0
-#define ZEUS_WAKEUP_GPIO 1
-#define ZEUS_UARTA_GPIO 9
-#define ZEUS_UARTB_GPIO 10
-#define ZEUS_UARTC_GPIO 12
-#define ZEUS_UARTD_GPIO 11
-#define ZEUS_ETH0_GPIO 14
-#define ZEUS_ISA_GPIO 17
-#define ZEUS_BKLEN_GPIO 19
-#define ZEUS_USB2_PWREN_GPIO 22
-#define ZEUS_PTT_GPIO 27
-#define ZEUS_CF_CD_GPIO 35
-#define ZEUS_MMC_WP_GPIO 52
-#define ZEUS_MMC_CD_GPIO 53
-#define ZEUS_EXTGPIO_GPIO 91
-#define ZEUS_CF_PWEN_GPIO 97
-#define ZEUS_CF_RDY_GPIO 99
-#define ZEUS_LCD_EN_GPIO 101
-#define ZEUS_ETH1_GPIO 113
-#define ZEUS_CAN_GPIO 116
-
-#define ZEUS_EXT0_GPIO_BASE 128
-#define ZEUS_EXT1_GPIO_BASE 160
-#define ZEUS_USER_GPIO_BASE 192
-
-#define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x))
-#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x))
-#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x))
-
-#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2)
-
-/*
- * CPLD registers:
- * Only 4 registers, but spread over a 32MB address space.
- * Be gentle, and remap that over 32kB...
- */
-
-#define ZEUS_CPLD IOMEM(0xf0000000)
-#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000)
-#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000)
-#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000)
-
-/* CPLD register bits */
-#define ZEUS_CPLD_CONTROL_CF_RST 0x01
-
-#define ZEUS_PC104IO IOMEM(0xf1000000)
-
-#define ZEUS_SRAM_SIZE (256 * 1024)
-
-#endif
-
-
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
deleted file mode 100644
index 79f0025fa17a..000000000000
--- a/arch/arm/mach-pxa/zylonite.c
+++ /dev/null
@@ -1,463 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/zylonite.c
- *
- * Support for the PXA3xx Development Platform (aka Zylonite)
- *
- * Copyright (C) 2006 Marvell International Ltd.
- *
- * 2007-09-04: eric miao <eric.miao@marvell.com>
- * rewrite to align with latest kernel
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/machine.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/smc91x.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include "pxa3xx.h"
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include "zylonite.h"
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-
-#include "devices.h"
-#include "generic.h"
-
-int gpio_eth_irq;
-int gpio_debug_led1;
-int gpio_debug_led2;
-
-int wm9713_irq;
-
-int lcd_id;
-int lcd_orientation;
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = ZYLONITE_ETH_PHYS + 0x300,
- .end = ZYLONITE_ETH_PHYS + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = -1, /* for run-time assignment */
- .end = -1,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct smc91x_platdata zylonite_smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT |
- SMC91X_NOWAIT | SMC91X_USE_DMA,
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &zylonite_smc91x_info,
- },
-};
-
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-static struct gpio_led zylonite_debug_leds[] = {
- [0] = {
- .name = "zylonite:yellow:1",
- .default_trigger = "heartbeat",
- },
- [1] = {
- .name = "zylonite:yellow:2",
- .default_trigger = "default-on",
- },
-};
-
-static struct gpio_led_platform_data zylonite_debug_leds_info = {
- .leds = zylonite_debug_leds,
- .num_leds = ARRAY_SIZE(zylonite_debug_leds),
-};
-
-static struct platform_device zylonite_device_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &zylonite_debug_leds_info,
- }
-};
-
-static void __init zylonite_init_leds(void)
-{
- zylonite_debug_leds[0].gpio = gpio_debug_led1;
- zylonite_debug_leds[1].gpio = gpio_debug_led2;
-
- platform_device_register(&zylonite_device_leds);
-}
-#else
-static inline void zylonite_init_leds(void) {}
-#endif
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pwm_lookup zylonite_pwm_lookup[] = {
- PWM_LOOKUP("pxa27x-pwm.1", 1, "pwm-backlight.0", NULL, 10000,
- PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data zylonite_backlight_data = {
- .max_brightness = 100,
- .dft_brightness = 100,
-};
-
-static struct platform_device zylonite_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &pxa27x_device_pwm1.dev,
- .platform_data = &zylonite_backlight_data,
- },
-};
-
-static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
- .pixclock = 110000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 4,
- .left_margin = 6,
- .right_margin = 4,
- .vsync_len = 2,
- .upper_margin = 2,
- .lower_margin = 3,
- .sync = FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
- .pixclock = 50000,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .hsync_len = 1,
- .left_margin = 0x9f,
- .right_margin = 1,
- .vsync_len = 44,
- .upper_margin = 0,
- .lower_margin = 0,
- .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
-};
-
-static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static struct pxafb_mode_info sharp_ls037_modes[] = {
- [0] = {
- .pixclock = 158000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .hsync_len = 4,
- .left_margin = 39,
- .right_margin = 39,
- .vsync_len = 1,
- .upper_margin = 2,
- .lower_margin = 3,
- .sync = 0,
- },
- [1] = {
- .pixclock = 39700,
- .xres = 480,
- .yres = 640,
- .bpp = 16,
- .hsync_len = 8,
- .left_margin = 81,
- .right_margin = 81,
- .vsync_len = 1,
- .upper_margin = 2,
- .lower_margin = 7,
- .sync = 0,
- },
-};
-
-static struct pxafb_mach_info zylonite_sharp_lcd_info = {
- .modes = sharp_ls037_modes,
- .num_modes = 2,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-};
-
-static void __init zylonite_init_lcd(void)
-{
- pwm_add_table(zylonite_pwm_lookup, ARRAY_SIZE(zylonite_pwm_lookup));
- platform_device_register(&zylonite_backlight_device);
-
- if (lcd_id & 0x20) {
- pxa_set_fb_info(NULL, &zylonite_sharp_lcd_info);
- return;
- }
-
- /* legacy LCD panels, it would be handy here if LCD panel type can
- * be decided at run-time
- */
- if (1)
- zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode;
- else
- zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode;
-
- pxa_set_fb_info(NULL, &zylonite_toshiba_lcd_info);
-}
-#else
-static inline void zylonite_init_lcd(void) {}
-#endif
-
-#if defined(CONFIG_MMC)
-static struct pxamci_platform_data zylonite_mci_platform_data = {
- .detect_delay_ms= 200,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-#define PCA9539A_MCI_CD 0
-#define PCA9539A_MCI1_CD 1
-#define PCA9539A_MCI_WP 2
-#define PCA9539A_MCI1_WP 3
-#define PCA9539A_MCI3_CD 30
-#define PCA9539A_MCI3_WP 31
-
-static struct gpiod_lookup_table zylonite_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- GPIO_LOOKUP("i2c-pca9539-a", PCA9539A_MCI_CD,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("i2c-pca9539-a", PCA9539A_MCI_WP,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct pxamci_platform_data zylonite_mci2_platform_data = {
- .detect_delay_ms= 200,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table zylonite_mci2_gpio_table = {
- .dev_id = "pxa2xx-mci.1",
- .table = {
- GPIO_LOOKUP("i2c-pca9539-a", PCA9539A_MCI1_CD,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("i2c-pca9539-a", PCA9539A_MCI1_WP,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct pxamci_platform_data zylonite_mci3_platform_data = {
- .detect_delay_ms= 200,
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table zylonite_mci3_gpio_table = {
- .dev_id = "pxa2xx-mci.2",
- .table = {
- GPIO_LOOKUP("i2c-pca9539-a", PCA9539A_MCI3_CD,
- "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("i2c-pca9539-a", PCA9539A_MCI3_WP,
- "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init zylonite_init_mmc(void)
-{
- gpiod_add_lookup_table(&zylonite_mci_gpio_table);
- pxa_set_mci_info(&zylonite_mci_platform_data);
- gpiod_add_lookup_table(&zylonite_mci2_gpio_table);
- pxa3xx_set_mci2_info(&zylonite_mci2_platform_data);
- if (cpu_is_pxa310()) {
- gpiod_add_lookup_table(&zylonite_mci3_gpio_table);
- pxa3xx_set_mci3_info(&zylonite_mci3_platform_data);
- }
-}
-#else
-static inline void zylonite_init_mmc(void) {}
-#endif
-
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int zylonite_matrix_key_map[] = {
- /* KEY(row, col, key_code) */
- KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D),
- KEY(1, 0, KEY_E), KEY(1, 1, KEY_F), KEY(1, 2, KEY_G), KEY(1, 5, KEY_H),
- KEY(2, 0, KEY_I), KEY(2, 1, KEY_J), KEY(2, 2, KEY_K), KEY(2, 5, KEY_L),
- KEY(3, 0, KEY_M), KEY(3, 1, KEY_N), KEY(3, 2, KEY_O), KEY(3, 5, KEY_P),
- KEY(5, 0, KEY_Q), KEY(5, 1, KEY_R), KEY(5, 2, KEY_S), KEY(5, 5, KEY_T),
- KEY(6, 0, KEY_U), KEY(6, 1, KEY_V), KEY(6, 2, KEY_W), KEY(6, 5, KEY_X),
- KEY(7, 1, KEY_Y), KEY(7, 2, KEY_Z),
-
- KEY(4, 4, KEY_0), KEY(1, 3, KEY_1), KEY(4, 1, KEY_2), KEY(1, 4, KEY_3),
- KEY(2, 3, KEY_4), KEY(4, 2, KEY_5), KEY(2, 4, KEY_6), KEY(3, 3, KEY_7),
- KEY(4, 3, KEY_8), KEY(3, 4, KEY_9),
-
- KEY(4, 5, KEY_SPACE),
- KEY(5, 3, KEY_KPASTERISK), /* * */
- KEY(5, 4, KEY_KPDOT), /* #" */
-
- KEY(0, 7, KEY_UP),
- KEY(1, 7, KEY_DOWN),
- KEY(2, 7, KEY_LEFT),
- KEY(3, 7, KEY_RIGHT),
- KEY(2, 6, KEY_HOME),
- KEY(3, 6, KEY_END),
- KEY(6, 4, KEY_DELETE),
- KEY(6, 6, KEY_BACK),
- KEY(6, 3, KEY_CAPSLOCK), /* KEY_LEFTSHIFT), */
-
- KEY(4, 6, KEY_ENTER), /* scroll push */
- KEY(5, 7, KEY_ENTER), /* keypad action */
-
- KEY(0, 4, KEY_EMAIL),
- KEY(5, 6, KEY_SEND),
- KEY(4, 0, KEY_CALENDAR),
- KEY(7, 6, KEY_RECORD),
- KEY(6, 7, KEY_VOLUMEUP),
- KEY(7, 7, KEY_VOLUMEDOWN),
-
- KEY(0, 6, KEY_F22), /* soft1 */
- KEY(1, 6, KEY_F23), /* soft2 */
- KEY(0, 3, KEY_AUX), /* contact */
-};
-
-static struct matrix_keymap_data zylonite_matrix_keymap_data = {
- .keymap = zylonite_matrix_key_map,
- .keymap_size = ARRAY_SIZE(zylonite_matrix_key_map),
-};
-
-static struct pxa27x_keypad_platform_data zylonite_keypad_info = {
- .matrix_key_rows = 8,
- .matrix_key_cols = 8,
- .matrix_keymap_data = &zylonite_matrix_keymap_data,
-
- .enable_rotary0 = 1,
- .rotary0_up_key = KEY_UP,
- .rotary0_down_key = KEY_DOWN,
-
- .debounce_interval = 30,
-};
-
-static void __init zylonite_init_keypad(void)
-{
- pxa_set_keypad_info(&zylonite_keypad_info);
-}
-#else
-static inline void zylonite_init_keypad(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
-static struct mtd_partition zylonite_nand_partitions[] = {
- [0] = {
- .name = "Bootloader",
- .offset = 0,
- .size = 0x060000,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- [1] = {
- .name = "Kernel",
- .offset = 0x060000,
- .size = 0x200000,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- [2] = {
- .name = "Filesystem",
- .offset = 0x0260000,
- .size = 0x3000000, /* 48M - rootfs */
- },
- [3] = {
- .name = "MassStorage",
- .offset = 0x3260000,
- .size = 0x3d40000,
- },
- [4] = {
- .name = "BBT",
- .offset = 0x6FA0000,
- .size = 0x80000,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- /* NOTE: we reserve some blocks at the end of the NAND flash for
- * bad block management, and the max number of relocation blocks
- * differs on different platforms. Please take care with it when
- * defining the partition table.
- */
-};
-
-static struct pxa3xx_nand_platform_data zylonite_nand_info = {
- .parts = zylonite_nand_partitions,
- .nr_parts = ARRAY_SIZE(zylonite_nand_partitions),
-};
-
-static void __init zylonite_init_nand(void)
-{
- pxa3xx_set_nand_info(&zylonite_nand_info);
-}
-#else
-static inline void zylonite_init_nand(void) {}
-#endif /* IS_ENABLED(CONFIG_MTD_NAND_MARVELL) */
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static struct pxaohci_platform_data zylonite_ohci_info = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 | ENABLE_PORT2 |
- POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-static void __init zylonite_init_ohci(void)
-{
- pxa_set_ohci_info(&zylonite_ohci_info);
-}
-#else
-static inline void zylonite_init_ohci(void) {}
-#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
-
-static void __init zylonite_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- /* board-processor specific initialization */
- zylonite_pxa300_init();
- zylonite_pxa320_init();
-
- /*
- * Note: We depend that the bootloader set
- * the correct value to MSC register for SMC91x.
- */
- smc91x_resources[1].start = PXA_GPIO_TO_IRQ(gpio_eth_irq);
- smc91x_resources[1].end = PXA_GPIO_TO_IRQ(gpio_eth_irq);
- platform_device_register(&smc91x_device);
-
- pxa_set_ac97_info(NULL);
- zylonite_init_lcd();
- zylonite_init_mmc();
- zylonite_init_keypad();
- zylonite_init_nand();
- zylonite_init_leds();
- zylonite_init_ohci();
-}
-
-MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
- .atag_offset = 0x100,
- .map_io = pxa3xx_map_io,
- .nr_irqs = ZYLONITE_NR_IRQS,
- .init_irq = pxa3xx_init_irq,
- .handle_irq = pxa3xx_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = zylonite_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite.h b/arch/arm/mach-pxa/zylonite.h
deleted file mode 100644
index 7300ec2aac0d..000000000000
--- a/arch/arm/mach-pxa/zylonite.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_ZYLONITE_H
-#define __ASM_ARCH_ZYLONITE_H
-
-#define ZYLONITE_ETH_PHYS 0x14000000
-
-#define EXT_GPIO(x) (128 + (x))
-
-#define ZYLONITE_NR_IRQS (IRQ_BOARD_START + 32)
-
-/* the following variables are processor specific and initialized
- * by the corresponding zylonite_pxa3xx_init()
- */
-extern int gpio_eth_irq;
-extern int gpio_debug_led1;
-extern int gpio_debug_led2;
-
-extern int wm9713_irq;
-
-extern int lcd_id;
-extern int lcd_orientation;
-
-#ifdef CONFIG_MACH_ZYLONITE300
-extern void zylonite_pxa300_init(void);
-#else
-static inline void zylonite_pxa300_init(void)
-{
- if (cpu_is_pxa300() || cpu_is_pxa310())
- panic("%s: PXA300/PXA310 not supported\n", __func__);
-}
-#endif
-
-#ifdef CONFIG_MACH_ZYLONITE320
-extern void zylonite_pxa320_init(void);
-#else
-static inline void zylonite_pxa320_init(void)
-{
- if (cpu_is_pxa320())
- panic("%s: PXA320 not supported\n", __func__);
-}
-#endif
-
-#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
deleted file mode 100644
index 956fec1c4940..000000000000
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ /dev/null
@@ -1,280 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/zylonite_pxa300.c
- *
- * PXA300/PXA310 specific support code for the
- * PXA3xx Development Platform (aka Zylonite)
- *
- * Copyright (C) 2007 Marvell Internation Ltd.
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- * initial version
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/gpio.h>
-
-#include "pxa300.h"
-#include "devices.h"
-#include "zylonite.h"
-
-#include "generic.h"
-
-/* PXA300/PXA310 common configurations */
-static mfp_cfg_t common_mfp_cfg[] __initdata = {
- /* LCD */
- GPIO54_LCD_LDD_0,
- GPIO55_LCD_LDD_1,
- GPIO56_LCD_LDD_2,
- GPIO57_LCD_LDD_3,
- GPIO58_LCD_LDD_4,
- GPIO59_LCD_LDD_5,
- GPIO60_LCD_LDD_6,
- GPIO61_LCD_LDD_7,
- GPIO62_LCD_LDD_8,
- GPIO63_LCD_LDD_9,
- GPIO64_LCD_LDD_10,
- GPIO65_LCD_LDD_11,
- GPIO66_LCD_LDD_12,
- GPIO67_LCD_LDD_13,
- GPIO68_LCD_LDD_14,
- GPIO69_LCD_LDD_15,
- GPIO70_LCD_LDD_16,
- GPIO71_LCD_LDD_17,
- GPIO72_LCD_FCLK,
- GPIO73_LCD_LCLK,
- GPIO74_LCD_PCLK,
- GPIO75_LCD_BIAS,
- GPIO76_LCD_VSYNC,
- GPIO127_LCD_CS_N,
- GPIO20_PWM3_OUT, /* backlight */
-
- /* BTUART */
- GPIO111_UART2_RTS,
- GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL,
- GPIO113_UART2_TXD,
- GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH,
-
- /* STUART */
- GPIO109_UART3_TXD,
- GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL,
-
- /* AC97 */
- GPIO23_AC97_nACRESET,
- GPIO24_AC97_SYSCLK,
- GPIO29_AC97_BITCLK,
- GPIO25_AC97_SDATA_IN_0,
- GPIO27_AC97_SDATA_OUT,
- GPIO28_AC97_SYNC,
- GPIO17_GPIO, /* SDATA_IN_1 but unused - configure to GPIO */
-
- /* SSP3 */
- GPIO91_SSP3_SCLK,
- GPIO92_SSP3_FRM,
- GPIO93_SSP3_TXD,
- GPIO94_SSP3_RXD,
-
- /* WM9713 IRQ */
- GPIO26_GPIO,
-
- /* Keypad */
- GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
- GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
- GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
- GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
- GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
- GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
- GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
- GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
- GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
- GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
- GPIO121_KP_MKOUT_0,
- GPIO122_KP_MKOUT_1,
- GPIO123_KP_MKOUT_2,
- GPIO124_KP_MKOUT_3,
- GPIO125_KP_MKOUT_4,
- GPIO4_2_KP_MKOUT_5,
- GPIO5_2_KP_MKOUT_6,
- GPIO6_2_KP_MKOUT_7,
-
- /* MMC1 */
- GPIO3_MMC1_DAT0,
- GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
- GPIO5_MMC1_DAT2,
- GPIO6_MMC1_DAT3,
- GPIO7_MMC1_CLK,
- GPIO8_MMC1_CMD, /* CMD0 for slot 0 */
- GPIO15_GPIO, /* CMD1 default as GPIO for slot 0 */
-
- /* MMC2 */
- GPIO9_MMC2_DAT0,
- GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
- GPIO11_MMC2_DAT2,
- GPIO12_MMC2_DAT3,
- GPIO13_MMC2_CLK,
- GPIO14_MMC2_CMD,
-
- /* USB Host */
- GPIO0_2_USBH_PEN,
- GPIO1_2_USBH_PWR,
-
- /* Standard I2C */
- GPIO21_I2C_SCL,
- GPIO22_I2C_SDA,
-
- /* GPIO */
- GPIO18_GPIO | MFP_PULL_HIGH, /* GPIO Expander #0 INT_N */
- GPIO19_GPIO | MFP_PULL_HIGH, /* GPIO Expander #1 INT_N */
-};
-
-static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
- /* FFUART */
- GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL,
- GPIO31_UART1_TXD,
- GPIO32_UART1_CTS,
- GPIO37_UART1_RTS,
- GPIO33_UART1_DCD,
- GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL,
- GPIO35_UART1_RI,
- GPIO36_UART1_DTR,
-
- /* Ethernet */
- GPIO2_nCS3,
- GPIO99_GPIO,
-};
-
-static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
- /* FFUART */
- GPIO99_UART1_RXD | MFP_LPM_EDGE_FALL,
- GPIO100_UART1_TXD,
- GPIO101_UART1_CTS,
- GPIO106_UART1_RTS,
-
- /* Ethernet */
- GPIO2_nCS3,
- GPIO102_GPIO,
-
- /* MMC3 */
- GPIO7_2_MMC3_DAT0,
- GPIO8_2_MMC3_DAT1 | MFP_LPM_EDGE_BOTH,
- GPIO9_2_MMC3_DAT2,
- GPIO10_2_MMC3_DAT3,
- GPIO103_MMC3_CLK,
- GPIO105_MMC3_CMD,
-};
-
-#define NUM_LCD_DETECT_PINS 7
-
-static int lcd_detect_pins[] __initdata = {
- MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */
- MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */
- MFP_PIN_GPIO75, /* LCD_BIAS - LCDID[4] */
- MFP_PIN_GPIO73, /* LCD_LCLK - LCDID[3] */
- MFP_PIN_GPIO72, /* LCD_FCLK - LCDID[2] */
- MFP_PIN_GPIO127,/* LCD_CS_N - LCDID[1] */
- MFP_PIN_GPIO76, /* LCD_VSYNC - LCDID[0] */
-};
-
-static void __init zylonite_detect_lcd_panel(void)
-{
- unsigned long mfpr_save[NUM_LCD_DETECT_PINS];
- int i, gpio, id = 0;
-
- /* save the original MFP settings of these pins and configure
- * them as GPIO Input, DS01X, Pull Neither, Edge Clear
- */
- for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
- mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
- pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440);
- }
-
- for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
- id = id << 1;
- gpio = mfp_to_gpio(lcd_detect_pins[i]);
- gpio_request(gpio, "LCD_ID_PINS");
- gpio_direction_input(gpio);
-
- if (gpio_get_value(gpio))
- id = id | 0x1;
- gpio_free(gpio);
- }
-
- /* lcd id, flush out bit 1 */
- lcd_id = id & 0x3d;
-
- /* lcd orientation, portrait or landscape */
- lcd_orientation = (id >> 6) & 0x1;
-
- /* restore the original MFP settings */
- for (i = 0; i < NUM_LCD_DETECT_PINS; i++)
- pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
-}
-
-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
-static struct pca953x_platform_data gpio_exp[] = {
- [0] = {
- .gpio_base = 128,
- },
- [1] = {
- .gpio_base = 144,
- },
-};
-
-static struct i2c_board_info zylonite_i2c_board_info[] = {
- {
- .type = "pca9539",
- .dev_name = "pca9539-a",
- .addr = 0x74,
- .platform_data = &gpio_exp[0],
- .irq = PXA_GPIO_TO_IRQ(18),
- }, {
- .type = "pca9539",
- .dev_name = "pca9539-b",
- .addr = 0x75,
- .platform_data = &gpio_exp[1],
- .irq = PXA_GPIO_TO_IRQ(19),
- },
-};
-
-static void __init zylonite_init_i2c(void)
-{
- pxa_set_i2c_info(NULL);
- i2c_register_board_info(0, ARRAY_AND_SIZE(zylonite_i2c_board_info));
-}
-#else
-static inline void zylonite_init_i2c(void) {}
-#endif
-
-void __init zylonite_pxa300_init(void)
-{
- if (cpu_is_pxa300() || cpu_is_pxa310()) {
- /* initialize MFP */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg));
-
- /* detect LCD panel */
- zylonite_detect_lcd_panel();
-
- /* WM9713 IRQ */
- wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO26);
-
- zylonite_init_i2c();
- }
-
- if (cpu_is_pxa300()) {
- pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg));
- gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99);
- }
-
- if (cpu_is_pxa310()) {
- pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
- gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
- }
-
- /* GPIOs for Debug LEDs */
- gpio_debug_led1 = EXT_GPIO(25);
- gpio_debug_led2 = EXT_GPIO(26);
-}
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
deleted file mode 100644
index 94cb834f36cd..000000000000
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ /dev/null
@@ -1,212 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/zylonite_pxa320.c
- *
- * PXA320 specific support code for the
- * PXA3xx Development Platform (aka Zylonite)
- *
- * Copyright (C) 2007 Marvell Internation Ltd.
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- * initial version
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-
-#include "pxa320.h"
-#include "zylonite.h"
-
-#include "generic.h"
-
-static mfp_cfg_t mfp_cfg[] __initdata = {
- /* LCD */
- GPIO6_2_LCD_LDD_0,
- GPIO7_2_LCD_LDD_1,
- GPIO8_2_LCD_LDD_2,
- GPIO9_2_LCD_LDD_3,
- GPIO10_2_LCD_LDD_4,
- GPIO11_2_LCD_LDD_5,
- GPIO12_2_LCD_LDD_6,
- GPIO13_2_LCD_LDD_7,
- GPIO63_LCD_LDD_8,
- GPIO64_LCD_LDD_9,
- GPIO65_LCD_LDD_10,
- GPIO66_LCD_LDD_11,
- GPIO67_LCD_LDD_12,
- GPIO68_LCD_LDD_13,
- GPIO69_LCD_LDD_14,
- GPIO70_LCD_LDD_15,
- GPIO71_LCD_LDD_16,
- GPIO72_LCD_LDD_17,
- GPIO73_LCD_CS_N,
- GPIO74_LCD_VSYNC,
- GPIO14_2_LCD_FCLK,
- GPIO15_2_LCD_LCLK,
- GPIO16_2_LCD_PCLK,
- GPIO17_2_LCD_BIAS,
- GPIO14_PWM3_OUT, /* backlight */
-
- /* FFUART */
- GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
- GPIO42_UART1_TXD,
- GPIO43_UART1_CTS,
- GPIO44_UART1_DCD,
- GPIO45_UART1_DSR | MFP_LPM_EDGE_FALL,
- GPIO46_UART1_RI,
- GPIO47_UART1_DTR,
- GPIO48_UART1_RTS,
-
- /* AC97 */
- GPIO34_AC97_SYSCLK,
- GPIO35_AC97_SDATA_IN_0,
- GPIO37_AC97_SDATA_OUT,
- GPIO38_AC97_SYNC,
- GPIO39_AC97_BITCLK,
- GPIO40_AC97_nACRESET,
- GPIO36_GPIO, /* SDATA_IN_1 but unused - configure to GPIO */
-
- /* SSP3 */
- GPIO89_SSP3_SCLK,
- GPIO90_SSP3_FRM,
- GPIO91_SSP3_TXD,
- GPIO92_SSP3_RXD,
-
- /* WM9713 IRQ */
- GPIO15_GPIO,
-
- /* I2C */
- GPIO32_I2C_SCL,
- GPIO33_I2C_SDA,
-
- /* Keypad */
- GPIO105_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
- GPIO106_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
- GPIO113_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
- GPIO114_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
- GPIO115_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
- GPIO116_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
- GPIO117_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
- GPIO118_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
- GPIO119_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
- GPIO120_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
- GPIO121_KP_MKOUT_0,
- GPIO122_KP_MKOUT_1,
- GPIO123_KP_MKOUT_2,
- GPIO124_KP_MKOUT_3,
- GPIO125_KP_MKOUT_4,
- GPIO126_KP_MKOUT_5,
- GPIO127_KP_MKOUT_6,
- GPIO5_2_KP_MKOUT_7,
-
- /* Ethernet */
- GPIO4_nCS3,
- GPIO90_GPIO,
-
- /* MMC1 */
- GPIO18_MMC1_DAT0,
- GPIO19_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
- GPIO20_MMC1_DAT2,
- GPIO21_MMC1_DAT3,
- GPIO22_MMC1_CLK,
- GPIO23_MMC1_CMD,/* CMD0 for slot 0 */
- GPIO31_GPIO, /* CMD1 default as GPIO for slot 0 */
-
- /* MMC2 */
- GPIO24_MMC2_DAT0,
- GPIO25_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
- GPIO26_MMC2_DAT2,
- GPIO27_MMC2_DAT3,
- GPIO28_MMC2_CLK,
- GPIO29_MMC2_CMD,
-
- /* USB Host */
- GPIO2_2_USBH_PEN,
- GPIO3_2_USBH_PWR,
-
- /* Debug LEDs */
- GPIO1_2_GPIO | MFP_LPM_DRIVE_HIGH,
- GPIO4_2_GPIO | MFP_LPM_DRIVE_HIGH,
-};
-
-#define NUM_LCD_DETECT_PINS 7
-
-static int lcd_detect_pins[] __initdata = {
- MFP_PIN_GPIO72, /* LCD_LDD_17 - ORIENT */
- MFP_PIN_GPIO71, /* LCD_LDD_16 - LCDID[5] */
- MFP_PIN_GPIO17_2, /* LCD_BIAS - LCDID[4] */
- MFP_PIN_GPIO15_2, /* LCD_LCLK - LCDID[3] */
- MFP_PIN_GPIO14_2, /* LCD_FCLK - LCDID[2] */
- MFP_PIN_GPIO73, /* LCD_CS_N - LCDID[1] */
- MFP_PIN_GPIO74, /* LCD_VSYNC - LCDID[0] */
- /*
- * set the MFP_PIN_GPIO 14/15/17 to alternate function other than
- * GPIO to avoid input level confliction with 14_2, 15_2, 17_2
- */
- MFP_PIN_GPIO14,
- MFP_PIN_GPIO15,
- MFP_PIN_GPIO17,
-};
-
-static int lcd_detect_mfpr[] __initdata = {
- /* AF0, DS 1X, Pull Neither, Edge Clear */
- 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440,
- 0xc442, /* Backlight, Pull-Up, AF2 */
- 0x8445, /* AF5 */
- 0x8445, /* AF5 */
-};
-
-static void __init zylonite_detect_lcd_panel(void)
-{
- unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)];
- int i, gpio, id = 0;
-
- /* save the original MFP settings of these pins and configure them
- * as GPIO Input, DS01X, Pull Neither, Edge Clear
- */
- for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) {
- mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
- pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]);
- }
-
- for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
- id = id << 1;
- gpio = mfp_to_gpio(lcd_detect_pins[i]);
- gpio_request(gpio, "LCD_ID_PINS");
- gpio_direction_input(gpio);
-
- if (gpio_get_value(gpio))
- id = id | 0x1;
- gpio_free(gpio);
- }
-
- /* lcd id, flush out bit 1 */
- lcd_id = id & 0x3d;
-
- /* lcd orientation, portrait or landscape */
- lcd_orientation = (id >> 6) & 0x1;
-
- /* restore the original MFP settings */
- for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++)
- pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
-}
-
-void __init zylonite_pxa320_init(void)
-{
- if (cpu_is_pxa320()) {
- /* initialize MFP */
- pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg));
-
- /* detect LCD panel */
- zylonite_detect_lcd_panel();
-
- /* GPIO pin assignment */
- gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
- gpio_debug_led1 = mfp_to_gpio(MFP_PIN_GPIO1_2);
- gpio_debug_led2 = mfp_to_gpio(MFP_PIN_GPIO4_2);
-
- /* WM9713 IRQ */
- wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO15);
- }
-}
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index 466acc4a5e0c..12a812e61c16 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -2,7 +2,6 @@
menuconfig ARCH_QCOM
bool "Qualcomm Support"
depends on ARCH_MULTI_V7
- select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_GIC
select ARM_AMBA
select PINCTRL
@@ -21,6 +20,10 @@ config ARCH_MSM8X60
bool "Enable support for MSM8X60"
select CLKSRC_QCOM
+config ARCH_MSM8909
+ bool "Enable support for MSM8909"
+ select HAVE_ARM_ARCH_TIMER
+
config ARCH_MSM8916
bool "Enable support for MSM8916"
select HAVE_ARM_ARCH_TIMER
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 65a0d5ce2bb3..eca2fe0f4314 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -14,7 +14,7 @@
#include <linux/of_address.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/qcom_scm.h>
+#include <linux/firmware/qcom/qcom_scm.h>
#include <asm/smp_plat.h>
@@ -384,6 +384,7 @@ static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = {
#endif
};
CPU_METHOD_OF_DECLARE(qcom_smp_msm8226, "qcom,msm8226-smp", &qcom_smp_cortex_a7_ops);
+CPU_METHOD_OF_DECLARE(qcom_smp_msm8909, "qcom,msm8909-smp", &qcom_smp_cortex_a7_ops);
CPU_METHOD_OF_DECLARE(qcom_smp_msm8916, "qcom,msm8916-smp", &qcom_smp_cortex_a7_ops);
static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
deleted file mode 100644
index a4c36024b5e8..000000000000
--- a/arch/arm/mach-realview/Kconfig
+++ /dev/null
@@ -1,103 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-menuconfig ARCH_REALVIEW
- bool "ARM Ltd. RealView family"
- depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7
- select ARM_AMBA
- select ARM_GIC
- select ARM_TIMER_SP804
- select CLK_SP810
- select GPIO_PL061 if GPIOLIB
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
- select HAVE_PATA_PLATFORM
- select HAVE_TCM
- select CLK_ICST
- select MACH_REALVIEW_EB if ARCH_MULTI_V5
- select MFD_SYSCON
- select PLAT_VERSATILE
- select POWER_RESET
- select POWER_RESET_VERSATILE
- select POWER_SUPPLY
- select SOC_REALVIEW
- help
- This enables support for ARM Ltd RealView boards.
-
-if ARCH_REALVIEW
-
-config MACH_REALVIEW_EB
- bool "Support RealView(R) Emulation Baseboard"
- select ARM_GIC
- select CPU_ARM926T if ARCH_MULTI_V5
- help
- Include support for the ARM(R) RealView(R) Emulation Baseboard
- platform. On an ARMv5 kernel, this will include support for
- the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
- one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore
- core tile options should be enabled.
-
-config REALVIEW_EB_ARM1136
- bool "Support ARM1136J(F)-S Tile"
- depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
- select CPU_V6
- help
- Enable support for the ARM1136 tile fitted to the
- Realview(R) Emulation Baseboard platform.
-
-config REALVIEW_EB_ARM1176
- bool "Support ARM1176JZ(F)-S Tile"
- depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
- help
- Enable support for the ARM1176 tile fitted to the
- Realview(R) Emulation Baseboard platform.
-
-config REALVIEW_EB_A9MP
- bool "Support Multicore Cortex-A9 Tile"
- depends on MACH_REALVIEW_EB && ARCH_MULTI_V7
- help
- Enable support for the Cortex-A9MPCore tile fitted to the
- Realview(R) Emulation Baseboard platform.
-
-config REALVIEW_EB_ARM11MP
- bool "Support ARM11MPCore Tile"
- depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
- select HAVE_SMP
- help
- Enable support for the ARM11MPCore tile fitted to the Realview(R)
- Emulation Baseboard platform.
-
-config MACH_REALVIEW_PB11MP
- bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
- depends on ARCH_MULTI_V6
- select HAVE_SMP
- help
- Include support for the ARM(R) RealView(R) Platform Baseboard for
- the ARM11MPCore. This platform has an on-board ARM11MPCore and has
- support for PCI-E and Compact Flash.
-
-# ARMv6 CPU without K extensions, but does have the new exclusive ops
-config MACH_REALVIEW_PB1176
- bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
- depends on ARCH_MULTI_V6
- select CPU_V6
- select HAVE_TCM
- help
- Include support for the ARM(R) RealView(R) Platform Baseboard for
- ARM1176JZF-S.
-
-config MACH_REALVIEW_PBA8
- bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
- depends on ARCH_MULTI_V7
- help
- Include support for the ARM(R) RealView Platform Baseboard for
- Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has
- support for PCI-E and Compact Flash.
-
-config MACH_REALVIEW_PBX
- bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9"
- depends on ARCH_MULTI_V7
- select ZONE_DMA
- help
- Include support for the ARM(R) RealView(R) Platform Baseboard
- Explore.
-
-endif
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
deleted file mode 100644
index e259091591b8..000000000000
--- a/arch/arm/mach-realview/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Makefile for the linux kernel.
-#
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-versatile/include
-
-obj-y += realview-dt.o
-obj-$(CONFIG_SMP) += platsmp-dt.o
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 5ec58d004b7d..36915a073c23 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -137,7 +137,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
/*
* We communicate with the bootrom to active the cpus other
* than cpu0, after a blob of initialize code, they will
- * stay at wfe state, once they are actived, they will check
+ * stay at wfe state, once they are activated, they will check
* the mailbox:
* sram_base_addr + 4: 0xdeadbeaf
* sram_base_addr + 8: start address for pc
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 87389d9456b9..30d781d80fe0 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -311,7 +311,7 @@ void __init rockchip_suspend_init(void)
&match);
if (!match) {
pr_err("Failed to find PMU node\n");
- return;
+ goto out_put;
}
pm_data = (struct rockchip_pm_data *) match->data;
@@ -320,9 +320,12 @@ void __init rockchip_suspend_init(void)
if (ret) {
pr_err("%s: matches init error %d\n", __func__, ret);
- return;
+ goto out_put;
}
}
suspend_set_ops(pm_data->ops);
+
+out_put:
+ of_node_put(np);
}
diff --git a/arch/arm/mach-rpc/Kconfig b/arch/arm/mach-rpc/Kconfig
new file mode 100644
index 000000000000..55f6d829b677
--- /dev/null
+++ b/arch/arm/mach-rpc/Kconfig
@@ -0,0 +1,21 @@
+config ARCH_RPC
+ bool "RiscPC"
+ depends on ARCH_MULTI_V4 && !(ARCH_MULTI_V4T || ARCH_MULTI_V5)
+ depends on !(ARCH_FOOTBRIDGE || ARCH_SA1100 || ARCH_MOXART || ARCH_GEMINI)
+ depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
+ depends on CPU_LITTLE_ENDIAN
+ depends on ATAGS
+ depends on MMU
+ select ARCH_ACORN
+ select ARCH_MAY_HAVE_PC_FDC
+ select CPU_SA110
+ select FIQ
+ select HAVE_PATA_PLATFORM
+ select ISA_DMA_API
+ select LEGACY_TIMER_TICK
+ select NEED_MACH_IO_H
+ select NEED_MACH_MEMORY_H
+ select NO_IOPORT_MAP
+ help
+ On the Acorn Risc-PC, Linux can support the internal IDE disk and
+ CD-ROM interface, serial and parallel port, and the floppy drive.
diff --git a/arch/arm/mach-rpc/Makefile.boot b/arch/arm/mach-rpc/Makefile.boot
deleted file mode 100644
index 0ed8e8fbde99..000000000000
--- a/arch/arm/mach-rpc/Makefile.boot
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
- zreladdr-y += 0x10008000
-params_phys-y := 0x10000100
-initrd_phys-y := 0x18000000
-
diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
index 53813f9464a2..c30df1097c52 100644
--- a/arch/arm/mach-rpc/ecard.c
+++ b/arch/arm/mach-rpc/ecard.c
@@ -253,7 +253,7 @@ static int ecard_init_mm(void)
current->mm = mm;
current->active_mm = mm;
activate_mm(active_mm, mm);
- mmdrop(active_mm);
+ mmdrop_lazy_tlb(active_mm);
ecard_init_pgtables(mm);
return 0;
}
diff --git a/arch/arm/mach-s3c/Kconfig b/arch/arm/mach-s3c/Kconfig
index 1899fc3f44fd..b3656109f1f7 100644
--- a/arch/arm/mach-s3c/Kconfig
+++ b/arch/arm/mach-s3c/Kconfig
@@ -2,13 +2,10 @@
#
# Copyright 2009 Simtec Electronics
-source "arch/arm/mach-s3c/Kconfig.s3c24xx"
source "arch/arm/mach-s3c/Kconfig.s3c64xx"
config PLAT_SAMSUNG
- bool
- depends on PLAT_S3C24XX || ARCH_S3C64XX
- default y
+ def_bool ARCH_S3C64XX
select GENERIC_IRQ_CHIP
select NO_IOPORT_MAP
select SOC_SAMSUNG
@@ -16,9 +13,8 @@ config PLAT_SAMSUNG
Base platform code for all Samsung SoC based systems
config SAMSUNG_PM
- bool
- depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX)
- default y
+ def_bool ARCH_S3C64XX
+ depends on PM
help
Base platform power management code for samsung code
@@ -43,12 +39,12 @@ config SAMSUNG_ATAGS
def_bool n
depends on ATAGS
help
- This option enables ATAGS based boot support code for
- Samsung platforms, including static platform devices, legacy
- clock, timer and interrupt initialization, etc.
+ This option enables ATAGS based boot support code for
+ Samsung platforms, including static platform devices, legacy
+ clock, timer and interrupt initialization, etc.
- Platforms that support only DT based boot need not to select
- this option.
+ Platforms that support only DT based boot need not to select
+ this option.
if SAMSUNG_ATAGS
@@ -67,16 +63,6 @@ config S3C_GPIO_TRACK
Internal configuration option to enable the s3c specific gpio
chip tracking if the platform requires it.
-# ADC driver
-
-config S3C_ADC
- bool "ADC common driver support"
- depends on !ARCH_MULTIPLATFORM
- help
- Core support for the ADC block found in the Samsung SoC systems
- for drivers such as the touchscreen and hwmon to use to share
- this resource.
-
# device definitions to compile in
config S3C_DEV_HSMMC
@@ -99,46 +85,11 @@ config S3C_DEV_HSMMC3
help
Compile in platform device definitions for HSMMC channel 3
-config S3C_DEV_HWMON
- bool
- help
- Compile in platform device definitions for HWMON
-
config S3C_DEV_I2C1
bool
help
Compile in platform device definitions for I2C channel 1
-config S3C_DEV_I2C2
- bool
- help
- Compile in platform device definitions for I2C channel 2
-
-config S3C_DEV_I2C3
- bool
- help
- Compile in platform device definition for I2C controller 3
-
-config S3C_DEV_I2C4
- bool
- help
- Compile in platform device definition for I2C controller 4
-
-config S3C_DEV_I2C5
- bool
- help
- Compile in platform device definition for I2C controller 5
-
-config S3C_DEV_I2C6
- bool
- help
- Compile in platform device definition for I2C controller 6
-
-config S3C_DEV_I2C7
- bool
- help
- Compile in platform device definition for I2C controller 7
-
config S3C_DEV_FB
bool
help
@@ -154,48 +105,12 @@ config S3C_DEV_USB_HSOTG
help
Compile in platform device definition for USB high-speed OtG
-config S3C_DEV_WDT
- bool
- default y if ARCH_S3C24XX
- help
- Compile in platform device definition for Watchdog Timer
-
-config S3C_DEV_NAND
- bool
- help
- Compile in platform device definition for NAND controller
-
-config S3C_DEV_ONENAND
- bool
- help
- Compile in platform device definition for OneNAND controller
-
-config S3C_DEV_RTC
- bool
- help
- Compile in platform device definition for RTC
-
-config SAMSUNG_DEV_ADC
- bool
- help
- Compile in platform device definition for ADC controller
-
-config SAMSUNG_DEV_IDE
- bool
- help
- Compile in platform device definitions for IDE
-
config S3C64XX_DEV_SPI0
bool
help
Compile in platform device definitions for S3C64XX's type
SPI controller 0
-config SAMSUNG_DEV_TS
- bool
- help
- Common in platform device definitions for touchscreen device
-
config SAMSUNG_DEV_KEYPAD
bool
help
@@ -203,18 +118,9 @@ config SAMSUNG_DEV_KEYPAD
config SAMSUNG_DEV_PWM
bool
- default y if ARCH_S3C24XX
help
Compile in platform device definition for PWM Timer
-config S3C24XX_PWM
- bool "PWM device support"
- select PWM
- select PWM_SAMSUNG
- help
- Support for exporting the PWM timer blocks via the pwm device
- system
-
config GPIO_SAMSUNG
def_bool y
diff --git a/arch/arm/mach-s3c/Kconfig.s3c24xx b/arch/arm/mach-s3c/Kconfig.s3c24xx
deleted file mode 100644
index 000e3e234f71..000000000000
--- a/arch/arm/mach-s3c/Kconfig.s3c24xx
+++ /dev/null
@@ -1,583 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (c) 2012 Samsung Electronics Co., Ltd.
-# http://www.samsung.com/
-#
-# Copyright 2007 Simtec Electronics
-
-if ARCH_S3C24XX
-
-config PLAT_S3C24XX
- def_bool y
- select GPIOLIB
- select NO_IOPORT_MAP
- select S3C_DEV_NAND
- select IRQ_DOMAIN
- select COMMON_CLK
- help
- Base platform code for any Samsung S3C24XX device
-
-
-
-menu "Samsung S3C24XX SoCs Support"
-
-comment "S3C24XX SoCs"
-
-config CPU_S3C2410
- bool "Samsung S3C2410"
- default y
- select CPU_ARM920T
- select S3C2410_COMMON_CLK
- select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
- select S3C2410_PM if PM
- help
- Support for S3C2410 and S3C2410A family from the S3C24XX line
- of Samsung Mobile CPUs.
-
-config CPU_S3C2412
- bool "Samsung S3C2412"
- select CPU_ARM926T
- select S3C2412_COMMON_CLK
- select S3C2412_PM if PM_SLEEP
- help
- Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
-
-config CPU_S3C2416
- bool "Samsung S3C2416/S3C2450"
- select CPU_ARM926T
- select S3C2416_PM if PM_SLEEP
- select S3C2443_COMMON_CLK
- help
- Support for the S3C2416 SoC from the S3C24XX line
-
-config CPU_S3C2440
- bool "Samsung S3C2440"
- select CPU_ARM920T
- select S3C2410_COMMON_CLK
- select S3C2410_PM if PM_SLEEP
- help
- Support for S3C2440 Samsung Mobile CPU based systems.
-
-config CPU_S3C2442
- bool "Samsung S3C2442"
- select CPU_ARM920T
- select S3C2410_COMMON_CLK
- select S3C2410_PM if PM_SLEEP
- help
- Support for S3C2442 Samsung Mobile CPU based systems.
-
-config CPU_S3C244X
- def_bool y
- depends on CPU_S3C2440 || CPU_S3C2442
-
-config CPU_S3C2443
- bool "Samsung S3C2443"
- select CPU_ARM920T
- select S3C2443_COMMON_CLK
- help
- Support for the S3C2443 SoC from the S3C24XX line
-
-# common code
-
-config S3C24XX_SMDK
- bool
- help
- Common machine code for SMDK2410 and SMDK2440
-
-config S3C24XX_SIMTEC_AUDIO
- bool
- depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
- default y
- help
- Add audio devices for common Simtec S3C24XX boards
-
-config S3C24XX_SIMTEC_PM
- bool
- help
- Common power management code for systems that are
- compatible with the Simtec style of power management
-
-config S3C24XX_SIMTEC_USB
- bool
- help
- USB management code for common Simtec S3C24XX boards
-
-config S3C24XX_SETUP_TS
- bool
- help
- Compile in platform device definition for Samsung TouchScreen.
-
-config S3C2410_PM
- bool
- help
- Power Management code common to S3C2410 and better
-
-config S3C24XX_PLL
- bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
- depends on ARM_S3C24XX_CPUFREQ
- help
- Compile in support for changing the PLL frequency from the
- S3C24XX series CPUfreq driver. The PLL takes time to settle
- after a frequency change, so by default it is not enabled.
-
- This also means that the PLL tables for the selected CPU(s) will
- be built which may increase the size of the kernel image.
-
-# cpu frequency items common between s3c2410 and s3c2440/s3c2442
-
-config S3C2410_IOTIMING
- bool
- depends on ARM_S3C24XX_CPUFREQ
- help
- Internal node to select io timing code that is common to the s3c2410
- and s3c2440/s3c2442 cpu frequency support.
-
-# cpu frequency support common to s3c2412, s3c2413 and s3c2442
-
-config S3C2412_IOTIMING
- bool
- depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443)
- help
- Intel node to select io timing code that is common to the s3c2412
- and the s3c2443.
-
-# cpu-specific sections
-
-if CPU_S3C2410
-
-config S3C2410_PLL
- bool
- depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL
- default y
- help
- Select the PLL table for the S3C2410
-
-config S3C24XX_SIMTEC_NOR
- bool
- help
- Internal node to specify machine has simtec NOR mapping
-
-config MACH_BAST_IDE
- bool
- select HAVE_PATA_PLATFORM
- help
- Internal node for machines with an BAST style IDE
- interface
-
-comment "S3C2410 Boards"
-
-#
-# The "S3C2410 Boards" list is ordered alphabetically by option text.
-# (without ARCH_ or MACH_)
-#
-
-config MACH_AML_M5900
- bool "AML M5900 Series"
- select S3C24XX_SIMTEC_PM if PM
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the American Microsystems M5900 Series
- <http://www.amltd.com>
-
-config ARCH_BAST
- bool "Simtec Electronics BAST (EB2410ITX)"
- select ISA
- select MACH_BAST_IDE
- select S3C2410_COMMON_DCLK
- select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
- select S3C24XX_SIMTEC_NOR
- select S3C24XX_SIMTEC_PM if PM
- select S3C24XX_SIMTEC_USB
- select S3C_DEV_HWMON
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Simtec Electronics EB2410ITX
- development board (also known as BAST)
-
-config BAST_PC104_IRQ
- bool "BAST PC104 IRQ support"
- depends on ARCH_BAST
- default y
- help
- Say Y here to enable the PC104 IRQ routing on the
- Simtec BAST (EB2410ITX)
-
-config ARCH_H1940
- bool "IPAQ H1940"
- select PM_H1940 if PM
- select S3C24XX_SETUP_TS
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the HP IPAQ H1940
-
-config H1940BT
- tristate "Control the state of H1940 bluetooth chip"
- depends on ARCH_H1940
- depends on RFKILL
- help
- This is a simple driver that is able to control
- the state of built in bluetooth chip on h1940.
-
-config MACH_N30
- bool "Acer N30 family"
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you want suppt for the Acer N30, Acer N35,
- Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
-
-config MACH_OTOM
- bool "NexVision OTOM Board"
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Nex Vision OTOM board
-
-config MACH_QT2410
- bool "QT2410"
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Armzone QT2410
-
-config ARCH_SMDK2410
- bool "SMDK2410/A9M2410"
- select S3C24XX_SMDK
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the SMDK2410 or the derived module A9M2410
- <http://www.fsforth.de>
-
-config MACH_TCT_HAMMER
- bool "TCT Hammer Board"
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the TinCanTools Hammer Board
- <https://www.tincantools.com>
-
-config MACH_VR1000
- bool "Thorcom VR1000"
- select MACH_BAST_IDE
- select S3C2410_COMMON_DCLK
- select S3C24XX_SIMTEC_NOR
- select S3C24XX_SIMTEC_PM if PM
- select S3C24XX_SIMTEC_USB
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Thorcom VR1000 board.
-
-endif # CPU_S3C2410
-
-config S3C2412_PM_SLEEP
- bool
- help
- Internal config node to apply sleep for S3C2412 power management.
- Can be selected by another SoCs such as S3C2416 with similar
- sleep procedure.
-
-if CPU_S3C2412
-
-config CPU_S3C2412_ONLY
- bool
- depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
- !CPU_S3C2442 && !CPU_S3C2443
- default y
-
-config S3C2412_PM
- bool
- select S3C2412_PM_SLEEP
- select SAMSUNG_WAKEMASK
- help
- Internal config node to apply S3C2412 power management
-
-comment "S3C2412 Boards"
-
-#
-# The "S3C2412 Boards" list is ordered alphabetically by option text.
-# (without ARCH_ or MACH_)
-#
-
-config MACH_JIVE
- bool "Logitech Jive"
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Logitech Jive.
-
-config MACH_JIVE_SHOW_BOOTLOADER
- bool "Allow access to bootloader partitions in MTD"
- depends on MACH_JIVE
-
-config MACH_S3C2413
- bool
- help
- Internal node for S3C2413 version of SMDK2413, so that
- machine_is_s3c2413() will work when MACH_SMDK2413 is
- selected
-
-config MACH_SMDK2412
- bool "SMDK2412"
- select MACH_SMDK2413
- help
- Say Y here if you are using an SMDK2412
-
- Note, this shares support with SMDK2413, so will automatically
- select MACH_SMDK2413.
-
-config MACH_SMDK2413
- bool "SMDK2413"
- select MACH_S3C2413
- select S3C24XX_SMDK
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using an SMDK2413
-
-config MACH_VSTMS
- bool "VMSTMS"
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using an VSTMS board
-
-endif # CPU_S3C2412
-
-if CPU_S3C2416
-
-config S3C2416_PM
- bool
- select S3C2412_PM_SLEEP
- select SAMSUNG_WAKEMASK
- help
- Internal config node to apply S3C2416 power management
-
-config S3C2416_SETUP_SDHCI
- bool
- select S3C2416_SETUP_SDHCI_GPIO
- help
- Internal helper functions for S3C2416 based SDHCI systems
-
-config S3C2416_SETUP_SDHCI_GPIO
- bool
- help
- Common setup code for SDHCI gpio.
-
-comment "S3C2416 Boards"
-
-config MACH_SMDK2416
- bool "SMDK2416"
- select S3C2416_SETUP_SDHCI
- select S3C24XX_SMDK
- select S3C_DEV_FB
- select S3C_DEV_HSMMC
- select S3C_DEV_HSMMC1
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using an SMDK2416
-
-config MACH_S3C2416_DT
- bool "Samsung S3C2416 machine using devicetree"
- select TIMER_OF
- select USE_OF
- select PINCTRL
- select PINCTRL_S3C24XX
- help
- Machine support for Samsung S3C2416 machines with device tree enabled.
- Select this if a fdt blob is available for the S3C2416 SoC based board.
- Note: This is under development and not all peripherals can be supported
- with this machine file.
-
-endif # CPU_S3C2416
-
-if CPU_S3C2440 || CPU_S3C2442
-
-config S3C2440_XTAL_12000000
- bool
- help
- Indicate that the build needs to support 12MHz system
- crystal.
-
-config S3C2440_XTAL_16934400
- bool
- help
- Indicate that the build needs to support 16.9344MHz system
- crystal.
-
-config S3C2440_PLL_12000000
- bool
- depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000
- default y if S3C24XX_PLL
- help
- PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
-
-config S3C2440_PLL_16934400
- bool
- depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400
- default y if S3C24XX_PLL
- help
- PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
-endif
-
-if CPU_S3C2440
-
-comment "S3C2440 Boards"
-
-#
-# The "S3C2440 Boards" list is ordered alphabetically by option text.
-# (without ARCH_ or MACH_)
-#
-
-config MACH_ANUBIS
- bool "Simtec Electronics ANUBIS"
- select HAVE_PATA_PLATFORM
- select S3C2410_COMMON_DCLK
- select S3C2440_XTAL_12000000
- select S3C24XX_SIMTEC_PM if PM
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Simtec Electronics ANUBIS
- development system
-
-config MACH_AT2440EVB
- bool "Avantech AT2440EVB development board"
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the AT2440EVB development board
-
-config MACH_MINI2440
- bool "MINI2440 development board"
- select LEDS_CLASS
- select LEDS_TRIGGERS
- select LEDS_TRIGGER_BACKLIGHT
- select NEW_LEDS
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
- available via various sources. It can come with a 3.5" or 7" touch LCD.
-
-config MACH_NEXCODER_2440
- bool "NexVision NEXCODER 2440 Light Board"
- select S3C2440_XTAL_12000000
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
-
-config MACH_OSIRIS
- bool "Simtec IM2440D20 (OSIRIS) module"
- select S3C2410_COMMON_DCLK
- select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
- select S3C2440_XTAL_12000000
- select S3C24XX_SIMTEC_PM if PM
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Simtec IM2440D20 module, also
- known as the Osiris.
-
-config MACH_OSIRIS_DVS
- tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
- depends on MACH_OSIRIS
- depends on TPS65010
- help
- Say Y/M here if you want to have dynamic voltage scaling support
- on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
-
- The DVS driver alters the voltage supplied to the ARM core
- depending on the frequency it is running at. The driver itself
- does not do any of the frequency alteration, which is left up
- to the cpufreq driver.
-
-config MACH_RX3715
- bool "HP iPAQ rx3715"
- select PM_H1940 if PM
- select S3C2440_XTAL_16934400
- select S3C_DEV_NAND
- help
- Say Y here if you are using the HP iPAQ rx3715.
-
-config ARCH_S3C2440
- bool "SMDK2440"
- select S3C2440_XTAL_16934400
- select S3C24XX_SMDK
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the SMDK2440.
-
-config SMDK2440_CPU2440
- bool "SMDK2440 with S3C2440 CPU module"
- default y if ARCH_S3C2440
- select S3C2440_XTAL_16934400
-
-endif # CPU_S3C2440
-
-if CPU_S3C2442
-
-comment "S3C2442 Boards"
-
-#
-# The "S3C2442 Boards" list is ordered alphabetically by option text.
-# (without ARCH_ or MACH_)
-#
-
-config MACH_NEO1973_GTA02
- bool "Openmoko GTA02 / Freerunner phone"
- select I2C
- select MFD_PCF50633
- select PCF50633_GPIO
- select POWER_SUPPLY
- select S3C24XX_PWM
- select S3C_DEV_USB_HOST
- help
- Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
-
-config MACH_RX1950
- bool "HP iPAQ rx1950"
- select I2C
- select PM_H1940 if PM
- select S3C2410_COMMON_DCLK
- select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
- select S3C2440_XTAL_16934400
- select S3C24XX_PWM
- select S3C_DEV_NAND
- help
- Say Y here if you're using HP iPAQ rx1950
-
-endif # CPU_S3C2442
-
-if CPU_S3C2443 || CPU_S3C2416
-
-config S3C2443_SETUP_SPI
- bool
- help
- Common setup code for SPI GPIO configurations
-
-endif # CPU_S3C2443 || CPU_S3C2416
-
-if CPU_S3C2443
-
-comment "S3C2443 Boards"
-
-config MACH_SMDK2443
- bool "SMDK2443"
- select S3C24XX_SMDK
- select S3C_DEV_HSMMC1
- help
- Say Y here if you are using an SMDK2443
-
-endif # CPU_S3C2443
-
-config PM_H1940
- bool
- help
- Internal node for H1940 and related PM
-
-endmenu # Samsung S3C24XX SoCs Support
-
-endif # ARCH_S3C24XX
diff --git a/arch/arm/mach-s3c/Kconfig.s3c64xx b/arch/arm/mach-s3c/Kconfig.s3c64xx
index af01675d8769..01a7a8eec6e8 100644
--- a/arch/arm/mach-s3c/Kconfig.s3c64xx
+++ b/arch/arm/mach-s3c/Kconfig.s3c64xx
@@ -4,7 +4,7 @@
# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
menuconfig ARCH_S3C64XX
- bool "Samsung S3C64XX"
+ bool "Samsung S3C64XX (deprecated, see help)"
depends on ARCH_MULTI_V6
select ARM_AMBA
select ARM_VIC
@@ -15,7 +15,6 @@ menuconfig ARCH_S3C64XX
select HAVE_TCM
select PLAT_SAMSUNG
select PM_GENERIC_DOMAINS if PM
- select S3C_DEV_NAND if ATAGS
select S3C_GPIO_TRACK if ATAGS
select S3C2410_WATCHDOG
select SAMSUNG_ATAGS if ATAGS
@@ -24,6 +23,11 @@ menuconfig ARCH_S3C64XX
help
Samsung S3C64XX series based systems
+ The platform is deprecated and scheduled for removal. Please reach to
+ the maintainers of the platform and linux-samsung-soc@vger.kernel.org if
+ you still use it.
+ Without such feedback, the platform will be removed after 2024.
+
if ARCH_S3C64XX
# Configuration options for the S3C6410 CPU
@@ -49,17 +53,6 @@ config S3C64XX_SETUP_SDHCI
Internal configuration for default SDHCI setup for S3C6400 and
S3C6410 SoCs.
-config S3C64XX_DEV_ONENAND1
- bool
- help
- Compile in platform device definition for OneNAND1 controller
-
-config SAMSUNG_DEV_BACKLIGHT
- bool
- depends on SAMSUNG_DEV_PWM
- help
- Compile in platform device definition LCD backlight with PWM Timer
-
# platform specific device setup
config S3C64XX_SETUP_I2C0
@@ -99,7 +92,7 @@ config S3C64XX_SETUP_SDHCI_GPIO
config S3C64XX_SETUP_SPI
bool
help
- Common setup code for SPI GPIO configurations
+ Common setup code for SPI GPIO configurations
config S3C64XX_SETUP_USB_PHY
bool
@@ -108,201 +101,6 @@ config S3C64XX_SETUP_USB_PHY
# S36400 Macchine support
-config MACH_SMDK6400
- bool "SMDK6400"
- depends on ATAGS
- select CPU_S3C6400
- select S3C64XX_SETUP_SDHCI
- select S3C_DEV_HSMMC1
- help
- Machine support for the Samsung SMDK6400
-
-# S3C6410 machine support
-
-config MACH_ANW6410
- bool "A&W6410"
- depends on ATAGS
- select CPU_S3C6410
- select S3C64XX_SETUP_FB_24BPP
- select S3C_DEV_FB
- help
- Machine support for the A&W6410
-
-config MACH_MINI6410
- bool "MINI6410"
- depends on ATAGS
- select CPU_S3C6410
- select S3C64XX_SETUP_FB_24BPP
- select S3C64XX_SETUP_SDHCI
- select S3C_DEV_FB
- select S3C_DEV_HSMMC
- select S3C_DEV_HSMMC1
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- select SAMSUNG_DEV_ADC
- select SAMSUNG_DEV_TS
- help
- Machine support for the FriendlyARM MINI6410
-
-config MACH_REAL6410
- bool "REAL6410"
- depends on ATAGS
- select CPU_S3C6410
- select S3C64XX_SETUP_FB_24BPP
- select S3C64XX_SETUP_SDHCI
- select S3C_DEV_FB
- select S3C_DEV_HSMMC
- select S3C_DEV_HSMMC1
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- select SAMSUNG_DEV_ADC
- select SAMSUNG_DEV_TS
- help
- Machine support for the CoreWind REAL6410
-
-config MACH_SMDK6410
- bool "SMDK6410"
- depends on ATAGS
- select CPU_S3C6410
- select S3C64XX_SETUP_FB_24BPP
- select S3C64XX_SETUP_I2C1
- select S3C64XX_SETUP_IDE
- select S3C64XX_SETUP_KEYPAD
- select S3C64XX_SETUP_SDHCI
- select S3C64XX_SETUP_USB_PHY
- select S3C_DEV_FB
- select S3C_DEV_HSMMC
- select S3C_DEV_HSMMC1
- select S3C_DEV_I2C1
- select S3C_DEV_RTC
- select S3C_DEV_USB_HOST
- select S3C_DEV_USB_HSOTG
- select S3C_DEV_WDT
- select SAMSUNG_DEV_ADC
- select SAMSUNG_DEV_BACKLIGHT
- select SAMSUNG_DEV_IDE
- select SAMSUNG_DEV_KEYPAD
- select SAMSUNG_DEV_PWM
- select SAMSUNG_DEV_TS
- help
- Machine support for the Samsung SMDK6410
-
-# At least some of the SMDK6410s were shipped with the card detect
-# for the MMC/SD slots connected to the same input. This means that
-# either the boards need to be altered to have channel0 to an alternate
-# configuration or that only one slot can be used.
-
-choice
- prompt "SMDK6410 MMC/SD slot setup"
- depends on MACH_SMDK6410
-
-config SMDK6410_SD_CH0
- bool "Use channel 0 only"
- depends on MACH_SMDK6410
- help
- Select CON7 (channel 0) as the MMC/SD slot, as
- at least some SMDK6410 boards come with the
- resistors fitted so that the card detects for
- channels 0 and 1 are the same.
-
-config SMDK6410_SD_CH1
- bool "Use channel 1 only"
- depends on MACH_SMDK6410
- help
- Select CON6 (channel 1) as the MMC/SD slot, as
- at least some SMDK6410 boards come with the
- resistors fitted so that the card detects for
- channels 0 and 1 are the same.
-
-endchoice
-
-config SMDK6410_WM1190_EV1
- bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
- depends on MACH_SMDK6410
- depends on I2C=y
- select MFD_WM8350_I2C
- select REGULATOR
- select REGULATOR_WM8350
- help
- The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
- and audio daughtercard for the Samsung SMDK6410 reference
- platform. Enabling this option will build support for this
- module into the kernel. The presence of the module will be
- detected at runtime so the resulting kernel can be used
- with or without the 1190-EV1 fitted.
-
-config SMDK6410_WM1192_EV1
- bool "Support Wolfson Microelectronics 1192-EV1 PMIC card"
- depends on MACH_SMDK6410
- depends on I2C=y
- select MFD_WM831X
- select MFD_WM831X_I2C
- select REGULATOR
- select REGULATOR_WM831X
- help
- The Wolfson Microelectronics 1192-EV1 is a WM831x based PMIC
- daughtercard for the Samsung SMDK6410 reference platform.
- Enabling this option will build support for this module into
- the kernel. The presence of the daughtercard will be
- detected at runtime so the resulting kernel can be used
- with or without the 1192-EV1 fitted.
-
-config MACH_NCP
- bool "NCP"
- depends on ATAGS
- select CPU_S3C6410
- select S3C64XX_SETUP_I2C1
- select S3C_DEV_HSMMC1
- select S3C_DEV_I2C1
- help
- Machine support for the Samsung NCP
-
-config MACH_HMT
- bool "Airgoo HMT"
- depends on ATAGS
- select CPU_S3C6410
- select S3C64XX_SETUP_FB_24BPP
- select S3C_DEV_FB
- select S3C_DEV_NAND
- select S3C_DEV_USB_HOST
- select SAMSUNG_DEV_PWM
- help
- Machine support for the Airgoo HMT
-
-config MACH_SMARTQ
- bool
- select CPU_S3C6410
- select S3C64XX_SETUP_FB_24BPP
- select S3C64XX_SETUP_SDHCI
- select S3C64XX_SETUP_USB_PHY
- select S3C_DEV_FB
- select S3C_DEV_HSMMC
- select S3C_DEV_HSMMC1
- select S3C_DEV_HSMMC2
- select S3C_DEV_HWMON
- select S3C_DEV_RTC
- select S3C_DEV_USB_HOST
- select S3C_DEV_USB_HSOTG
- select SAMSUNG_DEV_ADC
- select SAMSUNG_DEV_PWM
- select SAMSUNG_DEV_TS
- help
- Shared machine support for SmartQ 5/7
-
-config MACH_SMARTQ5
- bool "SmartQ 5"
- depends on ATAGS
- select MACH_SMARTQ
- help
- Machine support for the SmartQ 5
-
-config MACH_SMARTQ7
- bool "SmartQ 7"
- depends on ATAGS
- select MACH_SMARTQ
- help
- Machine support for the SmartQ 7
-
config MACH_WLF_CRAGG_6410
bool "Wolfson Cragganmore 6410"
depends on ATAGS
@@ -322,11 +120,8 @@ config MACH_WLF_CRAGG_6410
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_I2C1
- select S3C_DEV_RTC
select S3C_DEV_USB_HOST
select S3C_DEV_USB_HSOTG
- select S3C_DEV_WDT
- select SAMSUNG_DEV_ADC
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
help
diff --git a/arch/arm/mach-s3c/Makefile b/arch/arm/mach-s3c/Makefile
index 54188d10ab2e..713827bef831 100644
--- a/arch/arm/mach-s3c/Makefile
+++ b/arch/arm/mach-s3c/Makefile
@@ -2,28 +2,15 @@
#
# Copyright 2009 Simtec Electronics
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include
-
-ifdef CONFIG_ARCH_S3C24XX
-include $(src)/Makefile.s3c24xx
-endif
-
-ifdef CONFIG_ARCH_S3C64XX
-include $(src)/Makefile.s3c64xx
-endif
+include $(srctree)/$(src)/Makefile.s3c64xx
# Objects we always build independent of SoC choice
obj-y += init.o cpu.o
-# ADC
-
-obj-$(CONFIG_S3C_ADC) += adc.o
-
# devices
obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o
-
obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o
obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o
@@ -33,5 +20,4 @@ obj-$(CONFIG_GPIO_SAMSUNG) += gpio-samsung.o
obj-$(CONFIG_SAMSUNG_PM) += pm.o pm-common.o
obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o
-
obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
diff --git a/arch/arm/mach-s3c/Makefile.boot b/arch/arm/mach-s3c/Makefile.boot
deleted file mode 100644
index 7f19e226035e..000000000000
--- a/arch/arm/mach-s3c/Makefile.boot
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-
-ifeq ($(CONFIG_PM_H1940),y)
- zreladdr-y += 0x30108000
- params_phys-y := 0x30100100
-else
- zreladdr-y += 0x30008000
- params_phys-y := 0x30000100
-endif
diff --git a/arch/arm/mach-s3c/Makefile.s3c24xx b/arch/arm/mach-s3c/Makefile.s3c24xx
deleted file mode 100644
index 3483ab3a2b81..000000000000
--- a/arch/arm/mach-s3c/Makefile.s3c24xx
+++ /dev/null
@@ -1,102 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (c) 2012 Samsung Electronics Co., Ltd.
-# http://www.samsung.com/
-#
-# Copyright 2007 Simtec Electronics
-
-# core
-
-obj-y += s3c24xx.o
-obj-y += irq-s3c24xx.o
-obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq.o
-obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq-exports.o
-
-obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
-obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
-obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
-
-obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
-obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
-obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
-
-obj-$(CONFIG_CPU_S3C2416) += s3c2416.o
-obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
-
-obj-$(CONFIG_CPU_S3C2440) += s3c2440.o
-obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
-obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
-obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
-
-obj-$(CONFIG_CPU_S3C2443) += s3c2443.o
-
-# PM
-
-obj-$(CONFIG_PM) += pm-s3c24xx.o
-obj-$(CONFIG_PM_SLEEP) += irq-pm-s3c24xx.o sleep-s3c24xx.o
-
-# common code
-
-obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += cpufreq-utils-s3c24xx.o
-
-obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
-obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
-
-#
-# machine support
-# following is ordered alphabetically by option text.
-#
-
-obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o
-obj-$(CONFIG_ARCH_BAST) += mach-bast.o
-obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
-obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
-obj-$(CONFIG_H1940BT) += h1940-bluetooth.o
-obj-$(CONFIG_PM_H1940) += pm-h1940.o
-obj-$(CONFIG_MACH_N30) += mach-n30.o
-obj-$(CONFIG_MACH_OTOM) += mach-otom.o
-obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o
-obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
-obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o
-obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o
-
-obj-$(CONFIG_MACH_JIVE) += mach-jive.o
-obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o
-obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o
-
-obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o
-obj-$(CONFIG_MACH_S3C2416_DT) += mach-s3c2416-dt.o
-
-obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
-obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
-obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
-obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
-obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o
-obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
-obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
-
-obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
-obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
-
-obj-$(CONFIG_MACH_SMDK2443) += mach-smdk2443.o
-
-# common bits of machine support
-
-obj-$(CONFIG_S3C24XX_SMDK) += common-smdk-s3c24xx.o
-obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO) += simtec-audio.o
-obj-$(CONFIG_S3C24XX_SIMTEC_NOR) += simtec-nor.o
-obj-$(CONFIG_S3C24XX_SIMTEC_PM) += simtec-pm.o
-obj-$(CONFIG_S3C24XX_SIMTEC_USB) += simtec-usb.o
-
-# machine additions
-
-obj-$(CONFIG_MACH_BAST_IDE) += bast-ide.o
-obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o
-
-# device setup
-
-obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio-s3c24xx.o
-obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi-s3c24xx.o
-obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c-s3c24xx.o
-obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts-s3c24xx.o
diff --git a/arch/arm/mach-s3c/Makefile.s3c64xx b/arch/arm/mach-s3c/Makefile.s3c64xx
index 0c18e31936df..61287ad2ea42 100644
--- a/arch/arm/mach-s3c/Makefile.s3c64xx
+++ b/arch/arm/mach-s3c/Makefile.s3c64xx
@@ -3,9 +3,6 @@
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-
# PM
obj-$(CONFIG_PM) += pm-s3c64xx.o
@@ -19,7 +16,6 @@ obj-$(CONFIG_PM_SLEEP) += irq-pm-s3c64xx.o
# Core
obj-y += s3c64xx.o
-obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
# DMA support
@@ -36,26 +32,12 @@ obj-y += dev-audio-s3c64xx.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp-s3c64xx.o
obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0-s3c64xx.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1-s3c64xx.o
-obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide-s3c64xx.o
obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad-s3c64xx.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio-s3c64xx.o
obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi-s3c64xx.o
obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy-s3c64xx.o
-obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight-s3c64xx.o
-
# Machine support
-
-obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
-obj-$(CONFIG_MACH_HMT) += mach-hmt.o
-obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
-obj-$(CONFIG_MACH_NCP) += mach-ncp.o
-obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
-obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
-obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
-obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
-obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
-obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
endif
diff --git a/arch/arm/mach-s3c/adc-core.h b/arch/arm/mach-s3c/adc-core.h
deleted file mode 100644
index 039f6862b6a7..000000000000
--- a/arch/arm/mach-s3c/adc-core.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * Samsung ADC Controller core functions
- */
-
-#ifndef __ASM_PLAT_ADC_CORE_H
-#define __ASM_PLAT_ADC_CORE_H __FILE__
-
-/* These functions are only for use with the core support code, such as
- * the cpu specific initialisation code
- */
-
-/* re-define device name depending on support. */
-static inline void s3c_adc_setname(char *name)
-{
-#if defined(CONFIG_SAMSUNG_DEV_ADC) || defined(CONFIG_PLAT_S3C24XX)
- s3c_device_adc.name = name;
-#endif
-}
-
-#endif /* __ASM_PLAT_ADC_CORE_H */
diff --git a/arch/arm/mach-s3c/adc.c b/arch/arm/mach-s3c/adc.c
deleted file mode 100644
index 0232520d3c13..000000000000
--- a/arch/arm/mach-s3c/adc.c
+++ /dev/null
@@ -1,510 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0+
-//
-// Copyright (c) 2008 Simtec Electronics
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
-//
-// Samsung ADC device core
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/mod_devicetable.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/list.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/regulator/consumer.h>
-
-#include "regs-adc.h"
-#include <linux/soc/samsung/s3c-adc.h>
-
-/* This driver is designed to control the usage of the ADC block between
- * the touchscreen and any other drivers that may need to use it, such as
- * the hwmon driver.
- *
- * Priority will be given to the touchscreen driver, but as this itself is
- * rate limited it should not starve other requests which are processed in
- * order that they are received.
- *
- * Each user registers to get a client block which uniquely identifies it
- * and stores information such as the necessary functions to callback when
- * action is required.
- */
-
-enum s3c_cpu_type {
- TYPE_ADCV1, /* S3C24XX */
- TYPE_ADCV11, /* S3C2443 */
- TYPE_ADCV12, /* S3C2416, S3C2450 */
- TYPE_ADCV2, /* S3C64XX */
- TYPE_ADCV3, /* S5PV210, S5PC110, Exynos4210 */
-};
-
-struct s3c_adc_client {
- struct platform_device *pdev;
- struct list_head pend;
- wait_queue_head_t *wait;
-
- unsigned int nr_samples;
- int result;
- unsigned char is_ts;
- unsigned char channel;
-
- void (*select_cb)(struct s3c_adc_client *c, unsigned selected);
- void (*convert_cb)(struct s3c_adc_client *c,
- unsigned val1, unsigned val2,
- unsigned *samples_left);
-};
-
-struct adc_device {
- struct platform_device *pdev;
- struct platform_device *owner;
- struct clk *clk;
- struct s3c_adc_client *cur;
- struct s3c_adc_client *ts_pend;
- void __iomem *regs;
- spinlock_t lock;
-
- unsigned int prescale;
-
- int irq;
- struct regulator *vdd;
-};
-
-static struct adc_device *adc_dev;
-
-static LIST_HEAD(adc_pending); /* protected by adc_device.lock */
-
-#define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
-
-static inline void s3c_adc_convert(struct adc_device *adc)
-{
- unsigned con = readl(adc->regs + S3C2410_ADCCON);
-
- con |= S3C2410_ADCCON_ENABLE_START;
- writel(con, adc->regs + S3C2410_ADCCON);
-}
-
-static inline void s3c_adc_select(struct adc_device *adc,
- struct s3c_adc_client *client)
-{
- unsigned con = readl(adc->regs + S3C2410_ADCCON);
- enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
-
- client->select_cb(client, 1);
-
- if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
- con &= ~S3C2410_ADCCON_MUXMASK;
- con &= ~S3C2410_ADCCON_STDBM;
- con &= ~S3C2410_ADCCON_STARTMASK;
-
- if (!client->is_ts) {
- if (cpu == TYPE_ADCV3)
- writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
- else if (cpu == TYPE_ADCV11 || cpu == TYPE_ADCV12)
- writel(client->channel & 0xf,
- adc->regs + S3C2443_ADCMUX);
- else
- con |= S3C2410_ADCCON_SELMUX(client->channel);
- }
-
- writel(con, adc->regs + S3C2410_ADCCON);
-}
-
-static void s3c_adc_dbgshow(struct adc_device *adc)
-{
- adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
- readl(adc->regs + S3C2410_ADCCON),
- readl(adc->regs + S3C2410_ADCTSC),
- readl(adc->regs + S3C2410_ADCDLY));
-}
-
-static void s3c_adc_try(struct adc_device *adc)
-{
- struct s3c_adc_client *next = adc->ts_pend;
-
- if (!next && !list_empty(&adc_pending)) {
- next = list_first_entry(&adc_pending,
- struct s3c_adc_client, pend);
- list_del(&next->pend);
- } else
- adc->ts_pend = NULL;
-
- if (next) {
- adc_dbg(adc, "new client is %p\n", next);
- adc->cur = next;
- s3c_adc_select(adc, next);
- s3c_adc_convert(adc);
- s3c_adc_dbgshow(adc);
- }
-}
-
-int s3c_adc_start(struct s3c_adc_client *client,
- unsigned int channel, unsigned int nr_samples)
-{
- struct adc_device *adc = adc_dev;
- unsigned long flags;
-
- if (!adc) {
- printk(KERN_ERR "%s: failed to find adc\n", __func__);
- return -EINVAL;
- }
-
- spin_lock_irqsave(&adc->lock, flags);
-
- if (client->is_ts && adc->ts_pend) {
- spin_unlock_irqrestore(&adc->lock, flags);
- return -EAGAIN;
- }
-
- client->channel = channel;
- client->nr_samples = nr_samples;
-
- if (client->is_ts)
- adc->ts_pend = client;
- else
- list_add_tail(&client->pend, &adc_pending);
-
- if (!adc->cur)
- s3c_adc_try(adc);
-
- spin_unlock_irqrestore(&adc->lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(s3c_adc_start);
-
-static void s3c_convert_done(struct s3c_adc_client *client,
- unsigned v, unsigned u, unsigned *left)
-{
- client->result = v;
- wake_up(client->wait);
-}
-
-int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
-{
- DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
- int ret;
-
- client->convert_cb = s3c_convert_done;
- client->wait = &wake;
- client->result = -1;
-
- ret = s3c_adc_start(client, ch, 1);
- if (ret < 0)
- goto err;
-
- ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
- if (client->result < 0) {
- ret = -ETIMEDOUT;
- goto err;
- }
-
- client->convert_cb = NULL;
- return client->result;
-
-err:
- return ret;
-}
-EXPORT_SYMBOL_GPL(s3c_adc_read);
-
-static void s3c_adc_default_select(struct s3c_adc_client *client,
- unsigned select)
-{
-}
-
-struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
- void (*select)(struct s3c_adc_client *client,
- unsigned int selected),
- void (*conv)(struct s3c_adc_client *client,
- unsigned d0, unsigned d1,
- unsigned *samples_left),
- unsigned int is_ts)
-{
- struct s3c_adc_client *client;
-
- WARN_ON(!pdev);
-
- if (!select)
- select = s3c_adc_default_select;
-
- if (!pdev)
- return ERR_PTR(-EINVAL);
-
- client = kzalloc(sizeof(*client), GFP_KERNEL);
- if (!client)
- return ERR_PTR(-ENOMEM);
-
- client->pdev = pdev;
- client->is_ts = is_ts;
- client->select_cb = select;
- client->convert_cb = conv;
-
- return client;
-}
-EXPORT_SYMBOL_GPL(s3c_adc_register);
-
-void s3c_adc_release(struct s3c_adc_client *client)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&adc_dev->lock, flags);
-
- /* We should really check that nothing is in progress. */
- if (adc_dev->cur == client)
- adc_dev->cur = NULL;
- if (adc_dev->ts_pend == client)
- adc_dev->ts_pend = NULL;
- else {
- struct list_head *p, *n;
- struct s3c_adc_client *tmp;
-
- list_for_each_safe(p, n, &adc_pending) {
- tmp = list_entry(p, struct s3c_adc_client, pend);
- if (tmp == client)
- list_del(&tmp->pend);
- }
- }
-
- if (adc_dev->cur == NULL)
- s3c_adc_try(adc_dev);
-
- spin_unlock_irqrestore(&adc_dev->lock, flags);
- kfree(client);
-}
-EXPORT_SYMBOL_GPL(s3c_adc_release);
-
-static irqreturn_t s3c_adc_irq(int irq, void *pw)
-{
- struct adc_device *adc = pw;
- struct s3c_adc_client *client = adc->cur;
- enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
- unsigned data0, data1;
-
- if (!client) {
- dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
- goto exit;
- }
-
- data0 = readl(adc->regs + S3C2410_ADCDAT0);
- data1 = readl(adc->regs + S3C2410_ADCDAT1);
- adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
-
- client->nr_samples--;
-
- if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) {
- data0 &= 0x3ff;
- data1 &= 0x3ff;
- } else {
- /* S3C2416/S3C64XX/S5P ADC resolution is 12-bit */
- data0 &= 0xfff;
- data1 &= 0xfff;
- }
-
- if (client->convert_cb)
- (client->convert_cb)(client, data0, data1, &client->nr_samples);
-
- if (client->nr_samples > 0) {
- /* fire another conversion for this */
-
- client->select_cb(client, 1);
- s3c_adc_convert(adc);
- } else {
- spin_lock(&adc->lock);
- (client->select_cb)(client, 0);
- adc->cur = NULL;
-
- s3c_adc_try(adc);
- spin_unlock(&adc->lock);
- }
-
-exit:
- if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
- /* Clear ADC interrupt */
- writel(0, adc->regs + S3C64XX_ADCCLRINT);
- }
- return IRQ_HANDLED;
-}
-
-static int s3c_adc_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct adc_device *adc;
- enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
- int ret;
- unsigned tmp;
-
- adc = devm_kzalloc(dev, sizeof(*adc), GFP_KERNEL);
- if (!adc)
- return -ENOMEM;
-
- spin_lock_init(&adc->lock);
-
- adc->pdev = pdev;
- adc->prescale = S3C2410_ADCCON_PRSCVL(49);
-
- adc->vdd = devm_regulator_get(dev, "vdd");
- if (IS_ERR(adc->vdd)) {
- dev_err(dev, "operating without regulator \"vdd\" .\n");
- return PTR_ERR(adc->vdd);
- }
-
- adc->irq = platform_get_irq(pdev, 1);
- if (adc->irq <= 0)
- return -ENOENT;
-
- ret = devm_request_irq(dev, adc->irq, s3c_adc_irq, 0, dev_name(dev),
- adc);
- if (ret < 0) {
- dev_err(dev, "failed to attach adc irq\n");
- return ret;
- }
-
- adc->clk = devm_clk_get(dev, "adc");
- if (IS_ERR(adc->clk)) {
- dev_err(dev, "failed to get adc clock\n");
- return PTR_ERR(adc->clk);
- }
-
- adc->regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(adc->regs))
- return PTR_ERR(adc->regs);
-
- ret = regulator_enable(adc->vdd);
- if (ret)
- return ret;
-
- clk_prepare_enable(adc->clk);
-
- tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
-
- /* Enable 12-bit ADC resolution */
- if (cpu == TYPE_ADCV12)
- tmp |= S3C2416_ADCCON_RESSEL;
- if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
- tmp |= S3C64XX_ADCCON_RESSEL;
-
- writel(tmp, adc->regs + S3C2410_ADCCON);
-
- dev_info(dev, "attached adc driver\n");
-
- platform_set_drvdata(pdev, adc);
- adc_dev = adc;
-
- return 0;
-}
-
-static int s3c_adc_remove(struct platform_device *pdev)
-{
- struct adc_device *adc = platform_get_drvdata(pdev);
-
- clk_disable_unprepare(adc->clk);
- regulator_disable(adc->vdd);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int s3c_adc_suspend(struct device *dev)
-{
- struct adc_device *adc = dev_get_drvdata(dev);
- unsigned long flags;
- u32 con;
-
- spin_lock_irqsave(&adc->lock, flags);
-
- con = readl(adc->regs + S3C2410_ADCCON);
- con |= S3C2410_ADCCON_STDBM;
- writel(con, adc->regs + S3C2410_ADCCON);
-
- disable_irq(adc->irq);
- spin_unlock_irqrestore(&adc->lock, flags);
- clk_disable(adc->clk);
- regulator_disable(adc->vdd);
-
- return 0;
-}
-
-static int s3c_adc_resume(struct device *dev)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct adc_device *adc = platform_get_drvdata(pdev);
- enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
- int ret;
- unsigned long tmp;
-
- ret = regulator_enable(adc->vdd);
- if (ret)
- return ret;
- clk_enable(adc->clk);
- enable_irq(adc->irq);
-
- tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
-
- /* Enable 12-bit ADC resolution */
- if (cpu == TYPE_ADCV12)
- tmp |= S3C2416_ADCCON_RESSEL;
- if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
- tmp |= S3C64XX_ADCCON_RESSEL;
-
- writel(tmp, adc->regs + S3C2410_ADCCON);
-
- return 0;
-}
-
-#else
-#define s3c_adc_suspend NULL
-#define s3c_adc_resume NULL
-#endif
-
-static const struct platform_device_id s3c_adc_driver_ids[] = {
- {
- .name = "s3c24xx-adc",
- .driver_data = TYPE_ADCV1,
- }, {
- .name = "s3c2443-adc",
- .driver_data = TYPE_ADCV11,
- }, {
- .name = "s3c2416-adc",
- .driver_data = TYPE_ADCV12,
- }, {
- .name = "s3c64xx-adc",
- .driver_data = TYPE_ADCV2,
- }, {
- .name = "samsung-adc-v3",
- .driver_data = TYPE_ADCV3,
- },
- { }
-};
-MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
-
-static const struct dev_pm_ops adc_pm_ops = {
- .suspend = s3c_adc_suspend,
- .resume = s3c_adc_resume,
-};
-
-static struct platform_driver s3c_adc_driver = {
- .id_table = s3c_adc_driver_ids,
- .driver = {
- .name = "s3c-adc",
- .pm = &adc_pm_ops,
- },
- .probe = s3c_adc_probe,
- .remove = s3c_adc_remove,
-};
-
-static int __init adc_init(void)
-{
- int ret;
-
- ret = platform_driver_register(&s3c_adc_driver);
- if (ret)
- printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
-
- return ret;
-}
-
-module_init(adc_init);
diff --git a/arch/arm/mach-s3c/anubis.h b/arch/arm/mach-s3c/anubis.h
deleted file mode 100644
index 13847292e6c7..000000000000
--- a/arch/arm/mach-s3c/anubis.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2005 Simtec Electronics
- * http://www.simtec.co.uk/products/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - CPLD control constants
- * ANUBIS - IRQ Number definitions
- * ANUBIS - Memory map definitions
- */
-
-#ifndef __MACH_S3C24XX_ANUBIS_H
-#define __MACH_S3C24XX_ANUBIS_H __FILE__
-
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-
-#define ANUBIS_CTRL1_NANDSEL (0x3)
-
-/* IDREG - revision */
-
-#define ANUBIS_IDREG_REVMASK (0x7)
-
-/* irq */
-
-#define ANUBIS_IRQ_IDE0 IRQ_EINT2
-#define ANUBIS_IRQ_IDE1 IRQ_EINT3
-#define ANUBIS_IRQ_ASIX IRQ_EINT1
-
-/* map */
-
-/* start peripherals off after the S3C2410 */
-
-#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
-
-#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000)
-#define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD
-
-#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000)
-#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23))
-
-#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
-#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
-#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
-#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
-
-#endif /* __MACH_S3C24XX_ANUBIS_H */
diff --git a/arch/arm/mach-s3c/ata-core-s3c64xx.h b/arch/arm/mach-s3c/ata-core-s3c64xx.h
deleted file mode 100644
index 4863ad9d3a42..000000000000
--- a/arch/arm/mach-s3c/ata-core-s3c64xx.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Samsung CF-ATA Controller core functions
- */
-
-#ifndef __ASM_PLAT_ATA_CORE_S3C64XX_H
-#define __ASM_PLAT_ATA_CORE_S3C64XX_H __FILE__
-
-/* These functions are only for use with the core support code, such as
- * the cpu specific initialisation code
-*/
-
-/* re-define device name depending on support. */
-static inline void s3c_cfcon_setname(char *name)
-{
-#ifdef CONFIG_SAMSUNG_DEV_IDE
- s3c_device_cfcon.name = name;
-#endif
-}
-
-#endif /* __ASM_PLAT_ATA_CORE_S3C64XX_H */
diff --git a/arch/arm/mach-s3c/backlight-s3c64xx.h b/arch/arm/mach-s3c/backlight-s3c64xx.h
deleted file mode 100644
index 2a2b35821d58..000000000000
--- a/arch/arm/mach-s3c/backlight-s3c64xx.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- */
-
-#ifndef __ASM_PLAT_BACKLIGHT_S3C64XX_H
-#define __ASM_PLAT_BACKLIGHT_S3C64XX_H __FILE__
-
-/* samsung_bl_gpio_info - GPIO info for PWM Backlight control
- * @no: GPIO number for PWM timer out
- * @func: Special function of GPIO line for PWM timer
- */
-struct samsung_bl_gpio_info {
- int no;
- int func;
-};
-
-extern void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
- struct platform_pwm_backlight_data *bl_data);
-
-#endif /* __ASM_PLAT_BACKLIGHT_S3C64XX_H */
diff --git a/arch/arm/mach-s3c/bast-ide.c b/arch/arm/mach-s3c/bast-ide.c
deleted file mode 100644
index da64db1811d8..000000000000
--- a/arch/arm/mach-s3c/bast-ide.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2007 Simtec Electronics
-// http://www.simtec.co.uk/products/EB2410ITX/
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include "map.h"
-#include <mach/irqs.h>
-
-#include "bast.h"
-
-/* IDE ports */
-
-static struct pata_platform_info bast_ide_platdata = {
- .ioport_shift = 5,
-};
-
-static struct resource bast_ide0_resource[] = {
- [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
- [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
- [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
-};
-
-static struct platform_device bast_device_ide0 = {
- .name = "pata_platform",
- .id = 0,
- .num_resources = ARRAY_SIZE(bast_ide0_resource),
- .resource = bast_ide0_resource,
- .dev = {
- .platform_data = &bast_ide_platdata,
- .coherent_dma_mask = ~0,
- }
-
-};
-
-static struct resource bast_ide1_resource[] = {
- [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
- [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
- [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
-};
-
-static struct platform_device bast_device_ide1 = {
- .name = "pata_platform",
- .id = 1,
- .num_resources = ARRAY_SIZE(bast_ide1_resource),
- .resource = bast_ide1_resource,
- .dev = {
- .platform_data = &bast_ide_platdata,
- .coherent_dma_mask = ~0,
- }
-};
-
-static struct platform_device *bast_ide_devices[] __initdata = {
- &bast_device_ide0,
- &bast_device_ide1,
-};
-
-static __init int bast_ide_init(void)
-{
- if (machine_is_bast() || machine_is_vr1000())
- return platform_add_devices(bast_ide_devices,
- ARRAY_SIZE(bast_ide_devices));
-
- return 0;
-}
-
-fs_initcall(bast_ide_init);
diff --git a/arch/arm/mach-s3c/bast-irq.c b/arch/arm/mach-s3c/bast-irq.c
deleted file mode 100644
index d299f124e6dc..000000000000
--- a/arch/arm/mach-s3c/bast-irq.c
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright 2003-2005 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-//
-// http://www.simtec.co.uk/products/EB2410ITX/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/mach/irq.h>
-
-#include "regs-irq.h"
-#include <mach/irqs.h>
-
-#include "bast.h"
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-/* handle PC104 ISA interrupts from the system CPLD */
-
-/* table of ISA irq nos to the relevant mask... zero means
- * the irq is not implemented
-*/
-static const unsigned char bast_pc104_irqmasks[] = {
- 0, /* 0 */
- 0, /* 1 */
- 0, /* 2 */
- 1, /* 3 */
- 0, /* 4 */
- 2, /* 5 */
- 0, /* 6 */
- 4, /* 7 */
- 0, /* 8 */
- 0, /* 9 */
- 8, /* 10 */
- 0, /* 11 */
- 0, /* 12 */
- 0, /* 13 */
- 0, /* 14 */
- 0, /* 15 */
-};
-
-static const unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
-
-static void
-bast_pc104_mask(struct irq_data *data)
-{
- unsigned long temp;
-
- temp = __raw_readb(BAST_VA_PC104_IRQMASK);
- temp &= ~bast_pc104_irqmasks[data->irq];
- __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
-}
-
-static void
-bast_pc104_maskack(struct irq_data *data)
-{
- struct irq_desc *desc = irq_to_desc(BAST_IRQ_ISA);
-
- bast_pc104_mask(data);
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-}
-
-static void
-bast_pc104_unmask(struct irq_data *data)
-{
- unsigned long temp;
-
- temp = __raw_readb(BAST_VA_PC104_IRQMASK);
- temp |= bast_pc104_irqmasks[data->irq];
- __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
-}
-
-static struct irq_chip bast_pc104_chip = {
- .irq_mask = bast_pc104_mask,
- .irq_unmask = bast_pc104_unmask,
- .irq_ack = bast_pc104_maskack
-};
-
-static void bast_irq_pc104_demux(struct irq_desc *desc)
-{
- unsigned int stat;
- unsigned int irqno;
- int i;
-
- stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf;
-
- if (unlikely(stat == 0)) {
- /* ack if we get an irq with nothing (ie, startup) */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
- } else {
- /* handle the IRQ */
-
- for (i = 0; stat != 0; i++, stat >>= 1) {
- if (stat & 1) {
- irqno = bast_pc104_irqs[i];
- generic_handle_irq(irqno);
- }
- }
- }
-}
-
-static __init int bast_irq_init(void)
-{
- unsigned int i;
-
- if (machine_is_bast()) {
- printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
-
- /* zap all the IRQs */
-
- __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
-
- irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
-
- /* register our IRQs */
-
- for (i = 0; i < 4; i++) {
- unsigned int irqno = bast_pc104_irqs[i];
-
- irq_set_chip_and_handler(irqno, &bast_pc104_chip,
- handle_level_irq);
- irq_clear_status_flags(irqno, IRQ_NOREQUEST);
- }
- }
-
- return 0;
-}
-
-arch_initcall(bast_irq_init);
diff --git a/arch/arm/mach-s3c/bast.h b/arch/arm/mach-s3c/bast.h
deleted file mode 100644
index a7726f93f5eb..000000000000
--- a/arch/arm/mach-s3c/bast.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2003-2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * BAST - CPLD control constants
- * BAST - IRQ Number definitions
- * BAST - Memory map definitions
- */
-
-#ifndef __MACH_S3C24XX_BAST_H
-#define __MACH_S3C24XX_BAST_H __FILE__
-
-/* CTRL1 - Audio LR routing */
-
-#define BAST_CPLD_CTRL1_LRCOFF (0x00)
-#define BAST_CPLD_CTRL1_LRCADC (0x01)
-#define BAST_CPLD_CTRL1_LRCDAC (0x02)
-#define BAST_CPLD_CTRL1_LRCARM (0x03)
-#define BAST_CPLD_CTRL1_LRMASK (0x03)
-
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-
-#define BAST_CPLD_CTRL2_WNAND (0x04)
-#define BAST_CPLD_CTLR2_IDERST (0x08)
-
-/* CTRL3 - rom write control, CPLD identity */
-
-#define BAST_CPLD_CTRL3_IDMASK (0x0e)
-#define BAST_CPLD_CTRL3_ROMWEN (0x01)
-
-/* CTRL4 - 8bit LCD interface control/status */
-
-#define BAST_CPLD_CTRL4_LLAT (0x01)
-#define BAST_CPLD_CTRL4_LCDRW (0x02)
-#define BAST_CPLD_CTRL4_LCDCMD (0x04)
-#define BAST_CPLD_CTRL4_LCDE2 (0x01)
-
-/* CTRL5 - DMA routing */
-
-#define BAST_CPLD_DMA0_PRIIDE (0)
-#define BAST_CPLD_DMA0_SECIDE (1)
-#define BAST_CPLD_DMA0_ISA15 (2)
-#define BAST_CPLD_DMA0_ISA36 (3)
-
-#define BAST_CPLD_DMA1_PRIIDE (0 << 2)
-#define BAST_CPLD_DMA1_SECIDE (1 << 2)
-#define BAST_CPLD_DMA1_ISA15 (2 << 2)
-#define BAST_CPLD_DMA1_ISA36 (3 << 2)
-
-/* irq numbers to onboard peripherals */
-
-#define BAST_IRQ_USBOC IRQ_EINT18
-#define BAST_IRQ_IDE0 IRQ_EINT16
-#define BAST_IRQ_IDE1 IRQ_EINT17
-#define BAST_IRQ_PCSERIAL1 IRQ_EINT15
-#define BAST_IRQ_PCSERIAL2 IRQ_EINT14
-#define BAST_IRQ_PCPARALLEL IRQ_EINT13
-#define BAST_IRQ_ASIX IRQ_EINT11
-#define BAST_IRQ_DM9000 IRQ_EINT10
-#define BAST_IRQ_ISA IRQ_EINT9
-#define BAST_IRQ_SMALERT IRQ_EINT8
-
-/* map */
-
-/*
- * ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-
-#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000)
-#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
-
-#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000)
-#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
-
-#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000)
-#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
-
-#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000)
-#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
-
-/* next, we have the PC104 ISA interrupt registers */
-
-#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000)
-#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
-
-#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000)
-#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
-
-#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000)
-#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
-
-#define BAST_PA_LCD_RCMD1 (0x8800000)
-#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
-
-#define BAST_PA_LCD_WCMD1 (0x8000000)
-#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
-
-#define BAST_PA_LCD_RDATA1 (0x9800000)
-#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
-
-#define BAST_PA_LCD_WDATA1 (0x9000000)
-#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
-
-#define BAST_PA_LCD_RCMD2 (0xA800000)
-#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
-
-#define BAST_PA_LCD_WCMD2 (0xA000000)
-#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
-
-#define BAST_PA_LCD_RDATA2 (0xB800000)
-#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
-
-#define BAST_PA_LCD_WDATA2 (0xB000000)
-#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
-
-
-/*
- * 0xE0000000 contains the IO space that is split by speed and
- * whether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000 8bit, slow
- * 0x04000000 to 0x08000000 16bit, slow
- * 0x08000000 to 0x0C000000 16bit, net
- * 0x0C000000 to 0x10000000 16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x00000000 to 0x01000000 16MB ISA IO space
- * 0x01000000 to 0x02000000 16MB ISA memory space
- * 0x02000000 to 0x02100000 1MB IDE primary channel
- * 0x02100000 to 0x02200000 1MB IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB IDE secondary channel
- * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
- * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
- * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
- * 0x02600000 to 0x02700000 1MB PC SuperIO controller
- *
- * the phyiscal layout of the zones are:
- * nGCS2 - 8bit, slow
- * nGCS3 - 16bit, slow
- * nGCS4 - 16bit, net
- * nGCS5 - 16bit, fast
- */
-
-#define BAST_VA_MULTISPACE (0xE0000000)
-
-#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
-#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
-#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
-#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
-#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
-#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
-#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
-#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
-#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
-
-#define BAST_VAM_CS2 (0x00000000)
-#define BAST_VAM_CS3 (0x04000000)
-#define BAST_VAM_CS4 (0x08000000)
-#define BAST_VAM_CS5 (0x0C000000)
-
-/* physical offset addresses for the peripherals */
-
-#define BAST_PA_ISAIO (0x00000000)
-#define BAST_PA_ASIXNET (0x01000000)
-#define BAST_PA_SUPERIO (0x01800000)
-#define BAST_PA_IDEPRI (0x02000000)
-#define BAST_PA_IDEPRIAUX (0x02800000)
-#define BAST_PA_IDESEC (0x03000000)
-#define BAST_PA_IDESECAUX (0x03800000)
-#define BAST_PA_ISAMEM (0x04000000)
-#define BAST_PA_DM9000 (0x05000000)
-
-/* some configurations for the peripherals */
-
-#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
-
-#define BAST_ASIXNET_CS BAST_VAM_CS5
-#define BAST_DM9000_CS BAST_VAM_CS4
-
-#define BAST_IDE_CS S3C2410_CS5
-
-#endif /* __MACH_S3C24XX_BAST_H */
diff --git a/arch/arm/mach-s3c/common-smdk-s3c24xx.c b/arch/arm/mach-s3c/common-smdk-s3c24xx.c
deleted file mode 100644
index 6d124bbd384c..000000000000
--- a/arch/arm/mach-s3c/common-smdk-s3c24xx.c
+++ /dev/null
@@ -1,228 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2006 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-//
-// Common code for SMDK2410 and SMDK2440 boards
-//
-// http://www.fluff.org/ben/smdk2440/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-#include <linux/io.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-#include <linux/platform_data/leds-s3c24xx.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-
-#include "gpio-cfg.h"
-#include "devs.h"
-#include "pm.h"
-
-#include "common-smdk-s3c24xx.h"
-
-/* LED devices */
-
-static struct gpiod_lookup_table smdk_led4_gpio_table = {
- .dev_id = "s3c24xx_led.0",
- .table = {
- GPIO_LOOKUP("GPF", 4, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct gpiod_lookup_table smdk_led5_gpio_table = {
- .dev_id = "s3c24xx_led.1",
- .table = {
- GPIO_LOOKUP("GPF", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct gpiod_lookup_table smdk_led6_gpio_table = {
- .dev_id = "s3c24xx_led.2",
- .table = {
- GPIO_LOOKUP("GPF", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct gpiod_lookup_table smdk_led7_gpio_table = {
- .dev_id = "s3c24xx_led.3",
- .table = {
- GPIO_LOOKUP("GPF", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct s3c24xx_led_platdata smdk_pdata_led4 = {
- .name = "led4",
- .def_trigger = "timer",
-};
-
-static struct s3c24xx_led_platdata smdk_pdata_led5 = {
- .name = "led5",
- .def_trigger = "nand-disk",
-};
-
-static struct s3c24xx_led_platdata smdk_pdata_led6 = {
- .name = "led6",
-};
-
-static struct s3c24xx_led_platdata smdk_pdata_led7 = {
- .name = "led7",
-};
-
-static struct platform_device smdk_led4 = {
- .name = "s3c24xx_led",
- .id = 0,
- .dev = {
- .platform_data = &smdk_pdata_led4,
- },
-};
-
-static struct platform_device smdk_led5 = {
- .name = "s3c24xx_led",
- .id = 1,
- .dev = {
- .platform_data = &smdk_pdata_led5,
- },
-};
-
-static struct platform_device smdk_led6 = {
- .name = "s3c24xx_led",
- .id = 2,
- .dev = {
- .platform_data = &smdk_pdata_led6,
- },
-};
-
-static struct platform_device smdk_led7 = {
- .name = "s3c24xx_led",
- .id = 3,
- .dev = {
- .platform_data = &smdk_pdata_led7,
- },
-};
-
-/* NAND parititon from 2.4.18-swl5 */
-
-static struct mtd_partition smdk_default_nand_part[] = {
- [0] = {
- .name = "Boot Agent",
- .size = SZ_16K,
- .offset = 0,
- },
- [1] = {
- .name = "S3C2410 flash partition 1",
- .offset = 0,
- .size = SZ_2M,
- },
- [2] = {
- .name = "S3C2410 flash partition 2",
- .offset = SZ_4M,
- .size = SZ_4M,
- },
- [3] = {
- .name = "S3C2410 flash partition 3",
- .offset = SZ_8M,
- .size = SZ_2M,
- },
- [4] = {
- .name = "S3C2410 flash partition 4",
- .offset = SZ_1M * 10,
- .size = SZ_4M,
- },
- [5] = {
- .name = "S3C2410 flash partition 5",
- .offset = SZ_1M * 14,
- .size = SZ_1M * 10,
- },
- [6] = {
- .name = "S3C2410 flash partition 6",
- .offset = SZ_1M * 24,
- .size = SZ_1M * 24,
- },
- [7] = {
- .name = "S3C2410 flash partition 7",
- .offset = SZ_1M * 48,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct s3c2410_nand_set smdk_nand_sets[] = {
- [0] = {
- .name = "NAND",
- .nr_chips = 1,
- .nr_partitions = ARRAY_SIZE(smdk_default_nand_part),
- .partitions = smdk_default_nand_part,
- },
-};
-
-/* choose a set of timings which should suit most 512Mbit
- * chips and beyond.
-*/
-
-static struct s3c2410_platform_nand smdk_nand_info = {
- .tacls = 20,
- .twrph0 = 60,
- .twrph1 = 20,
- .nr_sets = ARRAY_SIZE(smdk_nand_sets),
- .sets = smdk_nand_sets,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-/* devices we initialise */
-
-static struct platform_device __initdata *smdk_devs[] = {
- &s3c_device_nand,
- &smdk_led4,
- &smdk_led5,
- &smdk_led6,
- &smdk_led7,
-};
-
-void __init smdk_machine_init(void)
-{
- if (machine_is_smdk2443())
- smdk_nand_info.twrph0 = 50;
-
- s3c_nand_set_platdata(&smdk_nand_info);
-
- /* Disable pull-up on the LED lines */
- s3c_gpio_setpull(S3C2410_GPF(4), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPF(5), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPF(6), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPF(7), S3C_GPIO_PULL_NONE);
-
- /* Add lookups for the lines */
- gpiod_add_lookup_table(&smdk_led4_gpio_table);
- gpiod_add_lookup_table(&smdk_led5_gpio_table);
- gpiod_add_lookup_table(&smdk_led6_gpio_table);
- gpiod_add_lookup_table(&smdk_led7_gpio_table);
-
- platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
-
- s3c_pm_init();
-}
diff --git a/arch/arm/mach-s3c/common-smdk-s3c24xx.h b/arch/arm/mach-s3c/common-smdk-s3c24xx.h
deleted file mode 100644
index c0352b06e435..000000000000
--- a/arch/arm/mach-s3c/common-smdk-s3c24xx.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Common code for SMDK2410 and SMDK2440 boards
- *
- * http://www.fluff.org/ben/smdk2440/
- */
-
-extern void smdk_machine_init(void);
diff --git a/arch/arm/mach-s3c/cpu.c b/arch/arm/mach-s3c/cpu.c
index 6e9772555f0d..3491f790d575 100644
--- a/arch/arm/mach-s3c/cpu.c
+++ b/arch/arm/mach-s3c/cpu.c
@@ -10,7 +10,7 @@
#include <linux/init.h>
#include <linux/io.h>
-#include <mach/map-base.h>
+#include "map-base.h"
#include "cpu.h"
unsigned long samsung_cpu_id;
@@ -28,4 +28,5 @@ void __init s3c64xx_init_cpu(void)
}
pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
+ pr_err("The platform is deprecated and scheduled for removal. Please reach to the maintainers of the platform and linux-samsung-soc@vger.kernel.org if you still use it. Without such feedback, the platform will be removed after 2022.\n");
}
diff --git a/arch/arm/mach-s3c/cpu.h b/arch/arm/mach-s3c/cpu.h
index 20ff98d05c53..d0adc9b40e25 100644
--- a/arch/arm/mach-s3c/cpu.h
+++ b/arch/arm/mach-s3c/cpu.h
@@ -16,15 +16,6 @@
extern unsigned long samsung_cpu_id;
-#define S3C2410_CPU_ID 0x32410000
-#define S3C2410_CPU_MASK 0xFFFFFFFF
-
-#define S3C24XX_CPU_ID 0x32400000
-#define S3C24XX_CPU_MASK 0xFFF00000
-
-#define S3C2412_CPU_ID 0x32412000
-#define S3C2412_CPU_MASK 0xFFFFF000
-
#define S3C6400_CPU_ID 0x36400000
#define S3C6410_CPU_ID 0x36410000
#define S3C64XX_CPU_MASK 0xFFFFF000
@@ -38,29 +29,9 @@ static inline int is_samsung_##name(void) \
return ((samsung_cpu_id & mask) == (id & mask)); \
}
-IS_SAMSUNG_CPU(s3c2410, S3C2410_CPU_ID, S3C2410_CPU_MASK)
-IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
-IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
-#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
- defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
- defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
- defined(CONFIG_CPU_S3C2443)
-# define soc_is_s3c24xx() is_samsung_s3c24xx()
-# define soc_is_s3c2410() is_samsung_s3c2410()
-#else
-# define soc_is_s3c24xx() 0
-# define soc_is_s3c2410() 0
-#endif
-
-#if defined(CONFIG_CPU_S3C2412)
-# define soc_is_s3c2412() is_samsung_s3c2412()
-#else
-# define soc_is_s3c2412() 0
-#endif
-
#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
# define soc_is_s3c6400() is_samsung_s3c6400()
# define soc_is_s3c6410() is_samsung_s3c6410()
@@ -71,12 +42,6 @@ IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
# define soc_is_s3c64xx() 0
#endif
-#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
-
-#ifndef KHZ
-#define KHZ (1000)
-#endif
-
#ifndef MHZ
#define MHZ (1000*1000)
#endif
@@ -96,7 +61,6 @@ struct cpu_table {
unsigned long idmask;
void (*map_io)(void);
void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
- void (*init_clocks)(int xtal);
int (*init)(void);
const char *name;
};
@@ -105,24 +69,13 @@ extern void s3c_init_cpu(unsigned long idcode,
struct cpu_table *cpus, unsigned int cputab_size);
/* core initialisation functions */
-
-extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
-
extern void s3c64xx_init_cpu(void);
extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c24xx_init_clocks(int xtal);
-
extern void s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no);
-extern struct syscore_ops s3c2410_pm_syscore_ops;
-extern struct syscore_ops s3c2412_pm_syscore_ops;
-extern struct syscore_ops s3c2416_pm_syscore_ops;
-extern struct syscore_ops s3c244x_pm_syscore_ops;
-
extern struct bus_type s3c6410_subsys;
#endif
diff --git a/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c b/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c
deleted file mode 100644
index c1784d8facdf..000000000000
--- a/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2009 Simtec Electronics
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>
-//
-// S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/cpufreq.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-
-#include "map.h"
-#include "regs-clock.h"
-
-#include <linux/soc/samsung/s3c-cpufreq-core.h>
-
-#include "regs-mem-s3c24xx.h"
-
-/**
- * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
- * @cfg: The frequency configuration
- *
- * Set the SDRAM refresh value appropriately for the configured
- * frequency.
- */
-void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
-{
- struct s3c_cpufreq_board *board = cfg->board;
- unsigned long refresh;
- unsigned long refval;
-
- /* Reduce both the refresh time (in ns) and the frequency (in MHz)
- * down to ensure that we do not overflow 32 bit numbers.
- *
- * This should work for HCLK up to 133MHz and refresh period up
- * to 30usec.
- */
-
- refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
- refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
- refresh = (1 << 11) + 1 - refresh;
-
- s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
-
- refval = __raw_readl(S3C2410_REFRESH);
- refval &= ~((1 << 12) - 1);
- refval |= refresh;
- __raw_writel(refval, S3C2410_REFRESH);
-}
-
-/**
- * s3c2410_set_fvco - set the PLL value
- * @cfg: The frequency configuration
- */
-void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
-{
- if (!IS_ERR(cfg->mpll))
- clk_set_rate(cfg->mpll, cfg->pll.frequency);
-}
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-u32 s3c2440_read_camdivn(void)
-{
- return __raw_readl(S3C2440_CAMDIVN);
-}
-
-void s3c2440_write_camdivn(u32 camdiv)
-{
- __raw_writel(camdiv, S3C2440_CAMDIVN);
-}
-#endif
-
-u32 s3c24xx_read_clkdivn(void)
-{
- return __raw_readl(S3C2410_CLKDIVN);
-}
-
-void s3c24xx_write_clkdivn(u32 clkdiv)
-{
- __raw_writel(clkdiv, S3C2410_CLKDIVN);
-}
-
-u32 s3c24xx_read_mpllcon(void)
-{
- return __raw_readl(S3C2410_MPLLCON);
-}
-
-void s3c24xx_write_locktime(u32 locktime)
-{
- return __raw_writel(locktime, S3C2410_LOCKTIME);
-}
diff --git a/arch/arm/mach-s3c/cpuidle-s3c64xx.c b/arch/arm/mach-s3c/cpuidle-s3c64xx.c
index b1c5f43d4922..27a13cc27893 100644
--- a/arch/arm/mach-s3c/cpuidle-s3c64xx.c
+++ b/arch/arm/mach-s3c/cpuidle-s3c64xx.c
@@ -19,9 +19,8 @@
#include "regs-sys-s3c64xx.h"
#include "regs-syscon-power-s3c64xx.h"
-static int s3c64xx_enter_idle(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
+static __cpuidle int s3c64xx_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
unsigned long tmp;
diff --git a/arch/arm/mach-s3c/dev-audio-s3c64xx.c b/arch/arm/mach-s3c/dev-audio-s3c64xx.c
index fc2f077afd24..7ce119dc3a72 100644
--- a/arch/arm/mach-s3c/dev-audio-s3c64xx.c
+++ b/arch/arm/mach-s3c/dev-audio-s3c64xx.c
@@ -10,7 +10,7 @@
#include <linux/gpio.h>
#include <linux/export.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "devs.h"
@@ -83,130 +83,3 @@ struct platform_device s3c64xx_device_iis1 = {
},
};
EXPORT_SYMBOL(s3c64xx_device_iis1);
-
-static struct resource s3c64xx_iisv4_resource[] = {
- [0] = DEFINE_RES_MEM(S3C64XX_PA_IISV4, SZ_256),
-};
-
-static struct s3c_audio_pdata i2sv4_pdata = {
- .cfg_gpio = s3c64xx_i2s_cfg_gpio,
- .type = {
- .quirks = QUIRK_PRI_6CHAN,
- },
-};
-
-struct platform_device s3c64xx_device_iisv4 = {
- .name = "samsung-i2s",
- .id = 2,
- .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource),
- .resource = s3c64xx_iisv4_resource,
- .dev = {
- .platform_data = &i2sv4_pdata,
- },
-};
-EXPORT_SYMBOL(s3c64xx_device_iisv4);
-
-
-/* PCM Controller platform_devices */
-
-static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
-{
- unsigned int base;
-
- switch (pdev->id) {
- case 0:
- base = S3C64XX_GPD(0);
- break;
- case 1:
- base = S3C64XX_GPE(0);
- break;
- default:
- printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
- pdev->id);
- return -EINVAL;
- }
-
- s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
- return 0;
-}
-
-static struct resource s3c64xx_pcm0_resource[] = {
- [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM0, SZ_256),
-};
-
-static struct s3c_audio_pdata s3c_pcm0_pdata = {
- .cfg_gpio = s3c64xx_pcm_cfg_gpio,
-};
-
-struct platform_device s3c64xx_device_pcm0 = {
- .name = "samsung-pcm",
- .id = 0,
- .num_resources = ARRAY_SIZE(s3c64xx_pcm0_resource),
- .resource = s3c64xx_pcm0_resource,
- .dev = {
- .platform_data = &s3c_pcm0_pdata,
- },
-};
-EXPORT_SYMBOL(s3c64xx_device_pcm0);
-
-static struct resource s3c64xx_pcm1_resource[] = {
- [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM1, SZ_256),
-};
-
-static struct s3c_audio_pdata s3c_pcm1_pdata = {
- .cfg_gpio = s3c64xx_pcm_cfg_gpio,
-};
-
-struct platform_device s3c64xx_device_pcm1 = {
- .name = "samsung-pcm",
- .id = 1,
- .num_resources = ARRAY_SIZE(s3c64xx_pcm1_resource),
- .resource = s3c64xx_pcm1_resource,
- .dev = {
- .platform_data = &s3c_pcm1_pdata,
- },
-};
-EXPORT_SYMBOL(s3c64xx_device_pcm1);
-
-/* AC97 Controller platform devices */
-
-static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
-{
- return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
-}
-
-static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
-{
- return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
-}
-
-static struct resource s3c64xx_ac97_resource[] = {
- [0] = DEFINE_RES_MEM(S3C64XX_PA_AC97, SZ_256),
- [1] = DEFINE_RES_IRQ(IRQ_AC97),
-};
-
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-};
-
-static u64 s3c64xx_ac97_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s3c64xx_device_ac97 = {
- .name = "samsung-ac97",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c64xx_ac97_resource),
- .resource = s3c64xx_ac97_resource,
- .dev = {
- .platform_data = &s3c_ac97_pdata,
- .dma_mask = &s3c64xx_ac97_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-EXPORT_SYMBOL(s3c64xx_device_ac97);
-
-void __init s3c64xx_ac97_setup_gpio(int num)
-{
- if (num == S3C64XX_AC97_GPD)
- s3c_ac97_pdata.cfg_gpio = s3c64xx_ac97_cfg_gpd;
- else
- s3c_ac97_pdata.cfg_gpio = s3c64xx_ac97_cfg_gpe;
-}
diff --git a/arch/arm/mach-s3c/dev-backlight-s3c64xx.c b/arch/arm/mach-s3c/dev-backlight-s3c64xx.c
deleted file mode 100644
index 65488b61e50c..000000000000
--- a/arch/arm/mach-s3c/dev-backlight-s3c64xx.c
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2011 Samsung Electronics Co., Ltd.
-// http://www.samsung.com
-//
-// Common infrastructure for PWM Backlight for Samsung boards
-
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/pwm_backlight.h>
-
-#include "devs.h"
-#include "gpio-cfg.h"
-
-#include "backlight-s3c64xx.h"
-
-struct samsung_bl_drvdata {
- struct platform_pwm_backlight_data plat_data;
- struct samsung_bl_gpio_info *gpio_info;
-};
-
-static int samsung_bl_init(struct device *dev)
-{
- int ret = 0;
- struct platform_pwm_backlight_data *pdata = dev->platform_data;
- struct samsung_bl_drvdata *drvdata = container_of(pdata,
- struct samsung_bl_drvdata, plat_data);
- struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info;
-
- ret = gpio_request(bl_gpio_info->no, "Backlight");
- if (ret) {
- printk(KERN_ERR "failed to request GPIO for LCD Backlight\n");
- return ret;
- }
-
- /* Configure GPIO pin with specific GPIO function for PWM timer */
- s3c_gpio_cfgpin(bl_gpio_info->no, bl_gpio_info->func);
-
- return 0;
-}
-
-static void samsung_bl_exit(struct device *dev)
-{
- struct platform_pwm_backlight_data *pdata = dev->platform_data;
- struct samsung_bl_drvdata *drvdata = container_of(pdata,
- struct samsung_bl_drvdata, plat_data);
- struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info;
-
- s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT);
- gpio_free(bl_gpio_info->no);
-}
-
-/* Initialize few important fields of platform_pwm_backlight_data
- * structure with default values. These fields can be overridden by
- * board-specific values sent from machine file.
- * For ease of operation, these fields are initialized with values
- * used by most samsung boards.
- * Users has the option of sending info about other parameters
- * for their specific boards
- */
-
-static struct samsung_bl_drvdata samsung_dfl_bl_data __initdata = {
- .plat_data = {
- .max_brightness = 255,
- .dft_brightness = 255,
- .init = samsung_bl_init,
- .exit = samsung_bl_exit,
- },
-};
-
-static struct platform_device samsung_dfl_bl_device __initdata = {
- .name = "pwm-backlight",
-};
-
-/* samsung_bl_set - Set board specific data (if any) provided by user for
- * PWM Backlight control and register specific PWM and backlight device.
- * @gpio_info: structure containing GPIO info for PWM timer
- * @bl_data: structure containing Backlight control data
- */
-void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
- struct platform_pwm_backlight_data *bl_data)
-{
- int ret = 0;
- struct platform_device *samsung_bl_device;
- struct samsung_bl_drvdata *samsung_bl_drvdata;
- struct platform_pwm_backlight_data *samsung_bl_data;
-
- samsung_bl_device = kmemdup(&samsung_dfl_bl_device,
- sizeof(struct platform_device), GFP_KERNEL);
- if (!samsung_bl_device)
- return;
-
- samsung_bl_drvdata = kmemdup(&samsung_dfl_bl_data,
- sizeof(samsung_dfl_bl_data), GFP_KERNEL);
- if (!samsung_bl_drvdata)
- goto err_data;
-
- samsung_bl_device->dev.platform_data = &samsung_bl_drvdata->plat_data;
- samsung_bl_drvdata->gpio_info = gpio_info;
- samsung_bl_data = &samsung_bl_drvdata->plat_data;
-
- /* Copy board specific data provided by user */
- samsung_bl_device->dev.parent = &samsung_device_pwm.dev;
-
- if (bl_data->max_brightness)
- samsung_bl_data->max_brightness = bl_data->max_brightness;
- if (bl_data->dft_brightness)
- samsung_bl_data->dft_brightness = bl_data->dft_brightness;
- if (bl_data->lth_brightness)
- samsung_bl_data->lth_brightness = bl_data->lth_brightness;
- if (bl_data->init)
- samsung_bl_data->init = bl_data->init;
- if (bl_data->notify)
- samsung_bl_data->notify = bl_data->notify;
- if (bl_data->notify_after)
- samsung_bl_data->notify_after = bl_data->notify_after;
- if (bl_data->exit)
- samsung_bl_data->exit = bl_data->exit;
- if (bl_data->check_fb)
- samsung_bl_data->check_fb = bl_data->check_fb;
-
- /* Register the Backlight dev */
- ret = platform_device_register(samsung_bl_device);
- if (ret) {
- printk(KERN_ERR "failed to register backlight device: %d\n", ret);
- goto err_plat_reg2;
- }
-
- return;
-
-err_plat_reg2:
- kfree(samsung_bl_data);
-err_data:
- kfree(samsung_bl_device);
-}
diff --git a/arch/arm/mach-s3c/dev-uart-s3c64xx.c b/arch/arm/mach-s3c/dev-uart-s3c64xx.c
index 8288e8d6c092..f9c947b8971b 100644
--- a/arch/arm/mach-s3c/dev-uart-s3c64xx.c
+++ b/arch/arm/mach-s3c/dev-uart-s3c64xx.c
@@ -16,7 +16,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include "map.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "devs.h"
diff --git a/arch/arm/mach-s3c/devs.c b/arch/arm/mach-s3c/devs.c
index 1e266fc24f9b..8c26d592d2a3 100644
--- a/arch/arm/mach-s3c/devs.c
+++ b/arch/arm/mach-s3c/devs.c
@@ -21,126 +21,34 @@
#include <linux/dma-mapping.h>
#include <linux/fb.h>
#include <linux/gfp.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/onenand.h>
-#include <linux/mtd/partitions.h>
#include <linux/mmc/host.h>
#include <linux/ioport.h>
#include <linux/sizes.h>
-#include <linux/platform_data/s3c-hsudc.h>
#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/dma-s3c24xx.h>
-
-#include <linux/platform_data/media/s5p_hdmi.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "gpio-samsung.h"
#include "gpio-cfg.h"
-#ifdef CONFIG_PLAT_S3C24XX
-#include "regs-s3c2443-clock.h"
-#endif /* CONFIG_PLAT_S3C24XX */
-
#include "cpu.h"
#include "devs.h"
-#include <linux/soc/samsung/s3c-adc.h>
-#include <linux/platform_data/ata-samsung_cf.h>
#include "fb.h"
-#include <linux/platform_data/fb-s3c2410.h>
-#include <linux/platform_data/hwmon-s3c.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include "keypad.h"
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
#include "pwm-core.h"
#include "sdhci.h"
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <linux/platform_data/usb-ohci-s3c2410.h>
#include "usb-phy.h"
#include <linux/platform_data/asoc-s3c.h>
#include <linux/platform_data/spi-s3c64xx.h>
#define samsung_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
-/* AC97 */
-#ifdef CONFIG_CPU_S3C2440
-static struct resource s3c_ac97_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
- [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
-};
-
-struct platform_device s3c_device_ac97 = {
- .name = "samsung-ac97",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_ac97_resource),
- .resource = s3c_ac97_resource,
- .dev = {
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-#endif /* CONFIG_CPU_S3C2440 */
-
-/* ADC */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_adc_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
- [1] = DEFINE_RES_IRQ(IRQ_TC),
- [2] = DEFINE_RES_IRQ(IRQ_ADC),
-};
-
-struct platform_device s3c_device_adc = {
- .name = "s3c24xx-adc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_adc_resource),
- .resource = s3c_adc_resource,
-};
-#endif /* CONFIG_PLAT_S3C24XX */
-
-#if defined(CONFIG_SAMSUNG_DEV_ADC)
-static struct resource s3c_adc_resource[] = {
- [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
- [1] = DEFINE_RES_IRQ(IRQ_ADC),
- [2] = DEFINE_RES_IRQ(IRQ_TC),
-};
-
-struct platform_device s3c_device_adc = {
- .name = "exynos-adc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_adc_resource),
- .resource = s3c_adc_resource,
-};
-#endif /* CONFIG_SAMSUNG_DEV_ADC */
-
-/* Camif Controller */
-
-#ifdef CONFIG_CPU_S3C2440
-static struct resource s3c_camif_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
- [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
- [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
-};
-
-struct platform_device s3c_device_camif = {
- .name = "s3c2440-camif",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_camif_resource),
- .resource = s3c_camif_resource,
- .dev = {
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-#endif /* CONFIG_CPU_S3C2440 */
-
/* FB */
#ifdef CONFIG_S3C_DEV_FB
@@ -169,22 +77,6 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
}
#endif /* CONFIG_S3C_DEV_FB */
-/* HWMON */
-
-#ifdef CONFIG_S3C_DEV_HWMON
-struct platform_device s3c_device_hwmon = {
- .name = "s3c-hwmon",
- .id = -1,
- .dev.parent = &s3c_device_adc.dev,
-};
-
-void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
-{
- s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
- &s3c_device_hwmon);
-}
-#endif /* CONFIG_S3C_DEV_HWMON */
-
/* HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC
@@ -374,220 +266,6 @@ void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
}
#endif /* CONFIG_S3C_DEV_I2C1 */
-#ifdef CONFIG_S3C_DEV_I2C2
-static struct resource s3c_i2c2_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
- [1] = DEFINE_RES_IRQ(IRQ_IIC2),
-};
-
-struct platform_device s3c_device_i2c2 = {
- .name = "s3c2410-i2c",
- .id = 2,
- .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
- .resource = s3c_i2c2_resource,
-};
-
-void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
-{
- struct s3c2410_platform_i2c *npd;
-
- if (!pd) {
- pd = &default_i2c_data;
- pd->bus_num = 2;
- }
-
- npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c2);
-
- if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c2_cfg_gpio;
-}
-#endif /* CONFIG_S3C_DEV_I2C2 */
-
-#ifdef CONFIG_S3C_DEV_I2C3
-static struct resource s3c_i2c3_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
- [1] = DEFINE_RES_IRQ(IRQ_IIC3),
-};
-
-struct platform_device s3c_device_i2c3 = {
- .name = "s3c2440-i2c",
- .id = 3,
- .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
- .resource = s3c_i2c3_resource,
-};
-
-void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
-{
- struct s3c2410_platform_i2c *npd;
-
- if (!pd) {
- pd = &default_i2c_data;
- pd->bus_num = 3;
- }
-
- npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c3);
-
- if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c3_cfg_gpio;
-}
-#endif /*CONFIG_S3C_DEV_I2C3 */
-
-#ifdef CONFIG_S3C_DEV_I2C4
-static struct resource s3c_i2c4_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
- [1] = DEFINE_RES_IRQ(IRQ_IIC4),
-};
-
-struct platform_device s3c_device_i2c4 = {
- .name = "s3c2440-i2c",
- .id = 4,
- .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
- .resource = s3c_i2c4_resource,
-};
-
-void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
-{
- struct s3c2410_platform_i2c *npd;
-
- if (!pd) {
- pd = &default_i2c_data;
- pd->bus_num = 4;
- }
-
- npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c4);
-
- if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c4_cfg_gpio;
-}
-#endif /*CONFIG_S3C_DEV_I2C4 */
-
-#ifdef CONFIG_S3C_DEV_I2C5
-static struct resource s3c_i2c5_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
- [1] = DEFINE_RES_IRQ(IRQ_IIC5),
-};
-
-struct platform_device s3c_device_i2c5 = {
- .name = "s3c2440-i2c",
- .id = 5,
- .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
- .resource = s3c_i2c5_resource,
-};
-
-void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
-{
- struct s3c2410_platform_i2c *npd;
-
- if (!pd) {
- pd = &default_i2c_data;
- pd->bus_num = 5;
- }
-
- npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c5);
-
- if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c5_cfg_gpio;
-}
-#endif /*CONFIG_S3C_DEV_I2C5 */
-
-#ifdef CONFIG_S3C_DEV_I2C6
-static struct resource s3c_i2c6_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
- [1] = DEFINE_RES_IRQ(IRQ_IIC6),
-};
-
-struct platform_device s3c_device_i2c6 = {
- .name = "s3c2440-i2c",
- .id = 6,
- .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
- .resource = s3c_i2c6_resource,
-};
-
-void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
-{
- struct s3c2410_platform_i2c *npd;
-
- if (!pd) {
- pd = &default_i2c_data;
- pd->bus_num = 6;
- }
-
- npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c6);
-
- if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c6_cfg_gpio;
-}
-#endif /* CONFIG_S3C_DEV_I2C6 */
-
-#ifdef CONFIG_S3C_DEV_I2C7
-static struct resource s3c_i2c7_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
- [1] = DEFINE_RES_IRQ(IRQ_IIC7),
-};
-
-struct platform_device s3c_device_i2c7 = {
- .name = "s3c2440-i2c",
- .id = 7,
- .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
- .resource = s3c_i2c7_resource,
-};
-
-void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
-{
- struct s3c2410_platform_i2c *npd;
-
- if (!pd) {
- pd = &default_i2c_data;
- pd->bus_num = 7;
- }
-
- npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c7);
-
- if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c7_cfg_gpio;
-}
-#endif /* CONFIG_S3C_DEV_I2C7 */
-
-/* I2S */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_iis_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
-};
-
-struct platform_device s3c_device_iis = {
- .name = "s3c24xx-iis",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_iis_resource),
- .resource = s3c_iis_resource,
- .dev = {
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-#endif /* CONFIG_PLAT_S3C24XX */
-
-/* IDE CFCON */
-
-#ifdef CONFIG_SAMSUNG_DEV_IDE
-static struct resource s3c_cfcon_resource[] = {
- [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
- [1] = DEFINE_RES_IRQ(IRQ_CFCON),
-};
-
-struct platform_device s3c_device_cfcon = {
- .id = 0,
- .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
- .resource = s3c_cfcon_resource,
-};
-
-void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
-{
- s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
- &s3c_device_cfcon);
-}
-#endif /* CONFIG_SAMSUNG_DEV_IDE */
-
/* KEYPAD */
#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
@@ -614,175 +292,6 @@ void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
}
#endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
-/* LCD Controller */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_lcd_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
- [1] = DEFINE_RES_IRQ(IRQ_LCD),
-};
-
-struct platform_device s3c_device_lcd = {
- .name = "s3c2410-lcd",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_lcd_resource),
- .resource = s3c_lcd_resource,
- .dev = {
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-
-void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
-{
- struct s3c2410fb_mach_info *npd;
-
- npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
- if (npd) {
- npd->displays = kmemdup(pd->displays,
- sizeof(struct s3c2410fb_display) * npd->num_displays,
- GFP_KERNEL);
- if (!npd->displays)
- printk(KERN_ERR "no memory for LCD display data\n");
- } else {
- printk(KERN_ERR "no memory for LCD platform data\n");
- }
-}
-#endif /* CONFIG_PLAT_S3C24XX */
-
-/* NAND */
-
-#ifdef CONFIG_S3C_DEV_NAND
-static struct resource s3c_nand_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
-};
-
-struct platform_device s3c_device_nand = {
- .name = "s3c2410-nand",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_nand_resource),
- .resource = s3c_nand_resource,
-};
-
-/*
- * s3c_nand_copy_set() - copy nand set data
- * @set: The new structure, directly copied from the old.
- *
- * Copy all the fields from the NAND set field from what is probably __initdata
- * to new kernel memory. The code returns 0 if the copy happened correctly or
- * an error code for the calling function to display.
- *
- * Note, we currently do not try and look to see if we've already copied the
- * data in a previous set.
- */
-static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
-{
- void *ptr;
- int size;
-
- size = sizeof(struct mtd_partition) * set->nr_partitions;
- if (size) {
- ptr = kmemdup(set->partitions, size, GFP_KERNEL);
- set->partitions = ptr;
-
- if (!ptr)
- return -ENOMEM;
- }
-
- if (set->nr_map && set->nr_chips) {
- size = sizeof(int) * set->nr_chips;
- ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
- set->nr_map = ptr;
-
- if (!ptr)
- return -ENOMEM;
- }
-
- return 0;
-}
-
-void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
-{
- struct s3c2410_platform_nand *npd;
- int size;
- int ret;
-
- /* note, if we get a failure in allocation, we simply drop out of the
- * function. If there is so little memory available at initialisation
- * time then there is little chance the system is going to run.
- */
-
- npd = s3c_set_platdata(nand, sizeof(*npd), &s3c_device_nand);
- if (!npd)
- return;
-
- /* now see if we need to copy any of the nand set data */
-
- size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
- if (size) {
- struct s3c2410_nand_set *from = npd->sets;
- struct s3c2410_nand_set *to;
- int i;
-
- to = kmemdup(from, size, GFP_KERNEL);
- npd->sets = to; /* set, even if we failed */
-
- if (!to) {
- printk(KERN_ERR "%s: no memory for sets\n", __func__);
- return;
- }
-
- for (i = 0; i < npd->nr_sets; i++) {
- ret = s3c_nand_copy_set(to);
- if (ret) {
- printk(KERN_ERR "%s: failed to copy set %d\n",
- __func__, i);
- return;
- }
- to++;
- }
- }
-}
-#endif /* CONFIG_S3C_DEV_NAND */
-
-/* ONENAND */
-
-#ifdef CONFIG_S3C_DEV_ONENAND
-static struct resource s3c_onenand_resources[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
- [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
- [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
-};
-
-struct platform_device s3c_device_onenand = {
- .name = "samsung-onenand",
- .id = 0,
- .num_resources = ARRAY_SIZE(s3c_onenand_resources),
- .resource = s3c_onenand_resources,
-};
-#endif /* CONFIG_S3C_DEV_ONENAND */
-
-#ifdef CONFIG_S3C64XX_DEV_ONENAND1
-static struct resource s3c64xx_onenand1_resources[] = {
- [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
- [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
- [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
-};
-
-struct platform_device s3c64xx_device_onenand1 = {
- .name = "samsung-onenand",
- .id = 1,
- .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
- .resource = s3c64xx_onenand1_resources,
-};
-
-void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
-{
- s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
- &s3c64xx_device_onenand1);
-}
-#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
-
/* PWM Timer */
#ifdef CONFIG_SAMSUNG_DEV_PWM
@@ -803,162 +312,6 @@ void __init samsung_pwm_set_platdata(struct samsung_pwm_variant *pd)
}
#endif /* CONFIG_SAMSUNG_DEV_PWM */
-/* RTC */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_rtc_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
- [1] = DEFINE_RES_IRQ(IRQ_RTC),
- [2] = DEFINE_RES_IRQ(IRQ_TICK),
-};
-
-struct platform_device s3c_device_rtc = {
- .name = "s3c2410-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_rtc_resource),
- .resource = s3c_rtc_resource,
-};
-#endif /* CONFIG_PLAT_S3C24XX */
-
-#ifdef CONFIG_S3C_DEV_RTC
-static struct resource s3c_rtc_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
- [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
- [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
-};
-
-struct platform_device s3c_device_rtc = {
- .name = "s3c64xx-rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_rtc_resource),
- .resource = s3c_rtc_resource,
-};
-#endif /* CONFIG_S3C_DEV_RTC */
-
-/* SDI */
-
-#ifdef CONFIG_PLAT_S3C24XX
-void s3c24xx_mci_def_set_power(unsigned char power_mode, unsigned short vdd)
-{
- switch (power_mode) {
- case MMC_POWER_ON:
- case MMC_POWER_UP:
- /* Configure GPE5...GPE10 pins in SD mode */
- s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
- S3C_GPIO_PULL_NONE);
- break;
-
- case MMC_POWER_OFF:
- default:
- gpio_direction_output(S3C2410_GPE(5), 0);
- break;
- }
-}
-
-static struct resource s3c_sdi_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
- [1] = DEFINE_RES_IRQ(IRQ_SDI),
-};
-
-static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
- /* This is currently here to avoid a number of if (host->pdata)
- * checks. Any zero fields to ensure reasonable defaults are picked. */
- .no_wprotect = 1,
- .no_detect = 1,
- .set_power = s3c24xx_mci_def_set_power,
-};
-
-struct platform_device s3c_device_sdi = {
- .name = "s3c2410-sdi",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_sdi_resource),
- .resource = s3c_sdi_resource,
- .dev.platform_data = &s3cmci_def_pdata,
-};
-
-void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
-{
- s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
- &s3c_device_sdi);
-}
-#endif /* CONFIG_PLAT_S3C24XX */
-
-/* SPI */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_spi0_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
- [1] = DEFINE_RES_IRQ(IRQ_SPI0),
-};
-
-struct platform_device s3c_device_spi0 = {
- .name = "s3c2410-spi",
- .id = 0,
- .num_resources = ARRAY_SIZE(s3c_spi0_resource),
- .resource = s3c_spi0_resource,
- .dev = {
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-
-static struct resource s3c_spi1_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
- [1] = DEFINE_RES_IRQ(IRQ_SPI1),
-};
-
-struct platform_device s3c_device_spi1 = {
- .name = "s3c2410-spi",
- .id = 1,
- .num_resources = ARRAY_SIZE(s3c_spi1_resource),
- .resource = s3c_spi1_resource,
- .dev = {
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- }
-};
-#endif /* CONFIG_PLAT_S3C24XX */
-
-/* Touchscreen */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_ts_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
- [1] = DEFINE_RES_IRQ(IRQ_TC),
-};
-
-struct platform_device s3c_device_ts = {
- .name = "s3c2410-ts",
- .id = -1,
- .dev.parent = &s3c_device_adc.dev,
- .num_resources = ARRAY_SIZE(s3c_ts_resource),
- .resource = s3c_ts_resource,
-};
-
-void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
-{
- s3c_set_platdata(hard_s3c2410ts_info,
- sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
-}
-#endif /* CONFIG_PLAT_S3C24XX */
-
-#ifdef CONFIG_SAMSUNG_DEV_TS
-static struct s3c2410_ts_mach_info default_ts_data __initdata = {
- .delay = 10000,
- .presc = 49,
- .oversampling_shift = 2,
-};
-
-void __init s3c64xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
-{
- if (!pd)
- pd = &default_ts_data;
-
- s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
- &s3c_device_adc);
-}
-#endif /* CONFIG_SAMSUNG_DEV_TS */
-
/* USB */
#ifdef CONFIG_S3C_DEV_USB_HOST
@@ -977,44 +330,8 @@ struct platform_device s3c_device_ohci = {
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
-
-/*
- * s3c_ohci_set_platdata - initialise OHCI device platform data
- * @info: The platform data.
- *
- * This call copies the @info passed in and sets the device .platform_data
- * field to that copy. The @info is copied so that the original can be marked
- * __initdata.
- */
-
-void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
-{
- s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
- &s3c_device_ohci);
-}
#endif /* CONFIG_S3C_DEV_USB_HOST */
-/* USB Device (Gadget) */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_usbgadget_resource[] = {
- [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
- [1] = DEFINE_RES_IRQ(IRQ_USBD),
-};
-
-struct platform_device s3c_device_usbgadget = {
- .name = "s3c2410-usbgadget",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
- .resource = s3c_usbgadget_resource,
-};
-
-void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
-{
- s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
-}
-#endif /* CONFIG_PLAT_S3C24XX */
-
/* USB HSOTG */
#ifdef CONFIG_S3C_DEV_USB_HSOTG
@@ -1047,49 +364,6 @@ void __init dwc2_hsotg_set_platdata(struct dwc2_hsotg_plat *pd)
}
#endif /* CONFIG_S3C_DEV_USB_HSOTG */
-/* USB High Spped 2.0 Device (Gadget) */
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct resource s3c_hsudc_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
- [1] = DEFINE_RES_IRQ(IRQ_USBD),
-};
-
-struct platform_device s3c_device_usb_hsudc = {
- .name = "s3c-hsudc",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
- .resource = s3c_hsudc_resource,
- .dev = {
- .dma_mask = &samsung_device_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
-{
- s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
- pd->phy_init = s3c_hsudc_init_phy;
- pd->phy_uninit = s3c_hsudc_uninit_phy;
-}
-#endif /* CONFIG_PLAT_S3C24XX */
-
-/* WDT */
-
-#ifdef CONFIG_S3C_DEV_WDT
-static struct resource s3c_wdt_resource[] = {
- [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
- [1] = DEFINE_RES_IRQ(IRQ_WDT),
-};
-
-struct platform_device s3c_device_wdt = {
- .name = "s3c2410-wdt",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_wdt_resource),
- .resource = s3c_wdt_resource,
-};
-#endif /* CONFIG_S3C_DEV_WDT */
-
#ifdef CONFIG_S3C64XX_DEV_SPI0
static struct resource s3c64xx_spi0_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
diff --git a/arch/arm/mach-s3c/devs.h b/arch/arm/mach-s3c/devs.h
index 02b0c5750572..21c00786c264 100644
--- a/arch/arm/mach-s3c/devs.h
+++ b/arch/arm/mach-s3c/devs.h
@@ -25,62 +25,23 @@ extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
extern struct platform_device *s3c24xx_uart_devs[];
extern struct platform_device *s3c24xx_uart_src[];
-extern struct platform_device s3c64xx_device_ac97;
extern struct platform_device s3c64xx_device_iis0;
extern struct platform_device s3c64xx_device_iis1;
-extern struct platform_device s3c64xx_device_iisv4;
-extern struct platform_device s3c64xx_device_onenand1;
-extern struct platform_device s3c64xx_device_pcm0;
-extern struct platform_device s3c64xx_device_pcm1;
extern struct platform_device s3c64xx_device_spi0;
-extern struct platform_device s3c64xx_device_spi1;
-extern struct platform_device s3c64xx_device_spi2;
-extern struct platform_device s3c_device_adc;
-extern struct platform_device s3c_device_cfcon;
extern struct platform_device s3c_device_fb;
-extern struct platform_device s3c_device_hwmon;
extern struct platform_device s3c_device_hsmmc0;
extern struct platform_device s3c_device_hsmmc1;
extern struct platform_device s3c_device_hsmmc2;
extern struct platform_device s3c_device_hsmmc3;
extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1;
-extern struct platform_device s3c_device_i2c2;
-extern struct platform_device s3c_device_i2c3;
-extern struct platform_device s3c_device_i2c4;
-extern struct platform_device s3c_device_i2c5;
-extern struct platform_device s3c_device_i2c6;
-extern struct platform_device s3c_device_i2c7;
-extern struct platform_device s3c_device_iis;
-extern struct platform_device s3c_device_lcd;
-extern struct platform_device s3c_device_nand;
extern struct platform_device s3c_device_ohci;
-extern struct platform_device s3c_device_onenand;
-extern struct platform_device s3c_device_rtc;
-extern struct platform_device s3c_device_sdi;
-extern struct platform_device s3c_device_spi0;
-extern struct platform_device s3c_device_spi1;
-extern struct platform_device s3c_device_ts;
-extern struct platform_device s3c_device_timer[];
-extern struct platform_device s3c_device_usbgadget;
extern struct platform_device s3c_device_usb_hsotg;
-extern struct platform_device s3c_device_usb_hsudc;
-extern struct platform_device s3c_device_wdt;
-extern struct platform_device samsung_asoc_idma;
extern struct platform_device samsung_device_keypad;
extern struct platform_device samsung_device_pwm;
-/* s3c2440 specific devices */
-
-#ifdef CONFIG_CPU_S3C2440
-
-extern struct platform_device s3c_device_camif;
-extern struct platform_device s3c_device_ac97;
-
-#endif
-
/**
* s3c_set_platdata() - helper for setting platform data
* @pd: The default platform data for this device.
diff --git a/arch/arm/mach-s3c/dma-s3c24xx.h b/arch/arm/mach-s3c/dma-s3c24xx.h
deleted file mode 100644
index 25fc9c258fc1..000000000000
--- a/arch/arm/mach-s3c/dma-s3c24xx.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2003-2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C24XX DMA support
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H __FILE__
-
-#include <linux/device.h>
-
-/* We use `virtual` dma channels to hide the fact we have only a limited
- * number of DMA channels, and not of all of them (dependent on the device)
- * can be attached to any DMA source. We therefore let the DMA core handle
- * the allocation of hardware channels to clients.
-*/
-
-enum dma_ch {
- DMACH_XD0 = 0,
- DMACH_XD1,
- DMACH_SDI,
- DMACH_SPI0,
- DMACH_SPI1,
- DMACH_UART0,
- DMACH_UART1,
- DMACH_UART2,
- DMACH_TIMER,
- DMACH_I2S_IN,
- DMACH_I2S_OUT,
- DMACH_PCM_IN,
- DMACH_PCM_OUT,
- DMACH_MIC_IN,
- DMACH_USB_EP1,
- DMACH_USB_EP2,
- DMACH_USB_EP3,
- DMACH_USB_EP4,
- DMACH_UART0_SRC2, /* s3c2412 second uart sources */
- DMACH_UART1_SRC2,
- DMACH_UART2_SRC2,
- DMACH_UART3, /* s3c2443 has extra uart */
- DMACH_UART3_SRC2,
- DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
- DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
- DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
- DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
- DMACH_MAX, /* the end entry */
-};
-
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c/dma-s3c64xx.h b/arch/arm/mach-s3c/dma-s3c64xx.h
deleted file mode 100644
index 40ca8de21096..000000000000
--- a/arch/arm/mach-s3c/dma-s3c64xx.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C6400 - DMA support
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H __FILE__
-
-#define S3C64XX_DMA_CHAN(name) ((unsigned long)(name))
-
-/* DMA0/SDMA0 */
-#define DMACH_UART0 "uart0_tx"
-#define DMACH_UART0_SRC2 "uart0_rx"
-#define DMACH_UART1 "uart1_tx"
-#define DMACH_UART1_SRC2 "uart1_rx"
-#define DMACH_UART2 "uart2_tx"
-#define DMACH_UART2_SRC2 "uart2_rx"
-#define DMACH_UART3 "uart3_tx"
-#define DMACH_UART3_SRC2 "uart3_rx"
-#define DMACH_PCM0_TX "pcm0_tx"
-#define DMACH_PCM0_RX "pcm0_rx"
-#define DMACH_I2S0_OUT "i2s0_tx"
-#define DMACH_I2S0_IN "i2s0_rx"
-#define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx")
-#define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx")
-#define DMACH_HSI_I2SV40_TX "i2s2_tx"
-#define DMACH_HSI_I2SV40_RX "i2s2_rx"
-
-/* DMA1/SDMA1 */
-#define DMACH_PCM1_TX "pcm1_tx"
-#define DMACH_PCM1_RX "pcm1_rx"
-#define DMACH_I2S1_OUT "i2s1_tx"
-#define DMACH_I2S1_IN "i2s1_rx"
-#define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx")
-#define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx")
-#define DMACH_AC97_PCMOUT "ac97_out"
-#define DMACH_AC97_PCMIN "ac97_in"
-#define DMACH_AC97_MICIN "ac97_mic"
-#define DMACH_PWM "pwm"
-#define DMACH_IRDA "irda"
-#define DMACH_EXTERNAL "external"
-#define DMACH_SECURITY_RX "sec_rx"
-#define DMACH_SECURITY_TX "sec_tx"
-
-enum dma_ch {
- DMACH_MAX = 32
-};
-
-#include <linux/amba/pl08x.h>
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c/dma.h b/arch/arm/mach-s3c/dma.h
deleted file mode 100644
index 59a4578c5f00..000000000000
--- a/arch/arm/mach-s3c/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifdef CONFIG_ARCH_S3C24XX
-#include "dma-s3c24xx.h"
-#endif
-
-#ifdef CONFIG_ARCH_S3C64XX
-#include "dma-s3c64xx.h"
-#endif
diff --git a/arch/arm/mach-s3c/fb-core-s3c24xx.h b/arch/arm/mach-s3c/fb-core-s3c24xx.h
deleted file mode 100644
index 0e07f3ba4aef..000000000000
--- a/arch/arm/mach-s3c/fb-core-s3c24xx.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2010 Samsung Electronics Co., Ltd.
- * Pawel Osciak <p.osciak@samsung.com>
- *
- * Samsung framebuffer driver core functions
- */
-#ifndef __ASM_PLAT_FB_CORE_S3C24XX_H
-#define __ASM_PLAT_FB_CORE_S3C24XX_H __FILE__
-
-/*
- * These functions are only for use with the core support code, such as
- * the CPU-specific initialization code.
- */
-
-/* Re-define device name depending on support. */
-static inline void s3c_fb_setname(char *name)
-{
-#ifdef CONFIG_S3C_DEV_FB
- s3c_device_fb.name = name;
-#endif
-}
-
-#endif /* __ASM_PLAT_FB_CORE_S3C24XX_H */
diff --git a/arch/arm/mach-s3c/gpio-cfg-helpers.h b/arch/arm/mach-s3c/gpio-cfg-helpers.h
index db0c56f5ca15..9d6f6319ae3e 100644
--- a/arch/arm/mach-s3c/gpio-cfg-helpers.h
+++ b/arch/arm/mach-s3c/gpio-cfg-helpers.h
@@ -26,134 +26,10 @@ static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip,
return (chip->config->set_config)(chip, off, config);
}
-static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip,
- unsigned int off)
-{
- return (chip->config->get_config)(chip, off);
-}
-
static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip,
unsigned int off, samsung_gpio_pull_t pull)
{
return (chip->config->set_pull)(chip, off, pull);
}
-static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip,
- unsigned int off)
-{
- return chip->config->get_pull(chip, off);
-}
-
-/* Pull-{up,down} resistor controls.
- *
- * S3C2410,S3C2440 = Pull-UP,
- * S3C2412,S3C2413 = Pull-Down
- * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
- * S3C2443 = Pull-Both [not same as S3C6400]
- */
-
-/**
- * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @param: pull: The pull mode being requested.
- *
- * This is a helper function for the case where we have GPIOs with one
- * bit configuring the presence of a pull-up resistor.
- */
-extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull);
-
-/**
- * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none
- * @chip: The gpio chip that is being configured
- * @off: The offset for the GPIO being configured
- * @param: pull: The pull mode being requested
- *
- * This is a helper function for the case where we have GPIOs with one
- * bit configuring the presence of a pull-down resistor.
- */
-extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull);
-
-/**
- * samsung_gpio_setpull_upown() - Pull configuration for choice of up,
- * down or none
- *
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @param: pull: The pull mode being requested.
- *
- * This is a helper function for the case where we have GPIOs with two
- * bits configuring the presence of a pull resistor, in the following
- * order:
- * 00 = No pull resistor connected
- * 01 = Pull-up resistor connected
- * 10 = Pull-down resistor connected
- */
-extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull);
-
-/**
- * samsung_gpio_getpull_updown() - Get configuration for choice of up,
- * down or none
- *
- * @chip: The gpio chip that the GPIO pin belongs to
- * @off: The offset to the pin to get the configuration of.
- *
- * This helper function reads the state of the pull-{up,down} resistor
- * for the given GPIO in the same case as samsung_gpio_setpull_upown.
-*/
-extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
- unsigned int off);
-
-/**
- * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none
- * @chip: The gpio chip that the GPIO pin belongs to
- * @off: The offset to the pin to get the configuration of.
- *
- * This helper function reads the state of the pull-up resistor for the
- * given GPIO in the same case as s3c24xx_gpio_setpull_1up.
-*/
-extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
- unsigned int off);
-
-/**
- * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none
- * @chip: The gpio chip that the GPIO pin belongs to
- * @off: The offset to the pin to get the configuration of.
- *
- * This helper function reads the state of the pull-down resistor for the
- * given GPIO in the same case as s3c24xx_gpio_setpull_1down.
-*/
-extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
- unsigned int off);
-
-/**
- * s3c2443_gpio_setpull() - Pull configuration for s3c2443.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @param: pull: The pull mode being requested.
- *
- * This is a helper function for the case where we have GPIOs with two
- * bits configuring the presence of a pull resistor, in the following
- * order:
- * 00 = Pull-up resistor connected
- * 10 = Pull-down resistor connected
- * x1 = No pull up resistor
- */
-extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull);
-
-/**
- * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors
- * @chip: The gpio chip that the GPIO pin belongs to.
- * @off: The offset to the pin to get the configuration of.
- *
- * This helper function reads the state of the pull-{up,down} resistor for the
- * given GPIO in the same case as samsung_gpio_setpull_upown.
-*/
-extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
- unsigned int off);
-
#endif /* __PLAT_GPIO_CFG_HELPERS_H */
diff --git a/arch/arm/mach-s3c/gpio-cfg.h b/arch/arm/mach-s3c/gpio-cfg.h
index 469c220e092b..2dfb0561001e 100644
--- a/arch/arm/mach-s3c/gpio-cfg.h
+++ b/arch/arm/mach-s3c/gpio-cfg.h
@@ -95,17 +95,6 @@ struct samsung_gpio_cfg {
extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
/**
- * s3c_gpio_getcfg - Read the current function for a GPIO pin
- * @pin: The pin to read the configuration value for.
- *
- * Read the configuration state of the given @pin, returning a value that
- * could be passed back to s3c_gpio_cfgpin().
- *
- * @sa s3c_gpio_cfgpin
- */
-extern unsigned s3c_gpio_getcfg(unsigned int pin);
-
-/**
* s3c_gpio_cfgpin_range() - Change the GPIO function for configuring pin range
* @start: The pin number to start at
* @nr: The number of pins to configure from @start.
@@ -142,14 +131,6 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
*/
extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull);
-/**
- * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
- * @pin: The pin number to get the settings for
- *
- * Read the pull resistor value for the specified pin.
-*/
-extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
-
/* configure `all` aspects of an gpio */
/**
diff --git a/arch/arm/mach-s3c/gpio-core.h b/arch/arm/mach-s3c/gpio-core.h
index b361c8c0d669..6801c85fb9da 100644
--- a/arch/arm/mach-s3c/gpio-core.h
+++ b/arch/arm/mach-s3c/gpio-core.h
@@ -93,9 +93,6 @@ static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc)
*/
extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset);
-/* exported for core SoC support to change */
-extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default;
-
#ifdef CONFIG_S3C_GPIO_TRACK
extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
diff --git a/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h b/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h
deleted file mode 100644
index c29fdc95f883..000000000000
--- a/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2008 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - GPIO lib support
- */
-
-/* some boards require extra gpio capacity to support external
- * devices that need GPIO.
- */
-
-#ifndef GPIO_SAMSUNG_S3C24XX_H
-#define GPIO_SAMSUNG_S3C24XX_H
-
-#include "map.h"
-
-/*
- * GPIO sizes for various SoCs:
- *
- * 2410 2412 2440 2443 2416
- * 2442
- * ---- ---- ---- ---- ----
- * A 23 22 25 16 27
- * B 11 11 11 11 11
- * C 16 16 16 16 16
- * D 16 16 16 16 16
- * E 16 16 16 16 16
- * F 8 8 8 8 8
- * G 16 16 16 16 8
- * H 11 11 11 15 15
- * J -- -- 13 16 --
- * K -- -- -- -- 16
- * L -- -- -- 15 14
- * M -- -- -- 2 2
- */
-
-/* GPIO bank sizes */
-
-#define S3C2410_GPIO_A_NR (32)
-#define S3C2410_GPIO_B_NR (32)
-#define S3C2410_GPIO_C_NR (32)
-#define S3C2410_GPIO_D_NR (32)
-#define S3C2410_GPIO_E_NR (32)
-#define S3C2410_GPIO_F_NR (32)
-#define S3C2410_GPIO_G_NR (32)
-#define S3C2410_GPIO_H_NR (32)
-#define S3C2410_GPIO_J_NR (32) /* technically 16. */
-#define S3C2410_GPIO_K_NR (32) /* technically 16. */
-#define S3C2410_GPIO_L_NR (32) /* technically 15. */
-#define S3C2410_GPIO_M_NR (32) /* technically 2. */
-
-#if CONFIG_S3C_GPIO_SPACE != 0
-#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
-#endif
-
-#define S3C2410_GPIO_NEXT(__gpio) \
- ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
-
-#ifndef __ASSEMBLY__
-
-enum s3c_gpio_number {
- S3C2410_GPIO_A_START = 0,
- S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
- S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
- S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
- S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
- S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
- S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
- S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
- S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
- S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
- S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
- S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
-};
-
-#endif /* __ASSEMBLY__ */
-
-/* S3C2410 GPIO number definitions. */
-
-#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
-#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
-#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
-#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
-#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
-#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
-#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
-#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
-#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
-#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
-#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
-#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
-
-#ifdef CONFIG_CPU_S3C244X
-#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
-#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
-#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
-#else
-#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
-#endif
-
-#endif /* GPIO_SAMSUNG_S3C24XX_H */
diff --git a/arch/arm/mach-s3c/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c
index fda2c01f5a08..87daaa09e2c3 100644
--- a/arch/arm/mach-s3c/gpio-samsung.c
+++ b/arch/arm/mach-s3c/gpio-samsung.c
@@ -26,7 +26,7 @@
#include <asm/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
@@ -35,10 +35,9 @@
#include "gpio-core.h"
#include "gpio-cfg.h"
#include "gpio-cfg-helpers.h"
-#include "hardware-s3c24xx.h"
#include "pm.h"
-int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
+static int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
unsigned int off, samsung_gpio_pull_t pull)
{
void __iomem *reg = chip->base + 0x08;
@@ -53,7 +52,7 @@ int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
return 0;
}
-samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
+static samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
unsigned int off)
{
void __iomem *reg = chip->base + 0x08;
@@ -66,113 +65,6 @@ samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
return (__force samsung_gpio_pull_t)pup;
}
-int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull)
-{
- switch (pull) {
- case S3C_GPIO_PULL_NONE:
- pull = 0x01;
- break;
- case S3C_GPIO_PULL_UP:
- pull = 0x00;
- break;
- case S3C_GPIO_PULL_DOWN:
- pull = 0x02;
- break;
- }
- return samsung_gpio_setpull_updown(chip, off, pull);
-}
-
-samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
- unsigned int off)
-{
- samsung_gpio_pull_t pull;
-
- pull = samsung_gpio_getpull_updown(chip, off);
-
- switch (pull) {
- case 0x00:
- pull = S3C_GPIO_PULL_UP;
- break;
- case 0x01:
- case 0x03:
- pull = S3C_GPIO_PULL_NONE;
- break;
- case 0x02:
- pull = S3C_GPIO_PULL_DOWN;
- break;
- }
-
- return pull;
-}
-
-static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull,
- samsung_gpio_pull_t updown)
-{
- void __iomem *reg = chip->base + 0x08;
- u32 pup = __raw_readl(reg);
-
- if (pull == updown)
- pup &= ~(1 << off);
- else if (pull == S3C_GPIO_PULL_NONE)
- pup |= (1 << off);
- else
- return -EINVAL;
-
- __raw_writel(pup, reg);
- return 0;
-}
-
-static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
- unsigned int off,
- samsung_gpio_pull_t updown)
-{
- void __iomem *reg = chip->base + 0x08;
- u32 pup = __raw_readl(reg);
-
- pup &= (1 << off);
- return pup ? S3C_GPIO_PULL_NONE : updown;
-}
-
-samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
- unsigned int off)
-{
- return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
-}
-
-int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull)
-{
- return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
-}
-
-samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
- unsigned int off)
-{
- return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
-}
-
-int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
- unsigned int off, samsung_gpio_pull_t pull)
-{
- return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
-}
-
-/*
- * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register
- * has two bits of configuration per gpio, which have the following
- * functions:
- * 00 = input
- * 01 = output
- * 1x = special function
- */
-
static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
@@ -289,70 +181,6 @@ static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
return S3C_GPIO_SPECIAL(con);
}
-#ifdef CONFIG_PLAT_S3C24XX
-/*
- * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register
- * has one bit of configuration for the gpio, where setting the bit
- * means the pin is in special function mode and unset means output.
- */
-
-static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
- unsigned int off, unsigned int cfg)
-{
- void __iomem *reg = chip->base;
- unsigned int shift = off;
- u32 con;
-
- if (samsung_gpio_is_cfg_special(cfg)) {
- cfg &= 0xf;
-
- /* Map output to 0, and SFN2 to 1 */
- cfg -= 1;
- if (cfg > 1)
- return -EINVAL;
-
- cfg <<= shift;
- }
-
- con = __raw_readl(reg);
- con &= ~(0x1 << shift);
- con |= cfg;
- __raw_writel(con, reg);
-
- return 0;
-}
-
-/*
- * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- *
- * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
- * GPIO configuration value.
- *
- * @sa samsung_gpio_getcfg_2bit
- * @sa samsung_gpio_getcfg_4bit
- */
-
-static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
- unsigned int off)
-{
- u32 con;
-
- con = __raw_readl(chip->base);
- con >>= off;
- con &= 1;
- con++;
-
- return S3C_GPIO_SFN(con);
-}
-#endif
-
static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
int nr_chips)
{
@@ -368,18 +196,6 @@ static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
}
}
-struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
- .set_config = samsung_gpio_setcfg_2bit,
- .get_config = samsung_gpio_getcfg_2bit,
-};
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
- .set_config = s3c24xx_gpio_setcfg_abank,
- .get_config = s3c24xx_gpio_getcfg_abank,
-};
-#endif
-
static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
[0] = {
.cfg_eint = 0x0,
@@ -614,44 +430,6 @@ static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
return 0;
}
-#ifdef CONFIG_PLAT_S3C24XX
-/* The next set of routines are for the case of s3c24xx bank a */
-
-static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
-{
- return -EINVAL;
-}
-
-static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
- void __iomem *base = ourchip->base;
- unsigned long flags;
- unsigned long dat;
- unsigned long con;
-
- local_irq_save(flags);
-
- con = __raw_readl(base + 0x00);
- dat = __raw_readl(base + 0x04);
-
- dat &= ~(1 << offset);
- if (value)
- dat |= 1 << offset;
-
- __raw_writel(dat, base + 0x04);
-
- con &= ~(1 << offset);
-
- __raw_writel(con, base + 0x00);
- __raw_writel(dat, base + 0x04);
-
- local_irq_restore(flags);
- return 0;
-}
-#endif
-
static void samsung_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
@@ -756,33 +534,6 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
s3c_gpiolib_track(chip);
}
-static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
- int nr_chips, void __iomem *base)
-{
- int i;
- struct gpio_chip *gc = &chip->chip;
-
- for (i = 0 ; i < nr_chips; i++, chip++) {
- /* skip banks not present on SoC */
- if (chip->chip.base >= S3C_GPIO_END)
- continue;
-
- if (!chip->config)
- chip->config = &s3c24xx_gpiocfg_default;
- if (!chip->pm)
- chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
- if ((base != NULL) && (chip->base == NULL))
- chip->base = base + ((i) * 0x10);
-
- if (!gc->direction_input)
- gc->direction_input = samsung_gpiolib_2bit_input;
- if (!gc->direction_output)
- gc->direction_output = samsung_gpiolib_2bit_output;
-
- samsung_gpiolib_add(chip);
- }
-}
-
static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
int nr_chips, void __iomem *base,
unsigned int offset)
@@ -865,24 +616,6 @@ int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
return samsung_chip->irq_base + offset;
}
-#ifdef CONFIG_PLAT_S3C24XX
-static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
-{
- if (offset < 4) {
- if (soc_is_s3c2412())
- return IRQ_EINT0_2412 + offset;
- else
- return IRQ_EINT0 + offset;
- }
-
- if (offset < 8)
- return IRQ_EINT4 + offset - 4;
-
- return -EINVAL;
-}
-#endif
-
-#ifdef CONFIG_ARCH_S3C64XX
static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
{
return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
@@ -892,109 +625,6 @@ static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
{
return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
}
-#endif
-
-struct samsung_gpio_chip s3c24xx_gpios[] = {
-#ifdef CONFIG_PLAT_S3C24XX
- {
- .config = &s3c24xx_gpiocfg_banka,
- .chip = {
- .base = S3C2410_GPA(0),
- .owner = THIS_MODULE,
- .label = "GPIOA",
- .ngpio = 27,
- .direction_input = s3c24xx_gpiolib_banka_input,
- .direction_output = s3c24xx_gpiolib_banka_output,
- },
- }, {
- .chip = {
- .base = S3C2410_GPB(0),
- .owner = THIS_MODULE,
- .label = "GPIOB",
- .ngpio = 11,
- },
- }, {
- .chip = {
- .base = S3C2410_GPC(0),
- .owner = THIS_MODULE,
- .label = "GPIOC",
- .ngpio = 16,
- },
- }, {
- .chip = {
- .base = S3C2410_GPD(0),
- .owner = THIS_MODULE,
- .label = "GPIOD",
- .ngpio = 16,
- },
- }, {
- .chip = {
- .base = S3C2410_GPE(0),
- .label = "GPIOE",
- .owner = THIS_MODULE,
- .ngpio = 16,
- },
- }, {
- .chip = {
- .base = S3C2410_GPF(0),
- .owner = THIS_MODULE,
- .label = "GPIOF",
- .ngpio = 8,
- .to_irq = s3c24xx_gpiolib_fbank_to_irq,
- },
- }, {
- .irq_base = IRQ_EINT8,
- .chip = {
- .base = S3C2410_GPG(0),
- .owner = THIS_MODULE,
- .label = "GPIOG",
- .ngpio = 16,
- .to_irq = samsung_gpiolib_to_irq,
- },
- }, {
- .chip = {
- .base = S3C2410_GPH(0),
- .owner = THIS_MODULE,
- .label = "GPIOH",
- .ngpio = 15,
- },
- },
- /* GPIOS for the S3C2443 and later devices. */
- {
- .base = S3C2440_GPJCON,
- .chip = {
- .base = S3C2410_GPJ(0),
- .owner = THIS_MODULE,
- .label = "GPIOJ",
- .ngpio = 16,
- },
- }, {
- .base = S3C2443_GPKCON,
- .chip = {
- .base = S3C2410_GPK(0),
- .owner = THIS_MODULE,
- .label = "GPIOK",
- .ngpio = 16,
- },
- }, {
- .base = S3C2443_GPLCON,
- .chip = {
- .base = S3C2410_GPL(0),
- .owner = THIS_MODULE,
- .label = "GPIOL",
- .ngpio = 15,
- },
- }, {
- .base = S3C2443_GPMCON,
- .chip = {
- .base = S3C2410_GPM(0),
- .owner = THIS_MODULE,
- .label = "GPIOM",
- .ngpio = 2,
- },
- },
-#endif
-};
/*
* GPIO bank summary:
@@ -1023,7 +653,6 @@ struct samsung_gpio_chip s3c24xx_gpios[] = {
*/
static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
-#ifdef CONFIG_ARCH_S3C64XX
{
.chip = {
.base = S3C64XX_GPA(0),
@@ -1072,11 +701,9 @@ static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
.to_irq = s3c64xx_gpiolib_mbank_to_irq,
},
},
-#endif
};
static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
-#ifdef CONFIG_ARCH_S3C64XX
{
.base = S3C64XX_GPH_BASE + 0x4,
.chip = {
@@ -1102,11 +729,9 @@ static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
.to_irq = s3c64xx_gpiolib_lbank_to_irq,
},
},
-#endif
};
static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
-#ifdef CONFIG_ARCH_S3C64XX
{
.base = S3C64XX_GPF_BASE,
.config = &samsung_gpio_cfgs[6],
@@ -1161,7 +786,6 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
.to_irq = samsung_gpiolib_to_irq,
},
},
-#endif
};
/* TODO: cleanup soc_is_* */
@@ -1176,12 +800,7 @@ static __init int samsung_gpiolib_init(void)
if (of_have_populated_dt())
return 0;
- if (soc_is_s3c24xx()) {
- samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
- ARRAY_SIZE(samsung_gpio_cfgs));
- s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
- ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
- } else if (soc_is_s3c64xx()) {
+ if (soc_is_s3c64xx()) {
samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
ARRAY_SIZE(samsung_gpio_cfgs));
samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
@@ -1249,25 +868,6 @@ int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
}
EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
-unsigned s3c_gpio_getcfg(unsigned int pin)
-{
- struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
- unsigned long flags;
- unsigned ret = 0;
- int offset;
-
- if (chip) {
- offset = pin - chip->chip.base;
-
- samsung_gpio_lock(chip, flags);
- ret = samsung_gpio_do_getcfg(chip, offset);
- samsung_gpio_unlock(chip, flags);
- }
-
- return ret;
-}
-EXPORT_SYMBOL(s3c_gpio_getcfg);
-
int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
{
struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
@@ -1286,40 +886,3 @@ int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
return ret;
}
EXPORT_SYMBOL(s3c_gpio_setpull);
-
-samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
-{
- struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
- unsigned long flags;
- int offset;
- u32 pup = 0;
-
- if (chip) {
- offset = pin - chip->chip.base;
-
- samsung_gpio_lock(chip, flags);
- pup = samsung_gpio_do_getpull(chip, offset);
- samsung_gpio_unlock(chip, flags);
- }
-
- return (__force samsung_gpio_pull_t)pup;
-}
-EXPORT_SYMBOL(s3c_gpio_getpull);
-
-#ifdef CONFIG_PLAT_S3C24XX
-unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
-{
- unsigned long flags;
- unsigned long misccr;
-
- local_irq_save(flags);
- misccr = __raw_readl(S3C24XX_MISCCR);
- misccr &= ~clear;
- misccr ^= change;
- __raw_writel(misccr, S3C24XX_MISCCR);
- local_irq_restore(flags);
-
- return misccr;
-}
-EXPORT_SYMBOL(s3c2410_modify_misccr);
-#endif
diff --git a/arch/arm/mach-s3c/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung.h
index 02f6f4a96862..4233515eddaa 100644
--- a/arch/arm/mach-s3c/gpio-samsung.h
+++ b/arch/arm/mach-s3c/gpio-samsung.h
@@ -1,9 +1,2 @@
/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifdef CONFIG_ARCH_S3C24XX
-#include "gpio-samsung-s3c24xx.h"
-#endif
-
-#ifdef CONFIG_ARCH_S3C64XX
#include "gpio-samsung-s3c64xx.h"
-#endif
diff --git a/arch/arm/mach-s3c/gta02.h b/arch/arm/mach-s3c/gta02.h
deleted file mode 100644
index 043ae382bfc5..000000000000
--- a/arch/arm/mach-s3c/gta02.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * GTA02 header
- */
-
-#ifndef __MACH_S3C24XX_GTA02_H
-#define __MACH_S3C24XX_GTA02_H __FILE__
-
-#include "regs-gpio.h"
-
-#define GTA02_GPIO_AUX_LED S3C2410_GPB(2)
-#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9)
-#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6)
-#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7)
-#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
-#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
-
-#define GTA02_IRQ_PCF50633 IRQ_EINT9
-
-#endif /* __MACH_S3C24XX_GTA02_H */
diff --git a/arch/arm/mach-s3c/h1940-bluetooth.c b/arch/arm/mach-s3c/h1940-bluetooth.c
deleted file mode 100644
index 59edcf8a620d..000000000000
--- a/arch/arm/mach-s3c/h1940-bluetooth.c
+++ /dev/null
@@ -1,140 +0,0 @@
-// SPDX-License-Identifier: GPL-1.0+
-//
-// Copyright (c) Arnaud Patard <arnaud.patard@rtp-net.org>
-//
-// S3C2410 bluetooth "driver"
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/ctype.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/rfkill.h>
-
-#include "gpio-cfg.h"
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-
-#include "h1940.h"
-
-#define DRV_NAME "h1940-bt"
-
-/* Bluetooth control */
-static void h1940bt_enable(int on)
-{
- if (on) {
- /* Power on the chip */
- gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1);
- /* Reset the chip */
- mdelay(10);
-
- gpio_set_value(S3C2410_GPH(1), 1);
- mdelay(10);
- gpio_set_value(S3C2410_GPH(1), 0);
-
- h1940_led_blink_set(NULL, GPIO_LED_BLINK, NULL, NULL);
- }
- else {
- gpio_set_value(S3C2410_GPH(1), 1);
- mdelay(10);
- gpio_set_value(S3C2410_GPH(1), 0);
- mdelay(10);
- gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0);
-
- h1940_led_blink_set(NULL, GPIO_LED_NO_BLINK_LOW, NULL, NULL);
- }
-}
-
-static int h1940bt_set_block(void *data, bool blocked)
-{
- h1940bt_enable(!blocked);
- return 0;
-}
-
-static const struct rfkill_ops h1940bt_rfkill_ops = {
- .set_block = h1940bt_set_block,
-};
-
-static int h1940bt_probe(struct platform_device *pdev)
-{
- struct rfkill *rfk;
- int ret = 0;
-
- ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
- if (ret) {
- dev_err(&pdev->dev, "could not get GPH1\n");
- return ret;
- }
-
- ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev));
- if (ret) {
- gpio_free(S3C2410_GPH(1));
- dev_err(&pdev->dev, "could not get BT_POWER\n");
- return ret;
- }
-
- /* Configures BT serial port GPIOs */
- s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
- s3c_gpio_setpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE);
- s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
- s3c_gpio_setpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE);
- s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
- s3c_gpio_setpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE);
- s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
- s3c_gpio_setpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE);
-
- rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
- &h1940bt_rfkill_ops, NULL);
- if (!rfk) {
- ret = -ENOMEM;
- goto err_rfk_alloc;
- }
-
- ret = rfkill_register(rfk);
- if (ret)
- goto err_rfkill;
-
- platform_set_drvdata(pdev, rfk);
-
- return 0;
-
-err_rfkill:
- rfkill_destroy(rfk);
-err_rfk_alloc:
- return ret;
-}
-
-static int h1940bt_remove(struct platform_device *pdev)
-{
- struct rfkill *rfk = platform_get_drvdata(pdev);
-
- platform_set_drvdata(pdev, NULL);
- gpio_free(S3C2410_GPH(1));
-
- if (rfk) {
- rfkill_unregister(rfk);
- rfkill_destroy(rfk);
- }
- rfk = NULL;
-
- h1940bt_enable(0);
-
- return 0;
-}
-
-
-static struct platform_driver h1940bt_driver = {
- .driver = {
- .name = DRV_NAME,
- },
- .probe = h1940bt_probe,
- .remove = h1940bt_remove,
-};
-
-module_platform_driver(h1940bt_driver);
-
-MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
-MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-s3c/h1940.h b/arch/arm/mach-s3c/h1940.h
deleted file mode 100644
index 5dfe9d10cd15..000000000000
--- a/arch/arm/mach-s3c/h1940.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
- *
- * Copyright (c) 2005 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * iPAQ H1940 series definitions
- */
-
-#ifndef __MACH_S3C24XX_H1940_H
-#define __MACH_S3C24XX_H1940_H __FILE__
-
-#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
-#define H1940_SUSPEND_RESUMEAT (0x30081000)
-#define H1940_SUSPEND_CHECK (0x30080000)
-
-struct gpio_desc;
-
-extern void h1940_pm_return(void);
-extern int h1940_led_blink_set(struct gpio_desc *desc, int state,
- unsigned long *delay_on,
- unsigned long *delay_off);
-
-#include <linux/gpio.h>
-
-#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
-
-/* SD layer latch */
-
-#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0)
-#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1)
-#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2)
-#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3)
-#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4)
-#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5)
-#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6)
-#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7)
-
-/* CPU layer latch */
-
-#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8)
-#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9)
-#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10)
-#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11)
-#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12)
-#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13)
-#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
-#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
-
-#endif /* __MACH_S3C24XX_H1940_H */
diff --git a/arch/arm/mach-s3c/hardware-s3c24xx.h b/arch/arm/mach-s3c/hardware-s3c24xx.h
deleted file mode 100644
index 33b37467d05f..000000000000
--- a/arch/arm/mach-s3c/hardware-s3c24xx.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2003 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- */
-
-#ifndef __ASM_ARCH_HARDWARE_S3C24XX_H
-#define __ASM_ARCH_HARDWARE_S3C24XX_H
-
-extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
-
-#endif /* __ASM_ARCH_HARDWARE_S3C24XX_H */
diff --git a/arch/arm/mach-s3c/iic-core.h b/arch/arm/mach-s3c/iic-core.h
index c5cfd5af3874..6672691bd7b8 100644
--- a/arch/arm/mach-s3c/iic-core.h
+++ b/arch/arm/mach-s3c/iic-core.h
@@ -28,11 +28,4 @@ static inline void s3c_i2c1_setname(char *name)
#endif
}
-static inline void s3c_i2c2_setname(char *name)
-{
-#ifdef CONFIG_S3C_DEV_I2C2
- s3c_device_i2c2.name = name;
-#endif
-}
-
#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h
deleted file mode 100644
index 738b775d3336..000000000000
--- a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-s3c2410/include/mach/io.h
- * from arch/arm/mach-rpc/include/mach/io.h
- *
- * Copyright (C) 1997 Russell King
- * (C) 2003 Simtec Electronics
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_S3C24XX_H
-#define __ASM_ARM_ARCH_IO_S3C24XX_H
-
-#include <mach/map-base.h>
-
-/*
- * ISA style IO, for each machine to sort out mappings for,
- * if it implements it. We reserve two 16M regions for ISA,
- * so the PC/104 can use separate addresses for 8-bit and
- * 16-bit port I/O.
- */
-#define PCIO_BASE S3C_ADDR(0x02000000)
-#define IO_SPACE_LIMIT 0x00ffffff
-#define S3C24XX_VA_ISA_WORD (PCIO_BASE)
-#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000)
-
-#ifdef CONFIG_ISA
-
-#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p))
-#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p))
-#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p))
-
-#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p))
-#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p))
-#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p))
-
-#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l)
-#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l)
-#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l)
-
-#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l)
-#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l)
-#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l)
-
-#else
-
-#define __io(x) (PCIO_BASE + (x))
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-s3c/include/mach/io.h b/arch/arm/mach-s3c/include/mach/io.h
deleted file mode 100644
index 30a0135708dc..000000000000
--- a/arch/arm/mach-s3c/include/mach/io.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2020 Krzysztof Kozlowski <krzk@kernel.org>
- */
-
-#ifdef CONFIG_ARCH_S3C24XX
-#include "io-s3c24xx.h"
-#endif
diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h b/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h
deleted file mode 100644
index aaf3bae08b52..000000000000
--- a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2003-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- */
-
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- */
-
-#define S3C2410_CPUIRQ_OFFSET (16)
-
-#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
-
-/* main cpu interrupts */
-#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
-#define IRQ_EINT1 S3C2410_IRQ(1)
-#define IRQ_EINT2 S3C2410_IRQ(2)
-#define IRQ_EINT3 S3C2410_IRQ(3)
-#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
-#define IRQ_EINT8t23 S3C2410_IRQ(5)
-#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
-#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
-#define IRQ_BATT_FLT S3C2410_IRQ(7)
-#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
-#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
-#define IRQ_TIMER0 S3C2410_IRQ(10)
-#define IRQ_TIMER1 S3C2410_IRQ(11)
-#define IRQ_TIMER2 S3C2410_IRQ(12)
-#define IRQ_TIMER3 S3C2410_IRQ(13)
-#define IRQ_TIMER4 S3C2410_IRQ(14)
-#define IRQ_UART2 S3C2410_IRQ(15)
-#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
-#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
-#define IRQ_DMA1 S3C2410_IRQ(18)
-#define IRQ_DMA2 S3C2410_IRQ(19)
-#define IRQ_DMA3 S3C2410_IRQ(20)
-#define IRQ_SDI S3C2410_IRQ(21)
-#define IRQ_SPI0 S3C2410_IRQ(22)
-#define IRQ_UART1 S3C2410_IRQ(23)
-#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
-#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
-#define IRQ_USBD S3C2410_IRQ(25)
-#define IRQ_USBH S3C2410_IRQ(26)
-#define IRQ_IIC S3C2410_IRQ(27)
-#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
-#define IRQ_SPI1 S3C2410_IRQ(29)
-#define IRQ_RTC S3C2410_IRQ(30)
-#define IRQ_ADCPARENT S3C2410_IRQ(31)
-
-/* interrupts generated from the external interrupts sources */
-#define IRQ_EINT0_2412 S3C2410_IRQ(32)
-#define IRQ_EINT1_2412 S3C2410_IRQ(33)
-#define IRQ_EINT2_2412 S3C2410_IRQ(34)
-#define IRQ_EINT3_2412 S3C2410_IRQ(35)
-#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
-#define IRQ_EINT5 S3C2410_IRQ(37)
-#define IRQ_EINT6 S3C2410_IRQ(38)
-#define IRQ_EINT7 S3C2410_IRQ(39)
-#define IRQ_EINT8 S3C2410_IRQ(40)
-#define IRQ_EINT9 S3C2410_IRQ(41)
-#define IRQ_EINT10 S3C2410_IRQ(42)
-#define IRQ_EINT11 S3C2410_IRQ(43)
-#define IRQ_EINT12 S3C2410_IRQ(44)
-#define IRQ_EINT13 S3C2410_IRQ(45)
-#define IRQ_EINT14 S3C2410_IRQ(46)
-#define IRQ_EINT15 S3C2410_IRQ(47)
-#define IRQ_EINT16 S3C2410_IRQ(48)
-#define IRQ_EINT17 S3C2410_IRQ(49)
-#define IRQ_EINT18 S3C2410_IRQ(50)
-#define IRQ_EINT19 S3C2410_IRQ(51)
-#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
-#define IRQ_EINT21 S3C2410_IRQ(53)
-#define IRQ_EINT22 S3C2410_IRQ(54)
-#define IRQ_EINT23 S3C2410_IRQ(55)
-
-#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
-#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
-
-#define IRQ_LCD_FIFO S3C2410_IRQ(56)
-#define IRQ_LCD_FRAME S3C2410_IRQ(57)
-
-/* IRQs for the interal UARTs, and ADC
- * these need to be ordered in number of appearance in the
- * SUBSRC mask register
-*/
-
-#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
-
-#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
-#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
-#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
-
-#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
-#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
-#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
-
-#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
-#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
-#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
-
-#define IRQ_TC S3C2410_IRQSUB(9)
-#define IRQ_ADC S3C2410_IRQSUB(10)
-
-/* extra irqs for s3c2412 */
-
-#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
-
-#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
-#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
-
-
-#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
-#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
-#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
-#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
-#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
-
-#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
-#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
-#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
-#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
-#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
-#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
-#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
-#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
-#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
-#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
-#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
-
-/* second interrupt-register of s3c2416/s3c2450 */
-
-#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
-#define IRQ_S3C2416_2D S3C2416_IRQ(0)
-#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
-#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
-#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3)
-#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4)
-#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5)
-#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6)
-#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7)
-
-/* extra irqs for s3c2440 */
-
-#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
-#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
-#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
-#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
-
-/* irqs for s3c2443 */
-
-#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
-#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
-#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
-#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
-#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
-
-#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
-
-#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0
-#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC
-
-#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
-#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
-#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
-#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
-
-#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
-#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
-#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
-#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
-#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
-#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
-
-/* UART3 */
-#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
-#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
-#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
-
-#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
-#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
-
-#if defined(CONFIG_CPU_S3C2416)
-#define NR_IRQS (IRQ_S3C2416_I2S1 + 1)
-#else
-#define NR_IRQS (IRQ_S3C2443_AC97 + 1)
-#endif
-
-/* compatibility define. */
-#define IRQ_UART3 IRQ_S3C2443_UART3
-#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
-#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
-#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
-
-#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
-#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
-
-#ifdef CONFIG_CPU_S3C2440
-#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
-#else
-#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
-#endif
-
-/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
-#define FIQ_START IRQ_EINT0
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs.h
deleted file mode 100644
index 0bff1c1c8eb0..000000000000
--- a/arch/arm/mach-s3c/include/mach/irqs.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifdef CONFIG_ARCH_S3C24XX
-#include "irqs-s3c24xx.h"
-#endif
-
-#ifdef CONFIG_ARCH_S3C64XX
-#include "irqs-s3c64xx.h"
-#endif
diff --git a/arch/arm/mach-s3c/init.c b/arch/arm/mach-s3c/init.c
index 9d92f03e9bc1..0ac079f23d51 100644
--- a/arch/arm/mach-s3c/init.c
+++ b/arch/arm/mach-s3c/init.c
@@ -59,29 +59,8 @@ void __init s3c_init_cpu(unsigned long idcode,
if (cpu->map_io)
cpu->map_io();
-}
-
-/* s3c24xx_init_clocks
- *
- * Initialise the clock subsystem and associated information from the
- * given master crystal value.
- *
- * xtal = 0 -> use default PLL crystal value (normally 12MHz)
- * != 0 -> PLL crystal value in Hz
-*/
-
-void __init s3c24xx_init_clocks(int xtal)
-{
- if (xtal == 0)
- xtal = 12*1000*1000;
-
- if (cpu == NULL)
- panic("s3c24xx_init_clocks: no cpu setup?\n");
- if (cpu->init_clocks == NULL)
- panic("s3c24xx_init_clocks: cpu has no clock init\n");
- else
- (cpu->init_clocks)(xtal);
+ pr_err("The platform is deprecated and scheduled for removal. Please reach to the maintainers of the platform and linux-samsung-soc@vger.kernel.org if you still use it. Without such feedback, the platform will be removed after 2022.\n");
}
/* uart management */
@@ -148,8 +127,7 @@ static int __init s3c_arch_init(void)
int ret;
/* init is only needed for ATAGS based platforms */
- if (!IS_ENABLED(CONFIG_ATAGS) ||
- (!soc_is_s3c24xx() && !soc_is_s3c64xx()))
+ if (!IS_ENABLED(CONFIG_ATAGS))
return 0;
// do the correct init for cpu
diff --git a/arch/arm/mach-s3c/iotiming-s3c2410.c b/arch/arm/mach-s3c/iotiming-s3c2410.c
deleted file mode 100644
index 28d9f473e24a..000000000000
--- a/arch/arm/mach-s3c/iotiming-s3c2410.c
+++ /dev/null
@@ -1,472 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2006-2009 Simtec Electronics
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>
-//
-// S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/cpufreq.h>
-#include <linux/seq_file.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include "map.h"
-#include "regs-clock.h"
-
-#include <linux/soc/samsung/s3c-cpufreq-core.h>
-
-#include "regs-mem-s3c24xx.h"
-
-#define print_ns(x) ((x) / 10), ((x) % 10)
-
-/**
- * s3c2410_print_timing - print bank timing data for debug purposes
- * @pfx: The prefix to put on the output
- * @timings: The timing inforamtion to print.
-*/
-static void s3c2410_print_timing(const char *pfx,
- struct s3c_iotimings *timings)
-{
- struct s3c2410_iobank_timing *bt;
- int bank;
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- bt = timings->bank[bank].io_2410;
- if (!bt)
- continue;
-
- printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
- "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
- print_ns(bt->tacs),
- print_ns(bt->tcos),
- print_ns(bt->tacc),
- print_ns(bt->tcoh),
- print_ns(bt->tcah));
- }
-}
-
-/**
- * bank_reg - convert bank number to pointer to the control register.
- * @bank: The IO bank number.
- */
-static inline void __iomem *bank_reg(unsigned int bank)
-{
- return S3C2410_BANKCON0 + (bank << 2);
-}
-
-/**
- * bank_is_io - test whether bank is used for IO
- * @bankcon: The bank control register.
- *
- * This is a simplistic test to see if any BANKCON[x] is not an IO
- * bank. It currently does not take into account whether BWSCON has
- * an illegal width-setting in it, or if the pin connected to nCS[x]
- * is actually being handled as a chip-select.
- */
-static inline int bank_is_io(unsigned long bankcon)
-{
- return !(bankcon & S3C2410_BANKCON_SDRAM);
-}
-
-/**
- * to_div - convert cycle time to divisor
- * @cyc: The cycle time, in 10ths of nanoseconds.
- * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
- *
- * Convert the given cycle time into the divisor to use to obtain it from
- * HCLK.
-*/
-static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
-{
- if (cyc == 0)
- return 0;
-
- return DIV_ROUND_UP(cyc, hclk_tns);
-}
-
-/**
- * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
- * @cyc: The cycle time, in 10ths of nanoseconds.
- * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
- * @v: Pointer to register to alter.
- * @shift: The shift to get to the control bits.
- *
- * Calculate the divisor, and turn it into the correct control bits to
- * set in the result, @v.
- */
-static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
- unsigned long *v, int shift)
-{
- unsigned int div = to_div(cyc, hclk_tns);
- unsigned long val;
-
- s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
- __func__, cyc, hclk_tns, shift, div);
-
- switch (div) {
- case 0:
- val = 0;
- break;
- case 1:
- val = 1;
- break;
- case 2:
- val = 2;
- break;
- case 3:
- case 4:
- val = 3;
- break;
- default:
- return -1;
- }
-
- *v |= val << shift;
- return 0;
-}
-
-static int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
-{
- /* Currently no support for Tacp calculations. */
- return 0;
-}
-
-/**
- * calc_tacc - calculate divisor control for tacc.
- * @cyc: The cycle time, in 10ths of nanoseconds.
- * @nwait_en: IS nWAIT enabled for this bank.
- * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
- * @v: Pointer to register to alter.
- *
- * Calculate the divisor control for tACC, taking into account whether
- * the bank has nWAIT enabled. The result is used to modify the value
- * pointed to by @v.
-*/
-static int calc_tacc(unsigned int cyc, int nwait_en,
- unsigned long hclk_tns, unsigned long *v)
-{
- unsigned int div = to_div(cyc, hclk_tns);
- unsigned long val;
-
- s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
- __func__, cyc, nwait_en, hclk_tns, div);
-
- /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
- if (nwait_en && div < 4)
- div = 4;
-
- switch (div) {
- case 0:
- val = 0;
- break;
-
- case 1:
- case 2:
- case 3:
- case 4:
- val = div - 1;
- break;
-
- case 5:
- case 6:
- val = 4;
- break;
-
- case 7:
- case 8:
- val = 5;
- break;
-
- case 9:
- case 10:
- val = 6;
- break;
-
- case 11:
- case 12:
- case 13:
- case 14:
- val = 7;
- break;
-
- default:
- return -1;
- }
-
- *v |= val << 8;
- return 0;
-}
-
-/**
- * s3c2410_calc_bank - calculate bank timing information
- * @cfg: The configuration we need to calculate for.
- * @bt: The bank timing information.
- *
- * Given the cycle timine for a bank @bt, calculate the new BANKCON
- * setting for the @cfg timing. This updates the timing information
- * ready for the cpu frequency change.
- */
-static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
- struct s3c2410_iobank_timing *bt)
-{
- unsigned long hclk = cfg->freq.hclk_tns;
- unsigned long res;
- int ret;
-
- res = bt->bankcon;
- res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
-
- /* tacp: 2,3,4,5 */
- /* tcah: 0,1,2,4 */
- /* tcoh: 0,1,2,4 */
- /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
- /* tcos: 0,1,2,4 */
- /* tacs: 0,1,2,4 */
-
- ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
- ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
- ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
- ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
-
- if (ret)
- return -EINVAL;
-
- ret |= calc_tacp(bt->tacp, hclk, &res);
- ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
-
- if (ret)
- return -EINVAL;
-
- bt->bankcon = res;
- return 0;
-}
-
-static const unsigned int tacc_tab[] = {
- [0] = 1,
- [1] = 2,
- [2] = 3,
- [3] = 4,
- [4] = 6,
- [5] = 9,
- [6] = 10,
- [7] = 14,
-};
-
-/**
- * get_tacc - turn tACC value into cycle time
- * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
- * @val: The bank timing register value, shifed down.
- */
-static unsigned int get_tacc(unsigned long hclk_tns,
- unsigned long val)
-{
- val &= 7;
- return hclk_tns * tacc_tab[val];
-}
-
-/**
- * get_0124 - turn 0/1/2/4 divider into cycle time
- * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
- * @val: The bank timing register value, shifed down.
- */
-static unsigned int get_0124(unsigned long hclk_tns,
- unsigned long val)
-{
- val &= 3;
- return hclk_tns * ((val == 3) ? 4 : val);
-}
-
-/**
- * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
- * @cfg: The frequency configuration
- * @bt: The bank timing to fill in (uses cached BANKCON)
- *
- * Given the BANKCON setting in @bt and the current frequency settings
- * in @cfg, update the cycle timing information.
- */
-static void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
- struct s3c2410_iobank_timing *bt)
-{
- unsigned long bankcon = bt->bankcon;
- unsigned long hclk = cfg->freq.hclk_tns;
-
- bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
- bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
- bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
- bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
- bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
-}
-
-/**
- * s3c2410_iotiming_debugfs - debugfs show io bank timing information
- * @seq: The seq_file to write output to using seq_printf().
- * @cfg: The current configuration.
- * @iob: The IO bank information to decode.
- */
-void s3c2410_iotiming_debugfs(struct seq_file *seq,
- struct s3c_cpufreq_config *cfg,
- union s3c_iobank *iob)
-{
- struct s3c2410_iobank_timing *bt = iob->io_2410;
- unsigned long bankcon = bt->bankcon;
- unsigned long hclk = cfg->freq.hclk_tns;
- unsigned int tacs;
- unsigned int tcos;
- unsigned int tacc;
- unsigned int tcoh;
- unsigned int tcah;
-
- seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
-
- tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
- tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
- tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
- tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
- tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
-
- seq_printf(seq,
- "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
- print_ns(bt->tacs),
- print_ns(bt->tcos),
- print_ns(bt->tacc),
- print_ns(bt->tcoh),
- print_ns(bt->tcah));
-
- seq_printf(seq,
- "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
- print_ns(tacs),
- print_ns(tcos),
- print_ns(tacc),
- print_ns(tcoh),
- print_ns(tcah));
-}
-
-/**
- * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
- * @cfg: The frequency configuration
- * @iot: The IO timing information to fill out.
- *
- * Calculate the new values for the banks in @iot based on the new
- * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
- * to update the timing when necessary.
- */
-int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot)
-{
- struct s3c2410_iobank_timing *bt;
- unsigned long bankcon;
- int bank;
- int ret;
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- bankcon = __raw_readl(bank_reg(bank));
- bt = iot->bank[bank].io_2410;
-
- if (!bt)
- continue;
-
- bt->bankcon = bankcon;
-
- ret = s3c2410_calc_bank(cfg, bt);
- if (ret) {
- printk(KERN_ERR "%s: cannot calculate bank %d io\n",
- __func__, bank);
- goto err;
- }
-
- s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
- __func__, bank, bt->bankcon);
- }
-
- return 0;
- err:
- return ret;
-}
-
-/**
- * s3c2410_iotiming_set - set the IO timings from the given setup.
- * @cfg: The frequency configuration
- * @iot: The IO timing information to use.
- *
- * Set all the currently used IO bank timing information generated
- * by s3c2410_iotiming_calc() once the core has validated that all
- * the new values are within permitted bounds.
- */
-void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot)
-{
- struct s3c2410_iobank_timing *bt;
- int bank;
-
- /* set the io timings from the specifier */
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- bt = iot->bank[bank].io_2410;
- if (!bt)
- continue;
-
- __raw_writel(bt->bankcon, bank_reg(bank));
- }
-}
-
-/**
- * s3c2410_iotiming_get - Get the timing information from current registers.
- * @cfg: The frequency configuration
- * @timings: The IO timing information to fill out.
- *
- * Calculate the @timings timing information from the current frequency
- * information in @cfg, and the new frequency configuration
- * through all the IO banks, reading the state and then updating @iot
- * as necessary.
- *
- * This is used at the moment on initialisation to get the current
- * configuration so that boards do not have to carry their own setup
- * if the timings are correct on initialisation.
- */
-
-int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *timings)
-{
- struct s3c2410_iobank_timing *bt;
- unsigned long bankcon;
- unsigned long bwscon;
- int bank;
-
- bwscon = __raw_readl(S3C2410_BWSCON);
-
- /* look through all banks to see what is currently set. */
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- bankcon = __raw_readl(bank_reg(bank));
-
- if (!bank_is_io(bankcon))
- continue;
-
- s3c_freq_iodbg("%s: bank %d: con %08lx\n",
- __func__, bank, bankcon);
-
- bt = kzalloc(sizeof(*bt), GFP_KERNEL);
- if (!bt)
- return -ENOMEM;
-
- /* find out in nWait is enabled for bank. */
-
- if (bank != 0) {
- unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank);
- if (tmp & S3C2410_BWSCON_WS)
- bt->nwait_en = 1;
- }
-
- timings->bank[bank].io_2410 = bt;
- bt->bankcon = bankcon;
-
- s3c2410_iotiming_getbank(cfg, bt);
- }
-
- s3c2410_print_timing("get", timings);
- return 0;
-}
diff --git a/arch/arm/mach-s3c/iotiming-s3c2412.c b/arch/arm/mach-s3c/iotiming-s3c2412.c
deleted file mode 100644
index 003f89c4dc53..000000000000
--- a/arch/arm/mach-s3c/iotiming-s3c2412.c
+++ /dev/null
@@ -1,278 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2006-2008 Simtec Electronics
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>
-//
-// S3C2412/S3C2443 (PL093 based) IO timing support
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/seq_file.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#include <linux/amba/pl093.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "cpu.h"
-#include <linux/soc/samsung/s3c-cpufreq-core.h>
-
-#include "s3c2412.h"
-
-#define print_ns(x) ((x) / 10), ((x) % 10)
-
-/**
- * s3c2412_print_timing - print timing information via printk.
- * @pfx: The prefix to print each line with.
- * @iot: The IO timing information
- */
-static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
-{
- struct s3c2412_iobank_timing *bt;
- unsigned int bank;
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- bt = iot->bank[bank].io_2412;
- if (!bt)
- continue;
-
- printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
- "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
- print_ns(bt->idcy),
- print_ns(bt->wstrd),
- print_ns(bt->wstwr),
- print_ns(bt->wstoen),
- print_ns(bt->wstwen),
- print_ns(bt->wstbrd));
- }
-}
-
-/**
- * to_div - turn a cycle length into a divisor setting.
- * @cyc_tns: The cycle time in 10ths of nanoseconds.
- * @clk_tns: The clock period in 10ths of nanoseconds.
- */
-static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
-{
- return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
-}
-
-/**
- * calc_timing - calculate timing divisor value and check in range.
- * @hwtm: The hardware timing in 10ths of nanoseconds.
- * @clk_tns: The clock period in 10ths of nanoseconds.
- * @err: Pointer to err variable to update in event of failure.
- */
-static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
- unsigned int *err)
-{
- unsigned int ret = to_div(hwtm, clk_tns);
-
- if (ret > 0xf)
- *err = -EINVAL;
-
- return ret;
-}
-
-/**
- * s3c2412_calc_bank - calculate the bank divisor settings.
- * @cfg: The current frequency configuration.
- * @bt: The bank timing.
- */
-static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
- struct s3c2412_iobank_timing *bt)
-{
- unsigned int hclk = cfg->freq.hclk_tns;
- int err = 0;
-
- bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
- bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
- bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
- bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
- bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
- bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
-
- return err;
-}
-
-/**
- * s3c2412_iotiming_debugfs - debugfs show io bank timing information
- * @seq: The seq_file to write output to using seq_printf().
- * @cfg: The current configuration.
- * @iob: The IO bank information to decode.
-*/
-void s3c2412_iotiming_debugfs(struct seq_file *seq,
- struct s3c_cpufreq_config *cfg,
- union s3c_iobank *iob)
-{
- struct s3c2412_iobank_timing *bt = iob->io_2412;
-
- seq_printf(seq,
- "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
- "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
- print_ns(bt->idcy),
- print_ns(bt->wstrd),
- print_ns(bt->wstwr),
- print_ns(bt->wstoen),
- print_ns(bt->wstwen),
- print_ns(bt->wstbrd));
-}
-
-/**
- * s3c2412_iotiming_calc - calculate all the bank divisor settings.
- * @cfg: The current frequency configuration.
- * @iot: The bank timing information.
- *
- * Calculate the timing information for all the banks that are
- * configured as IO, using s3c2412_calc_bank().
- */
-int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot)
-{
- struct s3c2412_iobank_timing *bt;
- int bank;
- int ret;
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- bt = iot->bank[bank].io_2412;
- if (!bt)
- continue;
-
- ret = s3c2412_calc_bank(cfg, bt);
- if (ret) {
- printk(KERN_ERR "%s: cannot calculate bank %d io\n",
- __func__, bank);
- goto err;
- }
- }
-
- return 0;
- err:
- return ret;
-}
-
-/**
- * s3c2412_iotiming_set - set the timing information
- * @cfg: The current frequency configuration.
- * @iot: The bank timing information.
- *
- * Set the IO bank information from the details calculated earlier from
- * calling s3c2412_iotiming_calc().
- */
-void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot)
-{
- struct s3c2412_iobank_timing *bt;
- void __iomem *regs;
- int bank;
-
- /* set the io timings from the specifier */
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- bt = iot->bank[bank].io_2412;
- if (!bt)
- continue;
-
- regs = S3C2412_SSMC_BANK(bank);
-
- __raw_writel(bt->smbidcyr, regs + SMBIDCYR);
- __raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
- __raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
- __raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
- __raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
- __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
- }
-}
-
-static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
-{
- return (reg & 0xf) * clock;
-}
-
-static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
- struct s3c2412_iobank_timing *bt,
- unsigned int bank)
-{
- unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */
- void __iomem *regs = S3C2412_SSMC_BANK(bank);
-
- bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
- bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
- bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
- bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
- bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
-}
-
-/**
- * bank_is_io - return true if bank is (possibly) IO.
- * @bank: The bank number.
- * @bankcfg: The value of S3C2412_EBI_BANKCFG.
- */
-static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
-{
- if (bank < 2)
- return true;
-
- return !(bankcfg & (1 << bank));
-}
-
-int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *timings)
-{
- struct s3c2412_iobank_timing *bt;
- u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
- unsigned int bank;
-
- /* look through all banks to see what is currently set. */
-
- for (bank = 0; bank < MAX_BANKS; bank++) {
- if (!bank_is_io(bank, bankcfg))
- continue;
-
- bt = kzalloc(sizeof(*bt), GFP_KERNEL);
- if (!bt)
- return -ENOMEM;
-
- timings->bank[bank].io_2412 = bt;
- s3c2412_iotiming_getbank(cfg, bt, bank);
- }
-
- s3c2412_print_timing("get", timings);
- return 0;
-}
-
-/* this is in here as it is so small, it doesn't currently warrant a file
- * to itself. We expect that any s3c24xx needing this is going to also
- * need the iotiming support.
- */
-void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
-{
- struct s3c_cpufreq_board *board = cfg->board;
- u32 refresh;
-
- WARN_ON(board == NULL);
-
- /* Reduce both the refresh time (in ns) and the frequency (in MHz)
- * down to ensure that we do not overflow 32 bit numbers.
- *
- * This should work for HCLK up to 133MHz and refresh period up
- * to 30usec.
- */
-
- refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
- refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
- refresh &= ((1 << 16) - 1);
-
- s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
-
- __raw_writel(refresh, S3C2412_REFRESH);
-}
diff --git a/arch/arm/mach-s3c/irq-pm-s3c24xx.c b/arch/arm/mach-s3c/irq-pm-s3c24xx.c
deleted file mode 100644
index 4d5e28312d91..000000000000
--- a/arch/arm/mach-s3c/irq-pm-s3c24xx.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2003-2004 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-// http://armlinux.simtec.co.uk/
-//
-// S3C24XX - IRQ PM code
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/syscore_ops.h>
-#include <linux/io.h>
-
-#include "cpu.h"
-#include "pm.h"
-#include <mach/map-base.h>
-#include "map-s3c.h"
-
-#include "regs-irq.h"
-#include "regs-gpio.h"
-#include "pm-core.h"
-
-#include <asm/irq.h>
-
-int s3c_irq_wake(struct irq_data *data, unsigned int state)
-{
- unsigned long irqbit = 1 << data->hwirq;
-
- if (!(s3c_irqwake_intallow & irqbit))
- return -ENOENT;
-
- pr_info("wake %s for hwirq %lu\n",
- state ? "enabled" : "disabled", data->hwirq);
-
- if (!state)
- s3c_irqwake_intmask |= irqbit;
- else
- s3c_irqwake_intmask &= ~irqbit;
-
- return 0;
-}
-
-static struct sleep_save irq_save[] = {
- SAVE_ITEM(S3C2410_INTMSK),
- SAVE_ITEM(S3C2410_INTSUBMSK),
-};
-
-/* the extint values move between the s3c2410/s3c2440 and the s3c2412
- * so we use an array to hold them, and to calculate the address of
- * the register at run-time
-*/
-
-static unsigned long save_extint[3];
-static unsigned long save_eintflt[4];
-static unsigned long save_eintmask;
-
-static int s3c24xx_irq_suspend(void)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(save_extint); i++)
- save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
-
- for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
- save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
-
- s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
- save_eintmask = __raw_readl(S3C24XX_EINTMASK);
-
- return 0;
-}
-
-static void s3c24xx_irq_resume(void)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(save_extint); i++)
- __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
-
- for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
- __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
-
- s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
- __raw_writel(save_eintmask, S3C24XX_EINTMASK);
-}
-
-struct syscore_ops s3c24xx_irq_syscore_ops = {
- .suspend = s3c24xx_irq_suspend,
- .resume = s3c24xx_irq_resume,
-};
-
-#ifdef CONFIG_CPU_S3C2416
-static struct sleep_save s3c2416_irq_save[] = {
- SAVE_ITEM(S3C2416_INTMSK2),
-};
-
-static int s3c2416_irq_suspend(void)
-{
- s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
-
- return 0;
-}
-
-static void s3c2416_irq_resume(void)
-{
- s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
-}
-
-struct syscore_ops s3c2416_irq_syscore_ops = {
- .suspend = s3c2416_irq_suspend,
- .resume = s3c2416_irq_resume,
-};
-#endif
diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c b/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c
deleted file mode 100644
index 84cf86376ded..000000000000
--- a/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <linux/stddef.h>
-#include <linux/export.h>
-#include <linux/spi/s3c24xx-fiq.h>
-
-EXPORT_SYMBOL(s3c24xx_spi_fiq_rx);
-EXPORT_SYMBOL(s3c24xx_spi_fiq_txrx);
-EXPORT_SYMBOL(s3c24xx_spi_fiq_tx);
diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S
deleted file mode 100644
index 5d238d9a798e..000000000000
--- a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* linux/drivers/spi/spi_s3c24xx_fiq.S
- *
- * Copyright 2009 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX SPI - FIQ pseudo-DMA transfer code
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-#include "map.h"
-#include "regs-irq.h"
-
-#include <linux/spi/s3c24xx-fiq.h>
-
-#define S3C2410_SPTDAT (0x10)
-#define S3C2410_SPRDAT (0x14)
-
- .text
-
- @ entry to these routines is as follows, with the register names
- @ defined in fiq.h so that they can be shared with the C files which
- @ setup the calling registers.
- @
- @ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND
- @ fiq_rtmp Temporary register to hold tx/rx data
- @ fiq_rspi The base of the SPI register block
- @ fiq_rtx The tx buffer pointer
- @ fiq_rrx The rx buffer pointer
- @ fiq_rcount The number of bytes to move
-
- @ each entry starts with a word entry of how long it is
- @ and an offset to the irq acknowledgment word
-
-ENTRY(s3c24xx_spi_fiq_rx)
- .word fiq_rx_end - fiq_rx_start
- .word fiq_rx_irq_ack - fiq_rx_start
-fiq_rx_start:
- ldr fiq_rtmp, fiq_rx_irq_ack
- str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
-
- ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
- strb fiq_rtmp, [ fiq_rrx ], #1
-
- mov fiq_rtmp, #0xff
- strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
-
- subs fiq_rcount, fiq_rcount, #1
- subsne pc, lr, #4 @@ return, still have work to do
-
- @@ set IRQ controller so that next op will trigger IRQ
- mov fiq_rtmp, #0
- str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
- subs pc, lr, #4
-
-fiq_rx_irq_ack:
- .word 0
-fiq_rx_end:
-
-ENTRY(s3c24xx_spi_fiq_txrx)
- .word fiq_txrx_end - fiq_txrx_start
- .word fiq_txrx_irq_ack - fiq_txrx_start
-fiq_txrx_start:
-
- ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
- strb fiq_rtmp, [ fiq_rrx ], #1
-
- ldr fiq_rtmp, fiq_txrx_irq_ack
- str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
-
- ldrb fiq_rtmp, [ fiq_rtx ], #1
- strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
-
- subs fiq_rcount, fiq_rcount, #1
- subsne pc, lr, #4 @@ return, still have work to do
-
- mov fiq_rtmp, #0
- str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
- subs pc, lr, #4
-
-fiq_txrx_irq_ack:
- .word 0
-
-fiq_txrx_end:
-
-ENTRY(s3c24xx_spi_fiq_tx)
- .word fiq_tx_end - fiq_tx_start
- .word fiq_tx_irq_ack - fiq_tx_start
-fiq_tx_start:
- ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
-
- ldr fiq_rtmp, fiq_tx_irq_ack
- str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
-
- ldrb fiq_rtmp, [ fiq_rtx ], #1
- strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
-
- subs fiq_rcount, fiq_rcount, #1
- subsne pc, lr, #4 @@ return, still have work to do
-
- mov fiq_rtmp, #0
- str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
- subs pc, lr, #4
-
-fiq_tx_irq_ack:
- .word 0
-
-fiq_tx_end:
-
- .end
diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c
deleted file mode 100644
index 3776d5206f9b..000000000000
--- a/arch/arm/mach-s3c/irq-s3c24xx.c
+++ /dev/null
@@ -1,1352 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * S3C24XX IRQ handling
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
-*/
-
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/spi/s3c24xx.h>
-
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
-
-#include <mach/irqs.h>
-#include "regs-irq.h"
-#include "regs-gpio.h"
-
-#include "cpu.h"
-#include "regs-irqtype.h"
-#include "pm.h"
-#include "s3c24xx.h"
-
-#define S3C_IRQTYPE_NONE 0
-#define S3C_IRQTYPE_EINT 1
-#define S3C_IRQTYPE_EDGE 2
-#define S3C_IRQTYPE_LEVEL 3
-
-struct s3c_irq_data {
- unsigned int type;
- unsigned long offset;
- unsigned long parent_irq;
-
- /* data gets filled during init */
- struct s3c_irq_intc *intc;
- unsigned long sub_bits;
- struct s3c_irq_intc *sub_intc;
-};
-
-/*
- * Structure holding the controller data
- * @reg_pending register holding pending irqs
- * @reg_intpnd special register intpnd in main intc
- * @reg_mask mask register
- * @domain irq_domain of the controller
- * @parent parent controller for ext and sub irqs
- * @irqs irq-data, always s3c_irq_data[32]
- */
-struct s3c_irq_intc {
- void __iomem *reg_pending;
- void __iomem *reg_intpnd;
- void __iomem *reg_mask;
- struct irq_domain *domain;
- struct s3c_irq_intc *parent;
- struct s3c_irq_data *irqs;
-};
-
-/*
- * Array holding pointers to the global controller structs
- * [0] ... main_intc
- * [1] ... sub_intc
- * [2] ... main_intc2 on s3c2416
- */
-static struct s3c_irq_intc *s3c_intc[3];
-
-static void s3c_irq_mask(struct irq_data *data)
-{
- struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
- struct s3c_irq_intc *intc = irq_data->intc;
- struct s3c_irq_intc *parent_intc = intc->parent;
- struct s3c_irq_data *parent_data;
- unsigned long mask;
- unsigned int irqno;
-
- mask = readl_relaxed(intc->reg_mask);
- mask |= (1UL << irq_data->offset);
- writel_relaxed(mask, intc->reg_mask);
-
- if (parent_intc) {
- parent_data = &parent_intc->irqs[irq_data->parent_irq];
-
- /* check to see if we need to mask the parent IRQ
- * The parent_irq is always in main_intc, so the hwirq
- * for find_mapping does not need an offset in any case.
- */
- if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
- irqno = irq_find_mapping(parent_intc->domain,
- irq_data->parent_irq);
- s3c_irq_mask(irq_get_irq_data(irqno));
- }
- }
-}
-
-static void s3c_irq_unmask(struct irq_data *data)
-{
- struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
- struct s3c_irq_intc *intc = irq_data->intc;
- struct s3c_irq_intc *parent_intc = intc->parent;
- unsigned long mask;
- unsigned int irqno;
-
- mask = readl_relaxed(intc->reg_mask);
- mask &= ~(1UL << irq_data->offset);
- writel_relaxed(mask, intc->reg_mask);
-
- if (parent_intc) {
- irqno = irq_find_mapping(parent_intc->domain,
- irq_data->parent_irq);
- s3c_irq_unmask(irq_get_irq_data(irqno));
- }
-}
-
-static inline void s3c_irq_ack(struct irq_data *data)
-{
- struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
- struct s3c_irq_intc *intc = irq_data->intc;
- unsigned long bitval = 1UL << irq_data->offset;
-
- writel_relaxed(bitval, intc->reg_pending);
- if (intc->reg_intpnd)
- writel_relaxed(bitval, intc->reg_intpnd);
-}
-
-static int s3c_irq_type(struct irq_data *data, unsigned int type)
-{
- switch (type) {
- case IRQ_TYPE_NONE:
- break;
- case IRQ_TYPE_EDGE_RISING:
- case IRQ_TYPE_EDGE_FALLING:
- case IRQ_TYPE_EDGE_BOTH:
- irq_set_handler(data->irq, handle_edge_irq);
- break;
- case IRQ_TYPE_LEVEL_LOW:
- case IRQ_TYPE_LEVEL_HIGH:
- irq_set_handler(data->irq, handle_level_irq);
- break;
- default:
- pr_err("No such irq type %d\n", type);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int s3c_irqext_type_set(void __iomem *gpcon_reg,
- void __iomem *extint_reg,
- unsigned long gpcon_offset,
- unsigned long extint_offset,
- unsigned int type)
-{
- unsigned long newvalue = 0, value;
-
- /* Set the GPIO to external interrupt mode */
- value = readl_relaxed(gpcon_reg);
- value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
- writel_relaxed(value, gpcon_reg);
-
- /* Set the external interrupt to pointed trigger type */
- switch (type)
- {
- case IRQ_TYPE_NONE:
- pr_warn("No edge setting!\n");
- break;
-
- case IRQ_TYPE_EDGE_RISING:
- newvalue = S3C2410_EXTINT_RISEEDGE;
- break;
-
- case IRQ_TYPE_EDGE_FALLING:
- newvalue = S3C2410_EXTINT_FALLEDGE;
- break;
-
- case IRQ_TYPE_EDGE_BOTH:
- newvalue = S3C2410_EXTINT_BOTHEDGE;
- break;
-
- case IRQ_TYPE_LEVEL_LOW:
- newvalue = S3C2410_EXTINT_LOWLEV;
- break;
-
- case IRQ_TYPE_LEVEL_HIGH:
- newvalue = S3C2410_EXTINT_HILEV;
- break;
-
- default:
- pr_err("No such irq type %d\n", type);
- return -EINVAL;
- }
-
- value = readl_relaxed(extint_reg);
- value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
- writel_relaxed(value, extint_reg);
-
- return 0;
-}
-
-static int s3c_irqext_type(struct irq_data *data, unsigned int type)
-{
- void __iomem *extint_reg;
- void __iomem *gpcon_reg;
- unsigned long gpcon_offset, extint_offset;
-
- if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
- gpcon_reg = S3C2410_GPFCON;
- extint_reg = S3C24XX_EXTINT0;
- gpcon_offset = (data->hwirq) * 2;
- extint_offset = (data->hwirq) * 4;
- } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
- gpcon_reg = S3C2410_GPGCON;
- extint_reg = S3C24XX_EXTINT1;
- gpcon_offset = (data->hwirq - 8) * 2;
- extint_offset = (data->hwirq - 8) * 4;
- } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
- gpcon_reg = S3C2410_GPGCON;
- extint_reg = S3C24XX_EXTINT2;
- gpcon_offset = (data->hwirq - 8) * 2;
- extint_offset = (data->hwirq - 16) * 4;
- } else {
- return -EINVAL;
- }
-
- return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
- extint_offset, type);
-}
-
-static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
-{
- void __iomem *extint_reg;
- void __iomem *gpcon_reg;
- unsigned long gpcon_offset, extint_offset;
-
- if (data->hwirq <= 3) {
- gpcon_reg = S3C2410_GPFCON;
- extint_reg = S3C24XX_EXTINT0;
- gpcon_offset = (data->hwirq) * 2;
- extint_offset = (data->hwirq) * 4;
- } else {
- return -EINVAL;
- }
-
- return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
- extint_offset, type);
-}
-
-static struct irq_chip s3c_irq_chip = {
- .name = "s3c",
- .irq_ack = s3c_irq_ack,
- .irq_mask = s3c_irq_mask,
- .irq_unmask = s3c_irq_unmask,
- .irq_set_type = s3c_irq_type,
- .irq_set_wake = s3c_irq_wake
-};
-
-static struct irq_chip s3c_irq_level_chip = {
- .name = "s3c-level",
- .irq_mask = s3c_irq_mask,
- .irq_unmask = s3c_irq_unmask,
- .irq_ack = s3c_irq_ack,
- .irq_set_type = s3c_irq_type,
-};
-
-static struct irq_chip s3c_irqext_chip = {
- .name = "s3c-ext",
- .irq_mask = s3c_irq_mask,
- .irq_unmask = s3c_irq_unmask,
- .irq_ack = s3c_irq_ack,
- .irq_set_type = s3c_irqext_type,
- .irq_set_wake = s3c_irqext_wake
-};
-
-static struct irq_chip s3c_irq_eint0t4 = {
- .name = "s3c-ext0",
- .irq_ack = s3c_irq_ack,
- .irq_mask = s3c_irq_mask,
- .irq_unmask = s3c_irq_unmask,
- .irq_set_wake = s3c_irq_wake,
- .irq_set_type = s3c_irqext0_type,
-};
-
-static void s3c_irq_demux(struct irq_desc *desc)
-{
- struct irq_chip *chip = irq_desc_get_chip(desc);
- struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
- struct s3c_irq_intc *intc = irq_data->intc;
- struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
- unsigned int n, offset;
- unsigned long src, msk;
-
- /* we're using individual domains for the non-dt case
- * and one big domain for the dt case where the subintc
- * starts at hwirq number 32.
- */
- offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
-
- chained_irq_enter(chip, desc);
-
- src = readl_relaxed(sub_intc->reg_pending);
- msk = readl_relaxed(sub_intc->reg_mask);
-
- src &= ~msk;
- src &= irq_data->sub_bits;
-
- while (src) {
- n = __ffs(src);
- src &= ~(1 << n);
- generic_handle_domain_irq(sub_intc->domain, offset + n);
- }
-
- chained_irq_exit(chip, desc);
-}
-
-static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
- struct pt_regs *regs, int intc_offset)
-{
- int pnd;
- int offset;
-
- pnd = readl_relaxed(intc->reg_intpnd);
- if (!pnd)
- return false;
-
- /* non-dt machines use individual domains */
- if (!irq_domain_get_of_node(intc->domain))
- intc_offset = 0;
-
- /* We have a problem that the INTOFFSET register does not always
- * show one interrupt. Occasionally we get two interrupts through
- * the prioritiser, and this causes the INTOFFSET register to show
- * what looks like the logical-or of the two interrupt numbers.
- *
- * Thanks to Klaus, Shannon, et al for helping to debug this problem
- */
- offset = readl_relaxed(intc->reg_intpnd + 4);
-
- /* Find the bit manually, when the offset is wrong.
- * The pending register only ever contains the one bit of the next
- * interrupt to handle.
- */
- if (!(pnd & (1 << offset)))
- offset = __ffs(pnd);
-
- generic_handle_domain_irq(intc->domain, intc_offset + offset);
- return true;
-}
-
-static asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
-{
- do {
- /*
- * For platform based machines, neither ERR nor NULL can happen here.
- * The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds:
- *
- * s3c_intc[0] = s3c24xx_init_intc()
- *
- * If this fails, the next calls to s3c24xx_init_intc() won't be executed.
- *
- * For DT machine, s3c_init_intc_of() could set the IRQ handler without
- * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no
- * such code path, so again the s3c_intc[0] will have a valid pointer if
- * set_handle_irq() is called.
- *
- * Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something.
- */
- if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
- continue;
-
- if (!IS_ERR_OR_NULL(s3c_intc[2]))
- if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
- continue;
-
- break;
- } while (1);
-}
-
-#ifdef CONFIG_FIQ
-/**
- * s3c24xx_set_fiq - set the FIQ routing
- * @irq: IRQ number to route to FIQ on processor.
- * @ack_ptr: pointer to a location for storing the bit mask
- * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
- *
- * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
- * @on is true, the @irq is checked to see if it can be routed and the
- * interrupt controller updated to route the IRQ. If @on is false, the FIQ
- * routing is cleared, regardless of which @irq is specified.
- *
- * returns the mask value for the register.
- */
-int s3c24xx_set_fiq(unsigned int irq, u32 *ack_ptr, bool on)
-{
- u32 intmod;
- unsigned offs;
-
- if (on) {
- offs = irq - FIQ_START;
- if (offs > 31)
- return 0;
-
- intmod = 1 << offs;
- } else {
- intmod = 0;
- }
-
- if (ack_ptr)
- *ack_ptr = intmod;
- writel_relaxed(intmod, S3C2410_INTMOD);
-
- return intmod;
-}
-
-EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
-#endif
-
-static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- struct s3c_irq_intc *intc = h->host_data;
- struct s3c_irq_data *irq_data = &intc->irqs[hw];
- struct s3c_irq_intc *parent_intc;
- struct s3c_irq_data *parent_irq_data;
- unsigned int irqno;
-
- /* attach controller pointer to irq_data */
- irq_data->intc = intc;
- irq_data->offset = hw;
-
- parent_intc = intc->parent;
-
- /* set handler and flags */
- switch (irq_data->type) {
- case S3C_IRQTYPE_NONE:
- return 0;
- case S3C_IRQTYPE_EINT:
- /* On the S3C2412, the EINT0to3 have a parent irq
- * but need the s3c_irq_eint0t4 chip
- */
- if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
- irq_set_chip_and_handler(virq, &s3c_irqext_chip,
- handle_edge_irq);
- else
- irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
- handle_edge_irq);
- break;
- case S3C_IRQTYPE_EDGE:
- if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
- irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
- handle_edge_irq);
- else
- irq_set_chip_and_handler(virq, &s3c_irq_chip,
- handle_edge_irq);
- break;
- case S3C_IRQTYPE_LEVEL:
- if (parent_intc)
- irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
- handle_level_irq);
- else
- irq_set_chip_and_handler(virq, &s3c_irq_chip,
- handle_level_irq);
- break;
- default:
- pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
- return -EINVAL;
- }
-
- irq_set_chip_data(virq, irq_data);
-
- if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
- if (irq_data->parent_irq > 31) {
- pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
- irq_data->parent_irq);
- return -EINVAL;
- }
-
- parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
- parent_irq_data->sub_intc = intc;
- parent_irq_data->sub_bits |= (1UL << hw);
-
- /* attach the demuxer to the parent irq */
- irqno = irq_find_mapping(parent_intc->domain,
- irq_data->parent_irq);
- if (!irqno) {
- pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
- irq_data->parent_irq);
- return -EINVAL;
- }
- irq_set_chained_handler(irqno, s3c_irq_demux);
- }
-
- return 0;
-}
-
-static const struct irq_domain_ops s3c24xx_irq_ops = {
- .map = s3c24xx_irq_map,
- .xlate = irq_domain_xlate_twocell,
-};
-
-static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
-{
- void __iomem *reg_source;
- unsigned long pend;
- unsigned long last;
- int i;
-
- /* if intpnd is set, read the next pending irq from there */
- reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
-
- last = 0;
- for (i = 0; i < 4; i++) {
- pend = readl_relaxed(reg_source);
-
- if (pend == 0 || pend == last)
- break;
-
- writel_relaxed(pend, intc->reg_pending);
- if (intc->reg_intpnd)
- writel_relaxed(pend, intc->reg_intpnd);
-
- pr_info("irq: clearing pending status %08x\n", (int)pend);
- last = pend;
- }
-}
-
-static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
- struct s3c_irq_data *irq_data,
- struct s3c_irq_intc *parent,
- unsigned long address)
-{
- struct s3c_irq_intc *intc;
- void __iomem *base = (void *)0xf6000000; /* static mapping */
- int irq_num;
- int irq_start;
- int ret;
-
- intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
- if (!intc)
- return ERR_PTR(-ENOMEM);
-
- intc->irqs = irq_data;
-
- if (parent)
- intc->parent = parent;
-
- /* select the correct data for the controller.
- * Need to hard code the irq num start and offset
- * to preserve the static mapping for now
- */
- switch (address) {
- case 0x4a000000:
- pr_debug("irq: found main intc\n");
- intc->reg_pending = base;
- intc->reg_mask = base + 0x08;
- intc->reg_intpnd = base + 0x10;
- irq_num = 32;
- irq_start = S3C2410_IRQ(0);
- break;
- case 0x4a000018:
- pr_debug("irq: found subintc\n");
- intc->reg_pending = base + 0x18;
- intc->reg_mask = base + 0x1c;
- irq_num = 29;
- irq_start = S3C2410_IRQSUB(0);
- break;
- case 0x4a000040:
- pr_debug("irq: found intc2\n");
- intc->reg_pending = base + 0x40;
- intc->reg_mask = base + 0x48;
- intc->reg_intpnd = base + 0x50;
- irq_num = 8;
- irq_start = S3C2416_IRQ(0);
- break;
- case 0x560000a4:
- pr_debug("irq: found eintc\n");
- base = (void *)0xfd000000;
-
- intc->reg_mask = base + 0xa4;
- intc->reg_pending = base + 0xa8;
- irq_num = 24;
- irq_start = S3C2410_IRQ(32);
- break;
- default:
- pr_err("irq: unsupported controller address\n");
- ret = -EINVAL;
- goto err;
- }
-
- /* now that all the data is complete, init the irq-domain */
- s3c24xx_clear_intc(intc);
- intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
- 0, &s3c24xx_irq_ops,
- intc);
- if (!intc->domain) {
- pr_err("irq: could not create irq-domain\n");
- ret = -EINVAL;
- goto err;
- }
-
- set_handle_irq(s3c24xx_handle_irq);
-
- return intc;
-
-err:
- kfree(intc);
- return ERR_PTR(ret);
-}
-
-static struct s3c_irq_data __maybe_unused init_eint[32] = {
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
-};
-
-#ifdef CONFIG_CPU_S3C2410
-static struct s3c_irq_data init_s3c2410base[32] = {
- { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
- { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
- { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2410subint[32] = {
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-};
-
-void __init s3c2410_init_irq(void)
-{
-#ifdef CONFIG_FIQ
- init_FIQ(FIQ_START);
-#endif
-
- s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
- 0x4a000000);
- if (IS_ERR(s3c_intc[0])) {
- pr_err("irq: could not create main interrupt controller\n");
- return;
- }
-
- s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
- s3c_intc[0], 0x4a000018);
- s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
-}
-#endif
-
-#ifdef CONFIG_CPU_S3C2412
-static struct s3c_irq_data init_s3c2412base[32] = {
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
- { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
- { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2412eint[32] = {
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
- { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
-};
-
-static struct s3c_irq_data init_s3c2412subint[32] = {
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
- { .type = S3C_IRQTYPE_NONE, },
- { .type = S3C_IRQTYPE_NONE, },
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
-};
-
-void __init s3c2412_init_irq(void)
-{
- pr_info("S3C2412: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
- init_FIQ(FIQ_START);
-#endif
-
- s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
- 0x4a000000);
- if (IS_ERR(s3c_intc[0])) {
- pr_err("irq: could not create main interrupt controller\n");
- return;
- }
-
- s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
- s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
- s3c_intc[0], 0x4a000018);
-}
-#endif
-
-#ifdef CONFIG_CPU_S3C2416
-static struct s3c_irq_data init_s3c2416base[32] = {
- { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
- { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
- { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
- { .type = S3C_IRQTYPE_NONE, }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
- { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
- { .type = S3C_IRQTYPE_NONE, },
- { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2416subint[32] = {
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-static struct s3c_irq_data init_s3c2416_second[32] = {
- { .type = S3C_IRQTYPE_EDGE }, /* 2D */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
-};
-
-void __init s3c2416_init_irq(void)
-{
- pr_info("S3C2416: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
- init_FIQ(FIQ_START);
-#endif
-
- s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
- 0x4a000000);
- if (IS_ERR(s3c_intc[0])) {
- pr_err("irq: could not create main interrupt controller\n");
- return;
- }
-
- s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
- s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
- s3c_intc[0], 0x4a000018);
-
- s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
- NULL, 0x4a000040);
-}
-
-#endif
-
-#ifdef CONFIG_CPU_S3C2440
-static struct s3c_irq_data init_s3c2440base[32] = {
- { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
- { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
- { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
- { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2440subint[32] = {
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-void __init s3c2440_init_irq(void)
-{
- pr_info("S3C2440: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
- init_FIQ(FIQ_START);
-#endif
-
- s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
- 0x4a000000);
- if (IS_ERR(s3c_intc[0])) {
- pr_err("irq: could not create main interrupt controller\n");
- return;
- }
-
- s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
- s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
- s3c_intc[0], 0x4a000018);
-}
-#endif
-
-#ifdef CONFIG_CPU_S3C2442
-static struct s3c_irq_data init_s3c2442base[32] = {
- { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
- { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
- { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
- { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2442subint[32] = {
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
-};
-
-void __init s3c2442_init_irq(void)
-{
- pr_info("S3C2442: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
- init_FIQ(FIQ_START);
-#endif
-
- s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
- 0x4a000000);
- if (IS_ERR(s3c_intc[0])) {
- pr_err("irq: could not create main interrupt controller\n");
- return;
- }
-
- s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
- s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
- s3c_intc[0], 0x4a000018);
-}
-#endif
-
-#ifdef CONFIG_CPU_S3C2443
-static struct s3c_irq_data init_s3c2443base[32] = {
- { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
- { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
- { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
- { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
- { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
- { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
- { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
- { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
- { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
- { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
- { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
- { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
- { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-
-static struct s3c_irq_data init_s3c2443subint[32] = {
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
- { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
- { .type = S3C_IRQTYPE_NONE }, /* reserved */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
- { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-void __init s3c2443_init_irq(void)
-{
- pr_info("S3C2443: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
- init_FIQ(FIQ_START);
-#endif
-
- s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
- 0x4a000000);
- if (IS_ERR(s3c_intc[0])) {
- pr_err("irq: could not create main interrupt controller\n");
- return;
- }
-
- s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
- s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
- s3c_intc[0], 0x4a000018);
-}
-#endif
-
-#ifdef CONFIG_OF
-static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- unsigned int ctrl_num = hw / 32;
- unsigned int intc_hw = hw % 32;
- struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
- struct s3c_irq_intc *parent_intc = intc->parent;
- struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
-
- /* attach controller pointer to irq_data */
- irq_data->intc = intc;
- irq_data->offset = intc_hw;
-
- if (!parent_intc)
- irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
- else
- irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
- handle_edge_irq);
-
- irq_set_chip_data(virq, irq_data);
-
- return 0;
-}
-
-/* Translate our of irq notation
- * format: <ctrl_num ctrl_irq parent_irq type>
- */
-static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
- const u32 *intspec, unsigned int intsize,
- irq_hw_number_t *out_hwirq, unsigned int *out_type)
-{
- struct s3c_irq_intc *intc;
- struct s3c_irq_intc *parent_intc;
- struct s3c_irq_data *irq_data;
- struct s3c_irq_data *parent_irq_data;
- int irqno;
-
- if (WARN_ON(intsize < 4))
- return -EINVAL;
-
- if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
- pr_err("controller number %d invalid\n", intspec[0]);
- return -EINVAL;
- }
- intc = s3c_intc[intspec[0]];
-
- *out_hwirq = intspec[0] * 32 + intspec[2];
- *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
-
- parent_intc = intc->parent;
- if (parent_intc) {
- irq_data = &intc->irqs[intspec[2]];
- irq_data->parent_irq = intspec[1];
- parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
- parent_irq_data->sub_intc = intc;
- parent_irq_data->sub_bits |= (1UL << intspec[2]);
-
- /* parent_intc is always s3c_intc[0], so no offset */
- irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
- if (irqno < 0) {
- pr_err("irq: could not map parent interrupt\n");
- return irqno;
- }
-
- irq_set_chained_handler(irqno, s3c_irq_demux);
- }
-
- return 0;
-}
-
-static const struct irq_domain_ops s3c24xx_irq_ops_of = {
- .map = s3c24xx_irq_map_of,
- .xlate = s3c24xx_irq_xlate_of,
-};
-
-struct s3c24xx_irq_of_ctrl {
- char *name;
- unsigned long offset;
- struct s3c_irq_intc **handle;
- struct s3c_irq_intc **parent;
- struct irq_domain_ops *ops;
-};
-
-static int __init s3c_init_intc_of(struct device_node *np,
- struct device_node *interrupt_parent,
- struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
-{
- struct s3c_irq_intc *intc;
- struct s3c24xx_irq_of_ctrl *ctrl;
- struct irq_domain *domain;
- void __iomem *reg_base;
- int i;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_err("irq-s3c24xx: could not map irq registers\n");
- return -EINVAL;
- }
-
- domain = irq_domain_add_linear(np, num_ctrl * 32,
- &s3c24xx_irq_ops_of, NULL);
- if (!domain) {
- pr_err("irq: could not create irq-domain\n");
- return -EINVAL;
- }
-
- for (i = 0; i < num_ctrl; i++) {
- ctrl = &s3c_ctrl[i];
-
- pr_debug("irq: found controller %s\n", ctrl->name);
-
- intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
- if (!intc)
- return -ENOMEM;
-
- intc->domain = domain;
- intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data),
- GFP_KERNEL);
- if (!intc->irqs) {
- kfree(intc);
- return -ENOMEM;
- }
-
- if (ctrl->parent) {
- intc->reg_pending = reg_base + ctrl->offset;
- intc->reg_mask = reg_base + ctrl->offset + 0x4;
-
- if (*(ctrl->parent)) {
- intc->parent = *(ctrl->parent);
- } else {
- pr_warn("irq: parent of %s missing\n",
- ctrl->name);
- kfree(intc->irqs);
- kfree(intc);
- continue;
- }
- } else {
- intc->reg_pending = reg_base + ctrl->offset;
- intc->reg_mask = reg_base + ctrl->offset + 0x08;
- intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
- }
-
- s3c24xx_clear_intc(intc);
- s3c_intc[i] = intc;
- }
-
- set_handle_irq(s3c24xx_handle_irq);
-
- return 0;
-}
-
-static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
- {
- .name = "intc",
- .offset = 0,
- }, {
- .name = "subintc",
- .offset = 0x18,
- .parent = &s3c_intc[0],
- }
-};
-
-static int __init s3c2410_init_intc_of(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- return s3c_init_intc_of(np, interrupt_parent,
- s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
-}
-IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
-
-static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
- {
- .name = "intc",
- .offset = 0,
- }, {
- .name = "subintc",
- .offset = 0x18,
- .parent = &s3c_intc[0],
- }, {
- .name = "intc2",
- .offset = 0x40,
- }
-};
-
-static int __init s3c2416_init_intc_of(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- return s3c_init_intc_of(np, interrupt_parent,
- s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
-}
-IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
-#endif
diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h b/arch/arm/mach-s3c/irqs-s3c64xx.h
index c244e480e6b3..c244e480e6b3 100644
--- a/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h
+++ b/arch/arm/mach-s3c/irqs-s3c64xx.h
diff --git a/arch/arm64/include/asm/xen/page-coherent.h b/arch/arm/mach-s3c/irqs.h
index 27e984977402..3ff0e0963080 100644
--- a/arch/arm64/include/asm/xen/page-coherent.h
+++ b/arch/arm/mach-s3c/irqs.h
@@ -1,2 +1,2 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#include <xen/arm/page-coherent.h>
+#include "irqs-s3c64xx.h"
diff --git a/arch/arm/mach-s3c/mach-amlm5900.c b/arch/arm/mach-s3c/mach-amlm5900.c
deleted file mode 100644
index 94c4512ace17..000000000000
--- a/arch/arm/mach-s3c/mach-amlm5900.c
+++ /dev/null
@@ -1,246 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright (c) 2006 American Microsystems Limited
-// David Anders <danders@amltd.com>
-//
-// @History:
-// derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
-// Ben Dooks <ben@simtec.co.uk>
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/io.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/flash.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <linux/platform_data/fb-s3c2410.h>
-
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include "devs.h"
-#include "cpu.h"
-#include "gpio-cfg.h"
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/physmap.h>
-
-#include "s3c24xx.h"
-
-static struct resource amlm5900_nor_resource =
- DEFINE_RES_MEM(0x00000000, SZ_16M);
-
-static struct mtd_partition amlm5900_mtd_partitions[] = {
- {
- .name = "System",
- .size = 0x240000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- .name = "Kernel",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "Ramdisk",
- .size = 0x300000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "JFFS2",
- .size = 0x9A0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "Settings",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data amlm5900_flash_data = {
- .width = 2,
- .parts = amlm5900_mtd_partitions,
- .nr_parts = ARRAY_SIZE(amlm5900_mtd_partitions),
-};
-
-static struct platform_device amlm5900_device_nor = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &amlm5900_flash_data,
- },
- .num_resources = 1,
- .resource = &amlm5900_nor_resource,
-};
-
-static struct map_desc amlm5900_iodesc[] __initdata = {
-};
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg amlm5900_uartcfgs[] = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- }
-};
-
-static struct gpiod_lookup_table amlm5900_mmc_gpio_table = {
- .dev_id = "s3c2410-sdi",
- .table = {
- /* bus pins */
- GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device *amlm5900_devices[] __initdata = {
-#ifdef CONFIG_FB_S3C2410
- &s3c_device_lcd,
-#endif
- &s3c_device_adc,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_ohci,
- &s3c_device_rtc,
- &s3c_device_usbgadget,
- &s3c_device_sdi,
- &amlm5900_device_nor,
-};
-
-static void __init amlm5900_map_io(void)
-{
- s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
- s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-static void __init amlm5900_init_time(void)
-{
- s3c2410_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-#ifdef CONFIG_FB_S3C2410
-static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
- .width = 160,
- .height = 160,
-
- .type = S3C2410_LCDCON1_STN4,
-
- .pixclock = 680000, /* HCLK = 100MHz */
- .xres = 160,
- .yres = 160,
- .bpp = 4,
- .left_margin = 1 << (4 + 3),
- .right_margin = 8 << 3,
- .hsync_len = 48,
- .upper_margin = 0,
- .lower_margin = 0,
-
- .lcdcon5 = 0x00000001,
-};
-
-static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = {
-
- .displays = &amlm5900_lcd_info,
- .num_displays = 1,
- .default_display = 0,
-
- .gpccon = 0xaaaaaaaa,
- .gpccon_mask = 0xffffffff,
- .gpccon_reg = S3C2410_GPCCON,
- .gpcup = 0x0000ffff,
- .gpcup_mask = 0xffffffff,
- .gpcup_reg = S3C2410_GPCUP,
-
- .gpdcon = 0xaaaaaaaa,
- .gpdcon_mask = 0xffffffff,
- .gpdcon_reg = S3C2410_GPDCON,
- .gpdup = 0x0000ffff,
- .gpdup_mask = 0xffffffff,
- .gpdup_reg = S3C2410_GPDUP,
-};
-#endif
-
-static irqreturn_t
-amlm5900_wake_interrupt(int irq, void *ignored)
-{
- return IRQ_HANDLED;
-}
-
-static void amlm5900_init_pm(void)
-{
- int ret = 0;
-
- ret = request_irq(IRQ_EINT9, &amlm5900_wake_interrupt,
- IRQF_TRIGGER_RISING | IRQF_SHARED,
- "amlm5900_wakeup", &amlm5900_wake_interrupt);
- if (ret != 0) {
- printk(KERN_ERR "AML-M5900: no wakeup irq, %d?\n", ret);
- } else {
- enable_irq_wake(IRQ_EINT9);
- /* configure the suspend/resume status pin */
- s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
- s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP);
- }
-}
-static void __init amlm5900_init(void)
-{
- amlm5900_init_pm();
-#ifdef CONFIG_FB_S3C2410
- s3c24xx_fb_set_platdata(&amlm5900_fb_info);
-#endif
- s3c_i2c0_set_platdata(NULL);
- gpiod_add_lookup_table(&amlm5900_mmc_gpio_table);
- platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
-}
-
-MACHINE_START(AML_M5900, "AML_M5900")
- .atag_offset = 0x100,
- .map_io = amlm5900_map_io,
- .init_irq = s3c2410_init_irq,
- .init_machine = amlm5900_init,
- .init_time = amlm5900_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c
deleted file mode 100644
index 04147cc0adcc..000000000000
--- a/arch/arm/mach-s3c/mach-anubis.c
+++ /dev/null
@@ -1,426 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2003-2009 Simtec Electronics
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/ata_platform.h>
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/sm501.h>
-#include <linux/sm501-regs.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-
-#include <net/ax88796.h>
-
-#include "devs.h"
-#include "cpu.h"
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
-
-#include "anubis.h"
-#include "s3c24xx.h"
-#include "simtec.h"
-
-#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
-
-static struct map_desc anubis_iodesc[] __initdata = {
- /* ISA IO areas */
-
- {
- .virtual = (u32)S3C24XX_VA_ISA_BYTE,
- .pfn = __phys_to_pfn(0x0),
- .length = SZ_4M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)S3C24XX_VA_ISA_WORD,
- .pfn = __phys_to_pfn(0x0),
- .length = SZ_4M,
- .type = MT_DEVICE,
- },
-
- /* we could possibly compress the next set down into a set of smaller tables
- * pagetables, but that would mean using an L2 section, and it still means
- * we cannot actually feed the same register to an LDR due to 16K spacing
- */
-
- /* CPLD control registers */
-
- {
- .virtual = (u32)ANUBIS_VA_CTRL1,
- .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)ANUBIS_VA_IDREG,
- .pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-};
-
-#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
- },
- [1] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
- },
-};
-
-/* NAND Flash on Anubis board */
-
-static int external_map[] = { 2 };
-static int chip0_map[] = { 0 };
-static int chip1_map[] = { 1 };
-
-static struct mtd_partition __initdata anubis_default_nand_part[] = {
- [0] = {
- .name = "Boot Agent",
- .size = SZ_16K,
- .offset = 0,
- },
- [1] = {
- .name = "/boot",
- .size = SZ_4M - SZ_16K,
- .offset = SZ_16K,
- },
- [2] = {
- .name = "user1",
- .offset = SZ_4M,
- .size = SZ_32M - SZ_4M,
- },
- [3] = {
- .name = "user2",
- .offset = SZ_32M,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
- [0] = {
- .name = "Boot Agent",
- .size = SZ_128K,
- .offset = 0,
- },
- [1] = {
- .name = "/boot",
- .size = SZ_4M - SZ_128K,
- .offset = SZ_128K,
- },
- [2] = {
- .name = "user1",
- .offset = SZ_4M,
- .size = SZ_32M - SZ_4M,
- },
- [3] = {
- .name = "user2",
- .offset = SZ_32M,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-/* the Anubis has 3 selectable slots for nand-flash, the two
- * on-board chip areas, as well as the external slot.
- *
- * Note, there is no current hot-plug support for the External
- * socket.
-*/
-
-static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
- [1] = {
- .name = "External",
- .nr_chips = 1,
- .nr_map = external_map,
- .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
- .partitions = anubis_default_nand_part,
- },
- [0] = {
- .name = "chip0",
- .nr_chips = 1,
- .nr_map = chip0_map,
- .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
- .partitions = anubis_default_nand_part,
- },
- [2] = {
- .name = "chip1",
- .nr_chips = 1,
- .nr_map = chip1_map,
- .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
- .partitions = anubis_default_nand_part,
- },
-};
-
-static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
-{
- unsigned int tmp;
-
- slot = set->nr_map[slot] & 3;
-
- pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
- slot, set, set->nr_map);
-
- tmp = __raw_readb(ANUBIS_VA_CTRL1);
- tmp &= ~ANUBIS_CTRL1_NANDSEL;
- tmp |= slot;
-
- pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
-
- __raw_writeb(tmp, ANUBIS_VA_CTRL1);
-}
-
-static struct s3c2410_platform_nand __initdata anubis_nand_info = {
- .tacls = 25,
- .twrph0 = 55,
- .twrph1 = 40,
- .nr_sets = ARRAY_SIZE(anubis_nand_sets),
- .sets = anubis_nand_sets,
- .select_chip = anubis_nand_select,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-/* IDE channels */
-
-static struct pata_platform_info anubis_ide_platdata = {
- .ioport_shift = 5,
-};
-
-static struct resource anubis_ide0_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
- [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
- [3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
-};
-
-static struct platform_device anubis_device_ide0 = {
- .name = "pata_platform",
- .id = 0,
- .num_resources = ARRAY_SIZE(anubis_ide0_resource),
- .resource = anubis_ide0_resource,
- .dev = {
- .platform_data = &anubis_ide_platdata,
- .coherent_dma_mask = ~0,
- },
-};
-
-static struct resource anubis_ide1_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
- [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
- [2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
-};
-
-static struct platform_device anubis_device_ide1 = {
- .name = "pata_platform",
- .id = 1,
- .num_resources = ARRAY_SIZE(anubis_ide1_resource),
- .resource = anubis_ide1_resource,
- .dev = {
- .platform_data = &anubis_ide_platdata,
- .coherent_dma_mask = ~0,
- },
-};
-
-/* Asix AX88796 10/100 ethernet controller */
-
-static struct ax_plat_data anubis_asix_platdata = {
- .flags = AXFLG_MAC_FROMDEV,
- .wordlength = 2,
- .dcr_val = 0x48,
- .rcr_val = 0x40,
-};
-
-static struct resource anubis_asix_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
- [1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
-};
-
-static struct platform_device anubis_device_asix = {
- .name = "ax88796",
- .id = 0,
- .num_resources = ARRAY_SIZE(anubis_asix_resource),
- .resource = anubis_asix_resource,
- .dev = {
- .platform_data = &anubis_asix_platdata,
- }
-};
-
-/* SM501 */
-
-static struct resource anubis_sm501_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
- [1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
- [2] = DEFINE_RES_IRQ(IRQ_EINT0),
-};
-
-static struct sm501_initdata anubis_sm501_initdata = {
- .gpio_high = {
- .set = 0x3F000000, /* 24bit panel */
- .mask = 0x0,
- },
- .misc_timing = {
- .set = 0x010100, /* SDRAM timing */
- .mask = 0x1F1F00,
- },
- .misc_control = {
- .set = SM501_MISC_PNL_24BIT,
- .mask = 0,
- },
-
- .devices = SM501_USE_GPIO,
-
- /* set the SDRAM and bus clocks */
- .mclk = 72 * MHZ,
- .m1xclk = 144 * MHZ,
-};
-
-static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
- [0] = {
- .bus_num = 1,
- .pin_scl = 44,
- .pin_sda = 45,
- },
- [1] = {
- .bus_num = 2,
- .pin_scl = 40,
- .pin_sda = 41,
- },
-};
-
-static struct sm501_platdata anubis_sm501_platdata = {
- .init = &anubis_sm501_initdata,
- .gpio_base = -1,
- .gpio_i2c = anubis_sm501_gpio_i2c,
- .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
-};
-
-static struct platform_device anubis_device_sm501 = {
- .name = "sm501",
- .id = 0,
- .num_resources = ARRAY_SIZE(anubis_sm501_resource),
- .resource = anubis_sm501_resource,
- .dev = {
- .platform_data = &anubis_sm501_platdata,
- },
-};
-
-/* Standard Anubis devices */
-
-static struct platform_device *anubis_devices[] __initdata = {
- &s3c2410_device_dclk,
- &s3c_device_ohci,
- &s3c_device_wdt,
- &s3c_device_adc,
- &s3c_device_i2c0,
- &s3c_device_rtc,
- &s3c_device_nand,
- &anubis_device_ide0,
- &anubis_device_ide1,
- &anubis_device_asix,
- &anubis_device_sm501,
-};
-
-/* I2C devices. */
-
-static struct i2c_board_info anubis_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("tps65011", 0x48),
- .irq = IRQ_EINT20,
- }
-};
-
-/* Audio setup */
-static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
- .have_mic = 1,
- .have_lout = 1,
- .output_cdclk = 1,
- .use_mpllin = 1,
- .amp_gpio = S3C2410_GPB(2),
- .amp_gain[0] = S3C2410_GPD(10),
- .amp_gain[1] = S3C2410_GPD(11),
-};
-
-static void __init anubis_map_io(void)
-{
- s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
- s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-
- /* check for the newer revision boards with large page nand */
-
- if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
- printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
- __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
- anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
- anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
- } else {
- /* ensure that the GPIO is setup */
- gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPA(0));
- }
-}
-
-static void __init anubis_init_time(void)
-{
- s3c2440_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-static void __init anubis_init(void)
-{
- s3c_i2c0_set_platdata(NULL);
- s3c_nand_set_platdata(&anubis_nand_info);
- simtec_audio_add(NULL, false, &anubis_audio);
-
- platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
-
- i2c_register_board_info(0, anubis_i2c_devs,
- ARRAY_SIZE(anubis_i2c_devs));
-}
-
-
-MACHINE_START(ANUBIS, "Simtec-Anubis")
- /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
- .atag_offset = 0x100,
- .map_io = anubis_map_io,
- .init_machine = anubis_init,
- .init_irq = s3c2440_init_irq,
- .init_time = anubis_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-anw6410.c b/arch/arm/mach-s3c/mach-anw6410.c
deleted file mode 100644
index 825714e9ac66..000000000000
--- a/arch/arm/mach-s3c/mach-anw6410.c
+++ /dev/null
@@ -1,230 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2008 Openmoko, Inc.
-// Copyright 2008 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-// http://armlinux.simtec.co.uk/
-// Copyright 2009 Kwangwoo Lee
-// Kwangwoo Lee <kwangwoo.lee@gmail.com>
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/dm9000.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include "map.h"
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include "fb.h"
-
-#include "devs.h"
-#include "cpu.h"
-#include <mach/irqs.h>
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-
-#include "s3c64xx.h"
-#include "regs-modem-s3c64xx.h"
-
-/* DM9000 */
-#define ANW6410_PA_DM9000 (0x18000000)
-
-/* A hardware buffer to control external devices is mapped at 0x30000000.
- * It can not be read. So current status must be kept in anw6410_extdev_status.
- */
-#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
-#define ANW6410_PA_EXTDEV (0x30000000)
-
-#define ANW6410_EN_DM9000 (1<<11)
-#define ANW6410_EN_LCD (1<<14)
-
-static __u32 anw6410_extdev_status;
-
-static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = 0x3c5,
- .ulcon = 0x03,
- .ufcon = 0x51,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = 0x3c5,
- .ulcon = 0x03,
- .ufcon = 0x51,
- },
-};
-
-/* framebuffer and LCD setup. */
-static void __init anw6410_lcd_mode_set(void)
-{
- u32 tmp;
-
- /* set the LCD type */
- tmp = __raw_readl(S3C64XX_SPCON);
- tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
- tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
- __raw_writel(tmp, S3C64XX_SPCON);
-
- /* remove the LCD bypass */
- tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
- tmp &= ~MIFPCON_LCD_BYPASS;
- __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
-}
-
-/* GPF1 = LCD panel power
- * GPF4 = LCD backlight control
- */
-static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
- unsigned int power)
-{
- if (power) {
- anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
- __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
-
- gpio_direction_output(S3C64XX_GPF(1), 1);
- gpio_direction_output(S3C64XX_GPF(4), 1);
- } else {
- anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
- __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
-
- gpio_direction_output(S3C64XX_GPF(1), 0);
- gpio_direction_output(S3C64XX_GPF(4), 0);
- }
-}
-
-static struct plat_lcd_data anw6410_lcd_power_data = {
- .set_power = anw6410_lcd_power_set,
-};
-
-static struct platform_device anw6410_lcd_powerdev = {
- .name = "platform-lcd",
- .dev.parent = &s3c_device_fb.dev,
- .dev.platform_data = &anw6410_lcd_power_data,
-};
-
-static struct s3c_fb_pd_win anw6410_fb_win0 = {
- .max_bpp = 32,
- .default_bpp = 16,
- .xres = 800,
- .yres = 480,
-};
-
-static struct fb_videomode anw6410_lcd_timing = {
- .left_margin = 8,
- .right_margin = 13,
- .upper_margin = 7,
- .lower_margin = 5,
- .hsync_len = 3,
- .vsync_len = 1,
- .xres = 800,
- .yres = 480,
-};
-
-/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
-static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
- .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
- .vtiming = &anw6410_lcd_timing,
- .win[0] = &anw6410_fb_win0,
- .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
- .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-};
-
-/* DM9000AEP 10/100 ethernet controller */
-static void __init anw6410_dm9000_enable(void)
-{
- anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
- __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
-}
-
-static struct resource anw6410_dm9000_resource[] = {
- [0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
- [1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
- [2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
- | IRQF_TRIGGER_HIGH),
-};
-
-static struct dm9000_plat_data anw6410_dm9000_pdata = {
- .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
- /* dev_addr can be set to provide hwaddr. */
-};
-
-static struct platform_device anw6410_device_eth = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
- .resource = anw6410_dm9000_resource,
- .dev = {
- .platform_data = &anw6410_dm9000_pdata,
- },
-};
-
-static struct map_desc anw6410_iodesc[] __initdata = {
- {
- .virtual = (unsigned long)ANW6410_VA_EXTDEV,
- .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
- .length = SZ_64K,
- .type = MT_DEVICE,
- },
-};
-
-static struct platform_device *anw6410_devices[] __initdata = {
- &s3c_device_fb,
- &anw6410_lcd_powerdev,
- &anw6410_device_eth,
-};
-
-static void __init anw6410_map_io(void)
-{
- s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
- s3c64xx_set_xtal_freq(12000000);
- s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
- s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
-
- anw6410_lcd_mode_set();
-}
-
-static void __init anw6410_machine_init(void)
-{
- s3c_fb_set_platdata(&anw6410_lcd_pdata);
-
- gpio_request(S3C64XX_GPF(1), "panel power");
- gpio_request(S3C64XX_GPF(4), "LCD backlight");
-
- anw6410_dm9000_enable();
-
- platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
-}
-
-MACHINE_START(ANW6410, "A&W6410")
- /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
- .atag_offset = 0x100,
- .nr_irqs = S3C64XX_NR_IRQS,
- .init_irq = s3c6410_init_irq,
- .map_io = anw6410_map_io,
- .init_machine = anw6410_machine_init,
- .init_time = s3c64xx_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c
deleted file mode 100644
index c6a5a51d84aa..000000000000
--- a/arch/arm/mach-s3c/mach-at2440evb.c
+++ /dev/null
@@ -1,232 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
-// Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
-// and modifications by SBZ <sbz@spgui.org> and
-// Weibing <http://weibing.blogbus.com>
-//
-// For product information, visit http://www.arm.com/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/gpio/machine.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/dm9000.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <linux/platform_data/fb-s3c2410.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-
-#include "devs.h"
-#include "cpu.h"
-#include <linux/platform_data/mmc-s3cmci.h>
-
-#include "s3c24xx.h"
-
-static struct map_desc at2440evb_iodesc[] __initdata = {
- /* Nothing here */
-};
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
-#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
-
-static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
- },
-};
-
-/* NAND Flash on AT2440EVB board */
-
-static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
- [0] = {
- .name = "Boot Agent",
- .size = SZ_256K,
- .offset = 0,
- },
- [1] = {
- .name = "Kernel",
- .size = SZ_2M,
- .offset = SZ_256K,
- },
- [2] = {
- .name = "Root",
- .offset = SZ_256K + SZ_2M,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
- [0] = {
- .name = "nand",
- .nr_chips = 1,
- .nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part),
- .partitions = at2440evb_default_nand_part,
- },
-};
-
-static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
- .tacls = 25,
- .twrph0 = 55,
- .twrph1 = 40,
- .nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
- .sets = at2440evb_nand_sets,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-/* DM9000AEP 10/100 ethernet controller */
-
-static struct resource at2440evb_dm9k_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS3, 4),
- [1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4),
- [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
- | IORESOURCE_IRQ_HIGHEDGE),
-};
-
-static struct dm9000_plat_data at2440evb_dm9k_pdata = {
- .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
-};
-
-static struct platform_device at2440evb_device_eth = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(at2440evb_dm9k_resource),
- .resource = at2440evb_dm9k_resource,
- .dev = {
- .platform_data = &at2440evb_dm9k_pdata,
- },
-};
-
-static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
- .set_power = s3c24xx_mci_def_set_power,
-};
-
-static struct gpiod_lookup_table at2440evb_mci_gpio_table = {
- .dev_id = "s3c2410-sdi",
- .table = {
- /* Card detect S3C2410_GPG(10) */
- GPIO_LOOKUP("GPIOG", 10, "cd", GPIO_ACTIVE_LOW),
- /* bus pins */
- GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-
-/* 7" LCD panel */
-
-static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
-
- .lcdcon5 = S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_PWREN |
- S3C2410_LCDCON5_HWSWP,
-
- .type = S3C2410_LCDCON1_TFT,
-
- .width = 800,
- .height = 480,
-
- .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
- .xres = 800,
- .yres = 480,
- .bpp = 16,
- .left_margin = 88,
- .right_margin = 40,
- .hsync_len = 128,
- .upper_margin = 32,
- .lower_margin = 11,
- .vsync_len = 2,
-};
-
-static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
- .displays = &at2440evb_lcd_cfg,
- .num_displays = 1,
- .default_display = 0,
-};
-
-static struct platform_device *at2440evb_devices[] __initdata = {
- &s3c_device_ohci,
- &s3c_device_wdt,
- &s3c_device_adc,
- &s3c_device_i2c0,
- &s3c_device_rtc,
- &s3c_device_nand,
- &s3c_device_sdi,
- &s3c_device_lcd,
- &at2440evb_device_eth,
-};
-
-static void __init at2440evb_map_io(void)
-{
- s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
- s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-static void __init at2440evb_init_time(void)
-{
- s3c2440_init_clocks(16934400);
- s3c24xx_timer_init();
-}
-
-static void __init at2440evb_init(void)
-{
- s3c24xx_fb_set_platdata(&at2440evb_fb_info);
- gpiod_add_lookup_table(&at2440evb_mci_gpio_table);
- s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
- s3c_nand_set_platdata(&at2440evb_nand_info);
- s3c_i2c0_set_platdata(NULL);
-
- platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
-}
-
-
-MACHINE_START(AT2440EVB, "AT2440EVB")
- .atag_offset = 0x100,
- .map_io = at2440evb_map_io,
- .init_machine = at2440evb_init,
- .init_irq = s3c2440_init_irq,
- .init_time = at2440evb_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c
deleted file mode 100644
index 27e8d5950228..000000000000
--- a/arch/arm/mach-s3c/mach-bast.c
+++ /dev/null
@@ -1,587 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2003-2008 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-//
-// http://www.simtec.co.uk/products/EB2410ITX/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/syscore_ops.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/dm9000.h>
-#include <linux/ata_platform.h>
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/serial_8250.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-
-#include <linux/platform_data/asoc-s3c24xx_simtec.h>
-#include <linux/platform_data/hwmon-s3c.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-
-#include <net/ax88796.h>
-
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach-types.h>
-
-#include <linux/platform_data/fb-s3c2410.h>
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-
-#include "cpu.h"
-#include <linux/soc/samsung/s3c-cpu-freq.h>
-#include "devs.h"
-#include "gpio-cfg.h"
-
-#include "bast.h"
-#include "s3c24xx.h"
-#include "simtec.h"
-
-#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
-
-/* macros for virtual address mods for the io space entries */
-#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
-#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
-#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
-#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
-
-/* macros to modify the physical addresses for io space */
-
-#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
-#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
-#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
-#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
-
-static struct map_desc bast_iodesc[] __initdata = {
- /* ISA IO areas */
- {
- .virtual = (u32)S3C24XX_VA_ISA_BYTE,
- .pfn = PA_CS2(BAST_PA_ISAIO),
- .length = SZ_16M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)S3C24XX_VA_ISA_WORD,
- .pfn = PA_CS3(BAST_PA_ISAIO),
- .length = SZ_16M,
- .type = MT_DEVICE,
- },
- /* bast CPLD control registers, and external interrupt controls */
- {
- .virtual = (u32)BAST_VA_CTRL1,
- .pfn = __phys_to_pfn(BAST_PA_CTRL1),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)BAST_VA_CTRL2,
- .pfn = __phys_to_pfn(BAST_PA_CTRL2),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)BAST_VA_CTRL3,
- .pfn = __phys_to_pfn(BAST_PA_CTRL3),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)BAST_VA_CTRL4,
- .pfn = __phys_to_pfn(BAST_PA_CTRL4),
- .length = SZ_1M,
- .type = MT_DEVICE,
- },
- /* PC104 IRQ mux */
- {
- .virtual = (u32)BAST_VA_PC104_IRQREQ,
- .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)BAST_VA_PC104_IRQRAW,
- .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)BAST_VA_PC104_IRQMASK,
- .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
- .length = SZ_1M,
- .type = MT_DEVICE,
- },
-
- /* peripheral space... one for each of fast/slow/byte/16bit */
- /* note, ide is only decoded in word space, even though some registers
- * are only 8bit */
-
- /* slow, byte */
- { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
- { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
- { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
-
- /* slow, word */
- { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
- { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
- { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
-
- /* fast, byte */
- { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
- { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
- { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
-
- /* fast, word */
- { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
- { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
- { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
-};
-
-#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- /* port 2 is not actually used */
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- }
-};
-
-/* NAND Flash on BAST board */
-
-#ifdef CONFIG_PM
-static int bast_pm_suspend(void)
-{
- /* ensure that an nRESET is not generated on resume. */
- gpio_direction_output(S3C2410_GPA(21), 1);
- return 0;
-}
-
-static void bast_pm_resume(void)
-{
- s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
-}
-
-#else
-#define bast_pm_suspend NULL
-#define bast_pm_resume NULL
-#endif
-
-static struct syscore_ops bast_pm_syscore_ops = {
- .suspend = bast_pm_suspend,
- .resume = bast_pm_resume,
-};
-
-static int smartmedia_map[] = { 0 };
-static int chip0_map[] = { 1 };
-static int chip1_map[] = { 2 };
-static int chip2_map[] = { 3 };
-
-static struct mtd_partition __initdata bast_default_nand_part[] = {
- [0] = {
- .name = "Boot Agent",
- .size = SZ_16K,
- .offset = 0,
- },
- [1] = {
- .name = "/boot",
- .size = SZ_4M - SZ_16K,
- .offset = SZ_16K,
- },
- [2] = {
- .name = "user",
- .offset = SZ_4M,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-/* the bast has 4 selectable slots for nand-flash, the three
- * on-board chip areas, as well as the external SmartMedia
- * slot.
- *
- * Note, there is no current hot-plug support for the SmartMedia
- * socket.
-*/
-
-static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
- [0] = {
- .name = "SmartMedia",
- .nr_chips = 1,
- .nr_map = smartmedia_map,
- .options = NAND_SCAN_SILENT_NODEV,
- .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
- .partitions = bast_default_nand_part,
- },
- [1] = {
- .name = "chip0",
- .nr_chips = 1,
- .nr_map = chip0_map,
- .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
- .partitions = bast_default_nand_part,
- },
- [2] = {
- .name = "chip1",
- .nr_chips = 1,
- .nr_map = chip1_map,
- .options = NAND_SCAN_SILENT_NODEV,
- .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
- .partitions = bast_default_nand_part,
- },
- [3] = {
- .name = "chip2",
- .nr_chips = 1,
- .nr_map = chip2_map,
- .options = NAND_SCAN_SILENT_NODEV,
- .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
- .partitions = bast_default_nand_part,
- }
-};
-
-static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
-{
- unsigned int tmp;
-
- slot = set->nr_map[slot] & 3;
-
- pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
- slot, set, set->nr_map);
-
- tmp = __raw_readb(BAST_VA_CTRL2);
- tmp &= BAST_CPLD_CTLR2_IDERST;
- tmp |= slot;
- tmp |= BAST_CPLD_CTRL2_WNAND;
-
- pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
-
- __raw_writeb(tmp, BAST_VA_CTRL2);
-}
-
-static struct s3c2410_platform_nand __initdata bast_nand_info = {
- .tacls = 30,
- .twrph0 = 60,
- .twrph1 = 60,
- .nr_sets = ARRAY_SIZE(bast_nand_sets),
- .sets = bast_nand_sets,
- .select_chip = bast_nand_select,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-/* DM9000 */
-
-static struct resource bast_dm9k_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
- [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
- [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
- | IORESOURCE_IRQ_HIGHLEVEL),
-};
-
-/* for the moment we limit ourselves to 16bit IO until some
- * better IO routines can be written and tested
-*/
-
-static struct dm9000_plat_data bast_dm9k_platdata = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device bast_device_dm9k = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(bast_dm9k_resource),
- .resource = bast_dm9k_resource,
- .dev = {
- .platform_data = &bast_dm9k_platdata,
- }
-};
-
-/* serial devices */
-
-#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
-#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
-#define SERIAL_CLK (1843200)
-
-static struct plat_serial8250_port bast_sio_data[] = {
- [0] = {
- .mapbase = SERIAL_BASE + 0x2f8,
- .irq = BAST_IRQ_PCSERIAL1,
- .flags = SERIAL_FLAGS,
- .iotype = UPIO_MEM,
- .regshift = 0,
- .uartclk = SERIAL_CLK,
- },
- [1] = {
- .mapbase = SERIAL_BASE + 0x3f8,
- .irq = BAST_IRQ_PCSERIAL2,
- .flags = SERIAL_FLAGS,
- .iotype = UPIO_MEM,
- .regshift = 0,
- .uartclk = SERIAL_CLK,
- },
- { }
-};
-
-static struct platform_device bast_sio = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = &bast_sio_data,
- },
-};
-
-/* we have devices on the bus which cannot work much over the
- * standard 100KHz i2c bus frequency
-*/
-
-static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
- .flags = 0,
- .slave_addr = 0x10,
- .frequency = 100*1000,
-};
-
-/* Asix AX88796 10/100 ethernet controller */
-
-static struct ax_plat_data bast_asix_platdata = {
- .flags = AXFLG_MAC_FROMDEV,
- .wordlength = 2,
- .dcr_val = 0x48,
- .rcr_val = 0x40,
-};
-
-static struct resource bast_asix_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
- [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
- [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
-};
-
-static struct platform_device bast_device_asix = {
- .name = "ax88796",
- .id = 0,
- .num_resources = ARRAY_SIZE(bast_asix_resource),
- .resource = bast_asix_resource,
- .dev = {
- .platform_data = &bast_asix_platdata
- }
-};
-
-/* Asix AX88796 10/100 ethernet controller parallel port */
-
-static struct resource bast_asixpp_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
- 0x30 * 0x20),
-};
-
-static struct platform_device bast_device_axpp = {
- .name = "ax88796-pp",
- .id = 0,
- .num_resources = ARRAY_SIZE(bast_asixpp_resource),
- .resource = bast_asixpp_resource,
-};
-
-/* LCD/VGA controller */
-
-static struct s3c2410fb_display __initdata bast_lcd_info[] = {
- {
- .type = S3C2410_LCDCON1_TFT,
- .width = 640,
- .height = 480,
-
- .pixclock = 33333,
- .xres = 640,
- .yres = 480,
- .bpp = 4,
- .left_margin = 40,
- .right_margin = 20,
- .hsync_len = 88,
- .upper_margin = 30,
- .lower_margin = 32,
- .vsync_len = 3,
-
- .lcdcon5 = 0x00014b02,
- },
- {
- .type = S3C2410_LCDCON1_TFT,
- .width = 640,
- .height = 480,
-
- .pixclock = 33333,
- .xres = 640,
- .yres = 480,
- .bpp = 8,
- .left_margin = 40,
- .right_margin = 20,
- .hsync_len = 88,
- .upper_margin = 30,
- .lower_margin = 32,
- .vsync_len = 3,
-
- .lcdcon5 = 0x00014b02,
- },
- {
- .type = S3C2410_LCDCON1_TFT,
- .width = 640,
- .height = 480,
-
- .pixclock = 33333,
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .left_margin = 40,
- .right_margin = 20,
- .hsync_len = 88,
- .upper_margin = 30,
- .lower_margin = 32,
- .vsync_len = 3,
-
- .lcdcon5 = 0x00014b02,
- },
-};
-
-/* LCD/VGA controller */
-
-static struct s3c2410fb_mach_info __initdata bast_fb_info = {
-
- .displays = bast_lcd_info,
- .num_displays = ARRAY_SIZE(bast_lcd_info),
- .default_display = 1,
-};
-
-/* I2C devices fitted. */
-
-static struct i2c_board_info bast_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("tlv320aic23", 0x1a),
- }, {
- I2C_BOARD_INFO("simtec-pmu", 0x6b),
- }, {
- I2C_BOARD_INFO("ch7013", 0x75),
- },
-};
-
-static struct s3c_hwmon_pdata bast_hwmon_info = {
- /* LCD contrast (0-6.6V) */
- .in[0] = &(struct s3c_hwmon_chcfg) {
- .name = "lcd-contrast",
- .mult = 3300,
- .div = 512,
- },
- /* LED current feedback */
- .in[1] = &(struct s3c_hwmon_chcfg) {
- .name = "led-feedback",
- .mult = 3300,
- .div = 1024,
- },
- /* LCD feedback (0-6.6V) */
- .in[2] = &(struct s3c_hwmon_chcfg) {
- .name = "lcd-feedback",
- .mult = 3300,
- .div = 512,
- },
- /* Vcore (1.8-2.0V), Vref 3.3V */
- .in[3] = &(struct s3c_hwmon_chcfg) {
- .name = "vcore",
- .mult = 3300,
- .div = 1024,
- },
-};
-
-/* Standard BAST devices */
-// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
-
-static struct platform_device *bast_devices[] __initdata = {
- &s3c2410_device_dclk,
- &s3c_device_ohci,
- &s3c_device_lcd,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_rtc,
- &s3c_device_nand,
- &s3c_device_adc,
- &s3c_device_hwmon,
- &bast_device_dm9k,
- &bast_device_asix,
- &bast_device_axpp,
- &bast_sio,
-};
-
-static struct s3c_cpufreq_board __initdata bast_cpufreq = {
- .refresh = 7800, /* 7.8usec */
- .auto_io = 1,
- .need_io = 1,
-};
-
-static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
- .have_mic = 1,
- .have_lout = 1,
-};
-
-static void __init bast_map_io(void)
-{
- s3c_hwmon_set_platdata(&bast_hwmon_info);
-
- s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
- s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-static void __init bast_init_time(void)
-{
- s3c2410_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-static void __init bast_init(void)
-{
- register_syscore_ops(&bast_pm_syscore_ops);
-
- s3c_i2c0_set_platdata(&bast_i2c_info);
- s3c_nand_set_platdata(&bast_nand_info);
- s3c24xx_fb_set_platdata(&bast_fb_info);
- platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
-
- i2c_register_board_info(0, bast_i2c_devs,
- ARRAY_SIZE(bast_i2c_devs));
-
- usb_simtec_init();
- nor_simtec_init();
- simtec_audio_add(NULL, true, &bast_audio);
-
- WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
-
- s3c_cpufreq_setboard(&bast_cpufreq);
-}
-
-MACHINE_START(BAST, "Simtec-BAST")
- /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
- .atag_offset = 0x100,
- .map_io = bast_map_io,
- .init_irq = s3c2410_init_irq,
- .init_machine = bast_init,
- .init_time = bast_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c
index 5d1d4b67a4b7..4edde13b89b5 100644
--- a/arch/arm/mach-s3c/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c/mach-crag6410-module.c
@@ -28,7 +28,7 @@
#include <linux/platform_data/spi-s3c64xx.h>
#include "cpu.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "crag6410.h"
diff --git a/arch/arm/mach-s3c/mach-crag6410.c b/arch/arm/mach-s3c/mach-crag6410.c
index e3e0fe897bcc..7c4bed4370a1 100644
--- a/arch/arm/mach-s3c/mach-crag6410.c
+++ b/arch/arm/mach-s3c/mach-crag6410.c
@@ -14,6 +14,7 @@
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/input-event-codes.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/leds.h>
@@ -47,7 +48,7 @@
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "fb.h"
#include "sdhci.h"
@@ -57,7 +58,6 @@
#include "keypad.h"
#include "devs.h"
#include "cpu.h"
-#include <linux/soc/samsung/s3c-adc.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include "pm.h"
diff --git a/arch/arm/mach-s3c/mach-gta02.c b/arch/arm/mach-s3c/mach-gta02.c
deleted file mode 100644
index 418939ce0fc3..000000000000
--- a/arch/arm/mach-s3c/mach-gta02.c
+++ /dev/null
@@ -1,579 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// S3C2442 Machine Support for Openmoko GTA02 / FreeRunner.
-//
-// Copyright (C) 2006-2009 by Openmoko, Inc.
-// Authors: Harald Welte <laforge@openmoko.org>
-// Andy Green <andy@openmoko.org>
-// Werner Almesberger <werner@openmoko.org>
-// All rights reserved.
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/delay.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/workqueue.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-
-#include <linux/mmc/host.h>
-
-#include <linux/mfd/pcf50633/adc.h>
-#include <linux/mfd/pcf50633/backlight.h>
-#include <linux/mfd/pcf50633/core.h>
-#include <linux/mfd/pcf50633/gpio.h>
-#include <linux/mfd/pcf50633/mbc.h>
-#include <linux/mfd/pcf50633/pmic.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#include <linux/regulator/machine.h>
-
-#include <linux/spi/spi.h>
-#include <linux/spi/s3c24xx.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <linux/platform_data/usb-ohci-s3c2410.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <linux/platform_data/fb-s3c2410.h>
-
-#include "regs-gpio.h"
-#include "regs-irq.h"
-#include "gpio-samsung.h"
-
-#include "cpu.h"
-#include "devs.h"
-#include "gpio-cfg.h"
-#include "pm.h"
-
-#include "s3c24xx.h"
-#include "gta02.h"
-
-static struct pcf50633 *gta02_pcf;
-
-/*
- * This gets called frequently when we paniced.
- */
-
-static long gta02_panic_blink(int state)
-{
- char led;
-
- led = (state) ? 1 : 0;
- gpio_direction_output(GTA02_GPIO_AUX_LED, led);
-
- return 0;
-}
-
-
-static struct map_desc gta02_iodesc[] __initdata = {
- {
- .virtual = 0xe0000000,
- .pfn = __phys_to_pfn(S3C2410_CS3 + 0x01000000),
- .length = SZ_1M,
- .type = MT_DEVICE
- },
-};
-
-#define UCON (S3C2410_UCON_DEFAULT | S3C2443_UCON_RXERR_IRQEN)
-#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
-#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
-
-static struct s3c2410_uartcfg gta02_uartcfgs[] = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
-};
-
-#ifdef CONFIG_CHARGER_PCF50633
-/*
- * On GTA02 the 1A charger features a 48K resistor to 0V on the ID pin.
- * We use this to recognize that we can pull 1A from the USB socket.
- *
- * These constants are the measured pcf50633 ADC levels with the 1A
- * charger / 48K resistor, and with no pulldown resistor.
- */
-
-#define ADC_NOM_CHG_DETECT_1A 6
-#define ADC_NOM_CHG_DETECT_USB 43
-
-#ifdef CONFIG_PCF50633_ADC
-static void
-gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res)
-{
- int ma;
-
- /* Interpret charger type */
- if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) {
-
- /*
- * Sanity - stop GPO driving out now that we have a 1A charger
- * GPO controls USB Host power generation on GTA02
- */
- pcf50633_gpio_set(pcf, PCF50633_GPO, 0);
-
- ma = 1000;
- } else
- ma = 100;
-
- pcf50633_mbc_usb_curlim_set(pcf, ma);
-}
-#endif
-
-static struct delayed_work gta02_charger_work;
-static int gta02_usb_vbus_draw;
-
-static void gta02_charger_worker(struct work_struct *work)
-{
- if (gta02_usb_vbus_draw) {
- pcf50633_mbc_usb_curlim_set(gta02_pcf, gta02_usb_vbus_draw);
- return;
- }
-
-#ifdef CONFIG_PCF50633_ADC
- pcf50633_adc_async_read(gta02_pcf,
- PCF50633_ADCC1_MUX_ADCIN1,
- PCF50633_ADCC1_AVERAGE_16,
- gta02_configure_pmu_for_charger,
- NULL);
-#else
- /*
- * If the PCF50633 ADC is disabled we fallback to a
- * 100mA limit for safety.
- */
- pcf50633_mbc_usb_curlim_set(gta02_pcf, 100);
-#endif
-}
-
-#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000)
-
-static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq)
-{
- if (irq == PCF50633_IRQ_USBINS) {
- schedule_delayed_work(&gta02_charger_work,
- GTA02_CHARGER_CONFIGURE_TIMEOUT);
-
- return;
- }
-
- if (irq == PCF50633_IRQ_USBREM) {
- cancel_delayed_work_sync(&gta02_charger_work);
- gta02_usb_vbus_draw = 0;
- }
-}
-
-static void gta02_udc_vbus_draw(unsigned int ma)
-{
- if (!gta02_pcf)
- return;
-
- gta02_usb_vbus_draw = ma;
-
- schedule_delayed_work(&gta02_charger_work,
- GTA02_CHARGER_CONFIGURE_TIMEOUT);
-}
-#else /* !CONFIG_CHARGER_PCF50633 */
-#define gta02_pmu_event_callback NULL
-#define gta02_udc_vbus_draw NULL
-#endif
-
-static char *gta02_batteries[] = {
- "battery",
-};
-
-static struct pcf50633_bl_platform_data gta02_backlight_data = {
- .default_brightness = 0x3f,
- .default_brightness_limit = 0,
- .ramp_time = 5,
-};
-
-static struct pcf50633_platform_data gta02_pcf_pdata = {
- .resumers = {
- [0] = PCF50633_INT1_USBINS |
- PCF50633_INT1_USBREM |
- PCF50633_INT1_ALARM,
- [1] = PCF50633_INT2_ONKEYF,
- [2] = PCF50633_INT3_ONKEY1S,
- [3] = PCF50633_INT4_LOWSYS |
- PCF50633_INT4_LOWBAT |
- PCF50633_INT4_HIGHTMP,
- },
-
- .batteries = gta02_batteries,
- .num_batteries = ARRAY_SIZE(gta02_batteries),
-
- .charger_reference_current_ma = 1000,
-
- .backlight_data = &gta02_backlight_data,
-
- .reg_init_data = {
- [PCF50633_REGULATOR_AUTO] = {
- .constraints = {
- .min_uV = 3300000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .always_on = 1,
- .apply_uV = 1,
- },
- },
- [PCF50633_REGULATOR_DOWN1] = {
- .constraints = {
- .min_uV = 1300000,
- .max_uV = 1600000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .always_on = 1,
- .apply_uV = 1,
- },
- },
- [PCF50633_REGULATOR_DOWN2] = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .apply_uV = 1,
- .always_on = 1,
- },
- },
- [PCF50633_REGULATOR_HCLDO] = {
- .constraints = {
- .min_uV = 2000000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- },
- [PCF50633_REGULATOR_LDO1] = {
- .constraints = {
- .min_uV = 3300000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = 1,
- },
- },
- [PCF50633_REGULATOR_LDO2] = {
- .constraints = {
- .min_uV = 3300000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .apply_uV = 1,
- },
- },
- [PCF50633_REGULATOR_LDO3] = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3000000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .apply_uV = 1,
- },
- },
- [PCF50633_REGULATOR_LDO4] = {
- .constraints = {
- .min_uV = 3200000,
- .max_uV = 3200000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = 1,
- },
- },
- [PCF50633_REGULATOR_LDO5] = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3000000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = 1,
- },
- },
- [PCF50633_REGULATOR_LDO6] = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3000000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- },
- },
- [PCF50633_REGULATOR_MEMLDO] = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- },
- },
-
- },
- .mbc_event_callback = gta02_pmu_event_callback,
-};
-
-
-/* NOR Flash. */
-
-#define GTA02_FLASH_BASE 0x18000000 /* GCS3 */
-#define GTA02_FLASH_SIZE 0x200000 /* 2MBytes */
-
-static struct physmap_flash_data gta02_nor_flash_data = {
- .width = 2,
-};
-
-static struct resource gta02_nor_flash_resource =
- DEFINE_RES_MEM(GTA02_FLASH_BASE, GTA02_FLASH_SIZE);
-
-static struct platform_device gta02_nor_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &gta02_nor_flash_data,
- },
- .resource = &gta02_nor_flash_resource,
- .num_resources = 1,
-};
-
-
-static struct platform_device s3c24xx_pwm_device = {
- .name = "s3c24xx_pwm",
- .num_resources = 0,
-};
-
-static struct platform_device gta02_dfbmcs320_device = {
- .name = "dfbmcs320",
-};
-
-static struct i2c_board_info gta02_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("pcf50633", 0x73),
- .irq = GTA02_IRQ_PCF50633,
- .platform_data = &gta02_pcf_pdata,
- },
- {
- I2C_BOARD_INFO("wm8753", 0x1a),
- },
-};
-
-static struct s3c2410_nand_set __initdata gta02_nand_sets[] = {
- [0] = {
- /*
- * This name is also hard-coded in the boot loaders, so
- * changing it would would require all users to upgrade
- * their boot loaders, some of which are stored in a NOR
- * that is considered to be immutable.
- */
- .name = "neo1973-nand",
- .nr_chips = 1,
- .flash_bbt = 1,
- },
-};
-
-/*
- * Choose a set of timings derived from S3C@2442B MCP54
- * data sheet (K5D2G13ACM-D075 MCP Memory).
- */
-
-static struct s3c2410_platform_nand __initdata gta02_nand_info = {
- .tacls = 0,
- .twrph0 = 25,
- .twrph1 = 15,
- .nr_sets = ARRAY_SIZE(gta02_nand_sets),
- .sets = gta02_nand_sets,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-
-/* Get PMU to set USB current limit accordingly. */
-static struct s3c2410_udc_mach_info gta02_udc_cfg __initdata = {
- .vbus_draw = gta02_udc_vbus_draw,
- .pullup_pin = GTA02_GPIO_USB_PULLUP,
-};
-
-/* USB */
-static struct s3c2410_hcd_info gta02_usb_info __initdata = {
- .port[0] = {
- .flags = S3C_HCDFLG_USED,
- },
- .port[1] = {
- .flags = 0,
- },
-};
-
-/* Touchscreen */
-static struct s3c2410_ts_mach_info gta02_ts_info = {
- .delay = 10000,
- .presc = 0xff, /* slow as we can go */
- .oversampling_shift = 2,
-};
-
-/* Buttons */
-static struct gpio_keys_button gta02_buttons[] = {
- {
- .gpio = GTA02_GPIO_AUX_KEY,
- .code = KEY_PHONE,
- .desc = "Aux",
- .type = EV_KEY,
- .debounce_interval = 100,
- },
- {
- .gpio = GTA02_GPIO_HOLD_KEY,
- .code = KEY_PAUSE,
- .desc = "Hold",
- .type = EV_KEY,
- .debounce_interval = 100,
- },
-};
-
-static struct gpio_keys_platform_data gta02_buttons_pdata = {
- .buttons = gta02_buttons,
- .nbuttons = ARRAY_SIZE(gta02_buttons),
-};
-
-static struct platform_device gta02_buttons_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &gta02_buttons_pdata,
- },
-};
-
-static struct gpiod_lookup_table gta02_audio_gpio_table = {
- .dev_id = "neo1973-audio",
- .table = {
- GPIO_LOOKUP("GPIOJ", 2, "amp-shut", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOJ", 1, "hp", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device gta02_audio = {
- .name = "neo1973-audio",
- .id = -1,
-};
-
-static struct gpiod_lookup_table gta02_mmc_gpio_table = {
- .dev_id = "s3c2410-sdi",
- .table = {
- /* bus pins */
- GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static void __init gta02_map_io(void)
-{
- s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
- s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-
-/* These are the guys that don't need to be children of PMU. */
-
-static struct platform_device *gta02_devices[] __initdata = {
- &s3c_device_ohci,
- &s3c_device_wdt,
- &s3c_device_sdi,
- &s3c_device_usbgadget,
- &s3c_device_nand,
- &gta02_nor_flash,
- &s3c24xx_pwm_device,
- &s3c_device_iis,
- &s3c_device_i2c0,
- &gta02_dfbmcs320_device,
- &gta02_buttons_device,
- &s3c_device_adc,
- &s3c_device_ts,
- &gta02_audio,
-};
-
-static void gta02_poweroff(void)
-{
- pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1);
-}
-
-static void __init gta02_machine_init(void)
-{
- /* Set the panic callback to turn AUX LED on or off. */
- panic_blink = gta02_panic_blink;
-
- s3c_pm_init();
-
-#ifdef CONFIG_CHARGER_PCF50633
- INIT_DELAYED_WORK(&gta02_charger_work, gta02_charger_worker);
-#endif
-
- s3c24xx_udc_set_platdata(&gta02_udc_cfg);
- s3c24xx_ts_set_platdata(&gta02_ts_info);
- s3c_ohci_set_platdata(&gta02_usb_info);
- s3c_nand_set_platdata(&gta02_nand_info);
- s3c_i2c0_set_platdata(NULL);
-
- i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
-
- /* Configure the I2S pins (GPE0...GPE4) in correct mode */
- s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
- S3C_GPIO_PULL_NONE);
-
- gpiod_add_lookup_table(&gta02_audio_gpio_table);
- gpiod_add_lookup_table(&gta02_mmc_gpio_table);
- platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
- pm_power_off = gta02_poweroff;
-
- regulator_has_full_constraints();
-}
-
-static void __init gta02_init_time(void)
-{
- s3c2442_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-MACHINE_START(NEO1973_GTA02, "GTA02")
- /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
- .atag_offset = 0x100,
- .map_io = gta02_map_io,
- .init_irq = s3c2442_init_irq,
- .init_machine = gta02_machine_init,
- .init_time = gta02_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-h1940.c b/arch/arm/mach-s3c/mach-h1940.c
deleted file mode 100644
index 8a43ed1c4c4d..000000000000
--- a/arch/arm/mach-s3c/mach-h1940.c
+++ /dev/null
@@ -1,801 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2003-2005 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-//
-// https://www.handhelds.org/projects/h1940.html
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/memblock.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/i2c.h>
-#include <linux/leds.h>
-#include <linux/pda_power.h>
-#include <linux/s3c_adc_battery.h>
-#include <linux/delay.h>
-
-#include <video/platform_lcd.h>
-
-#include <linux/mmc/host.h>
-#include <linux/export.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-
-#include <sound/uda1380.h>
-
-#include <linux/platform_data/fb-s3c2410.h>
-#include "map.h"
-#include "hardware-s3c24xx.h"
-#include "regs-clock.h"
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-
-#include "cpu.h"
-#include "devs.h"
-#include "gpio-cfg.h"
-#include "pm.h"
-
-#include "s3c24xx.h"
-#include "h1940.h"
-
-#define H1940_LATCH ((void __force __iomem *)0xF8000000)
-
-#define H1940_PA_LATCH S3C2410_CS2
-
-#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END))
-
-#define S3C24XX_PLL_MDIV_SHIFT (12)
-#define S3C24XX_PLL_PDIV_SHIFT (4)
-#define S3C24XX_PLL_SDIV_SHIFT (0)
-
-static struct map_desc h1940_iodesc[] __initdata = {
- [0] = {
- .virtual = (unsigned long)H1940_LATCH,
- .pfn = __phys_to_pfn(H1940_PA_LATCH),
- .length = SZ_16K,
- .type = MT_DEVICE
- },
-};
-
-#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = 0x3c5,
- .ulcon = 0x03,
- .ufcon = 0x51,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = 0x245,
- .ulcon = 0x03,
- .ufcon = 0x00,
- },
- /* IR port */
- [2] = {
- .hwport = 2,
- .flags = 0,
- .uart_flags = UPF_CONS_FLOW,
- .ucon = 0x3c5,
- .ulcon = 0x43,
- .ufcon = 0x51,
- }
-};
-
-/* Board control latch control */
-
-static unsigned int latch_state;
-
-static void h1940_latch_control(unsigned int clear, unsigned int set)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- latch_state &= ~clear;
- latch_state |= set;
-
- __raw_writel(latch_state, H1940_LATCH);
-
- local_irq_restore(flags);
-}
-
-static inline int h1940_gpiolib_to_latch(int offset)
-{
- return 1 << (offset + 16);
-}
-
-static void h1940_gpiolib_latch_set(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- int latch_bit = h1940_gpiolib_to_latch(offset);
-
- h1940_latch_control(value ? 0 : latch_bit,
- value ? latch_bit : 0);
-}
-
-static int h1940_gpiolib_latch_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- h1940_gpiolib_latch_set(chip, offset, value);
- return 0;
-}
-
-static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
- unsigned offset)
-{
- return (latch_state >> (offset + 16)) & 1;
-}
-
-static struct gpio_chip h1940_latch_gpiochip = {
- .base = H1940_LATCH_GPIO(0),
- .owner = THIS_MODULE,
- .label = "H1940_LATCH",
- .ngpio = 16,
- .direction_output = h1940_gpiolib_latch_output,
- .set = h1940_gpiolib_latch_set,
- .get = h1940_gpiolib_latch_get,
-};
-
-static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
- .vbus_pin = S3C2410_GPG(5),
- .vbus_pin_inverted = 1,
- .pullup_pin = H1940_LATCH_USB_DP,
-};
-
-static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = {
- .delay = 10000,
- .presc = 49,
- .oversampling_shift = 2,
- .cfg_gpio = s3c24xx_ts_cfg_gpio,
-};
-
-/*
- * Set lcd on or off
- */
-static struct s3c2410fb_display h1940_lcd __initdata = {
- .lcdcon5= S3C2410_LCDCON5_FRM565 | \
- S3C2410_LCDCON5_INVVLINE | \
- S3C2410_LCDCON5_HWSWP,
-
- .type = S3C2410_LCDCON1_TFT,
- .width = 240,
- .height = 320,
- .pixclock = 260000,
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .left_margin = 8,
- .right_margin = 20,
- .hsync_len = 4,
- .upper_margin = 8,
- .lower_margin = 7,
- .vsync_len = 1,
-};
-
-static struct s3c2410fb_mach_info h1940_fb_info __initdata = {
- .displays = &h1940_lcd,
- .num_displays = 1,
- .default_display = 0,
-
- .lpcsel = 0x02,
- .gpccon = 0xaa940659,
- .gpccon_mask = 0xffffc0f0,
- .gpccon_reg = S3C2410_GPCCON,
- .gpcup = 0x0000ffff,
- .gpcup_mask = 0xffffffff,
- .gpcup_reg = S3C2410_GPCUP,
- .gpdcon = 0xaa84aaa0,
- .gpdcon_mask = 0xffffffff,
- .gpdcon_reg = S3C2410_GPDCON,
- .gpdup = 0x0000faff,
- .gpdup_mask = 0xffffffff,
- .gpdup_reg = S3C2410_GPDUP,
-};
-
-static int power_supply_init(struct device *dev)
-{
- return gpio_request(S3C2410_GPF(2), "cable plugged");
-}
-
-static int h1940_is_ac_online(void)
-{
- return !gpio_get_value(S3C2410_GPF(2));
-}
-
-static void power_supply_exit(struct device *dev)
-{
- gpio_free(S3C2410_GPF(2));
-}
-
-static char *h1940_supplicants[] = {
- "main-battery",
- "backup-battery",
-};
-
-static struct pda_power_pdata power_supply_info = {
- .init = power_supply_init,
- .is_ac_online = h1940_is_ac_online,
- .exit = power_supply_exit,
- .supplied_to = h1940_supplicants,
- .num_supplicants = ARRAY_SIZE(h1940_supplicants),
-};
-
-static struct resource power_supply_resources[] = {
- [0] = DEFINE_RES_NAMED(IRQ_EINT2, 1, "ac", IORESOURCE_IRQ \
- | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE),
-};
-
-static struct platform_device power_supply = {
- .name = "pda-power",
- .id = -1,
- .dev = {
- .platform_data =
- &power_supply_info,
- },
- .resource = power_supply_resources,
- .num_resources = ARRAY_SIZE(power_supply_resources),
-};
-
-static const struct s3c_adc_bat_thresh bat_lut_noac[] = {
- { .volt = 4070, .cur = 162, .level = 100},
- { .volt = 4040, .cur = 165, .level = 95},
- { .volt = 4016, .cur = 164, .level = 90},
- { .volt = 3996, .cur = 166, .level = 85},
- { .volt = 3971, .cur = 168, .level = 80},
- { .volt = 3951, .cur = 168, .level = 75},
- { .volt = 3931, .cur = 170, .level = 70},
- { .volt = 3903, .cur = 172, .level = 65},
- { .volt = 3886, .cur = 172, .level = 60},
- { .volt = 3858, .cur = 176, .level = 55},
- { .volt = 3842, .cur = 176, .level = 50},
- { .volt = 3818, .cur = 176, .level = 45},
- { .volt = 3789, .cur = 180, .level = 40},
- { .volt = 3769, .cur = 180, .level = 35},
- { .volt = 3749, .cur = 184, .level = 30},
- { .volt = 3732, .cur = 184, .level = 25},
- { .volt = 3716, .cur = 184, .level = 20},
- { .volt = 3708, .cur = 184, .level = 15},
- { .volt = 3716, .cur = 96, .level = 10},
- { .volt = 3700, .cur = 96, .level = 5},
- { .volt = 3684, .cur = 96, .level = 0},
-};
-
-static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
- { .volt = 4130, .cur = 0, .level = 100},
- { .volt = 3982, .cur = 0, .level = 50},
- { .volt = 3854, .cur = 0, .level = 10},
- { .volt = 3841, .cur = 0, .level = 0},
-};
-
-static struct gpiod_lookup_table h1940_bat_gpio_table = {
- .dev_id = "s3c-adc-battery",
- .table = {
- /* Charge status S3C2410_GPF(3) */
- GPIO_LOOKUP("GPIOF", 3, "charge-status", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static int h1940_bat_init(void)
-{
- int ret;
-
- ret = gpio_request(H1940_LATCH_SM803_ENABLE, "h1940-charger-enable");
- if (ret)
- return ret;
- gpio_direction_output(H1940_LATCH_SM803_ENABLE, 0);
-
- return 0;
-
-}
-
-static void h1940_bat_exit(void)
-{
- gpio_free(H1940_LATCH_SM803_ENABLE);
-}
-
-static void h1940_enable_charger(void)
-{
- gpio_set_value(H1940_LATCH_SM803_ENABLE, 1);
-}
-
-static void h1940_disable_charger(void)
-{
- gpio_set_value(H1940_LATCH_SM803_ENABLE, 0);
-}
-
-static struct s3c_adc_bat_pdata h1940_bat_cfg = {
- .init = h1940_bat_init,
- .exit = h1940_bat_exit,
- .enable_charger = h1940_enable_charger,
- .disable_charger = h1940_disable_charger,
- .lut_noac = bat_lut_noac,
- .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac),
- .lut_acin = bat_lut_acin,
- .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin),
- .volt_channel = 0,
- .current_channel = 1,
- .volt_mult = 4056,
- .current_mult = 1893,
- .internal_impedance = 200,
- .backup_volt_channel = 3,
- /* TODO Check backup volt multiplier */
- .backup_volt_mult = 4056,
- .backup_volt_min = 0,
- .backup_volt_max = 4149288
-};
-
-static struct platform_device h1940_battery = {
- .name = "s3c-adc-battery",
- .id = -1,
- .dev = {
- .parent = &s3c_device_adc.dev,
- .platform_data = &h1940_bat_cfg,
- },
-};
-
-static DEFINE_SPINLOCK(h1940_blink_spin);
-
-int h1940_led_blink_set(struct gpio_desc *desc, int state,
- unsigned long *delay_on, unsigned long *delay_off)
-{
- int blink_gpio, check_gpio1, check_gpio2;
- int gpio = desc ? desc_to_gpio(desc) : -EINVAL;
-
- switch (gpio) {
- case H1940_LATCH_LED_GREEN:
- blink_gpio = S3C2410_GPA(7);
- check_gpio1 = S3C2410_GPA(1);
- check_gpio2 = S3C2410_GPA(3);
- break;
- case H1940_LATCH_LED_RED:
- blink_gpio = S3C2410_GPA(1);
- check_gpio1 = S3C2410_GPA(7);
- check_gpio2 = S3C2410_GPA(3);
- break;
- default:
- blink_gpio = S3C2410_GPA(3);
- check_gpio1 = S3C2410_GPA(1);
- check_gpio2 = S3C2410_GPA(7);
- break;
- }
-
- if (delay_on && delay_off && !*delay_on && !*delay_off)
- *delay_on = *delay_off = 500;
-
- spin_lock(&h1940_blink_spin);
-
- switch (state) {
- case GPIO_LED_NO_BLINK_LOW:
- case GPIO_LED_NO_BLINK_HIGH:
- if (!gpio_get_value(check_gpio1) &&
- !gpio_get_value(check_gpio2))
- gpio_set_value(H1940_LATCH_LED_FLASH, 0);
- gpio_set_value(blink_gpio, 0);
- if (gpio_is_valid(gpio))
- gpio_set_value(gpio, state);
- break;
- case GPIO_LED_BLINK:
- if (gpio_is_valid(gpio))
- gpio_set_value(gpio, 0);
- gpio_set_value(H1940_LATCH_LED_FLASH, 1);
- gpio_set_value(blink_gpio, 1);
- break;
- }
-
- spin_unlock(&h1940_blink_spin);
-
- return 0;
-}
-EXPORT_SYMBOL(h1940_led_blink_set);
-
-static struct gpio_led h1940_leds_desc[] = {
- {
- .name = "Green",
- .default_trigger = "main-battery-full",
- .gpio = H1940_LATCH_LED_GREEN,
- .retain_state_suspended = 1,
- },
- {
- .name = "Red",
- .default_trigger
- = "main-battery-charging-blink-full-solid",
- .gpio = H1940_LATCH_LED_RED,
- .retain_state_suspended = 1,
- },
-};
-
-static struct gpio_led_platform_data h1940_leds_pdata = {
- .num_leds = ARRAY_SIZE(h1940_leds_desc),
- .leds = h1940_leds_desc,
- .gpio_blink_set = h1940_led_blink_set,
-};
-
-static struct platform_device h1940_device_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &h1940_leds_pdata,
- },
-};
-
-static struct platform_device h1940_device_bluetooth = {
- .name = "h1940-bt",
- .id = -1,
-};
-
-static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
-{
- s3c24xx_mci_def_set_power(power_mode, vdd);
-
- switch (power_mode) {
- case MMC_POWER_OFF:
- gpio_set_value(H1940_LATCH_SD_POWER, 0);
- break;
- case MMC_POWER_UP:
- case MMC_POWER_ON:
- gpio_set_value(H1940_LATCH_SD_POWER, 1);
- break;
- default:
- break;
- }
-}
-
-static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
- .set_power = h1940_set_mmc_power,
- .ocr_avail = MMC_VDD_32_33,
-};
-
-static struct gpiod_lookup_table h1940_mmc_gpio_table = {
- .dev_id = "s3c2410-sdi",
- .table = {
- /* Card detect S3C2410_GPF(5) */
- GPIO_LOOKUP("GPIOF", 5, "cd", GPIO_ACTIVE_LOW),
- /* Write protect S3C2410_GPH(8) */
- GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_LOW),
- /* bus pins */
- GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct gpiod_lookup_table h1940_audio_gpio_table = {
- .dev_id = "h1940-audio",
- .table = {
- GPIO_LOOKUP("H1940_LATCH",
- H1940_LATCH_AUDIO_POWER - H1940_LATCH_GPIO(0),
- "speaker-power", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOG", 4, "hp", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct platform_device h1940_audio = {
- .name = "h1940-audio",
- .id = -1,
-};
-
-static struct pwm_lookup h1940_pwm_lookup[] = {
- PWM_LOOKUP("samsung-pwm", 0, "pwm-backlight", NULL, 36296,
- PWM_POLARITY_NORMAL),
-};
-
-static int h1940_backlight_init(struct device *dev)
-{
- gpio_request(S3C2410_GPB(0), "Backlight");
-
- gpio_direction_output(S3C2410_GPB(0), 0);
- s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
- s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
- gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
-
- return 0;
-}
-
-static int h1940_backlight_notify(struct device *dev, int brightness)
-{
- if (!brightness) {
- gpio_direction_output(S3C2410_GPB(0), 1);
- gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
- } else {
- gpio_direction_output(S3C2410_GPB(0), 0);
- s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
- s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
- gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
- }
- return brightness;
-}
-
-static void h1940_backlight_exit(struct device *dev)
-{
- gpio_direction_output(S3C2410_GPB(0), 1);
- gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
-}
-
-
-static struct platform_pwm_backlight_data backlight_data = {
- .max_brightness = 100,
- .dft_brightness = 50,
- .init = h1940_backlight_init,
- .notify = h1940_backlight_notify,
- .exit = h1940_backlight_exit,
-};
-
-static struct platform_device h1940_backlight = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &samsung_device_pwm.dev,
- .platform_data = &backlight_data,
- },
- .id = -1,
-};
-
-static void h1940_lcd_power_set(struct plat_lcd_data *pd,
- unsigned int power)
-{
- int value, retries = 100;
-
- if (!power) {
- gpio_set_value(S3C2410_GPC(0), 0);
- /* wait for 3ac */
- do {
- value = gpio_get_value(S3C2410_GPC(6));
- } while (value && retries--);
-
- gpio_set_value(H1940_LATCH_LCD_P2, 0);
- gpio_set_value(H1940_LATCH_LCD_P3, 0);
- gpio_set_value(H1940_LATCH_LCD_P4, 0);
-
- gpio_direction_output(S3C2410_GPC(1), 0);
- gpio_direction_output(S3C2410_GPC(4), 0);
-
- gpio_set_value(H1940_LATCH_LCD_P1, 0);
- gpio_set_value(H1940_LATCH_LCD_P0, 0);
-
- gpio_set_value(S3C2410_GPC(5), 0);
-
- } else {
- gpio_set_value(H1940_LATCH_LCD_P0, 1);
- gpio_set_value(H1940_LATCH_LCD_P1, 1);
-
- gpio_direction_input(S3C2410_GPC(1));
- gpio_direction_input(S3C2410_GPC(4));
- mdelay(10);
- s3c_gpio_cfgpin(S3C2410_GPC(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S3C2410_GPC(4), S3C_GPIO_SFN(2));
-
- gpio_set_value(S3C2410_GPC(5), 1);
- gpio_set_value(S3C2410_GPC(0), 1);
-
- gpio_set_value(H1940_LATCH_LCD_P3, 1);
- gpio_set_value(H1940_LATCH_LCD_P2, 1);
- gpio_set_value(H1940_LATCH_LCD_P4, 1);
- }
-}
-
-static struct plat_lcd_data h1940_lcd_power_data = {
- .set_power = h1940_lcd_power_set,
-};
-
-static struct platform_device h1940_lcd_powerdev = {
- .name = "platform-lcd",
- .dev.parent = &s3c_device_lcd.dev,
- .dev.platform_data = &h1940_lcd_power_data,
-};
-
-static struct uda1380_platform_data uda1380_info = {
- .gpio_power = H1940_LATCH_UDA_POWER,
- .gpio_reset = S3C2410_GPA(12),
- .dac_clk = UDA1380_DAC_CLK_SYSCLK,
-};
-
-static struct i2c_board_info h1940_i2c_devices[] = {
- {
- I2C_BOARD_INFO("uda1380", 0x1a),
- .platform_data = &uda1380_info,
- },
-};
-
-#define DECLARE_BUTTON(p, k, n, w) \
- { \
- .gpio = p, \
- .code = k, \
- .desc = n, \
- .wakeup = w, \
- .active_low = 1, \
- }
-
-static struct gpio_keys_button h1940_buttons[] = {
- DECLARE_BUTTON(S3C2410_GPF(0), KEY_POWER, "Power", 1),
- DECLARE_BUTTON(S3C2410_GPF(6), KEY_ENTER, "Select", 1),
- DECLARE_BUTTON(S3C2410_GPF(7), KEY_RECORD, "Record", 0),
- DECLARE_BUTTON(S3C2410_GPG(0), KEY_F11, "Calendar", 0),
- DECLARE_BUTTON(S3C2410_GPG(2), KEY_F12, "Contacts", 0),
- DECLARE_BUTTON(S3C2410_GPG(3), KEY_MAIL, "Mail", 0),
- DECLARE_BUTTON(S3C2410_GPG(6), KEY_LEFT, "Left_arrow", 0),
- DECLARE_BUTTON(S3C2410_GPG(7), KEY_HOMEPAGE, "Home", 0),
- DECLARE_BUTTON(S3C2410_GPG(8), KEY_RIGHT, "Right_arrow", 0),
- DECLARE_BUTTON(S3C2410_GPG(9), KEY_UP, "Up_arrow", 0),
- DECLARE_BUTTON(S3C2410_GPG(10), KEY_DOWN, "Down_arrow", 0),
-};
-
-static struct gpio_keys_platform_data h1940_buttons_data = {
- .buttons = h1940_buttons,
- .nbuttons = ARRAY_SIZE(h1940_buttons),
-};
-
-static struct platform_device h1940_dev_buttons = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &h1940_buttons_data,
- }
-};
-
-static struct platform_device *h1940_devices[] __initdata = {
- &h1940_dev_buttons,
- &s3c_device_ohci,
- &s3c_device_lcd,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_iis,
- &s3c_device_usbgadget,
- &h1940_device_leds,
- &h1940_device_bluetooth,
- &s3c_device_sdi,
- &s3c_device_rtc,
- &samsung_device_pwm,
- &h1940_backlight,
- &h1940_lcd_powerdev,
- &s3c_device_adc,
- &s3c_device_ts,
- &power_supply,
- &h1940_battery,
- &h1940_audio,
-};
-
-static void __init h1940_map_io(void)
-{
- s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
- s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-
- /* setup PM */
-
-#ifdef CONFIG_PM_H1940
- memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
-#endif
- s3c_pm_init();
-
- /* Add latch gpio chip, set latch initial value */
- h1940_latch_control(0, 0);
- WARN_ON(gpiochip_add_data(&h1940_latch_gpiochip, NULL));
-}
-
-static void __init h1940_init_time(void)
-{
- s3c2410_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-/* H1940 and RX3715 need to reserve this for suspend */
-static void __init h1940_reserve(void)
-{
- memblock_reserve(0x30003000, 0x1000);
- memblock_reserve(0x30081000, 0x1000);
-}
-
-static void __init h1940_init(void)
-{
- u32 tmp;
-
- s3c24xx_fb_set_platdata(&h1940_fb_info);
- gpiod_add_lookup_table(&h1940_mmc_gpio_table);
- gpiod_add_lookup_table(&h1940_audio_gpio_table);
- gpiod_add_lookup_table(&h1940_bat_gpio_table);
- /* Configure the I2S pins (GPE0...GPE4) in correct mode */
- s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
- S3C_GPIO_PULL_NONE);
- s3c24xx_mci_set_platdata(&h1940_mmc_cfg);
- s3c24xx_udc_set_platdata(&h1940_udc_cfg);
- s3c24xx_ts_set_platdata(&h1940_ts_cfg);
- s3c_i2c0_set_platdata(NULL);
-
- /* Turn off suspend on both USB ports, and switch the
- * selectable USB port to USB device mode. */
-
- s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
- S3C2410_MISCCR_USBSUSPND0 |
- S3C2410_MISCCR_USBSUSPND1, 0x0);
-
- tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT)
- | (0x02 << S3C24XX_PLL_PDIV_SHIFT)
- | (0x03 << S3C24XX_PLL_SDIV_SHIFT);
- writel(tmp, S3C2410_UPLLCON);
-
- gpio_request(S3C2410_GPC(0), "LCD power");
- gpio_request(S3C2410_GPC(1), "LCD power");
- gpio_request(S3C2410_GPC(4), "LCD power");
- gpio_request(S3C2410_GPC(5), "LCD power");
- gpio_request(S3C2410_GPC(6), "LCD power");
- gpio_request(H1940_LATCH_LCD_P0, "LCD power");
- gpio_request(H1940_LATCH_LCD_P1, "LCD power");
- gpio_request(H1940_LATCH_LCD_P2, "LCD power");
- gpio_request(H1940_LATCH_LCD_P3, "LCD power");
- gpio_request(H1940_LATCH_LCD_P4, "LCD power");
- gpio_request(H1940_LATCH_MAX1698_nSHUTDOWN, "LCD power");
- gpio_direction_output(S3C2410_GPC(0), 0);
- gpio_direction_output(S3C2410_GPC(1), 0);
- gpio_direction_output(S3C2410_GPC(4), 0);
- gpio_direction_output(S3C2410_GPC(5), 0);
- gpio_direction_input(S3C2410_GPC(6));
- gpio_direction_output(H1940_LATCH_LCD_P0, 0);
- gpio_direction_output(H1940_LATCH_LCD_P1, 0);
- gpio_direction_output(H1940_LATCH_LCD_P2, 0);
- gpio_direction_output(H1940_LATCH_LCD_P3, 0);
- gpio_direction_output(H1940_LATCH_LCD_P4, 0);
- gpio_direction_output(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
-
- gpio_request(H1940_LATCH_SD_POWER, "SD power");
- gpio_direction_output(H1940_LATCH_SD_POWER, 0);
-
- pwm_add_table(h1940_pwm_lookup, ARRAY_SIZE(h1940_pwm_lookup));
- platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
-
- gpio_request(S3C2410_GPA(1), "Red LED blink");
- gpio_request(S3C2410_GPA(3), "Blue LED blink");
- gpio_request(S3C2410_GPA(7), "Green LED blink");
- gpio_request(H1940_LATCH_LED_FLASH, "LED blink");
- gpio_direction_output(S3C2410_GPA(1), 0);
- gpio_direction_output(S3C2410_GPA(3), 0);
- gpio_direction_output(S3C2410_GPA(7), 0);
- gpio_direction_output(H1940_LATCH_LED_FLASH, 0);
-
- i2c_register_board_info(0, h1940_i2c_devices,
- ARRAY_SIZE(h1940_i2c_devices));
-}
-
-MACHINE_START(H1940, "IPAQ-H1940")
- /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
- .atag_offset = 0x100,
- .map_io = h1940_map_io,
- .reserve = h1940_reserve,
- .init_irq = s3c2410_init_irq,
- .init_machine = h1940_init,
- .init_time = h1940_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-hmt.c b/arch/arm/mach-s3c/mach-hmt.c
deleted file mode 100644
index b287e9987311..000000000000
--- a/arch/arm/mach-s3c/mach-hmt.c
+++ /dev/null
@@ -1,282 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// mach-hmt.c - Platform code for Airgoo HMT
-//
-// Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk>
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/leds.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <video/samsung_fimd.h>
-#include "map.h"
-#include <mach/irqs.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include "gpio-samsung.h"
-#include "fb.h"
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-
-#include "devs.h"
-#include "cpu.h"
-
-#include "s3c64xx.h"
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
-#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
-
-static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
-};
-
-static struct pwm_lookup hmt_pwm_lookup[] = {
- PWM_LOOKUP("samsung-pwm", 1, "pwm-backlight.0", NULL,
- 1000000000 / (100 * 256 * 20), PWM_POLARITY_NORMAL),
-};
-
-static int hmt_bl_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable");
- if (!ret)
- ret = gpio_direction_output(S3C64XX_GPB(4), 0);
-
- return ret;
-}
-
-static int hmt_bl_notify(struct device *dev, int brightness)
-{
- /*
- * translate from CIELUV/CIELAB L*->brightness, E.G. from
- * perceived luminance to light output. Assumes range 0..25600
- */
- if (brightness < 0x800) {
- /* Y = Yn * L / 903.3 */
- brightness = (100*256 * brightness + 231245/2) / 231245;
- } else {
- /* Y = Yn * ((L + 16) / 116 )^3 */
- int t = (brightness*4 + 16*1024 + 58)/116;
- brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000);
- }
-
- gpio_set_value(S3C64XX_GPB(4), brightness);
-
- return brightness;
-}
-
-static void hmt_bl_exit(struct device *dev)
-{
- gpio_free(S3C64XX_GPB(4));
-}
-
-static struct platform_pwm_backlight_data hmt_backlight_data = {
- .max_brightness = 100 * 256,
- .dft_brightness = 40 * 256,
- .init = hmt_bl_init,
- .notify = hmt_bl_notify,
- .exit = hmt_bl_exit,
-
-};
-
-static struct platform_device hmt_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &samsung_device_pwm.dev,
- .platform_data = &hmt_backlight_data,
- },
-};
-
-static struct s3c_fb_pd_win hmt_fb_win0 = {
- .max_bpp = 32,
- .default_bpp = 16,
- .xres = 800,
- .yres = 480,
-};
-
-static struct fb_videomode hmt_lcd_timing = {
- .left_margin = 8,
- .right_margin = 13,
- .upper_margin = 7,
- .lower_margin = 5,
- .hsync_len = 3,
- .vsync_len = 1,
- .xres = 800,
- .yres = 480,
-};
-
-/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
-static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
- .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
- .vtiming = &hmt_lcd_timing,
- .win[0] = &hmt_fb_win0,
- .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
- .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-};
-
-static struct mtd_partition hmt_nand_part[] = {
- [0] = {
- .name = "uboot",
- .size = SZ_512K,
- .offset = 0,
- },
- [1] = {
- .name = "uboot-env1",
- .size = SZ_256K,
- .offset = SZ_512K,
- },
- [2] = {
- .name = "uboot-env2",
- .size = SZ_256K,
- .offset = SZ_512K + SZ_256K,
- },
- [3] = {
- .name = "kernel",
- .size = SZ_2M,
- .offset = SZ_1M,
- },
- [4] = {
- .name = "rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = SZ_1M + SZ_2M,
- },
-};
-
-static struct s3c2410_nand_set hmt_nand_sets[] = {
- [0] = {
- .name = "nand",
- .nr_chips = 1,
- .nr_partitions = ARRAY_SIZE(hmt_nand_part),
- .partitions = hmt_nand_part,
- },
-};
-
-static struct s3c2410_platform_nand hmt_nand_info = {
- .tacls = 25,
- .twrph0 = 55,
- .twrph1 = 40,
- .nr_sets = ARRAY_SIZE(hmt_nand_sets),
- .sets = hmt_nand_sets,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-static struct gpio_led hmt_leds[] = {
- { /* left function keys */
- .name = "left:blue",
- .gpio = S3C64XX_GPO(12),
- .default_trigger = "default-on",
- },
- { /* right function keys - red */
- .name = "right:red",
- .gpio = S3C64XX_GPO(13),
- },
- { /* right function keys - green */
- .name = "right:green",
- .gpio = S3C64XX_GPO(14),
- },
- { /* right function keys - blue */
- .name = "right:blue",
- .gpio = S3C64XX_GPO(15),
- .default_trigger = "default-on",
- },
-};
-
-static struct gpio_led_platform_data hmt_led_data = {
- .num_leds = ARRAY_SIZE(hmt_leds),
- .leds = hmt_leds,
-};
-
-static struct platform_device hmt_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev.platform_data = &hmt_led_data,
-};
-
-static struct map_desc hmt_iodesc[] = {};
-
-static struct platform_device *hmt_devices[] __initdata = {
- &s3c_device_i2c0,
- &s3c_device_nand,
- &s3c_device_fb,
- &s3c_device_ohci,
- &samsung_device_pwm,
- &hmt_backlight_device,
- &hmt_leds_device,
-};
-
-static void __init hmt_map_io(void)
-{
- s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
- s3c64xx_set_xtal_freq(12000000);
- s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
- s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
-}
-
-static void __init hmt_machine_init(void)
-{
- s3c_i2c0_set_platdata(NULL);
- s3c_fb_set_platdata(&hmt_lcd_pdata);
- s3c_nand_set_platdata(&hmt_nand_info);
-
- gpio_request(S3C64XX_GPC(7), "usb power");
- gpio_direction_output(S3C64XX_GPC(7), 0);
- gpio_request(S3C64XX_GPM(0), "usb power");
- gpio_direction_output(S3C64XX_GPM(0), 1);
- gpio_request(S3C64XX_GPK(7), "usb power");
- gpio_direction_output(S3C64XX_GPK(7), 1);
- gpio_request(S3C64XX_GPF(13), "usb power");
- gpio_direction_output(S3C64XX_GPF(13), 1);
-
- pwm_add_table(hmt_pwm_lookup, ARRAY_SIZE(hmt_pwm_lookup));
- platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices));
-}
-
-MACHINE_START(HMT, "Airgoo-HMT")
- /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
- .atag_offset = 0x100,
- .nr_irqs = S3C64XX_NR_IRQS,
- .init_irq = s3c6410_init_irq,
- .map_io = hmt_map_io,
- .init_machine = hmt_machine_init,
- .init_time = s3c64xx_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-jive.c b/arch/arm/mach-s3c/mach-jive.c
deleted file mode 100644
index 0d7d408c3729..000000000000
--- a/arch/arm/mach-s3c/mach-jive.c
+++ /dev/null
@@ -1,685 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2007 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-//
-// http://armlinux.simtec.co.uk/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/syscore_ops.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-
-#include <video/ili9320.h>
-
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include "hardware-s3c24xx.h"
-#include "regs-gpio.h"
-#include <linux/platform_data/fb-s3c2410.h>
-#include "gpio-samsung.h"
-
-#include <asm/mach-types.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-
-#include "gpio-cfg.h"
-#include "devs.h"
-#include "cpu.h"
-#include "pm.h"
-#include <linux/platform_data/usb-s3c2410_udc.h>
-
-#include "s3c24xx.h"
-#include "s3c2412-power.h"
-
-static struct map_desc jive_iodesc[] __initdata = {
-};
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg jive_uartcfgs[] = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- }
-};
-
-/* Jive flash assignment
- *
- * 0x00000000-0x00028000 : uboot
- * 0x00028000-0x0002c000 : uboot env
- * 0x0002c000-0x00030000 : spare
- * 0x00030000-0x00200000 : zimage A
- * 0x00200000-0x01600000 : cramfs A
- * 0x01600000-0x017d0000 : zimage B
- * 0x017d0000-0x02bd0000 : cramfs B
- * 0x02bd0000-0x03fd0000 : yaffs
- */
-static struct mtd_partition __initdata jive_imageA_nand_part[] = {
-
-#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
- /* Don't allow access to the bootloader from linux */
- {
- .name = "uboot",
- .offset = 0,
- .size = (160 * SZ_1K),
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
-
- /* spare */
- {
- .name = "spare",
- .offset = (176 * SZ_1K),
- .size = (16 * SZ_1K),
- },
-#endif
-
- /* booted images */
- {
- .name = "kernel (ro)",
- .offset = (192 * SZ_1K),
- .size = (SZ_2M) - (192 * SZ_1K),
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- }, {
- .name = "root (ro)",
- .offset = (SZ_2M),
- .size = (20 * SZ_1M),
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
-
- /* yaffs */
- {
- .name = "yaffs",
- .offset = (44 * SZ_1M),
- .size = (20 * SZ_1M),
- },
-
- /* bootloader environment */
- {
- .name = "env",
- .offset = (160 * SZ_1K),
- .size = (16 * SZ_1K),
- },
-
- /* upgrade images */
- {
- .name = "zimage",
- .offset = (22 * SZ_1M),
- .size = (2 * SZ_1M) - (192 * SZ_1K),
- }, {
- .name = "cramfs",
- .offset = (24 * SZ_1M) - (192*SZ_1K),
- .size = (20 * SZ_1M),
- },
-};
-
-static struct mtd_partition __initdata jive_imageB_nand_part[] = {
-
-#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
- /* Don't allow access to the bootloader from linux */
- {
- .name = "uboot",
- .offset = 0,
- .size = (160 * SZ_1K),
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
-
- /* spare */
- {
- .name = "spare",
- .offset = (176 * SZ_1K),
- .size = (16 * SZ_1K),
- },
-#endif
-
- /* booted images */
- {
- .name = "kernel (ro)",
- .offset = (22 * SZ_1M),
- .size = (2 * SZ_1M) - (192 * SZ_1K),
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "root (ro)",
- .offset = (24 * SZ_1M) - (192 * SZ_1K),
- .size = (20 * SZ_1M),
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
-
- /* yaffs */
- {
- .name = "yaffs",
- .offset = (44 * SZ_1M),
- .size = (20 * SZ_1M),
- },
-
- /* bootloader environment */
- {
- .name = "env",
- .offset = (160 * SZ_1K),
- .size = (16 * SZ_1K),
- },
-
- /* upgrade images */
- {
- .name = "zimage",
- .offset = (192 * SZ_1K),
- .size = (2 * SZ_1M) - (192 * SZ_1K),
- }, {
- .name = "cramfs",
- .offset = (2 * SZ_1M),
- .size = (20 * SZ_1M),
- },
-};
-
-static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
- [0] = {
- .name = "flash",
- .nr_chips = 1,
- .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
- .partitions = jive_imageA_nand_part,
- },
-};
-
-static struct s3c2410_platform_nand __initdata jive_nand_info = {
- /* set taken from osiris nand timings, possibly still conservative */
- .tacls = 30,
- .twrph0 = 55,
- .twrph1 = 40,
- .sets = jive_nand_sets,
- .nr_sets = ARRAY_SIZE(jive_nand_sets),
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-static int __init jive_mtdset(char *options)
-{
- struct s3c2410_nand_set *nand = &jive_nand_sets[0];
- unsigned long set;
-
- if (options == NULL || options[0] == '\0')
- return 1;
-
- if (kstrtoul(options, 10, &set)) {
- printk(KERN_ERR "failed to parse mtdset=%s\n", options);
- return 1;
- }
-
- switch (set) {
- case 1:
- nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
- nand->partitions = jive_imageB_nand_part;
- break;
- case 0:
- /* this is already setup in the nand info */
- break;
- default:
- printk(KERN_ERR "Unknown mtd set %ld specified,"
- "using default.", set);
- }
-
- return 1;
-}
-
-/* parse the mtdset= option given to the kernel command line */
-__setup("mtdset=", jive_mtdset);
-
-/* LCD timing and setup */
-
-#define LCD_XRES (240)
-#define LCD_YRES (320)
-#define LCD_LEFT_MARGIN (12)
-#define LCD_RIGHT_MARGIN (12)
-#define LCD_LOWER_MARGIN (12)
-#define LCD_UPPER_MARGIN (12)
-#define LCD_VSYNC (2)
-#define LCD_HSYNC (2)
-
-#define LCD_REFRESH (60)
-
-#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
-#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
-
-static struct s3c2410fb_display jive_vgg2432a4_display[] = {
- [0] = {
- .width = LCD_XRES,
- .height = LCD_YRES,
- .xres = LCD_XRES,
- .yres = LCD_YRES,
- .left_margin = LCD_LEFT_MARGIN,
- .right_margin = LCD_RIGHT_MARGIN,
- .upper_margin = LCD_UPPER_MARGIN,
- .lower_margin = LCD_LOWER_MARGIN,
- .hsync_len = LCD_HSYNC,
- .vsync_len = LCD_VSYNC,
-
- .pixclock = (1000000000000LL /
- (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
-
- .bpp = 16,
- .type = (S3C2410_LCDCON1_TFT16BPP |
- S3C2410_LCDCON1_TFT),
-
- .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_INVVDEN |
- S3C2410_LCDCON5_PWREN),
- },
-};
-
-/* todo - put into gpio header */
-
-#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
-#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
-
-static struct s3c2410fb_mach_info jive_lcd_config = {
- .displays = jive_vgg2432a4_display,
- .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
- .default_display = 0,
-
- /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
- * and disable the pull down resistors on pins we are using for LCD
- * data. */
-
- .gpcup = (0xf << 1) | (0x3f << 10),
- .gpcup_reg = S3C2410_GPCUP,
-
- .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
- S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
- S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
- S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
- S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
-
- .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
- S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
- S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
- S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
- S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
-
- .gpccon_reg = S3C2410_GPCCON,
-
- .gpdup = (0x3f << 2) | (0x3f << 10),
-
- .gpdup_reg = S3C2410_GPDUP,
-
- .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
- S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
- S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
- S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
- S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
- S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
-
- .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
- S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
- S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
- S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
- S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
- S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
-
- .gpdcon_reg = S3C2410_GPDCON,
-};
-
-/* ILI9320 support. */
-
-static void jive_lcm_reset(unsigned int set)
-{
- printk(KERN_DEBUG "%s(%d)\n", __func__, set);
-
- gpio_set_value(S3C2410_GPG(13), set);
-}
-
-#undef LCD_UPPER_MARGIN
-#define LCD_UPPER_MARGIN 2
-
-static struct ili9320_platdata jive_lcm_config = {
- .hsize = LCD_XRES,
- .vsize = LCD_YRES,
-
- .reset = jive_lcm_reset,
- .suspend = ILI9320_SUSPEND_DEEP,
-
- .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
- .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
- ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
- .display3 = 0x0,
- .display4 = 0x0,
- .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
- ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
- .rgb_if2 = ILI9320_RGBIF2_DPL,
- .interface2 = 0x0,
- .interface3 = 0x3,
- .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
- ILI9320_INTERFACE4_DIVE(1)),
- .interface5 = 0x0,
- .interface6 = 0x0,
-};
-
-/* LCD SPI support */
-
-static struct spi_gpio_platform_data jive_lcd_spi = {
- .num_chipselect = 1,
-};
-
-static struct platform_device jive_device_lcdspi = {
- .name = "spi_gpio",
- .id = 1,
- .dev.platform_data = &jive_lcd_spi,
-};
-
-static struct gpiod_lookup_table jive_lcdspi_gpiod_table = {
- .dev_id = "spi_gpio",
- .table = {
- GPIO_LOOKUP("GPIOG", 8,
- "sck", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOB", 8,
- "mosi", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOB", 7,
- "cs", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/* WM8750 audio code SPI definition */
-
-static struct spi_gpio_platform_data jive_wm8750_spi = {
- .num_chipselect = 1,
-};
-
-static struct platform_device jive_device_wm8750 = {
- .name = "spi_gpio",
- .id = 2,
- .dev.platform_data = &jive_wm8750_spi,
-};
-
-static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
- .dev_id = "spi_gpio",
- .table = {
- GPIO_LOOKUP("GPIOB", 4,
- "sck", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOB", 9,
- "mosi", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOH", 10,
- "cs", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/* JIVE SPI devices. */
-
-static struct spi_board_info __initdata jive_spi_devs[] = {
- [0] = {
- .modalias = "VGG2432A4",
- .bus_num = 1,
- .chip_select = 0,
- .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
- .max_speed_hz = 100000,
- .platform_data = &jive_lcm_config,
- }, {
- .modalias = "WM8750",
- .bus_num = 2,
- .chip_select = 0,
- .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
- .max_speed_hz = 100000,
- },
-};
-
-/* I2C bus and device configuration. */
-
-static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
- .frequency = 80 * 1000,
- .flags = S3C_IICFLG_FILTER,
- .sda_delay = 2,
-};
-
-static struct i2c_board_info jive_i2c_devs[] __initdata = {
- [0] = {
- I2C_BOARD_INFO("lis302dl", 0x1c),
- .irq = IRQ_EINT14,
- },
-};
-
-/* The platform devices being used. */
-
-static struct platform_device *jive_devices[] __initdata = {
- &s3c_device_ohci,
- &s3c_device_rtc,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_lcd,
- &jive_device_lcdspi,
- &jive_device_wm8750,
- &s3c_device_nand,
- &s3c_device_usbgadget,
- &s3c2412_device_dma,
-};
-
-static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
- .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
-};
-
-/* Jive power management device */
-
-#ifdef CONFIG_PM
-static int jive_pm_suspend(void)
-{
- /* Write the magic value u-boot uses to check for resume into
- * the INFORM0 register, and ensure INFORM1 is set to the
- * correct address to resume from. */
-
- __raw_writel(0x2BED, S3C2412_INFORM0);
- __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
-
- return 0;
-}
-
-static void jive_pm_resume(void)
-{
- __raw_writel(0x0, S3C2412_INFORM0);
-}
-
-#else
-#define jive_pm_suspend NULL
-#define jive_pm_resume NULL
-#endif
-
-static struct syscore_ops jive_pm_syscore_ops = {
- .suspend = jive_pm_suspend,
- .resume = jive_pm_resume,
-};
-
-static void __init jive_map_io(void)
-{
- s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
- s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-static void __init jive_init_time(void)
-{
- s3c2412_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-static void jive_power_off(void)
-{
- printk(KERN_INFO "powering system down...\n");
-
- gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPC(5));
-}
-
-static void __init jive_machine_init(void)
-{
- /* register system core operations for managing low level suspend */
-
- register_syscore_ops(&jive_pm_syscore_ops);
-
- /* write our sleep configurations for the IO. Pull down all unused
- * IO, ensure that we have turned off all peripherals we do not
- * need, and configure the ones we do need. */
-
- /* Port B sleep */
-
- __raw_writel(S3C2412_SLPCON_IN(0) |
- S3C2412_SLPCON_PULL(1) |
- S3C2412_SLPCON_HIGH(2) |
- S3C2412_SLPCON_PULL(3) |
- S3C2412_SLPCON_PULL(4) |
- S3C2412_SLPCON_PULL(5) |
- S3C2412_SLPCON_PULL(6) |
- S3C2412_SLPCON_HIGH(7) |
- S3C2412_SLPCON_PULL(8) |
- S3C2412_SLPCON_PULL(9) |
- S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
-
- /* Port C sleep */
-
- __raw_writel(S3C2412_SLPCON_PULL(0) |
- S3C2412_SLPCON_PULL(1) |
- S3C2412_SLPCON_PULL(2) |
- S3C2412_SLPCON_PULL(3) |
- S3C2412_SLPCON_PULL(4) |
- S3C2412_SLPCON_PULL(5) |
- S3C2412_SLPCON_LOW(6) |
- S3C2412_SLPCON_PULL(6) |
- S3C2412_SLPCON_PULL(7) |
- S3C2412_SLPCON_PULL(8) |
- S3C2412_SLPCON_PULL(9) |
- S3C2412_SLPCON_PULL(10) |
- S3C2412_SLPCON_PULL(11) |
- S3C2412_SLPCON_PULL(12) |
- S3C2412_SLPCON_PULL(13) |
- S3C2412_SLPCON_PULL(14) |
- S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
-
- /* Port D sleep */
-
- __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
-
- /* Port F sleep */
-
- __raw_writel(S3C2412_SLPCON_LOW(0) |
- S3C2412_SLPCON_LOW(1) |
- S3C2412_SLPCON_LOW(2) |
- S3C2412_SLPCON_EINT(3) |
- S3C2412_SLPCON_EINT(4) |
- S3C2412_SLPCON_EINT(5) |
- S3C2412_SLPCON_EINT(6) |
- S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
-
- /* Port G sleep */
-
- __raw_writel(S3C2412_SLPCON_IN(0) |
- S3C2412_SLPCON_IN(1) |
- S3C2412_SLPCON_IN(2) |
- S3C2412_SLPCON_IN(3) |
- S3C2412_SLPCON_IN(4) |
- S3C2412_SLPCON_IN(5) |
- S3C2412_SLPCON_IN(6) |
- S3C2412_SLPCON_IN(7) |
- S3C2412_SLPCON_PULL(8) |
- S3C2412_SLPCON_PULL(9) |
- S3C2412_SLPCON_IN(10) |
- S3C2412_SLPCON_PULL(11) |
- S3C2412_SLPCON_PULL(12) |
- S3C2412_SLPCON_PULL(13) |
- S3C2412_SLPCON_IN(14) |
- S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
-
- /* Port H sleep */
-
- __raw_writel(S3C2412_SLPCON_PULL(0) |
- S3C2412_SLPCON_PULL(1) |
- S3C2412_SLPCON_PULL(2) |
- S3C2412_SLPCON_PULL(3) |
- S3C2412_SLPCON_PULL(4) |
- S3C2412_SLPCON_PULL(5) |
- S3C2412_SLPCON_PULL(6) |
- S3C2412_SLPCON_IN(7) |
- S3C2412_SLPCON_IN(8) |
- S3C2412_SLPCON_PULL(9) |
- S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
-
- /* initialise the power management now we've setup everything. */
-
- s3c_pm_init();
-
- /** TODO - check that this is after the cmdline option! */
- s3c_nand_set_platdata(&jive_nand_info);
-
- gpio_request(S3C2410_GPG(13), "lcm reset");
- gpio_direction_output(S3C2410_GPG(13), 0);
-
- gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
- gpio_free(S3C2410_GPB(6));
-
- /* Turn off suspend on both USB ports, and switch the
- * selectable USB port to USB device mode. */
-
- s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
- S3C2410_MISCCR_USBSUSPND0 |
- S3C2410_MISCCR_USBSUSPND1, 0x0);
-
- s3c24xx_udc_set_platdata(&jive_udc_cfg);
- s3c24xx_fb_set_platdata(&jive_lcd_config);
-
- spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
-
- s3c_i2c0_set_platdata(&jive_i2c_cfg);
- i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
-
- pm_power_off = jive_power_off;
-
- gpiod_add_lookup_table(&jive_lcdspi_gpiod_table);
- gpiod_add_lookup_table(&jive_wm8750_gpiod_table);
- platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
-}
-
-MACHINE_START(JIVE, "JIVE")
- /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
- .atag_offset = 0x100,
-
- .init_irq = s3c2412_init_irq,
- .map_io = jive_map_io,
- .init_machine = jive_machine_init,
- .init_time = jive_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-mini2440.c b/arch/arm/mach-s3c/mach-mini2440.c
deleted file mode 100644
index 551ec660ab59..000000000000
--- a/arch/arm/mach-s3c/mach-mini2440.c
+++ /dev/null
@@ -1,796 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
-// Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
-// and modifications by SBZ <sbz@spgui.org> and
-// Weibing <http://weibing.blogbus.com> and
-// Michel Pollet <buserror@gmail.com>
-//
-// For product information, visit https://code.google.com/p/mini2440/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/dm9000.h>
-#include <linux/property.h>
-#include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
-#include <linux/i2c.h>
-#include <linux/mmc/host.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <linux/platform_data/fb-s3c2410.h>
-#include <asm/mach-types.h>
-
-#include "regs-gpio.h"
-#include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/irqs.h>
-#include "gpio-samsung.h"
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-
-#include "gpio-cfg.h"
-#include "devs.h"
-#include "cpu.h"
-
-#include <sound/s3c24xx_uda134x.h>
-
-#include "s3c24xx.h"
-
-#define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300)
-
-static struct map_desc mini2440_iodesc[] __initdata = {
- /* nothing to declare, move along */
-};
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
-#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
-
-
-static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
-};
-
-/* USB device UDC support */
-
-static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = {
- .pullup_pin = S3C2410_GPC(5),
-};
-
-
-/* LCD timing and setup */
-
-/*
- * This macro simplifies the table bellow
- */
-#define _LCD_DECLARE(_clock, _xres, margin_left, margin_right, hsync, \
- _yres, margin_top, margin_bottom, vsync, refresh) \
- .width = _xres, \
- .xres = _xres, \
- .height = _yres, \
- .yres = _yres, \
- .left_margin = margin_left, \
- .right_margin = margin_right, \
- .upper_margin = margin_top, \
- .lower_margin = margin_bottom, \
- .hsync_len = hsync, \
- .vsync_len = vsync, \
- .pixclock = ((_clock*100000000000LL) / \
- ((refresh) * \
- (hsync + margin_left + _xres + margin_right) * \
- (vsync + margin_top + _yres + margin_bottom))), \
- .bpp = 16,\
- .type = (S3C2410_LCDCON1_TFT16BPP |\
- S3C2410_LCDCON1_TFT)
-
-static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
- [0] = { /* mini2440 + 3.5" TFT + touchscreen */
- _LCD_DECLARE(
- 7, /* The 3.5 is quite fast */
- 240, 21, 38, 6, /* x timing */
- 320, 4, 4, 2, /* y timing */
- 60), /* refresh rate */
- .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_INVVDEN |
- S3C2410_LCDCON5_PWREN),
- },
- [1] = { /* mini2440 + 7" TFT + touchscreen */
- _LCD_DECLARE(
- 10, /* the 7" runs slower */
- 800, 40, 40, 48, /* x timing */
- 480, 29, 3, 3, /* y timing */
- 50), /* refresh rate */
- .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_PWREN),
- },
- /* The VGA shield can outout at several resolutions. All share
- * the same timings, however, anything smaller than 1024x768
- * will only be displayed in the top left corner of a 1024x768
- * XGA output unless you add optional dip switches to the shield.
- * Therefore timings for other resolutions have been omitted here.
- */
- [2] = {
- _LCD_DECLARE(
- 10,
- 1024, 1, 2, 2, /* y timing */
- 768, 200, 16, 16, /* x timing */
- 24), /* refresh rate, maximum stable,
- * tested with the FPGA shield
- */
- .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_HWSWP),
- },
- /* mini2440 + 3.5" TFT (LCD-W35i, LQ035Q1DG06 type) + touchscreen*/
- [3] = {
- _LCD_DECLARE(
- /* clock */
- 7,
- /* xres, margin_right, margin_left, hsync */
- 320, 68, 66, 4,
- /* yres, margin_top, margin_bottom, vsync */
- 240, 4, 4, 9,
- /* refresh rate */
- 60),
- .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVDEN |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVCLK |
- S3C2410_LCDCON5_HWSWP),
- },
-};
-
-/* todo - put into gpio header */
-
-#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
-#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
-
-static struct s3c2410fb_mach_info mini2440_fb_info __initdata = {
- .displays = &mini2440_lcd_cfg[0], /* not constant! see init */
- .num_displays = 1,
- .default_display = 0,
-
- /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
- * and disable the pull down resistors on pins we are using for LCD
- * data.
- */
-
- .gpcup = (0xf << 1) | (0x3f << 10),
-
- .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
- S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
- S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
- S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
- S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
-
- .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
- S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
- S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
- S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
- S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
-
- .gpccon_reg = S3C2410_GPCCON,
- .gpcup_reg = S3C2410_GPCUP,
-
- .gpdup = (0x3f << 2) | (0x3f << 10),
-
- .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
- S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
- S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
- S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
- S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
- S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
-
- .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
- S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
- S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
- S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
- S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
- S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
-
- .gpdcon_reg = S3C2410_GPDCON,
- .gpdup_reg = S3C2410_GPDUP,
-};
-
-/* MMC/SD */
-
-static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = {
- .wprotect_invert = 1,
- .set_power = s3c24xx_mci_def_set_power,
- .ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table mini2440_mmc_gpio_table = {
- .dev_id = "s3c2410-sdi",
- .table = {
- /* Card detect S3C2410_GPG(8) */
- GPIO_LOOKUP("GPIOG", 8, "cd", GPIO_ACTIVE_LOW),
- /* Write protect S3C2410_GPH(8) */
- GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_HIGH),
- /* bus pins */
- GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/* NAND Flash on MINI2440 board */
-
-static struct mtd_partition mini2440_default_nand_part[] __initdata = {
- [0] = {
- .name = "u-boot",
- .size = SZ_256K,
- .offset = 0,
- },
- [1] = {
- .name = "u-boot-env",
- .size = SZ_128K,
- .offset = SZ_256K,
- },
- [2] = {
- .name = "kernel",
- /* 5 megabytes, for a kernel with no modules
- * or a uImage with a ramdisk attached
- */
- .size = 0x00500000,
- .offset = SZ_256K + SZ_128K,
- },
- [3] = {
- .name = "root",
- .offset = SZ_256K + SZ_128K + 0x00500000,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = {
- [0] = {
- .name = "nand",
- .nr_chips = 1,
- .nr_partitions = ARRAY_SIZE(mini2440_default_nand_part),
- .partitions = mini2440_default_nand_part,
- .flash_bbt = 1, /* we use u-boot to create a BBT */
- },
-};
-
-static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
- .tacls = 0,
- .twrph0 = 25,
- .twrph1 = 15,
- .nr_sets = ARRAY_SIZE(mini2440_nand_sets),
- .sets = mini2440_nand_sets,
- .ignore_unset_ecc = 1,
- .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
-};
-
-/* DM9000AEP 10/100 ethernet controller */
-
-static struct resource mini2440_dm9k_resource[] = {
- [0] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE, 4),
- [1] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE + 4, 4),
- [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ
- | IORESOURCE_IRQ_HIGHEDGE),
-};
-
-/*
- * The DM9000 has no eeprom, and it's MAC address is set by
- * the bootloader before starting the kernel.
- */
-static struct dm9000_plat_data mini2440_dm9k_pdata = {
- .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
-};
-
-static struct platform_device mini2440_device_eth = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(mini2440_dm9k_resource),
- .resource = mini2440_dm9k_resource,
- .dev = {
- .platform_data = &mini2440_dm9k_pdata,
- },
-};
-
-/* CON5
- * +--+ /-----\
- * | | | |
- * | | | BAT |
- * | | \_____/
- * | |
- * | | +----+ +----+
- * | | | K5 | | K1 |
- * | | +----+ +----+
- * | | +----+ +----+
- * | | | K4 | | K2 |
- * | | +----+ +----+
- * | | +----+ +----+
- * | | | K6 | | K3 |
- * | | +----+ +----+
- * .....
- */
-static struct gpio_keys_button mini2440_buttons[] = {
- {
- .gpio = S3C2410_GPG(0), /* K1 */
- .code = KEY_F1,
- .desc = "Button 1",
- .active_low = 1,
- },
- {
- .gpio = S3C2410_GPG(3), /* K2 */
- .code = KEY_F2,
- .desc = "Button 2",
- .active_low = 1,
- },
- {
- .gpio = S3C2410_GPG(5), /* K3 */
- .code = KEY_F3,
- .desc = "Button 3",
- .active_low = 1,
- },
- {
- .gpio = S3C2410_GPG(6), /* K4 */
- .code = KEY_POWER,
- .desc = "Power",
- .active_low = 1,
- },
- {
- .gpio = S3C2410_GPG(7), /* K5 */
- .code = KEY_F5,
- .desc = "Button 5",
- .active_low = 1,
- },
-#if 0
- /* this pin is also known as TCLK1 and seems to already
- * marked as "in use" somehow in the kernel -- possibly wrongly
- */
- {
- .gpio = S3C2410_GPG(11), /* K6 */
- .code = KEY_F6,
- .desc = "Button 6",
- .active_low = 1,
- },
-#endif
-};
-
-static struct gpio_keys_platform_data mini2440_button_data = {
- .buttons = mini2440_buttons,
- .nbuttons = ARRAY_SIZE(mini2440_buttons),
-};
-
-static struct platform_device mini2440_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &mini2440_button_data,
- }
-};
-
-/* LEDS */
-
-static struct gpiod_lookup_table mini2440_led1_gpio_table = {
- .dev_id = "s3c24xx_led.1",
- .table = {
- GPIO_LOOKUP("GPB", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct gpiod_lookup_table mini2440_led2_gpio_table = {
- .dev_id = "s3c24xx_led.2",
- .table = {
- GPIO_LOOKUP("GPB", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct gpiod_lookup_table mini2440_led3_gpio_table = {
- .dev_id = "s3c24xx_led.3",
- .table = {
- GPIO_LOOKUP("GPB", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct gpiod_lookup_table mini2440_led4_gpio_table = {
- .dev_id = "s3c24xx_led.4",
- .table = {
- GPIO_LOOKUP("GPB", 8, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct gpiod_lookup_table mini2440_backlight_gpio_table = {
- .dev_id = "s3c24xx_led.5",
- .table = {
- GPIO_LOOKUP("GPG", 4, NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct s3c24xx_led_platdata mini2440_led1_pdata = {
- .name = "led1",
- .def_trigger = "heartbeat",
-};
-
-static struct s3c24xx_led_platdata mini2440_led2_pdata = {
- .name = "led2",
- .def_trigger = "nand-disk",
-};
-
-static struct s3c24xx_led_platdata mini2440_led3_pdata = {
- .name = "led3",
- .def_trigger = "mmc0",
-};
-
-static struct s3c24xx_led_platdata mini2440_led4_pdata = {
- .name = "led4",
- .def_trigger = "",
-};
-
-static struct s3c24xx_led_platdata mini2440_led_backlight_pdata = {
- .name = "backlight",
- .def_trigger = "backlight",
-};
-
-static struct platform_device mini2440_led1 = {
- .name = "s3c24xx_led",
- .id = 1,
- .dev = {
- .platform_data = &mini2440_led1_pdata,
- },
-};
-
-static struct platform_device mini2440_led2 = {
- .name = "s3c24xx_led",
- .id = 2,
- .dev = {
- .platform_data = &mini2440_led2_pdata,
- },
-};
-
-static struct platform_device mini2440_led3 = {
- .name = "s3c24xx_led",
- .id = 3,
- .dev = {
- .platform_data = &mini2440_led3_pdata,
- },
-};
-
-static struct platform_device mini2440_led4 = {
- .name = "s3c24xx_led",
- .id = 4,
- .dev = {
- .platform_data = &mini2440_led4_pdata,
- },
-};
-
-static struct platform_device mini2440_led_backlight = {
- .name = "s3c24xx_led",
- .id = 5,
- .dev = {
- .platform_data = &mini2440_led_backlight_pdata,
- },
-};
-
-/* AUDIO */
-
-static struct s3c24xx_uda134x_platform_data mini2440_audio_pins = {
- .l3_clk = S3C2410_GPB(4),
- .l3_mode = S3C2410_GPB(2),
- .l3_data = S3C2410_GPB(3),
- .model = UDA134X_UDA1341
-};
-
-static struct platform_device mini2440_audio = {
- .name = "s3c24xx_uda134x",
- .id = 0,
- .dev = {
- .platform_data = &mini2440_audio_pins,
- },
-};
-
-/*
- * I2C devices
- */
-static const struct property_entry mini2440_at24_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 16),
- { }
-};
-
-static const struct software_node mini2440_at24_node = {
- .properties = mini2440_at24_properties,
-};
-
-static struct i2c_board_info mini2440_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("24c08", 0x50),
- .swnode = &mini2440_at24_node,
- },
-};
-
-static struct uda134x_platform_data s3c24xx_uda134x = {
- .l3 = {
- .gpio_clk = S3C2410_GPB(4),
- .gpio_data = S3C2410_GPB(3),
- .gpio_mode = S3C2410_GPB(2),
- .use_gpios = 1,
- .data_hold = 1,
- .data_setup = 1,
- .clock_high = 1,
- .mode_hold = 1,
- .mode = 1,
- .mode_setup = 1,
- },
- .model = UDA134X_UDA1341,
-};
-
-static struct platform_device uda1340_codec = {
- .name = "uda134x-codec",
- .id = -1,
- .dev = {
- .platform_data = &s3c24xx_uda134x,
- },
-};
-
-static struct platform_device *mini2440_devices[] __initdata = {
- &s3c_device_ohci,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_rtc,
- &s3c_device_usbgadget,
- &mini2440_device_eth,
- &mini2440_led1,
- &mini2440_led2,
- &mini2440_led3,
- &mini2440_led4,
- &mini2440_button_device,
- &s3c_device_nand,
- &s3c_device_sdi,
- &s3c2440_device_dma,
- &s3c_device_iis,
- &uda1340_codec,
- &mini2440_audio,
-};
-
-static void __init mini2440_map_io(void)
-{
- s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
- s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-static void __init mini2440_init_time(void)
-{
- s3c2440_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-/*
- * mini2440_features string
- *
- * t = Touchscreen present
- * b = backlight control
- * c = camera [TODO]
- * 0-9 LCD configuration
- *
- */
-static char mini2440_features_str[12] __initdata = "0tb";
-
-static int __init mini2440_features_setup(char *str)
-{
- if (str)
- strlcpy(mini2440_features_str, str,
- sizeof(mini2440_features_str));
- return 1;
-}
-
-__setup("mini2440=", mini2440_features_setup);
-
-#define FEATURE_SCREEN (1 << 0)
-#define FEATURE_BACKLIGHT (1 << 1)
-#define FEATURE_TOUCH (1 << 2)
-#define FEATURE_CAMERA (1 << 3)
-
-struct mini2440_features_t {
- int count;
- int done;
- int lcd_index;
- struct platform_device *optional[8];
-};
-
-static void __init mini2440_parse_features(
- struct mini2440_features_t *features,
- const char *features_str)
-{
- const char *fp = features_str;
-
- features->count = 0;
- features->done = 0;
- features->lcd_index = -1;
-
- while (*fp) {
- char f = *fp++;
-
- switch (f) {
- case '0'...'9': /* tft screen */
- if (features->done & FEATURE_SCREEN) {
- pr_info("MINI2440: '%c' ignored, screen type already set\n",
- f);
- } else {
- int li = f - '0';
-
- if (li >= ARRAY_SIZE(mini2440_lcd_cfg))
- pr_info("MINI2440: '%c' out of range LCD mode\n",
- f);
- else {
- features->optional[features->count++] =
- &s3c_device_lcd;
- features->lcd_index = li;
- }
- }
- features->done |= FEATURE_SCREEN;
- break;
- case 'b':
- if (features->done & FEATURE_BACKLIGHT)
- pr_info("MINI2440: '%c' ignored, backlight already set\n",
- f);
- else {
- features->optional[features->count++] =
- &mini2440_led_backlight;
- }
- features->done |= FEATURE_BACKLIGHT;
- break;
- case 't':
- pr_info("MINI2440: '%c' ignored, touchscreen not compiled in\n",
- f);
- break;
- case 'c':
- if (features->done & FEATURE_CAMERA)
- pr_info("MINI2440: '%c' ignored, camera already registered\n",
- f);
- else
- features->optional[features->count++] =
- &s3c_device_camif;
- features->done |= FEATURE_CAMERA;
- break;
- }
- }
-}
-
-static void __init mini2440_init(void)
-{
- struct mini2440_features_t features = { 0 };
- int i;
-
- pr_info("MINI2440: Option string mini2440=%s\n",
- mini2440_features_str);
-
- /* Parse the feature string */
- mini2440_parse_features(&features, mini2440_features_str);
-
- /* turn LCD on */
- s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
-
- /* Turn the backlight early on */
- WARN_ON(gpio_request_one(S3C2410_GPG(4), GPIOF_OUT_INIT_HIGH, NULL));
- gpio_free(S3C2410_GPG(4));
-
- /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
- gpio_request_one(S3C2410_GPB(1), GPIOF_IN, NULL);
- s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
- gpio_free(S3C2410_GPB(1));
-
- /* mark the key as input, without pullups (there is one on the board) */
- for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
- s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT);
- }
-
- /* Configure the I2S pins (GPE0...GPE4) in correct mode */
- s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
- S3C_GPIO_PULL_NONE);
-
- if (features.lcd_index != -1) {
- int li;
-
- mini2440_fb_info.displays =
- &mini2440_lcd_cfg[features.lcd_index];
-
- pr_info("MINI2440: LCD");
- for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++)
- if (li == features.lcd_index)
- pr_cont(" [%d:%dx%d]", li,
- mini2440_lcd_cfg[li].width,
- mini2440_lcd_cfg[li].height);
- else
- pr_cont(" %d:%dx%d", li,
- mini2440_lcd_cfg[li].width,
- mini2440_lcd_cfg[li].height);
- pr_cont("\n");
- s3c24xx_fb_set_platdata(&mini2440_fb_info);
- }
-
- s3c24xx_udc_set_platdata(&mini2440_udc_cfg);
- gpiod_add_lookup_table(&mini2440_mmc_gpio_table);
- s3c24xx_mci_set_platdata(&mini2440_mmc_cfg);
- s3c_nand_set_platdata(&mini2440_nand_info);
- s3c_i2c0_set_platdata(NULL);
-
- i2c_register_board_info(0, mini2440_i2c_devs,
- ARRAY_SIZE(mini2440_i2c_devs));
-
- /* Disable pull-up on the LED lines */
- s3c_gpio_setpull(S3C2410_GPB(5), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPB(6), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPB(7), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPB(8), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPG(4), S3C_GPIO_PULL_NONE);
-
- /* Add lookups for the lines */
- gpiod_add_lookup_table(&mini2440_led1_gpio_table);
- gpiod_add_lookup_table(&mini2440_led2_gpio_table);
- gpiod_add_lookup_table(&mini2440_led3_gpio_table);
- gpiod_add_lookup_table(&mini2440_led4_gpio_table);
- gpiod_add_lookup_table(&mini2440_backlight_gpio_table);
-
- platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices));
-
- if (features.count) /* the optional features */
- platform_add_devices(features.optional, features.count);
-
-}
-
-
-MACHINE_START(MINI2440, "MINI2440")
- /* Maintainer: Michel Pollet <buserror@gmail.com> */
- .atag_offset = 0x100,
- .map_io = mini2440_map_io,
- .init_machine = mini2440_init,
- .init_irq = s3c2440_init_irq,
- .init_time = mini2440_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-mini6410.c b/arch/arm/mach-s3c/mach-mini6410.c
deleted file mode 100644
index c14c2e27127b..000000000000
--- a/arch/arm/mach-s3c/mach-mini6410.c
+++ /dev/null
@@ -1,365 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
-// Copyright 2008 Openmoko, Inc.
-// Copyright 2008 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-// http://armlinux.simtec.co.uk/
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/dm9000.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/types.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "map.h"
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-
-#include <linux/soc/samsung/s3c-adc.h>
-#include "cpu.h"
-#include "devs.h"
-#include "fb.h"
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/mmc-sdhci-s3c.h>
-#include "sdhci.h"
-#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <mach/irqs.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include "s3c64xx.h"
-#include "regs-modem-s3c64xx.h"
-#include "regs-srom-s3c64xx.h"
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
-#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
-
-static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [3] = {
- .hwport = 3,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
-};
-
-/* DM9000AEP 10/100 ethernet controller */
-
-static struct resource mini6410_dm9k_resource[] = {
- [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
- [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
- [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
- | IORESOURCE_IRQ_HIGHLEVEL),
-};
-
-static struct dm9000_plat_data mini6410_dm9k_pdata = {
- .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
-};
-
-static struct platform_device mini6410_device_eth = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
- .resource = mini6410_dm9k_resource,
- .dev = {
- .platform_data = &mini6410_dm9k_pdata,
- },
-};
-
-static struct mtd_partition mini6410_nand_part[] = {
- [0] = {
- .name = "uboot",
- .size = SZ_1M,
- .offset = 0,
- },
- [1] = {
- .name = "kernel",
- .size = SZ_2M,
- .offset = SZ_1M,
- },
- [2] = {
- .name = "rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = SZ_1M + SZ_2M,
- },
-};
-
-static struct s3c2410_nand_set mini6410_nand_sets[] = {
- [0] = {
- .name = "nand",
- .nr_chips = 1,
- .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
- .partitions = mini6410_nand_part,
- },
-};
-
-static struct s3c2410_platform_nand mini6410_nand_info = {
- .tacls = 25,
- .twrph0 = 55,
- .twrph1 = 40,
- .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
- .sets = mini6410_nand_sets,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
- .max_bpp = 32,
- .default_bpp = 16,
- .xres = 480,
- .yres = 272,
-};
-
-static struct fb_videomode mini6410_lcd_type0_timing = {
- /* 4.3" 480x272 */
- .left_margin = 3,
- .right_margin = 2,
- .upper_margin = 1,
- .lower_margin = 1,
- .hsync_len = 40,
- .vsync_len = 1,
- .xres = 480,
- .yres = 272,
-};
-
-static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
- .max_bpp = 32,
- .default_bpp = 16,
- .xres = 800,
- .yres = 480,
-};
-
-static struct fb_videomode mini6410_lcd_type1_timing = {
- /* 7.0" 800x480 */
- .left_margin = 8,
- .right_margin = 13,
- .upper_margin = 7,
- .lower_margin = 5,
- .hsync_len = 3,
- .vsync_len = 1,
- .xres = 800,
- .yres = 480,
-};
-
-static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
- {
- .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
- .vtiming = &mini6410_lcd_type0_timing,
- .win[0] = &mini6410_lcd_type0_fb_win,
- .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
- .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
- }, {
- .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
- .vtiming = &mini6410_lcd_type1_timing,
- .win[0] = &mini6410_lcd_type1_fb_win,
- .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
- .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
- },
- { },
-};
-
-static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
- unsigned int power)
-{
- if (power)
- gpio_direction_output(S3C64XX_GPE(0), 1);
- else
- gpio_direction_output(S3C64XX_GPE(0), 0);
-}
-
-static struct plat_lcd_data mini6410_lcd_power_data = {
- .set_power = mini6410_lcd_power_set,
-};
-
-static struct platform_device mini6410_lcd_powerdev = {
- .name = "platform-lcd",
- .dev.parent = &s3c_device_fb.dev,
- .dev.platform_data = &mini6410_lcd_power_data,
-};
-
-static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = {
- .max_width = 4,
- .cd_type = S3C_SDHCI_CD_GPIO,
- .ext_cd_gpio = S3C64XX_GPN(10),
- .ext_cd_gpio_invert = true,
-};
-
-static struct platform_device *mini6410_devices[] __initdata = {
- &mini6410_device_eth,
- &s3c_device_hsmmc0,
- &s3c_device_hsmmc1,
- &s3c_device_ohci,
- &s3c_device_nand,
- &s3c_device_fb,
- &mini6410_lcd_powerdev,
- &s3c_device_adc,
-};
-
-static void __init mini6410_map_io(void)
-{
- u32 tmp;
-
- s3c64xx_init_io(NULL, 0);
- s3c64xx_set_xtal_freq(12000000);
- s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
- s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
-
- /* set the LCD type */
- tmp = __raw_readl(S3C64XX_SPCON);
- tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
- tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
- __raw_writel(tmp, S3C64XX_SPCON);
-
- /* remove the LCD bypass */
- tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
- tmp &= ~MIFPCON_LCD_BYPASS;
- __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
-}
-
-/*
- * mini6410_features string
- *
- * 0-9 LCD configuration
- *
- */
-static char mini6410_features_str[12] __initdata = "0";
-
-static int __init mini6410_features_setup(char *str)
-{
- if (str)
- strscpy(mini6410_features_str, str,
- sizeof(mini6410_features_str));
- return 1;
-}
-
-__setup("mini6410=", mini6410_features_setup);
-
-#define FEATURE_SCREEN (1 << 0)
-
-struct mini6410_features_t {
- int done;
- int lcd_index;
-};
-
-static void mini6410_parse_features(
- struct mini6410_features_t *features,
- const char *features_str)
-{
- const char *fp = features_str;
-
- features->done = 0;
- features->lcd_index = 0;
-
- while (*fp) {
- char f = *fp++;
-
- switch (f) {
- case '0'...'9': /* tft screen */
- if (features->done & FEATURE_SCREEN) {
- printk(KERN_INFO "MINI6410: '%c' ignored, "
- "screen type already set\n", f);
- } else {
- int li = f - '0';
- if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
- printk(KERN_INFO "MINI6410: '%c' out "
- "of range LCD mode\n", f);
- else {
- features->lcd_index = li;
- }
- }
- features->done |= FEATURE_SCREEN;
- break;
- }
- }
-}
-
-static void __init mini6410_machine_init(void)
-{
- u32 cs1;
- struct mini6410_features_t features = { 0 };
-
- printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
- mini6410_features_str);
-
- /* Parse the feature string */
- mini6410_parse_features(&features, mini6410_features_str);
-
- printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
- mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
- mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
-
- s3c_nand_set_platdata(&mini6410_nand_info);
- s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
- s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata);
- s3c64xx_ts_set_platdata(NULL);
-
- /* configure nCS1 width to 16 bits */
-
- cs1 = __raw_readl(S3C64XX_SROM_BW) &
- ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
- cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
- (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
- (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
- S3C64XX_SROM_BW__NCS1__SHIFT;
- __raw_writel(cs1, S3C64XX_SROM_BW);
-
- /* set timing for nCS1 suitable for ethernet chip */
-
- __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
- (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
- (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
- (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
- (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
- (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
- (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
-
- gpio_request(S3C64XX_GPF(15), "LCD power");
- gpio_request(S3C64XX_GPE(0), "LCD power");
-
- platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
-}
-
-MACHINE_START(MINI6410, "MINI6410")
- /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
- .atag_offset = 0x100,
- .nr_irqs = S3C64XX_NR_IRQS,
- .init_irq = s3c6410_init_irq,
- .map_io = mini6410_map_io,
- .init_machine = mini6410_machine_init,
- .init_time = s3c64xx_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-n30.c b/arch/arm/mach-s3c/mach-n30.c
deleted file mode 100644
index e40c1fcf418c..000000000000
--- a/arch/arm/mach-s3c/mach-n30.c
+++ /dev/null
@@ -1,673 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Machine specific code for the Acer n30, Acer N35, Navman PiN 570,
-// Yakumo AlphaX and Airis NC05 PDAs.
-//
-// Copyright (c) 2003-2005 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-//
-// Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se>
-//
-// There is a wiki with more information about the n30 port at
-// https://handhelds.org/moin/moin.cgi/AcerN30Documentation .
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include <linux/gpio_keys.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <linux/mmc/host.h>
-
-#include "hardware-s3c24xx.h"
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <linux/platform_data/fb-s3c2410.h>
-#include <linux/platform_data/leds-s3c24xx.h>
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-#include "gpio-cfg.h"
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include "cpu.h"
-#include "devs.h"
-#include <linux/platform_data/mmc-s3cmci.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-
-#include "s3c24xx.h"
-
-static struct map_desc n30_iodesc[] __initdata = {
- /* nothing here yet */
-};
-
-static struct s3c2410_uartcfg n30_uartcfgs[] = {
- /* Normal serial port */
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = 0x2c5,
- .ulcon = 0x03,
- .ufcon = 0x51,
- },
- /* IR port */
- [1] = {
- .hwport = 1,
- .flags = 0,
- .uart_flags = UPF_CONS_FLOW,
- .ucon = 0x2c5,
- .ulcon = 0x43,
- .ufcon = 0x51,
- },
- /* On the N30 the bluetooth controller is connected here.
- * On the N35 and variants the GPS receiver is connected here. */
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = 0x2c5,
- .ulcon = 0x03,
- .ufcon = 0x51,
- },
-};
-
-static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
- .vbus_pin = S3C2410_GPG(1),
- .vbus_pin_inverted = 0,
- .pullup_pin = S3C2410_GPB(3),
-};
-
-static struct gpio_keys_button n30_buttons[] = {
- {
- .gpio = S3C2410_GPF(0),
- .code = KEY_POWER,
- .desc = "Power",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(9),
- .code = KEY_UP,
- .desc = "Thumbwheel Up",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(8),
- .code = KEY_DOWN,
- .desc = "Thumbwheel Down",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(7),
- .code = KEY_ENTER,
- .desc = "Thumbwheel Press",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(7),
- .code = KEY_HOMEPAGE,
- .desc = "Home",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(6),
- .code = KEY_CALENDAR,
- .desc = "Calendar",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(5),
- .code = KEY_ADDRESSBOOK,
- .desc = "Contacts",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(4),
- .code = KEY_MAIL,
- .desc = "Mail",
- .active_low = 0,
- },
-};
-
-static struct gpio_keys_platform_data n30_button_data = {
- .buttons = n30_buttons,
- .nbuttons = ARRAY_SIZE(n30_buttons),
-};
-
-static struct platform_device n30_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &n30_button_data,
- }
-};
-
-static struct gpio_keys_button n35_buttons[] = {
- {
- .gpio = S3C2410_GPF(0),
- .code = KEY_POWER,
- .type = EV_PWR,
- .desc = "Power",
- .active_low = 0,
- .wakeup = 1,
- },
- {
- .gpio = S3C2410_GPG(9),
- .code = KEY_UP,
- .desc = "Joystick Up",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(8),
- .code = KEY_DOWN,
- .desc = "Joystick Down",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(6),
- .code = KEY_DOWN,
- .desc = "Joystick Left",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(5),
- .code = KEY_DOWN,
- .desc = "Joystick Right",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(7),
- .code = KEY_ENTER,
- .desc = "Joystick Press",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(7),
- .code = KEY_HOMEPAGE,
- .desc = "Home",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(6),
- .code = KEY_CALENDAR,
- .desc = "Calendar",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(5),
- .code = KEY_ADDRESSBOOK,
- .desc = "Contacts",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(4),
- .code = KEY_MAIL,
- .desc = "Mail",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPF(3),
- .code = SW_RADIO,
- .desc = "GPS Antenna",
- .active_low = 0,
- },
- {
- .gpio = S3C2410_GPG(2),
- .code = SW_HEADPHONE_INSERT,
- .desc = "Headphone",
- .active_low = 0,
- },
-};
-
-static struct gpio_keys_platform_data n35_button_data = {
- .buttons = n35_buttons,
- .nbuttons = ARRAY_SIZE(n35_buttons),
-};
-
-static struct platform_device n35_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &n35_button_data,
- }
-};
-
-/* This is the bluetooth LED on the device. */
-
-static struct gpiod_lookup_table n30_blue_led_gpio_table = {
- .dev_id = "s3c24xx_led.1",
- .table = {
- GPIO_LOOKUP("GPG", 6, NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct s3c24xx_led_platdata n30_blue_led_pdata = {
- .name = "blue_led",
- .def_trigger = "",
-};
-
-/* This is the blue LED on the device. Originally used to indicate GPS activity
- * by flashing. */
-
-static struct gpiod_lookup_table n35_blue_led_gpio_table = {
- .dev_id = "s3c24xx_led.1",
- .table = {
- GPIO_LOOKUP("GPD", 8, NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct s3c24xx_led_platdata n35_blue_led_pdata = {
- .name = "blue_led",
- .def_trigger = "",
-};
-
-/* This LED is driven by the battery microcontroller, and is blinking
- * red, blinking green or solid green when the battery is low,
- * charging or full respectively. By driving GPD9 low, it's possible
- * to force the LED to blink red, so call that warning LED. */
-
-static struct gpiod_lookup_table n30_warning_led_gpio_table = {
- .dev_id = "s3c24xx_led.2",
- .table = {
- GPIO_LOOKUP("GPD", 9, NULL, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static struct s3c24xx_led_platdata n30_warning_led_pdata = {
- .name = "warning_led",
- .def_trigger = "",
-};
-
-static struct gpiod_lookup_table n35_warning_led_gpio_table = {
- .dev_id = "s3c24xx_led.2",
- .table = {
- GPIO_LOOKUP("GPD", 9, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct s3c24xx_led_platdata n35_warning_led_pdata = {
- .name = "warning_led",
- .def_trigger = "",
-};
-
-static struct platform_device n30_blue_led = {
- .name = "s3c24xx_led",
- .id = 1,
- .dev = {
- .platform_data = &n30_blue_led_pdata,
- },
-};
-
-static struct platform_device n35_blue_led = {
- .name = "s3c24xx_led",
- .id = 1,
- .dev = {
- .platform_data = &n35_blue_led_pdata,
- },
-};
-
-static struct platform_device n30_warning_led = {
- .name = "s3c24xx_led",
- .id = 2,
- .dev = {
- .platform_data = &n30_warning_led_pdata,
- },
-};
-
-static struct platform_device n35_warning_led = {
- .name = "s3c24xx_led",
- .id = 2,
- .dev = {
- .platform_data = &n35_warning_led_pdata,
- },
-};
-
-static struct s3c2410fb_display n30_display __initdata = {
- .type = S3C2410_LCDCON1_TFT,
- .width = 240,
- .height = 320,
- .pixclock = 170000,
-
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .left_margin = 3,
- .right_margin = 40,
- .hsync_len = 40,
- .upper_margin = 2,
- .lower_margin = 3,
- .vsync_len = 2,
-
- .lcdcon5 = S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVFRAME,
-};
-
-static struct s3c2410fb_mach_info n30_fb_info __initdata = {
- .displays = &n30_display,
- .num_displays = 1,
- .default_display = 0,
- .lpcsel = 0x06,
-};
-
-static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd)
-{
- s3c24xx_mci_def_set_power(power_mode, vdd);
-
- switch (power_mode) {
- case MMC_POWER_ON:
- case MMC_POWER_UP:
- gpio_set_value(S3C2410_GPG(4), 1);
- break;
- case MMC_POWER_OFF:
- default:
- gpio_set_value(S3C2410_GPG(4), 0);
- break;
- }
-}
-
-static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = {
- .ocr_avail = MMC_VDD_32_33,
- .set_power = n30_sdi_set_power,
-};
-
-static struct gpiod_lookup_table n30_mci_gpio_table = {
- .dev_id = "s3c2410-sdi",
- .table = {
- /* Card detect S3C2410_GPF(1) */
- GPIO_LOOKUP("GPIOF", 1, "cd", GPIO_ACTIVE_LOW),
- /* Write protect S3C2410_GPG(10) */
- GPIO_LOOKUP("GPIOG", 10, "wp", GPIO_ACTIVE_LOW),
- { },
- /* bus pins */
- GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
- },
-};
-
-static struct platform_device *n30_devices[] __initdata = {
- &s3c_device_lcd,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_iis,
- &s3c_device_ohci,
- &s3c_device_rtc,
- &s3c_device_usbgadget,
- &s3c_device_sdi,
- &n30_button_device,
- &n30_blue_led,
- &n30_warning_led,
-};
-
-static struct platform_device *n35_devices[] __initdata = {
- &s3c_device_lcd,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_iis,
- &s3c_device_rtc,
- &s3c_device_usbgadget,
- &s3c_device_sdi,
- &n35_button_device,
- &n35_blue_led,
- &n35_warning_led,
-};
-
-static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
- .flags = 0,
- .slave_addr = 0x10,
- .frequency = 10*1000,
-};
-
-/* Lots of hardcoded stuff, but it sets up the hardware in a useful
- * state so that we can boot Linux directly from flash. */
-static void __init n30_hwinit(void)
-{
- /* GPA0-11 special functions -- unknown what they do
- * GPA12 N30 special function -- unknown what it does
- * N35/PiN output -- unknown what it does
- *
- * A12 is nGCS1 on the N30 and an output on the N35/PiN. I
- * don't think it does anything useful on the N30, so I ought
- * to make it an output there too since it always driven to 0
- * as far as I can tell. */
- if (machine_is_n30())
- __raw_writel(0x007fffff, S3C2410_GPACON);
- if (machine_is_n35())
- __raw_writel(0x007fefff, S3C2410_GPACON);
- __raw_writel(0x00000000, S3C2410_GPADAT);
-
- /* GPB0 TOUT0 backlight level
- * GPB1 output 1=backlight on
- * GPB2 output IrDA enable 0=transceiver enabled, 1=disabled
- * GPB3 output USB D+ pull up 0=disabled, 1=enabled
- * GPB4 N30 output -- unknown function
- * N30/PiN GPS control 0=GPS enabled, 1=GPS disabled
- * GPB5 output -- unknown function
- * GPB6 input -- unknown function
- * GPB7 output -- unknown function
- * GPB8 output -- probably LCD driver enable
- * GPB9 output -- probably LCD VSYNC driver enable
- * GPB10 output -- probably LCD HSYNC driver enable
- */
- __raw_writel(0x00154556, S3C2410_GPBCON);
- __raw_writel(0x00000750, S3C2410_GPBDAT);
- __raw_writel(0x00000073, S3C2410_GPBUP);
-
- /* GPC0 input RS232 DCD/DSR/RI
- * GPC1 LCD
- * GPC2 output RS232 DTR?
- * GPC3 input RS232 DCD/DSR/RI
- * GPC4 LCD
- * GPC5 output 0=NAND write enabled, 1=NAND write protect
- * GPC6 input -- unknown function
- * GPC7 input charger status 0=charger connected
- * this input can be triggered by power on the USB device
- * port too, but will go back to disconnected soon after.
- * GPC8 N30/N35 output -- unknown function, always driven to 1
- * PiN input -- unknown function, always read as 1
- * Make it an input with a pull up for all models.
- * GPC9-15 LCD
- */
- __raw_writel(0xaaa80618, S3C2410_GPCCON);
- __raw_writel(0x0000014c, S3C2410_GPCDAT);
- __raw_writel(0x0000fef2, S3C2410_GPCUP);
-
- /* GPD0 input -- unknown function
- * GPD1-D7 LCD
- * GPD8 N30 output -- unknown function
- * N35/PiN output 1=GPS LED on
- * GPD9 output 0=power led blinks red, 1=normal power led function
- * GPD10 output -- unknown function
- * GPD11-15 LCD drivers
- */
- __raw_writel(0xaa95aaa4, S3C2410_GPDCON);
- __raw_writel(0x00000601, S3C2410_GPDDAT);
- __raw_writel(0x0000fbfe, S3C2410_GPDUP);
-
- /* GPE0-4 I2S audio bus
- * GPE5-10 SD/MMC bus
- * E11-13 outputs -- unknown function, probably power management
- * E14-15 I2C bus connected to the battery controller
- */
- __raw_writel(0xa56aaaaa, S3C2410_GPECON);
- __raw_writel(0x0000efc5, S3C2410_GPEDAT);
- __raw_writel(0x0000f81f, S3C2410_GPEUP);
-
- /* GPF0 input 0=power button pressed
- * GPF1 input SD/MMC switch 0=card present
- * GPF2 N30 1=reset button pressed (inverted compared to the rest)
- * N35/PiN 0=reset button pressed
- * GPF3 N30/PiN input -- unknown function
- * N35 input GPS antenna position, 0=antenna closed, 1=open
- * GPF4 input 0=button 4 pressed
- * GPF5 input 0=button 3 pressed
- * GPF6 input 0=button 2 pressed
- * GPF7 input 0=button 1 pressed
- */
- __raw_writel(0x0000aaaa, S3C2410_GPFCON);
- __raw_writel(0x00000000, S3C2410_GPFDAT);
- __raw_writel(0x000000ff, S3C2410_GPFUP);
-
- /* GPG0 input RS232 DCD/DSR/RI
- * GPG1 input 1=USB gadget port has power from a host
- * GPG2 N30 input -- unknown function
- * N35/PiN input 0=headphones plugged in, 1=not plugged in
- * GPG3 N30 output -- unknown function
- * N35/PiN input with unknown function
- * GPG4 N30 output 0=MMC enabled, 1=MMC disabled
- * GPG5 N30 output 0=BlueTooth chip disabled, 1=enabled
- * N35/PiN input joystick right
- * GPG6 N30 output 0=blue led on, 1=off
- * N35/PiN input joystick left
- * GPG7 input 0=thumbwheel pressed
- * GPG8 input 0=thumbwheel down
- * GPG9 input 0=thumbwheel up
- * GPG10 input SD/MMC write protect switch
- * GPG11 N30 input -- unknown function
- * N35 output 0=GPS antenna powered, 1=not powered
- * PiN output -- unknown function
- * GPG12-15 touch screen functions
- *
- * The pullups differ between the models, so enable all
- * pullups that are enabled on any of the models.
- */
- if (machine_is_n30())
- __raw_writel(0xff0a956a, S3C2410_GPGCON);
- if (machine_is_n35())
- __raw_writel(0xff4aa92a, S3C2410_GPGCON);
- __raw_writel(0x0000e800, S3C2410_GPGDAT);
- __raw_writel(0x0000f86f, S3C2410_GPGUP);
-
- /* GPH0/1/2/3 RS232 serial port
- * GPH4/5 IrDA serial port
- * GPH6/7 N30 BlueTooth serial port
- * N35/PiN GPS receiver
- * GPH8 input -- unknown function
- * GPH9 CLKOUT0 HCLK -- unknown use
- * GPH10 CLKOUT1 FCLK -- unknown use
- *
- * The pull ups for H6/H7 are enabled on N30 but not on the
- * N35/PiN. I suppose is useful for a budget model of the N30
- * with no bluetooth. It doesn't hurt to have the pull ups
- * enabled on the N35, so leave them enabled for all models.
- */
- __raw_writel(0x0028aaaa, S3C2410_GPHCON);
- __raw_writel(0x000005ef, S3C2410_GPHDAT);
- __raw_writel(0x0000063f, S3C2410_GPHUP);
-}
-
-static void __init n30_map_io(void)
-{
- s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
- n30_hwinit();
- s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-static void __init n30_init_time(void)
-{
- s3c2410_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-/* GPB3 is the line that controls the pull-up for the USB D+ line */
-
-static void __init n30_init(void)
-{
- WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power"));
-
- s3c24xx_fb_set_platdata(&n30_fb_info);
- s3c24xx_udc_set_platdata(&n30_udc_cfg);
- gpiod_add_lookup_table(&n30_mci_gpio_table);
- s3c24xx_mci_set_platdata(&n30_mci_cfg);
- s3c_i2c0_set_platdata(&n30_i2ccfg);
-
- /* Turn off suspend on both USB ports, and switch the
- * selectable USB port to USB device mode. */
-
- s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
- S3C2410_MISCCR_USBSUSPND0 |
- S3C2410_MISCCR_USBSUSPND1, 0x0);
-
- /* Configure the I2S pins (GPE0...GPE4) in correct mode */
- s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
- S3C_GPIO_PULL_NONE);
-
- if (machine_is_n30()) {
- /* Turn off suspend on both USB ports, and switch the
- * selectable USB port to USB device mode. */
- s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
- S3C2410_MISCCR_USBSUSPND0 |
- S3C2410_MISCCR_USBSUSPND1, 0x0);
-
- /* Disable pull-up and add GPIO tables */
- s3c_gpio_setpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
- gpiod_add_lookup_table(&n30_blue_led_gpio_table);
- gpiod_add_lookup_table(&n30_warning_led_gpio_table);
-
- platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
- }
-
- if (machine_is_n35()) {
- /* Turn off suspend and switch the selectable USB port
- * to USB device mode. Turn on suspend for the host
- * port since it is not connected on the N35.
- *
- * Actually, the host port is available at some pads
- * on the back of the device, so it would actually be
- * possible to add a USB device inside the N35 if you
- * are willing to do some hardware modifications. */
- s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
- S3C2410_MISCCR_USBSUSPND0 |
- S3C2410_MISCCR_USBSUSPND1,
- S3C2410_MISCCR_USBSUSPND0);
-
- /* Disable pull-up and add GPIO tables */
- s3c_gpio_setpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
- s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
- gpiod_add_lookup_table(&n35_blue_led_gpio_table);
- gpiod_add_lookup_table(&n35_warning_led_gpio_table);
-
- platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
- }
-}
-
-MACHINE_START(N30, "Acer-N30")
- /* Maintainer: Christer Weinigel <christer@weinigel.se>,
- Ben Dooks <ben-linux@fluff.org>
- */
- .atag_offset = 0x100,
- .init_time = n30_init_time,
- .init_machine = n30_init,
- .init_irq = s3c2410_init_irq,
- .map_io = n30_map_io,
-MACHINE_END
-
-MACHINE_START(N35, "Acer-N35")
- /* Maintainer: Christer Weinigel <christer@weinigel.se>
- */
- .atag_offset = 0x100,
- .init_time = n30_init_time,
- .init_machine = n30_init,
- .init_irq = s3c2410_init_irq,
- .map_io = n30_map_io,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-ncp.c b/arch/arm/mach-s3c/mach-ncp.c
deleted file mode 100644
index 1a45bed56622..000000000000
--- a/arch/arm/mach-s3c/mach-ncp.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (C) 2008-2009 Samsung Electronics
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/irqs.h>
-#include "map.h"
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <linux/platform_data/i2c-s3c2410.h>
-#include "fb.h"
-
-#include "devs.h"
-#include "cpu.h"
-
-#include "s3c64xx.h"
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
- /* REVISIT: NCP uses only serial 1, 2 */
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
-};
-
-static struct platform_device *ncp_devices[] __initdata = {
- &s3c_device_hsmmc1,
- &s3c_device_i2c0,
-};
-
-static struct map_desc ncp_iodesc[] __initdata = {};
-
-static void __init ncp_map_io(void)
-{
- s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
- s3c64xx_set_xtal_freq(12000000);
- s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
- s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
-}
-
-static void __init ncp_machine_init(void)
-{
- s3c_i2c0_set_platdata(NULL);
-
- platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
-}
-
-MACHINE_START(NCP, "NCP")
- /* Maintainer: Samsung Electronics */
- .atag_offset = 0x100,
- .nr_irqs = S3C64XX_NR_IRQS,
- .init_irq = s3c6410_init_irq,
- .map_io = ncp_map_io,
- .init_machine = ncp_machine_init,
- .init_time = s3c64xx_timer_init,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-nexcoder.c b/arch/arm/mach-s3c/mach-nexcoder.c
deleted file mode 100644
index 2a454c919658..000000000000
--- a/arch/arm/mach-s3c/mach-nexcoder.c
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-// linux/arch/arm/mach-s3c2440/mach-nexcoder.c
-//
-// Copyright (c) 2004 Nex Vision
-// Guillaume GOURAT <guillaume.gourat@nexvision.tv>
-//
-// Modifications:
-// 15-10-2004 GG Created initial version
-// 12-03-2005 BJD Updated for release
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/string.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mtd/map.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/setup.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-//#include <asm/debug-ll.h>
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include "gpio-cfg.h"
-#include "devs.h"
-#include "cpu.h"
-
-#include "s3c24xx.h"
-
-static struct map_desc nexcoder_iodesc[] __initdata = {
- /* nothing here yet */
-};
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- }
-};
-
-/* NOR Flash on NexVision NexCoder 2440 board */
-
-static struct resource nexcoder_nor_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS0, SZ_8M),
-};
-
-static struct map_info nexcoder_nor_map = {
- .bankwidth = 2,
-};
-
-static struct platform_device nexcoder_device_nor = {
- .name = "mtd-flash",
- .id = -1,
- .num_resources = ARRAY_SIZE(nexcoder_nor_resource),
- .resource = nexcoder_nor_resource,
- .dev =
- {
- .platform_data = &nexcoder_nor_map,
- }
-};
-
-/* Standard Nexcoder devices */
-
-static struct platform_device *nexcoder_devices[] __initdata = {
- &s3c_device_ohci,
- &s3c_device_lcd,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_iis,
- &s3c_device_rtc,
- &s3c_device_camif,
- &s3c_device_spi0,
- &s3c_device_spi1,
- &nexcoder_device_nor,
-};
-
-static void __init nexcoder_sensorboard_init(void)
-{
- /* Initialize SCCB bus */
- gpio_request_one(S3C2410_GPE(14), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPE(14)); /* IICSCL */
- gpio_request_one(S3C2410_GPE(15), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPE(15)); /* IICSDA */
-
- /* Power up the sensor board */
- gpio_request_one(S3C2410_GPF(1), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPF(1)); /* CAM_GPIO7 => nLDO_PWRDN */
- gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
- gpio_free(S3C2410_GPF(2)); /* CAM_GPIO6 => CAM_PWRDN */
-}
-
-static void __init nexcoder_map_io(void)
-{
- s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
- s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-
- nexcoder_sensorboard_init();
-}
-
-static void __init nexcoder_init_time(void)
-{
- s3c2440_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-static void __init nexcoder_init(void)
-{
- s3c_i2c0_set_platdata(NULL);
-
- /* Configure the I2S pins (GPE0...GPE4) in correct mode */
- s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
- S3C_GPIO_PULL_NONE);
-
- platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
-};
-
-MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
- /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
- .atag_offset = 0x100,
- .map_io = nexcoder_map_io,
- .init_machine = nexcoder_init,
- .init_irq = s3c2440_init_irq,
- .init_time = nexcoder_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-osiris-dvs.c b/arch/arm/mach-s3c/mach-osiris-dvs.c
deleted file mode 100644
index 2e283aedab65..000000000000
--- a/arch/arm/mach-s3c/mach-osiris-dvs.c
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2009 Simtec Electronics
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>
-//
-// Simtec Osiris Dynamic Voltage Scaling support.
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/cpufreq.h>
-#include <linux/gpio.h>
-
-#include <linux/mfd/tps65010.h>
-
-#include <linux/soc/samsung/s3c-cpu-freq.h>
-#include "gpio-samsung.h"
-
-#define OSIRIS_GPIO_DVS S3C2410_GPB(5)
-
-static bool dvs_en;
-
-static void osiris_dvs_tps_setdvs(bool on)
-{
- unsigned vregs1 = 0, vdcdc2 = 0;
-
- if (!on) {
- vdcdc2 = TPS_VCORE_DISCH | TPS_LP_COREOFF;
- vregs1 = TPS_LDO1_OFF; /* turn off in low-power mode */
- }
-
- dvs_en = on;
- vdcdc2 |= TPS_VCORE_1_3V | TPS_VCORE_LP_1_0V;
- vregs1 |= TPS_LDO2_ENABLE | TPS_LDO1_ENABLE;
-
- tps65010_config_vregs1(vregs1);
- tps65010_config_vdcdc2(vdcdc2);
-}
-
-static bool is_dvs(struct s3c_freq *f)
-{
- /* at the moment, we assume ARMCLK = HCLK => DVS */
- return f->armclk == f->hclk;
-}
-
-/* keep track of current state */
-static bool cur_dvs = false;
-
-static int osiris_dvs_notify(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- struct cpufreq_freqs *cf = data;
- struct s3c_cpufreq_freqs *freqs = to_s3c_cpufreq(cf);
- bool old_dvs = is_dvs(&freqs->old);
- bool new_dvs = is_dvs(&freqs->new);
- int ret = 0;
-
- if (!dvs_en)
- return 0;
-
- printk(KERN_DEBUG "%s: old %ld,%ld new %ld,%ld\n", __func__,
- freqs->old.armclk, freqs->old.hclk,
- freqs->new.armclk, freqs->new.hclk);
-
- switch (val) {
- case CPUFREQ_PRECHANGE:
- if ((old_dvs && !new_dvs) ||
- (cur_dvs && !new_dvs)) {
- pr_debug("%s: exiting dvs\n", __func__);
- cur_dvs = false;
- gpio_set_value(OSIRIS_GPIO_DVS, 1);
- }
- break;
- case CPUFREQ_POSTCHANGE:
- if ((!old_dvs && new_dvs) ||
- (!cur_dvs && new_dvs)) {
- pr_debug("entering dvs\n");
- cur_dvs = true;
- gpio_set_value(OSIRIS_GPIO_DVS, 0);
- }
- break;
- }
-
- return ret;
-}
-
-static struct notifier_block osiris_dvs_nb = {
- .notifier_call = osiris_dvs_notify,
-};
-
-static int osiris_dvs_probe(struct platform_device *pdev)
-{
- int ret;
-
- dev_info(&pdev->dev, "initialising\n");
-
- ret = gpio_request(OSIRIS_GPIO_DVS, "osiris-dvs");
- if (ret) {
- dev_err(&pdev->dev, "cannot claim gpio\n");
- goto err_nogpio;
- }
-
- /* start with dvs disabled */
- gpio_direction_output(OSIRIS_GPIO_DVS, 1);
-
- ret = cpufreq_register_notifier(&osiris_dvs_nb,
- CPUFREQ_TRANSITION_NOTIFIER);
- if (ret) {
- dev_err(&pdev->dev, "failed to register with cpufreq\n");
- goto err_nofreq;
- }
-
- osiris_dvs_tps_setdvs(true);
-
- return 0;
-
-err_nofreq:
- gpio_free(OSIRIS_GPIO_DVS);
-
-err_nogpio:
- return ret;
-}
-
-static int osiris_dvs_remove(struct platform_device *pdev)
-{
- dev_info(&pdev->dev, "exiting\n");
-
- /* disable any current dvs */
- gpio_set_value(OSIRIS_GPIO_DVS, 1);
- osiris_dvs_tps_setdvs(false);
-
- cpufreq_unregister_notifier(&osiris_dvs_nb,
- CPUFREQ_TRANSITION_NOTIFIER);
-
- gpio_free(OSIRIS_GPIO_DVS);
-
- return 0;
-}
-
-/* the CONFIG_PM block is so small, it isn't worth actually compiling it
- * out if the configuration isn't set. */
-
-static int osiris_dvs_suspend(struct device *dev)
-{
- gpio_set_value(OSIRIS_GPIO_DVS, 1);
- osiris_dvs_tps_setdvs(false);
- cur_dvs = false;
-
- return 0;
-}
-
-static int osiris_dvs_resume(struct device *dev)
-{
- osiris_dvs_tps_setdvs(true);
- return 0;
-}
-
-static const struct dev_pm_ops osiris_dvs_pm = {
- .suspend = osiris_dvs_suspend,
- .resume = osiris_dvs_resume,
-};
-
-static struct platform_driver osiris_dvs_driver = {
- .probe = osiris_dvs_probe,
- .remove = osiris_dvs_remove,
- .driver = {
- .name = "osiris-dvs",
- .pm = &osiris_dvs_pm,
- },
-};
-
-module_platform_driver(osiris_dvs_driver);
-
-MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
-MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:osiris-dvs");
diff --git a/arch/arm/mach-s3c/mach-osiris.c b/arch/arm/mach-s3c/mach-osiris.c
deleted file mode 100644
index 3aefb9d22340..000000000000
--- a/arch/arm/mach-s3c/mach-osiris.c
+++ /dev/null
@@ -1,409 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2005-2008 Simtec Electronics
-// http://armlinux.simtec.co.uk/
-// Ben Dooks <ben@simtec.co.uk>
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-
-#include <linux/mfd/tps65010.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/irq.h>
-
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-
-#include "cpu.h"
-#include <linux/soc/samsung/s3c-cpu-freq.h>
-#include "devs.h"
-#include "gpio-cfg.h"
-
-#include "regs-gpio.h"
-#include "gpio-samsung.h"
-
-#include "s3c24xx.h"
-#include "osiris.h"
-#include "regs-mem-s3c24xx.h"
-
-/* onboard perihperal map */
-
-static struct map_desc osiris_iodesc[] __initdata = {
- /* ISA IO areas (may be over-written later) */
-
- {
- .virtual = (u32)S3C24XX_VA_ISA_BYTE,
- .pfn = __phys_to_pfn(S3C2410_CS5),
- .length = SZ_16M,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)S3C24XX_VA_ISA_WORD,
- .pfn = __phys_to_pfn(S3C2410_CS5),
- .length = SZ_16M,
- .type = MT_DEVICE,
- },
-
- /* CPLD control registers */
-
- {
- .virtual = (u32)OSIRIS_VA_CTRL0,
- .pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)OSIRIS_VA_CTRL1,
- .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)OSIRIS_VA_CTRL2,
- .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual = (u32)OSIRIS_VA_IDREG,
- .pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
- .length = SZ_16K,
- .type = MT_DEVICE,
- },
-};
-
-#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
- }
-};
-
-/* NAND Flash on Osiris board */
-
-static int external_map[] = { 2 };
-static int chip0_map[] = { 0 };
-static int chip1_map[] = { 1 };
-
-static struct mtd_partition __initdata osiris_default_nand_part[] = {
- [0] = {
- .name = "Boot Agent",
- .size = SZ_16K,
- .offset = 0,
- },
- [1] = {
- .name = "/boot",
- .size = SZ_4M - SZ_16K,
- .offset = SZ_16K,
- },
- [2] = {
- .name = "user1",
- .offset = SZ_4M,
- .size = SZ_32M - SZ_4M,
- },
- [3] = {
- .name = "user2",
- .offset = SZ_32M,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
- [0] = {
- .name = "Boot Agent",
- .size = SZ_128K,
- .offset = 0,
- },
- [1] = {
- .name = "/boot",
- .size = SZ_4M - SZ_128K,
- .offset = SZ_128K,
- },
- [2] = {
- .name = "user1",
- .offset = SZ_4M,
- .size = SZ_32M - SZ_4M,
- },
- [3] = {
- .name = "user2",
- .offset = SZ_32M,
- .size = MTDPART_SIZ_FULL,
- }
-};
-
-/* the Osiris has 3 selectable slots for nand-flash, the two
- * on-board chip areas, as well as the external slot.
- *
- * Note, there is no current hot-plug support for the External
- * socket.
-*/
-
-static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
- [1] = {
- .name = "External",
- .nr_chips = 1,
- .nr_map = external_map,
- .options = NAND_SCAN_SILENT_NODEV,
- .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
- .partitions = osiris_default_nand_part,
- },
- [0] = {
- .name = "chip0",
- .nr_chips = 1,
- .nr_map = chip0_map,
- .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
- .partitions = osiris_default_nand_part,
- },
- [2] = {
- .name = "chip1",
- .nr_chips = 1,
- .nr_map = chip1_map,
- .options = NAND_SCAN_SILENT_NODEV,
- .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
- .partitions = osiris_default_nand_part,
- },
-};
-
-static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
-{
- unsigned int tmp;
-
- slot = set->nr_map[slot] & 3;
-
- pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
- slot, set, set->nr_map);
-
- tmp = __raw_readb(OSIRIS_VA_CTRL0);
- tmp &= ~OSIRIS_CTRL0_NANDSEL;
- tmp |= slot;
-
- pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
-
- __raw_writeb(tmp, OSIRIS_VA_CTRL0);
-}
-
-static struct s3c2410_platform_nand __initdata osiris_nand_info = {
- .tacls = 25,
- .twrph0 = 60,
- .twrph1 = 60,
- .nr_sets = ARRAY_SIZE(osiris_nand_sets),
- .sets = osiris_nand_sets,
- .select_chip = osiris_nand_select,
- .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
-};
-
-/* PCMCIA control and configuration */
-
-static struct resource osiris_pcmcia_resource[] = {
- [0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
- [1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
-};
-
-static struct platform_device osiris_pcmcia = {
- .name = "osiris-pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
- .resource = osiris_pcmcia_resource,
-};
-
-/* Osiris power management device */
-
-#ifdef CONFIG_PM
-static unsigned char pm_osiris_ctrl0;
-
-static int osiris_pm_suspend(void)
-{
- unsigned int tmp;
-
- pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
- tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
-
- /* ensure correct NAND slot is selected on resume */
- if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
- tmp |= 2;
-
- __raw_writeb(tmp, OSIRIS_VA_CTRL0);
-
- /* ensure that an nRESET is not generated on resume. */
- gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPA(21));
-
- return 0;
-}
-
-static void osiris_pm_resume(void)
-{
- if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
- __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
-
- __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
-
- s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
-}
-
-#else
-#define osiris_pm_suspend NULL
-#define osiris_pm_resume NULL
-#endif
-
-static struct syscore_ops osiris_pm_syscore_ops = {
- .suspend = osiris_pm_suspend,
- .resume = osiris_pm_resume,
-};
-
-/* Link for DVS driver to TPS65011 */
-
-static void osiris_tps_release(struct device *dev)
-{
- /* static device, do not need to release anything */
-}
-
-static struct platform_device osiris_tps_device = {
- .name = "osiris-dvs",
- .id = -1,
- .dev.release = osiris_tps_release,
-};
-
-static int osiris_tps_setup(struct i2c_client *client, void *context)
-{
- osiris_tps_device.dev.parent = &client->dev;
- return platform_device_register(&osiris_tps_device);
-}
-
-static int osiris_tps_remove(struct i2c_client *client, void *context)
-{
- platform_device_unregister(&osiris_tps_device);
- return 0;
-}
-
-static struct tps65010_board osiris_tps_board = {
- .base = -1, /* GPIO can go anywhere at the moment */
- .setup = osiris_tps_setup,
- .teardown = osiris_tps_remove,
-};
-
-/* I2C devices fitted. */
-
-static struct i2c_board_info osiris_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("tps65011", 0x48),
- .irq = IRQ_EINT20,
- .platform_data = &osiris_tps_board,
- },
-};
-
-/* Standard Osiris devices */
-
-static struct platform_device *osiris_devices[] __initdata = {
- &s3c2410_device_dclk,
- &s3c_device_i2c0,
- &s3c_device_wdt,
- &s3c_device_nand,
- &osiris_pcmcia,
-};
-
-static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
- .refresh = 7800, /* refresh period is 7.8usec */
- .auto_io = 1,
- .need_io = 1,
-};
-
-static void __init osiris_map_io(void)
-{
- unsigned long flags;
-
- s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
- s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-
- /* check for the newer revision boards with large page nand */
-
- if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
- printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
- __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
- osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
- osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
- } else {
- /* write-protect line to the NAND */
- gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
- gpio_free(S3C2410_GPA(0));
- }
-
- /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
-
- local_irq_save(flags);
- __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
- local_irq_restore(flags);
-}
-
-static void __init osiris_init_time(void)
-{
- s3c2440_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-static void __init osiris_init(void)
-{
- register_syscore_ops(&osiris_pm_syscore_ops);
-
- s3c_i2c0_set_platdata(NULL);
- s3c_nand_set_platdata(&osiris_nand_info);
-
- s3c_cpufreq_setboard(&osiris_cpufreq);
-
- i2c_register_board_info(0, osiris_i2c_devs,
- ARRAY_SIZE(osiris_i2c_devs));
-
- platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
-};
-
-MACHINE_START(OSIRIS, "Simtec-OSIRIS")
- /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
- .atag_offset = 0x100,
- .map_io = osiris_map_io,
- .init_irq = s3c2440_init_irq,
- .init_machine = osiris_init,
- .init_time = osiris_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-otom.c b/arch/arm/mach-s3c/mach-otom.c
deleted file mode 100644
index 460ee97766cd..000000000000
--- a/arch/arm/mach-s3c/mach-otom.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2004 Nex Vision
-// Guillaume GOURAT <guillaume.gourat@nexvision.fr>
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/platform_data/i2c-s3c2410.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include "gpio-samsung.h"
-#include "gpio-cfg.h"
-
-#include "cpu.h"
-#include "devs.h"
-
-#include "s3c24xx.h"
-#include "otom.h"
-
-static struct map_desc otom11_iodesc[] __initdata = {
- /* Device area */
- { (u32)OTOM_VA_CS8900A_BASE, OTOM_PA_CS8900A_BASE, SZ_16M, MT_DEVICE },
-};
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- /* port 2 is not actually used */
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- }
-};
-
-/* NOR Flash on NexVision OTOM board */
-
-static struct resource otom_nor_resource[] = {
- [0] = DEFINE_RES_MEM(S3C2410_CS0, SZ_4M),
-};
-
-static struct platform_device otom_device_nor = {
- .name = "mtd-flash",
- .id = -1,
- .num_resources = ARRAY_SIZE(otom_nor_resource),
- .resource = otom_nor_resource,
-};
-
-/* Standard OTOM devices */
-
-static struct platform_device *otom11_devices[] __initdata = {
- &s3c_device_ohci,
- &s3c_device_lcd,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_iis,
- &s3c_device_rtc,
- &otom_device_nor,
-};
-
-static void __init otom11_map_io(void)
-{
- s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
- s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
- s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
-}
-
-static void __init otom11_init_time(void)
-{
- s3c2410_init_clocks(12000000);
- s3c24xx_timer_init();
-}
-
-static void __init otom11_init(void)
-{
- s3c_i2c0_set_platdata(NULL);
-
- /* Configure the I2S pins (GPE0...GPE4) in correct mode */
- s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
- S3C_GPIO_PULL_NONE);
- platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
-}
-
-MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
- /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
- .atag_offset = 0x100,
- .map_io = otom11_map_io,
- .init_machine = otom11_init,
- .init_irq = s3c2410_init_irq,
- .init_time = otom11_init_time,
-MACHINE_END
diff --git a/arch/arm/mach-s3c/mach-qt2410.c b/arch/arm/mach-s3c/mach-qt2410.c
deleted file mode 100644
index f88b961798fd..000000000000
--- a/arch/arm/mach-s3c/mach-qt2410.c
+++ /dev/null
@@ -1,374 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright (C) 2006 by OpenMoko, Inc.
-// Author: Harald Welte <laforge@openmoko.org>
-// All rights reserved.
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand-ecc-sw-hamming.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <linux/platform_data/leds-s3c24xx.h>
-#include <linux/platform_data/fb-s3c2410.h>
-#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include "gpio-samsung.h"
-
-#include "gpio-cfg.h"
-#include "devs.h"
-#include "cpu.h"
-#include "pm.h"
-
-#include "s3c24xx.h"
-#include "common-smdk-s3c24xx.h"
-
-static struct map_desc qt2410_iodesc[] __initdata = {
- { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
-};
-
-#define UCON S3C2410_UCON_DEFAULT
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-
-static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
- [0] = {
- .hwport = 0,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [1] = {
- .hwport = 1,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- },
- [2] = {
- .hwport = 2,
- .flags = 0,
- .ucon = UCON,
- .ulcon = ULCON,
- .ufcon = UFCON,
- }
-};
-
-/* LCD driver info */
-
-static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
- {
- /* Configuration for 640x480 SHARP LQ080V3DG01 */
- .lcdcon5 = S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_PWREN |
- S3C2410_LCDCON5_HWSWP,
-
- .type = S3C2410_LCDCON1_TFT,
- .width = 640,
- .height = 480,
-
- .pixclock = 40000, /* HCLK/4 */
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .left_margin = 44,
- .right_margin = 116,
- .hsync_len = 96,
- .upper_margin = 19,
- .lower_margin = 11,
- .vsync_len = 15,
- },
- {
- /* Configuration for 480x640 toppoly TD028TTEC1 */
- .lcdcon5 = S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_PWREN |
- S3C2410_LCDCON5_HWSWP,
-
- .type = S3C2410_LCDCON1_TFT,
- .width = 480,
- .height = 640,
- .pixclock = 40000, /* HCLK/4 */
- .xres = 480,
- .yres = 640,
- .bpp = 16,
- .left_margin = 8,
- .right_margin = 24,
- .hsync_len = 8,
- .upper_margin = 2,
- .lower_margin = 4,
- .vsync_len = 2,
- },
- {
- /* Config for 240x320 LCD */
- .lcdcon5 = S3C2410_LCDCON5_FRM565 |
- S3C2410_LCDCON5_INVVLINE |
- S3C2410_LCDCON5_INVVFRAME |
- S3C2410_LCDCON5_PWREN |
- S3C2410_LCDCON5_HWSWP,
-
- .type = S3C2410_LCDCON1_TFT,
- .width = 240,
- .height = 320,
- .pixclock = 100000, /* HCLK/10 */
- .xres = 240,
- .yres = 320,
- .bpp = 16,
- .left_margin = 13,
- .right_margin = 8,
- .hsync_len = 4,
- .upper_margin = 2,
- .lower_margin = 7,
- .vsync_len = 4,
- },
-};
-
-
-static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
- .displays = qt2410_lcd_cfg,
- .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
- .default_display = 0,
-
- .lpcsel = ((0xCE6) & ~7) | 1<<4,
-};
-
-/* CS8900 */
-
-static struct resource qt2410_cs89x0_resources[] = {
- [0] = DEFINE_RES_MEM(0x19000000, 17),
- [1] = DEFINE_RES_IRQ(IRQ_EINT9),
-};
-
-static struct platform_device qt2410_cs89x0 = {
- .name = "cirrus-cs89x0",
- .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
- .resource = qt2410_cs89x0_resources,
-};
-
-/* LED */
-
-static struct gpiod_lookup_table qt2410_led_gpio_table = {
- .dev_id = "s3c24xx_led.0",
- .table = {
- GPIO_LOOKUP("GPB", 0, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
- { },
- },
-};
-
-static struct s3c24xx_led_platdata qt2410_pdata_led = {
- .name = "led",
- .def_trigger = "timer",
-};
-
-static struct platform_device qt2410_led = {
- .name = "s3c24xx_led",
- .id = 0,
- .dev = {
- .platform_data = &qt2410_pdata_led,
- },
-};
-
-/* SPI */
-
-static struct spi_gpio_platform_data spi_gpio_cfg = {
- .num_chipselect = 1,
-};
-
-static struct platform_device qt2410_spi = {
- .name = "spi_gpio",
- .id = 1,
- .dev.platform_data = &spi_gpio_cfg,
-};
-
-static struct gpiod_lookup_table qt2410_spi_gpiod_table = {
- .dev_id = "spi_gpio",
- .table = {
- GPIO_LOOKUP("GPIOG", 7,
- "sck", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOG", 6,
- "mosi", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOG", 5,
- "miso", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("GPIOB", 5,
- "cs", GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-static struct gpiod_lookup_table qt2410_mmc_gpiod_table = {
- .dev_id = "s3c2410-sdi",
- .table = {
- /* bus pins */
- GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/* Board devices */
-
-static struct platform_device *qt2410_devices[] __initdata = {
- &s3c_device_ohci,
- &s3c_device_lcd,
- &s3c_device_wdt,
- &s3c_device_i2c0,
- &s3c_device_iis,
- &s3c_device_sdi,
- &s3c_device_usbgadget,
- &qt2410_spi,
- &qt2410_cs89x0,
- &qt2410_led,
-};
-
-static struct mtd_partition __initdata qt2410_nand_part[] = {
- [0] = {
- .name = "U-Boot",
- .size = 0x30000,
- .offset = 0,
- },
- [1] = {
- .name = "U-Boot environment",
- .offset = 0x30000,
- .size = 0x4000,
- },
- [2] = {
- .name = "kernel",
- .offset = 0x34000,
- .size = SZ_2M,
- },
- [3] = {
- .name = "initrd",