diff options
| author | Caesar Wang <wxt@rock-chips.com> | 2016-08-25 06:31:32 +0800 |
|---|---|---|
| committer | Caesar Wang <wxt@rock-chips.com> | 2016-08-25 12:29:27 +0800 |
| commit | 9d5aee2b1fdcb0d7df70b0a13622b09780fbc9dc (patch) | |
| tree | fc13fb1525cde36e926fea9fea4274e50a195e3a | |
| parent | 0786d68853700687a7221240945e0bff51ef75db (diff) | |
rockchip: on rk3399 enable Schmitt trigger on 32 kHz clock
If we don't enable the Schmitt trigger on the 32 kHz clock then systems
won't always resume from suspend properly. Presumably anything else in
the system that relies on the 32 kHz clock also will have problems
without the Schmitt trigger enabled.
Enable it always since having the 32 kHz clock on GPIO0_A0 isn't
exactly an optional feature, so all boards using rk3399 will need this.
Change-Id: Idc18c6cd1adc5be5f60efd9cb805d83d5cd40129
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.c | 6 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.h | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 9fc796cc..00df0858 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -1078,6 +1078,12 @@ void plat_rockchip_pmu_init(void) CPU_BOOT_ADDR_WMASK); mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); + /* + * Enable Schmitt trigger for better 32 kHz input signal, which is + * important for suspend/resume reliability among other things. + */ + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); + init_pmu_counts(); nonboot_cpus_off(); diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h index c821efc0..65fe7dbe 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.h +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h @@ -819,6 +819,7 @@ enum pmu_core_pwr_st { #define AP_PWROFF 0x0a +#define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0) #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) #define TSADC_INT_PIN 38 @@ -876,6 +877,7 @@ enum pmu_core_pwr_st { #define GRF_SOC_CON4 0x0e210 #define GRF_GPIO4C_IOMUX 0x0e028 +#define PMUGRF_GPIO0A_SMT 0x0120 #define PMUGRF_SOC_CON0 0x0180 #define CCI_FORCE_WAKEUP WMSK_BIT(8) |