diff options
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.c | 6 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.h | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 9fc796cc..00df0858 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -1078,6 +1078,12 @@ void plat_rockchip_pmu_init(void) CPU_BOOT_ADDR_WMASK); mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); + /* + * Enable Schmitt trigger for better 32 kHz input signal, which is + * important for suspend/resume reliability among other things. + */ + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); + init_pmu_counts(); nonboot_cpus_off(); diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h index c821efc0..65fe7dbe 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.h +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h @@ -819,6 +819,7 @@ enum pmu_core_pwr_st { #define AP_PWROFF 0x0a +#define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0) #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) #define TSADC_INT_PIN 38 @@ -876,6 +877,7 @@ enum pmu_core_pwr_st { #define GRF_SOC_CON4 0x0e210 #define GRF_GPIO4C_IOMUX 0x0e028 +#define PMUGRF_GPIO0A_SMT 0x0120 #define PMUGRF_SOC_CON0 0x0180 #define CCI_FORCE_WAKEUP WMSK_BIT(8) |