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| author | Soby Mathew <soby.mathew@arm.com> | 2014-09-22 14:13:34 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2014-10-29 17:39:59 +0000 |
| commit | 5541bb3f61ae97b49203939f940931455b2f3037 (patch) | |
| tree | 13a011a9857ba598ccb96563b4b33919bb491b96 /docs/firmware-design.md | |
| parent | b1a9631d8110a2bcd458ec5809b50d5263a200ef (diff) | |
Optimize Cortex-A57 cluster power down sequence on Juno
This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.
This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.
Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
Diffstat (limited to 'docs/firmware-design.md')
| -rw-r--r-- | docs/firmware-design.md | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index fde61da7..bc075da3 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -982,9 +982,10 @@ Please note that only 2. is mandated by the TRM. The CPU specific operations framework scales to accommodate a large number of different CPUs during power down and reset handling. The platform can specify +any CPU optimization it wants to enable for each CPU. It can also specify the CPU errata workarounds to be applied for each CPU type during reset handling by defining CPU errata compile time macros. Details on these macros -can be found in the [cpu-errata-workarounds.md][ERRW] file. +can be found in the [cpu-specific-build-macros.md][CPUBM] file. The CPU specific operations framework depends on the `cpu_ops` structure which needs to be exported for each type of CPU in the platform. It is defined in @@ -1485,4 +1486,4 @@ _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ [User Guide]: ./user-guide.md [Porting Guide]: ./porting-guide.md [INTRG]: ./interrupt-framework-design.md -[ERRW]: ./cpu-errata-workarounds.md +[CPUBM]: ./cpu-specific-build-macros.md.md |