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author | danh-arm <dan.handley@arm.com> | 2015-12-17 17:37:15 +0000 |
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committer | danh-arm <dan.handley@arm.com> | 2015-12-17 17:37:15 +0000 |
commit | 6f0be12536a905ceca024979cecf81942ee8f6cc (patch) | |
tree | 465788cead6ac0b52e9ae9b3ece4d50b88f18d11 /docs/firmware-design.md | |
parent | 6ab79de4b3a3cc36546d1911d0f0e47c9d19d68b (diff) | |
parent | 84a5d6d660c7a194e9829e6c46d6eb80ecab84f5 (diff) |
Merge pull request #472 from danh-arm/dh/fwu-docs
FWU: Add documentation for Firmware Update feature
Diffstat (limited to 'docs/firmware-design.md')
-rw-r--r-- | docs/firmware-design.md | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index fb94f564..c32f0bd0 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -194,9 +194,21 @@ the CCI slave interface corresponding to the cluster that includes the primary CPU. BL1 also initializes a UART (PL011 console), which enables access to the `printf` family of functions in BL1. +#### Firmware Update detection and execution + +After performing platform setup, BL1 common code calls +`bl1_plat_get_next_image_id()` to determine if [Firmware Update] is required or +to proceed with the normal boot process. If the platform code returns +`BL2_IMAGE_ID` then the normal boot sequence is executed as described in the +next section, else BL1 assumes that [Firmware Update] is required and execution +passes to the first image in the [Firmware Update] process. In either case, BL1 +retrieves a descriptor of the next image by calling `bl1_plat_get_image_desc()`. +The image descriptor contains an `entry_point_info_t` structure, which BL1 +uses to initialize the execution state of the next image. + #### BL2 image load and execution -BL1 execution continues as follows: +In the normal boot flow, BL1 execution continues as follows: 1. BL1 determines the amount of free trusted SRAM memory available by calculating the extent of its own data section, which also resides in @@ -1728,3 +1740,4 @@ _Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ [Reset Design]: ./reset-design.md [INTRG]: ./interrupt-framework-design.md [CPUBM]: ./cpu-specific-build-macros.md.md +[Firmware Update]: ./firmware-update.md |