diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2014-08-14 16:19:29 +0100 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-08-20 19:14:31 +0100 |
| commit | d9bdaf2d989f7d594cd17fdd4c6e5a0665610266 (patch) | |
| tree | 7b789dbc50f9d156774ea3bdb022306fc54347cb /include/lib | |
| parent | d3f70af6e09d669da9c7d7890b7af5a0cdc4b3a5 (diff) | |
Add support for selected Cortex-A57 errata workarounds
This patch adds workarounds for selected errata which affect the Cortex-A57 r0p0
part. Each workaround has a build time flag which should be used by the platform
port to enable or disable the corresponding workaround. The workarounds are
disabled by default. An assertion is raised if the platform enables a workaround
which does not match the CPU revision at runtime.
Change-Id: I9ae96b01c6ff733d04dc733bd4e67dbf77b29fb0
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch64/arch.h | 2 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 97242ccb..b2aac2fb 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -37,6 +37,8 @@ ******************************************************************************/ #define MIDR_IMPL_MASK 0xff #define MIDR_IMPL_SHIFT 0x18 +#define MIDR_VAR_SHIFT 20 +#define MIDR_REV_SHIFT 0 #define MIDR_PN_MASK 0xfff #define MIDR_PN_SHIFT 0x4 diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index dc0e0f4e..9cf8780d 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -44,4 +44,12 @@ #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) + #endif /* __CORTEX_A57_H__ */ |