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| author | Tao Zhang <quic_taozha@quicinc.com> | 2025-02-25 22:40:07 -0800 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-02-26 11:25:10 +0000 |
| commit | 07f7c21745db0afa71a813e594f0983b8bd0f031 (patch) | |
| tree | 0b7318976535fffb83fac981027f81a6f7eefa83 /tools/perf/scripts/python/stackcollapse.py | |
| parent | ee39dbe9395bd91435aed0194abc3c7c83dba146 (diff) | |
coresight-tpdm: Add support to select lane
TPDM MCMB subunits supports up to 8 lanes CMB. For MCMB
configurations, the field "XTRIG_LNSEL" in CMB_CR register selects
which lane participates in the output pattern mach cross trigger
mechanism governed by the M_CMB_DXPR and M_CMB_XPMR regisers.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250226064008.2531037-3-quic_jinlmao@quicinc.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions