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| author | Tao Zhang <quic_taozha@quicinc.com> | 2025-02-25 22:40:08 -0800 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-02-26 11:25:10 +0000 |
| commit | 0c0b6c05e208abc60ae0f1aab0660ab93b25cfc7 (patch) | |
| tree | 4ce46225c43eaef3af718acc204df223a2e1321f /tools/perf/scripts/python/stackcollapse.py | |
| parent | 07f7c21745db0afa71a813e594f0983b8bd0f031 (diff) | |
coresight-tpdm: Add support to enable the lane for MCMB TPDM
Add the sysfs file to set/get the enablement of the lane. For MCMB
configurations, the field "E_LN" in CMB_CR register is the
individual lane enables. MCMB lane N is enabled for trace
generation when M_CMB_CR.E=1 and M_CMB_CR.E_LN[N]=1. For lanes
that are not implemented on a given MCMB configuration, the
corresponding bits of this field read as 0 and ignore writes.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250226064008.2531037-4-quic_jinlmao@quicinc.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions