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author | Linus Torvalds <torvalds@linux-foundation.org> | 2025-05-31 08:14:37 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-05-31 08:14:37 -0700 |
commit | 31848987f177a6c0944fd0254a55ffd7c52a8c50 (patch) | |
tree | cc2b01451df5f6ed42d7a77f04b76c23f05f7c11 /Documentation/DocBook/procfs_example.c | |
parent | ec71f661a572a770d7c861cd52a50cbbb0e1a8d1 (diff) | |
parent | 9bba618694cc905b898661c18e3e40955573ef5e (diff) |
Merge tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull sophgo SoC devicetree updates from Arnd Bergmann:
"The Sophgo SG2044 SoC is their second generation server chip with 64
cores, following the SG2042.
In addition, there are minor updates for the cv180x SoCs"
* tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
dt-bindings: riscv: sophgo: Add SG2044 compatible string
dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
riscv: dts: sophgo: Move riscv cpu definition to a separate file
riscv: dts: sophgo: Move all soc specific device into soc dtsi file
riscv: sophgo: dts: Add spi controller for SG2042
riscv: dts: sophgo: sg2042: add pinctrl support
Diffstat (limited to 'Documentation/DocBook/procfs_example.c')
0 files changed, 0 insertions, 0 deletions