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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-08-20 09:16:19 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-08-20 09:16:19 +0200 |
| commit | 845d5c1a3218466e3a2bb4924ac2c58dc879996b (patch) | |
| tree | e6de5ee5359b3f164f806047bd094354a0fd9d81 /net/unix/sysctl_net_unix.c | |
| parent | 059db30b32e968fdbf6e416411fb78d481ff94bd (diff) | |
| parent | 5293e8f2a854344ef9aba2391b44c7a437889ebb (diff) | |
Merge tag 'renesas-r9a09g077-dt-binding-defs-tag3' into renesas-clk-for-v6.18
Renesas RZ/T2H and RZ/N2H USB_CLK and Pin Control DT Binding Definitions
USB_CLK Clock and Pin Control DT binding definitions for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT
source files.
Diffstat (limited to 'net/unix/sysctl_net_unix.c')
0 files changed, 0 insertions, 0 deletions