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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2023-03-20 10:19:35 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-03-20 12:34:25 -0500 |
| commit | 438b8dc949bf45979c32553e96086ff1c6e2504e (patch) | |
| tree | 148e605ae682298a76f58c71395fb77aceae0bd4 /scripts/generate_rust_analyzer.py | |
| parent | 6974371cab1c488a53960945cb139b20ebb5f16b (diff) | |
arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB
Per AM62Ax SoC datasheet[0] L2 cache is 512KB.
[0] https://www.ti.com/lit/gpn/am62a7 Page 1.
Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions