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authorVille Syrjälä <ville.syrjala@linux.intel.com>2025-06-17 20:07:56 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2025-06-23 17:50:07 +0300
commit7184a994cf7629dfb0440cdf05dc9407964d9eb5 (patch)
tree5d59bd5095856251eef7638718d65c1bfd70921a /scripts/generate_rust_analyzer.py
parent761748679e80cc429f035bcb64662becf0ecf4f6 (diff)
drm/i915/dmc: Reload pipe DMC MMIO registers for pipe C/D on various platforms
On ADL/MTL pipe DMC MMIO state evidently lives in PG0. The main DMC saves/restores it for pipes A/B, but for pipes C/D we have to do it in the driver. On PTL the situation is mostly the same, except the main DMC firmware doesn't seem to have the PG0 save/restore code anymore, and instead the hardware (or maybe Punit?) seems to take care of this job now. Pipes C/D still need a manual restore by the driver. On LNL I've been unable to lose any pipe DMC state, despite the main DMC firmware still implementing the PG0 save/restore for pipes A/B. Not sure what's going on here. On DG2 I've also not been able to lose the pipe DMC state. DG2 doesn't support DC6, so that might explain part of it. But even DC9 doesn't make a difference here. Perhaps PG0 is just always on for DG2? BMG I've not tested at all. The main DMC firmware does appaer to implement the PG0 pipe A/B save/restore logic. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-7-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
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