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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-17 20:07:52 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-23 17:50:07 +0300 |
| commit | eddc8a0572b951af5a9da464d763bf2f81bad1c1 (patch) | |
| tree | d9cbcd51049c060ab7ac74ddc8f44c3ad94ff26b /scripts/generate_rust_analyzer.py | |
| parent | 42a7bf8aa730606ae89b60c1058c50866f240e5d (diff) | |
drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS
The MTL+ pipe DMC clock gating bits can be parametrized.
Make it so.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-3-ville.syrjala@linux.intel.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions