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| author | Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> | 2025-03-28 15:58:31 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2025-04-19 19:42:38 +0530 |
| commit | f9eb654fb194e7c404d4984481a18edb9b1c1d7c (patch) | |
| tree | a2f5ffc52d4e4bef818b128a7097311d05b7c2bc /scripts/lib/kdoc/kdoc_re.py | |
| parent | 57a4591df70900252265ecfd6eeba95ce2021504 (diff) | |
PCI: dwc: Update pci->num_lanes to maximum supported link width
If the num-lanes property is not present in the devicetree, update
pci->num_lanes with the hardware supported maximum link width using
the newly introduced dw_pcie_link_get_max_link_width() API.
The API is used to get the Maximum Link Width (MLW) of the controller.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: reworded commit message a bit]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250328-preset_v6-v9-3-22cfa0490518@oss.qualcomm.com
Diffstat (limited to 'scripts/lib/kdoc/kdoc_re.py')
0 files changed, 0 insertions, 0 deletions