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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-07 15:10:02 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:38:01 +0200 |
| commit | ceb22d9312b3dcb3568da7ab0d62aea8b8bf0a15 (patch) | |
| tree | 8f1e4cc66c096f9be2faf326c404a3142c78fab0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | f5684bde0375f4feb2a9ed1c146df29437652e70 (diff) | |
clk: renesas: r8a779g0: Add SCIF clocks
Add the module clocks used by the Serial Communication Interfaces with
FIFO (SCIF) on the Renesas R-Car V4H (R8A779G0) SoC.
Based on a larger patch in the BSP by Kazuya Mizuguchi.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/a6ab466cfdac377106494c00b811a60151cb1825.1665147497.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions