diff options
| author | Richard Fitzgerald <rf@opensource.cirrus.com> | 2021-10-15 14:36:14 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-10-15 16:14:18 +0100 |
| commit | 3c211cb7db2905221f9f006aa66b8af17bfcd480 (patch) | |
| tree | 6aaa805d8e85bde66db4ba40e381a1b0ef68eb97 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 2a031a99428bafba089437e9044b8fd5dc6e7551 (diff) | |
ASoC: cs42l42: Use PLL for SCLK > 12.288MHz
It isn't possible to switch MCLK between 12MHz and 24MHz rate groups
on-the-fly - this can only be done when cs42l42 is powered-down.
All "normal" SCLK rates use an MCLK in the 12MHz group, so change the
configs for SCLK > 12.288 MHz to use the PLL to generate an MCLK in
the 12MHz group.
As this means MCLK_DIV is always 0 it can be removed from the pll
configuration setup.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211015133619.4698-12-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions